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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV323; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV644 5define void @add_v16i8(ptr %x, ptr %y) {6; CHECK-LABEL: add_v16i8:7; CHECK:       # %bb.0:8; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma9; CHECK-NEXT:    vle8.v v8, (a0)10; CHECK-NEXT:    vle8.v v9, (a1)11; CHECK-NEXT:    vadd.vv v8, v8, v912; CHECK-NEXT:    vse8.v v8, (a0)13; CHECK-NEXT:    ret14  %a = load <16 x i8>, ptr %x15  %b = load <16 x i8>, ptr %y16  %c = add <16 x i8> %a, %b17  store <16 x i8> %c, ptr %x18  ret void19}20 21define void @add_v8i16(ptr %x, ptr %y) {22; CHECK-LABEL: add_v8i16:23; CHECK:       # %bb.0:24; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma25; CHECK-NEXT:    vle16.v v8, (a0)26; CHECK-NEXT:    vle16.v v9, (a1)27; CHECK-NEXT:    vadd.vv v8, v8, v928; CHECK-NEXT:    vse16.v v8, (a0)29; CHECK-NEXT:    ret30  %a = load <8 x i16>, ptr %x31  %b = load <8 x i16>, ptr %y32  %c = add <8 x i16> %a, %b33  store <8 x i16> %c, ptr %x34  ret void35}36 37define void @add_v6i16(ptr %x, ptr %y) {38; CHECK-LABEL: add_v6i16:39; CHECK:       # %bb.0:40; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma41; CHECK-NEXT:    vle16.v v8, (a0)42; CHECK-NEXT:    vle16.v v9, (a1)43; CHECK-NEXT:    vadd.vv v8, v8, v944; CHECK-NEXT:    vse16.v v8, (a0)45; CHECK-NEXT:    ret46  %a = load <6 x i16>, ptr %x47  %b = load <6 x i16>, ptr %y48  %c = add <6 x i16> %a, %b49  store <6 x i16> %c, ptr %x50  ret void51}52 53define void @add_v4i32(ptr %x, ptr %y) {54; CHECK-LABEL: add_v4i32:55; CHECK:       # %bb.0:56; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma57; CHECK-NEXT:    vle32.v v8, (a0)58; CHECK-NEXT:    vle32.v v9, (a1)59; CHECK-NEXT:    vadd.vv v8, v8, v960; CHECK-NEXT:    vse32.v v8, (a0)61; CHECK-NEXT:    ret62  %a = load <4 x i32>, ptr %x63  %b = load <4 x i32>, ptr %y64  %c = add <4 x i32> %a, %b65  store <4 x i32> %c, ptr %x66  ret void67}68 69define void @add_v2i64(ptr %x, ptr %y) {70; CHECK-LABEL: add_v2i64:71; CHECK:       # %bb.0:72; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma73; CHECK-NEXT:    vle64.v v8, (a0)74; CHECK-NEXT:    vle64.v v9, (a1)75; CHECK-NEXT:    vadd.vv v8, v8, v976; CHECK-NEXT:    vse64.v v8, (a0)77; CHECK-NEXT:    ret78  %a = load <2 x i64>, ptr %x79  %b = load <2 x i64>, ptr %y80  %c = add <2 x i64> %a, %b81  store <2 x i64> %c, ptr %x82  ret void83}84 85define void @sub_v16i8(ptr %x, ptr %y) {86; CHECK-LABEL: sub_v16i8:87; CHECK:       # %bb.0:88; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma89; CHECK-NEXT:    vle8.v v8, (a0)90; CHECK-NEXT:    vle8.v v9, (a1)91; CHECK-NEXT:    vsub.vv v8, v8, v992; CHECK-NEXT:    vse8.v v8, (a0)93; CHECK-NEXT:    ret94  %a = load <16 x i8>, ptr %x95  %b = load <16 x i8>, ptr %y96  %c = sub <16 x i8> %a, %b97  store <16 x i8> %c, ptr %x98  ret void99}100 101define void @sub_v8i16(ptr %x, ptr %y) {102; CHECK-LABEL: sub_v8i16:103; CHECK:       # %bb.0:104; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma105; CHECK-NEXT:    vle16.v v8, (a0)106; CHECK-NEXT:    vle16.v v9, (a1)107; CHECK-NEXT:    vsub.vv v8, v8, v9108; CHECK-NEXT:    vse16.v v8, (a0)109; CHECK-NEXT:    ret110  %a = load <8 x i16>, ptr %x111  %b = load <8 x i16>, ptr %y112  %c = sub <8 x i16> %a, %b113  store <8 x i16> %c, ptr %x114  ret void115}116 117define void @sub_v6i16(ptr %x, ptr %y) {118; CHECK-LABEL: sub_v6i16:119; CHECK:       # %bb.0:120; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma121; CHECK-NEXT:    vle16.v v8, (a0)122; CHECK-NEXT:    vle16.v v9, (a1)123; CHECK-NEXT:    vsub.vv v8, v8, v9124; CHECK-NEXT:    vse16.v v8, (a0)125; CHECK-NEXT:    ret126  %a = load <6 x i16>, ptr %x127  %b = load <6 x i16>, ptr %y128  %c = sub <6 x i16> %a, %b129  store <6 x i16> %c, ptr %x130  ret void131}132 133define void @sub_v4i32(ptr %x, ptr %y) {134; CHECK-LABEL: sub_v4i32:135; CHECK:       # %bb.0:136; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma137; CHECK-NEXT:    vle32.v v8, (a0)138; CHECK-NEXT:    vle32.v v9, (a1)139; CHECK-NEXT:    vsub.vv v8, v8, v9140; CHECK-NEXT:    vse32.v v8, (a0)141; CHECK-NEXT:    ret142  %a = load <4 x i32>, ptr %x143  %b = load <4 x i32>, ptr %y144  %c = sub <4 x i32> %a, %b145  store <4 x i32> %c, ptr %x146  ret void147}148 149define void @sub_v2i64(ptr %x, ptr %y) {150; CHECK-LABEL: sub_v2i64:151; CHECK:       # %bb.0:152; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma153; CHECK-NEXT:    vle64.v v8, (a0)154; CHECK-NEXT:    vle64.v v9, (a1)155; CHECK-NEXT:    vsub.vv v8, v8, v9156; CHECK-NEXT:    vse64.v v8, (a0)157; CHECK-NEXT:    ret158  %a = load <2 x i64>, ptr %x159  %b = load <2 x i64>, ptr %y160  %c = sub <2 x i64> %a, %b161  store <2 x i64> %c, ptr %x162  ret void163}164 165define void @mul_v16i8(ptr %x, ptr %y) {166; CHECK-LABEL: mul_v16i8:167; CHECK:       # %bb.0:168; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma169; CHECK-NEXT:    vle8.v v8, (a0)170; CHECK-NEXT:    vle8.v v9, (a1)171; CHECK-NEXT:    vmul.vv v8, v8, v9172; CHECK-NEXT:    vse8.v v8, (a0)173; CHECK-NEXT:    ret174  %a = load <16 x i8>, ptr %x175  %b = load <16 x i8>, ptr %y176  %c = mul <16 x i8> %a, %b177  store <16 x i8> %c, ptr %x178  ret void179}180 181define void @mul_v8i16(ptr %x, ptr %y) {182; CHECK-LABEL: mul_v8i16:183; CHECK:       # %bb.0:184; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma185; CHECK-NEXT:    vle16.v v8, (a0)186; CHECK-NEXT:    vle16.v v9, (a1)187; CHECK-NEXT:    vmul.vv v8, v8, v9188; CHECK-NEXT:    vse16.v v8, (a0)189; CHECK-NEXT:    ret190  %a = load <8 x i16>, ptr %x191  %b = load <8 x i16>, ptr %y192  %c = mul <8 x i16> %a, %b193  store <8 x i16> %c, ptr %x194  ret void195}196 197define void @mul_v6i16(ptr %x, ptr %y) {198; CHECK-LABEL: mul_v6i16:199; CHECK:       # %bb.0:200; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma201; CHECK-NEXT:    vle16.v v8, (a0)202; CHECK-NEXT:    vle16.v v9, (a1)203; CHECK-NEXT:    vmul.vv v8, v8, v9204; CHECK-NEXT:    vse16.v v8, (a0)205; CHECK-NEXT:    ret206  %a = load <6 x i16>, ptr %x207  %b = load <6 x i16>, ptr %y208  %c = mul <6 x i16> %a, %b209  store <6 x i16> %c, ptr %x210  ret void211}212 213define void @mul_v4i32(ptr %x, ptr %y) {214; CHECK-LABEL: mul_v4i32:215; CHECK:       # %bb.0:216; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma217; CHECK-NEXT:    vle32.v v8, (a0)218; CHECK-NEXT:    vle32.v v9, (a1)219; CHECK-NEXT:    vmul.vv v8, v8, v9220; CHECK-NEXT:    vse32.v v8, (a0)221; CHECK-NEXT:    ret222  %a = load <4 x i32>, ptr %x223  %b = load <4 x i32>, ptr %y224  %c = mul <4 x i32> %a, %b225  store <4 x i32> %c, ptr %x226  ret void227}228 229define void @mul_v2i64(ptr %x, ptr %y) {230; CHECK-LABEL: mul_v2i64:231; CHECK:       # %bb.0:232; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma233; CHECK-NEXT:    vle64.v v8, (a0)234; CHECK-NEXT:    vle64.v v9, (a1)235; CHECK-NEXT:    vmul.vv v8, v8, v9236; CHECK-NEXT:    vse64.v v8, (a0)237; CHECK-NEXT:    ret238  %a = load <2 x i64>, ptr %x239  %b = load <2 x i64>, ptr %y240  %c = mul <2 x i64> %a, %b241  store <2 x i64> %c, ptr %x242  ret void243}244 245define void @and_v16i8(ptr %x, ptr %y) {246; CHECK-LABEL: and_v16i8:247; CHECK:       # %bb.0:248; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma249; CHECK-NEXT:    vle8.v v8, (a0)250; CHECK-NEXT:    vle8.v v9, (a1)251; CHECK-NEXT:    vand.vv v8, v8, v9252; CHECK-NEXT:    vse8.v v8, (a0)253; CHECK-NEXT:    ret254  %a = load <16 x i8>, ptr %x255  %b = load <16 x i8>, ptr %y256  %c = and <16 x i8> %a, %b257  store <16 x i8> %c, ptr %x258  ret void259}260 261define void @and_v8i16(ptr %x, ptr %y) {262; CHECK-LABEL: and_v8i16:263; CHECK:       # %bb.0:264; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma265; CHECK-NEXT:    vle16.v v8, (a0)266; CHECK-NEXT:    vle16.v v9, (a1)267; CHECK-NEXT:    vand.vv v8, v8, v9268; CHECK-NEXT:    vse16.v v8, (a0)269; CHECK-NEXT:    ret270  %a = load <8 x i16>, ptr %x271  %b = load <8 x i16>, ptr %y272  %c = and <8 x i16> %a, %b273  store <8 x i16> %c, ptr %x274  ret void275}276 277define void @and_v6i16(ptr %x, ptr %y) {278; CHECK-LABEL: and_v6i16:279; CHECK:       # %bb.0:280; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma281; CHECK-NEXT:    vle16.v v8, (a0)282; CHECK-NEXT:    vle16.v v9, (a1)283; CHECK-NEXT:    vand.vv v8, v8, v9284; CHECK-NEXT:    vse16.v v8, (a0)285; CHECK-NEXT:    ret286  %a = load <6 x i16>, ptr %x287  %b = load <6 x i16>, ptr %y288  %c = and <6 x i16> %a, %b289  store <6 x i16> %c, ptr %x290  ret void291}292 293define void @and_v4i32(ptr %x, ptr %y) {294; CHECK-LABEL: and_v4i32:295; CHECK:       # %bb.0:296; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma297; CHECK-NEXT:    vle32.v v8, (a0)298; CHECK-NEXT:    vle32.v v9, (a1)299; CHECK-NEXT:    vand.vv v8, v8, v9300; CHECK-NEXT:    vse32.v v8, (a0)301; CHECK-NEXT:    ret302  %a = load <4 x i32>, ptr %x303  %b = load <4 x i32>, ptr %y304  %c = and <4 x i32> %a, %b305  store <4 x i32> %c, ptr %x306  ret void307}308 309define void @and_v2i64(ptr %x, ptr %y) {310; CHECK-LABEL: and_v2i64:311; CHECK:       # %bb.0:312; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma313; CHECK-NEXT:    vle64.v v8, (a0)314; CHECK-NEXT:    vle64.v v9, (a1)315; CHECK-NEXT:    vand.vv v8, v8, v9316; CHECK-NEXT:    vse64.v v8, (a0)317; CHECK-NEXT:    ret318  %a = load <2 x i64>, ptr %x319  %b = load <2 x i64>, ptr %y320  %c = and <2 x i64> %a, %b321  store <2 x i64> %c, ptr %x322  ret void323}324 325define void @or_v16i8(ptr %x, ptr %y) {326; CHECK-LABEL: or_v16i8:327; CHECK:       # %bb.0:328; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma329; CHECK-NEXT:    vle8.v v8, (a0)330; CHECK-NEXT:    vle8.v v9, (a1)331; CHECK-NEXT:    vor.vv v8, v8, v9332; CHECK-NEXT:    vse8.v v8, (a0)333; CHECK-NEXT:    ret334  %a = load <16 x i8>, ptr %x335  %b = load <16 x i8>, ptr %y336  %c = or <16 x i8> %a, %b337  store <16 x i8> %c, ptr %x338  ret void339}340 341define void @or_v8i16(ptr %x, ptr %y) {342; CHECK-LABEL: or_v8i16:343; CHECK:       # %bb.0:344; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma345; CHECK-NEXT:    vle16.v v8, (a0)346; CHECK-NEXT:    vle16.v v9, (a1)347; CHECK-NEXT:    vor.vv v8, v8, v9348; CHECK-NEXT:    vse16.v v8, (a0)349; CHECK-NEXT:    ret350  %a = load <8 x i16>, ptr %x351  %b = load <8 x i16>, ptr %y352  %c = or <8 x i16> %a, %b353  store <8 x i16> %c, ptr %x354  ret void355}356 357define void @or_v6i16(ptr %x, ptr %y) {358; CHECK-LABEL: or_v6i16:359; CHECK:       # %bb.0:360; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma361; CHECK-NEXT:    vle16.v v8, (a0)362; CHECK-NEXT:    vle16.v v9, (a1)363; CHECK-NEXT:    vor.vv v8, v8, v9364; CHECK-NEXT:    vse16.v v8, (a0)365; CHECK-NEXT:    ret366  %a = load <6 x i16>, ptr %x367  %b = load <6 x i16>, ptr %y368  %c = or <6 x i16> %a, %b369  store <6 x i16> %c, ptr %x370  ret void371}372 373define void @or_v4i32(ptr %x, ptr %y) {374; CHECK-LABEL: or_v4i32:375; CHECK:       # %bb.0:376; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma377; CHECK-NEXT:    vle32.v v8, (a0)378; CHECK-NEXT:    vle32.v v9, (a1)379; CHECK-NEXT:    vor.vv v8, v8, v9380; CHECK-NEXT:    vse32.v v8, (a0)381; CHECK-NEXT:    ret382  %a = load <4 x i32>, ptr %x383  %b = load <4 x i32>, ptr %y384  %c = or <4 x i32> %a, %b385  store <4 x i32> %c, ptr %x386  ret void387}388 389define void @or_v2i64(ptr %x, ptr %y) {390; CHECK-LABEL: or_v2i64:391; CHECK:       # %bb.0:392; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma393; CHECK-NEXT:    vle64.v v8, (a0)394; CHECK-NEXT:    vle64.v v9, (a1)395; CHECK-NEXT:    vor.vv v8, v8, v9396; CHECK-NEXT:    vse64.v v8, (a0)397; CHECK-NEXT:    ret398  %a = load <2 x i64>, ptr %x399  %b = load <2 x i64>, ptr %y400  %c = or <2 x i64> %a, %b401  store <2 x i64> %c, ptr %x402  ret void403}404 405define void @xor_v16i8(ptr %x, ptr %y) {406; CHECK-LABEL: xor_v16i8:407; CHECK:       # %bb.0:408; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma409; CHECK-NEXT:    vle8.v v8, (a0)410; CHECK-NEXT:    vle8.v v9, (a1)411; CHECK-NEXT:    vxor.vv v8, v8, v9412; CHECK-NEXT:    vse8.v v8, (a0)413; CHECK-NEXT:    ret414  %a = load <16 x i8>, ptr %x415  %b = load <16 x i8>, ptr %y416  %c = xor <16 x i8> %a, %b417  store <16 x i8> %c, ptr %x418  ret void419}420 421define void @xor_v8i16(ptr %x, ptr %y) {422; CHECK-LABEL: xor_v8i16:423; CHECK:       # %bb.0:424; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma425; CHECK-NEXT:    vle16.v v8, (a0)426; CHECK-NEXT:    vle16.v v9, (a1)427; CHECK-NEXT:    vxor.vv v8, v8, v9428; CHECK-NEXT:    vse16.v v8, (a0)429; CHECK-NEXT:    ret430  %a = load <8 x i16>, ptr %x431  %b = load <8 x i16>, ptr %y432  %c = xor <8 x i16> %a, %b433  store <8 x i16> %c, ptr %x434  ret void435}436 437define void @xor_v6i16(ptr %x, ptr %y) {438; CHECK-LABEL: xor_v6i16:439; CHECK:       # %bb.0:440; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma441; CHECK-NEXT:    vle16.v v8, (a0)442; CHECK-NEXT:    vle16.v v9, (a1)443; CHECK-NEXT:    vxor.vv v8, v8, v9444; CHECK-NEXT:    vse16.v v8, (a0)445; CHECK-NEXT:    ret446  %a = load <6 x i16>, ptr %x447  %b = load <6 x i16>, ptr %y448  %c = xor <6 x i16> %a, %b449  store <6 x i16> %c, ptr %x450  ret void451}452 453define void @xor_v4i32(ptr %x, ptr %y) {454; CHECK-LABEL: xor_v4i32:455; CHECK:       # %bb.0:456; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma457; CHECK-NEXT:    vle32.v v8, (a0)458; CHECK-NEXT:    vle32.v v9, (a1)459; CHECK-NEXT:    vxor.vv v8, v8, v9460; CHECK-NEXT:    vse32.v v8, (a0)461; CHECK-NEXT:    ret462  %a = load <4 x i32>, ptr %x463  %b = load <4 x i32>, ptr %y464  %c = xor <4 x i32> %a, %b465  store <4 x i32> %c, ptr %x466  ret void467}468 469define void @xor_v2i64(ptr %x, ptr %y) {470; CHECK-LABEL: xor_v2i64:471; CHECK:       # %bb.0:472; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma473; CHECK-NEXT:    vle64.v v8, (a0)474; CHECK-NEXT:    vle64.v v9, (a1)475; CHECK-NEXT:    vxor.vv v8, v8, v9476; CHECK-NEXT:    vse64.v v8, (a0)477; CHECK-NEXT:    ret478  %a = load <2 x i64>, ptr %x479  %b = load <2 x i64>, ptr %y480  %c = xor <2 x i64> %a, %b481  store <2 x i64> %c, ptr %x482  ret void483}484 485define void @lshr_v16i8(ptr %x, ptr %y) {486; CHECK-LABEL: lshr_v16i8:487; CHECK:       # %bb.0:488; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma489; CHECK-NEXT:    vle8.v v8, (a0)490; CHECK-NEXT:    vle8.v v9, (a1)491; CHECK-NEXT:    vsrl.vv v8, v8, v9492; CHECK-NEXT:    vse8.v v8, (a0)493; CHECK-NEXT:    ret494  %a = load <16 x i8>, ptr %x495  %b = load <16 x i8>, ptr %y496  %c = lshr <16 x i8> %a, %b497  store <16 x i8> %c, ptr %x498  ret void499}500 501define void @lshr_v8i16(ptr %x, ptr %y) {502; CHECK-LABEL: lshr_v8i16:503; CHECK:       # %bb.0:504; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma505; CHECK-NEXT:    vle16.v v8, (a0)506; CHECK-NEXT:    vle16.v v9, (a1)507; CHECK-NEXT:    vsrl.vv v8, v8, v9508; CHECK-NEXT:    vse16.v v8, (a0)509; CHECK-NEXT:    ret510  %a = load <8 x i16>, ptr %x511  %b = load <8 x i16>, ptr %y512  %c = lshr <8 x i16> %a, %b513  store <8 x i16> %c, ptr %x514  ret void515}516 517define void @lshr_v6i16(ptr %x, ptr %y) {518; CHECK-LABEL: lshr_v6i16:519; CHECK:       # %bb.0:520; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma521; CHECK-NEXT:    vle16.v v8, (a0)522; CHECK-NEXT:    vle16.v v9, (a1)523; CHECK-NEXT:    vsrl.vv v8, v8, v9524; CHECK-NEXT:    vse16.v v8, (a0)525; CHECK-NEXT:    ret526  %a = load <6 x i16>, ptr %x527  %b = load <6 x i16>, ptr %y528  %c = lshr <6 x i16> %a, %b529  store <6 x i16> %c, ptr %x530  ret void531}532 533define void @lshr_v4i32(ptr %x, ptr %y) {534; CHECK-LABEL: lshr_v4i32:535; CHECK:       # %bb.0:536; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma537; CHECK-NEXT:    vle32.v v8, (a0)538; CHECK-NEXT:    vle32.v v9, (a1)539; CHECK-NEXT:    vsrl.vv v8, v8, v9540; CHECK-NEXT:    vse32.v v8, (a0)541; CHECK-NEXT:    ret542  %a = load <4 x i32>, ptr %x543  %b = load <4 x i32>, ptr %y544  %c = lshr <4 x i32> %a, %b545  store <4 x i32> %c, ptr %x546  ret void547}548 549define void @lshr_v2i64(ptr %x, ptr %y) {550; CHECK-LABEL: lshr_v2i64:551; CHECK:       # %bb.0:552; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma553; CHECK-NEXT:    vle64.v v8, (a0)554; CHECK-NEXT:    vle64.v v9, (a1)555; CHECK-NEXT:    vsrl.vv v8, v8, v9556; CHECK-NEXT:    vse64.v v8, (a0)557; CHECK-NEXT:    ret558  %a = load <2 x i64>, ptr %x559  %b = load <2 x i64>, ptr %y560  %c = lshr <2 x i64> %a, %b561  store <2 x i64> %c, ptr %x562  ret void563}564 565define void @ashr_v16i8(ptr %x, ptr %y) {566; CHECK-LABEL: ashr_v16i8:567; CHECK:       # %bb.0:568; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma569; CHECK-NEXT:    vle8.v v8, (a0)570; CHECK-NEXT:    vle8.v v9, (a1)571; CHECK-NEXT:    vsra.vv v8, v8, v9572; CHECK-NEXT:    vse8.v v8, (a0)573; CHECK-NEXT:    ret574  %a = load <16 x i8>, ptr %x575  %b = load <16 x i8>, ptr %y576  %c = ashr <16 x i8> %a, %b577  store <16 x i8> %c, ptr %x578  ret void579}580 581define void @ashr_v8i16(ptr %x, ptr %y) {582; CHECK-LABEL: ashr_v8i16:583; CHECK:       # %bb.0:584; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma585; CHECK-NEXT:    vle16.v v8, (a0)586; CHECK-NEXT:    vle16.v v9, (a1)587; CHECK-NEXT:    vsra.vv v8, v8, v9588; CHECK-NEXT:    vse16.v v8, (a0)589; CHECK-NEXT:    ret590  %a = load <8 x i16>, ptr %x591  %b = load <8 x i16>, ptr %y592  %c = ashr <8 x i16> %a, %b593  store <8 x i16> %c, ptr %x594  ret void595}596 597define void @ashr_v6i16(ptr %x, ptr %y) {598; CHECK-LABEL: ashr_v6i16:599; CHECK:       # %bb.0:600; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma601; CHECK-NEXT:    vle16.v v8, (a0)602; CHECK-NEXT:    vle16.v v9, (a1)603; CHECK-NEXT:    vsra.vv v8, v8, v9604; CHECK-NEXT:    vse16.v v8, (a0)605; CHECK-NEXT:    ret606  %a = load <6 x i16>, ptr %x607  %b = load <6 x i16>, ptr %y608  %c = ashr <6 x i16> %a, %b609  store <6 x i16> %c, ptr %x610  ret void611}612 613define void @ashr_v4i32(ptr %x, ptr %y) {614; CHECK-LABEL: ashr_v4i32:615; CHECK:       # %bb.0:616; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma617; CHECK-NEXT:    vle32.v v8, (a0)618; CHECK-NEXT:    vle32.v v9, (a1)619; CHECK-NEXT:    vsra.vv v8, v8, v9620; CHECK-NEXT:    vse32.v v8, (a0)621; CHECK-NEXT:    ret622  %a = load <4 x i32>, ptr %x623  %b = load <4 x i32>, ptr %y624  %c = ashr <4 x i32> %a, %b625  store <4 x i32> %c, ptr %x626  ret void627}628 629define void @ashr_v2i64(ptr %x, ptr %y) {630; CHECK-LABEL: ashr_v2i64:631; CHECK:       # %bb.0:632; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma633; CHECK-NEXT:    vle64.v v8, (a0)634; CHECK-NEXT:    vle64.v v9, (a1)635; CHECK-NEXT:    vsra.vv v8, v8, v9636; CHECK-NEXT:    vse64.v v8, (a0)637; CHECK-NEXT:    ret638  %a = load <2 x i64>, ptr %x639  %b = load <2 x i64>, ptr %y640  %c = ashr <2 x i64> %a, %b641  store <2 x i64> %c, ptr %x642  ret void643}644 645define void @shl_v16i8(ptr %x, ptr %y) {646; CHECK-LABEL: shl_v16i8:647; CHECK:       # %bb.0:648; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma649; CHECK-NEXT:    vle8.v v8, (a0)650; CHECK-NEXT:    vle8.v v9, (a1)651; CHECK-NEXT:    vsll.vv v8, v8, v9652; CHECK-NEXT:    vse8.v v8, (a0)653; CHECK-NEXT:    ret654  %a = load <16 x i8>, ptr %x655  %b = load <16 x i8>, ptr %y656  %c = shl <16 x i8> %a, %b657  store <16 x i8> %c, ptr %x658  ret void659}660 661define void @shl_v8i16(ptr %x, ptr %y) {662; CHECK-LABEL: shl_v8i16:663; CHECK:       # %bb.0:664; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma665; CHECK-NEXT:    vle16.v v8, (a0)666; CHECK-NEXT:    vle16.v v9, (a1)667; CHECK-NEXT:    vsll.vv v8, v8, v9668; CHECK-NEXT:    vse16.v v8, (a0)669; CHECK-NEXT:    ret670  %a = load <8 x i16>, ptr %x671  %b = load <8 x i16>, ptr %y672  %c = shl <8 x i16> %a, %b673  store <8 x i16> %c, ptr %x674  ret void675}676 677define void @shl_v6i16(ptr %x, ptr %y) {678; CHECK-LABEL: shl_v6i16:679; CHECK:       # %bb.0:680; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma681; CHECK-NEXT:    vle16.v v8, (a0)682; CHECK-NEXT:    vle16.v v9, (a1)683; CHECK-NEXT:    vsll.vv v8, v8, v9684; CHECK-NEXT:    vse16.v v8, (a0)685; CHECK-NEXT:    ret686  %a = load <6 x i16>, ptr %x687  %b = load <6 x i16>, ptr %y688  %c = shl <6 x i16> %a, %b689  store <6 x i16> %c, ptr %x690  ret void691}692 693define void @shl_v4i32(ptr %x, ptr %y) {694; CHECK-LABEL: shl_v4i32:695; CHECK:       # %bb.0:696; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma697; CHECK-NEXT:    vle32.v v8, (a0)698; CHECK-NEXT:    vle32.v v9, (a1)699; CHECK-NEXT:    vsll.vv v8, v8, v9700; CHECK-NEXT:    vse32.v v8, (a0)701; CHECK-NEXT:    ret702  %a = load <4 x i32>, ptr %x703  %b = load <4 x i32>, ptr %y704  %c = shl <4 x i32> %a, %b705  store <4 x i32> %c, ptr %x706  ret void707}708 709define void @shl_v2i64(ptr %x, ptr %y) {710; CHECK-LABEL: shl_v2i64:711; CHECK:       # %bb.0:712; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma713; CHECK-NEXT:    vle64.v v8, (a0)714; CHECK-NEXT:    vle64.v v9, (a1)715; CHECK-NEXT:    vsll.vv v8, v8, v9716; CHECK-NEXT:    vse64.v v8, (a0)717; CHECK-NEXT:    ret718  %a = load <2 x i64>, ptr %x719  %b = load <2 x i64>, ptr %y720  %c = shl <2 x i64> %a, %b721  store <2 x i64> %c, ptr %x722  ret void723}724 725define void @sdiv_v16i8(ptr %x, ptr %y) {726; CHECK-LABEL: sdiv_v16i8:727; CHECK:       # %bb.0:728; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma729; CHECK-NEXT:    vle8.v v8, (a0)730; CHECK-NEXT:    vle8.v v9, (a1)731; CHECK-NEXT:    vdiv.vv v8, v8, v9732; CHECK-NEXT:    vse8.v v8, (a0)733; CHECK-NEXT:    ret734  %a = load <16 x i8>, ptr %x735  %b = load <16 x i8>, ptr %y736  %c = sdiv <16 x i8> %a, %b737  store <16 x i8> %c, ptr %x738  ret void739}740 741define void @sdiv_v8i16(ptr %x, ptr %y) {742; CHECK-LABEL: sdiv_v8i16:743; CHECK:       # %bb.0:744; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma745; CHECK-NEXT:    vle16.v v8, (a0)746; CHECK-NEXT:    vle16.v v9, (a1)747; CHECK-NEXT:    vdiv.vv v8, v8, v9748; CHECK-NEXT:    vse16.v v8, (a0)749; CHECK-NEXT:    ret750  %a = load <8 x i16>, ptr %x751  %b = load <8 x i16>, ptr %y752  %c = sdiv <8 x i16> %a, %b753  store <8 x i16> %c, ptr %x754  ret void755}756 757define void @sdiv_v6i16(ptr %x, ptr %y) {758; CHECK-LABEL: sdiv_v6i16:759; CHECK:       # %bb.0:760; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma761; CHECK-NEXT:    vle16.v v8, (a0)762; CHECK-NEXT:    vle16.v v9, (a1)763; CHECK-NEXT:    vdiv.vv v8, v8, v9764; CHECK-NEXT:    vse16.v v8, (a0)765; CHECK-NEXT:    ret766  %a = load <6 x i16>, ptr %x767  %b = load <6 x i16>, ptr %y768  %c = sdiv <6 x i16> %a, %b769  store <6 x i16> %c, ptr %x770  ret void771}772 773define void @sdiv_v4i32(ptr %x, ptr %y) {774; CHECK-LABEL: sdiv_v4i32:775; CHECK:       # %bb.0:776; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma777; CHECK-NEXT:    vle32.v v8, (a0)778; CHECK-NEXT:    vle32.v v9, (a1)779; CHECK-NEXT:    vdiv.vv v8, v8, v9780; CHECK-NEXT:    vse32.v v8, (a0)781; CHECK-NEXT:    ret782  %a = load <4 x i32>, ptr %x783  %b = load <4 x i32>, ptr %y784  %c = sdiv <4 x i32> %a, %b785  store <4 x i32> %c, ptr %x786  ret void787}788 789define void @sdiv_v2i64(ptr %x, ptr %y) {790; CHECK-LABEL: sdiv_v2i64:791; CHECK:       # %bb.0:792; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma793; CHECK-NEXT:    vle64.v v8, (a0)794; CHECK-NEXT:    vle64.v v9, (a1)795; CHECK-NEXT:    vdiv.vv v8, v8, v9796; CHECK-NEXT:    vse64.v v8, (a0)797; CHECK-NEXT:    ret798  %a = load <2 x i64>, ptr %x799  %b = load <2 x i64>, ptr %y800  %c = sdiv <2 x i64> %a, %b801  store <2 x i64> %c, ptr %x802  ret void803}804 805define void @srem_v16i8(ptr %x, ptr %y) {806; CHECK-LABEL: srem_v16i8:807; CHECK:       # %bb.0:808; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma809; CHECK-NEXT:    vle8.v v8, (a0)810; CHECK-NEXT:    vle8.v v9, (a1)811; CHECK-NEXT:    vrem.vv v8, v8, v9812; CHECK-NEXT:    vse8.v v8, (a0)813; CHECK-NEXT:    ret814  %a = load <16 x i8>, ptr %x815  %b = load <16 x i8>, ptr %y816  %c = srem <16 x i8> %a, %b817  store <16 x i8> %c, ptr %x818  ret void819}820 821define void @srem_v8i16(ptr %x, ptr %y) {822; CHECK-LABEL: srem_v8i16:823; CHECK:       # %bb.0:824; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma825; CHECK-NEXT:    vle16.v v8, (a0)826; CHECK-NEXT:    vle16.v v9, (a1)827; CHECK-NEXT:    vrem.vv v8, v8, v9828; CHECK-NEXT:    vse16.v v8, (a0)829; CHECK-NEXT:    ret830  %a = load <8 x i16>, ptr %x831  %b = load <8 x i16>, ptr %y832  %c = srem <8 x i16> %a, %b833  store <8 x i16> %c, ptr %x834  ret void835}836 837define void @srem_v6i16(ptr %x, ptr %y) {838; CHECK-LABEL: srem_v6i16:839; CHECK:       # %bb.0:840; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma841; CHECK-NEXT:    vle16.v v8, (a0)842; CHECK-NEXT:    vle16.v v9, (a1)843; CHECK-NEXT:    vrem.vv v8, v8, v9844; CHECK-NEXT:    vse16.v v8, (a0)845; CHECK-NEXT:    ret846  %a = load <6 x i16>, ptr %x847  %b = load <6 x i16>, ptr %y848  %c = srem <6 x i16> %a, %b849  store <6 x i16> %c, ptr %x850  ret void851}852 853define void @srem_v4i32(ptr %x, ptr %y) {854; CHECK-LABEL: srem_v4i32:855; CHECK:       # %bb.0:856; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma857; CHECK-NEXT:    vle32.v v8, (a0)858; CHECK-NEXT:    vle32.v v9, (a1)859; CHECK-NEXT:    vrem.vv v8, v8, v9860; CHECK-NEXT:    vse32.v v8, (a0)861; CHECK-NEXT:    ret862  %a = load <4 x i32>, ptr %x863  %b = load <4 x i32>, ptr %y864  %c = srem <4 x i32> %a, %b865  store <4 x i32> %c, ptr %x866  ret void867}868 869define void @srem_v2i64(ptr %x, ptr %y) {870; CHECK-LABEL: srem_v2i64:871; CHECK:       # %bb.0:872; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma873; CHECK-NEXT:    vle64.v v8, (a0)874; CHECK-NEXT:    vle64.v v9, (a1)875; CHECK-NEXT:    vrem.vv v8, v8, v9876; CHECK-NEXT:    vse64.v v8, (a0)877; CHECK-NEXT:    ret878  %a = load <2 x i64>, ptr %x879  %b = load <2 x i64>, ptr %y880  %c = srem <2 x i64> %a, %b881  store <2 x i64> %c, ptr %x882  ret void883}884 885define void @udiv_v16i8(ptr %x, ptr %y) {886; CHECK-LABEL: udiv_v16i8:887; CHECK:       # %bb.0:888; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma889; CHECK-NEXT:    vle8.v v8, (a0)890; CHECK-NEXT:    vle8.v v9, (a1)891; CHECK-NEXT:    vdivu.vv v8, v8, v9892; CHECK-NEXT:    vse8.v v8, (a0)893; CHECK-NEXT:    ret894  %a = load <16 x i8>, ptr %x895  %b = load <16 x i8>, ptr %y896  %c = udiv <16 x i8> %a, %b897  store <16 x i8> %c, ptr %x898  ret void899}900 901define void @udiv_v8i16(ptr %x, ptr %y) {902; CHECK-LABEL: udiv_v8i16:903; CHECK:       # %bb.0:904; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma905; CHECK-NEXT:    vle16.v v8, (a0)906; CHECK-NEXT:    vle16.v v9, (a1)907; CHECK-NEXT:    vdivu.vv v8, v8, v9908; CHECK-NEXT:    vse16.v v8, (a0)909; CHECK-NEXT:    ret910  %a = load <8 x i16>, ptr %x911  %b = load <8 x i16>, ptr %y912  %c = udiv <8 x i16> %a, %b913  store <8 x i16> %c, ptr %x914  ret void915}916 917define void @udiv_v6i16(ptr %x, ptr %y) {918; CHECK-LABEL: udiv_v6i16:919; CHECK:       # %bb.0:920; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma921; CHECK-NEXT:    vle16.v v8, (a0)922; CHECK-NEXT:    vle16.v v9, (a1)923; CHECK-NEXT:    vdivu.vv v8, v8, v9924; CHECK-NEXT:    vse16.v v8, (a0)925; CHECK-NEXT:    ret926  %a = load <6 x i16>, ptr %x927  %b = load <6 x i16>, ptr %y928  %c = udiv <6 x i16> %a, %b929  store <6 x i16> %c, ptr %x930  ret void931}932 933define void @udiv_v4i32(ptr %x, ptr %y) {934; CHECK-LABEL: udiv_v4i32:935; CHECK:       # %bb.0:936; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma937; CHECK-NEXT:    vle32.v v8, (a0)938; CHECK-NEXT:    vle32.v v9, (a1)939; CHECK-NEXT:    vdivu.vv v8, v8, v9940; CHECK-NEXT:    vse32.v v8, (a0)941; CHECK-NEXT:    ret942  %a = load <4 x i32>, ptr %x943  %b = load <4 x i32>, ptr %y944  %c = udiv <4 x i32> %a, %b945  store <4 x i32> %c, ptr %x946  ret void947}948 949define void @udiv_v2i64(ptr %x, ptr %y) {950; CHECK-LABEL: udiv_v2i64:951; CHECK:       # %bb.0:952; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma953; CHECK-NEXT:    vle64.v v8, (a0)954; CHECK-NEXT:    vle64.v v9, (a1)955; CHECK-NEXT:    vdivu.vv v8, v8, v9956; CHECK-NEXT:    vse64.v v8, (a0)957; CHECK-NEXT:    ret958  %a = load <2 x i64>, ptr %x959  %b = load <2 x i64>, ptr %y960  %c = udiv <2 x i64> %a, %b961  store <2 x i64> %c, ptr %x962  ret void963}964 965define void @urem_v16i8(ptr %x, ptr %y) {966; CHECK-LABEL: urem_v16i8:967; CHECK:       # %bb.0:968; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma969; CHECK-NEXT:    vle8.v v8, (a0)970; CHECK-NEXT:    vle8.v v9, (a1)971; CHECK-NEXT:    vremu.vv v8, v8, v9972; CHECK-NEXT:    vse8.v v8, (a0)973; CHECK-NEXT:    ret974  %a = load <16 x i8>, ptr %x975  %b = load <16 x i8>, ptr %y976  %c = urem <16 x i8> %a, %b977  store <16 x i8> %c, ptr %x978  ret void979}980 981define void @urem_v8i16(ptr %x, ptr %y) {982; CHECK-LABEL: urem_v8i16:983; CHECK:       # %bb.0:984; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma985; CHECK-NEXT:    vle16.v v8, (a0)986; CHECK-NEXT:    vle16.v v9, (a1)987; CHECK-NEXT:    vremu.vv v8, v8, v9988; CHECK-NEXT:    vse16.v v8, (a0)989; CHECK-NEXT:    ret990  %a = load <8 x i16>, ptr %x991  %b = load <8 x i16>, ptr %y992  %c = urem <8 x i16> %a, %b993  store <8 x i16> %c, ptr %x994  ret void995}996 997define void @urem_v6i16(ptr %x, ptr %y) {998; CHECK-LABEL: urem_v6i16:999; CHECK:       # %bb.0:1000; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma1001; CHECK-NEXT:    vle16.v v8, (a0)1002; CHECK-NEXT:    vle16.v v9, (a1)1003; CHECK-NEXT:    vremu.vv v8, v8, v91004; CHECK-NEXT:    vse16.v v8, (a0)1005; CHECK-NEXT:    ret1006  %a = load <6 x i16>, ptr %x1007  %b = load <6 x i16>, ptr %y1008  %c = urem <6 x i16> %a, %b1009  store <6 x i16> %c, ptr %x1010  ret void1011}1012 1013define void @urem_v4i32(ptr %x, ptr %y) {1014; CHECK-LABEL: urem_v4i32:1015; CHECK:       # %bb.0:1016; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma1017; CHECK-NEXT:    vle32.v v8, (a0)1018; CHECK-NEXT:    vle32.v v9, (a1)1019; CHECK-NEXT:    vremu.vv v8, v8, v91020; CHECK-NEXT:    vse32.v v8, (a0)1021; CHECK-NEXT:    ret1022  %a = load <4 x i32>, ptr %x1023  %b = load <4 x i32>, ptr %y1024  %c = urem <4 x i32> %a, %b1025  store <4 x i32> %c, ptr %x1026  ret void1027}1028 1029define void @urem_v2i64(ptr %x, ptr %y) {1030; CHECK-LABEL: urem_v2i64:1031; CHECK:       # %bb.0:1032; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma1033; CHECK-NEXT:    vle64.v v8, (a0)1034; CHECK-NEXT:    vle64.v v9, (a1)1035; CHECK-NEXT:    vremu.vv v8, v8, v91036; CHECK-NEXT:    vse64.v v8, (a0)1037; CHECK-NEXT:    ret1038  %a = load <2 x i64>, ptr %x1039  %b = load <2 x i64>, ptr %y1040  %c = urem <2 x i64> %a, %b1041  store <2 x i64> %c, ptr %x1042  ret void1043}1044 1045define void @mulhu_v16i8(ptr %x) {1046; CHECK-LABEL: mulhu_v16i8:1047; CHECK:       # %bb.0:1048; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma1049; CHECK-NEXT:    vle8.v v8, (a0)1050; CHECK-NEXT:    lui a1, 31051; CHECK-NEXT:    vmv.v.i v9, 01052; CHECK-NEXT:    lui a2, %hi(.LCPI65_0)1053; CHECK-NEXT:    addi a2, a2, %lo(.LCPI65_0)1054; CHECK-NEXT:    vle8.v v10, (a2)1055; CHECK-NEXT:    li a2, -1281056; CHECK-NEXT:    addi a1, a1, -20441057; CHECK-NEXT:    vsetvli zero, zero, e16, m2, ta, ma1058; CHECK-NEXT:    vmv.s.x v0, a11059; CHECK-NEXT:    lui a1, 11060; CHECK-NEXT:    vsetvli zero, zero, e8, m1, ta, ma1061; CHECK-NEXT:    vmerge.vxm v11, v9, a2, v01062; CHECK-NEXT:    addi a2, a1, 321063; CHECK-NEXT:    vsetvli zero, zero, e16, m2, ta, ma1064; CHECK-NEXT:    vmv.s.x v0, a21065; CHECK-NEXT:    li a2, 5131066; CHECK-NEXT:    vsetvli zero, zero, e8, m1, ta, ma1067; CHECK-NEXT:    vmv.v.i v12, 41068; CHECK-NEXT:    addi a1, a1, 781069; CHECK-NEXT:    vmerge.vim v9, v9, 1, v01070; CHECK-NEXT:    vsetvli zero, zero, e16, m2, ta, ma1071; CHECK-NEXT:    vmv.s.x v0, a21072; CHECK-NEXT:    vsetvli zero, zero, e8, m1, ta, ma1073; CHECK-NEXT:    vsrl.vv v9, v8, v91074; CHECK-NEXT:    vmerge.vim v12, v12, 1, v01075; CHECK-NEXT:    vsetvli zero, zero, e16, m2, ta, ma1076; CHECK-NEXT:    vmv.s.x v0, a11077; CHECK-NEXT:    vsetvli zero, zero, e8, m1, ta, ma1078; CHECK-NEXT:    vmulhu.vv v9, v9, v101079; CHECK-NEXT:    vmerge.vim v10, v12, 3, v01080; CHECK-NEXT:    lui a1, 81081; CHECK-NEXT:    addi a1, a1, 3041082; CHECK-NEXT:    vsub.vv v8, v8, v91083; CHECK-NEXT:    vmulhu.vv v8, v8, v111084; CHECK-NEXT:    vsetvli zero, zero, e16, m2, ta, ma1085; CHECK-NEXT:    vmv.s.x v0, a11086; CHECK-NEXT:    vsetvli zero, zero, e8, m1, ta, ma1087; CHECK-NEXT:    vadd.vv v8, v8, v91088; CHECK-NEXT:    vmerge.vim v9, v10, 2, v01089; CHECK-NEXT:    vsrl.vv v8, v8, v91090; CHECK-NEXT:    vse8.v v8, (a0)1091; CHECK-NEXT:    ret1092  %a = load <16 x i8>, ptr %x1093  %b = udiv <16 x i8> %a, <i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25>1094  store <16 x i8> %b, ptr %x1095  ret void1096}1097 1098define void @mulhu_v8i16(ptr %x) {1099; CHECK-LABEL: mulhu_v8i16:1100; CHECK:       # %bb.0:1101; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma1102; CHECK-NEXT:    vle16.v v8, (a0)1103; CHECK-NEXT:    vmv.v.i v9, 01104; CHECK-NEXT:    vsetivli zero, 7, e16, m1, ta, ma1105; CHECK-NEXT:    vmv.v.i v10, 11106; CHECK-NEXT:    li a1, 331107; CHECK-NEXT:    vmv.s.x v0, a11108; CHECK-NEXT:    lui a1, %hi(.LCPI66_0)1109; CHECK-NEXT:    addi a1, a1, %lo(.LCPI66_0)1110; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma1111; CHECK-NEXT:    vmv.v.i v11, 31112; CHECK-NEXT:    vle16.v v12, (a1)1113; CHECK-NEXT:    vmerge.vim v11, v11, 2, v01114; CHECK-NEXT:    vmv1r.v v13, v91115; CHECK-NEXT:    vsetivli zero, 7, e16, m1, tu, ma1116; CHECK-NEXT:    vslideup.vi v9, v10, 61117; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma1118; CHECK-NEXT:    vsrl.vv v9, v8, v91119; CHECK-NEXT:    vmulhu.vv v9, v9, v121120; CHECK-NEXT:    lui a1, 10485681121; CHECK-NEXT:    vsetvli zero, zero, e16, m1, tu, ma1122; CHECK-NEXT:    vmv.s.x v13, a11123; CHECK-NEXT:    vsetvli zero, zero, e16, m1, ta, ma1124; CHECK-NEXT:    vsub.vv v8, v8, v91125; CHECK-NEXT:    vmulhu.vv v8, v8, v131126; CHECK-NEXT:    vadd.vv v8, v8, v91127; CHECK-NEXT:    vsetivli zero, 7, e16, m1, tu, ma1128; CHECK-NEXT:    vslideup.vi v11, v10, 61129; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma1130; CHECK-NEXT:    vsrl.vv v8, v8, v111131; CHECK-NEXT:    vse16.v v8, (a0)1132; CHECK-NEXT:    ret1133  %a = load <8 x i16>, ptr %x1134  %b = udiv <8 x i16> %a, <i16 7, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>1135  store <8 x i16> %b, ptr %x1136  ret void1137}1138 1139define void @mulhu_v6i16(ptr %x) {1140; CHECK-LABEL: mulhu_v6i16:1141; CHECK:       # %bb.0:1142; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma1143; CHECK-NEXT:    vle16.v v8, (a0)1144; CHECK-NEXT:    lui a1, %hi(.LCPI67_0)1145; CHECK-NEXT:    addi a1, a1, %lo(.LCPI67_0)1146; CHECK-NEXT:    vle16.v v9, (a1)1147; CHECK-NEXT:    vdivu.vv v8, v8, v91148; CHECK-NEXT:    vse16.v v8, (a0)1149; CHECK-NEXT:    ret1150  %a = load <6 x i16>, ptr %x1151  %b = udiv <6 x i16> %a, <i16 7, i16 9, i16 10, i16 11, i16 12, i16 13>1152  store <6 x i16> %b, ptr %x1153  ret void1154}1155 1156define void @mulhu_v4i32(ptr %x) {1157; CHECK-LABEL: mulhu_v4i32:1158; CHECK:       # %bb.0:1159; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma1160; CHECK-NEXT:    vle32.v v8, (a0)1161; CHECK-NEXT:    lui a1, 5242881162; CHECK-NEXT:    vmv.v.i v9, 01163; CHECK-NEXT:    vmv.s.x v10, a11164; CHECK-NEXT:    lui a1, %hi(.LCPI68_0)1165; CHECK-NEXT:    addi a1, a1, %lo(.LCPI68_0)1166; CHECK-NEXT:    vle32.v v11, (a1)1167; CHECK-NEXT:    vsetivli zero, 3, e32, m1, tu, ma1168; CHECK-NEXT:    vslideup.vi v9, v10, 21169; CHECK-NEXT:    lui a1, 41281170; CHECK-NEXT:    addi a1, a1, 5141171; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma1172; CHECK-NEXT:    vmulhu.vv v10, v8, v111173; CHECK-NEXT:    vsub.vv v8, v8, v101174; CHECK-NEXT:    vmulhu.vv v8, v8, v91175; CHECK-NEXT:    vmv.s.x v9, a11176; CHECK-NEXT:    vadd.vv v8, v8, v101177; CHECK-NEXT:    vsext.vf4 v10, v91178; CHECK-NEXT:    vsrl.vv v8, v8, v101179; CHECK-NEXT:    vse32.v v8, (a0)1180; CHECK-NEXT:    ret1181  %a = load <4 x i32>, ptr %x1182  %b = udiv <4 x i32> %a, <i32 5, i32 6, i32 7, i32 9>1183  store <4 x i32> %b, ptr %x1184  ret void1185}1186 1187define void @mulhu_v2i64(ptr %x) {1188; RV32-LABEL: mulhu_v2i64:1189; RV32:       # %bb.0:1190; RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, ma1191; RV32-NEXT:    vle64.v v8, (a0)1192; RV32-NEXT:    lui a1, %hi(.LCPI69_0)1193; RV32-NEXT:    addi a1, a1, %lo(.LCPI69_0)1194; RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, ma1195; RV32-NEXT:    vle32.v v9, (a1)1196; RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, ma1197; RV32-NEXT:    vmulhu.vv v8, v8, v91198; RV32-NEXT:    vid.v v91199; RV32-NEXT:    vadd.vi v9, v9, 11200; RV32-NEXT:    vsrl.vv v8, v8, v91201; RV32-NEXT:    vse64.v v8, (a0)1202; RV32-NEXT:    ret1203;1204; RV64-LABEL: mulhu_v2i64:1205; RV64:       # %bb.0:1206; RV64-NEXT:    vsetivli zero, 2, e64, m1, ta, ma1207; RV64-NEXT:    vle64.v v8, (a0)1208; RV64-NEXT:    lui a1, 8388611209; RV64-NEXT:    lui a2, 6990511210; RV64-NEXT:    addi a1, a1, -8191211; RV64-NEXT:    addi a2, a2, -13651212; RV64-NEXT:    slli a3, a1, 321213; RV64-NEXT:    add a1, a1, a31214; RV64-NEXT:    slli a3, a2, 321215; RV64-NEXT:    add a2, a2, a31216; RV64-NEXT:    vmv.v.x v9, a11217; RV64-NEXT:    vsetvli zero, zero, e64, m1, tu, ma1218; RV64-NEXT:    vmv.s.x v9, a21219; RV64-NEXT:    vsetvli zero, zero, e64, m1, ta, ma1220; RV64-NEXT:    vmulhu.vv v8, v8, v91221; RV64-NEXT:    vid.v v91222; RV64-NEXT:    vadd.vi v9, v9, 11223; RV64-NEXT:    vsrl.vv v8, v8, v91224; RV64-NEXT:    vse64.v v8, (a0)1225; RV64-NEXT:    ret1226  %a = load <2 x i64>, ptr %x1227  %b = udiv <2 x i64> %a, <i64 3, i64 5>1228  store <2 x i64> %b, ptr %x1229  ret void1230}1231 1232define void @mulhs_v16i8(ptr %x) {1233; CHECK-LABEL: mulhs_v16i8:1234; CHECK:       # %bb.0:1235; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma1236; CHECK-NEXT:    vle8.v v8, (a0)1237; CHECK-NEXT:    li a1, -1231238; CHECK-NEXT:    vmv.v.x v9, a11239; CHECK-NEXT:    lui a1, 51240; CHECK-NEXT:    addi a1, a1, -14521241; CHECK-NEXT:    vsetvli zero, zero, e16, m2, ta, ma1242; CHECK-NEXT:    vmv.s.x v0, a11243; CHECK-NEXT:    li a1, 571244; CHECK-NEXT:    vsetvli zero, zero, e8, m1, ta, ma1245; CHECK-NEXT:    vmerge.vxm v9, v9, a1, v01246; CHECK-NEXT:    vmv.v.i v10, 71247; CHECK-NEXT:    vmulhu.vv v8, v8, v91248; CHECK-NEXT:    vmerge.vim v9, v10, 1, v01249; CHECK-NEXT:    vsrl.vv v8, v8, v91250; CHECK-NEXT:    vse8.v v8, (a0)1251; CHECK-NEXT:    ret1252  %a = load <16 x i8>, ptr %x1253  %b = udiv <16 x i8> %a, <i8 -9, i8 -9, i8 9, i8 -9, i8 9, i8 -9, i8 9, i8 -9, i8 -9, i8 9, i8 -9, i8 9, i8 -9, i8 -9, i8 9, i8 -9>1254  store <16 x i8> %b, ptr %x1255  ret void1256}1257 1258define void @mulhs_v8i16(ptr %x) {1259; CHECK-LABEL: mulhs_v8i16:1260; CHECK:       # %bb.0:1261; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma1262; CHECK-NEXT:    vle16.v v8, (a0)1263; CHECK-NEXT:    li a1, 1051264; CHECK-NEXT:    vmv.s.x v0, a11265; CHECK-NEXT:    lui a1, 51266; CHECK-NEXT:    addi a1, a1, -17551267; CHECK-NEXT:    vmv.v.x v9, a11268; CHECK-NEXT:    lui a1, 10485711269; CHECK-NEXT:    addi a1, a1, 17551270; CHECK-NEXT:    vmerge.vxm v9, v9, a1, v01271; CHECK-NEXT:    vmulh.vv v8, v8, v91272; CHECK-NEXT:    vsra.vi v8, v8, 11273; CHECK-NEXT:    vsrl.vi v9, v8, 151274; CHECK-NEXT:    vadd.vv v8, v8, v91275; CHECK-NEXT:    vse16.v v8, (a0)1276; CHECK-NEXT:    ret1277  %a = load <8 x i16>, ptr %x1278  %b = sdiv <8 x i16> %a, <i16 -7, i16 7, i16 7, i16 -7, i16 7, i16 -7, i16 -7, i16 7>1279  store <8 x i16> %b, ptr %x1280  ret void1281}1282 1283define void @mulhs_v6i16(ptr %x) {1284; CHECK-LABEL: mulhs_v6i16:1285; CHECK:       # %bb.0:1286; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma1287; CHECK-NEXT:    vle16.v v8, (a0)1288; CHECK-NEXT:    li a1, 221289; CHECK-NEXT:    vmv.s.x v0, a11290; CHECK-NEXT:    vmv.v.i v9, -71291; CHECK-NEXT:    vmerge.vim v9, v9, 7, v01292; CHECK-NEXT:    vdiv.vv v8, v8, v91293; CHECK-NEXT:    vse16.v v8, (a0)1294; CHECK-NEXT:    ret1295  %a = load <6 x i16>, ptr %x1296  %b = sdiv <6 x i16> %a, <i16 -7, i16 7, i16 7, i16 -7, i16 7, i16 -7>1297  store <6 x i16> %b, ptr %x1298  ret void1299}1300 1301define void @mulhs_v4i32(ptr %x) {1302; RV32-LABEL: mulhs_v4i32:1303; RV32:       # %bb.0:1304; RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, ma1305; RV32-NEXT:    vle32.v v8, (a0)1306; RV32-NEXT:    lui a1, 4194301307; RV32-NEXT:    vmv.v.i v0, 51308; RV32-NEXT:    addi a1, a1, 16391309; RV32-NEXT:    vmv.v.x v9, a11310; RV32-NEXT:    lui a1, 6291461311; RV32-NEXT:    addi a1, a1, -16391312; RV32-NEXT:    vmerge.vxm v9, v9, a1, v01313; RV32-NEXT:    vmulh.vv v8, v8, v91314; RV32-NEXT:    vsrl.vi v9, v8, 311315; RV32-NEXT:    vsra.vi v8, v8, 11316; RV32-NEXT:    vadd.vv v8, v8, v91317; RV32-NEXT:    vse32.v v8, (a0)1318; RV32-NEXT:    ret1319;1320; RV64-LABEL: mulhs_v4i32:1321; RV64:       # %bb.0:1322; RV64-NEXT:    lui a1, %hi(.LCPI73_0)1323; RV64-NEXT:    ld a1, %lo(.LCPI73_0)(a1)1324; RV64-NEXT:    vsetivli zero, 4, e32, m1, ta, ma1325; RV64-NEXT:    vle32.v v8, (a0)1326; RV64-NEXT:    vsetivli zero, 2, e64, m1, ta, ma1327; RV64-NEXT:    vmv.v.x v9, a11328; RV64-NEXT:    vsetivli zero, 4, e32, m1, ta, ma1329; RV64-NEXT:    vmulh.vv v8, v8, v91330; RV64-NEXT:    vsra.vi v8, v8, 11331; RV64-NEXT:    vsrl.vi v9, v8, 311332; RV64-NEXT:    vadd.vv v8, v8, v91333; RV64-NEXT:    vse32.v v8, (a0)1334; RV64-NEXT:    ret1335  %a = load <4 x i32>, ptr %x1336  %b = sdiv <4 x i32> %a, <i32 -5, i32 5, i32 -5, i32 5>1337  store <4 x i32> %b, ptr %x1338  ret void1339}1340 1341define void @mulhs_v2i64(ptr %x) {1342; RV32-LABEL: mulhs_v2i64:1343; RV32:       # %bb.0:1344; RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, ma1345; RV32-NEXT:    vle64.v v8, (a0)1346; RV32-NEXT:    lui a1, 3495251347; RV32-NEXT:    vid.v v91348; RV32-NEXT:    addi a2, a1, 13651349; RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, ma1350; RV32-NEXT:    vmv.v.x v10, a21351; RV32-NEXT:    li a2, 631352; RV32-NEXT:    addi a1, a1, 13661353; RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, ma1354; RV32-NEXT:    vrsub.vi v11, v9, 01355; RV32-NEXT:    vsetvli zero, zero, e32, mf2, tu, ma1356; RV32-NEXT:    vmv.s.x v10, a11357; RV32-NEXT:    vsetvli zero, zero, e64, m1, ta, ma1358; RV32-NEXT:    vmulh.vv v10, v8, v101359; RV32-NEXT:    vmadd.vv v11, v8, v101360; RV32-NEXT:    vsrl.vx v8, v11, a21361; RV32-NEXT:    vsra.vv v9, v11, v91362; RV32-NEXT:    vadd.vv v8, v9, v81363; RV32-NEXT:    vse64.v v8, (a0)1364; RV32-NEXT:    ret1365;1366; RV64-LABEL: mulhs_v2i64:1367; RV64:       # %bb.0:1368; RV64-NEXT:    vsetivli zero, 2, e64, m1, ta, ma1369; RV64-NEXT:    vle64.v v8, (a0)1370; RV64-NEXT:    lui a1, 3495251371; RV64-NEXT:    addi a1, a1, 13651372; RV64-NEXT:    slli a2, a1, 321373; RV64-NEXT:    add a1, a1, a21374; RV64-NEXT:    lui a2, %hi(.LCPI74_0)1375; RV64-NEXT:    vid.v v91376; RV64-NEXT:    ld a2, %lo(.LCPI74_0)(a2)1377; RV64-NEXT:    vmv.v.x v10, a11378; RV64-NEXT:    li a1, 631379; RV64-NEXT:    vrsub.vi v11, v9, 01380; RV64-NEXT:    vsetvli zero, zero, e64, m1, tu, ma1381; RV64-NEXT:    vmv.s.x v10, a21382; RV64-NEXT:    vsetvli zero, zero, e64, m1, ta, ma1383; RV64-NEXT:    vmulh.vv v10, v8, v101384; RV64-NEXT:    vmadd.vv v11, v8, v101385; RV64-NEXT:    vsrl.vx v8, v11, a11386; RV64-NEXT:    vsra.vv v9, v11, v91387; RV64-NEXT:    vadd.vv v8, v9, v81388; RV64-NEXT:    vse64.v v8, (a0)1389; RV64-NEXT:    ret1390  %a = load <2 x i64>, ptr %x1391  %b = sdiv <2 x i64> %a, <i64 3, i64 -3>1392  store <2 x i64> %b, ptr %x1393  ret void1394}1395 1396define void @smin_v16i8(ptr %x, ptr %y) {1397; CHECK-LABEL: smin_v16i8:1398; CHECK:       # %bb.0:1399; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma1400; CHECK-NEXT:    vle8.v v8, (a0)1401; CHECK-NEXT:    vle8.v v9, (a1)1402; CHECK-NEXT:    vmin.vv v8, v8, v91403; CHECK-NEXT:    vse8.v v8, (a0)1404; CHECK-NEXT:    ret1405  %a = load <16 x i8>, ptr %x1406  %b = load <16 x i8>, ptr %y1407  %cc = icmp slt <16 x i8> %a, %b1408  %c = select <16 x i1> %cc, <16 x i8> %a, <16 x i8> %b1409  store <16 x i8> %c, ptr %x1410  ret void1411}1412 1413define void @smin_v8i16(ptr %x, ptr %y) {1414; CHECK-LABEL: smin_v8i16:1415; CHECK:       # %bb.0:1416; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma1417; CHECK-NEXT:    vle16.v v8, (a0)1418; CHECK-NEXT:    vle16.v v9, (a1)1419; CHECK-NEXT:    vmin.vv v8, v8, v91420; CHECK-NEXT:    vse16.v v8, (a0)1421; CHECK-NEXT:    ret1422  %a = load <8 x i16>, ptr %x1423  %b = load <8 x i16>, ptr %y1424  %cc = icmp slt <8 x i16> %a, %b1425  %c = select <8 x i1> %cc, <8 x i16> %a, <8 x i16> %b1426  store <8 x i16> %c, ptr %x1427  ret void1428}1429 1430define void @smin_v6i16(ptr %x, ptr %y) {1431; CHECK-LABEL: smin_v6i16:1432; CHECK:       # %bb.0:1433; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma1434; CHECK-NEXT:    vle16.v v8, (a0)1435; CHECK-NEXT:    vle16.v v9, (a1)1436; CHECK-NEXT:    vmin.vv v8, v8, v91437; CHECK-NEXT:    vse16.v v8, (a0)1438; CHECK-NEXT:    ret1439  %a = load <6 x i16>, ptr %x1440  %b = load <6 x i16>, ptr %y1441  %cc = icmp slt <6 x i16> %a, %b1442  %c = select <6 x i1> %cc, <6 x i16> %a, <6 x i16> %b1443  store <6 x i16> %c, ptr %x1444  ret void1445}1446 1447define void @smin_v4i32(ptr %x, ptr %y) {1448; CHECK-LABEL: smin_v4i32:1449; CHECK:       # %bb.0:1450; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma1451; CHECK-NEXT:    vle32.v v8, (a0)1452; CHECK-NEXT:    vle32.v v9, (a1)1453; CHECK-NEXT:    vmin.vv v8, v8, v91454; CHECK-NEXT:    vse32.v v8, (a0)1455; CHECK-NEXT:    ret1456  %a = load <4 x i32>, ptr %x1457  %b = load <4 x i32>, ptr %y1458  %cc = icmp slt <4 x i32> %a, %b1459  %c = select <4 x i1> %cc, <4 x i32> %a, <4 x i32> %b1460  store <4 x i32> %c, ptr %x1461  ret void1462}1463 1464define void @smin_v2i64(ptr %x, ptr %y) {1465; CHECK-LABEL: smin_v2i64:1466; CHECK:       # %bb.0:1467; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma1468; CHECK-NEXT:    vle64.v v8, (a0)1469; CHECK-NEXT:    vle64.v v9, (a1)1470; CHECK-NEXT:    vmin.vv v8, v8, v91471; CHECK-NEXT:    vse64.v v8, (a0)1472; CHECK-NEXT:    ret1473  %a = load <2 x i64>, ptr %x1474  %b = load <2 x i64>, ptr %y1475  %cc = icmp slt <2 x i64> %a, %b1476  %c = select <2 x i1> %cc, <2 x i64> %a, <2 x i64> %b1477  store <2 x i64> %c, ptr %x1478  ret void1479}1480 1481define void @smin_vx_v16i8(ptr %x, i8 %y) {1482; CHECK-LABEL: smin_vx_v16i8:1483; CHECK:       # %bb.0:1484; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma1485; CHECK-NEXT:    vle8.v v8, (a0)1486; CHECK-NEXT:    vmin.vx v8, v8, a11487; CHECK-NEXT:    vse8.v v8, (a0)1488; CHECK-NEXT:    ret1489  %a = load <16 x i8>, ptr %x1490  %b = insertelement <16 x i8> poison, i8 %y, i32 01491  %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer1492  %d = call <16 x i8> @llvm.smin.v16i8(<16 x i8> %a, <16 x i8> %c)1493  store <16 x i8> %d, ptr %x1494  ret void1495}1496 1497define void @smin_vx_v8i16(ptr %x, i16 %y) {1498; CHECK-LABEL: smin_vx_v8i16:1499; CHECK:       # %bb.0:1500; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma1501; CHECK-NEXT:    vle16.v v8, (a0)1502; CHECK-NEXT:    vmin.vx v8, v8, a11503; CHECK-NEXT:    vse16.v v8, (a0)1504; CHECK-NEXT:    ret1505  %a = load <8 x i16>, ptr %x1506  %b = insertelement <8 x i16> poison, i16 %y, i32 01507  %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer1508  %d = call <8 x i16> @llvm.smin.v8i16(<8 x i16> %a, <8 x i16> %c)1509  store <8 x i16> %d, ptr %x1510  ret void1511}1512 1513define void @smin_vx_v6i16(ptr %x, i16 %y) {1514; CHECK-LABEL: smin_vx_v6i16:1515; CHECK:       # %bb.0:1516; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma1517; CHECK-NEXT:    vle16.v v8, (a0)1518; CHECK-NEXT:    vmin.vx v8, v8, a11519; CHECK-NEXT:    vse16.v v8, (a0)1520; CHECK-NEXT:    ret1521  %a = load <6 x i16>, ptr %x1522  %b = insertelement <6 x i16> poison, i16 %y, i32 01523  %c = shufflevector <6 x i16> %b, <6 x i16> poison, <6 x i32> zeroinitializer1524  %d = call <6 x i16> @llvm.smin.v6i16(<6 x i16> %a, <6 x i16> %c)1525  store <6 x i16> %d, ptr %x1526  ret void1527}1528 1529define void @smin_vx_v4i32(ptr %x, i32 %y) {1530; CHECK-LABEL: smin_vx_v4i32:1531; CHECK:       # %bb.0:1532; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma1533; CHECK-NEXT:    vle32.v v8, (a0)1534; CHECK-NEXT:    vmin.vx v8, v8, a11535; CHECK-NEXT:    vse32.v v8, (a0)1536; CHECK-NEXT:    ret1537  %a = load <4 x i32>, ptr %x1538  %b = insertelement <4 x i32> poison, i32 %y, i32 01539  %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer1540  %d = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %a, <4 x i32> %c)1541  store <4 x i32> %d, ptr %x1542  ret void1543}1544 1545define void @smin_xv_v16i8(ptr %x, i8 %y) {1546; CHECK-LABEL: smin_xv_v16i8:1547; CHECK:       # %bb.0:1548; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma1549; CHECK-NEXT:    vle8.v v8, (a0)1550; CHECK-NEXT:    vmin.vx v8, v8, a11551; CHECK-NEXT:    vse8.v v8, (a0)1552; CHECK-NEXT:    ret1553  %a = load <16 x i8>, ptr %x1554  %b = insertelement <16 x i8> poison, i8 %y, i32 01555  %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer1556  %d = call <16 x i8> @llvm.smin.v16i8(<16 x i8> %c, <16 x i8> %a)1557  store <16 x i8> %d, ptr %x1558  ret void1559}1560 1561define void @smin_xv_v8i16(ptr %x, i16 %y) {1562; CHECK-LABEL: smin_xv_v8i16:1563; CHECK:       # %bb.0:1564; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma1565; CHECK-NEXT:    vle16.v v8, (a0)1566; CHECK-NEXT:    vmin.vx v8, v8, a11567; CHECK-NEXT:    vse16.v v8, (a0)1568; CHECK-NEXT:    ret1569  %a = load <8 x i16>, ptr %x1570  %b = insertelement <8 x i16> poison, i16 %y, i32 01571  %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer1572  %d = call <8 x i16> @llvm.smin.v8i16(<8 x i16> %c, <8 x i16> %a)1573  store <8 x i16> %d, ptr %x1574  ret void1575}1576 1577define void @smin_xv_v6i16(ptr %x, i16 %y) {1578; CHECK-LABEL: smin_xv_v6i16:1579; CHECK:       # %bb.0:1580; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma1581; CHECK-NEXT:    vle16.v v8, (a0)1582; CHECK-NEXT:    vmin.vx v8, v8, a11583; CHECK-NEXT:    vse16.v v8, (a0)1584; CHECK-NEXT:    ret1585  %a = load <6 x i16>, ptr %x1586  %b = insertelement <6 x i16> poison, i16 %y, i32 01587  %c = shufflevector <6 x i16> %b, <6 x i16> poison, <6 x i32> zeroinitializer1588  %d = call <6 x i16> @llvm.smin.v6i16(<6 x i16> %c, <6 x i16> %a)1589  store <6 x i16> %d, ptr %x1590  ret void1591}1592 1593define void @smin_xv_v4i32(ptr %x, i32 %y) {1594; CHECK-LABEL: smin_xv_v4i32:1595; CHECK:       # %bb.0:1596; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma1597; CHECK-NEXT:    vle32.v v8, (a0)1598; CHECK-NEXT:    vmin.vx v8, v8, a11599; CHECK-NEXT:    vse32.v v8, (a0)1600; CHECK-NEXT:    ret1601  %a = load <4 x i32>, ptr %x1602  %b = insertelement <4 x i32> poison, i32 %y, i32 01603  %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer1604  %d = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %c, <4 x i32> %a)1605  store <4 x i32> %d, ptr %x1606  ret void1607}1608 1609define void @smax_v16i8(ptr %x, ptr %y) {1610; CHECK-LABEL: smax_v16i8:1611; CHECK:       # %bb.0:1612; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma1613; CHECK-NEXT:    vle8.v v8, (a0)1614; CHECK-NEXT:    vle8.v v9, (a1)1615; CHECK-NEXT:    vmax.vv v8, v8, v91616; CHECK-NEXT:    vse8.v v8, (a0)1617; CHECK-NEXT:    ret1618  %a = load <16 x i8>, ptr %x1619  %b = load <16 x i8>, ptr %y1620  %cc = icmp sgt <16 x i8> %a, %b1621  %c = select <16 x i1> %cc, <16 x i8> %a, <16 x i8> %b1622  store <16 x i8> %c, ptr %x1623  ret void1624}1625 1626define void @smax_v8i16(ptr %x, ptr %y) {1627; CHECK-LABEL: smax_v8i16:1628; CHECK:       # %bb.0:1629; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma1630; CHECK-NEXT:    vle16.v v8, (a0)1631; CHECK-NEXT:    vle16.v v9, (a1)1632; CHECK-NEXT:    vmax.vv v8, v8, v91633; CHECK-NEXT:    vse16.v v8, (a0)1634; CHECK-NEXT:    ret1635  %a = load <8 x i16>, ptr %x1636  %b = load <8 x i16>, ptr %y1637  %cc = icmp sgt <8 x i16> %a, %b1638  %c = select <8 x i1> %cc, <8 x i16> %a, <8 x i16> %b1639  store <8 x i16> %c, ptr %x1640  ret void1641}1642 1643define void @smax_v6i16(ptr %x, ptr %y) {1644; CHECK-LABEL: smax_v6i16:1645; CHECK:       # %bb.0:1646; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma1647; CHECK-NEXT:    vle16.v v8, (a0)1648; CHECK-NEXT:    vle16.v v9, (a1)1649; CHECK-NEXT:    vmax.vv v8, v8, v91650; CHECK-NEXT:    vse16.v v8, (a0)1651; CHECK-NEXT:    ret1652  %a = load <6 x i16>, ptr %x1653  %b = load <6 x i16>, ptr %y1654  %cc = icmp sgt <6 x i16> %a, %b1655  %c = select <6 x i1> %cc, <6 x i16> %a, <6 x i16> %b1656  store <6 x i16> %c, ptr %x1657  ret void1658}1659 1660define void @smax_v4i32(ptr %x, ptr %y) {1661; CHECK-LABEL: smax_v4i32:1662; CHECK:       # %bb.0:1663; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma1664; CHECK-NEXT:    vle32.v v8, (a0)1665; CHECK-NEXT:    vle32.v v9, (a1)1666; CHECK-NEXT:    vmax.vv v8, v8, v91667; CHECK-NEXT:    vse32.v v8, (a0)1668; CHECK-NEXT:    ret1669  %a = load <4 x i32>, ptr %x1670  %b = load <4 x i32>, ptr %y1671  %cc = icmp sgt <4 x i32> %a, %b1672  %c = select <4 x i1> %cc, <4 x i32> %a, <4 x i32> %b1673  store <4 x i32> %c, ptr %x1674  ret void1675}1676 1677define void @smax_v2i64(ptr %x, ptr %y) {1678; CHECK-LABEL: smax_v2i64:1679; CHECK:       # %bb.0:1680; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma1681; CHECK-NEXT:    vle64.v v8, (a0)1682; CHECK-NEXT:    vle64.v v9, (a1)1683; CHECK-NEXT:    vmax.vv v8, v8, v91684; CHECK-NEXT:    vse64.v v8, (a0)1685; CHECK-NEXT:    ret1686  %a = load <2 x i64>, ptr %x1687  %b = load <2 x i64>, ptr %y1688  %cc = icmp sgt <2 x i64> %a, %b1689  %c = select <2 x i1> %cc, <2 x i64> %a, <2 x i64> %b1690  store <2 x i64> %c, ptr %x1691  ret void1692}1693 1694define void @smax_vx_v16i8(ptr %x, i8 %y) {1695; CHECK-LABEL: smax_vx_v16i8:1696; CHECK:       # %bb.0:1697; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma1698; CHECK-NEXT:    vle8.v v8, (a0)1699; CHECK-NEXT:    vmax.vx v8, v8, a11700; CHECK-NEXT:    vse8.v v8, (a0)1701; CHECK-NEXT:    ret1702  %a = load <16 x i8>, ptr %x1703  %b = insertelement <16 x i8> poison, i8 %y, i32 01704  %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer1705  %d = call <16 x i8> @llvm.smax.v16i8(<16 x i8> %a, <16 x i8> %c)1706  store <16 x i8> %d, ptr %x1707  ret void1708}1709 1710define void @smax_vx_v8i16(ptr %x, i16 %y) {1711; CHECK-LABEL: smax_vx_v8i16:1712; CHECK:       # %bb.0:1713; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma1714; CHECK-NEXT:    vle16.v v8, (a0)1715; CHECK-NEXT:    vmax.vx v8, v8, a11716; CHECK-NEXT:    vse16.v v8, (a0)1717; CHECK-NEXT:    ret1718  %a = load <8 x i16>, ptr %x1719  %b = insertelement <8 x i16> poison, i16 %y, i32 01720  %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer1721  %d = call <8 x i16> @llvm.smax.v8i16(<8 x i16> %a, <8 x i16> %c)1722  store <8 x i16> %d, ptr %x1723  ret void1724}1725 1726define void @smax_vx_v6i16(ptr %x, i16 %y) {1727; CHECK-LABEL: smax_vx_v6i16:1728; CHECK:       # %bb.0:1729; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma1730; CHECK-NEXT:    vle16.v v8, (a0)1731; CHECK-NEXT:    vmax.vx v8, v8, a11732; CHECK-NEXT:    vse16.v v8, (a0)1733; CHECK-NEXT:    ret1734  %a = load <6 x i16>, ptr %x1735  %b = insertelement <6 x i16> poison, i16 %y, i32 01736  %c = shufflevector <6 x i16> %b, <6 x i16> poison, <6 x i32> zeroinitializer1737  %d = call <6 x i16> @llvm.smax.v6i16(<6 x i16> %a, <6 x i16> %c)1738  store <6 x i16> %d, ptr %x1739  ret void1740}1741 1742define void @smax_vx_v4i32(ptr %x, i32 %y) {1743; CHECK-LABEL: smax_vx_v4i32:1744; CHECK:       # %bb.0:1745; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma1746; CHECK-NEXT:    vle32.v v8, (a0)1747; CHECK-NEXT:    vmax.vx v8, v8, a11748; CHECK-NEXT:    vse32.v v8, (a0)1749; CHECK-NEXT:    ret1750  %a = load <4 x i32>, ptr %x1751  %b = insertelement <4 x i32> poison, i32 %y, i32 01752  %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer1753  %d = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %a, <4 x i32> %c)1754  store <4 x i32> %d, ptr %x1755  ret void1756}1757 1758define void @smax_xv_v16i8(ptr %x, i8 %y) {1759; CHECK-LABEL: smax_xv_v16i8:1760; CHECK:       # %bb.0:1761; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma1762; CHECK-NEXT:    vle8.v v8, (a0)1763; CHECK-NEXT:    vmax.vx v8, v8, a11764; CHECK-NEXT:    vse8.v v8, (a0)1765; CHECK-NEXT:    ret1766  %a = load <16 x i8>, ptr %x1767  %b = insertelement <16 x i8> poison, i8 %y, i32 01768  %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer1769  %d = call <16 x i8> @llvm.smax.v16i8(<16 x i8> %c, <16 x i8> %a)1770  store <16 x i8> %d, ptr %x1771  ret void1772}1773 1774define void @smax_xv_v8i16(ptr %x, i16 %y) {1775; CHECK-LABEL: smax_xv_v8i16:1776; CHECK:       # %bb.0:1777; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma1778; CHECK-NEXT:    vle16.v v8, (a0)1779; CHECK-NEXT:    vmax.vx v8, v8, a11780; CHECK-NEXT:    vse16.v v8, (a0)1781; CHECK-NEXT:    ret1782  %a = load <8 x i16>, ptr %x1783  %b = insertelement <8 x i16> poison, i16 %y, i32 01784  %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer1785  %d = call <8 x i16> @llvm.smax.v8i16(<8 x i16> %c, <8 x i16> %a)1786  store <8 x i16> %d, ptr %x1787  ret void1788}1789 1790define void @smax_xv_v6i16(ptr %x, i16 %y) {1791; CHECK-LABEL: smax_xv_v6i16:1792; CHECK:       # %bb.0:1793; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma1794; CHECK-NEXT:    vle16.v v8, (a0)1795; CHECK-NEXT:    vmax.vx v8, v8, a11796; CHECK-NEXT:    vse16.v v8, (a0)1797; CHECK-NEXT:    ret1798  %a = load <6 x i16>, ptr %x1799  %b = insertelement <6 x i16> poison, i16 %y, i32 01800  %c = shufflevector <6 x i16> %b, <6 x i16> poison, <6 x i32> zeroinitializer1801  %d = call <6 x i16> @llvm.smax.v6i16(<6 x i16> %c, <6 x i16> %a)1802  store <6 x i16> %d, ptr %x1803  ret void1804}1805 1806define void @smax_xv_v4i32(ptr %x, i32 %y) {1807; CHECK-LABEL: smax_xv_v4i32:1808; CHECK:       # %bb.0:1809; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma1810; CHECK-NEXT:    vle32.v v8, (a0)1811; CHECK-NEXT:    vmax.vx v8, v8, a11812; CHECK-NEXT:    vse32.v v8, (a0)1813; CHECK-NEXT:    ret1814  %a = load <4 x i32>, ptr %x1815  %b = insertelement <4 x i32> poison, i32 %y, i32 01816  %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer1817  %d = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %c, <4 x i32> %a)1818  store <4 x i32> %d, ptr %x1819  ret void1820}1821 1822define void @umin_v16i8(ptr %x, ptr %y) {1823; CHECK-LABEL: umin_v16i8:1824; CHECK:       # %bb.0:1825; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma1826; CHECK-NEXT:    vle8.v v8, (a0)1827; CHECK-NEXT:    vle8.v v9, (a1)1828; CHECK-NEXT:    vminu.vv v8, v8, v91829; CHECK-NEXT:    vse8.v v8, (a0)1830; CHECK-NEXT:    ret1831  %a = load <16 x i8>, ptr %x1832  %b = load <16 x i8>, ptr %y1833  %cc = icmp ult <16 x i8> %a, %b1834  %c = select <16 x i1> %cc, <16 x i8> %a, <16 x i8> %b1835  store <16 x i8> %c, ptr %x1836  ret void1837}1838 1839define void @umin_v8i16(ptr %x, ptr %y) {1840; CHECK-LABEL: umin_v8i16:1841; CHECK:       # %bb.0:1842; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma1843; CHECK-NEXT:    vle16.v v8, (a0)1844; CHECK-NEXT:    vle16.v v9, (a1)1845; CHECK-NEXT:    vminu.vv v8, v8, v91846; CHECK-NEXT:    vse16.v v8, (a0)1847; CHECK-NEXT:    ret1848  %a = load <8 x i16>, ptr %x1849  %b = load <8 x i16>, ptr %y1850  %cc = icmp ult <8 x i16> %a, %b1851  %c = select <8 x i1> %cc, <8 x i16> %a, <8 x i16> %b1852  store <8 x i16> %c, ptr %x1853  ret void1854}1855 1856define void @umin_v6i16(ptr %x, ptr %y) {1857; CHECK-LABEL: umin_v6i16:1858; CHECK:       # %bb.0:1859; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma1860; CHECK-NEXT:    vle16.v v8, (a0)1861; CHECK-NEXT:    vle16.v v9, (a1)1862; CHECK-NEXT:    vminu.vv v8, v8, v91863; CHECK-NEXT:    vse16.v v8, (a0)1864; CHECK-NEXT:    ret1865  %a = load <6 x i16>, ptr %x1866  %b = load <6 x i16>, ptr %y1867  %cc = icmp ult <6 x i16> %a, %b1868  %c = select <6 x i1> %cc, <6 x i16> %a, <6 x i16> %b1869  store <6 x i16> %c, ptr %x1870  ret void1871}1872 1873define void @umin_v4i32(ptr %x, ptr %y) {1874; CHECK-LABEL: umin_v4i32:1875; CHECK:       # %bb.0:1876; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma1877; CHECK-NEXT:    vle32.v v8, (a0)1878; CHECK-NEXT:    vle32.v v9, (a1)1879; CHECK-NEXT:    vminu.vv v8, v8, v91880; CHECK-NEXT:    vse32.v v8, (a0)1881; CHECK-NEXT:    ret1882  %a = load <4 x i32>, ptr %x1883  %b = load <4 x i32>, ptr %y1884  %cc = icmp ult <4 x i32> %a, %b1885  %c = select <4 x i1> %cc, <4 x i32> %a, <4 x i32> %b1886  store <4 x i32> %c, ptr %x1887  ret void1888}1889 1890define void @umin_v2i64(ptr %x, ptr %y) {1891; CHECK-LABEL: umin_v2i64:1892; CHECK:       # %bb.0:1893; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma1894; CHECK-NEXT:    vle64.v v8, (a0)1895; CHECK-NEXT:    vle64.v v9, (a1)1896; CHECK-NEXT:    vminu.vv v8, v8, v91897; CHECK-NEXT:    vse64.v v8, (a0)1898; CHECK-NEXT:    ret1899  %a = load <2 x i64>, ptr %x1900  %b = load <2 x i64>, ptr %y1901  %cc = icmp ult <2 x i64> %a, %b1902  %c = select <2 x i1> %cc, <2 x i64> %a, <2 x i64> %b1903  store <2 x i64> %c, ptr %x1904  ret void1905}1906 1907define void @umin_vx_v16i8(ptr %x, i8 %y) {1908; CHECK-LABEL: umin_vx_v16i8:1909; CHECK:       # %bb.0:1910; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma1911; CHECK-NEXT:    vle8.v v8, (a0)1912; CHECK-NEXT:    vminu.vx v8, v8, a11913; CHECK-NEXT:    vse8.v v8, (a0)1914; CHECK-NEXT:    ret1915  %a = load <16 x i8>, ptr %x1916  %b = insertelement <16 x i8> poison, i8 %y, i32 01917  %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer1918  %d = call <16 x i8> @llvm.umin.v16i8(<16 x i8> %a, <16 x i8> %c)1919  store <16 x i8> %d, ptr %x1920  ret void1921}1922 1923define void @umin_vx_v8i16(ptr %x, i16 %y) {1924; CHECK-LABEL: umin_vx_v8i16:1925; CHECK:       # %bb.0:1926; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma1927; CHECK-NEXT:    vle16.v v8, (a0)1928; CHECK-NEXT:    vminu.vx v8, v8, a11929; CHECK-NEXT:    vse16.v v8, (a0)1930; CHECK-NEXT:    ret1931  %a = load <8 x i16>, ptr %x1932  %b = insertelement <8 x i16> poison, i16 %y, i32 01933  %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer1934  %d = call <8 x i16> @llvm.umin.v8i16(<8 x i16> %a, <8 x i16> %c)1935  store <8 x i16> %d, ptr %x1936  ret void1937}1938 1939define void @umin_vx_v6i16(ptr %x, i16 %y) {1940; CHECK-LABEL: umin_vx_v6i16:1941; CHECK:       # %bb.0:1942; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma1943; CHECK-NEXT:    vle16.v v8, (a0)1944; CHECK-NEXT:    vminu.vx v8, v8, a11945; CHECK-NEXT:    vse16.v v8, (a0)1946; CHECK-NEXT:    ret1947  %a = load <6 x i16>, ptr %x1948  %b = insertelement <6 x i16> poison, i16 %y, i32 01949  %c = shufflevector <6 x i16> %b, <6 x i16> poison, <6 x i32> zeroinitializer1950  %d = call <6 x i16> @llvm.umin.v6i16(<6 x i16> %a, <6 x i16> %c)1951  store <6 x i16> %d, ptr %x1952  ret void1953}1954 1955define void @umin_vx_v4i32(ptr %x, i32 %y) {1956; CHECK-LABEL: umin_vx_v4i32:1957; CHECK:       # %bb.0:1958; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma1959; CHECK-NEXT:    vle32.v v8, (a0)1960; CHECK-NEXT:    vminu.vx v8, v8, a11961; CHECK-NEXT:    vse32.v v8, (a0)1962; CHECK-NEXT:    ret1963  %a = load <4 x i32>, ptr %x1964  %b = insertelement <4 x i32> poison, i32 %y, i32 01965  %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer1966  %d = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %a, <4 x i32> %c)1967  store <4 x i32> %d, ptr %x1968  ret void1969}1970 1971define void @umin_xv_v16i8(ptr %x, i8 %y) {1972; CHECK-LABEL: umin_xv_v16i8:1973; CHECK:       # %bb.0:1974; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma1975; CHECK-NEXT:    vle8.v v8, (a0)1976; CHECK-NEXT:    vminu.vx v8, v8, a11977; CHECK-NEXT:    vse8.v v8, (a0)1978; CHECK-NEXT:    ret1979  %a = load <16 x i8>, ptr %x1980  %b = insertelement <16 x i8> poison, i8 %y, i32 01981  %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer1982  %d = call <16 x i8> @llvm.umin.v16i8(<16 x i8> %c, <16 x i8> %a)1983  store <16 x i8> %d, ptr %x1984  ret void1985}1986 1987define void @umin_xv_v8i16(ptr %x, i16 %y) {1988; CHECK-LABEL: umin_xv_v8i16:1989; CHECK:       # %bb.0:1990; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma1991; CHECK-NEXT:    vle16.v v8, (a0)1992; CHECK-NEXT:    vminu.vx v8, v8, a11993; CHECK-NEXT:    vse16.v v8, (a0)1994; CHECK-NEXT:    ret1995  %a = load <8 x i16>, ptr %x1996  %b = insertelement <8 x i16> poison, i16 %y, i32 01997  %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer1998  %d = call <8 x i16> @llvm.umin.v8i16(<8 x i16> %c, <8 x i16> %a)1999  store <8 x i16> %d, ptr %x2000  ret void2001}2002 2003define void @umin_xv_v6i16(ptr %x, i16 %y) {2004; CHECK-LABEL: umin_xv_v6i16:2005; CHECK:       # %bb.0:2006; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma2007; CHECK-NEXT:    vle16.v v8, (a0)2008; CHECK-NEXT:    vminu.vx v8, v8, a12009; CHECK-NEXT:    vse16.v v8, (a0)2010; CHECK-NEXT:    ret2011  %a = load <6 x i16>, ptr %x2012  %b = insertelement <6 x i16> poison, i16 %y, i32 02013  %c = shufflevector <6 x i16> %b, <6 x i16> poison, <6 x i32> zeroinitializer2014  %d = call <6 x i16> @llvm.umin.v6i16(<6 x i16> %c, <6 x i16> %a)2015  store <6 x i16> %d, ptr %x2016  ret void2017}2018 2019define void @umin_xv_v4i32(ptr %x, i32 %y) {2020; CHECK-LABEL: umin_xv_v4i32:2021; CHECK:       # %bb.0:2022; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma2023; CHECK-NEXT:    vle32.v v8, (a0)2024; CHECK-NEXT:    vminu.vx v8, v8, a12025; CHECK-NEXT:    vse32.v v8, (a0)2026; CHECK-NEXT:    ret2027  %a = load <4 x i32>, ptr %x2028  %b = insertelement <4 x i32> poison, i32 %y, i32 02029  %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer2030  %d = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %c, <4 x i32> %a)2031  store <4 x i32> %d, ptr %x2032  ret void2033}2034 2035define void @umax_v16i8(ptr %x, ptr %y) {2036; CHECK-LABEL: umax_v16i8:2037; CHECK:       # %bb.0:2038; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma2039; CHECK-NEXT:    vle8.v v8, (a0)2040; CHECK-NEXT:    vle8.v v9, (a1)2041; CHECK-NEXT:    vmaxu.vv v8, v8, v92042; CHECK-NEXT:    vse8.v v8, (a0)2043; CHECK-NEXT:    ret2044  %a = load <16 x i8>, ptr %x2045  %b = load <16 x i8>, ptr %y2046  %cc = icmp ugt <16 x i8> %a, %b2047  %c = select <16 x i1> %cc, <16 x i8> %a, <16 x i8> %b2048  store <16 x i8> %c, ptr %x2049  ret void2050}2051 2052define void @umax_v8i16(ptr %x, ptr %y) {2053; CHECK-LABEL: umax_v8i16:2054; CHECK:       # %bb.0:2055; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma2056; CHECK-NEXT:    vle16.v v8, (a0)2057; CHECK-NEXT:    vle16.v v9, (a1)2058; CHECK-NEXT:    vmaxu.vv v8, v8, v92059; CHECK-NEXT:    vse16.v v8, (a0)2060; CHECK-NEXT:    ret2061  %a = load <8 x i16>, ptr %x2062  %b = load <8 x i16>, ptr %y2063  %cc = icmp ugt <8 x i16> %a, %b2064  %c = select <8 x i1> %cc, <8 x i16> %a, <8 x i16> %b2065  store <8 x i16> %c, ptr %x2066  ret void2067}2068 2069define void @umax_v6i16(ptr %x, ptr %y) {2070; CHECK-LABEL: umax_v6i16:2071; CHECK:       # %bb.0:2072; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma2073; CHECK-NEXT:    vle16.v v8, (a0)2074; CHECK-NEXT:    vle16.v v9, (a1)2075; CHECK-NEXT:    vmaxu.vv v8, v8, v92076; CHECK-NEXT:    vse16.v v8, (a0)2077; CHECK-NEXT:    ret2078  %a = load <6 x i16>, ptr %x2079  %b = load <6 x i16>, ptr %y2080  %cc = icmp ugt <6 x i16> %a, %b2081  %c = select <6 x i1> %cc, <6 x i16> %a, <6 x i16> %b2082  store <6 x i16> %c, ptr %x2083  ret void2084}2085 2086define void @umax_v4i32(ptr %x, ptr %y) {2087; CHECK-LABEL: umax_v4i32:2088; CHECK:       # %bb.0:2089; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma2090; CHECK-NEXT:    vle32.v v8, (a0)2091; CHECK-NEXT:    vle32.v v9, (a1)2092; CHECK-NEXT:    vmaxu.vv v8, v8, v92093; CHECK-NEXT:    vse32.v v8, (a0)2094; CHECK-NEXT:    ret2095  %a = load <4 x i32>, ptr %x2096  %b = load <4 x i32>, ptr %y2097  %cc = icmp ugt <4 x i32> %a, %b2098  %c = select <4 x i1> %cc, <4 x i32> %a, <4 x i32> %b2099  store <4 x i32> %c, ptr %x2100  ret void2101}2102 2103define void @umax_v2i64(ptr %x, ptr %y) {2104; CHECK-LABEL: umax_v2i64:2105; CHECK:       # %bb.0:2106; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma2107; CHECK-NEXT:    vle64.v v8, (a0)2108; CHECK-NEXT:    vle64.v v9, (a1)2109; CHECK-NEXT:    vmaxu.vv v8, v8, v92110; CHECK-NEXT:    vse64.v v8, (a0)2111; CHECK-NEXT:    ret2112  %a = load <2 x i64>, ptr %x2113  %b = load <2 x i64>, ptr %y2114  %cc = icmp ugt <2 x i64> %a, %b2115  %c = select <2 x i1> %cc, <2 x i64> %a, <2 x i64> %b2116  store <2 x i64> %c, ptr %x2117  ret void2118}2119 2120define void @umax_vx_v16i8(ptr %x, i8 %y) {2121; CHECK-LABEL: umax_vx_v16i8:2122; CHECK:       # %bb.0:2123; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma2124; CHECK-NEXT:    vle8.v v8, (a0)2125; CHECK-NEXT:    vmaxu.vx v8, v8, a12126; CHECK-NEXT:    vse8.v v8, (a0)2127; CHECK-NEXT:    ret2128  %a = load <16 x i8>, ptr %x2129  %b = insertelement <16 x i8> poison, i8 %y, i32 02130  %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer2131  %d = call <16 x i8> @llvm.umax.v16i8(<16 x i8> %a, <16 x i8> %c)2132  store <16 x i8> %d, ptr %x2133  ret void2134}2135 2136define void @umax_vx_v8i16(ptr %x, i16 %y) {2137; CHECK-LABEL: umax_vx_v8i16:2138; CHECK:       # %bb.0:2139; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma2140; CHECK-NEXT:    vle16.v v8, (a0)2141; CHECK-NEXT:    vmaxu.vx v8, v8, a12142; CHECK-NEXT:    vse16.v v8, (a0)2143; CHECK-NEXT:    ret2144  %a = load <8 x i16>, ptr %x2145  %b = insertelement <8 x i16> poison, i16 %y, i32 02146  %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer2147  %d = call <8 x i16> @llvm.umax.v8i16(<8 x i16> %a, <8 x i16> %c)2148  store <8 x i16> %d, ptr %x2149  ret void2150}2151 2152define void @umax_vx_v6i16(ptr %x, i16 %y) {2153; CHECK-LABEL: umax_vx_v6i16:2154; CHECK:       # %bb.0:2155; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma2156; CHECK-NEXT:    vle16.v v8, (a0)2157; CHECK-NEXT:    vmaxu.vx v8, v8, a12158; CHECK-NEXT:    vse16.v v8, (a0)2159; CHECK-NEXT:    ret2160  %a = load <6 x i16>, ptr %x2161  %b = insertelement <6 x i16> poison, i16 %y, i32 02162  %c = shufflevector <6 x i16> %b, <6 x i16> poison, <6 x i32> zeroinitializer2163  %d = call <6 x i16> @llvm.umax.v6i16(<6 x i16> %a, <6 x i16> %c)2164  store <6 x i16> %d, ptr %x2165  ret void2166}2167 2168define void @umax_vx_v4i32(ptr %x, i32 %y) {2169; CHECK-LABEL: umax_vx_v4i32:2170; CHECK:       # %bb.0:2171; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma2172; CHECK-NEXT:    vle32.v v8, (a0)2173; CHECK-NEXT:    vmaxu.vx v8, v8, a12174; CHECK-NEXT:    vse32.v v8, (a0)2175; CHECK-NEXT:    ret2176  %a = load <4 x i32>, ptr %x2177  %b = insertelement <4 x i32> poison, i32 %y, i32 02178  %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer2179  %d = call <4 x i32> @llvm.umax.v4i32(<4 x i32> %a, <4 x i32> %c)2180  store <4 x i32> %d, ptr %x2181  ret void2182}2183 2184define void @umax_xv_v16i8(ptr %x, i8 %y) {2185; CHECK-LABEL: umax_xv_v16i8:2186; CHECK:       # %bb.0:2187; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma2188; CHECK-NEXT:    vle8.v v8, (a0)2189; CHECK-NEXT:    vmaxu.vx v8, v8, a12190; CHECK-NEXT:    vse8.v v8, (a0)2191; CHECK-NEXT:    ret2192  %a = load <16 x i8>, ptr %x2193  %b = insertelement <16 x i8> poison, i8 %y, i32 02194  %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer2195  %d = call <16 x i8> @llvm.umax.v16i8(<16 x i8> %c, <16 x i8> %a)2196  store <16 x i8> %d, ptr %x2197  ret void2198}2199 2200define void @umax_xv_v8i16(ptr %x, i16 %y) {2201; CHECK-LABEL: umax_xv_v8i16:2202; CHECK:       # %bb.0:2203; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma2204; CHECK-NEXT:    vle16.v v8, (a0)2205; CHECK-NEXT:    vmaxu.vx v8, v8, a12206; CHECK-NEXT:    vse16.v v8, (a0)2207; CHECK-NEXT:    ret2208  %a = load <8 x i16>, ptr %x2209  %b = insertelement <8 x i16> poison, i16 %y, i32 02210  %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer2211  %d = call <8 x i16> @llvm.umax.v8i16(<8 x i16> %c, <8 x i16> %a)2212  store <8 x i16> %d, ptr %x2213  ret void2214}2215 2216define void @umax_xv_v6i16(ptr %x, i16 %y) {2217; CHECK-LABEL: umax_xv_v6i16:2218; CHECK:       # %bb.0:2219; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma2220; CHECK-NEXT:    vle16.v v8, (a0)2221; CHECK-NEXT:    vmaxu.vx v8, v8, a12222; CHECK-NEXT:    vse16.v v8, (a0)2223; CHECK-NEXT:    ret2224  %a = load <6 x i16>, ptr %x2225  %b = insertelement <6 x i16> poison, i16 %y, i32 02226  %c = shufflevector <6 x i16> %b, <6 x i16> poison, <6 x i32> zeroinitializer2227  %d = call <6 x i16> @llvm.umax.v6i16(<6 x i16> %c, <6 x i16> %a)2228  store <6 x i16> %d, ptr %x2229  ret void2230}2231 2232define void @umax_xv_v4i32(ptr %x, i32 %y) {2233; CHECK-LABEL: umax_xv_v4i32:2234; CHECK:       # %bb.0:2235; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma2236; CHECK-NEXT:    vle32.v v8, (a0)2237; CHECK-NEXT:    vmaxu.vx v8, v8, a12238; CHECK-NEXT:    vse32.v v8, (a0)2239; CHECK-NEXT:    ret2240  %a = load <4 x i32>, ptr %x2241  %b = insertelement <4 x i32> poison, i32 %y, i32 02242  %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer2243  %d = call <4 x i32> @llvm.umax.v4i32(<4 x i32> %c, <4 x i32> %a)2244  store <4 x i32> %d, ptr %x2245  ret void2246}2247 2248define void @add_v32i8(ptr %x, ptr %y) {2249; CHECK-LABEL: add_v32i8:2250; CHECK:       # %bb.0:2251; CHECK-NEXT:    li a2, 322252; CHECK-NEXT:    vsetvli zero, a2, e8, m2, ta, ma2253; CHECK-NEXT:    vle8.v v8, (a0)2254; CHECK-NEXT:    vle8.v v10, (a1)2255; CHECK-NEXT:    vadd.vv v8, v8, v102256; CHECK-NEXT:    vse8.v v8, (a0)2257; CHECK-NEXT:    ret2258  %a = load <32 x i8>, ptr %x2259  %b = load <32 x i8>, ptr %y2260  %c = add <32 x i8> %a, %b2261  store <32 x i8> %c, ptr %x2262  ret void2263}2264 2265define void @add_v16i16(ptr %x, ptr %y) {2266; CHECK-LABEL: add_v16i16:2267; CHECK:       # %bb.0:2268; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma2269; CHECK-NEXT:    vle16.v v8, (a0)2270; CHECK-NEXT:    vle16.v v10, (a1)2271; CHECK-NEXT:    vadd.vv v8, v8, v102272; CHECK-NEXT:    vse16.v v8, (a0)2273; CHECK-NEXT:    ret2274  %a = load <16 x i16>, ptr %x2275  %b = load <16 x i16>, ptr %y2276  %c = add <16 x i16> %a, %b2277  store <16 x i16> %c, ptr %x2278  ret void2279}2280 2281define void @add_v8i32(ptr %x, ptr %y) {2282; CHECK-LABEL: add_v8i32:2283; CHECK:       # %bb.0:2284; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma2285; CHECK-NEXT:    vle32.v v8, (a0)2286; CHECK-NEXT:    vle32.v v10, (a1)2287; CHECK-NEXT:    vadd.vv v8, v8, v102288; CHECK-NEXT:    vse32.v v8, (a0)2289; CHECK-NEXT:    ret2290  %a = load <8 x i32>, ptr %x2291  %b = load <8 x i32>, ptr %y2292  %c = add <8 x i32> %a, %b2293  store <8 x i32> %c, ptr %x2294  ret void2295}2296 2297define void @add_v6i32(ptr %x, ptr %y) {2298; CHECK-LABEL: add_v6i32:2299; CHECK:       # %bb.0:2300; CHECK-NEXT:    vsetivli zero, 6, e32, m2, ta, ma2301; CHECK-NEXT:    vle32.v v8, (a0)2302; CHECK-NEXT:    vle32.v v10, (a1)2303; CHECK-NEXT:    vadd.vv v8, v8, v102304; CHECK-NEXT:    vse32.v v8, (a0)2305; CHECK-NEXT:    ret2306  %a = load <6 x i32>, ptr %x2307  %b = load <6 x i32>, ptr %y2308  %c = add <6 x i32> %a, %b2309  store <6 x i32> %c, ptr %x2310  ret void2311}2312 2313define void @add_v4i64(ptr %x, ptr %y) {2314; CHECK-LABEL: add_v4i64:2315; CHECK:       # %bb.0:2316; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma2317; CHECK-NEXT:    vle64.v v8, (a0)2318; CHECK-NEXT:    vle64.v v10, (a1)2319; CHECK-NEXT:    vadd.vv v8, v8, v102320; CHECK-NEXT:    vse64.v v8, (a0)2321; CHECK-NEXT:    ret2322  %a = load <4 x i64>, ptr %x2323  %b = load <4 x i64>, ptr %y2324  %c = add <4 x i64> %a, %b2325  store <4 x i64> %c, ptr %x2326  ret void2327}2328 2329define void @sub_v32i8(ptr %x, ptr %y) {2330; CHECK-LABEL: sub_v32i8:2331; CHECK:       # %bb.0:2332; CHECK-NEXT:    li a2, 322333; CHECK-NEXT:    vsetvli zero, a2, e8, m2, ta, ma2334; CHECK-NEXT:    vle8.v v8, (a0)2335; CHECK-NEXT:    vle8.v v10, (a1)2336; CHECK-NEXT:    vsub.vv v8, v8, v102337; CHECK-NEXT:    vse8.v v8, (a0)2338; CHECK-NEXT:    ret2339  %a = load <32 x i8>, ptr %x2340  %b = load <32 x i8>, ptr %y2341  %c = sub <32 x i8> %a, %b2342  store <32 x i8> %c, ptr %x2343  ret void2344}2345 2346define void @sub_v16i16(ptr %x, ptr %y) {2347; CHECK-LABEL: sub_v16i16:2348; CHECK:       # %bb.0:2349; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma2350; CHECK-NEXT:    vle16.v v8, (a0)2351; CHECK-NEXT:    vle16.v v10, (a1)2352; CHECK-NEXT:    vsub.vv v8, v8, v102353; CHECK-NEXT:    vse16.v v8, (a0)2354; CHECK-NEXT:    ret2355  %a = load <16 x i16>, ptr %x2356  %b = load <16 x i16>, ptr %y2357  %c = sub <16 x i16> %a, %b2358  store <16 x i16> %c, ptr %x2359  ret void2360}2361 2362define void @sub_v8i32(ptr %x, ptr %y) {2363; CHECK-LABEL: sub_v8i32:2364; CHECK:       # %bb.0:2365; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma2366; CHECK-NEXT:    vle32.v v8, (a0)2367; CHECK-NEXT:    vle32.v v10, (a1)2368; CHECK-NEXT:    vsub.vv v8, v8, v102369; CHECK-NEXT:    vse32.v v8, (a0)2370; CHECK-NEXT:    ret2371  %a = load <8 x i32>, ptr %x2372  %b = load <8 x i32>, ptr %y2373  %c = sub <8 x i32> %a, %b2374  store <8 x i32> %c, ptr %x2375  ret void2376}2377 2378define void @sub_v4i64(ptr %x, ptr %y) {2379; CHECK-LABEL: sub_v4i64:2380; CHECK:       # %bb.0:2381; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma2382; CHECK-NEXT:    vle64.v v8, (a0)2383; CHECK-NEXT:    vle64.v v10, (a1)2384; CHECK-NEXT:    vsub.vv v8, v8, v102385; CHECK-NEXT:    vse64.v v8, (a0)2386; CHECK-NEXT:    ret2387  %a = load <4 x i64>, ptr %x2388  %b = load <4 x i64>, ptr %y2389  %c = sub <4 x i64> %a, %b2390  store <4 x i64> %c, ptr %x2391  ret void2392}2393 2394define void @mul_v32i8(ptr %x, ptr %y) {2395; CHECK-LABEL: mul_v32i8:2396; CHECK:       # %bb.0:2397; CHECK-NEXT:    li a2, 322398; CHECK-NEXT:    vsetvli zero, a2, e8, m2, ta, ma2399; CHECK-NEXT:    vle8.v v8, (a0)2400; CHECK-NEXT:    vle8.v v10, (a1)2401; CHECK-NEXT:    vmul.vv v8, v8, v102402; CHECK-NEXT:    vse8.v v8, (a0)2403; CHECK-NEXT:    ret2404  %a = load <32 x i8>, ptr %x2405  %b = load <32 x i8>, ptr %y2406  %c = mul <32 x i8> %a, %b2407  store <32 x i8> %c, ptr %x2408  ret void2409}2410 2411define void @mul_v16i16(ptr %x, ptr %y) {2412; CHECK-LABEL: mul_v16i16:2413; CHECK:       # %bb.0:2414; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma2415; CHECK-NEXT:    vle16.v v8, (a0)2416; CHECK-NEXT:    vle16.v v10, (a1)2417; CHECK-NEXT:    vmul.vv v8, v8, v102418; CHECK-NEXT:    vse16.v v8, (a0)2419; CHECK-NEXT:    ret2420  %a = load <16 x i16>, ptr %x2421  %b = load <16 x i16>, ptr %y2422  %c = mul <16 x i16> %a, %b2423  store <16 x i16> %c, ptr %x2424  ret void2425}2426 2427define void @mul_v8i32(ptr %x, ptr %y) {2428; CHECK-LABEL: mul_v8i32:2429; CHECK:       # %bb.0:2430; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma2431; CHECK-NEXT:    vle32.v v8, (a0)2432; CHECK-NEXT:    vle32.v v10, (a1)2433; CHECK-NEXT:    vmul.vv v8, v8, v102434; CHECK-NEXT:    vse32.v v8, (a0)2435; CHECK-NEXT:    ret2436  %a = load <8 x i32>, ptr %x2437  %b = load <8 x i32>, ptr %y2438  %c = mul <8 x i32> %a, %b2439  store <8 x i32> %c, ptr %x2440  ret void2441}2442 2443define void @mul_v4i64(ptr %x, ptr %y) {2444; CHECK-LABEL: mul_v4i64:2445; CHECK:       # %bb.0:2446; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma2447; CHECK-NEXT:    vle64.v v8, (a0)2448; CHECK-NEXT:    vle64.v v10, (a1)2449; CHECK-NEXT:    vmul.vv v8, v8, v102450; CHECK-NEXT:    vse64.v v8, (a0)2451; CHECK-NEXT:    ret2452  %a = load <4 x i64>, ptr %x2453  %b = load <4 x i64>, ptr %y2454  %c = mul <4 x i64> %a, %b2455  store <4 x i64> %c, ptr %x2456  ret void2457}2458 2459define void @and_v32i8(ptr %x, ptr %y) {2460; CHECK-LABEL: and_v32i8:2461; CHECK:       # %bb.0:2462; CHECK-NEXT:    li a2, 322463; CHECK-NEXT:    vsetvli zero, a2, e8, m2, ta, ma2464; CHECK-NEXT:    vle8.v v8, (a0)2465; CHECK-NEXT:    vle8.v v10, (a1)2466; CHECK-NEXT:    vand.vv v8, v8, v102467; CHECK-NEXT:    vse8.v v8, (a0)2468; CHECK-NEXT:    ret2469  %a = load <32 x i8>, ptr %x2470  %b = load <32 x i8>, ptr %y2471  %c = and <32 x i8> %a, %b2472  store <32 x i8> %c, ptr %x2473  ret void2474}2475 2476define void @and_v16i16(ptr %x, ptr %y) {2477; CHECK-LABEL: and_v16i16:2478; CHECK:       # %bb.0:2479; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma2480; CHECK-NEXT:    vle16.v v8, (a0)2481; CHECK-NEXT:    vle16.v v10, (a1)2482; CHECK-NEXT:    vand.vv v8, v8, v102483; CHECK-NEXT:    vse16.v v8, (a0)2484; CHECK-NEXT:    ret2485  %a = load <16 x i16>, ptr %x2486  %b = load <16 x i16>, ptr %y2487  %c = and <16 x i16> %a, %b2488  store <16 x i16> %c, ptr %x2489  ret void2490}2491 2492define void @and_v8i32(ptr %x, ptr %y) {2493; CHECK-LABEL: and_v8i32:2494; CHECK:       # %bb.0:2495; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma2496; CHECK-NEXT:    vle32.v v8, (a0)2497; CHECK-NEXT:    vle32.v v10, (a1)2498; CHECK-NEXT:    vand.vv v8, v8, v102499; CHECK-NEXT:    vse32.v v8, (a0)2500; CHECK-NEXT:    ret2501  %a = load <8 x i32>, ptr %x2502  %b = load <8 x i32>, ptr %y2503  %c = and <8 x i32> %a, %b2504  store <8 x i32> %c, ptr %x2505  ret void2506}2507 2508define void @and_v4i64(ptr %x, ptr %y) {2509; CHECK-LABEL: and_v4i64:2510; CHECK:       # %bb.0:2511; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma2512; CHECK-NEXT:    vle64.v v8, (a0)2513; CHECK-NEXT:    vle64.v v10, (a1)2514; CHECK-NEXT:    vand.vv v8, v8, v102515; CHECK-NEXT:    vse64.v v8, (a0)2516; CHECK-NEXT:    ret2517  %a = load <4 x i64>, ptr %x2518  %b = load <4 x i64>, ptr %y2519  %c = and <4 x i64> %a, %b2520  store <4 x i64> %c, ptr %x2521  ret void2522}2523 2524define void @or_v32i8(ptr %x, ptr %y) {2525; CHECK-LABEL: or_v32i8:2526; CHECK:       # %bb.0:2527; CHECK-NEXT:    li a2, 322528; CHECK-NEXT:    vsetvli zero, a2, e8, m2, ta, ma2529; CHECK-NEXT:    vle8.v v8, (a0)2530; CHECK-NEXT:    vle8.v v10, (a1)2531; CHECK-NEXT:    vor.vv v8, v8, v102532; CHECK-NEXT:    vse8.v v8, (a0)2533; CHECK-NEXT:    ret2534  %a = load <32 x i8>, ptr %x2535  %b = load <32 x i8>, ptr %y2536  %c = or <32 x i8> %a, %b2537  store <32 x i8> %c, ptr %x2538  ret void2539}2540 2541define void @or_v16i16(ptr %x, ptr %y) {2542; CHECK-LABEL: or_v16i16:2543; CHECK:       # %bb.0:2544; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma2545; CHECK-NEXT:    vle16.v v8, (a0)2546; CHECK-NEXT:    vle16.v v10, (a1)2547; CHECK-NEXT:    vor.vv v8, v8, v102548; CHECK-NEXT:    vse16.v v8, (a0)2549; CHECK-NEXT:    ret2550  %a = load <16 x i16>, ptr %x2551  %b = load <16 x i16>, ptr %y2552  %c = or <16 x i16> %a, %b2553  store <16 x i16> %c, ptr %x2554  ret void2555}2556 2557define void @or_v8i32(ptr %x, ptr %y) {2558; CHECK-LABEL: or_v8i32:2559; CHECK:       # %bb.0:2560; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma2561; CHECK-NEXT:    vle32.v v8, (a0)2562; CHECK-NEXT:    vle32.v v10, (a1)2563; CHECK-NEXT:    vor.vv v8, v8, v102564; CHECK-NEXT:    vse32.v v8, (a0)2565; CHECK-NEXT:    ret2566  %a = load <8 x i32>, ptr %x2567  %b = load <8 x i32>, ptr %y2568  %c = or <8 x i32> %a, %b2569  store <8 x i32> %c, ptr %x2570  ret void2571}2572 2573define void @or_v4i64(ptr %x, ptr %y) {2574; CHECK-LABEL: or_v4i64:2575; CHECK:       # %bb.0:2576; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma2577; CHECK-NEXT:    vle64.v v8, (a0)2578; CHECK-NEXT:    vle64.v v10, (a1)2579; CHECK-NEXT:    vor.vv v8, v8, v102580; CHECK-NEXT:    vse64.v v8, (a0)2581; CHECK-NEXT:    ret2582  %a = load <4 x i64>, ptr %x2583  %b = load <4 x i64>, ptr %y2584  %c = or <4 x i64> %a, %b2585  store <4 x i64> %c, ptr %x2586  ret void2587}2588 2589define void @xor_v32i8(ptr %x, ptr %y) {2590; CHECK-LABEL: xor_v32i8:2591; CHECK:       # %bb.0:2592; CHECK-NEXT:    li a2, 322593; CHECK-NEXT:    vsetvli zero, a2, e8, m2, ta, ma2594; CHECK-NEXT:    vle8.v v8, (a0)2595; CHECK-NEXT:    vle8.v v10, (a1)2596; CHECK-NEXT:    vxor.vv v8, v8, v102597; CHECK-NEXT:    vse8.v v8, (a0)2598; CHECK-NEXT:    ret2599  %a = load <32 x i8>, ptr %x2600  %b = load <32 x i8>, ptr %y2601  %c = xor <32 x i8> %a, %b2602  store <32 x i8> %c, ptr %x2603  ret void2604}2605 2606define void @xor_v16i16(ptr %x, ptr %y) {2607; CHECK-LABEL: xor_v16i16:2608; CHECK:       # %bb.0:2609; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma2610; CHECK-NEXT:    vle16.v v8, (a0)2611; CHECK-NEXT:    vle16.v v10, (a1)2612; CHECK-NEXT:    vxor.vv v8, v8, v102613; CHECK-NEXT:    vse16.v v8, (a0)2614; CHECK-NEXT:    ret2615  %a = load <16 x i16>, ptr %x2616  %b = load <16 x i16>, ptr %y2617  %c = xor <16 x i16> %a, %b2618  store <16 x i16> %c, ptr %x2619  ret void2620}2621 2622define void @xor_v8i32(ptr %x, ptr %y) {2623; CHECK-LABEL: xor_v8i32:2624; CHECK:       # %bb.0:2625; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma2626; CHECK-NEXT:    vle32.v v8, (a0)2627; CHECK-NEXT:    vle32.v v10, (a1)2628; CHECK-NEXT:    vxor.vv v8, v8, v102629; CHECK-NEXT:    vse32.v v8, (a0)2630; CHECK-NEXT:    ret2631  %a = load <8 x i32>, ptr %x2632  %b = load <8 x i32>, ptr %y2633  %c = xor <8 x i32> %a, %b2634  store <8 x i32> %c, ptr %x2635  ret void2636}2637 2638define void @xor_v4i64(ptr %x, ptr %y) {2639; CHECK-LABEL: xor_v4i64:2640; CHECK:       # %bb.0:2641; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma2642; CHECK-NEXT:    vle64.v v8, (a0)2643; CHECK-NEXT:    vle64.v v10, (a1)2644; CHECK-NEXT:    vxor.vv v8, v8, v102645; CHECK-NEXT:    vse64.v v8, (a0)2646; CHECK-NEXT:    ret2647  %a = load <4 x i64>, ptr %x2648  %b = load <4 x i64>, ptr %y2649  %c = xor <4 x i64> %a, %b2650  store <4 x i64> %c, ptr %x2651  ret void2652}2653 2654define void @lshr_v32i8(ptr %x, ptr %y) {2655; CHECK-LABEL: lshr_v32i8:2656; CHECK:       # %bb.0:2657; CHECK-NEXT:    li a2, 322658; CHECK-NEXT:    vsetvli zero, a2, e8, m2, ta, ma2659; CHECK-NEXT:    vle8.v v8, (a0)2660; CHECK-NEXT:    vle8.v v10, (a1)2661; CHECK-NEXT:    vsrl.vv v8, v8, v102662; CHECK-NEXT:    vse8.v v8, (a0)2663; CHECK-NEXT:    ret2664  %a = load <32 x i8>, ptr %x2665  %b = load <32 x i8>, ptr %y2666  %c = lshr <32 x i8> %a, %b2667  store <32 x i8> %c, ptr %x2668  ret void2669}2670 2671define void @lshr_v16i16(ptr %x, ptr %y) {2672; CHECK-LABEL: lshr_v16i16:2673; CHECK:       # %bb.0:2674; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma2675; CHECK-NEXT:    vle16.v v8, (a0)2676; CHECK-NEXT:    vle16.v v10, (a1)2677; CHECK-NEXT:    vsrl.vv v8, v8, v102678; CHECK-NEXT:    vse16.v v8, (a0)2679; CHECK-NEXT:    ret2680  %a = load <16 x i16>, ptr %x2681  %b = load <16 x i16>, ptr %y2682  %c = lshr <16 x i16> %a, %b2683  store <16 x i16> %c, ptr %x2684  ret void2685}2686 2687define void @lshr_v8i32(ptr %x, ptr %y) {2688; CHECK-LABEL: lshr_v8i32:2689; CHECK:       # %bb.0:2690; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma2691; CHECK-NEXT:    vle32.v v8, (a0)2692; CHECK-NEXT:    vle32.v v10, (a1)2693; CHECK-NEXT:    vsrl.vv v8, v8, v102694; CHECK-NEXT:    vse32.v v8, (a0)2695; CHECK-NEXT:    ret2696  %a = load <8 x i32>, ptr %x2697  %b = load <8 x i32>, ptr %y2698  %c = lshr <8 x i32> %a, %b2699  store <8 x i32> %c, ptr %x2700  ret void2701}2702 2703define void @lshr_v4i64(ptr %x, ptr %y) {2704; CHECK-LABEL: lshr_v4i64:2705; CHECK:       # %bb.0:2706; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma2707; CHECK-NEXT:    vle64.v v8, (a0)2708; CHECK-NEXT:    vle64.v v10, (a1)2709; CHECK-NEXT:    vsrl.vv v8, v8, v102710; CHECK-NEXT:    vse64.v v8, (a0)2711; CHECK-NEXT:    ret2712  %a = load <4 x i64>, ptr %x2713  %b = load <4 x i64>, ptr %y2714  %c = lshr <4 x i64> %a, %b2715  store <4 x i64> %c, ptr %x2716  ret void2717}2718 2719define void @ashr_v32i8(ptr %x, ptr %y) {2720; CHECK-LABEL: ashr_v32i8:2721; CHECK:       # %bb.0:2722; CHECK-NEXT:    li a2, 322723; CHECK-NEXT:    vsetvli zero, a2, e8, m2, ta, ma2724; CHECK-NEXT:    vle8.v v8, (a0)2725; CHECK-NEXT:    vle8.v v10, (a1)2726; CHECK-NEXT:    vsra.vv v8, v8, v102727; CHECK-NEXT:    vse8.v v8, (a0)2728; CHECK-NEXT:    ret2729  %a = load <32 x i8>, ptr %x2730  %b = load <32 x i8>, ptr %y2731  %c = ashr <32 x i8> %a, %b2732  store <32 x i8> %c, ptr %x2733  ret void2734}2735 2736define void @ashr_v16i16(ptr %x, ptr %y) {2737; CHECK-LABEL: ashr_v16i16:2738; CHECK:       # %bb.0:2739; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma2740; CHECK-NEXT:    vle16.v v8, (a0)2741; CHECK-NEXT:    vle16.v v10, (a1)2742; CHECK-NEXT:    vsra.vv v8, v8, v102743; CHECK-NEXT:    vse16.v v8, (a0)2744; CHECK-NEXT:    ret2745  %a = load <16 x i16>, ptr %x2746  %b = load <16 x i16>, ptr %y2747  %c = ashr <16 x i16> %a, %b2748  store <16 x i16> %c, ptr %x2749  ret void2750}2751 2752define void @ashr_v8i32(ptr %x, ptr %y) {2753; CHECK-LABEL: ashr_v8i32:2754; CHECK:       # %bb.0:2755; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma2756; CHECK-NEXT:    vle32.v v8, (a0)2757; CHECK-NEXT:    vle32.v v10, (a1)2758; CHECK-NEXT:    vsra.vv v8, v8, v102759; CHECK-NEXT:    vse32.v v8, (a0)2760; CHECK-NEXT:    ret2761  %a = load <8 x i32>, ptr %x2762  %b = load <8 x i32>, ptr %y2763  %c = ashr <8 x i32> %a, %b2764  store <8 x i32> %c, ptr %x2765  ret void2766}2767 2768define void @ashr_v4i64(ptr %x, ptr %y) {2769; CHECK-LABEL: ashr_v4i64:2770; CHECK:       # %bb.0:2771; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma2772; CHECK-NEXT:    vle64.v v8, (a0)2773; CHECK-NEXT:    vle64.v v10, (a1)2774; CHECK-NEXT:    vsra.vv v8, v8, v102775; CHECK-NEXT:    vse64.v v8, (a0)2776; CHECK-NEXT:    ret2777  %a = load <4 x i64>, ptr %x2778  %b = load <4 x i64>, ptr %y2779  %c = ashr <4 x i64> %a, %b2780  store <4 x i64> %c, ptr %x2781  ret void2782}2783 2784define void @shl_v32i8(ptr %x, ptr %y) {2785; CHECK-LABEL: shl_v32i8:2786; CHECK:       # %bb.0:2787; CHECK-NEXT:    li a2, 322788; CHECK-NEXT:    vsetvli zero, a2, e8, m2, ta, ma2789; CHECK-NEXT:    vle8.v v8, (a0)2790; CHECK-NEXT:    vle8.v v10, (a1)2791; CHECK-NEXT:    vsll.vv v8, v8, v102792; CHECK-NEXT:    vse8.v v8, (a0)2793; CHECK-NEXT:    ret2794  %a = load <32 x i8>, ptr %x2795  %b = load <32 x i8>, ptr %y2796  %c = shl <32 x i8> %a, %b2797  store <32 x i8> %c, ptr %x2798  ret void2799}2800 2801define void @shl_v16i16(ptr %x, ptr %y) {2802; CHECK-LABEL: shl_v16i16:2803; CHECK:       # %bb.0:2804; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma2805; CHECK-NEXT:    vle16.v v8, (a0)2806; CHECK-NEXT:    vle16.v v10, (a1)2807; CHECK-NEXT:    vsll.vv v8, v8, v102808; CHECK-NEXT:    vse16.v v8, (a0)2809; CHECK-NEXT:    ret2810  %a = load <16 x i16>, ptr %x2811  %b = load <16 x i16>, ptr %y2812  %c = shl <16 x i16> %a, %b2813  store <16 x i16> %c, ptr %x2814  ret void2815}2816 2817define void @shl_v8i32(ptr %x, ptr %y) {2818; CHECK-LABEL: shl_v8i32:2819; CHECK:       # %bb.0:2820; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma2821; CHECK-NEXT:    vle32.v v8, (a0)2822; CHECK-NEXT:    vle32.v v10, (a1)2823; CHECK-NEXT:    vsll.vv v8, v8, v102824; CHECK-NEXT:    vse32.v v8, (a0)2825; CHECK-NEXT:    ret2826  %a = load <8 x i32>, ptr %x2827  %b = load <8 x i32>, ptr %y2828  %c = shl <8 x i32> %a, %b2829  store <8 x i32> %c, ptr %x2830  ret void2831}2832 2833define void @shl_v4i64(ptr %x, ptr %y) {2834; CHECK-LABEL: shl_v4i64:2835; CHECK:       # %bb.0:2836; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma2837; CHECK-NEXT:    vle64.v v8, (a0)2838; CHECK-NEXT:    vle64.v v10, (a1)2839; CHECK-NEXT:    vsll.vv v8, v8, v102840; CHECK-NEXT:    vse64.v v8, (a0)2841; CHECK-NEXT:    ret2842  %a = load <4 x i64>, ptr %x2843  %b = load <4 x i64>, ptr %y2844  %c = shl <4 x i64> %a, %b2845  store <4 x i64> %c, ptr %x2846  ret void2847}2848 2849define void @sdiv_v32i8(ptr %x, ptr %y) {2850; CHECK-LABEL: sdiv_v32i8:2851; CHECK:       # %bb.0:2852; CHECK-NEXT:    li a2, 322853; CHECK-NEXT:    vsetvli zero, a2, e8, m2, ta, ma2854; CHECK-NEXT:    vle8.v v8, (a0)2855; CHECK-NEXT:    vle8.v v10, (a1)2856; CHECK-NEXT:    vdiv.vv v8, v8, v102857; CHECK-NEXT:    vse8.v v8, (a0)2858; CHECK-NEXT:    ret2859  %a = load <32 x i8>, ptr %x2860  %b = load <32 x i8>, ptr %y2861  %c = sdiv <32 x i8> %a, %b2862  store <32 x i8> %c, ptr %x2863  ret void2864}2865 2866define void @sdiv_v16i16(ptr %x, ptr %y) {2867; CHECK-LABEL: sdiv_v16i16:2868; CHECK:       # %bb.0:2869; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma2870; CHECK-NEXT:    vle16.v v8, (a0)2871; CHECK-NEXT:    vle16.v v10, (a1)2872; CHECK-NEXT:    vdiv.vv v8, v8, v102873; CHECK-NEXT:    vse16.v v8, (a0)2874; CHECK-NEXT:    ret2875  %a = load <16 x i16>, ptr %x2876  %b = load <16 x i16>, ptr %y2877  %c = sdiv <16 x i16> %a, %b2878  store <16 x i16> %c, ptr %x2879  ret void2880}2881 2882define void @sdiv_v8i32(ptr %x, ptr %y) {2883; CHECK-LABEL: sdiv_v8i32:2884; CHECK:       # %bb.0:2885; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma2886; CHECK-NEXT:    vle32.v v8, (a0)2887; CHECK-NEXT:    vle32.v v10, (a1)2888; CHECK-NEXT:    vdiv.vv v8, v8, v102889; CHECK-NEXT:    vse32.v v8, (a0)2890; CHECK-NEXT:    ret2891  %a = load <8 x i32>, ptr %x2892  %b = load <8 x i32>, ptr %y2893  %c = sdiv <8 x i32> %a, %b2894  store <8 x i32> %c, ptr %x2895  ret void2896}2897 2898define void @sdiv_v4i64(ptr %x, ptr %y) {2899; CHECK-LABEL: sdiv_v4i64:2900; CHECK:       # %bb.0:2901; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma2902; CHECK-NEXT:    vle64.v v8, (a0)2903; CHECK-NEXT:    vle64.v v10, (a1)2904; CHECK-NEXT:    vdiv.vv v8, v8, v102905; CHECK-NEXT:    vse64.v v8, (a0)2906; CHECK-NEXT:    ret2907  %a = load <4 x i64>, ptr %x2908  %b = load <4 x i64>, ptr %y2909  %c = sdiv <4 x i64> %a, %b2910  store <4 x i64> %c, ptr %x2911  ret void2912}2913 2914define void @srem_v32i8(ptr %x, ptr %y) {2915; CHECK-LABEL: srem_v32i8:2916; CHECK:       # %bb.0:2917; CHECK-NEXT:    li a2, 322918; CHECK-NEXT:    vsetvli zero, a2, e8, m2, ta, ma2919; CHECK-NEXT:    vle8.v v8, (a0)2920; CHECK-NEXT:    vle8.v v10, (a1)2921; CHECK-NEXT:    vrem.vv v8, v8, v102922; CHECK-NEXT:    vse8.v v8, (a0)2923; CHECK-NEXT:    ret2924  %a = load <32 x i8>, ptr %x2925  %b = load <32 x i8>, ptr %y2926  %c = srem <32 x i8> %a, %b2927  store <32 x i8> %c, ptr %x2928  ret void2929}2930 2931define void @srem_v16i16(ptr %x, ptr %y) {2932; CHECK-LABEL: srem_v16i16:2933; CHECK:       # %bb.0:2934; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma2935; CHECK-NEXT:    vle16.v v8, (a0)2936; CHECK-NEXT:    vle16.v v10, (a1)2937; CHECK-NEXT:    vrem.vv v8, v8, v102938; CHECK-NEXT:    vse16.v v8, (a0)2939; CHECK-NEXT:    ret2940  %a = load <16 x i16>, ptr %x2941  %b = load <16 x i16>, ptr %y2942  %c = srem <16 x i16> %a, %b2943  store <16 x i16> %c, ptr %x2944  ret void2945}2946 2947define void @srem_v8i32(ptr %x, ptr %y) {2948; CHECK-LABEL: srem_v8i32:2949; CHECK:       # %bb.0:2950; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma2951; CHECK-NEXT:    vle32.v v8, (a0)2952; CHECK-NEXT:    vle32.v v10, (a1)2953; CHECK-NEXT:    vrem.vv v8, v8, v102954; CHECK-NEXT:    vse32.v v8, (a0)2955; CHECK-NEXT:    ret2956  %a = load <8 x i32>, ptr %x2957  %b = load <8 x i32>, ptr %y2958  %c = srem <8 x i32> %a, %b2959  store <8 x i32> %c, ptr %x2960  ret void2961}2962 2963define void @srem_v4i64(ptr %x, ptr %y) {2964; CHECK-LABEL: srem_v4i64:2965; CHECK:       # %bb.0:2966; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma2967; CHECK-NEXT:    vle64.v v8, (a0)2968; CHECK-NEXT:    vle64.v v10, (a1)2969; CHECK-NEXT:    vrem.vv v8, v8, v102970; CHECK-NEXT:    vse64.v v8, (a0)2971; CHECK-NEXT:    ret2972  %a = load <4 x i64>, ptr %x2973  %b = load <4 x i64>, ptr %y2974  %c = srem <4 x i64> %a, %b2975  store <4 x i64> %c, ptr %x2976  ret void2977}2978 2979define void @udiv_v32i8(ptr %x, ptr %y) {2980; CHECK-LABEL: udiv_v32i8:2981; CHECK:       # %bb.0:2982; CHECK-NEXT:    li a2, 322983; CHECK-NEXT:    vsetvli zero, a2, e8, m2, ta, ma2984; CHECK-NEXT:    vle8.v v8, (a0)2985; CHECK-NEXT:    vle8.v v10, (a1)2986; CHECK-NEXT:    vdivu.vv v8, v8, v102987; CHECK-NEXT:    vse8.v v8, (a0)2988; CHECK-NEXT:    ret2989  %a = load <32 x i8>, ptr %x2990  %b = load <32 x i8>, ptr %y2991  %c = udiv <32 x i8> %a, %b2992  store <32 x i8> %c, ptr %x2993  ret void2994}2995 2996define void @udiv_v16i16(ptr %x, ptr %y) {2997; CHECK-LABEL: udiv_v16i16:2998; CHECK:       # %bb.0:2999; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma3000; CHECK-NEXT:    vle16.v v8, (a0)3001; CHECK-NEXT:    vle16.v v10, (a1)3002; CHECK-NEXT:    vdivu.vv v8, v8, v103003; CHECK-NEXT:    vse16.v v8, (a0)3004; CHECK-NEXT:    ret3005  %a = load <16 x i16>, ptr %x3006  %b = load <16 x i16>, ptr %y3007  %c = udiv <16 x i16> %a, %b3008  store <16 x i16> %c, ptr %x3009  ret void3010}3011 3012define void @udiv_v8i32(ptr %x, ptr %y) {3013; CHECK-LABEL: udiv_v8i32:3014; CHECK:       # %bb.0:3015; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma3016; CHECK-NEXT:    vle32.v v8, (a0)3017; CHECK-NEXT:    vle32.v v10, (a1)3018; CHECK-NEXT:    vdivu.vv v8, v8, v103019; CHECK-NEXT:    vse32.v v8, (a0)3020; CHECK-NEXT:    ret3021  %a = load <8 x i32>, ptr %x3022  %b = load <8 x i32>, ptr %y3023  %c = udiv <8 x i32> %a, %b3024  store <8 x i32> %c, ptr %x3025  ret void3026}3027 3028define void @udiv_v4i64(ptr %x, ptr %y) {3029; CHECK-LABEL: udiv_v4i64:3030; CHECK:       # %bb.0:3031; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma3032; CHECK-NEXT:    vle64.v v8, (a0)3033; CHECK-NEXT:    vle64.v v10, (a1)3034; CHECK-NEXT:    vdivu.vv v8, v8, v103035; CHECK-NEXT:    vse64.v v8, (a0)3036; CHECK-NEXT:    ret3037  %a = load <4 x i64>, ptr %x3038  %b = load <4 x i64>, ptr %y3039  %c = udiv <4 x i64> %a, %b3040  store <4 x i64> %c, ptr %x3041  ret void3042}3043 3044define void @urem_v32i8(ptr %x, ptr %y) {3045; CHECK-LABEL: urem_v32i8:3046; CHECK:       # %bb.0:3047; CHECK-NEXT:    li a2, 323048; CHECK-NEXT:    vsetvli zero, a2, e8, m2, ta, ma3049; CHECK-NEXT:    vle8.v v8, (a0)3050; CHECK-NEXT:    vle8.v v10, (a1)3051; CHECK-NEXT:    vremu.vv v8, v8, v103052; CHECK-NEXT:    vse8.v v8, (a0)3053; CHECK-NEXT:    ret3054  %a = load <32 x i8>, ptr %x3055  %b = load <32 x i8>, ptr %y3056  %c = urem <32 x i8> %a, %b3057  store <32 x i8> %c, ptr %x3058  ret void3059}3060 3061define void @urem_v16i16(ptr %x, ptr %y) {3062; CHECK-LABEL: urem_v16i16:3063; CHECK:       # %bb.0:3064; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma3065; CHECK-NEXT:    vle16.v v8, (a0)3066; CHECK-NEXT:    vle16.v v10, (a1)3067; CHECK-NEXT:    vremu.vv v8, v8, v103068; CHECK-NEXT:    vse16.v v8, (a0)3069; CHECK-NEXT:    ret3070  %a = load <16 x i16>, ptr %x3071  %b = load <16 x i16>, ptr %y3072  %c = urem <16 x i16> %a, %b3073  store <16 x i16> %c, ptr %x3074  ret void3075}3076 3077define void @urem_v8i32(ptr %x, ptr %y) {3078; CHECK-LABEL: urem_v8i32:3079; CHECK:       # %bb.0:3080; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma3081; CHECK-NEXT:    vle32.v v8, (a0)3082; CHECK-NEXT:    vle32.v v10, (a1)3083; CHECK-NEXT:    vremu.vv v8, v8, v103084; CHECK-NEXT:    vse32.v v8, (a0)3085; CHECK-NEXT:    ret3086  %a = load <8 x i32>, ptr %x3087  %b = load <8 x i32>, ptr %y3088  %c = urem <8 x i32> %a, %b3089  store <8 x i32> %c, ptr %x3090  ret void3091}3092 3093define void @urem_v4i64(ptr %x, ptr %y) {3094; CHECK-LABEL: urem_v4i64:3095; CHECK:       # %bb.0:3096; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma3097; CHECK-NEXT:    vle64.v v8, (a0)3098; CHECK-NEXT:    vle64.v v10, (a1)3099; CHECK-NEXT:    vremu.vv v8, v8, v103100; CHECK-NEXT:    vse64.v v8, (a0)3101; CHECK-NEXT:    ret3102  %a = load <4 x i64>, ptr %x3103  %b = load <4 x i64>, ptr %y3104  %c = urem <4 x i64> %a, %b3105  store <4 x i64> %c, ptr %x3106  ret void3107}3108 3109define void @extract_v4i64(ptr %x, ptr %y) {3110; CHECK-LABEL: extract_v4i64:3111; CHECK:       # %bb.0:3112; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma3113; CHECK-NEXT:    vle64.v v8, (a0)3114; CHECK-NEXT:    vle64.v v10, (a1)3115; CHECK-NEXT:    vadd.vv v8, v8, v103116; CHECK-NEXT:    vse64.v v8, (a0)3117; CHECK-NEXT:    ret3118  %a = load <4 x i64>, ptr %x3119  %b = load <4 x i64>, ptr %y3120  br label %"compute"3121"compute":3122  %c = add <4 x i64> %a, %b3123  store <4 x i64> %c, ptr %x3124  ret void3125}3126 3127define void @mulhu_v32i8(ptr %x) {3128; CHECK-LABEL: mulhu_v32i8:3129; CHECK:       # %bb.0:3130; CHECK-NEXT:    li a1, 323131; CHECK-NEXT:    lui a2, %hi(.LCPI181_0)3132; CHECK-NEXT:    addi a2, a2, %lo(.LCPI181_0)3133; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma3134; CHECK-NEXT:    vle8.v v8, (a2)3135; CHECK-NEXT:    lui a1, 1639073136; CHECK-NEXT:    addi a1, a1, -20443137; CHECK-NEXT:    vmv.s.x v0, a13138; CHECK-NEXT:    li a1, -1283139; CHECK-NEXT:    vsetvli zero, zero, e8, m2, ta, ma3140; CHECK-NEXT:    vmv.v.i v10, 03141; CHECK-NEXT:    vmerge.vxm v12, v10, a1, v03142; CHECK-NEXT:    lui a1, 660493143; CHECK-NEXT:    addi a1, a1, 323144; CHECK-NEXT:    vsetvli zero, zero, e32, m8, ta, ma3145; CHECK-NEXT:    vmv.s.x v0, a13146; CHECK-NEXT:    lui a1, 82083147; CHECK-NEXT:    vle8.v v14, (a0)3148; CHECK-NEXT:    addi a1, a1, 5133149; CHECK-NEXT:    vsetvli zero, zero, e8, m2, ta, ma3150; CHECK-NEXT:    vmerge.vim v10, v10, 1, v03151; CHECK-NEXT:    vsetvli zero, zero, e32, m8, ta, ma3152; CHECK-NEXT:    vmv.s.x v0, a13153; CHECK-NEXT:    lui a1, 667853154; CHECK-NEXT:    vsetvli zero, zero, e8, m2, ta, ma3155; CHECK-NEXT:    vmv.v.i v16, 43156; CHECK-NEXT:    addi a1, a1, 783157; CHECK-NEXT:    vsrl.vv v10, v14, v103158; CHECK-NEXT:    vmerge.vim v16, v16, 1, v03159; CHECK-NEXT:    vsetvli zero, zero, e32, m8, ta, ma3160; CHECK-NEXT:    vmv.s.x v0, a13161; CHECK-NEXT:    vsetvli zero, zero, e8, m2, ta, ma3162; CHECK-NEXT:    vmulhu.vv v8, v10, v83163; CHECK-NEXT:    vmerge.vim v10, v16, 3, v03164; CHECK-NEXT:    lui a1, 5291603165; CHECK-NEXT:    addi a1, a1, 3043166; CHECK-NEXT:    vsub.vv v14, v14, v83167; CHECK-NEXT:    vmulhu.vv v12, v14, v123168; CHECK-NEXT:    vsetvli zero, zero, e32, m8, ta, ma3169; CHECK-NEXT:    vmv.s.x v0, a13170; CHECK-NEXT:    vsetvli zero, zero, e8, m2, ta, ma3171; CHECK-NEXT:    vadd.vv v8, v12, v83172; CHECK-NEXT:    vmerge.vim v10, v10, 2, v03173; CHECK-NEXT:    vsrl.vv v8, v8, v103174; CHECK-NEXT:    vse8.v v8, (a0)3175; CHECK-NEXT:    ret3176  %a = load <32 x i8>, ptr %x3177  %b = udiv <32 x i8> %a, <i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25>3178  store <32 x i8> %b, ptr %x3179  ret void3180}3181 3182define void @mulhu_v16i16(ptr %x) {3183; RV32-LABEL: mulhu_v16i16:3184; RV32:       # %bb.0:3185; RV32-NEXT:    vsetivli zero, 16, e16, m2, ta, ma3186; RV32-NEXT:    vle16.v v10, (a0)3187; RV32-NEXT:    li a1, 2573188; RV32-NEXT:    vmv.v.i v8, 03189; RV32-NEXT:    vmv.s.x v0, a13190; RV32-NEXT:    lui a1, 10485683191; RV32-NEXT:    vmerge.vxm v12, v8, a1, v03192; RV32-NEXT:    lui a1, 43193; RV32-NEXT:    vsetvli zero, zero, e8, m1, ta, ma3194; RV32-NEXT:    vmv.v.i v9, 03195; RV32-NEXT:    addi a1, a1, 643196; RV32-NEXT:    vsetvli zero, zero, e16, m2, ta, ma3197; RV32-NEXT:    vmv.s.x v8, a13198; RV32-NEXT:    lui a1, 23199; RV32-NEXT:    addi a1, a1, 2893200; RV32-NEXT:    vmv1r.v v0, v83201; RV32-NEXT:    vsetvli zero, zero, e8, m1, ta, ma3202; RV32-NEXT:    vmerge.vim v16, v9, 1, v03203; RV32-NEXT:    vsetvli zero, zero, e16, m2, ta, ma3204; RV32-NEXT:    vmv.s.x v0, a13205; RV32-NEXT:    lui a1, %hi(.LCPI182_0)3206; RV32-NEXT:    addi a1, a1, %lo(.LCPI182_0)3207; RV32-NEXT:    vsetvli zero, zero, e8, m1, ta, ma3208; RV32-NEXT:    vmv.v.i v9, 33209; RV32-NEXT:    vmerge.vim v9, v9, 2, v03210; RV32-NEXT:    vle16.v v14, (a1)3211; RV32-NEXT:    vmv1r.v v0, v83212; RV32-NEXT:    vmerge.vim v17, v9, 1, v03213; RV32-NEXT:    vsetvli zero, zero, e16, m2, ta, ma3214; RV32-NEXT:    vsext.vf2 v8, v163215; RV32-NEXT:    vsrl.vv v8, v10, v83216; RV32-NEXT:    vmulhu.vv v8, v8, v143217; RV32-NEXT:    vsub.vv v10, v10, v83218; RV32-NEXT:    vmulhu.vv v10, v10, v123219; RV32-NEXT:    vadd.vv v8, v10, v83220; RV32-NEXT:    vsext.vf2 v10, v173221; RV32-NEXT:    vsrl.vv v8, v8, v103222; RV32-NEXT:    vse16.v v8, (a0)3223; RV32-NEXT:    ret3224;3225; RV64-LABEL: mulhu_v16i16:3226; RV64:       # %bb.0:3227; RV64-NEXT:    vsetivli zero, 16, e16, m2, ta, ma3228; RV64-NEXT:    vle16.v v8, (a0)3229; RV64-NEXT:    li a1, 2573230; RV64-NEXT:    vmv.v.i v10, 03231; RV64-NEXT:    vmv.s.x v0, a13232; RV64-NEXT:    lui a1, %hi(.LCPI182_0)3233; RV64-NEXT:    addi a1, a1, %lo(.LCPI182_0)3234; RV64-NEXT:    vle16.v v12, (a1)3235; RV64-NEXT:    lui a1, 10485683236; RV64-NEXT:    vmerge.vxm v10, v10, a1, v03237; RV64-NEXT:    li a1, 13238; RV64-NEXT:    slli a1, a1, 483239; RV64-NEXT:    vsetivli zero, 2, e64, m1, ta, ma3240; RV64-NEXT:    vmv.v.x v16, a13241; RV64-NEXT:    lui a1, %hi(.LCPI182_1)3242; RV64-NEXT:    ld a1, %lo(.LCPI182_1)(a1)3243; RV64-NEXT:    vsetivli zero, 16, e16, m2, ta, ma3244; RV64-NEXT:    vsext.vf2 v14, v163245; RV64-NEXT:    vsrl.vv v14, v8, v143246; RV64-NEXT:    vmulhu.vv v12, v14, v123247; RV64-NEXT:    vsetivli zero, 2, e64, m1, ta, ma3248; RV64-NEXT:    vmv.v.x v14, a13249; RV64-NEXT:    vsetivli zero, 16, e16, m2, ta, ma3250; RV64-NEXT:    vsub.vv v8, v8, v123251; RV64-NEXT:    vmulhu.vv v8, v8, v103252; RV64-NEXT:    vadd.vv v8, v8, v123253; RV64-NEXT:    vsext.vf2 v10, v143254; RV64-NEXT:    vsrl.vv v8, v8, v103255; RV64-NEXT:    vse16.v v8, (a0)3256; RV64-NEXT:    ret3257  %a = load <16 x i16>, ptr %x3258  %b = udiv <16 x i16> %a, <i16 7, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 7, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>3259  store <16 x i16> %b, ptr %x3260  ret void3261}3262 3263define void @mulhu_v8i32(ptr %x) {3264; CHECK-LABEL: mulhu_v8i32:3265; CHECK:       # %bb.0:3266; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma3267; CHECK-NEXT:    vle32.v v8, (a0)3268; CHECK-NEXT:    li a1, 683269; CHECK-NEXT:    vmv.v.i v10, 03270; CHECK-NEXT:    vmv.s.x v0, a13271; CHECK-NEXT:    lui a1, %hi(.LCPI183_0)3272; CHECK-NEXT:    addi a1, a1, %lo(.LCPI183_0)3273; CHECK-NEXT:    vle32.v v12, (a1)3274; CHECK-NEXT:    lui a1, 5242883275; CHECK-NEXT:    vmerge.vxm v10, v10, a1, v03276; CHECK-NEXT:    lui a1, 41283277; CHECK-NEXT:    addi a1, a1, 5143278; CHECK-NEXT:    vmulhu.vv v12, v8, v123279; CHECK-NEXT:    vsub.vv v8, v8, v123280; CHECK-NEXT:    vmulhu.vv v8, v8, v103281; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma3282; CHECK-NEXT:    vmv.v.x v14, a13283; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma3284; CHECK-NEXT:    vadd.vv v8, v8, v123285; CHECK-NEXT:    vsext.vf4 v10, v143286; CHECK-NEXT:    vsrl.vv v8, v8, v103287; CHECK-NEXT:    vse32.v v8, (a0)3288; CHECK-NEXT:    ret3289  %a = load <8 x i32>, ptr %x3290  %b = udiv <8 x i32> %a, <i32 5, i32 6, i32 7, i32 9, i32 5, i32 6, i32 7, i32 9>3291  store <8 x i32> %b, ptr %x3292  ret void3293}3294 3295define void @mulhu_v4i64(ptr %x) {3296; RV32-LABEL: mulhu_v4i64:3297; RV32:       # %bb.0:3298; RV32-NEXT:    vsetivli zero, 4, e64, m2, ta, ma3299; RV32-NEXT:    vle64.v v8, (a0)3300; RV32-NEXT:    lui a1, %hi(.LCPI184_0)3301; RV32-NEXT:    addi a1, a1, %lo(.LCPI184_0)3302; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma3303; RV32-NEXT:    vle32.v v10, (a1)3304; RV32-NEXT:    lui a1, 5242883305; RV32-NEXT:    vmv.v.i v12, 03306; RV32-NEXT:    vmv.s.x v14, a13307; RV32-NEXT:    lui a1, %hi(.LCPI184_1)3308; RV32-NEXT:    addi a1, a1, %lo(.LCPI184_1)3309; RV32-NEXT:    vsetivli zero, 6, e32, m2, tu, ma3310; RV32-NEXT:    vslideup.vi v12, v14, 53311; RV32-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma3312; RV32-NEXT:    vle8.v v14, (a1)3313; RV32-NEXT:    vsetivli zero, 4, e64, m2, ta, ma3314; RV32-NEXT:    vmulhu.vv v10, v8, v103315; RV32-NEXT:    vsub.vv v8, v8, v103316; RV32-NEXT:    vmulhu.vv v8, v8, v123317; RV32-NEXT:    vadd.vv v8, v8, v103318; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma3319; RV32-NEXT:    vsext.vf4 v10, v143320; RV32-NEXT:    vsetivli zero, 4, e64, m2, ta, ma3321; RV32-NEXT:    vsrl.vv v8, v8, v103322; RV32-NEXT:    vse64.v v8, (a0)3323; RV32-NEXT:    ret3324;3325; RV64-LABEL: mulhu_v4i64:3326; RV64:       # %bb.0:3327; RV64-NEXT:    vsetivli zero, 4, e64, m2, ta, ma3328; RV64-NEXT:    vle64.v v8, (a0)3329; RV64-NEXT:    lui a1, %hi(.LCPI184_0)3330; RV64-NEXT:    addi a1, a1, %lo(.LCPI184_0)3331; RV64-NEXT:    vle64.v v10, (a1)3332; RV64-NEXT:    li a1, -13333; RV64-NEXT:    vmv.v.i v12, 03334; RV64-NEXT:    slli a1, a1, 633335; RV64-NEXT:    vmv.s.x v14, a13336; RV64-NEXT:    lui a1, 123203337; RV64-NEXT:    addi a1, a1, 5133338; RV64-NEXT:    vsetivli zero, 3, e64, m2, tu, ma3339; RV64-NEXT:    vslideup.vi v12, v14, 23340; RV64-NEXT:    vmv.s.x v14, a13341; RV64-NEXT:    vsetivli zero, 4, e64, m2, ta, ma3342; RV64-NEXT:    vmulhu.vv v10, v8, v103343; RV64-NEXT:    vsub.vv v8, v8, v103344; RV64-NEXT:    vmulhu.vv v8, v8, v123345; RV64-NEXT:    vadd.vv v8, v8, v103346; RV64-NEXT:    vsext.vf8 v10, v143347; RV64-NEXT:    vsrl.vv v8, v8, v103348; RV64-NEXT:    vse64.v v8, (a0)3349; RV64-NEXT:    ret3350  %a = load <4 x i64>, ptr %x3351  %b = udiv <4 x i64> %a, <i64 3, i64 5, i64 7, i64 9>3352  store <4 x i64> %b, ptr %x3353  ret void3354}3355 3356define void @mulhs_v32i8(ptr %x) {3357; CHECK-LABEL: mulhs_v32i8:3358; CHECK:       # %bb.0:3359; CHECK-NEXT:    li a1, 323360; CHECK-NEXT:    lui a2, 3044533361; CHECK-NEXT:    addi a2, a2, -14523362; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, ma3363; CHECK-NEXT:    vmv.s.x v0, a23364; CHECK-NEXT:    li a2, -1233365; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma3366; CHECK-NEXT:    vle8.v v8, (a0)3367; CHECK-NEXT:    vmv.v.i v10, 73368; CHECK-NEXT:    vmerge.vim v10, v10, 1, v03369; CHECK-NEXT:    vmv.v.x v12, a23370; CHECK-NEXT:    li a1, 573371; CHECK-NEXT:    vmerge.vxm v12, v12, a1, v03372; CHECK-NEXT:    vmulhu.vv v8, v8, v123373; CHECK-NEXT:    vsrl.vv v8, v8, v103374; CHECK-NEXT:    vse8.v v8, (a0)3375; CHECK-NEXT:    ret3376  %a = load <32 x i8>, ptr %x3377  %b = udiv <32 x i8> %a, <i8 -9, i8 -9, i8 9, i8 -9, i8 9, i8 -9, i8 9, i8 -9, i8 -9, i8 9, i8 -9, i8 9, i8 -9, i8 -9, i8 9, i8 -9, i8 -9, i8 -9, i8 9, i8 -9, i8 9, i8 -9, i8 9, i8 -9, i8 -9, i8 9, i8 -9, i8 9, i8 -9, i8 -9, i8 9, i8 -9>3378  store <32 x i8> %b, ptr %x3379  ret void3380}3381 3382define void @mulhs_v16i16(ptr %x) {3383; CHECK-LABEL: mulhs_v16i16:3384; CHECK:       # %bb.0:3385; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma3386; CHECK-NEXT:    vle16.v v8, (a0)3387; CHECK-NEXT:    lui a1, 53388; CHECK-NEXT:    addi a1, a1, -17553389; CHECK-NEXT:    vmv.v.x v10, a13390; CHECK-NEXT:    lui a1, 73391; CHECK-NEXT:    addi a1, a1, -16873392; CHECK-NEXT:    vmv.s.x v0, a13393; CHECK-NEXT:    lui a1, 10485713394; CHECK-NEXT:    addi a1, a1, 17553395; CHECK-NEXT:    vmerge.vxm v10, v10, a1, v03396; CHECK-NEXT:    vmulh.vv v8, v8, v103397; CHECK-NEXT:    vsra.vi v8, v8, 13398; CHECK-NEXT:    vsrl.vi v10, v8, 153399; CHECK-NEXT:    vadd.vv v8, v8, v103400; CHECK-NEXT:    vse16.v v8, (a0)3401; CHECK-NEXT:    ret3402  %a = load <16 x i16>, ptr %x3403  %b = sdiv <16 x i16> %a, <i16 -7, i16 7, i16 7, i16 -7, i16 7, i16 -7, i16 -7, i16 7, i16 -7, i16 7, i16 7, i16 -7, i16 7, i16 -7, i16 -7, i16 7>3404  store <16 x i16> %b, ptr %x3405  ret void3406}3407 3408define void @mulhs_v8i32(ptr %x) {3409; RV32-LABEL: mulhs_v8i32:3410; RV32:       # %bb.0:3411; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma3412; RV32-NEXT:    vle32.v v8, (a0)3413; RV32-NEXT:    li a1, 853414; RV32-NEXT:    vmv.s.x v0, a13415; RV32-NEXT:    lui a1, 4194303416; RV32-NEXT:    addi a1, a1, 16393417; RV32-NEXT:    vmv.v.x v10, a13418; RV32-NEXT:    lui a1, 6291463419; RV32-NEXT:    addi a1, a1, -16393420; RV32-NEXT:    vmerge.vxm v10, v10, a1, v03421; RV32-NEXT:    vmulh.vv v8, v8, v103422; RV32-NEXT:    vsrl.vi v10, v8, 313423; RV32-NEXT:    vsra.vi v8, v8, 13424; RV32-NEXT:    vadd.vv v8, v8, v103425; RV32-NEXT:    vse32.v v8, (a0)3426; RV32-NEXT:    ret3427;3428; RV64-LABEL: mulhs_v8i32:3429; RV64:       # %bb.0:3430; RV64-NEXT:    lui a1, %hi(.LCPI187_0)3431; RV64-NEXT:    ld a1, %lo(.LCPI187_0)(a1)3432; RV64-NEXT:    vsetivli zero, 8, e32, m2, ta, ma3433; RV64-NEXT:    vle32.v v8, (a0)3434; RV64-NEXT:    vsetivli zero, 4, e64, m2, ta, ma3435; RV64-NEXT:    vmv.v.x v10, a13436; RV64-NEXT:    vsetivli zero, 8, e32, m2, ta, ma3437; RV64-NEXT:    vmulh.vv v8, v8, v103438; RV64-NEXT:    vsra.vi v8, v8, 13439; RV64-NEXT:    vsrl.vi v10, v8, 313440; RV64-NEXT:    vadd.vv v8, v8, v103441; RV64-NEXT:    vse32.v v8, (a0)3442; RV64-NEXT:    ret3443  %a = load <8 x i32>, ptr %x3444  %b = sdiv <8 x i32> %a, <i32 -5, i32 5, i32 -5, i32 5, i32 -5, i32 5, i32 -5, i32 5>3445  store <8 x i32> %b, ptr %x3446  ret void3447}3448 3449define void @mulhs_v4i64(ptr %x) {3450; RV32-LABEL: mulhs_v4i64:3451; RV32:       # %bb.0:3452; RV32-NEXT:    vsetivli zero, 4, e64, m2, ta, ma3453; RV32-NEXT:    vle64.v v8, (a0)3454; RV32-NEXT:    lui a1, 3495253455; RV32-NEXT:    li a2, 173456; RV32-NEXT:    vmv.s.x v0, a23457; RV32-NEXT:    lui a2, 10485603458; RV32-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma3459; RV32-NEXT:    vmv.v.x v14, a23460; RV32-NEXT:    addi a2, a1, 13653461; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma3462; RV32-NEXT:    vmv.v.x v10, a23463; RV32-NEXT:    li a2, 633464; RV32-NEXT:    addi a1, a1, 13663465; RV32-NEXT:    vmerge.vxm v10, v10, a1, v03466; RV32-NEXT:    lui a1, 163467; RV32-NEXT:    vsext.vf4 v12, v143468; RV32-NEXT:    vsetivli zero, 4, e64, m2, ta, ma3469; RV32-NEXT:    vmulh.vv v10, v8, v103470; RV32-NEXT:    vmadd.vv v12, v8, v103471; RV32-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma3472; RV32-NEXT:    vmv.v.x v10, a13473; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma3474; RV32-NEXT:    vsext.vf4 v8, v103475; RV32-NEXT:    vsetivli zero, 4, e64, m2, ta, ma3476; RV32-NEXT:    vsrl.vx v10, v12, a23477; RV32-NEXT:    vsra.vv v8, v12, v83478; RV32-NEXT:    vadd.vv v8, v8, v103479; RV32-NEXT:    vse64.v v8, (a0)3480; RV32-NEXT:    ret3481;3482; RV64-LABEL: mulhs_v4i64:3483; RV64:       # %bb.0:3484; RV64-NEXT:    vsetivli zero, 4, e64, m2, ta, ma3485; RV64-NEXT:    vle64.v v8, (a0)3486; RV64-NEXT:    lui a1, 3495253487; RV64-NEXT:    lui a2, 10444963488; RV64-NEXT:    addi a1, a1, 13653489; RV64-NEXT:    addi a2, a2, -2563490; RV64-NEXT:    vmv.s.x v14, a23491; RV64-NEXT:    slli a2, a1, 323492; RV64-NEXT:    add a1, a1, a23493; RV64-NEXT:    lui a2, %hi(.LCPI188_0)3494; RV64-NEXT:    ld a2, %lo(.LCPI188_0)(a2)3495; RV64-NEXT:    vsetivli zero, 1, e8, mf8, ta, ma3496; RV64-NEXT:    vmv.v.i v0, 53497; RV64-NEXT:    vsetivli zero, 4, e64, m2, ta, ma3498; RV64-NEXT:    vmv.v.x v10, a13499; RV64-NEXT:    li a1, 633500; RV64-NEXT:    vmerge.vxm v10, v10, a2, v03501; RV64-NEXT:    lui a2, 40963502; RV64-NEXT:    addi a2, a2, 2563503; RV64-NEXT:    vsext.vf8 v12, v143504; RV64-NEXT:    vmulh.vv v10, v8, v103505; RV64-NEXT:    vmadd.vv v12, v8, v103506; RV64-NEXT:    vmv.s.x v10, a23507; RV64-NEXT:    vsext.vf8 v8, v103508; RV64-NEXT:    vsrl.vx v10, v12, a13509; RV64-NEXT:    vsra.vv v8, v12, v83510; RV64-NEXT:    vadd.vv v8, v8, v103511; RV64-NEXT:    vse64.v v8, (a0)3512; RV64-NEXT:    ret3513  %a = load <4 x i64>, ptr %x3514  %b = sdiv <4 x i64> %a, <i64 3, i64 -3, i64 3, i64 -3>3515  store <4 x i64> %b, ptr %x3516  ret void3517}3518 3519define void @smin_v32i8(ptr %x, ptr %y) {3520; CHECK-LABEL: smin_v32i8:3521; CHECK:       # %bb.0:3522; CHECK-NEXT:    li a2, 323523; CHECK-NEXT:    vsetvli zero, a2, e8, m2, ta, ma3524; CHECK-NEXT:    vle8.v v8, (a0)3525; CHECK-NEXT:    vle8.v v10, (a1)3526; CHECK-NEXT:    vmin.vv v8, v8, v103527; CHECK-NEXT:    vse8.v v8, (a0)3528; CHECK-NEXT:    ret3529  %a = load <32 x i8>, ptr %x3530  %b = load <32 x i8>, ptr %y3531  %cc = icmp slt <32 x i8> %a, %b3532  %c = select <32 x i1> %cc, <32 x i8> %a, <32 x i8> %b3533  store <32 x i8> %c, ptr %x3534  ret void3535}3536 3537define void @smin_v16i16(ptr %x, ptr %y) {3538; CHECK-LABEL: smin_v16i16:3539; CHECK:       # %bb.0:3540; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma3541; CHECK-NEXT:    vle16.v v8, (a0)3542; CHECK-NEXT:    vle16.v v10, (a1)3543; CHECK-NEXT:    vmin.vv v8, v8, v103544; CHECK-NEXT:    vse16.v v8, (a0)3545; CHECK-NEXT:    ret3546  %a = load <16 x i16>, ptr %x3547  %b = load <16 x i16>, ptr %y3548  %cc = icmp slt <16 x i16> %a, %b3549  %c = select <16 x i1> %cc, <16 x i16> %a, <16 x i16> %b3550  store <16 x i16> %c, ptr %x3551  ret void3552}3553 3554define void @smin_v8i32(ptr %x, ptr %y) {3555; CHECK-LABEL: smin_v8i32:3556; CHECK:       # %bb.0:3557; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma3558; CHECK-NEXT:    vle32.v v8, (a0)3559; CHECK-NEXT:    vle32.v v10, (a1)3560; CHECK-NEXT:    vmin.vv v8, v8, v103561; CHECK-NEXT:    vse32.v v8, (a0)3562; CHECK-NEXT:    ret3563  %a = load <8 x i32>, ptr %x3564  %b = load <8 x i32>, ptr %y3565  %cc = icmp slt <8 x i32> %a, %b3566  %c = select <8 x i1> %cc, <8 x i32> %a, <8 x i32> %b3567  store <8 x i32> %c, ptr %x3568  ret void3569}3570 3571define void @smin_v4i64(ptr %x, ptr %y) {3572; CHECK-LABEL: smin_v4i64:3573; CHECK:       # %bb.0:3574; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma3575; CHECK-NEXT:    vle64.v v8, (a0)3576; CHECK-NEXT:    vle64.v v10, (a1)3577; CHECK-NEXT:    vmin.vv v8, v8, v103578; CHECK-NEXT:    vse64.v v8, (a0)3579; CHECK-NEXT:    ret3580  %a = load <4 x i64>, ptr %x3581  %b = load <4 x i64>, ptr %y3582  %cc = icmp slt <4 x i64> %a, %b3583  %c = select <4 x i1> %cc, <4 x i64> %a, <4 x i64> %b3584  store <4 x i64> %c, ptr %x3585  ret void3586}3587 3588define void @smax_v32i8(ptr %x, ptr %y) {3589; CHECK-LABEL: smax_v32i8:3590; CHECK:       # %bb.0:3591; CHECK-NEXT:    li a2, 323592; CHECK-NEXT:    vsetvli zero, a2, e8, m2, ta, ma3593; CHECK-NEXT:    vle8.v v8, (a0)3594; CHECK-NEXT:    vle8.v v10, (a1)3595; CHECK-NEXT:    vmax.vv v8, v8, v103596; CHECK-NEXT:    vse8.v v8, (a0)3597; CHECK-NEXT:    ret3598  %a = load <32 x i8>, ptr %x3599  %b = load <32 x i8>, ptr %y3600  %cc = icmp sgt <32 x i8> %a, %b3601  %c = select <32 x i1> %cc, <32 x i8> %a, <32 x i8> %b3602  store <32 x i8> %c, ptr %x3603  ret void3604}3605 3606define void @smax_v16i16(ptr %x, ptr %y) {3607; CHECK-LABEL: smax_v16i16:3608; CHECK:       # %bb.0:3609; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma3610; CHECK-NEXT:    vle16.v v8, (a0)3611; CHECK-NEXT:    vle16.v v10, (a1)3612; CHECK-NEXT:    vmax.vv v8, v8, v103613; CHECK-NEXT:    vse16.v v8, (a0)3614; CHECK-NEXT:    ret3615  %a = load <16 x i16>, ptr %x3616  %b = load <16 x i16>, ptr %y3617  %cc = icmp sgt <16 x i16> %a, %b3618  %c = select <16 x i1> %cc, <16 x i16> %a, <16 x i16> %b3619  store <16 x i16> %c, ptr %x3620  ret void3621}3622 3623define void @smax_v8i32(ptr %x, ptr %y) {3624; CHECK-LABEL: smax_v8i32:3625; CHECK:       # %bb.0:3626; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma3627; CHECK-NEXT:    vle32.v v8, (a0)3628; CHECK-NEXT:    vle32.v v10, (a1)3629; CHECK-NEXT:    vmax.vv v8, v8, v103630; CHECK-NEXT:    vse32.v v8, (a0)3631; CHECK-NEXT:    ret3632  %a = load <8 x i32>, ptr %x3633  %b = load <8 x i32>, ptr %y3634  %cc = icmp sgt <8 x i32> %a, %b3635  %c = select <8 x i1> %cc, <8 x i32> %a, <8 x i32> %b3636  store <8 x i32> %c, ptr %x3637  ret void3638}3639 3640define void @smax_v4i64(ptr %x, ptr %y) {3641; CHECK-LABEL: smax_v4i64:3642; CHECK:       # %bb.0:3643; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma3644; CHECK-NEXT:    vle64.v v8, (a0)3645; CHECK-NEXT:    vle64.v v10, (a1)3646; CHECK-NEXT:    vmax.vv v8, v8, v103647; CHECK-NEXT:    vse64.v v8, (a0)3648; CHECK-NEXT:    ret3649  %a = load <4 x i64>, ptr %x3650  %b = load <4 x i64>, ptr %y3651  %cc = icmp sgt <4 x i64> %a, %b3652  %c = select <4 x i1> %cc, <4 x i64> %a, <4 x i64> %b3653  store <4 x i64> %c, ptr %x3654  ret void3655}3656 3657define void @umin_v32i8(ptr %x, ptr %y) {3658; CHECK-LABEL: umin_v32i8:3659; CHECK:       # %bb.0:3660; CHECK-NEXT:    li a2, 323661; CHECK-NEXT:    vsetvli zero, a2, e8, m2, ta, ma3662; CHECK-NEXT:    vle8.v v8, (a0)3663; CHECK-NEXT:    vle8.v v10, (a1)3664; CHECK-NEXT:    vminu.vv v8, v8, v103665; CHECK-NEXT:    vse8.v v8, (a0)3666; CHECK-NEXT:    ret3667  %a = load <32 x i8>, ptr %x3668  %b = load <32 x i8>, ptr %y3669  %cc = icmp ult <32 x i8> %a, %b3670  %c = select <32 x i1> %cc, <32 x i8> %a, <32 x i8> %b3671  store <32 x i8> %c, ptr %x3672  ret void3673}3674 3675define void @umin_v16i16(ptr %x, ptr %y) {3676; CHECK-LABEL: umin_v16i16:3677; CHECK:       # %bb.0:3678; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma3679; CHECK-NEXT:    vle16.v v8, (a0)3680; CHECK-NEXT:    vle16.v v10, (a1)3681; CHECK-NEXT:    vminu.vv v8, v8, v103682; CHECK-NEXT:    vse16.v v8, (a0)3683; CHECK-NEXT:    ret3684  %a = load <16 x i16>, ptr %x3685  %b = load <16 x i16>, ptr %y3686  %cc = icmp ult <16 x i16> %a, %b3687  %c = select <16 x i1> %cc, <16 x i16> %a, <16 x i16> %b3688  store <16 x i16> %c, ptr %x3689  ret void3690}3691 3692define void @umin_v8i32(ptr %x, ptr %y) {3693; CHECK-LABEL: umin_v8i32:3694; CHECK:       # %bb.0:3695; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma3696; CHECK-NEXT:    vle32.v v8, (a0)3697; CHECK-NEXT:    vle32.v v10, (a1)3698; CHECK-NEXT:    vminu.vv v8, v8, v103699; CHECK-NEXT:    vse32.v v8, (a0)3700; CHECK-NEXT:    ret3701  %a = load <8 x i32>, ptr %x3702  %b = load <8 x i32>, ptr %y3703  %cc = icmp ult <8 x i32> %a, %b3704  %c = select <8 x i1> %cc, <8 x i32> %a, <8 x i32> %b3705  store <8 x i32> %c, ptr %x3706  ret void3707}3708 3709define void @umin_v4i64(ptr %x, ptr %y) {3710; CHECK-LABEL: umin_v4i64:3711; CHECK:       # %bb.0:3712; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma3713; CHECK-NEXT:    vle64.v v8, (a0)3714; CHECK-NEXT:    vle64.v v10, (a1)3715; CHECK-NEXT:    vminu.vv v8, v8, v103716; CHECK-NEXT:    vse64.v v8, (a0)3717; CHECK-NEXT:    ret3718  %a = load <4 x i64>, ptr %x3719  %b = load <4 x i64>, ptr %y3720  %cc = icmp ult <4 x i64> %a, %b3721  %c = select <4 x i1> %cc, <4 x i64> %a, <4 x i64> %b3722  store <4 x i64> %c, ptr %x3723  ret void3724}3725 3726define void @umax_v32i8(ptr %x, ptr %y) {3727; CHECK-LABEL: umax_v32i8:3728; CHECK:       # %bb.0:3729; CHECK-NEXT:    li a2, 323730; CHECK-NEXT:    vsetvli zero, a2, e8, m2, ta, ma3731; CHECK-NEXT:    vle8.v v8, (a0)3732; CHECK-NEXT:    vle8.v v10, (a1)3733; CHECK-NEXT:    vmaxu.vv v8, v8, v103734; CHECK-NEXT:    vse8.v v8, (a0)3735; CHECK-NEXT:    ret3736  %a = load <32 x i8>, ptr %x3737  %b = load <32 x i8>, ptr %y3738  %cc = icmp ugt <32 x i8> %a, %b3739  %c = select <32 x i1> %cc, <32 x i8> %a, <32 x i8> %b3740  store <32 x i8> %c, ptr %x3741  ret void3742}3743 3744define void @umax_v16i16(ptr %x, ptr %y) {3745; CHECK-LABEL: umax_v16i16:3746; CHECK:       # %bb.0:3747; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma3748; CHECK-NEXT:    vle16.v v8, (a0)3749; CHECK-NEXT:    vle16.v v10, (a1)3750; CHECK-NEXT:    vmaxu.vv v8, v8, v103751; CHECK-NEXT:    vse16.v v8, (a0)3752; CHECK-NEXT:    ret3753  %a = load <16 x i16>, ptr %x3754  %b = load <16 x i16>, ptr %y3755  %cc = icmp ugt <16 x i16> %a, %b3756  %c = select <16 x i1> %cc, <16 x i16> %a, <16 x i16> %b3757  store <16 x i16> %c, ptr %x3758  ret void3759}3760 3761define void @umax_v8i32(ptr %x, ptr %y) {3762; CHECK-LABEL: umax_v8i32:3763; CHECK:       # %bb.0:3764; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma3765; CHECK-NEXT:    vle32.v v8, (a0)3766; CHECK-NEXT:    vle32.v v10, (a1)3767; CHECK-NEXT:    vmaxu.vv v8, v8, v103768; CHECK-NEXT:    vse32.v v8, (a0)3769; CHECK-NEXT:    ret3770  %a = load <8 x i32>, ptr %x3771  %b = load <8 x i32>, ptr %y3772  %cc = icmp ugt <8 x i32> %a, %b3773  %c = select <8 x i1> %cc, <8 x i32> %a, <8 x i32> %b3774  store <8 x i32> %c, ptr %x3775  ret void3776}3777 3778define void @umax_v4i64(ptr %x, ptr %y) {3779; CHECK-LABEL: umax_v4i64:3780; CHECK:       # %bb.0:3781; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma3782; CHECK-NEXT:    vle64.v v8, (a0)3783; CHECK-NEXT:    vle64.v v10, (a1)3784; CHECK-NEXT:    vmaxu.vv v8, v8, v103785; CHECK-NEXT:    vse64.v v8, (a0)3786; CHECK-NEXT:    ret3787  %a = load <4 x i64>, ptr %x3788  %b = load <4 x i64>, ptr %y3789  %cc = icmp ugt <4 x i64> %a, %b3790  %c = select <4 x i1> %cc, <4 x i64> %a, <4 x i64> %b3791  store <4 x i64> %c, ptr %x3792  ret void3793}3794 3795define void @add_vi_v16i8(ptr %x) {3796; CHECK-LABEL: add_vi_v16i8:3797; CHECK:       # %bb.0:3798; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma3799; CHECK-NEXT:    vle8.v v8, (a0)3800; CHECK-NEXT:    vadd.vi v8, v8, -13801; CHECK-NEXT:    vse8.v v8, (a0)3802; CHECK-NEXT:    ret3803  %a = load <16 x i8>, ptr %x3804  %d = add <16 x i8> %a, splat (i8 -1)3805  store <16 x i8> %d, ptr %x3806  ret void3807}3808 3809define void @add_vi_v8i16(ptr %x) {3810; CHECK-LABEL: add_vi_v8i16:3811; CHECK:       # %bb.0:3812; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma3813; CHECK-NEXT:    vle16.v v8, (a0)3814; CHECK-NEXT:    vadd.vi v8, v8, -13815; CHECK-NEXT:    vse16.v v8, (a0)3816; CHECK-NEXT:    ret3817  %a = load <8 x i16>, ptr %x3818  %d = add <8 x i16> %a, splat (i16 -1)3819  store <8 x i16> %d, ptr %x3820  ret void3821}3822 3823define void @add_vi_v4i32(ptr %x) {3824; CHECK-LABEL: add_vi_v4i32:3825; CHECK:       # %bb.0:3826; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma3827; CHECK-NEXT:    vle32.v v8, (a0)3828; CHECK-NEXT:    vadd.vi v8, v8, -13829; CHECK-NEXT:    vse32.v v8, (a0)3830; CHECK-NEXT:    ret3831  %a = load <4 x i32>, ptr %x3832  %d = add <4 x i32> %a, splat (i32 -1)3833  store <4 x i32> %d, ptr %x3834  ret void3835}3836 3837define void @add_vi_v2i64(ptr %x) {3838; CHECK-LABEL: add_vi_v2i64:3839; CHECK:       # %bb.0:3840; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma3841; CHECK-NEXT:    vle64.v v8, (a0)3842; CHECK-NEXT:    vadd.vi v8, v8, -13843; CHECK-NEXT:    vse64.v v8, (a0)3844; CHECK-NEXT:    ret3845  %a = load <2 x i64>, ptr %x3846  %d = add <2 x i64> %a, splat (i64 -1)3847  store <2 x i64> %d, ptr %x3848  ret void3849}3850 3851define void @add_iv_v16i8(ptr %x) {3852; CHECK-LABEL: add_iv_v16i8:3853; CHECK:       # %bb.0:3854; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma3855; CHECK-NEXT:    vle8.v v8, (a0)3856; CHECK-NEXT:    vadd.vi v8, v8, 13857; CHECK-NEXT:    vse8.v v8, (a0)3858; CHECK-NEXT:    ret3859  %a = load <16 x i8>, ptr %x3860  %d = add <16 x i8> splat (i8 1), %a3861  store <16 x i8> %d, ptr %x3862  ret void3863}3864 3865define void @add_iv_v8i16(ptr %x) {3866; CHECK-LABEL: add_iv_v8i16:3867; CHECK:       # %bb.0:3868; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma3869; CHECK-NEXT:    vle16.v v8, (a0)3870; CHECK-NEXT:    vadd.vi v8, v8, 13871; CHECK-NEXT:    vse16.v v8, (a0)3872; CHECK-NEXT:    ret3873  %a = load <8 x i16>, ptr %x3874  %d = add <8 x i16> splat (i16 1), %a3875  store <8 x i16> %d, ptr %x3876  ret void3877}3878 3879define void @add_iv_v4i32(ptr %x) {3880; CHECK-LABEL: add_iv_v4i32:3881; CHECK:       # %bb.0:3882; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma3883; CHECK-NEXT:    vle32.v v8, (a0)3884; CHECK-NEXT:    vadd.vi v8, v8, 13885; CHECK-NEXT:    vse32.v v8, (a0)3886; CHECK-NEXT:    ret3887  %a = load <4 x i32>, ptr %x3888  %d = add <4 x i32> splat (i32 1), %a3889  store <4 x i32> %d, ptr %x3890  ret void3891}3892 3893define void @add_iv_v2i64(ptr %x) {3894; CHECK-LABEL: add_iv_v2i64:3895; CHECK:       # %bb.0:3896; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma3897; CHECK-NEXT:    vle64.v v8, (a0)3898; CHECK-NEXT:    vadd.vi v8, v8, 13899; CHECK-NEXT:    vse64.v v8, (a0)3900; CHECK-NEXT:    ret3901  %a = load <2 x i64>, ptr %x3902  %d = add <2 x i64> splat (i64 1), %a3903  store <2 x i64> %d, ptr %x3904  ret void3905}3906 3907define void @add_vx_v16i8(ptr %x, i8 %y) {3908; CHECK-LABEL: add_vx_v16i8:3909; CHECK:       # %bb.0:3910; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma3911; CHECK-NEXT:    vle8.v v8, (a0)3912; CHECK-NEXT:    vadd.vx v8, v8, a13913; CHECK-NEXT:    vse8.v v8, (a0)3914; CHECK-NEXT:    ret3915  %a = load <16 x i8>, ptr %x3916  %b = insertelement <16 x i8> poison, i8 %y, i32 03917  %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer3918  %d = add <16 x i8> %a, %c3919  store <16 x i8> %d, ptr %x3920  ret void3921}3922 3923define void @add_vx_v8i16(ptr %x, i16 %y) {3924; CHECK-LABEL: add_vx_v8i16:3925; CHECK:       # %bb.0:3926; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma3927; CHECK-NEXT:    vle16.v v8, (a0)3928; CHECK-NEXT:    vadd.vx v8, v8, a13929; CHECK-NEXT:    vse16.v v8, (a0)3930; CHECK-NEXT:    ret3931  %a = load <8 x i16>, ptr %x3932  %b = insertelement <8 x i16> poison, i16 %y, i32 03933  %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer3934  %d = add <8 x i16> %a, %c3935  store <8 x i16> %d, ptr %x3936  ret void3937}3938 3939define void @add_vx_v4i32(ptr %x, i32 %y) {3940; CHECK-LABEL: add_vx_v4i32:3941; CHECK:       # %bb.0:3942; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma3943; CHECK-NEXT:    vle32.v v8, (a0)3944; CHECK-NEXT:    vadd.vx v8, v8, a13945; CHECK-NEXT:    vse32.v v8, (a0)3946; CHECK-NEXT:    ret3947  %a = load <4 x i32>, ptr %x3948  %b = insertelement <4 x i32> poison, i32 %y, i32 03949  %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer3950  %d = add <4 x i32> %a, %c3951  store <4 x i32> %d, ptr %x3952  ret void3953}3954 3955define void @add_xv_v16i8(ptr %x, i8 %y) {3956; CHECK-LABEL: add_xv_v16i8:3957; CHECK:       # %bb.0:3958; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma3959; CHECK-NEXT:    vle8.v v8, (a0)3960; CHECK-NEXT:    vadd.vx v8, v8, a13961; CHECK-NEXT:    vse8.v v8, (a0)3962; CHECK-NEXT:    ret3963  %a = load <16 x i8>, ptr %x3964  %b = insertelement <16 x i8> poison, i8 %y, i32 03965  %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer3966  %d = add <16 x i8> %c, %a3967  store <16 x i8> %d, ptr %x3968  ret void3969}3970 3971define void @add_xv_v8i16(ptr %x, i16 %y) {3972; CHECK-LABEL: add_xv_v8i16:3973; CHECK:       # %bb.0:3974; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma3975; CHECK-NEXT:    vle16.v v8, (a0)3976; CHECK-NEXT:    vadd.vx v8, v8, a13977; CHECK-NEXT:    vse16.v v8, (a0)3978; CHECK-NEXT:    ret3979  %a = load <8 x i16>, ptr %x3980  %b = insertelement <8 x i16> poison, i16 %y, i32 03981  %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer3982  %d = add <8 x i16> %c, %a3983  store <8 x i16> %d, ptr %x3984  ret void3985}3986 3987define void @add_xv_v4i32(ptr %x, i32 %y) {3988; CHECK-LABEL: add_xv_v4i32:3989; CHECK:       # %bb.0:3990; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma3991; CHECK-NEXT:    vle32.v v8, (a0)3992; CHECK-NEXT:    vadd.vx v8, v8, a13993; CHECK-NEXT:    vse32.v v8, (a0)3994; CHECK-NEXT:    ret3995  %a = load <4 x i32>, ptr %x3996  %b = insertelement <4 x i32> poison, i32 %y, i32 03997  %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer3998  %d = add <4 x i32> %c, %a3999  store <4 x i32> %d, ptr %x4000  ret void4001}4002 4003define void @sub_vi_v16i8(ptr %x) {4004; CHECK-LABEL: sub_vi_v16i8:4005; CHECK:       # %bb.0:4006; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma4007; CHECK-NEXT:    vle8.v v8, (a0)4008; CHECK-NEXT:    vadd.vi v8, v8, 14009; CHECK-NEXT:    vse8.v v8, (a0)4010; CHECK-NEXT:    ret4011  %a = load <16 x i8>, ptr %x4012  %d = sub <16 x i8> %a, splat (i8 -1)4013  store <16 x i8> %d, ptr %x4014  ret void4015}4016 4017define void @sub_vi_v8i16(ptr %x) {4018; CHECK-LABEL: sub_vi_v8i16:4019; CHECK:       # %bb.0:4020; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma4021; CHECK-NEXT:    vle16.v v8, (a0)4022; CHECK-NEXT:    vadd.vi v8, v8, 14023; CHECK-NEXT:    vse16.v v8, (a0)4024; CHECK-NEXT:    ret4025  %a = load <8 x i16>, ptr %x4026  %d = sub <8 x i16> %a, splat (i16 -1)4027  store <8 x i16> %d, ptr %x4028  ret void4029}4030 4031define void @sub_vi_v4i32(ptr %x) {4032; CHECK-LABEL: sub_vi_v4i32:4033; CHECK:       # %bb.0:4034; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma4035; CHECK-NEXT:    vle32.v v8, (a0)4036; CHECK-NEXT:    vadd.vi v8, v8, 14037; CHECK-NEXT:    vse32.v v8, (a0)4038; CHECK-NEXT:    ret4039  %a = load <4 x i32>, ptr %x4040  %d = sub <4 x i32> %a, splat (i32 -1)4041  store <4 x i32> %d, ptr %x4042  ret void4043}4044 4045define void @sub_vi_v2i64(ptr %x) {4046; CHECK-LABEL: sub_vi_v2i64:4047; CHECK:       # %bb.0:4048; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma4049; CHECK-NEXT:    vle64.v v8, (a0)4050; CHECK-NEXT:    vadd.vi v8, v8, 14051; CHECK-NEXT:    vse64.v v8, (a0)4052; CHECK-NEXT:    ret4053  %a = load <2 x i64>, ptr %x4054  %d = sub <2 x i64> %a, splat (i64 -1)4055  store <2 x i64> %d, ptr %x4056  ret void4057}4058 4059define void @sub_iv_v16i8(ptr %x) {4060; CHECK-LABEL: sub_iv_v16i8:4061; CHECK:       # %bb.0:4062; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma4063; CHECK-NEXT:    vle8.v v8, (a0)4064; CHECK-NEXT:    vrsub.vi v8, v8, 14065; CHECK-NEXT:    vse8.v v8, (a0)4066; CHECK-NEXT:    ret4067  %a = load <16 x i8>, ptr %x4068  %d = sub <16 x i8> splat (i8 1), %a4069  store <16 x i8> %d, ptr %x4070  ret void4071}4072 4073define void @sub_iv_v8i16(ptr %x) {4074; CHECK-LABEL: sub_iv_v8i16:4075; CHECK:       # %bb.0:4076; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma4077; CHECK-NEXT:    vle16.v v8, (a0)4078; CHECK-NEXT:    vrsub.vi v8, v8, 14079; CHECK-NEXT:    vse16.v v8, (a0)4080; CHECK-NEXT:    ret4081  %a = load <8 x i16>, ptr %x4082  %d = sub <8 x i16> splat (i16 1), %a4083  store <8 x i16> %d, ptr %x4084  ret void4085}4086 4087define void @sub_iv_v4i32(ptr %x) {4088; CHECK-LABEL: sub_iv_v4i32:4089; CHECK:       # %bb.0:4090; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma4091; CHECK-NEXT:    vle32.v v8, (a0)4092; CHECK-NEXT:    vrsub.vi v8, v8, 14093; CHECK-NEXT:    vse32.v v8, (a0)4094; CHECK-NEXT:    ret4095  %a = load <4 x i32>, ptr %x4096  %d = sub <4 x i32> splat (i32 1), %a4097  store <4 x i32> %d, ptr %x4098  ret void4099}4100 4101define void @sub_iv_v2i64(ptr %x) {4102; CHECK-LABEL: sub_iv_v2i64:4103; CHECK:       # %bb.0:4104; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma4105; CHECK-NEXT:    vle64.v v8, (a0)4106; CHECK-NEXT:    vrsub.vi v8, v8, 14107; CHECK-NEXT:    vse64.v v8, (a0)4108; CHECK-NEXT:    ret4109  %a = load <2 x i64>, ptr %x4110  %d = sub <2 x i64> splat (i64 1), %a4111  store <2 x i64> %d, ptr %x4112  ret void4113}4114 4115define void @sub_vx_v16i8(ptr %x, i8 %y) {4116; CHECK-LABEL: sub_vx_v16i8:4117; CHECK:       # %bb.0:4118; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma4119; CHECK-NEXT:    vle8.v v8, (a0)4120; CHECK-NEXT:    vsub.vx v8, v8, a14121; CHECK-NEXT:    vse8.v v8, (a0)4122; CHECK-NEXT:    ret4123  %a = load <16 x i8>, ptr %x4124  %b = insertelement <16 x i8> poison, i8 %y, i32 04125  %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer4126  %d = sub <16 x i8> %a, %c4127  store <16 x i8> %d, ptr %x4128  ret void4129}4130 4131define void @sub_vx_v8i16(ptr %x, i16 %y) {4132; CHECK-LABEL: sub_vx_v8i16:4133; CHECK:       # %bb.0:4134; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma4135; CHECK-NEXT:    vle16.v v8, (a0)4136; CHECK-NEXT:    vsub.vx v8, v8, a14137; CHECK-NEXT:    vse16.v v8, (a0)4138; CHECK-NEXT:    ret4139  %a = load <8 x i16>, ptr %x4140  %b = insertelement <8 x i16> poison, i16 %y, i32 04141  %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer4142  %d = sub <8 x i16> %a, %c4143  store <8 x i16> %d, ptr %x4144  ret void4145}4146 4147define void @sub_vx_v4i32(ptr %x, i32 %y) {4148; CHECK-LABEL: sub_vx_v4i32:4149; CHECK:       # %bb.0:4150; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma4151; CHECK-NEXT:    vle32.v v8, (a0)4152; CHECK-NEXT:    vsub.vx v8, v8, a14153; CHECK-NEXT:    vse32.v v8, (a0)4154; CHECK-NEXT:    ret4155  %a = load <4 x i32>, ptr %x4156  %b = insertelement <4 x i32> poison, i32 %y, i32 04157  %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer4158  %d = sub <4 x i32> %a, %c4159  store <4 x i32> %d, ptr %x4160  ret void4161}4162 4163define void @sub_xv_v16i8(ptr %x, i8 %y) {4164; CHECK-LABEL: sub_xv_v16i8:4165; CHECK:       # %bb.0:4166; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma4167; CHECK-NEXT:    vle8.v v8, (a0)4168; CHECK-NEXT:    vrsub.vx v8, v8, a14169; CHECK-NEXT:    vse8.v v8, (a0)4170; CHECK-NEXT:    ret4171  %a = load <16 x i8>, ptr %x4172  %b = insertelement <16 x i8> poison, i8 %y, i32 04173  %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer4174  %d = sub <16 x i8> %c, %a4175  store <16 x i8> %d, ptr %x4176  ret void4177}4178 4179define void @sub_xv_v8i16(ptr %x, i16 %y) {4180; CHECK-LABEL: sub_xv_v8i16:4181; CHECK:       # %bb.0:4182; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma4183; CHECK-NEXT:    vle16.v v8, (a0)4184; CHECK-NEXT:    vrsub.vx v8, v8, a14185; CHECK-NEXT:    vse16.v v8, (a0)4186; CHECK-NEXT:    ret4187  %a = load <8 x i16>, ptr %x4188  %b = insertelement <8 x i16> poison, i16 %y, i32 04189  %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer4190  %d = sub <8 x i16> %c, %a4191  store <8 x i16> %d, ptr %x4192  ret void4193}4194 4195define void @sub_xv_v4i32(ptr %x, i32 %y) {4196; CHECK-LABEL: sub_xv_v4i32:4197; CHECK:       # %bb.0:4198; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma4199; CHECK-NEXT:    vle32.v v8, (a0)4200; CHECK-NEXT:    vrsub.vx v8, v8, a14201; CHECK-NEXT:    vse32.v v8, (a0)4202; CHECK-NEXT:    ret4203  %a = load <4 x i32>, ptr %x4204  %b = insertelement <4 x i32> poison, i32 %y, i32 04205  %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer4206  %d = sub <4 x i32> %c, %a4207  store <4 x i32> %d, ptr %x4208  ret void4209}4210 4211define void @mul_vx_v16i8(ptr %x, i8 %y) {4212; CHECK-LABEL: mul_vx_v16i8:4213; CHECK:       # %bb.0:4214; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma4215; CHECK-NEXT:    vle8.v v8, (a0)4216; CHECK-NEXT:    vmul.vx v8, v8, a14217; CHECK-NEXT:    vse8.v v8, (a0)4218; CHECK-NEXT:    ret4219  %a = load <16 x i8>, ptr %x4220  %b = insertelement <16 x i8> poison, i8 %y, i32 04221  %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer4222  %d = mul <16 x i8> %a, %c4223  store <16 x i8> %d, ptr %x4224  ret void4225}4226 4227define void @mul_vx_v8i16(ptr %x, i16 %y) {4228; CHECK-LABEL: mul_vx_v8i16:4229; CHECK:       # %bb.0:4230; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma4231; CHECK-NEXT:    vle16.v v8, (a0)4232; CHECK-NEXT:    vmul.vx v8, v8, a14233; CHECK-NEXT:    vse16.v v8, (a0)4234; CHECK-NEXT:    ret4235  %a = load <8 x i16>, ptr %x4236  %b = insertelement <8 x i16> poison, i16 %y, i32 04237  %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer4238  %d = mul <8 x i16> %a, %c4239  store <8 x i16> %d, ptr %x4240  ret void4241}4242 4243define void @mul_vx_v4i32(ptr %x, i32 %y) {4244; CHECK-LABEL: mul_vx_v4i32:4245; CHECK:       # %bb.0:4246; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma4247; CHECK-NEXT:    vle32.v v8, (a0)4248; CHECK-NEXT:    vmul.vx v8, v8, a14249; CHECK-NEXT:    vse32.v v8, (a0)4250; CHECK-NEXT:    ret4251  %a = load <4 x i32>, ptr %x4252  %b = insertelement <4 x i32> poison, i32 %y, i32 04253  %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer4254  %d = mul <4 x i32> %a, %c4255  store <4 x i32> %d, ptr %x4256  ret void4257}4258 4259define void @mul_xv_v16i8(ptr %x, i8 %y) {4260; CHECK-LABEL: mul_xv_v16i8:4261; CHECK:       # %bb.0:4262; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma4263; CHECK-NEXT:    vle8.v v8, (a0)4264; CHECK-NEXT:    vmul.vx v8, v8, a14265; CHECK-NEXT:    vse8.v v8, (a0)4266; CHECK-NEXT:    ret4267  %a = load <16 x i8>, ptr %x4268  %b = insertelement <16 x i8> poison, i8 %y, i32 04269  %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer4270  %d = mul <16 x i8> %c, %a4271  store <16 x i8> %d, ptr %x4272  ret void4273}4274 4275define void @mul_xv_v8i16(ptr %x, i16 %y) {4276; CHECK-LABEL: mul_xv_v8i16:4277; CHECK:       # %bb.0:4278; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma4279; CHECK-NEXT:    vle16.v v8, (a0)4280; CHECK-NEXT:    vmul.vx v8, v8, a14281; CHECK-NEXT:    vse16.v v8, (a0)4282; CHECK-NEXT:    ret4283  %a = load <8 x i16>, ptr %x4284  %b = insertelement <8 x i16> poison, i16 %y, i32 04285  %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer4286  %d = mul <8 x i16> %c, %a4287  store <8 x i16> %d, ptr %x4288  ret void4289}4290 4291define void @mul_xv_v4i32(ptr %x, i32 %y) {4292; CHECK-LABEL: mul_xv_v4i32:4293; CHECK:       # %bb.0:4294; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma4295; CHECK-NEXT:    vle32.v v8, (a0)4296; CHECK-NEXT:    vmul.vx v8, v8, a14297; CHECK-NEXT:    vse32.v v8, (a0)4298; CHECK-NEXT:    ret4299  %a = load <4 x i32>, ptr %x4300  %b = insertelement <4 x i32> poison, i32 %y, i32 04301  %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer4302  %d = mul <4 x i32> %c, %a4303  store <4 x i32> %d, ptr %x4304  ret void4305}4306 4307define void @and_vi_v16i8(ptr %x) {4308; CHECK-LABEL: and_vi_v16i8:4309; CHECK:       # %bb.0:4310; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma4311; CHECK-NEXT:    vle8.v v8, (a0)4312; CHECK-NEXT:    vand.vi v8, v8, -24313; CHECK-NEXT:    vse8.v v8, (a0)4314; CHECK-NEXT:    ret4315  %a = load <16 x i8>, ptr %x4316  %d = and <16 x i8> %a, splat (i8 -2)4317  store <16 x i8> %d, ptr %x4318  ret void4319}4320 4321define void @and_vi_v8i16(ptr %x) {4322; CHECK-LABEL: and_vi_v8i16:4323; CHECK:       # %bb.0:4324; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma4325; CHECK-NEXT:    vle16.v v8, (a0)4326; CHECK-NEXT:    vand.vi v8, v8, -24327; CHECK-NEXT:    vse16.v v8, (a0)4328; CHECK-NEXT:    ret4329  %a = load <8 x i16>, ptr %x4330  %d = and <8 x i16> %a, splat (i16 -2)4331  store <8 x i16> %d, ptr %x4332  ret void4333}4334 4335define void @and_vi_v4i32(ptr %x) {4336; CHECK-LABEL: and_vi_v4i32:4337; CHECK:       # %bb.0:4338; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma4339; CHECK-NEXT:    vle32.v v8, (a0)4340; CHECK-NEXT:    vand.vi v8, v8, -24341; CHECK-NEXT:    vse32.v v8, (a0)4342; CHECK-NEXT:    ret4343  %a = load <4 x i32>, ptr %x4344  %d = and <4 x i32> %a, splat (i32 -2)4345  store <4 x i32> %d, ptr %x4346  ret void4347}4348 4349define void @and_vi_v2i64(ptr %x) {4350; CHECK-LABEL: and_vi_v2i64:4351; CHECK:       # %bb.0:4352; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma4353; CHECK-NEXT:    vle64.v v8, (a0)4354; CHECK-NEXT:    vand.vi v8, v8, -24355; CHECK-NEXT:    vse64.v v8, (a0)4356; CHECK-NEXT:    ret4357  %a = load <2 x i64>, ptr %x4358  %d = and <2 x i64> %a, splat (i64 -2)4359  store <2 x i64> %d, ptr %x4360  ret void4361}4362 4363define void @and_iv_v16i8(ptr %x) {4364; CHECK-LABEL: and_iv_v16i8:4365; CHECK:       # %bb.0:4366; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma4367; CHECK-NEXT:    vle8.v v8, (a0)4368; CHECK-NEXT:    vand.vi v8, v8, 14369; CHECK-NEXT:    vse8.v v8, (a0)4370; CHECK-NEXT:    ret4371  %a = load <16 x i8>, ptr %x4372  %d = and <16 x i8> splat (i8 1), %a4373  store <16 x i8> %d, ptr %x4374  ret void4375}4376 4377define void @and_iv_v8i16(ptr %x) {4378; CHECK-LABEL: and_iv_v8i16:4379; CHECK:       # %bb.0:4380; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma4381; CHECK-NEXT:    vle16.v v8, (a0)4382; CHECK-NEXT:    vand.vi v8, v8, 14383; CHECK-NEXT:    vse16.v v8, (a0)4384; CHECK-NEXT:    ret4385  %a = load <8 x i16>, ptr %x4386  %d = and <8 x i16> splat (i16 1), %a4387  store <8 x i16> %d, ptr %x4388  ret void4389}4390 4391define void @and_iv_v4i32(ptr %x) {4392; CHECK-LABEL: and_iv_v4i32:4393; CHECK:       # %bb.0:4394; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma4395; CHECK-NEXT:    vle32.v v8, (a0)4396; CHECK-NEXT:    vand.vi v8, v8, 14397; CHECK-NEXT:    vse32.v v8, (a0)4398; CHECK-NEXT:    ret4399  %a = load <4 x i32>, ptr %x4400  %d = and <4 x i32> splat (i32 1), %a4401  store <4 x i32> %d, ptr %x4402  ret void4403}4404 4405define void @and_iv_v2i64(ptr %x) {4406; CHECK-LABEL: and_iv_v2i64:4407; CHECK:       # %bb.0:4408; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma4409; CHECK-NEXT:    vle64.v v8, (a0)4410; CHECK-NEXT:    vand.vi v8, v8, 14411; CHECK-NEXT:    vse64.v v8, (a0)4412; CHECK-NEXT:    ret4413  %a = load <2 x i64>, ptr %x4414  %d = and <2 x i64> splat (i64 1), %a4415  store <2 x i64> %d, ptr %x4416  ret void4417}4418 4419define void @and_vx_v16i8(ptr %x, i8 %y) {4420; CHECK-LABEL: and_vx_v16i8:4421; CHECK:       # %bb.0:4422; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma4423; CHECK-NEXT:    vle8.v v8, (a0)4424; CHECK-NEXT:    vand.vx v8, v8, a14425; CHECK-NEXT:    vse8.v v8, (a0)4426; CHECK-NEXT:    ret4427  %a = load <16 x i8>, ptr %x4428  %b = insertelement <16 x i8> poison, i8 %y, i32 04429  %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer4430  %d = and <16 x i8> %a, %c4431  store <16 x i8> %d, ptr %x4432  ret void4433}4434 4435define void @and_vx_v8i16(ptr %x, i16 %y) {4436; CHECK-LABEL: and_vx_v8i16:4437; CHECK:       # %bb.0:4438; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma4439; CHECK-NEXT:    vle16.v v8, (a0)4440; CHECK-NEXT:    vand.vx v8, v8, a14441; CHECK-NEXT:    vse16.v v8, (a0)4442; CHECK-NEXT:    ret4443  %a = load <8 x i16>, ptr %x4444  %b = insertelement <8 x i16> poison, i16 %y, i32 04445  %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer4446  %d = and <8 x i16> %a, %c4447  store <8 x i16> %d, ptr %x4448  ret void4449}4450 4451define void @and_vx_v4i32(ptr %x, i32 %y) {4452; CHECK-LABEL: and_vx_v4i32:4453; CHECK:       # %bb.0:4454; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma4455; CHECK-NEXT:    vle32.v v8, (a0)4456; CHECK-NEXT:    vand.vx v8, v8, a14457; CHECK-NEXT:    vse32.v v8, (a0)4458; CHECK-NEXT:    ret4459  %a = load <4 x i32>, ptr %x4460  %b = insertelement <4 x i32> poison, i32 %y, i32 04461  %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer4462  %d = and <4 x i32> %a, %c4463  store <4 x i32> %d, ptr %x4464  ret void4465}4466 4467define void @and_xv_v16i8(ptr %x, i8 %y) {4468; CHECK-LABEL: and_xv_v16i8:4469; CHECK:       # %bb.0:4470; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma4471; CHECK-NEXT:    vle8.v v8, (a0)4472; CHECK-NEXT:    vand.vx v8, v8, a14473; CHECK-NEXT:    vse8.v v8, (a0)4474; CHECK-NEXT:    ret4475  %a = load <16 x i8>, ptr %x4476  %b = insertelement <16 x i8> poison, i8 %y, i32 04477  %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer4478  %d = and <16 x i8> %c, %a4479  store <16 x i8> %d, ptr %x4480  ret void4481}4482 4483define void @and_xv_v8i16(ptr %x, i16 %y) {4484; CHECK-LABEL: and_xv_v8i16:4485; CHECK:       # %bb.0:4486; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma4487; CHECK-NEXT:    vle16.v v8, (a0)4488; CHECK-NEXT:    vand.vx v8, v8, a14489; CHECK-NEXT:    vse16.v v8, (a0)4490; CHECK-NEXT:    ret4491  %a = load <8 x i16>, ptr %x4492  %b = insertelement <8 x i16> poison, i16 %y, i32 04493  %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer4494  %d = and <8 x i16> %c, %a4495  store <8 x i16> %d, ptr %x4496  ret void4497}4498 4499define void @and_xv_v4i32(ptr %x, i32 %y) {4500; CHECK-LABEL: and_xv_v4i32:4501; CHECK:       # %bb.0:4502; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma4503; CHECK-NEXT:    vle32.v v8, (a0)4504; CHECK-NEXT:    vand.vx v8, v8, a14505; CHECK-NEXT:    vse32.v v8, (a0)4506; CHECK-NEXT:    ret4507  %a = load <4 x i32>, ptr %x4508  %b = insertelement <4 x i32> poison, i32 %y, i32 04509  %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer4510  %d = and <4 x i32> %c, %a4511  store <4 x i32> %d, ptr %x4512  ret void4513}4514 4515define void @or_vi_v16i8(ptr %x) {4516; CHECK-LABEL: or_vi_v16i8:4517; CHECK:       # %bb.0:4518; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma4519; CHECK-NEXT:    vle8.v v8, (a0)4520; CHECK-NEXT:    vor.vi v8, v8, -24521; CHECK-NEXT:    vse8.v v8, (a0)4522; CHECK-NEXT:    ret4523  %a = load <16 x i8>, ptr %x4524  %d = or <16 x i8> %a, splat (i8 -2)4525  store <16 x i8> %d, ptr %x4526  ret void4527}4528 4529define void @or_vi_v8i16(ptr %x) {4530; CHECK-LABEL: or_vi_v8i16:4531; CHECK:       # %bb.0:4532; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma4533; CHECK-NEXT:    vle16.v v8, (a0)4534; CHECK-NEXT:    vor.vi v8, v8, -24535; CHECK-NEXT:    vse16.v v8, (a0)4536; CHECK-NEXT:    ret4537  %a = load <8 x i16>, ptr %x4538  %d = or <8 x i16> %a, splat (i16 -2)4539  store <8 x i16> %d, ptr %x4540  ret void4541}4542 4543define void @or_vi_v4i32(ptr %x) {4544; CHECK-LABEL: or_vi_v4i32:4545; CHECK:       # %bb.0:4546; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma4547; CHECK-NEXT:    vle32.v v8, (a0)4548; CHECK-NEXT:    vor.vi v8, v8, -24549; CHECK-NEXT:    vse32.v v8, (a0)4550; CHECK-NEXT:    ret4551  %a = load <4 x i32>, ptr %x4552  %d = or <4 x i32> %a, splat (i32 -2)4553  store <4 x i32> %d, ptr %x4554  ret void4555}4556 4557define void @or_vi_v2i64(ptr %x) {4558; CHECK-LABEL: or_vi_v2i64:4559; CHECK:       # %bb.0:4560; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma4561; CHECK-NEXT:    vle64.v v8, (a0)4562; CHECK-NEXT:    vor.vi v8, v8, -24563; CHECK-NEXT:    vse64.v v8, (a0)4564; CHECK-NEXT:    ret4565  %a = load <2 x i64>, ptr %x4566  %d = or <2 x i64> %a, splat (i64 -2)4567  store <2 x i64> %d, ptr %x4568  ret void4569}4570 4571define void @or_iv_v16i8(ptr %x) {4572; CHECK-LABEL: or_iv_v16i8:4573; CHECK:       # %bb.0:4574; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma4575; CHECK-NEXT:    vle8.v v8, (a0)4576; CHECK-NEXT:    vor.vi v8, v8, 14577; CHECK-NEXT:    vse8.v v8, (a0)4578; CHECK-NEXT:    ret4579  %a = load <16 x i8>, ptr %x4580  %d = or <16 x i8> splat (i8 1), %a4581  store <16 x i8> %d, ptr %x4582  ret void4583}4584 4585define void @or_iv_v8i16(ptr %x) {4586; CHECK-LABEL: or_iv_v8i16:4587; CHECK:       # %bb.0:4588; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma4589; CHECK-NEXT:    vle16.v v8, (a0)4590; CHECK-NEXT:    vor.vi v8, v8, 14591; CHECK-NEXT:    vse16.v v8, (a0)4592; CHECK-NEXT:    ret4593  %a = load <8 x i16>, ptr %x4594  %d = or <8 x i16> splat (i16 1), %a4595  store <8 x i16> %d, ptr %x4596  ret void4597}4598 4599define void @or_iv_v4i32(ptr %x) {4600; CHECK-LABEL: or_iv_v4i32:4601; CHECK:       # %bb.0:4602; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma4603; CHECK-NEXT:    vle32.v v8, (a0)4604; CHECK-NEXT:    vor.vi v8, v8, 14605; CHECK-NEXT:    vse32.v v8, (a0)4606; CHECK-NEXT:    ret4607  %a = load <4 x i32>, ptr %x4608  %d = or <4 x i32> splat (i32 1), %a4609  store <4 x i32> %d, ptr %x4610  ret void4611}4612 4613define void @or_iv_v2i64(ptr %x) {4614; CHECK-LABEL: or_iv_v2i64:4615; CHECK:       # %bb.0:4616; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma4617; CHECK-NEXT:    vle64.v v8, (a0)4618; CHECK-NEXT:    vor.vi v8, v8, 14619; CHECK-NEXT:    vse64.v v8, (a0)4620; CHECK-NEXT:    ret4621  %a = load <2 x i64>, ptr %x4622  %d = or <2 x i64> splat (i64 1), %a4623  store <2 x i64> %d, ptr %x4624  ret void4625}4626 4627define void @or_vx_v16i8(ptr %x, i8 %y) {4628; CHECK-LABEL: or_vx_v16i8:4629; CHECK:       # %bb.0:4630; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma4631; CHECK-NEXT:    vle8.v v8, (a0)4632; CHECK-NEXT:    vor.vx v8, v8, a14633; CHECK-NEXT:    vse8.v v8, (a0)4634; CHECK-NEXT:    ret4635  %a = load <16 x i8>, ptr %x4636  %b = insertelement <16 x i8> poison, i8 %y, i32 04637  %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer4638  %d = or <16 x i8> %a, %c4639  store <16 x i8> %d, ptr %x4640  ret void4641}4642 4643define void @or_vx_v8i16(ptr %x, i16 %y) {4644; CHECK-LABEL: or_vx_v8i16:4645; CHECK:       # %bb.0:4646; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma4647; CHECK-NEXT:    vle16.v v8, (a0)4648; CHECK-NEXT:    vor.vx v8, v8, a14649; CHECK-NEXT:    vse16.v v8, (a0)4650; CHECK-NEXT:    ret4651  %a = load <8 x i16>, ptr %x4652  %b = insertelement <8 x i16> poison, i16 %y, i32 04653  %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer4654  %d = or <8 x i16> %a, %c4655  store <8 x i16> %d, ptr %x4656  ret void4657}4658 4659define void @or_vx_v4i32(ptr %x, i32 %y) {4660; CHECK-LABEL: or_vx_v4i32:4661; CHECK:       # %bb.0:4662; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma4663; CHECK-NEXT:    vle32.v v8, (a0)4664; CHECK-NEXT:    vor.vx v8, v8, a14665; CHECK-NEXT:    vse32.v v8, (a0)4666; CHECK-NEXT:    ret4667  %a = load <4 x i32>, ptr %x4668  %b = insertelement <4 x i32> poison, i32 %y, i32 04669  %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer4670  %d = or <4 x i32> %a, %c4671  store <4 x i32> %d, ptr %x4672  ret void4673}4674 4675define void @or_xv_v16i8(ptr %x, i8 %y) {4676; CHECK-LABEL: or_xv_v16i8:4677; CHECK:       # %bb.0:4678; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma4679; CHECK-NEXT:    vle8.v v8, (a0)4680; CHECK-NEXT:    vor.vx v8, v8, a14681; CHECK-NEXT:    vse8.v v8, (a0)4682; CHECK-NEXT:    ret4683  %a = load <16 x i8>, ptr %x4684  %b = insertelement <16 x i8> poison, i8 %y, i32 04685  %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer4686  %d = or <16 x i8> %c, %a4687  store <16 x i8> %d, ptr %x4688  ret void4689}4690 4691define void @or_xv_v8i16(ptr %x, i16 %y) {4692; CHECK-LABEL: or_xv_v8i16:4693; CHECK:       # %bb.0:4694; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma4695; CHECK-NEXT:    vle16.v v8, (a0)4696; CHECK-NEXT:    vor.vx v8, v8, a14697; CHECK-NEXT:    vse16.v v8, (a0)4698; CHECK-NEXT:    ret4699  %a = load <8 x i16>, ptr %x4700  %b = insertelement <8 x i16> poison, i16 %y, i32 04701  %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer4702  %d = or <8 x i16> %c, %a4703  store <8 x i16> %d, ptr %x4704  ret void4705}4706 4707define void @or_xv_v4i32(ptr %x, i32 %y) {4708; CHECK-LABEL: or_xv_v4i32:4709; CHECK:       # %bb.0:4710; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma4711; CHECK-NEXT:    vle32.v v8, (a0)4712; CHECK-NEXT:    vor.vx v8, v8, a14713; CHECK-NEXT:    vse32.v v8, (a0)4714; CHECK-NEXT:    ret4715  %a = load <4 x i32>, ptr %x4716  %b = insertelement <4 x i32> poison, i32 %y, i32 04717  %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer4718  %d = or <4 x i32> %c, %a4719  store <4 x i32> %d, ptr %x4720  ret void4721}4722 4723define void @xor_vi_v16i8(ptr %x) {4724; CHECK-LABEL: xor_vi_v16i8:4725; CHECK:       # %bb.0:4726; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma4727; CHECK-NEXT:    vle8.v v8, (a0)4728; CHECK-NEXT:    vnot.v v8, v84729; CHECK-NEXT:    vse8.v v8, (a0)4730; CHECK-NEXT:    ret4731  %a = load <16 x i8>, ptr %x4732  %d = xor <16 x i8> %a, splat (i8 -1)4733  store <16 x i8> %d, ptr %x4734  ret void4735}4736 4737define void @xor_vi_v8i16(ptr %x) {4738; CHECK-LABEL: xor_vi_v8i16:4739; CHECK:       # %bb.0:4740; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma4741; CHECK-NEXT:    vle16.v v8, (a0)4742; CHECK-NEXT:    vnot.v v8, v84743; CHECK-NEXT:    vse16.v v8, (a0)4744; CHECK-NEXT:    ret4745  %a = load <8 x i16>, ptr %x4746  %d = xor <8 x i16> %a, splat (i16 -1)4747  store <8 x i16> %d, ptr %x4748  ret void4749}4750 4751define void @xor_vi_v4i32(ptr %x) {4752; CHECK-LABEL: xor_vi_v4i32:4753; CHECK:       # %bb.0:4754; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma4755; CHECK-NEXT:    vle32.v v8, (a0)4756; CHECK-NEXT:    vnot.v v8, v84757; CHECK-NEXT:    vse32.v v8, (a0)4758; CHECK-NEXT:    ret4759  %a = load <4 x i32>, ptr %x4760  %d = xor <4 x i32> %a, splat (i32 -1)4761  store <4 x i32> %d, ptr %x4762  ret void4763}4764 4765define void @xor_vi_v2i64(ptr %x) {4766; CHECK-LABEL: xor_vi_v2i64:4767; CHECK:       # %bb.0:4768; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma4769; CHECK-NEXT:    vle64.v v8, (a0)4770; CHECK-NEXT:    vnot.v v8, v84771; CHECK-NEXT:    vse64.v v8, (a0)4772; CHECK-NEXT:    ret4773  %a = load <2 x i64>, ptr %x4774  %d = xor <2 x i64> %a, splat (i64 -1)4775  store <2 x i64> %d, ptr %x4776  ret void4777}4778 4779define void @xor_iv_v16i8(ptr %x) {4780; CHECK-LABEL: xor_iv_v16i8:4781; CHECK:       # %bb.0:4782; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma4783; CHECK-NEXT:    vle8.v v8, (a0)4784; CHECK-NEXT:    vxor.vi v8, v8, 14785; CHECK-NEXT:    vse8.v v8, (a0)4786; CHECK-NEXT:    ret4787  %a = load <16 x i8>, ptr %x4788  %d = xor <16 x i8> splat (i8 1), %a4789  store <16 x i8> %d, ptr %x4790  ret void4791}4792 4793define void @xor_iv_v8i16(ptr %x) {4794; CHECK-LABEL: xor_iv_v8i16:4795; CHECK:       # %bb.0:4796; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma4797; CHECK-NEXT:    vle16.v v8, (a0)4798; CHECK-NEXT:    vxor.vi v8, v8, 14799; CHECK-NEXT:    vse16.v v8, (a0)4800; CHECK-NEXT:    ret4801  %a = load <8 x i16>, ptr %x4802  %d = xor <8 x i16> splat (i16 1), %a4803  store <8 x i16> %d, ptr %x4804  ret void4805}4806 4807define void @xor_iv_v4i32(ptr %x) {4808; CHECK-LABEL: xor_iv_v4i32:4809; CHECK:       # %bb.0:4810; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma4811; CHECK-NEXT:    vle32.v v8, (a0)4812; CHECK-NEXT:    vxor.vi v8, v8, 14813; CHECK-NEXT:    vse32.v v8, (a0)4814; CHECK-NEXT:    ret4815  %a = load <4 x i32>, ptr %x4816  %d = xor <4 x i32> splat (i32 1), %a4817  store <4 x i32> %d, ptr %x4818  ret void4819}4820 4821define void @xor_iv_v2i64(ptr %x) {4822; CHECK-LABEL: xor_iv_v2i64:4823; CHECK:       # %bb.0:4824; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma4825; CHECK-NEXT:    vle64.v v8, (a0)4826; CHECK-NEXT:    vxor.vi v8, v8, 14827; CHECK-NEXT:    vse64.v v8, (a0)4828; CHECK-NEXT:    ret4829  %a = load <2 x i64>, ptr %x4830  %d = xor <2 x i64> splat (i64 1), %a4831  store <2 x i64> %d, ptr %x4832  ret void4833}4834 4835define void @xor_vx_v16i8(ptr %x, i8 %y) {4836; CHECK-LABEL: xor_vx_v16i8:4837; CHECK:       # %bb.0:4838; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma4839; CHECK-NEXT:    vle8.v v8, (a0)4840; CHECK-NEXT:    vxor.vx v8, v8, a14841; CHECK-NEXT:    vse8.v v8, (a0)4842; CHECK-NEXT:    ret4843  %a = load <16 x i8>, ptr %x4844  %b = insertelement <16 x i8> poison, i8 %y, i32 04845  %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer4846  %d = xor <16 x i8> %a, %c4847  store <16 x i8> %d, ptr %x4848  ret void4849}4850 4851define void @xor_vx_v8i16(ptr %x, i16 %y) {4852; CHECK-LABEL: xor_vx_v8i16:4853; CHECK:       # %bb.0:4854; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma4855; CHECK-NEXT:    vle16.v v8, (a0)4856; CHECK-NEXT:    vxor.vx v8, v8, a14857; CHECK-NEXT:    vse16.v v8, (a0)4858; CHECK-NEXT:    ret4859  %a = load <8 x i16>, ptr %x4860  %b = insertelement <8 x i16> poison, i16 %y, i32 04861  %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer4862  %d = xor <8 x i16> %a, %c4863  store <8 x i16> %d, ptr %x4864  ret void4865}4866 4867define void @xor_vx_v4i32(ptr %x, i32 %y) {4868; CHECK-LABEL: xor_vx_v4i32:4869; CHECK:       # %bb.0:4870; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma4871; CHECK-NEXT:    vle32.v v8, (a0)4872; CHECK-NEXT:    vxor.vx v8, v8, a14873; CHECK-NEXT:    vse32.v v8, (a0)4874; CHECK-NEXT:    ret4875  %a = load <4 x i32>, ptr %x4876  %b = insertelement <4 x i32> poison, i32 %y, i32 04877  %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer4878  %d = xor <4 x i32> %a, %c4879  store <4 x i32> %d, ptr %x4880  ret void4881}4882 4883define void @xor_xv_v16i8(ptr %x, i8 %y) {4884; CHECK-LABEL: xor_xv_v16i8:4885; CHECK:       # %bb.0:4886; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma4887; CHECK-NEXT:    vle8.v v8, (a0)4888; CHECK-NEXT:    vxor.vx v8, v8, a14889; CHECK-NEXT:    vse8.v v8, (a0)4890; CHECK-NEXT:    ret4891  %a = load <16 x i8>, ptr %x4892  %b = insertelement <16 x i8> poison, i8 %y, i32 04893  %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer4894  %d = xor <16 x i8> %c, %a4895  store <16 x i8> %d, ptr %x4896  ret void4897}4898 4899define void @xor_xv_v8i16(ptr %x, i16 %y) {4900; CHECK-LABEL: xor_xv_v8i16:4901; CHECK:       # %bb.0:4902; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma4903; CHECK-NEXT:    vle16.v v8, (a0)4904; CHECK-NEXT:    vxor.vx v8, v8, a14905; CHECK-NEXT:    vse16.v v8, (a0)4906; CHECK-NEXT:    ret4907  %a = load <8 x i16>, ptr %x4908  %b = insertelement <8 x i16> poison, i16 %y, i32 04909  %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer4910  %d = xor <8 x i16> %c, %a4911  store <8 x i16> %d, ptr %x4912  ret void4913}4914 4915define void @xor_xv_v4i32(ptr %x, i32 %y) {4916; CHECK-LABEL: xor_xv_v4i32:4917; CHECK:       # %bb.0:4918; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma4919; CHECK-NEXT:    vle32.v v8, (a0)4920; CHECK-NEXT:    vxor.vx v8, v8, a14921; CHECK-NEXT:    vse32.v v8, (a0)4922; CHECK-NEXT:    ret4923  %a = load <4 x i32>, ptr %x4924  %b = insertelement <4 x i32> poison, i32 %y, i32 04925  %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer4926  %d = xor <4 x i32> %c, %a4927  store <4 x i32> %d, ptr %x4928  ret void4929}4930 4931define void @lshr_vi_v16i8(ptr %x) {4932; CHECK-LABEL: lshr_vi_v16i8:4933; CHECK:       # %bb.0:4934; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma4935; CHECK-NEXT:    vle8.v v8, (a0)4936; CHECK-NEXT:    vsrl.vi v8, v8, 74937; CHECK-NEXT:    vse8.v v8, (a0)4938; CHECK-NEXT:    ret4939  %a = load <16 x i8>, ptr %x4940  %d = lshr <16 x i8> %a, splat (i8 7)4941  store <16 x i8> %d, ptr %x4942  ret void4943}4944 4945define void @lshr_vi_v8i16(ptr %x) {4946; CHECK-LABEL: lshr_vi_v8i16:4947; CHECK:       # %bb.0:4948; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma4949; CHECK-NEXT:    vle16.v v8, (a0)4950; CHECK-NEXT:    vsrl.vi v8, v8, 154951; CHECK-NEXT:    vse16.v v8, (a0)4952; CHECK-NEXT:    ret4953  %a = load <8 x i16>, ptr %x4954  %d = lshr <8 x i16> %a, splat (i16 15)4955  store <8 x i16> %d, ptr %x4956  ret void4957}4958 4959define void @lshr_vi_v4i32(ptr %x) {4960; CHECK-LABEL: lshr_vi_v4i32:4961; CHECK:       # %bb.0:4962; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma4963; CHECK-NEXT:    vle32.v v8, (a0)4964; CHECK-NEXT:    vsrl.vi v8, v8, 314965; CHECK-NEXT:    vse32.v v8, (a0)4966; CHECK-NEXT:    ret4967  %a = load <4 x i32>, ptr %x4968  %d = lshr <4 x i32> %a, splat (i32 31)4969  store <4 x i32> %d, ptr %x4970  ret void4971}4972 4973define void @lshr_vi_v2i64(ptr %x) {4974; CHECK-LABEL: lshr_vi_v2i64:4975; CHECK:       # %bb.0:4976; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma4977; CHECK-NEXT:    vle64.v v8, (a0)4978; CHECK-NEXT:    vsrl.vi v8, v8, 314979; CHECK-NEXT:    vse64.v v8, (a0)4980; CHECK-NEXT:    ret4981  %a = load <2 x i64>, ptr %x4982  %d = lshr <2 x i64> %a, splat (i64 31)4983  store <2 x i64> %d, ptr %x4984  ret void4985}4986 4987define void @lshr_vx_v16i8(ptr %x, i8 %y) {4988; CHECK-LABEL: lshr_vx_v16i8:4989; CHECK:       # %bb.0:4990; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma4991; CHECK-NEXT:    vle8.v v8, (a0)4992; CHECK-NEXT:    vsrl.vx v8, v8, a14993; CHECK-NEXT:    vse8.v v8, (a0)4994; CHECK-NEXT:    ret4995  %a = load <16 x i8>, ptr %x4996  %b = insertelement <16 x i8> poison, i8 %y, i32 04997  %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer4998  %d = lshr <16 x i8> %a, %c4999  store <16 x i8> %d, ptr %x5000  ret void5001}5002 5003define void @lshr_vx_v8i16(ptr %x, i16 %y) {5004; CHECK-LABEL: lshr_vx_v8i16:5005; CHECK:       # %bb.0:5006; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma5007; CHECK-NEXT:    vle16.v v8, (a0)5008; CHECK-NEXT:    vsrl.vx v8, v8, a15009; CHECK-NEXT:    vse16.v v8, (a0)5010; CHECK-NEXT:    ret5011  %a = load <8 x i16>, ptr %x5012  %b = insertelement <8 x i16> poison, i16 %y, i32 05013  %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer5014  %d = lshr <8 x i16> %a, %c5015  store <8 x i16> %d, ptr %x5016  ret void5017}5018 5019define void @lshr_vx_v4i32(ptr %x, i32 %y) {5020; CHECK-LABEL: lshr_vx_v4i32:5021; CHECK:       # %bb.0:5022; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma5023; CHECK-NEXT:    vle32.v v8, (a0)5024; CHECK-NEXT:    vsrl.vx v8, v8, a15025; CHECK-NEXT:    vse32.v v8, (a0)5026; CHECK-NEXT:    ret5027  %a = load <4 x i32>, ptr %x5028  %b = insertelement <4 x i32> poison, i32 %y, i32 05029  %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer5030  %d = lshr <4 x i32> %a, %c5031  store <4 x i32> %d, ptr %x5032  ret void5033}5034 5035define void @ashr_vi_v16i8(ptr %x) {5036; CHECK-LABEL: ashr_vi_v16i8:5037; CHECK:       # %bb.0:5038; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma5039; CHECK-NEXT:    vle8.v v8, (a0)5040; CHECK-NEXT:    vsra.vi v8, v8, 75041; CHECK-NEXT:    vse8.v v8, (a0)5042; CHECK-NEXT:    ret5043  %a = load <16 x i8>, ptr %x5044  %d = ashr <16 x i8> %a, splat (i8 7)5045  store <16 x i8> %d, ptr %x5046  ret void5047}5048 5049define void @ashr_vi_v8i16(ptr %x) {5050; CHECK-LABEL: ashr_vi_v8i16:5051; CHECK:       # %bb.0:5052; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma5053; CHECK-NEXT:    vle16.v v8, (a0)5054; CHECK-NEXT:    vsra.vi v8, v8, 155055; CHECK-NEXT:    vse16.v v8, (a0)5056; CHECK-NEXT:    ret5057  %a = load <8 x i16>, ptr %x5058  %d = ashr <8 x i16> %a, splat (i16 15)5059  store <8 x i16> %d, ptr %x5060  ret void5061}5062 5063define void @ashr_vi_v4i32(ptr %x) {5064; CHECK-LABEL: ashr_vi_v4i32:5065; CHECK:       # %bb.0:5066; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma5067; CHECK-NEXT:    vle32.v v8, (a0)5068; CHECK-NEXT:    vsra.vi v8, v8, 315069; CHECK-NEXT:    vse32.v v8, (a0)5070; CHECK-NEXT:    ret5071  %a = load <4 x i32>, ptr %x5072  %d = ashr <4 x i32> %a, splat (i32 31)5073  store <4 x i32> %d, ptr %x5074  ret void5075}5076 5077define void @ashr_vi_v2i64(ptr %x) {5078; CHECK-LABEL: ashr_vi_v2i64:5079; CHECK:       # %bb.0:5080; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma5081; CHECK-NEXT:    vle64.v v8, (a0)5082; CHECK-NEXT:    vsra.vi v8, v8, 315083; CHECK-NEXT:    vse64.v v8, (a0)5084; CHECK-NEXT:    ret5085  %a = load <2 x i64>, ptr %x5086  %d = ashr <2 x i64> %a, splat (i64 31)5087  store <2 x i64> %d, ptr %x5088  ret void5089}5090 5091define void @ashr_vx_v16i8(ptr %x, i8 %y) {5092; CHECK-LABEL: ashr_vx_v16i8:5093; CHECK:       # %bb.0:5094; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma5095; CHECK-NEXT:    vle8.v v8, (a0)5096; CHECK-NEXT:    vsra.vx v8, v8, a15097; CHECK-NEXT:    vse8.v v8, (a0)5098; CHECK-NEXT:    ret5099  %a = load <16 x i8>, ptr %x5100  %b = insertelement <16 x i8> poison, i8 %y, i32 05101  %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer5102  %d = ashr <16 x i8> %a, %c5103  store <16 x i8> %d, ptr %x5104  ret void5105}5106 5107define void @ashr_vx_v8i16(ptr %x, i16 %y) {5108; CHECK-LABEL: ashr_vx_v8i16:5109; CHECK:       # %bb.0:5110; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma5111; CHECK-NEXT:    vle16.v v8, (a0)5112; CHECK-NEXT:    vsra.vx v8, v8, a15113; CHECK-NEXT:    vse16.v v8, (a0)5114; CHECK-NEXT:    ret5115  %a = load <8 x i16>, ptr %x5116  %b = insertelement <8 x i16> poison, i16 %y, i32 05117  %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer5118  %d = ashr <8 x i16> %a, %c5119  store <8 x i16> %d, ptr %x5120  ret void5121}5122 5123define void @ashr_vx_v4i32(ptr %x, i32 %y) {5124; CHECK-LABEL: ashr_vx_v4i32:5125; CHECK:       # %bb.0:5126; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma5127; CHECK-NEXT:    vle32.v v8, (a0)5128; CHECK-NEXT:    vsra.vx v8, v8, a15129; CHECK-NEXT:    vse32.v v8, (a0)5130; CHECK-NEXT:    ret5131  %a = load <4 x i32>, ptr %x5132  %b = insertelement <4 x i32> poison, i32 %y, i32 05133  %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer5134  %d = ashr <4 x i32> %a, %c5135  store <4 x i32> %d, ptr %x5136  ret void5137}5138 5139define void @shl_vi_v16i8(ptr %x) {5140; CHECK-LABEL: shl_vi_v16i8:5141; CHECK:       # %bb.0:5142; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma5143; CHECK-NEXT:    vle8.v v8, (a0)5144; CHECK-NEXT:    vsll.vi v8, v8, 75145; CHECK-NEXT:    vse8.v v8, (a0)5146; CHECK-NEXT:    ret5147  %a = load <16 x i8>, ptr %x5148  %d = shl <16 x i8> %a, splat (i8 7)5149  store <16 x i8> %d, ptr %x5150  ret void5151}5152 5153define void @shl_vi_v8i16(ptr %x) {5154; CHECK-LABEL: shl_vi_v8i16:5155; CHECK:       # %bb.0:5156; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma5157; CHECK-NEXT:    vle16.v v8, (a0)5158; CHECK-NEXT:    vsll.vi v8, v8, 155159; CHECK-NEXT:    vse16.v v8, (a0)5160; CHECK-NEXT:    ret5161  %a = load <8 x i16>, ptr %x5162  %d = shl <8 x i16> %a, splat (i16 15)5163  store <8 x i16> %d, ptr %x5164  ret void5165}5166 5167define void @shl_vi_v4i32(ptr %x) {5168; CHECK-LABEL: shl_vi_v4i32:5169; CHECK:       # %bb.0:5170; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma5171; CHECK-NEXT:    vle32.v v8, (a0)5172; CHECK-NEXT:    vsll.vi v8, v8, 315173; CHECK-NEXT:    vse32.v v8, (a0)5174; CHECK-NEXT:    ret5175  %a = load <4 x i32>, ptr %x5176  %d = shl <4 x i32> %a, splat (i32 31)5177  store <4 x i32> %d, ptr %x5178  ret void5179}5180 5181define void @shl_vi_v2i64(ptr %x) {5182; CHECK-LABEL: shl_vi_v2i64:5183; CHECK:       # %bb.0:5184; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma5185; CHECK-NEXT:    vle64.v v8, (a0)5186; CHECK-NEXT:    vsll.vi v8, v8, 315187; CHECK-NEXT:    vse64.v v8, (a0)5188; CHECK-NEXT:    ret5189  %a = load <2 x i64>, ptr %x5190  %d = shl <2 x i64> %a, splat (i64 31)5191  store <2 x i64> %d, ptr %x5192  ret void5193}5194 5195define void @shl_vx_v16i8(ptr %x, i8 %y) {5196; CHECK-LABEL: shl_vx_v16i8:5197; CHECK:       # %bb.0:5198; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma5199; CHECK-NEXT:    vle8.v v8, (a0)5200; CHECK-NEXT:    vsll.vx v8, v8, a15201; CHECK-NEXT:    vse8.v v8, (a0)5202; CHECK-NEXT:    ret5203  %a = load <16 x i8>, ptr %x5204  %b = insertelement <16 x i8> poison, i8 %y, i32 05205  %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer5206  %d = shl <16 x i8> %a, %c5207  store <16 x i8> %d, ptr %x5208  ret void5209}5210 5211define void @shl_vx_v8i16(ptr %x, i16 %y) {5212; CHECK-LABEL: shl_vx_v8i16:5213; CHECK:       # %bb.0:5214; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma5215; CHECK-NEXT:    vle16.v v8, (a0)5216; CHECK-NEXT:    vsll.vx v8, v8, a15217; CHECK-NEXT:    vse16.v v8, (a0)5218; CHECK-NEXT:    ret5219  %a = load <8 x i16>, ptr %x5220  %b = insertelement <8 x i16> poison, i16 %y, i32 05221  %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer5222  %d = shl <8 x i16> %a, %c5223  store <8 x i16> %d, ptr %x5224  ret void5225}5226 5227define void @shl_vx_v4i32(ptr %x, i32 %y) {5228; CHECK-LABEL: shl_vx_v4i32:5229; CHECK:       # %bb.0:5230; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma5231; CHECK-NEXT:    vle32.v v8, (a0)5232; CHECK-NEXT:    vsll.vx v8, v8, a15233; CHECK-NEXT:    vse32.v v8, (a0)5234; CHECK-NEXT:    ret5235  %a = load <4 x i32>, ptr %x5236  %b = insertelement <4 x i32> poison, i32 %y, i32 05237  %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer5238  %d = shl <4 x i32> %a, %c5239  store <4 x i32> %d, ptr %x5240  ret void5241}5242 5243define void @sdiv_vx_v16i8(ptr %x, i8 %y) {5244; CHECK-LABEL: sdiv_vx_v16i8:5245; CHECK:       # %bb.0:5246; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma5247; CHECK-NEXT:    vle8.v v8, (a0)5248; CHECK-NEXT:    vdiv.vx v8, v8, a15249; CHECK-NEXT:    vse8.v v8, (a0)5250; CHECK-NEXT:    ret5251  %a = load <16 x i8>, ptr %x5252  %b = insertelement <16 x i8> poison, i8 %y, i32 05253  %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer5254  %d = sdiv <16 x i8> %a, %c5255  store <16 x i8> %d, ptr %x5256  ret void5257}5258 5259define void @sdiv_vx_v8i16(ptr %x, i16 %y) {5260; CHECK-LABEL: sdiv_vx_v8i16:5261; CHECK:       # %bb.0:5262; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma5263; CHECK-NEXT:    vle16.v v8, (a0)5264; CHECK-NEXT:    vdiv.vx v8, v8, a15265; CHECK-NEXT:    vse16.v v8, (a0)5266; CHECK-NEXT:    ret5267  %a = load <8 x i16>, ptr %x5268  %b = insertelement <8 x i16> poison, i16 %y, i32 05269  %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer5270  %d = sdiv <8 x i16> %a, %c5271  store <8 x i16> %d, ptr %x5272  ret void5273}5274 5275define void @sdiv_vx_v4i32(ptr %x, i32 %y) {5276; CHECK-LABEL: sdiv_vx_v4i32:5277; CHECK:       # %bb.0:5278; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma5279; CHECK-NEXT:    vle32.v v8, (a0)5280; CHECK-NEXT:    vdiv.vx v8, v8, a15281; CHECK-NEXT:    vse32.v v8, (a0)5282; CHECK-NEXT:    ret5283  %a = load <4 x i32>, ptr %x5284  %b = insertelement <4 x i32> poison, i32 %y, i32 05285  %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer5286  %d = sdiv <4 x i32> %a, %c5287  store <4 x i32> %d, ptr %x5288  ret void5289}5290 5291define void @srem_vx_v16i8(ptr %x, i8 %y) {5292; CHECK-LABEL: srem_vx_v16i8:5293; CHECK:       # %bb.0:5294; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma5295; CHECK-NEXT:    vle8.v v8, (a0)5296; CHECK-NEXT:    vrem.vx v8, v8, a15297; CHECK-NEXT:    vse8.v v8, (a0)5298; CHECK-NEXT:    ret5299  %a = load <16 x i8>, ptr %x5300  %b = insertelement <16 x i8> poison, i8 %y, i32 05301  %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer5302  %d = srem <16 x i8> %a, %c5303  store <16 x i8> %d, ptr %x5304  ret void5305}5306 5307define void @srem_vx_v8i16(ptr %x, i16 %y) {5308; CHECK-LABEL: srem_vx_v8i16:5309; CHECK:       # %bb.0:5310; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma5311; CHECK-NEXT:    vle16.v v8, (a0)5312; CHECK-NEXT:    vrem.vx v8, v8, a15313; CHECK-NEXT:    vse16.v v8, (a0)5314; CHECK-NEXT:    ret5315  %a = load <8 x i16>, ptr %x5316  %b = insertelement <8 x i16> poison, i16 %y, i32 05317  %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer5318  %d = srem <8 x i16> %a, %c5319  store <8 x i16> %d, ptr %x5320  ret void5321}5322 5323define void @srem_vx_v4i32(ptr %x, i32 %y) {5324; CHECK-LABEL: srem_vx_v4i32:5325; CHECK:       # %bb.0:5326; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma5327; CHECK-NEXT:    vle32.v v8, (a0)5328; CHECK-NEXT:    vrem.vx v8, v8, a15329; CHECK-NEXT:    vse32.v v8, (a0)5330; CHECK-NEXT:    ret5331  %a = load <4 x i32>, ptr %x5332  %b = insertelement <4 x i32> poison, i32 %y, i32 05333  %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer5334  %d = srem <4 x i32> %a, %c5335  store <4 x i32> %d, ptr %x5336  ret void5337}5338 5339define void @udiv_vx_v16i8(ptr %x, i8 %y) {5340; CHECK-LABEL: udiv_vx_v16i8:5341; CHECK:       # %bb.0:5342; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma5343; CHECK-NEXT:    vle8.v v8, (a0)5344; CHECK-NEXT:    vdivu.vx v8, v8, a15345; CHECK-NEXT:    vse8.v v8, (a0)5346; CHECK-NEXT:    ret5347  %a = load <16 x i8>, ptr %x5348  %b = insertelement <16 x i8> poison, i8 %y, i32 05349  %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer5350  %d = udiv <16 x i8> %a, %c5351  store <16 x i8> %d, ptr %x5352  ret void5353}5354 5355define void @udiv_vx_v8i16(ptr %x, i16 %y) {5356; CHECK-LABEL: udiv_vx_v8i16:5357; CHECK:       # %bb.0:5358; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma5359; CHECK-NEXT:    vle16.v v8, (a0)5360; CHECK-NEXT:    vdivu.vx v8, v8, a15361; CHECK-NEXT:    vse16.v v8, (a0)5362; CHECK-NEXT:    ret5363  %a = load <8 x i16>, ptr %x5364  %b = insertelement <8 x i16> poison, i16 %y, i32 05365  %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer5366  %d = udiv <8 x i16> %a, %c5367  store <8 x i16> %d, ptr %x5368  ret void5369}5370 5371define void @udiv_vx_v4i32(ptr %x, i32 %y) {5372; CHECK-LABEL: udiv_vx_v4i32:5373; CHECK:       # %bb.0:5374; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma5375; CHECK-NEXT:    vle32.v v8, (a0)5376; CHECK-NEXT:    vdivu.vx v8, v8, a15377; CHECK-NEXT:    vse32.v v8, (a0)5378; CHECK-NEXT:    ret5379  %a = load <4 x i32>, ptr %x5380  %b = insertelement <4 x i32> poison, i32 %y, i32 05381  %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer5382  %d = udiv <4 x i32> %a, %c5383  store <4 x i32> %d, ptr %x5384  ret void5385}5386 5387define void @urem_vx_v16i8(ptr %x, i8 %y) {5388; CHECK-LABEL: urem_vx_v16i8:5389; CHECK:       # %bb.0:5390; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma5391; CHECK-NEXT:    vle8.v v8, (a0)5392; CHECK-NEXT:    vremu.vx v8, v8, a15393; CHECK-NEXT:    vse8.v v8, (a0)5394; CHECK-NEXT:    ret5395  %a = load <16 x i8>, ptr %x5396  %b = insertelement <16 x i8> poison, i8 %y, i32 05397  %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer5398  %d = urem <16 x i8> %a, %c5399  store <16 x i8> %d, ptr %x5400  ret void5401}5402 5403define void @urem_vx_v8i16(ptr %x, i16 %y) {5404; CHECK-LABEL: urem_vx_v8i16:5405; CHECK:       # %bb.0:5406; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma5407; CHECK-NEXT:    vle16.v v8, (a0)5408; CHECK-NEXT:    vremu.vx v8, v8, a15409; CHECK-NEXT:    vse16.v v8, (a0)5410; CHECK-NEXT:    ret5411  %a = load <8 x i16>, ptr %x5412  %b = insertelement <8 x i16> poison, i16 %y, i32 05413  %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer5414  %d = urem <8 x i16> %a, %c5415  store <8 x i16> %d, ptr %x5416  ret void5417}5418 5419define void @urem_vx_v4i32(ptr %x, i32 %y) {5420; CHECK-LABEL: urem_vx_v4i32:5421; CHECK:       # %bb.0:5422; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma5423; CHECK-NEXT:    vle32.v v8, (a0)5424; CHECK-NEXT:    vremu.vx v8, v8, a15425; CHECK-NEXT:    vse32.v v8, (a0)5426; CHECK-NEXT:    ret5427  %a = load <4 x i32>, ptr %x5428  %b = insertelement <4 x i32> poison, i32 %y, i32 05429  %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer5430  %d = urem <4 x i32> %a, %c5431  store <4 x i32> %d, ptr %x5432  ret void5433}5434 5435define void @mulhu_vx_v16i8(ptr %x) {5436; CHECK-LABEL: mulhu_vx_v16i8:5437; CHECK:       # %bb.0:5438; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma5439; CHECK-NEXT:    vle8.v v8, (a0)5440; CHECK-NEXT:    li a1, 575441; CHECK-NEXT:    vmulhu.vx v8, v8, a15442; CHECK-NEXT:    vsrl.vi v8, v8, 15443; CHECK-NEXT:    vse8.v v8, (a0)5444; CHECK-NEXT:    ret5445  %a = load <16 x i8>, ptr %x5446  %b = udiv <16 x i8> %a, <i8 9, i8 9, i8 9, i8 9, i8 9, i8 9, i8 9, i8 9, i8 9, i8 9, i8 9, i8 9, i8 9, i8 9, i8 9, i8 9>5447  store <16 x i8> %b, ptr %x5448  ret void5449}5450 5451define void @mulhu_vx_v8i16(ptr %x) {5452; CHECK-LABEL: mulhu_vx_v8i16:5453; CHECK:       # %bb.0:5454; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma5455; CHECK-NEXT:    vle16.v v8, (a0)5456; CHECK-NEXT:    lui a1, 25457; CHECK-NEXT:    addi a1, a1, 11715458; CHECK-NEXT:    vmulhu.vx v9, v8, a15459; CHECK-NEXT:    vsub.vv v8, v8, v95460; CHECK-NEXT:    vsrl.vi v8, v8, 15461; CHECK-NEXT:    vadd.vv v8, v8, v95462; CHECK-NEXT:    vsrl.vi v8, v8, 25463; CHECK-NEXT:    vse16.v v8, (a0)5464; CHECK-NEXT:    ret5465  %a = load <8 x i16>, ptr %x5466  %b = udiv <8 x i16> %a, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>5467  store <8 x i16> %b, ptr %x5468  ret void5469}5470 5471define void @mulhu_vx_v4i32(ptr %x) {5472; CHECK-LABEL: mulhu_vx_v4i32:5473; CHECK:       # %bb.0:5474; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma5475; CHECK-NEXT:    vle32.v v8, (a0)5476; CHECK-NEXT:    lui a1, 8388615477; CHECK-NEXT:    addi a1, a1, -8195478; CHECK-NEXT:    vmulhu.vx v8, v8, a15479; CHECK-NEXT:    vsrl.vi v8, v8, 25480; CHECK-NEXT:    vse32.v v8, (a0)5481; CHECK-NEXT:    ret5482  %a = load <4 x i32>, ptr %x5483  %b = udiv <4 x i32> %a, <i32 5, i32 5, i32 5, i32 5>5484  store <4 x i32> %b, ptr %x5485  ret void5486}5487 5488define void @mulhu_vx_v2i64(ptr %x) {5489; RV32-LABEL: mulhu_vx_v2i64:5490; RV32:       # %bb.0:5491; RV32-NEXT:    addi sp, sp, -165492; RV32-NEXT:    .cfi_def_cfa_offset 165493; RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, ma5494; RV32-NEXT:    vle64.v v8, (a0)5495; RV32-NEXT:    lui a1, 6990515496; RV32-NEXT:    addi a2, a1, -13665497; RV32-NEXT:    addi a1, a1, -13655498; RV32-NEXT:    sw a1, 8(sp)5499; RV32-NEXT:    sw a2, 12(sp)5500; RV32-NEXT:    addi a1, sp, 85501; RV32-NEXT:    vlse64.v v9, (a1), zero5502; RV32-NEXT:    vmulhu.vv v8, v8, v95503; RV32-NEXT:    vsrl.vi v8, v8, 15504; RV32-NEXT:    vse64.v v8, (a0)5505; RV32-NEXT:    addi sp, sp, 165506; RV32-NEXT:    .cfi_def_cfa_offset 05507; RV32-NEXT:    ret5508;5509; RV64-LABEL: mulhu_vx_v2i64:5510; RV64:       # %bb.0:5511; RV64-NEXT:    vsetivli zero, 2, e64, m1, ta, ma5512; RV64-NEXT:    vle64.v v8, (a0)5513; RV64-NEXT:    lui a1, 6990515514; RV64-NEXT:    addi a1, a1, -13655515; RV64-NEXT:    slli a2, a1, 325516; RV64-NEXT:    add a1, a1, a25517; RV64-NEXT:    vmulhu.vx v8, v8, a15518; RV64-NEXT:    vsrl.vi v8, v8, 15519; RV64-NEXT:    vse64.v v8, (a0)5520; RV64-NEXT:    ret5521  %a = load <2 x i64>, ptr %x5522  %b = udiv <2 x i64> %a, <i64 3, i64 3>5523  store <2 x i64> %b, ptr %x5524  ret void5525}5526 5527define void @mulhs_vx_v16i8(ptr %x) {5528; CHECK-LABEL: mulhs_vx_v16i8:5529; CHECK:       # %bb.0:5530; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma5531; CHECK-NEXT:    vle8.v v8, (a0)5532; CHECK-NEXT:    li a1, -1235533; CHECK-NEXT:    vmulhu.vx v8, v8, a15534; CHECK-NEXT:    vsrl.vi v8, v8, 75535; CHECK-NEXT:    vse8.v v8, (a0)5536; CHECK-NEXT:    ret5537  %a = load <16 x i8>, ptr %x5538  %b = udiv <16 x i8> %a, <i8 -9, i8 -9, i8 -9, i8 -9, i8 -9, i8 -9, i8 -9, i8 -9, i8 -9, i8 -9, i8 -9, i8 -9, i8 -9, i8 -9, i8 -9, i8 -9>5539  store <16 x i8> %b, ptr %x5540  ret void5541}5542 5543define void @mulhs_vx_v8i16(ptr %x) {5544; CHECK-LABEL: mulhs_vx_v8i16:5545; CHECK:       # %bb.0:5546; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma5547; CHECK-NEXT:    vle16.v v8, (a0)5548; CHECK-NEXT:    lui a1, 55549; CHECK-NEXT:    addi a1, a1, -17555550; CHECK-NEXT:    vmulh.vx v8, v8, a15551; CHECK-NEXT:    vsra.vi v8, v8, 15552; CHECK-NEXT:    vsrl.vi v9, v8, 155553; CHECK-NEXT:    vadd.vv v8, v8, v95554; CHECK-NEXT:    vse16.v v8, (a0)5555; CHECK-NEXT:    ret5556  %a = load <8 x i16>, ptr %x5557  %b = sdiv <8 x i16> %a, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>5558  store <8 x i16> %b, ptr %x5559  ret void5560}5561 5562define void @mulhs_vx_v4i32(ptr %x) {5563; RV32-LABEL: mulhs_vx_v4i32:5564; RV32:       # %bb.0:5565; RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, ma5566; RV32-NEXT:    vle32.v v8, (a0)5567; RV32-NEXT:    lui a1, 6291465568; RV32-NEXT:    addi a1, a1, -16395569; RV32-NEXT:    vmulh.vx v8, v8, a15570; RV32-NEXT:    vsrl.vi v9, v8, 315571; RV32-NEXT:    vsra.vi v8, v8, 15572; RV32-NEXT:    vadd.vv v8, v8, v95573; RV32-NEXT:    vse32.v v8, (a0)5574; RV32-NEXT:    ret5575;5576; RV64-LABEL: mulhs_vx_v4i32:5577; RV64:       # %bb.0:5578; RV64-NEXT:    vsetivli zero, 4, e32, m1, ta, ma5579; RV64-NEXT:    vle32.v v8, (a0)5580; RV64-NEXT:    lui a1, 6291465581; RV64-NEXT:    addi a1, a1, -16395582; RV64-NEXT:    vmulh.vx v8, v8, a15583; RV64-NEXT:    vsra.vi v8, v8, 15584; RV64-NEXT:    vsrl.vi v9, v8, 315585; RV64-NEXT:    vadd.vv v8, v8, v95586; RV64-NEXT:    vse32.v v8, (a0)5587; RV64-NEXT:    ret5588  %a = load <4 x i32>, ptr %x5589  %b = sdiv <4 x i32> %a, <i32 -5, i32 -5, i32 -5, i32 -5>5590  store <4 x i32> %b, ptr %x5591  ret void5592}5593 5594define void @mulhs_vx_v2i64(ptr %x) {5595; RV32-LABEL: mulhs_vx_v2i64:5596; RV32:       # %bb.0:5597; RV32-NEXT:    addi sp, sp, -165598; RV32-NEXT:    .cfi_def_cfa_offset 165599; RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, ma5600; RV32-NEXT:    vle64.v v8, (a0)5601; RV32-NEXT:    lui a1, 3495255602; RV32-NEXT:    addi a2, sp, 85603; RV32-NEXT:    addi a3, a1, 13655604; RV32-NEXT:    addi a1, a1, 13665605; RV32-NEXT:    sw a1, 8(sp)5606; RV32-NEXT:    sw a3, 12(sp)5607; RV32-NEXT:    vlse64.v v9, (a2), zero5608; RV32-NEXT:    vmulh.vv v8, v8, v95609; RV32-NEXT:    li a1, 635610; RV32-NEXT:    vsrl.vx v9, v8, a15611; RV32-NEXT:    vadd.vv v8, v8, v95612; RV32-NEXT:    vse64.v v8, (a0)5613; RV32-NEXT:    addi sp, sp, 165614; RV32-NEXT:    .cfi_def_cfa_offset 05615; RV32-NEXT:    ret5616;5617; RV64-LABEL: mulhs_vx_v2i64:5618; RV64:       # %bb.0:5619; RV64-NEXT:    vsetivli zero, 2, e64, m1, ta, ma5620; RV64-NEXT:    vle64.v v8, (a0)5621; RV64-NEXT:    lui a1, %hi(.LCPI321_0)5622; RV64-NEXT:    ld a1, %lo(.LCPI321_0)(a1)5623; RV64-NEXT:    vmulh.vx v8, v8, a15624; RV64-NEXT:    li a1, 635625; RV64-NEXT:    vsrl.vx v9, v8, a15626; RV64-NEXT:    vadd.vv v8, v8, v95627; RV64-NEXT:    vse64.v v8, (a0)5628; RV64-NEXT:    ret5629  %a = load <2 x i64>, ptr %x5630  %b = sdiv <2 x i64> %a, <i64 3, i64 3>5631  store <2 x i64> %b, ptr %x5632  ret void5633}5634 5635define void @madd_vv_v2i64(ptr %x, <2 x i64> %y) {5636; CHECK-LABEL: madd_vv_v2i64:5637; CHECK:       # %bb.0:5638; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma5639; CHECK-NEXT:    vle64.v v9, (a0)5640; CHECK-NEXT:    vmadd.vv v9, v8, v85641; CHECK-NEXT:    vse64.v v9, (a0)5642; CHECK-NEXT:    ret5643  %a = load <2 x i64>, ptr %x5644  %b = add <2 x i64> %a, <i64 1, i64 1>5645  %c = mul <2 x i64> %b, %y5646  store <2 x i64> %c, ptr %x5647  ret void5648}5649 5650define void @madd_vv_v2i64_2(ptr %x, <2 x i64> %y) {5651; CHECK-LABEL: madd_vv_v2i64_2:5652; CHECK:       # %bb.0:5653; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma5654; CHECK-NEXT:    vle64.v v9, (a0)5655; CHECK-NEXT:    vmadd.vv v9, v8, v85656; CHECK-NEXT:    vse64.v v9, (a0)5657; CHECK-NEXT:    ret5658  %a = load <2 x i64>, ptr %x5659  %b = add <2 x i64> %a, <i64 1, i64 1>5660  %c = mul <2 x i64> %y, %b5661  store <2 x i64> %c, ptr %x5662  ret void5663}5664 5665define void @msub_vv_v2i64(ptr %x, <2 x i64> %y) {5666; CHECK-LABEL: msub_vv_v2i64:5667; CHECK:       # %bb.0:5668; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma5669; CHECK-NEXT:    vle64.v v9, (a0)5670; CHECK-NEXT:    vnmsub.vv v9, v8, v85671; CHECK-NEXT:    vse64.v v9, (a0)5672; CHECK-NEXT:    ret5673  %a = load <2 x i64>, ptr %x5674  %b = sub <2 x i64> <i64 1, i64 1>, %a5675  %c = mul <2 x i64> %b, %y5676  store <2 x i64> %c, ptr %x5677  ret void5678}5679 5680define void @msub_vv_v2i64_2(ptr %x, <2 x i64> %y) {5681; CHECK-LABEL: msub_vv_v2i64_2:5682; CHECK:       # %bb.0:5683; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma5684; CHECK-NEXT:    vle64.v v9, (a0)5685; CHECK-NEXT:    vnmsub.vv v9, v8, v85686; CHECK-NEXT:    vse64.v v9, (a0)5687; CHECK-NEXT:    ret5688  %a = load <2 x i64>, ptr %x5689  %b = sub <2 x i64> <i64 1, i64 1>, %a5690  %c = mul <2 x i64> %y, %b5691  store <2 x i64> %c, ptr %x5692  ret void5693}5694 5695define <8 x i8> @vsub_if_uge_v8i8(<8 x i8> %va, <8 x i8> %vb) {5696; CHECK-LABEL: vsub_if_uge_v8i8:5697; CHECK:       # %bb.0:5698; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma5699; CHECK-NEXT:    vsub.vv v9, v8, v95700; CHECK-NEXT:    vminu.vv v8, v8, v95701; CHECK-NEXT:    ret5702  %cmp = icmp ult <8 x i8> %va, %vb5703  %select = select <8 x i1> %cmp, <8 x i8> zeroinitializer, <8 x i8> %vb5704  %sub = sub nuw <8 x i8> %va, %select5705  ret <8 x i8> %sub5706}5707 5708define <8 x i8> @vsub_if_uge_swapped_v8i8(<8 x i8> %va, <8 x i8> %vb) {5709; CHECK-LABEL: vsub_if_uge_swapped_v8i8:5710; CHECK:       # %bb.0:5711; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma5712; CHECK-NEXT:    vsub.vv v9, v8, v95713; CHECK-NEXT:    vminu.vv v8, v8, v95714; CHECK-NEXT:    ret5715  %cmp = icmp uge <8 x i8> %va, %vb5716  %select = select <8 x i1> %cmp, <8 x i8> %vb, <8 x i8> zeroinitializer5717  %sub = sub nuw <8 x i8> %va, %select5718  ret <8 x i8> %sub5719}5720 5721define <8 x i16> @vsub_if_uge_v8i16(<8 x i16> %va, <8 x i16> %vb) {5722; CHECK-LABEL: vsub_if_uge_v8i16:5723; CHECK:       # %bb.0:5724; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma5725; CHECK-NEXT:    vsub.vv v9, v8, v95726; CHECK-NEXT:    vminu.vv v8, v8, v95727; CHECK-NEXT:    ret5728  %cmp = icmp ult <8 x i16> %va, %vb5729  %select = select <8 x i1> %cmp, <8 x i16> zeroinitializer, <8 x i16> %vb5730  %sub = sub nuw <8 x i16> %va, %select5731  ret <8 x i16> %sub5732}5733 5734define <8 x i16> @vsub_if_uge_swapped_v8i16(<8 x i16> %va, <8 x i16> %vb) {5735; CHECK-LABEL: vsub_if_uge_swapped_v8i16:5736; CHECK:       # %bb.0:5737; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma5738; CHECK-NEXT:    vsub.vv v9, v8, v95739; CHECK-NEXT:    vminu.vv v8, v8, v95740; CHECK-NEXT:    ret5741  %cmp = icmp uge <8 x i16> %va, %vb5742  %select = select <8 x i1> %cmp, <8 x i16> %vb, <8 x i16> zeroinitializer5743  %sub = sub nuw <8 x i16> %va, %select5744  ret <8 x i16> %sub5745}5746 5747define <4 x i32> @vsub_if_uge_v4i32(<4 x i32> %va, <4 x i32> %vb) {5748; CHECK-LABEL: vsub_if_uge_v4i32:5749; CHECK:       # %bb.0:5750; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma5751; CHECK-NEXT:    vsub.vv v9, v8, v95752; CHECK-NEXT:    vminu.vv v8, v8, v95753; CHECK-NEXT:    ret5754  %cmp = icmp ult <4 x i32> %va, %vb5755  %select = select <4 x i1> %cmp, <4 x i32> zeroinitializer, <4 x i32> %vb5756  %sub = sub nuw <4 x i32> %va, %select5757  ret <4 x i32> %sub5758}5759 5760define <4 x i32> @vsub_if_uge_swapped_v4i32(<4 x i32> %va, <4 x i32> %vb) {5761; CHECK-LABEL: vsub_if_uge_swapped_v4i32:5762; CHECK:       # %bb.0:5763; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma5764; CHECK-NEXT:    vsub.vv v9, v8, v95765; CHECK-NEXT:    vminu.vv v8, v8, v95766; CHECK-NEXT:    ret5767  %cmp = icmp uge <4 x i32> %va, %vb5768  %select = select <4 x i1> %cmp, <4 x i32> %vb, <4 x i32> zeroinitializer5769  %sub = sub nuw <4 x i32> %va, %select5770  ret <4 x i32> %sub5771}5772 5773define <2 x i64> @vsub_if_uge_v2i64(<2 x i64> %va, <2 x i64> %vb) {5774; CHECK-LABEL: vsub_if_uge_v2i64:5775; CHECK:       # %bb.0:5776; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma5777; CHECK-NEXT:    vsub.vv v9, v8, v95778; CHECK-NEXT:    vminu.vv v8, v8, v95779; CHECK-NEXT:    ret5780  %cmp = icmp ult <2 x i64> %va, %vb5781  %select = select <2 x i1> %cmp, <2 x i64> zeroinitializer, <2 x i64> %vb5782  %sub = sub nuw <2 x i64> %va, %select5783  ret <2 x i64> %sub5784}5785 5786define <2 x i64> @vsub_if_uge_swapped_v2i64(<2 x i64> %va, <2 x i64> %vb) {5787; CHECK-LABEL: vsub_if_uge_swapped_v2i64:5788; CHECK:       # %bb.0:5789; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma5790; CHECK-NEXT:    vsub.vv v9, v8, v95791; CHECK-NEXT:    vminu.vv v8, v8, v95792; CHECK-NEXT:    ret5793  %cmp = icmp uge <2 x i64> %va, %vb5794  %select = select <2 x i1> %cmp, <2 x i64> %vb, <2 x i64> zeroinitializer5795  %sub = sub nuw <2 x i64> %va, %select5796  ret <2 x i64> %sub5797}5798 5799define <8 x i8> @sub_if_uge_C_v8i8(<8 x i8> %x) {5800; CHECK-LABEL: sub_if_uge_C_v8i8:5801; CHECK:       # %bb.0:5802; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma5803; CHECK-NEXT:    vadd.vi v9, v8, -135804; CHECK-NEXT:    vminu.vv v8, v9, v85805; CHECK-NEXT:    ret5806  %cmp = icmp ugt <8 x i8> %x, splat (i8 12)5807  %sub = add <8 x i8> %x, splat (i8 -13)5808  %select = select <8 x i1> %cmp, <8 x i8> %sub, <8 x i8> %x5809  ret <8 x i8> %select5810}5811 5812define <8 x i16> @sub_if_uge_C_v8i16(<8 x i16> %x) {5813; CHECK-LABEL: sub_if_uge_C_v8i16:5814; CHECK:       # %bb.0:5815; CHECK-NEXT:    li a0, -20015816; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma5817; CHECK-NEXT:    vadd.vx v9, v8, a05818; CHECK-NEXT:    vminu.vv v8, v9, v85819; CHECK-NEXT:    ret5820  %cmp = icmp ugt <8 x i16> %x, splat (i16 2000)5821  %sub = add <8 x i16> %x, splat (i16 -2001)5822  %select = select <8 x i1> %cmp, <8 x i16> %sub, <8 x i16> %x5823  ret <8 x i16> %select5824}5825 5826define <4 x i32> @sub_if_uge_C_v4i32(<4 x i32> %x) {5827; CHECK-LABEL: sub_if_uge_C_v4i32:5828; CHECK:       # %bb.0:5829; CHECK-NEXT:    lui a0, 10485605830; CHECK-NEXT:    addi a0, a0, 155831; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma5832; CHECK-NEXT:    vadd.vx v9, v8, a05833; CHECK-NEXT:    vminu.vv v8, v9, v85834; CHECK-NEXT:    ret5835  %cmp = icmp ugt <4 x i32> %x, splat (i32 65520)5836  %sub = add <4 x i32> %x, splat (i32 -65521)5837  %select = select <4 x i1> %cmp, <4 x i32> %sub, <4 x i32> %x5838  ret <4 x i32> %select5839}5840 5841define <4 x i32> @sub_if_uge_C_swapped_v4i32(<4 x i32> %x) {5842; CHECK-LABEL: sub_if_uge_C_swapped_v4i32:5843; CHECK:       # %bb.0:5844; CHECK-NEXT:    lui a0, 10485605845; CHECK-NEXT:    addi a0, a0, 155846; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma5847; CHECK-NEXT:    vadd.vx v9, v8, a05848; CHECK-NEXT:    vminu.vv v8, v8, v95849; CHECK-NEXT:    ret5850  %cmp = icmp ult <4 x i32> %x, splat (i32 65521)5851  %sub = add <4 x i32> %x, splat (i32 -65521)5852  %select = select <4 x i1> %cmp, <4 x i32> %x, <4 x i32> %sub5853  ret <4 x i32> %select5854}5855 5856define <2 x i64> @sub_if_uge_C_v2i64(<2 x i64> %x) nounwind {5857; RV32-LABEL: sub_if_uge_C_v2i64:5858; RV32:       # %bb.0:5859; RV32-NEXT:    addi sp, sp, -165860; RV32-NEXT:    li a0, -25861; RV32-NEXT:    lui a1, 8764495862; RV32-NEXT:    addi a1, a1, -5135863; RV32-NEXT:    sw a1, 8(sp)5864; RV32-NEXT:    sw a0, 12(sp)5865; RV32-NEXT:    addi a0, sp, 85866; RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, ma5867; RV32-NEXT:    vlse64.v v9, (a0), zero5868; RV32-NEXT:    vadd.vv v9, v8, v95869; RV32-NEXT:    vminu.vv v8, v9, v85870; RV32-NEXT:    addi sp, sp, 165871; RV32-NEXT:    ret5872;5873; RV64-LABEL: sub_if_uge_C_v2i64:5874; RV64:       # %bb.0:5875; RV64-NEXT:    lui a0, 10482785876; RV64-NEXT:    addi a0, a0, -955877; RV64-NEXT:    slli a0, a0, 125878; RV64-NEXT:    addi a0, a0, -5135879; RV64-NEXT:    vsetivli zero, 2, e64, m1, ta, ma5880; RV64-NEXT:    vadd.vx v9, v8, a05881; RV64-NEXT:    vminu.vv v8, v9, v85882; RV64-NEXT:    ret5883  %cmp = icmp ugt <2 x i64> %x, splat (i64 5000000000)5884  %sub = add <2 x i64> %x, splat (i64 -5000000001)5885  %select = select <2 x i1> %cmp, <2 x i64> %sub, <2 x i64> %x5886  ret <2 x i64> %select5887}5888