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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvfh,+zvfbfmin | FileCheck %s3; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfh,+zvfbfmin | FileCheck %s4; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvfhmin,+zvfbfmin | FileCheck %s5; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfhmin,+zvfbfmin | FileCheck %s6 7; Integers8 9define void @vector_interleave_store_v32i1_v16i1(<16 x i1> %a, <16 x i1> %b, ptr %p) {10; CHECK-LABEL: vector_interleave_store_v32i1_v16i1:11; CHECK: # %bb.0:12; CHECK-NEXT: li a1, 3213; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma14; CHECK-NEXT: vslideup.vi v0, v8, 215; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma16; CHECK-NEXT: vmv.v.i v8, 017; CHECK-NEXT: vmerge.vim v8, v8, 1, v018; CHECK-NEXT: vsetivli zero, 16, e8, m2, ta, ma19; CHECK-NEXT: vslidedown.vi v10, v8, 1620; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma21; CHECK-NEXT: vwaddu.vv v12, v8, v1022; CHECK-NEXT: li a2, -123; CHECK-NEXT: vwmaccu.vx v12, a2, v1024; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma25; CHECK-NEXT: vmsne.vi v8, v12, 026; CHECK-NEXT: vsm.v v8, (a0)27; CHECK-NEXT: ret28 %res = call <32 x i1> @llvm.vector.interleave2.v32i1(<16 x i1> %a, <16 x i1> %b)29 store <32 x i1> %res, ptr %p30 ret void31}32 33; Shouldn't be lowered to vsseg because it's unaligned34define void @vector_interleave_store_v16i16_v8i16_align1(<8 x i16> %a, <8 x i16> %b, ptr %p) {35; CHECK-LABEL: vector_interleave_store_v16i16_v8i16_align1:36; CHECK: # %bb.0:37; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma38; CHECK-NEXT: vwaddu.vv v10, v8, v939; CHECK-NEXT: li a1, -140; CHECK-NEXT: vwmaccu.vx v10, a1, v941; CHECK-NEXT: li a1, 3242; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma43; CHECK-NEXT: vse8.v v10, (a0)44; CHECK-NEXT: ret45 %res = call <16 x i16> @llvm.vector.interleave2.v16i16(<8 x i16> %a, <8 x i16> %b)46 store <16 x i16> %res, ptr %p, align 147 ret void48}49 50define void @vector_interleave_store_v16i16_v8i16(<8 x i16> %a, <8 x i16> %b, ptr %p) {51; CHECK-LABEL: vector_interleave_store_v16i16_v8i16:52; CHECK: # %bb.0:53; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma54; CHECK-NEXT: vsseg2e16.v v8, (a0)55; CHECK-NEXT: ret56 %res = call <16 x i16> @llvm.vector.interleave2.v16i16(<8 x i16> %a, <8 x i16> %b)57 store <16 x i16> %res, ptr %p58 ret void59}60 61define void @vector_interleave_store_v8i32_v4i32(<4 x i32> %a, <4 x i32> %b, ptr %p) {62; CHECK-LABEL: vector_interleave_store_v8i32_v4i32:63; CHECK: # %bb.0:64; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma65; CHECK-NEXT: vsseg2e32.v v8, (a0)66; CHECK-NEXT: ret67 %res = call <8 x i32> @llvm.vector.interleave2.v8i32(<4 x i32> %a, <4 x i32> %b)68 store <8 x i32> %res, ptr %p69 ret void70}71 72define void @vector_interleave_store_v4i64_v2i64(<2 x i64> %a, <2 x i64> %b, ptr %p) {73; CHECK-LABEL: vector_interleave_store_v4i64_v2i64:74; CHECK: # %bb.0:75; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma76; CHECK-NEXT: vsseg2e64.v v8, (a0)77; CHECK-NEXT: ret78 %res = call <4 x i64> @llvm.vector.interleave2.v4i64(<2 x i64> %a, <2 x i64> %b)79 store <4 x i64> %res, ptr %p80 ret void81}82 83; Floats84 85define void @vector_interleave_store_v4bf16_v2bf16(<2 x bfloat> %a, <2 x bfloat> %b, ptr %p) {86; CHECK-LABEL: vector_interleave_store_v4bf16_v2bf16:87; CHECK: # %bb.0:88; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma89; CHECK-NEXT: vsseg2e16.v v8, (a0)90; CHECK-NEXT: ret91 %res = call <4 x bfloat> @llvm.vector.interleave2.v4bf16(<2 x bfloat> %a, <2 x bfloat> %b)92 store <4 x bfloat> %res, ptr %p93 ret void94}95 96define void @vector_interleave_store_v8bf16_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b, ptr %p) {97; CHECK-LABEL: vector_interleave_store_v8bf16_v4bf16:98; CHECK: # %bb.0:99; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma100; CHECK-NEXT: vsseg2e16.v v8, (a0)101; CHECK-NEXT: ret102 %res = call <8 x bfloat> @llvm.vector.interleave2.v8bf16(<4 x bfloat> %a, <4 x bfloat> %b)103 store <8 x bfloat> %res, ptr %p104 ret void105}106 107define void @vector_interleave_store_v4f16_v2f16(<2 x half> %a, <2 x half> %b, ptr %p) {108; CHECK-LABEL: vector_interleave_store_v4f16_v2f16:109; CHECK: # %bb.0:110; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma111; CHECK-NEXT: vsseg2e16.v v8, (a0)112; CHECK-NEXT: ret113 %res = call <4 x half> @llvm.vector.interleave2.v4f16(<2 x half> %a, <2 x half> %b)114 store <4 x half> %res, ptr %p115 ret void116}117 118define void @vector_interleave_store_v8f16_v4f16(<4 x half> %a, <4 x half> %b, ptr %p) {119; CHECK-LABEL: vector_interleave_store_v8f16_v4f16:120; CHECK: # %bb.0:121; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma122; CHECK-NEXT: vsseg2e16.v v8, (a0)123; CHECK-NEXT: ret124 %res = call <8 x half> @llvm.vector.interleave2.v8f16(<4 x half> %a, <4 x half> %b)125 store <8 x half> %res, ptr %p126 ret void127}128 129define void @vector_interleave_store_v4f32_v2f32(<2 x float> %a, <2 x float> %b, ptr %p) {130; CHECK-LABEL: vector_interleave_store_v4f32_v2f32:131; CHECK: # %bb.0:132; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma133; CHECK-NEXT: vsseg2e32.v v8, (a0)134; CHECK-NEXT: ret135 %res = call <4 x float> @llvm.vector.interleave2.v4f32(<2 x float> %a, <2 x float> %b)136 store <4 x float> %res, ptr %p137 ret void138}139 140define void @vector_interleave_store_v16bf16_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b, ptr %p) {141; CHECK-LABEL: vector_interleave_store_v16bf16_v8bf16:142; CHECK: # %bb.0:143; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma144; CHECK-NEXT: vsseg2e16.v v8, (a0)145; CHECK-NEXT: ret146 %res = call <16 x bfloat> @llvm.vector.interleave2.v16bf16(<8 x bfloat> %a, <8 x bfloat> %b)147 store <16 x bfloat> %res, ptr %p148 ret void149}150 151define void @vector_interleave_store_v16f16_v8f16(<8 x half> %a, <8 x half> %b, ptr %p) {152; CHECK-LABEL: vector_interleave_store_v16f16_v8f16:153; CHECK: # %bb.0:154; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma155; CHECK-NEXT: vsseg2e16.v v8, (a0)156; CHECK-NEXT: ret157 %res = call <16 x half> @llvm.vector.interleave2.v16f16(<8 x half> %a, <8 x half> %b)158 store <16 x half> %res, ptr %p159 ret void160}161 162define void @vector_interleave_store_v8f32_v4f32(<4 x float> %a, <4 x float> %b, ptr %p) {163; CHECK-LABEL: vector_interleave_store_v8f32_v4f32:164; CHECK: # %bb.0:165; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma166; CHECK-NEXT: vsseg2e32.v v8, (a0)167; CHECK-NEXT: ret168 %res = call <8 x float> @llvm.vector.interleave2.v8f32(<4 x float> %a, <4 x float> %b)169 store <8 x float> %res, ptr %p170 ret void171}172 173define void @vector_interleave_store_v4f64_v2f64(<2 x double> %a, <2 x double> %b, ptr %p) {174; CHECK-LABEL: vector_interleave_store_v4f64_v2f64:175; CHECK: # %bb.0:176; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma177; CHECK-NEXT: vsseg2e64.v v8, (a0)178; CHECK-NEXT: ret179 %res = call <4 x double> @llvm.vector.interleave2.v4f64(<2 x double> %a, <2 x double> %b)180 store <4 x double> %res, ptr %p181 ret void182}183 184define void @vector_interleave_store_factor3(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, ptr %p) {185; CHECK-LABEL: vector_interleave_store_factor3:186; CHECK: # %bb.0:187; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma188; CHECK-NEXT: vsseg3e32.v v8, (a0)189; CHECK-NEXT: ret190 %v = call <12 x i32> @llvm.vector.interleave3(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c)191 store <12 x i32> %v, ptr %p192 ret void193}194 195define void @vector_interleave_store_factor4(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d, ptr %p) {196; CHECK-LABEL: vector_interleave_store_factor4:197; CHECK: # %bb.0:198; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma199; CHECK-NEXT: vsseg4e32.v v8, (a0)200; CHECK-NEXT: ret201 %v = call <16 x i32> @llvm.vector.interleave4(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d)202 store <16 x i32> %v, ptr %p203 ret void204}205 206define void @vector_interleave_store_factor5(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d, <4 x i32> %e, ptr %p) {207; CHECK-LABEL: vector_interleave_store_factor5:208; CHECK: # %bb.0:209; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma210; CHECK-NEXT: vsseg5e32.v v8, (a0)211; CHECK-NEXT: ret212 %v = call <20 x i32> @llvm.vector.interleave5(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d, <4 x i32> %e)213 store <20 x i32> %v, ptr %p214 ret void215}216 217define void @vector_interleave_store_factor6(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d, <4 x i32> %e, <4 x i32> %f, ptr %p) {218; CHECK-LABEL: vector_interleave_store_factor6:219; CHECK: # %bb.0:220; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma221; CHECK-NEXT: vsseg6e32.v v8, (a0)222; CHECK-NEXT: ret223 %v = call <24 x i32> @llvm.vector.interleave6(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d, <4 x i32> %e, <4 x i32> %f)224 store <24 x i32> %v, ptr %p225 ret void226}227 228define void @vector_interleave_store_factor7(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d, <4 x i32> %e, <4 x i32> %f, <4 x i32> %g, ptr %p) {229; CHECK-LABEL: vector_interleave_store_factor7:230; CHECK: # %bb.0:231; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma232; CHECK-NEXT: vsseg7e32.v v8, (a0)233; CHECK-NEXT: ret234 %v = call <28 x i32> @llvm.vector.interleave7(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d, <4 x i32> %e, <4 x i32> %f, <4 x i32> %g)235 store <28 x i32> %v, ptr %p236 ret void237}238 239define void @vector_interleave_store_factor8(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d, <4 x i32> %e, <4 x i32> %f, <4 x i32> %g, <4 x i32> %h, ptr %p) {240; CHECK-LABEL: vector_interleave_store_factor8:241; CHECK: # %bb.0:242; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma243; CHECK-NEXT: vsseg8e32.v v8, (a0)244; CHECK-NEXT: ret245 %v = call <32 x i32> @llvm.vector.interleave8(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d, <4 x i32> %e, <4 x i32> %f, <4 x i32> %g, <4 x i32> %h)246 store <32 x i32> %v, ptr %p247 ret void248}249