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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+zve32x,+zvl1024b -O2 | FileCheck %s -check-prefix=ZVE32X3; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+zve64x,+zvl1024b -O2 | FileCheck %s -check-prefix=ZVE64X4 5; TODO: Currently we don't lower interleaved accesses of ptr types if XLEN isn't6; a supported SEW. We should improve this with a wide load and a set of shuffles.7define <4 x i1> @load_large_vector(ptr %p) {8; ZVE32X-LABEL: load_large_vector:9; ZVE32X: # %bb.0:10; ZVE32X-NEXT: ld a1, 0(a0)11; ZVE32X-NEXT: ld a2, 8(a0)12; ZVE32X-NEXT: ld a3, 24(a0)13; ZVE32X-NEXT: ld a4, 32(a0)14; ZVE32X-NEXT: ld a5, 48(a0)15; ZVE32X-NEXT: ld a6, 56(a0)16; ZVE32X-NEXT: ld a7, 72(a0)17; ZVE32X-NEXT: ld a0, 80(a0)18; ZVE32X-NEXT: vsetivli zero, 4, e8, mf4, ta, ma19; ZVE32X-NEXT: vmv.s.x v8, zero20; ZVE32X-NEXT: vmv.v.i v9, 021; ZVE32X-NEXT: xor a3, a3, a422; ZVE32X-NEXT: xor a1, a1, a223; ZVE32X-NEXT: xor a2, a5, a624; ZVE32X-NEXT: xor a0, a7, a025; ZVE32X-NEXT: snez a3, a326; ZVE32X-NEXT: snez a1, a127; ZVE32X-NEXT: vmv.s.x v10, a328; ZVE32X-NEXT: vmv.s.x v11, a129; ZVE32X-NEXT: vsetivli zero, 1, e8, mf4, ta, ma30; ZVE32X-NEXT: vand.vi v10, v10, 131; ZVE32X-NEXT: vmsne.vi v0, v10, 032; ZVE32X-NEXT: vand.vi v10, v11, 133; ZVE32X-NEXT: vmerge.vim v11, v8, 1, v034; ZVE32X-NEXT: vmsne.vi v0, v10, 035; ZVE32X-NEXT: snez a1, a236; ZVE32X-NEXT: vsetivli zero, 4, e8, mf4, ta, ma37; ZVE32X-NEXT: vmerge.vim v10, v9, 1, v038; ZVE32X-NEXT: vsetivli zero, 2, e8, mf4, tu, ma39; ZVE32X-NEXT: vslideup.vi v10, v11, 140; ZVE32X-NEXT: vmv.s.x v11, a141; ZVE32X-NEXT: vsetivli zero, 4, e8, mf4, ta, ma42; ZVE32X-NEXT: vmsne.vi v0, v10, 043; ZVE32X-NEXT: vsetivli zero, 1, e8, mf4, ta, ma44; ZVE32X-NEXT: vand.vi v10, v11, 145; ZVE32X-NEXT: vsetivli zero, 4, e8, mf4, ta, ma46; ZVE32X-NEXT: vmerge.vim v11, v9, 1, v047; ZVE32X-NEXT: vsetivli zero, 1, e8, mf4, ta, ma48; ZVE32X-NEXT: vmsne.vi v0, v10, 049; ZVE32X-NEXT: snez a0, a050; ZVE32X-NEXT: vmerge.vim v10, v8, 1, v051; ZVE32X-NEXT: vsetivli zero, 3, e8, mf4, tu, ma52; ZVE32X-NEXT: vslideup.vi v11, v10, 253; ZVE32X-NEXT: vmv.s.x v10, a054; ZVE32X-NEXT: vsetivli zero, 4, e8, mf4, ta, ma55; ZVE32X-NEXT: vmsne.vi v0, v11, 056; ZVE32X-NEXT: vsetivli zero, 1, e8, mf4, ta, ma57; ZVE32X-NEXT: vand.vi v10, v10, 158; ZVE32X-NEXT: vsetivli zero, 4, e8, mf4, ta, ma59; ZVE32X-NEXT: vmerge.vim v9, v9, 1, v060; ZVE32X-NEXT: vsetivli zero, 1, e8, mf4, ta, ma61; ZVE32X-NEXT: vmsne.vi v0, v10, 062; ZVE32X-NEXT: vmerge.vim v8, v8, 1, v063; ZVE32X-NEXT: vsetivli zero, 4, e8, mf4, ta, ma64; ZVE32X-NEXT: vslideup.vi v9, v8, 365; ZVE32X-NEXT: vmsne.vi v0, v9, 066; ZVE32X-NEXT: ret67;68; ZVE64X-LABEL: load_large_vector:69; ZVE64X: # %bb.0:70; ZVE64X-NEXT: vsetivli zero, 4, e64, m1, ta, ma71; ZVE64X-NEXT: vlseg3e64.v v8, (a0)72; ZVE64X-NEXT: vmsne.vv v0, v8, v973; ZVE64X-NEXT: ret74 %l = load <12 x ptr>, ptr %p75 %s1 = shufflevector <12 x ptr> %l, <12 x ptr> poison, <4 x i32> <i32 0, i32 3, i32 6, i32 9>76 %s2 = shufflevector <12 x ptr> %l, <12 x ptr> poison, <4 x i32> <i32 1, i32 4, i32 7, i32 10>77 %ret = icmp ne <4 x ptr> %s1, %s278 ret <4 x i1> %ret79}80