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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=riscv32 -mattr=+v,m -O2 | FileCheck -check-prefixes=CHECK,RV32 %s3; RUN: llc < %s -mtriple=riscv64 -mattr=+v,m -O2 | FileCheck -check-prefixes=CHECK,RV64 %s4 5; ------------------------------------------------------------------------------6; Loads7; ------------------------------------------------------------------------------8 9; FIXME: This should be widened to a vlseg2 of <4 x i32> with VL set to 310define {<3 x i32>, <3 x i32>} @load_factor2_v3(ptr %ptr) {11; CHECK-LABEL: load_factor2_v3:12; CHECK:       # %bb.0:13; CHECK-NEXT:    vsetivli zero, 6, e32, m2, ta, ma14; CHECK-NEXT:    vle32.v v10, (a0)15; CHECK-NEXT:    li a0, 3216; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma17; CHECK-NEXT:    vnsrl.wx v9, v10, a018; CHECK-NEXT:    vnsrl.wi v8, v10, 019; CHECK-NEXT:    ret20  %interleaved.vec = load <6 x i32>, ptr %ptr21  %v0 = shufflevector <6 x i32> %interleaved.vec, <6 x i32> poison, <3 x i32> <i32 0, i32 2, i32 4>22  %v1 = shufflevector <6 x i32> %interleaved.vec, <6 x i32> poison, <3 x i32> <i32 1, i32 3, i32 5>23  %res0 = insertvalue {<3 x i32>, <3 x i32>} poison, <3 x i32> %v0, 024  %res1 = insertvalue {<3 x i32>, <3 x i32>} %res0, <3 x i32> %v1, 125  ret {<3 x i32>, <3 x i32>} %res126}27 28define {<4 x i32>, <4 x i32>} @load_factor2(ptr %ptr) {29; CHECK-LABEL: load_factor2:30; CHECK:       # %bb.0:31; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma32; CHECK-NEXT:    vlseg2e32.v v8, (a0)33; CHECK-NEXT:    ret34  %interleaved.vec = load <8 x i32>, ptr %ptr35  %v0 = shufflevector <8 x i32> %interleaved.vec, <8 x i32> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>36  %v1 = shufflevector <8 x i32> %interleaved.vec, <8 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>37  %res0 = insertvalue {<4 x i32>, <4 x i32>} poison, <4 x i32> %v0, 038  %res1 = insertvalue {<4 x i32>, <4 x i32>} %res0, <4 x i32> %v1, 139  ret {<4 x i32>, <4 x i32>} %res140}41 42 43define {<4 x i32>, <4 x i32>, <4 x i32>} @load_factor3(ptr %ptr) {44; CHECK-LABEL: load_factor3:45; CHECK:       # %bb.0:46; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma47; CHECK-NEXT:    vlseg3e32.v v8, (a0)48; CHECK-NEXT:    ret49  %interleaved.vec = load <12 x i32>, ptr %ptr50  %v0 = shufflevector <12 x i32> %interleaved.vec, <12 x i32> poison, <4 x i32> <i32 0, i32 3, i32 6, i32 9>51  %v1 = shufflevector <12 x i32> %interleaved.vec, <12 x i32> poison, <4 x i32> <i32 1, i32 4, i32 7, i32 10>52  %v2 = shufflevector <12 x i32> %interleaved.vec, <12 x i32> poison, <4 x i32> <i32 2, i32 5, i32 8, i32 11>53  %res0 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>} poison, <4 x i32> %v0, 054  %res1 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>} %res0, <4 x i32> %v1, 155  %res2 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>} %res1, <4 x i32> %v2, 256  ret {<4 x i32>, <4 x i32>, <4 x i32>} %res257}58 59define {<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>} @load_factor4(ptr %ptr) {60; CHECK-LABEL: load_factor4:61; CHECK:       # %bb.0:62; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma63; CHECK-NEXT:    vlseg4e32.v v8, (a0)64; CHECK-NEXT:    ret65  %interleaved.vec = load <16 x i32>, ptr %ptr66  %v0 = shufflevector <16 x i32> %interleaved.vec, <16 x i32> poison, <4 x i32> <i32 0, i32 4, i32 8, i32 12>67  %v1 = shufflevector <16 x i32> %interleaved.vec, <16 x i32> poison, <4 x i32> <i32 1, i32 5, i32 9, i32 13>68  %v2 = shufflevector <16 x i32> %interleaved.vec, <16 x i32> poison, <4 x i32> <i32 2, i32 6, i32 10, i32 14>69  %v3 = shufflevector <16 x i32> %interleaved.vec, <16 x i32> poison, <4 x i32> <i32 3, i32 7, i32 11, i32 15>70  %res0 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>} poison, <4 x i32> %v0, 071  %res1 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>} %res0, <4 x i32> %v1, 172  %res2 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>} %res1, <4 x i32> %v2, 273  %res3 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>} %res2, <4 x i32> %v3, 374  ret {<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>} %res375}76 77define {<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>} @load_factor5(ptr %ptr) {78; CHECK-LABEL: load_factor5:79; CHECK:       # %bb.0:80; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma81; CHECK-NEXT:    vlseg5e32.v v8, (a0)82; CHECK-NEXT:    ret83  %interleaved.vec = load <20 x i32>, ptr %ptr84  %v0 = shufflevector <20 x i32> %interleaved.vec, <20 x i32> poison, <4 x i32> <i32 0, i32 5, i32 10, i32 15>85  %v1 = shufflevector <20 x i32> %interleaved.vec, <20 x i32> poison, <4 x i32> <i32 1, i32 6, i32 11, i32 16>86  %v2 = shufflevector <20 x i32> %interleaved.vec, <20 x i32> poison, <4 x i32> <i32 2, i32 7, i32 12, i32 17>87  %v3 = shufflevector <20 x i32> %interleaved.vec, <20 x i32> poison, <4 x i32> <i32 3, i32 8, i32 13, i32 18>88  %v4 = shufflevector <20 x i32> %interleaved.vec, <20 x i32> poison, <4 x i32> <i32 4, i32 9, i32 14, i32 19>89  %res0 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>} poison, <4 x i32> %v0, 090  %res1 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>} %res0, <4 x i32> %v1, 191  %res2 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>} %res1, <4 x i32> %v2, 292  %res3 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>} %res2, <4 x i32> %v3, 393  %res4 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>} %res3, <4 x i32> %v4, 494  ret {<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>} %res495}96 97define {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} @load_factor6(ptr %ptr) {98; CHECK-LABEL: load_factor6:99; CHECK:       # %bb.0:100; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma101; CHECK-NEXT:    vlseg6e16.v v8, (a0)102; CHECK-NEXT:    ret103  %interleaved.vec = load <12 x i16>, ptr %ptr104  %v0 = shufflevector <12 x i16> %interleaved.vec, <12 x i16> poison, <2 x i32> <i32 0, i32 6>105  %v1 = shufflevector <12 x i16> %interleaved.vec, <12 x i16> poison, <2 x i32> <i32 1, i32 7>106  %v2 = shufflevector <12 x i16> %interleaved.vec, <12 x i16> poison, <2 x i32> <i32 2, i32 8>107  %v3 = shufflevector <12 x i16> %interleaved.vec, <12 x i16> poison, <2 x i32> <i32 3, i32 9>108  %v4 = shufflevector <12 x i16> %interleaved.vec, <12 x i16> poison, <2 x i32> <i32 4, i32 10>109  %v5 = shufflevector <12 x i16> %interleaved.vec, <12 x i16> poison, <2 x i32> <i32 5, i32 11>110  %res0 = insertvalue {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} poison, <2 x i16> %v0, 0111  %res1 = insertvalue {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} %res0, <2 x i16> %v1, 1112  %res2 = insertvalue {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} %res1, <2 x i16> %v2, 2113  %res3 = insertvalue {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} %res2, <2 x i16> %v3, 3114  %res4 = insertvalue {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} %res3, <2 x i16> %v4, 4115  %res5 = insertvalue {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} %res4, <2 x i16> %v5, 5116  ret {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} %res5117}118 119define {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} @load_factor7(ptr %ptr) {120; CHECK-LABEL: load_factor7:121; CHECK:       # %bb.0:122; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma123; CHECK-NEXT:    vlseg7e16.v v8, (a0)124; CHECK-NEXT:    ret125  %interleaved.vec = load <14 x i16>, ptr %ptr126  %v0 = shufflevector <14 x i16> %interleaved.vec, <14 x i16> poison, <2 x i32> <i32 0, i32 7>127  %v1 = shufflevector <14 x i16> %interleaved.vec, <14 x i16> poison, <2 x i32> <i32 1, i32 8>128  %v2 = shufflevector <14 x i16> %interleaved.vec, <14 x i16> poison, <2 x i32> <i32 2, i32 9>129  %v3 = shufflevector <14 x i16> %interleaved.vec, <14 x i16> poison, <2 x i32> <i32 3, i32 10>130  %v4 = shufflevector <14 x i16> %interleaved.vec, <14 x i16> poison, <2 x i32> <i32 4, i32 11>131  %v5 = shufflevector <14 x i16> %interleaved.vec, <14 x i16> poison, <2 x i32> <i32 5, i32 12>132  %v6 = shufflevector <14 x i16> %interleaved.vec, <14 x i16> poison, <2 x i32> <i32 6, i32 13>133  %res0 = insertvalue {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} poison, <2 x i16> %v0, 0134  %res1 = insertvalue {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} %res0, <2 x i16> %v1, 1135  %res2 = insertvalue {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} %res1, <2 x i16> %v2, 2136  %res3 = insertvalue {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} %res2, <2 x i16> %v3, 3137  %res4 = insertvalue {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} %res3, <2 x i16> %v4, 4138  %res5 = insertvalue {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} %res4, <2 x i16> %v5, 5139  %res6 = insertvalue {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} %res5, <2 x i16> %v6, 6140  ret {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} %res6141}142 143define {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} @load_factor8(ptr %ptr) {144; CHECK-LABEL: load_factor8:145; CHECK:       # %bb.0:146; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma147; CHECK-NEXT:    vlseg8e16.v v8, (a0)148; CHECK-NEXT:    ret149  %interleaved.vec = load <16 x i16>, ptr %ptr150  %v0 = shufflevector <16 x i16> %interleaved.vec, <16 x i16> poison, <2 x i32> <i32 0, i32 8>151  %v1 = shufflevector <16 x i16> %interleaved.vec, <16 x i16> poison, <2 x i32> <i32 1, i32 9>152  %v2 = shufflevector <16 x i16> %interleaved.vec, <16 x i16> poison, <2 x i32> <i32 2, i32 10>153  %v3 = shufflevector <16 x i16> %interleaved.vec, <16 x i16> poison, <2 x i32> <i32 3, i32 11>154  %v4 = shufflevector <16 x i16> %interleaved.vec, <16 x i16> poison, <2 x i32> <i32 4, i32 12>155  %v5 = shufflevector <16 x i16> %interleaved.vec, <16 x i16> poison, <2 x i32> <i32 5, i32 13>156  %v6 = shufflevector <16 x i16> %interleaved.vec, <16 x i16> poison, <2 x i32> <i32 6, i32 14>157  %v7 = shufflevector <16 x i16> %interleaved.vec, <16 x i16> poison, <2 x i32> <i32 7, i32 15>158  %res0 = insertvalue {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} poison, <2 x i16> %v0, 0159  %res1 = insertvalue {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} %res0, <2 x i16> %v1, 1160  %res2 = insertvalue {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} %res1, <2 x i16> %v2, 2161  %res3 = insertvalue {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} %res2, <2 x i16> %v3, 3162  %res4 = insertvalue {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} %res3, <2 x i16> %v4, 4163  %res5 = insertvalue {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} %res4, <2 x i16> %v5, 5164  %res6 = insertvalue {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} %res5, <2 x i16> %v6, 6165  %res7 = insertvalue {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} %res6, <2 x i16> %v7, 7166  ret {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} %res7167}168 169define {<4 x i32>, <4 x i32>} @vpload_factor2(ptr %ptr) {170; CHECK-LABEL: vpload_factor2:171; CHECK:       # %bb.0:172; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma173; CHECK-NEXT:    vlseg2e32.v v8, (a0)174; CHECK-NEXT:    ret175  %interleaved.vec = tail call <8 x i32> @llvm.vp.load.v8i32.p0(ptr %ptr, <8 x i1> splat (i1 true), i32 8)176  %v0 = shufflevector <8 x i32> %interleaved.vec, <8 x i32> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>177  %v1 = shufflevector <8 x i32> %interleaved.vec, <8 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>178  %res0 = insertvalue {<4 x i32>, <4 x i32>} poison, <4 x i32> %v0, 0179  %res1 = insertvalue {<4 x i32>, <4 x i32>} %res0, <4 x i32> %v1, 1180  ret {<4 x i32>, <4 x i32>} %res1181}182 183define {<4 x i32>, <4 x i32>} @vpload_factor2_interleaved_mask_intrinsic(ptr %ptr, <4 x i1> %m) {184; CHECK-LABEL: vpload_factor2_interleaved_mask_intrinsic:185; CHECK:       # %bb.0:186; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma187; CHECK-NEXT:    vlseg2e32.v v8, (a0), v0.t188; CHECK-NEXT:    ret189  %interleaved.mask = call <8 x i1> @llvm.vector.interleave2(<4 x i1> %m, <4 x i1> %m)190  %interleaved.vec = tail call <8 x i32> @llvm.vp.load.v8i32.p0(ptr %ptr, <8 x i1> %interleaved.mask, i32 8)191  %v0 = shufflevector <8 x i32> %interleaved.vec, <8 x i32> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>192  %v1 = shufflevector <8 x i32> %interleaved.vec, <8 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>193  %res0 = insertvalue {<4 x i32>, <4 x i32>} poison, <4 x i32> %v0, 0194  %res1 = insertvalue {<4 x i32>, <4 x i32>} %res0, <4 x i32> %v1, 1195  ret {<4 x i32>, <4 x i32>} %res1196}197 198; mask = %m, skip the last two fields.199define {<2 x i32>, <2 x i32>} @vpload_factor4_interleaved_mask_intrinsic_skip_fields(ptr %ptr, <2 x i1> %m) {200; CHECK-LABEL: vpload_factor4_interleaved_mask_intrinsic_skip_fields:201; CHECK:       # %bb.0:202; CHECK-NEXT:    li a1, 16203; CHECK-NEXT:    vsetivli zero, 4, e32, mf2, ta, ma204; CHECK-NEXT:    vlsseg2e32.v v8, (a0), a1, v0.t205; CHECK-NEXT:    ret206  %interleaved.mask = call <8 x i1> @llvm.vector.interleave4(<2 x i1> %m, <2 x i1> %m, <2 x i1> splat (i1 false), <2 x i1> splat (i1 false))207  %interleaved.vec = tail call <8 x i32> @llvm.vp.load.v8i32.p0(ptr %ptr, <8 x i1> %interleaved.mask, i32 8)208  %v0 = shufflevector <8 x i32> %interleaved.vec, <8 x i32> poison, <2 x i32> <i32 0, i32 4>209  %v1 = shufflevector <8 x i32> %interleaved.vec, <8 x i32> poison, <2 x i32> <i32 1, i32 5>210  %res0 = insertvalue {<2 x i32>, <2 x i32>} poison, <2 x i32> %v0, 0211  %res1 = insertvalue {<2 x i32>, <2 x i32>} %res0, <2 x i32> %v1, 1212  ret {<2 x i32>, <2 x i32>} %res1213}214 215define {<4 x i32>, <4 x i32>} @vpload_factor2_interleaved_mask_shuffle(ptr %ptr, <4 x i1> %m) {216; CHECK-LABEL: vpload_factor2_interleaved_mask_shuffle:217; CHECK:       # %bb.0:218; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma219; CHECK-NEXT:    vlseg2e32.v v8, (a0), v0.t220; CHECK-NEXT:    ret221  %interleaved.mask = shufflevector <4 x i1> %m, <4 x i1> poison, <8 x i32> <i32 0, i32 0, i32 1, i32 1, i32 2, i32 2, i32 3, i32 3>222  %interleaved.vec = tail call <8 x i32> @llvm.vp.load.v8i32.p0(ptr %ptr, <8 x i1> %interleaved.mask, i32 8)223  %v0 = shufflevector <8 x i32> %interleaved.vec, <8 x i32> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>224  %v1 = shufflevector <8 x i32> %interleaved.vec, <8 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>225  %res0 = insertvalue {<4 x i32>, <4 x i32>} poison, <4 x i32> %v0, 0226  %res1 = insertvalue {<4 x i32>, <4 x i32>} %res0, <4 x i32> %v1, 1227  ret {<4 x i32>, <4 x i32>} %res1228}229 230define {<4 x i32>, <4 x i32>} @vpload_factor2_interleaved_mask_shuffle2(ptr %ptr, <2 x i1> %m) {231; CHECK-LABEL: vpload_factor2_interleaved_mask_shuffle2:232; CHECK:       # %bb.0:233; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma234; CHECK-NEXT:    vmv.v.i v8, 0235; CHECK-NEXT:    li a1, -1236; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0237; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma238; CHECK-NEXT:    vwaddu.vv v9, v8, v8239; CHECK-NEXT:    vwmaccu.vx v9, a1, v8240; CHECK-NEXT:    vsetivli zero, 4, e8, mf2, ta, ma241; CHECK-NEXT:    vmsne.vi v0, v9, 0242; CHECK-NEXT:    vle32.v v10, (a0), v0.t243; CHECK-NEXT:    li a0, 32244; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma245; CHECK-NEXT:    vnsrl.wi v8, v10, 0246; CHECK-NEXT:    vnsrl.wx v9, v10, a0247; CHECK-NEXT:    ret248  %interleaved.mask = shufflevector <2 x i1> %m, <2 x i1> poison, <8 x i32> <i32 0, i32 0, i32 1, i32 1, i32 2, i32 2, i32 3, i32 3>249  %interleaved.vec = tail call <8 x i32> @llvm.vp.load.v8i32.p0(ptr %ptr, <8 x i1> %interleaved.mask, i32 4)250  %v0 = shufflevector <8 x i32> %interleaved.vec, <8 x i32> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>251  %v1 = shufflevector <8 x i32> %interleaved.vec, <8 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>252  %res0 = insertvalue {<4 x i32>, <4 x i32>} poison, <4 x i32> %v0, 0253  %res1 = insertvalue {<4 x i32>, <4 x i32>} %res0, <4 x i32> %v1, 1254  ret {<4 x i32>, <4 x i32>} %res1255}256 257define {<4 x i32>, <4 x i32>, <4 x i32>} @vpload_factor3(ptr %ptr) {258; CHECK-LABEL: vpload_factor3:259; CHECK:       # %bb.0:260; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma261; CHECK-NEXT:    vlseg3e32.v v8, (a0)262; CHECK-NEXT:    ret263  %interleaved.vec = tail call <12 x i32> @llvm.vp.load.v12i32.p0(ptr %ptr, <12 x i1> splat (i1 true), i32 12)264  %v0 = shufflevector <12 x i32> %interleaved.vec, <12 x i32> poison, <4 x i32> <i32 0, i32 3, i32 6, i32 9>265  %v1 = shufflevector <12 x i32> %interleaved.vec, <12 x i32> poison, <4 x i32> <i32 1, i32 4, i32 7, i32 10>266  %v2 = shufflevector <12 x i32> %interleaved.vec, <12 x i32> poison, <4 x i32> <i32 2, i32 5, i32 8, i32 11>267  %res0 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>} poison, <4 x i32> %v0, 0268  %res1 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>} %res0, <4 x i32> %v1, 1269  %res2 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>} %res1, <4 x i32> %v2, 2270  ret {<4 x i32>, <4 x i32>, <4 x i32>} %res2271}272 273; We only extract some of the fields.274define {<4 x i32>, <4 x i32>} @vpload_factor3_partial(ptr %ptr) {275; CHECK-LABEL: vpload_factor3_partial:276; CHECK:       # %bb.0:277; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma278; CHECK-NEXT:    vlseg3e32.v v7, (a0)279; CHECK-NEXT:    vmv1r.v v8, v7280; CHECK-NEXT:    ret281  %interleaved.vec = tail call <12 x i32> @llvm.vp.load.v12i32.p0(ptr %ptr, <12 x i1> splat (i1 true), i32 12)282  %v0 = shufflevector <12 x i32> %interleaved.vec, <12 x i32> poison, <4 x i32> <i32 0, i32 3, i32 6, i32 9>283  %v2 = shufflevector <12 x i32> %interleaved.vec, <12 x i32> poison, <4 x i32> <i32 2, i32 5, i32 8, i32 11>284  %res0 = insertvalue {<4 x i32>, <4 x i32>} poison, <4 x i32> %v0, 0285  %res1 = insertvalue {<4 x i32>, <4 x i32>} %res0, <4 x i32> %v2, 1286  ret {<4 x i32>, <4 x i32>} %res1287}288 289; Load a larger vector but only deinterleave a subset of the elements.290define {<4 x i32>, <4 x i32>, <4 x i32>} @vpload_factor3_v16i32(ptr %ptr) {291; CHECK-LABEL: vpload_factor3_v16i32:292; CHECK:       # %bb.0:293; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma294; CHECK-NEXT:    vlseg3e32.v v8, (a0)295; CHECK-NEXT:    ret296  %interleaved.vec = tail call <16 x i32> @llvm.vp.load.v16i32.p0(ptr %ptr, <16 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 0, i1 1>, i32 12)297  %v0 = shufflevector <16 x i32> %interleaved.vec, <16 x i32> poison, <4 x i32> <i32 0, i32 3, i32 6, i32 9>298  %v1 = shufflevector <16 x i32> %interleaved.vec, <16 x i32> poison, <4 x i32> <i32 1, i32 4, i32 7, i32 10>299  %v2 = shufflevector <16 x i32> %interleaved.vec, <16 x i32> poison, <4 x i32> <i32 2, i32 5, i32 8, i32 11>300  %res0 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>} poison, <4 x i32> %v0, 0301  %res1 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>} %res0, <4 x i32> %v1, 1302  %res2 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>} %res1, <4 x i32> %v2, 2303  ret {<4 x i32>, <4 x i32>, <4 x i32>} %res2304}305 306; Make sure the mask is propagated.307define {<4 x i32>, <4 x i32>, <4 x i32>} @vpload_factor3_mask(ptr %ptr) {308; CHECK-LABEL: vpload_factor3_mask:309; CHECK:       # %bb.0:310; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma311; CHECK-NEXT:    vmv.v.i v0, 10312; CHECK-NEXT:    vlseg3e32.v v8, (a0), v0.t313; CHECK-NEXT:    ret314  %interleaved.vec = tail call <12 x i32> @llvm.vp.load.v12i32.p0(ptr %ptr, <12 x i1> <i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1>, i32 12)315  %v0 = shufflevector <12 x i32> %interleaved.vec, <12 x i32> poison, <4 x i32> <i32 0, i32 3, i32 6, i32 9>316  %v1 = shufflevector <12 x i32> %interleaved.vec, <12 x i32> poison, <4 x i32> <i32 1, i32 4, i32 7, i32 10>317  %v2 = shufflevector <12 x i32> %interleaved.vec, <12 x i32> poison, <4 x i32> <i32 2, i32 5, i32 8, i32 11>318  %res0 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>} poison, <4 x i32> %v0, 0319  %res1 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>} %res0, <4 x i32> %v1, 1320  %res2 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>} %res1, <4 x i32> %v2, 2321  ret {<4 x i32>, <4 x i32>, <4 x i32>} %res2322}323 324; Poison/poison in the shuffle mask shouldn't affect anything.325define {<4 x i32>, <4 x i32>, <4 x i32>} @vpload_factor3_poison_shufflemask(ptr %ptr) {326; CHECK-LABEL: vpload_factor3_poison_shufflemask:327; CHECK:       # %bb.0:328; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma329; CHECK-NEXT:    vmv.v.i v0, 10330; CHECK-NEXT:    vlseg3e32.v v8, (a0), v0.t331; CHECK-NEXT:    ret332  %interleaved.vec = tail call <12 x i32> @llvm.vp.load.v12i32.p0(ptr %ptr, <12 x i1> <i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1>, i32 12)333  %v0 = shufflevector <12 x i32> %interleaved.vec, <12 x i32> poison, <4 x i32> <i32 0, i32 3, i32 6, i32 9>334  %v1 = shufflevector <12 x i32> %interleaved.vec, <12 x i32> poison, <4 x i32> <i32 1, i32 4, i32 poison, i32 10>335  %v2 = shufflevector <12 x i32> %interleaved.vec, <12 x i32> poison, <4 x i32> <i32 2, i32 5, i32 8, i32 11>336  %res0 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>} poison, <4 x i32> %v0, 0337  %res1 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>} %res0, <4 x i32> %v1, 1338  %res2 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>} %res1, <4 x i32> %v2, 2339  ret {<4 x i32>, <4 x i32>, <4 x i32>} %res2340}341 342define {<4 x i32>, <4 x i32>} @vpload_factor3_skip_fields(ptr %ptr) {343  ; mask = 1111, skip the last field.344; CHECK-LABEL: vpload_factor3_skip_fields:345; CHECK:       # %bb.0:346; CHECK-NEXT:    li a1, 12347; CHECK-NEXT:    vsetivli zero, 6, e32, m1, ta, ma348; CHECK-NEXT:    vlsseg2e32.v v8, (a0), a1349; CHECK-NEXT:    ret350  %interleaved.vec = tail call <12 x i32> @llvm.vp.load.v12i32.p0(ptr %ptr, <12 x i1> <i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0>, i32 12)351  %v0 = shufflevector <12 x i32> %interleaved.vec, <12 x i32> poison, <4 x i32> <i32 0, i32 3, i32 6, i32 9>352  %v1 = shufflevector <12 x i32> %interleaved.vec, <12 x i32> poison, <4 x i32> <i32 1, i32 4, i32 poison, i32 10>353  %v2 = shufflevector <12 x i32> %interleaved.vec, <12 x i32> poison, <4 x i32> <i32 2, i32 5, i32 8, i32 11>354  %res0 = insertvalue {<4 x i32>, <4 x i32>} poison, <4 x i32> %v0, 0355  %res1 = insertvalue {<4 x i32>, <4 x i32>} %res0, <4 x i32> %v1, 1356  ret {<4 x i32>, <4 x i32>} %res1357}358 359define {<4 x i32>, <4 x i32>} @vpload_factor3_mask_skip_fields(ptr %ptr) {360  ; mask = 0101, skip the last field.361; CHECK-LABEL: vpload_factor3_mask_skip_fields:362; CHECK:       # %bb.0:363; CHECK-NEXT:    vsetivli zero, 6, e32, m1, ta, ma364; CHECK-NEXT:    vmv.v.i v0, 10365; CHECK-NEXT:    li a1, 12366; CHECK-NEXT:    vlsseg2e32.v v8, (a0), a1, v0.t367; CHECK-NEXT:    ret368  %interleaved.vec = tail call <12 x i32> @llvm.vp.load.v12i32.p0(ptr %ptr, <12 x i1> <i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0>, i32 12)369  %v0 = shufflevector <12 x i32> %interleaved.vec, <12 x i32> poison, <4 x i32> <i32 0, i32 3, i32 6, i32 9>370  %v1 = shufflevector <12 x i32> %interleaved.vec, <12 x i32> poison, <4 x i32> <i32 1, i32 4, i32 poison, i32 10>371  %v2 = shufflevector <12 x i32> %interleaved.vec, <12 x i32> poison, <4 x i32> <i32 2, i32 5, i32 8, i32 11>372  %res0 = insertvalue {<4 x i32>, <4 x i32>} poison, <4 x i32> %v0, 0373  %res1 = insertvalue {<4 x i32>, <4 x i32>} %res0, <4 x i32> %v1, 1374  ret {<4 x i32>, <4 x i32>} %res1375}376 377define {<4 x i32>, <4 x i32>} @vpload_factor3_combined_mask_skip_field(ptr %ptr, <4 x i1> %mask) {378; CHECK-LABEL: vpload_factor3_combined_mask_skip_field:379; CHECK:       # %bb.0:380; CHECK-NEXT:    li a1, 12381; CHECK-NEXT:    vsetivli zero, 6, e32, m1, ta, ma382; CHECK-NEXT:    vlsseg2e32.v v8, (a0), a1, v0.t383; CHECK-NEXT:    ret384  %interleaved.mask = shufflevector <4 x i1> %mask, <4 x i1> poison, <12 x i32> <i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 2, i32 2, i32 2, i32 3, i32 3, i32 3>385  %combined = and <12 x i1> %interleaved.mask, <i1 true, i1 true, i1 false, i1 true, i1 true, i1 false, i1 true, i1 true, i1 false, i1 true, i1 true, i1 false>386  %interleaved.vec = tail call <12 x i32> @llvm.vp.load.v12i32.p0(ptr %ptr, <12 x i1> %combined, i32 12)387  ; mask = %mask, skip the last field388  %v0 = shufflevector <12 x i32> %interleaved.vec, <12 x i32> poison, <4 x i32> <i32 0, i32 3, i32 6, i32 9>389  %v1 = shufflevector <12 x i32> %interleaved.vec, <12 x i32> poison, <4 x i32> <i32 1, i32 4, i32 7, i32 10>390  %res0 = insertvalue {<4 x i32>, <4 x i32>} poison, <4 x i32> %v0, 0391  %res1 = insertvalue {<4 x i32>, <4 x i32>} %res0, <4 x i32> %v1, 1392  ret {<4 x i32>, <4 x i32>} %res1393}394 395define {<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>} @vpload_factor4(ptr %ptr) {396; CHECK-LABEL: vpload_factor4:397; CHECK:       # %bb.0:398; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma399; CHECK-NEXT:    vlseg4e32.v v8, (a0)400; CHECK-NEXT:    ret401  %interleaved.vec = tail call <16 x i32> @llvm.vp.load.v16i32.p0(ptr %ptr, <16 x i1> splat (i1 true), i32 16)402  %v0 = shufflevector <16 x i32> %interleaved.vec, <16 x i32> poison, <4 x i32> <i32 0, i32 4, i32 8, i32 12>403  %v1 = shufflevector <16 x i32> %interleaved.vec, <16 x i32> poison, <4 x i32> <i32 1, i32 5, i32 9, i32 13>404  %v2 = shufflevector <16 x i32> %interleaved.vec, <16 x i32> poison, <4 x i32> <i32 2, i32 6, i32 10, i32 14>405  %v3 = shufflevector <16 x i32> %interleaved.vec, <16 x i32> poison, <4 x i32> <i32 3, i32 7, i32 11, i32 15>406  %res0 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>} poison, <4 x i32> %v0, 0407  %res1 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>} %res0, <4 x i32> %v1, 1408  %res2 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>} %res1, <4 x i32> %v2, 2409  %res3 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>} %res2, <4 x i32> %v3, 3410  ret {<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>} %res3411}412 413; TODO: Add more tests for vp.load/store + (de)interleave intrinsics with fixed vectors.414define {<2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>} @vpload_factor4_intrinsics(ptr %ptr) {415; CHECK-LABEL: vpload_factor4_intrinsics:416; CHECK:       # %bb.0:417; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma418; CHECK-NEXT:    vlseg4e32.v v8, (a0)419; CHECK-NEXT:    ret420  %wide.masked.load = call <8 x i32> @llvm.vp.load.v8i32.p0(ptr %ptr, <8 x i1> splat (i1 true), i32 8)421  %d = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave4.v8i32(<8 x i32> %wide.masked.load)422  %t0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %d, 0423  %t1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %d, 1424  %t2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %d, 2425  %t3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %d, 3426 427  %res0 = insertvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } poison, <2 x i32> %t0, 0428  %res1 = insertvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %res0, <2 x i32> %t1, 1429  %res2 = insertvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %res1, <2 x i32> %t2, 2430  %res3 = insertvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %res2, <2 x i32> %t3, 3431  ret { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %res3432}433 434define {<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>} @vpload_factor5(ptr %ptr) {435; CHECK-LABEL: vpload_factor5:436; CHECK:       # %bb.0:437; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma438; CHECK-NEXT:    vlseg5e32.v v8, (a0)439; CHECK-NEXT:    ret440  %interleaved.vec = tail call <20 x i32> @llvm.vp.load.v20i32.p0(ptr %ptr, <20 x i1> splat (i1 true), i32 20)441  %v0 = shufflevector <20 x i32> %interleaved.vec, <20 x i32> poison, <4 x i32> <i32 0, i32 5, i32 10, i32 15>442  %v1 = shufflevector <20 x i32> %interleaved.vec, <20 x i32> poison, <4 x i32> <i32 1, i32 6, i32 11, i32 16>443  %v2 = shufflevector <20 x i32> %interleaved.vec, <20 x i32> poison, <4 x i32> <i32 2, i32 7, i32 12, i32 17>444  %v3 = shufflevector <20 x i32> %interleaved.vec, <20 x i32> poison, <4 x i32> <i32 3, i32 8, i32 13, i32 18>445  %v4 = shufflevector <20 x i32> %interleaved.vec, <20 x i32> poison, <4 x i32> <i32 4, i32 9, i32 14, i32 19>446  %res0 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>} poison, <4 x i32> %v0, 0447  %res1 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>} %res0, <4 x i32> %v1, 1448  %res2 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>} %res1, <4 x i32> %v2, 2449  %res3 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>} %res2, <4 x i32> %v3, 3450  %res4 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>} %res3, <4 x i32> %v4, 4451  ret {<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>} %res4452}453 454define {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} @vpload_factor6(ptr %ptr) {455; CHECK-LABEL: vpload_factor6:456; CHECK:       # %bb.0:457; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma458; CHECK-NEXT:    vlseg6e16.v v8, (a0)459; CHECK-NEXT:    ret460  %interleaved.vec = tail call <12 x i16> @llvm.vp.load.v12i16.p0(ptr %ptr, <12 x i1> splat (i1 true), i32 12)461  %v0 = shufflevector <12 x i16> %interleaved.vec, <12 x i16> poison, <2 x i32> <i32 0, i32 6>462  %v1 = shufflevector <12 x i16> %interleaved.vec, <12 x i16> poison, <2 x i32> <i32 1, i32 7>463  %v2 = shufflevector <12 x i16> %interleaved.vec, <12 x i16> poison, <2 x i32> <i32 2, i32 8>464  %v3 = shufflevector <12 x i16> %interleaved.vec, <12 x i16> poison, <2 x i32> <i32 3, i32 9>465  %v4 = shufflevector <12 x i16> %interleaved.vec, <12 x i16> poison, <2 x i32> <i32 4, i32 10>466  %v5 = shufflevector <12 x i16> %interleaved.vec, <12 x i16> poison, <2 x i32> <i32 5, i32 11>467  %res0 = insertvalue {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} poison, <2 x i16> %v0, 0468  %res1 = insertvalue {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} %res0, <2 x i16> %v1, 1469  %res2 = insertvalue {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} %res1, <2 x i16> %v2, 2470  %res3 = insertvalue {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} %res2, <2 x i16> %v3, 3471  %res4 = insertvalue {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} %res3, <2 x i16> %v4, 4472  %res5 = insertvalue {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} %res4, <2 x i16> %v5, 5473  ret {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} %res5474}475 476define {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} @vpload_factor7(ptr %ptr) {477; CHECK-LABEL: vpload_factor7:478; CHECK:       # %bb.0:479; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma480; CHECK-NEXT:    vlseg7e16.v v8, (a0)481; CHECK-NEXT:    ret482  %interleaved.vec = tail call <14 x i16> @llvm.vp.load.v14i16.p0(ptr %ptr, <14 x i1> splat (i1 true), i32 14)483  %v0 = shufflevector <14 x i16> %interleaved.vec, <14 x i16> poison, <2 x i32> <i32 0, i32 7>484  %v1 = shufflevector <14 x i16> %interleaved.vec, <14 x i16> poison, <2 x i32> <i32 1, i32 8>485  %v2 = shufflevector <14 x i16> %interleaved.vec, <14 x i16> poison, <2 x i32> <i32 2, i32 9>486  %v3 = shufflevector <14 x i16> %interleaved.vec, <14 x i16> poison, <2 x i32> <i32 3, i32 10>487  %v4 = shufflevector <14 x i16> %interleaved.vec, <14 x i16> poison, <2 x i32> <i32 4, i32 11>488  %v5 = shufflevector <14 x i16> %interleaved.vec, <14 x i16> poison, <2 x i32> <i32 5, i32 12>489  %v6 = shufflevector <14 x i16> %interleaved.vec, <14 x i16> poison, <2 x i32> <i32 6, i32 13>490  %res0 = insertvalue {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} poison, <2 x i16> %v0, 0491  %res1 = insertvalue {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} %res0, <2 x i16> %v1, 1492  %res2 = insertvalue {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} %res1, <2 x i16> %v2, 2493  %res3 = insertvalue {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} %res2, <2 x i16> %v3, 3494  %res4 = insertvalue {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} %res3, <2 x i16> %v4, 4495  %res5 = insertvalue {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} %res4, <2 x i16> %v5, 5496  %res6 = insertvalue {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} %res5, <2 x i16> %v6, 6497  ret {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} %res6498}499 500define {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} @vpload_factor8(ptr %ptr) {501; CHECK-LABEL: vpload_factor8:502; CHECK:       # %bb.0:503; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma504; CHECK-NEXT:    vlseg8e16.v v8, (a0)505; CHECK-NEXT:    ret506  %interleaved.vec = tail call <16 x i16> @llvm.vp.load.v16i16.p0(ptr %ptr, <16 x i1> splat (i1 true), i32 16)507  %v0 = shufflevector <16 x i16> %interleaved.vec, <16 x i16> poison, <2 x i32> <i32 0, i32 8>508  %v1 = shufflevector <16 x i16> %interleaved.vec, <16 x i16> poison, <2 x i32> <i32 1, i32 9>509  %v2 = shufflevector <16 x i16> %interleaved.vec, <16 x i16> poison, <2 x i32> <i32 2, i32 10>510  %v3 = shufflevector <16 x i16> %interleaved.vec, <16 x i16> poison, <2 x i32> <i32 3, i32 11>511  %v4 = shufflevector <16 x i16> %interleaved.vec, <16 x i16> poison, <2 x i32> <i32 4, i32 12>512  %v5 = shufflevector <16 x i16> %interleaved.vec, <16 x i16> poison, <2 x i32> <i32 5, i32 13>513  %v6 = shufflevector <16 x i16> %interleaved.vec, <16 x i16> poison, <2 x i32> <i32 6, i32 14>514  %v7 = shufflevector <16 x i16> %interleaved.vec, <16 x i16> poison, <2 x i32> <i32 7, i32 15>515  %res0 = insertvalue {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} poison, <2 x i16> %v0, 0516  %res1 = insertvalue {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} %res0, <2 x i16> %v1, 1517  %res2 = insertvalue {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} %res1, <2 x i16> %v2, 2518  %res3 = insertvalue {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} %res2, <2 x i16> %v3, 3519  %res4 = insertvalue {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} %res3, <2 x i16> %v4, 4520  %res5 = insertvalue {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} %res4, <2 x i16> %v5, 5521  %res6 = insertvalue {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} %res5, <2 x i16> %v6, 6522  %res7 = insertvalue {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} %res6, <2 x i16> %v7, 7523  ret {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} %res7524}525 526; LMUL * NF is > 8 here and so shouldn't be lowered to a vlseg527define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_factor6_too_big(ptr %ptr) {528; RV32-LABEL: load_factor6_too_big:529; RV32:       # %bb.0:530; RV32-NEXT:    addi sp, sp, -16531; RV32-NEXT:    .cfi_def_cfa_offset 16532; RV32-NEXT:    csrr a2, vlenb533; RV32-NEXT:    li a3, 100534; RV32-NEXT:    mul a2, a2, a3535; RV32-NEXT:    sub sp, sp, a2536; RV32-NEXT:    .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0xe4, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 100 * vlenb537; RV32-NEXT:    addi a4, a1, 128538; RV32-NEXT:    addi a5, a1, 256539; RV32-NEXT:    li a2, 32540; RV32-NEXT:    lui a3, 12541; RV32-NEXT:    lui a6, 12291542; RV32-NEXT:    lui a7, %hi(.LCPI27_0)543; RV32-NEXT:    addi a7, a7, %lo(.LCPI27_0)544; RV32-NEXT:    vsetvli zero, a2, e32, m8, ta, ma545; RV32-NEXT:    vle32.v v24, (a5)546; RV32-NEXT:    vmv.s.x v0, a3547; RV32-NEXT:    vle32.v v8, (a1)548; RV32-NEXT:    csrr a1, vlenb549; RV32-NEXT:    slli a1, a1, 6550; RV32-NEXT:    add a1, sp, a1551; RV32-NEXT:    addi a1, a1, 16552; RV32-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill553; RV32-NEXT:    addi a6, a6, 3554; RV32-NEXT:    vsetivli zero, 16, e32, m4, ta, ma555; RV32-NEXT:    vslideup.vi v16, v24, 4556; RV32-NEXT:    vsetivli zero, 16, e32, m8, ta, ma557; RV32-NEXT:    vslidedown.vi v8, v24, 16558; RV32-NEXT:    csrr a1, vlenb559; RV32-NEXT:    li a5, 76560; RV32-NEXT:    mul a1, a1, a5561; RV32-NEXT:    add a1, sp, a1562; RV32-NEXT:    addi a1, a1, 16563; RV32-NEXT:    vs8r.v v24, (a1) # vscale x 64-byte Folded Spill564; RV32-NEXT:    csrr a1, vlenb565; RV32-NEXT:    li a5, 92566; RV32-NEXT:    mul a1, a1, a5567; RV32-NEXT:    add a1, sp, a1568; RV32-NEXT:    addi a1, a1, 16569; RV32-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill570; RV32-NEXT:    vmv1r.v v30, v0571; RV32-NEXT:    vsetivli zero, 16, e32, m4, ta, mu572; RV32-NEXT:    vslideup.vi v16, v8, 10, v0.t573; RV32-NEXT:    csrr a1, vlenb574; RV32-NEXT:    li a5, 72575; RV32-NEXT:    mul a1, a1, a5576; RV32-NEXT:    add a1, sp, a1577; RV32-NEXT:    addi a1, a1, 16578; RV32-NEXT:    vs4r.v v16, (a1) # vscale x 32-byte Folded Spill579; RV32-NEXT:    vsetvli zero, a2, e32, m8, ta, ma580; RV32-NEXT:    vle32.v v8, (a4)581; RV32-NEXT:    csrr a1, vlenb582; RV32-NEXT:    li a4, 84583; RV32-NEXT:    mul a1, a1, a4584; RV32-NEXT:    add a1, sp, a1585; RV32-NEXT:    addi a1, a1, 16586; RV32-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill587; RV32-NEXT:    vsetivli zero, 16, e32, m4, ta, ma588; RV32-NEXT:    vle16.v v28, (a7)589; RV32-NEXT:    vmv.s.x v0, a6590; RV32-NEXT:    csrr a1, vlenb591; RV32-NEXT:    slli a1, a1, 6592; RV32-NEXT:    add a1, sp, a1593; RV32-NEXT:    addi a1, a1, 16594; RV32-NEXT:    vl8r.v v16, (a1) # vscale x 64-byte Folded Reload595; RV32-NEXT:    csrr a1, vlenb596; RV32-NEXT:    li a4, 84597; RV32-NEXT:    mul a1, a1, a4598; RV32-NEXT:    add a1, sp, a1599; RV32-NEXT:    addi a1, a1, 16600; RV32-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload601; RV32-NEXT:    vsetvli zero, a2, e32, m8, ta, ma602; RV32-NEXT:    vmerge.vvm v16, v8, v16, v0603; RV32-NEXT:    vsetivli zero, 16, e64, m8, ta, ma604; RV32-NEXT:    vrgatherei16.vv v0, v16, v28605; RV32-NEXT:    csrr a1, vlenb606; RV32-NEXT:    li a4, 52607; RV32-NEXT:    mul a1, a1, a4608; RV32-NEXT:    add a1, sp, a1609; RV32-NEXT:    addi a1, a1, 16610; RV32-NEXT:    vs8r.v v0, (a1) # vscale x 64-byte Folded Spill611; RV32-NEXT:    vsetvli zero, zero, e32, m4, ta, mu612; RV32-NEXT:    vslideup.vi v8, v24, 2613; RV32-NEXT:    vmv1r.v v0, v30614; RV32-NEXT:    csrr a1, vlenb615; RV32-NEXT:    li a4, 92616; RV32-NEXT:    mul a1, a1, a4617; RV32-NEXT:    add a1, sp, a1618; RV32-NEXT:    addi a1, a1, 16619; RV32-NEXT:    vl8r.v v16, (a1) # vscale x 64-byte Folded Reload620; RV32-NEXT:    vslideup.vi v8, v16, 8, v0.t621; RV32-NEXT:    csrr a1, vlenb622; RV32-NEXT:    li a4, 60623; RV32-NEXT:    mul a1, a1, a4624; RV32-NEXT:    add a1, sp, a1625; RV32-NEXT:    addi a1, a1, 16626; RV32-NEXT:    vs4r.v v8, (a1) # vscale x 32-byte Folded Spill627; RV32-NEXT:    lui a7, 49164628; RV32-NEXT:    lui a1, %hi(.LCPI27_1)629; RV32-NEXT:    addi a1, a1, %lo(.LCPI27_1)630; RV32-NEXT:    lui t2, 3631; RV32-NEXT:    lui t1, 196656632; RV32-NEXT:    lui a4, %hi(.LCPI27_3)633; RV32-NEXT:    addi a4, a4, %lo(.LCPI27_3)634; RV32-NEXT:    lui t0, 786624635; RV32-NEXT:    li a5, 48636; RV32-NEXT:    lui a6, 768637; RV32-NEXT:    addi a7, a7, 12638; RV32-NEXT:    vmv.s.x v0, a7639; RV32-NEXT:    addi t2, t2, 3640; RV32-NEXT:    csrr a7, vlenb641; RV32-NEXT:    li t3, 84642; RV32-NEXT:    mul a7, a7, t3643; RV32-NEXT:    add a7, sp, a7644; RV32-NEXT:    addi a7, a7, 16645; RV32-NEXT:    vl8r.v v16, (a7) # vscale x 64-byte Folded Reload646; RV32-NEXT:    csrr a7, vlenb647; RV32-NEXT:    slli a7, a7, 6648; RV32-NEXT:    add a7, sp, a7649; RV32-NEXT:    addi a7, a7, 16650; RV32-NEXT:    vl8r.v v8, (a7) # vscale x 64-byte Folded Reload651; RV32-NEXT:    vsetvli zero, a2, e32, m8, ta, ma652; RV32-NEXT:    vmerge.vvm v8, v16, v8, v0653; RV32-NEXT:    csrr a7, vlenb654; RV32-NEXT:    slli a7, a7, 5655; RV32-NEXT:    add a7, sp, a7656; RV32-NEXT:    addi a7, a7, 16657; RV32-NEXT:    vs8r.v v8, (a7) # vscale x 64-byte Folded Spill658; RV32-NEXT:    vmv.s.x v0, t2659; RV32-NEXT:    addi a7, t1, 48660; RV32-NEXT:    csrr t1, vlenb661; RV32-NEXT:    li t2, 92662; RV32-NEXT:    mul t1, t1, t2663; RV32-NEXT:    add t1, sp, t1664; RV32-NEXT:    addi t1, t1, 16665; RV32-NEXT:    vl8r.v v24, (t1) # vscale x 64-byte Folded Reload666; RV32-NEXT:    csrr t1, vlenb667; RV32-NEXT:    li t2, 76668; RV32-NEXT:    mul t1, t1, t2669; RV32-NEXT:    add t1, sp, t1670; RV32-NEXT:    addi t1, t1, 16671; RV32-NEXT:    vl8r.v v8, (t1) # vscale x 64-byte Folded Reload672; RV32-NEXT:    vsetivli zero, 16, e32, m4, ta, ma673; RV32-NEXT:    vmerge.vvm v8, v24, v8, v0674; RV32-NEXT:    csrr t1, vlenb675; RV32-NEXT:    li t2, 44676; RV32-NEXT:    mul t1, t1, t2677; RV32-NEXT:    add t1, sp, t1678; RV32-NEXT:    addi t1, t1, 16679; RV32-NEXT:    vs4r.v v8, (t1) # vscale x 32-byte Folded Spill680; RV32-NEXT:    vmv.s.x v0, a7681; RV32-NEXT:    addi a3, a3, 12682; RV32-NEXT:    csrr a7, vlenb683; RV32-NEXT:    slli a7, a7, 6684; RV32-NEXT:    add a7, sp, a7685; RV32-NEXT:    addi a7, a7, 16686; RV32-NEXT:    vl8r.v v24, (a7) # vscale x 64-byte Folded Reload687; RV32-NEXT:    vsetvli zero, a2, e32, m8, ta, ma688; RV32-NEXT:    vmerge.vvm v8, v16, v24, v0689; RV32-NEXT:    csrr a7, vlenb690; RV32-NEXT:    slli a7, a7, 4691; RV32-NEXT:    add a7, sp, a7692; RV32-NEXT:    addi a7, a7, 16693; RV32-NEXT:    vs8r.v v8, (a7) # vscale x 64-byte Folded Spill694; RV32-NEXT:    vmv8r.v v16, v24695; RV32-NEXT:    vmv.s.x v0, a3696; RV32-NEXT:    addi a3, t0, 192697; RV32-NEXT:    csrr a7, vlenb698; RV32-NEXT:    li t0, 92699; RV32-NEXT:    mul a7, a7, t0700; RV32-NEXT:    add a7, sp, a7701; RV32-NEXT:    addi a7, a7, 16702; RV32-NEXT:    vl8r.v v24, (a7) # vscale x 64-byte Folded Reload703; RV32-NEXT:    csrr a7, vlenb704; RV32-NEXT:    li t0, 76705; RV32-NEXT:    mul a7, a7, t0706; RV32-NEXT:    add a7, sp, a7707; RV32-NEXT:    addi a7, a7, 16708; RV32-NEXT:    vl8r.v v8, (a7) # vscale x 64-byte Folded Reload709; RV32-NEXT:    vsetivli zero, 16, e32, m4, ta, ma710; RV32-NEXT:    vmerge.vvm v8, v24, v8, v0711; RV32-NEXT:    csrr a7, vlenb712; RV32-NEXT:    li t0, 48713; RV32-NEXT:    mul a7, a7, t0714; RV32-NEXT:    add a7, sp, a7715; RV32-NEXT:    addi a7, a7, 16716; RV32-NEXT:    vs4r.v v8, (a7) # vscale x 32-byte Folded Spill717; RV32-NEXT:    vmv.s.x v0, a3718; RV32-NEXT:    li a3, 192719; RV32-NEXT:    csrr a7, vlenb720; RV32-NEXT:    li t0, 84721; RV32-NEXT:    mul a7, a7, t0722; RV32-NEXT:    add a7, sp, a7723; RV32-NEXT:    addi a7, a7, 16724; RV32-NEXT:    vl8r.v v8, (a7) # vscale x 64-byte Folded Reload725; RV32-NEXT:    vsetvli zero, a2, e32, m8, ta, ma726; RV32-NEXT:    vmerge.vvm v8, v8, v16, v0727; RV32-NEXT:    csrr a7, vlenb728; RV32-NEXT:    li t0, 24729; RV32-NEXT:    mul a7, a7, t0730; RV32-NEXT:    add a7, sp, a7731; RV32-NEXT:    addi a7, a7, 16732; RV32-NEXT:    vs8r.v v8, (a7) # vscale x 64-byte Folded Spill733; RV32-NEXT:    vmv.s.x v0, a5734; RV32-NEXT:    addi a5, a6, 768735; RV32-NEXT:    csrr a6, vlenb736; RV32-NEXT:    li a7, 92737; RV32-NEXT:    mul a6, a6, a7738; RV32-NEXT:    add a6, sp, a6739; RV32-NEXT:    addi a6, a6, 16740; RV32-NEXT:    vl8r.v v24, (a6) # vscale x 64-byte Folded Reload741; RV32-NEXT:    csrr a6, vlenb742; RV32-NEXT:    li a7, 76743; RV32-NEXT:    mul a6, a6, a7744; RV32-NEXT:    add a6, sp, a6745; RV32-NEXT:    addi a6, a6, 16746; RV32-NEXT:    vl8r.v v8, (a6) # vscale x 64-byte Folded Reload747; RV32-NEXT:    vsetivli zero, 16, e32, m4, ta, ma748; RV32-NEXT:    vmerge.vvm v8, v24, v8, v0749; RV32-NEXT:    csrr a6, vlenb750; RV32-NEXT:    li a7, 40751; RV32-NEXT:    mul a6, a6, a7752; RV32-NEXT:    add a6, sp, a6753; RV32-NEXT:    addi a6, a6, 16754; RV32-NEXT:    vs4r.v v8, (a6) # vscale x 32-byte Folded Spill755; RV32-NEXT:    vmv.s.x v0, a5756; RV32-NEXT:    vle16.v v6, (a1)757; RV32-NEXT:    vle16.v v2, (a4)758; RV32-NEXT:    csrr a1, vlenb759; RV32-NEXT:    li a4, 84760; RV32-NEXT:    mul a1, a1, a4761; RV32-NEXT:    add a1, sp, a1762; RV32-NEXT:    addi a1, a1, 16763; RV32-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload764; RV32-NEXT:    vsetvli zero, a2, e32, m8, ta, ma765; RV32-NEXT:    vmerge.vvm v8, v8, v16, v0766; RV32-NEXT:    csrr a1, vlenb767; RV32-NEXT:    slli a1, a1, 3768; RV32-NEXT:    add a1, sp, a1769; RV32-NEXT:    addi a1, a1, 16770; RV32-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill771; RV32-NEXT:    vmv.s.x v0, a3772; RV32-NEXT:    csrr a1, vlenb773; RV32-NEXT:    slli a1, a1, 5774; RV32-NEXT:    add a1, sp, a1775; RV32-NEXT:    addi a1, a1, 16776; RV32-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload777; RV32-NEXT:    vsetivli zero, 16, e64, m8, ta, ma778; RV32-NEXT:    vrgatherei16.vv v24, v8, v6779; RV32-NEXT:    addi a1, sp, 16780; RV32-NEXT:    vs8r.v v24, (a1) # vscale x 64-byte Folded Spill781; RV32-NEXT:    csrr a1, vlenb782; RV32-NEXT:    li a3, 92783; RV32-NEXT:    mul a1, a1, a3784; RV32-NEXT:    add a1, sp, a1785; RV32-NEXT:    addi a1, a1, 16786; RV32-NEXT:    vl8r.v v24, (a1) # vscale x 64-byte Folded Reload787; RV32-NEXT:    csrr a1, vlenb788; RV32-NEXT:    li a3, 76789; RV32-NEXT:    mul a1, a1, a3790; RV32-NEXT:    add a1, sp, a1791; RV32-NEXT:    addi a1, a1, 16792; RV32-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload793; RV32-NEXT:    vsetvli zero, zero, e32, m4, ta, ma794; RV32-NEXT:    vmerge.vvm v8, v24, v8, v0795; RV32-NEXT:    csrr a1, vlenb796; RV32-NEXT:    li a3, 92797; RV32-NEXT:    mul a1, a1, a3798; RV32-NEXT:    add a1, sp, a1799; RV32-NEXT:    addi a1, a1, 16800; RV32-NEXT:    vs4r.v v8, (a1) # vscale x 32-byte Folded Spill801; RV32-NEXT:    csrr a1, vlenb802; RV32-NEXT:    slli a1, a1, 4803; RV32-NEXT:    add a1, sp, a1804; RV32-NEXT:    addi a1, a1, 16805; RV32-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload806; RV32-NEXT:    vsetvli zero, zero, e64, m8, ta, ma807; RV32-NEXT:    vrgatherei16.vv v24, v8, v2808; RV32-NEXT:    lui a1, %hi(.LCPI27_2)809; RV32-NEXT:    addi a1, a1, %lo(.LCPI27_2)810; RV32-NEXT:    lui a3, 3073811; RV32-NEXT:    addi a3, a3, -1024812; RV32-NEXT:    vmv.s.x v0, a3813; RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma814; RV32-NEXT:    vle16.v v3, (a1)815; RV32-NEXT:    csrr a1, vlenb816; RV32-NEXT:    li a3, 84817; RV32-NEXT:    mul a1, a1, a3818; RV32-NEXT:    add a1, sp, a1819; RV32-NEXT:    addi a1, a1, 16820; RV32-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload821; RV32-NEXT:    vsetvli zero, a2, e32, m8, ta, ma822; RV32-NEXT:    vmerge.vvm v8, v8, v16, v0823; RV32-NEXT:    csrr a1, vlenb824; RV32-NEXT:    li a2, 72825; RV32-NEXT:    mul a1, a1, a2826; RV32-NEXT:    add a1, sp, a1827; RV32-NEXT:    addi a1, a1, 16828; RV32-NEXT:    vl4r.v v28, (a1) # vscale x 32-byte Folded Reload829; RV32-NEXT:    csrr a1, vlenb830; RV32-NEXT:    li a2, 52831; RV32-NEXT:    mul a1, a1, a2832; RV32-NEXT:    add a1, sp, a1833; RV32-NEXT:    addi a1, a1, 16834; RV32-NEXT:    vl8r.v v16, (a1) # vscale x 64-byte Folded Reload835; RV32-NEXT:    vsetivli zero, 12, e32, m4, tu, ma836; RV32-NEXT:    vmv.v.v v28, v16837; RV32-NEXT:    csrr a1, vlenb838; RV32-NEXT:    li a2, 72839; RV32-NEXT:    mul a1, a1, a2840; RV32-NEXT:    add a1, sp, a1841; RV32-NEXT:    addi a1, a1, 16842; RV32-NEXT:    vs4r.v v28, (a1) # vscale x 32-byte Folded Spill843; RV32-NEXT:    addi a1, sp, 16844; RV32-NEXT:    vl8r.v v16, (a1) # vscale x 64-byte Folded Reload845; RV32-NEXT:    csrr a1, vlenb846; RV32-NEXT:    li a2, 60847; RV32-NEXT:    mul a1, a1, a2848; RV32-NEXT:    add a1, sp, a1849; RV32-NEXT:    addi a1, a1, 16850; RV32-NEXT:    vl4r.v v20, (a1) # vscale x 32-byte Folded Reload851; RV32-NEXT:    vmv.v.v v20, v16852; RV32-NEXT:    csrr a1, vlenb853; RV32-NEXT:    li a2, 60854; RV32-NEXT:    mul a1, a1, a2855; RV32-NEXT:    add a1, sp, a1856; RV32-NEXT:    addi a1, a1, 16857; RV32-NEXT:    vs4r.v v20, (a1) # vscale x 32-byte Folded Spill858; RV32-NEXT:    csrr a1, vlenb859; RV32-NEXT:    li a2, 44860; RV32-NEXT:    mul a1, a1, a2861; RV32-NEXT:    add a1, sp, a1862; RV32-NEXT:    addi a1, a1, 16863; RV32-NEXT:    vl4r.v v16, (a1) # vscale x 32-byte Folded Reload864; RV32-NEXT:    vsetivli zero, 8, e64, m4, ta, ma865; RV32-NEXT:    vrgatherei16.vv v20, v16, v3866; RV32-NEXT:    vsetivli zero, 10, e32, m4, tu, ma867; RV32-NEXT:    vmv.v.v v20, v24868; RV32-NEXT:    csrr a1, vlenb869; RV32-NEXT:    slli a1, a1, 6870; RV32-NEXT:    add a1, sp, a1871; RV32-NEXT:    addi a1, a1, 16872; RV32-NEXT:    vs4r.v v20, (a1) # vscale x 32-byte Folded Spill873; RV32-NEXT:    lui a1, %hi(.LCPI27_4)874; RV32-NEXT:    addi a1, a1, %lo(.LCPI27_4)875; RV32-NEXT:    lui a2, %hi(.LCPI27_5)876; RV32-NEXT:    addi a2, a2, %lo(.LCPI27_5)877; RV32-NEXT:    vsetivli zero, 16, e16, m2, ta, ma878; RV32-NEXT:    vle16.v v24, (a2)879; RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma880; RV32-NEXT:    vle16.v v16, (a1)881; RV32-NEXT:    csrr a1, vlenb882; RV32-NEXT:    li a2, 84883; RV32-NEXT:    mul a1, a1, a2884; RV32-NEXT:    add a1, sp, a1885; RV32-NEXT:    addi a1, a1, 16886; RV32-NEXT:    vs1r.v v16, (a1) # vscale x 8-byte Folded Spill887; RV32-NEXT:    lui a1, %hi(.LCPI27_7)888; RV32-NEXT:    addi a1, a1, %lo(.LCPI27_7)889; RV32-NEXT:    vsetivli zero, 16, e64, m8, ta, ma890; RV32-NEXT:    vle16.v v16, (a1)891; RV32-NEXT:    csrr a1, vlenb892; RV32-NEXT:    li a2, 76893; RV32-NEXT:    mul a1, a1, a2894; RV32-NEXT:    add a1, sp, a1895; RV32-NEXT:    addi a1, a1, 16896; RV32-NEXT:    vs2r.v v16, (a1) # vscale x 16-byte Folded Spill897; RV32-NEXT:    csrr a1, vlenb898; RV32-NEXT:    li a2, 24899; RV32-NEXT:    mul a1, a1, a2900; RV32-NEXT:    add a1, sp, a1901; RV32-NEXT:    addi a1, a1, 16902; RV32-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload903; RV32-NEXT:    vrgatherei16.vv v16, v0, v24904; RV32-NEXT:    csrr a1, vlenb905; RV32-NEXT:    li a2, 48906; RV32-NEXT:    mul a1, a1, a2907; RV32-NEXT:    add a1, sp, a1908; RV32-NEXT:    addi a1, a1, 16909; RV32-NEXT:    vl4r.v v20, (a1) # vscale x 32-byte Folded Reload910; RV32-NEXT:    csrr a1, vlenb911; RV32-NEXT:    li a2, 84912; RV32-NEXT:    mul a1, a1, a2913; RV32-NEXT:    add a1, sp, a1914; RV32-NEXT:    addi a1, a1, 16915; RV32-NEXT:    vl1r.v v7, (a1) # vscale x 8-byte Folded Reload916; RV32-NEXT:    vsetivli zero, 8, e64, m4, ta, ma917; RV32-NEXT:    vrgatherei16.vv v24, v20, v7918; RV32-NEXT:    vsetivli zero, 10, e32, m4, tu, ma919; RV32-NEXT:    vmv.v.v v24, v16920; RV32-NEXT:    csrr a1, vlenb921; RV32-NEXT:    slli a1, a1, 3922; RV32-NEXT:    add a1, sp, a1923; RV32-NEXT:    addi a1, a1, 16924; RV32-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload925; RV32-NEXT:    csrr a1, vlenb926; RV32-NEXT:    li a2, 76927; RV32-NEXT:    mul a1, a1, a2928; RV32-NEXT:    add a1, sp, a1929; RV32-NEXT:    addi a1, a1, 16930; RV32-NEXT:    vl2r.v v28, (a1) # vscale x 16-byte Folded Reload931; RV32-NEXT:    vsetivli zero, 16, e64, m8, ta, ma932; RV32-NEXT:    vrgatherei16.vv v16, v0, v28933; RV32-NEXT:    lui a1, %hi(.LCPI27_6)934; RV32-NEXT:    addi a1, a1, %lo(.LCPI27_6)935; RV32-NEXT:    lui a2, %hi(.LCPI27_8)936; RV32-NEXT:    addi a2, a2, %lo(.LCPI27_8)937; RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma938; RV32-NEXT:    vle16.v v4, (a1)939; RV32-NEXT:    lui a1, %hi(.LCPI27_9)940; RV32-NEXT:    addi a1, a1, %lo(.LCPI27_9)941; RV32-NEXT:    vsetivli zero, 16, e16, m2, ta, ma942; RV32-NEXT:    vle16.v v6, (a1)943; RV32-NEXT:    vsetivli zero, 8, e64, m4, ta, ma944; RV32-NEXT:    vle16.v v5, (a2)945; RV32-NEXT:    csrr a1, vlenb946; RV32-NEXT:    li a2, 40947; RV32-NEXT:    mul a1, a1, a2948; RV32-NEXT:    add a1, sp, a1949; RV32-NEXT:    addi a1, a1, 16950; RV32-NEXT:    vl4r.v v20, (a1) # vscale x 32-byte Folded Reload951; RV32-NEXT:    vrgatherei16.vv v0, v20, v4952; RV32-NEXT:    vsetivli zero, 10, e32, m4, tu, ma953; RV32-NEXT:    vmv.v.v v0, v16954; RV32-NEXT:    vsetivli zero, 16, e64, m8, ta, ma955; RV32-NEXT:    vrgatherei16.vv v16, v8, v6956; RV32-NEXT:    csrr a1, vlenb957; RV32-NEXT:    li a2, 92958; RV32-NEXT:    mul a1, a1, a2959; RV32-NEXT:    add a1, sp, a1960; RV32-NEXT:    addi a1, a1, 16961; RV32-NEXT:    vl4r.v v12, (a1) # vscale x 32-byte Folded Reload962; RV32-NEXT:    vsetivli zero, 8, e64, m4, ta, ma963; RV32-NEXT:    vrgatherei16.vv v8, v12, v5964; RV32-NEXT:    vsetivli zero, 10, e32, m4, tu, ma965; RV32-NEXT:    vmv.v.v v8, v16966; RV32-NEXT:    addi a1, a0, 320967; RV32-NEXT:    vsetivli zero, 16, e32, m4, ta, ma968; RV32-NEXT:    vse32.v v8, (a1)969; RV32-NEXT:    addi a1, a0, 256970; RV32-NEXT:    vse32.v v0, (a1)971; RV32-NEXT:    addi a1, a0, 192972; RV32-NEXT:    vse32.v v24, (a1)973; RV32-NEXT:    addi a1, a0, 128974; RV32-NEXT:    csrr a2, vlenb975; RV32-NEXT:    slli a2, a2, 6976; RV32-NEXT:    add a2, sp, a2977; RV32-NEXT:    addi a2, a2, 16978; RV32-NEXT:    vl4r.v v8, (a2) # vscale x 32-byte Folded Reload979; RV32-NEXT:    vse32.v v8, (a1)980; RV32-NEXT:    addi a1, a0, 64981; RV32-NEXT:    csrr a2, vlenb982; RV32-NEXT:    li a3, 60983; RV32-NEXT:    mul a2, a2, a3984; RV32-NEXT:    add a2, sp, a2985; RV32-NEXT:    addi a2, a2, 16986; RV32-NEXT:    vl4r.v v8, (a2) # vscale x 32-byte Folded Reload987; RV32-NEXT:    vse32.v v8, (a1)988; RV32-NEXT:    csrr a1, vlenb989; RV32-NEXT:    li a2, 72990; RV32-NEXT:    mul a1, a1, a2991; RV32-NEXT:    add a1, sp, a1992; RV32-NEXT:    addi a1, a1, 16993; RV32-NEXT:    vl4r.v v8, (a1) # vscale x 32-byte Folded Reload994; RV32-NEXT:    vse32.v v8, (a0)995; RV32-NEXT:    csrr a0, vlenb996; RV32-NEXT:    li a1, 100997; RV32-NEXT:    mul a0, a0, a1998; RV32-NEXT:    add sp, sp, a0999; RV32-NEXT:    .cfi_def_cfa sp, 161000; RV32-NEXT:    addi sp, sp, 161001; RV32-NEXT:    .cfi_def_cfa_offset 01002; RV32-NEXT:    ret1003;1004; RV64-LABEL: load_factor6_too_big:1005; RV64:       # %bb.0:1006; RV64-NEXT:    addi sp, sp, -161007; RV64-NEXT:    .cfi_def_cfa_offset 161008; RV64-NEXT:    csrr a2, vlenb1009; RV64-NEXT:    li a3, 931010; RV64-NEXT:    mul a2, a2, a31011; RV64-NEXT:    sub sp, sp, a21012; RV64-NEXT:    .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0xdd, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 93 * vlenb1013; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, ma1014; RV64-NEXT:    vle64.v v8, (a1)1015; RV64-NEXT:    csrr a2, vlenb1016; RV64-NEXT:    li a3, 531017; RV64-NEXT:    mul a2, a2, a31018; RV64-NEXT:    add a2, sp, a21019; RV64-NEXT:    addi a2, a2, 161020; RV64-NEXT:    vs8r.v v8, (a2) # vscale x 64-byte Folded Spill1021; RV64-NEXT:    addi a2, a1, 1281022; RV64-NEXT:    addi a3, a1, 2561023; RV64-NEXT:    li a4, 1281024; RV64-NEXT:    lui a1, 11025; RV64-NEXT:    vle64.v v8, (a3)1026; RV64-NEXT:    lui a3, %hi(.LCPI27_0)1027; RV64-NEXT:    addi a3, a3, %lo(.LCPI27_0)1028; RV64-NEXT:    vmv.s.x v0, a41029; RV64-NEXT:    csrr a4, vlenb1030; RV64-NEXT:    li a5, 611031; RV64-NEXT:    mul a4, a4, a51032; RV64-NEXT:    add a4, sp, a41033; RV64-NEXT:    addi a4, a4, 161034; RV64-NEXT:    vs1r.v v0, (a4) # vscale x 8-byte Folded Spill1035; RV64-NEXT:    addi a4, a1, 651036; RV64-NEXT:    vsetivli zero, 8, e64, m4, ta, ma1037; RV64-NEXT:    vslideup.vi v24, v8, 21038; RV64-NEXT:    vsetivli zero, 8, e64, m8, ta, ma1039; RV64-NEXT:    vslidedown.vi v16, v8, 81040; RV64-NEXT:    csrr a5, vlenb1041; RV64-NEXT:    li a6, 771042; RV64-NEXT:    mul a5, a5, a61043; RV64-NEXT:    add a5, sp, a51044; RV64-NEXT:    addi a5, a5, 161045; RV64-NEXT:    vs8r.v v16, (a5) # vscale x 64-byte Folded Spill1046; RV64-NEXT:    csrr a5, vlenb1047; RV64-NEXT:    li a6, 771048; RV64-NEXT:    mul a5, a5, a61049; RV64-NEXT:    add a5, sp, a51050; RV64-NEXT:    addi a5, a5, 161051; RV64-NEXT:    vl8r.v v16, (a5) # vscale x 64-byte Folded Reload1052; RV64-NEXT:    vsetivli zero, 8, e64, m4, ta, mu1053; RV64-NEXT:    vslideup.vi v24, v16, 5, v0.t1054; RV64-NEXT:    csrr a5, vlenb1055; RV64-NEXT:    li a6, 731056; RV64-NEXT:    mul a5, a5, a61057; RV64-NEXT:    add a5, sp, a51058; RV64-NEXT:    addi a5, a5, 161059; RV64-NEXT:    vs4r.v v24, (a5) # vscale x 32-byte Folded Spill1060; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, ma1061; RV64-NEXT:    vle64.v v24, (a2)1062; RV64-NEXT:    csrr a2, vlenb1063; RV64-NEXT:    li a5, 851064; RV64-NEXT:    mul a2, a2, a51065; RV64-NEXT:    add a2, sp, a21066; RV64-NEXT:    addi a2, a2, 161067; RV64-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill1068; RV64-NEXT:    vle16.v v12, (a3)1069; RV64-NEXT:    vmv.s.x v0, a41070; RV64-NEXT:    csrr a2, vlenb1071; RV64-NEXT:    li a3, 851072; RV64-NEXT:    mul a2, a2, a31073; RV64-NEXT:    add a2, sp, a21074; RV64-NEXT:    addi a2, a2, 161075; RV64-NEXT:    vl8r.v v24, (a2) # vscale x 64-byte Folded Reload1076; RV64-NEXT:    csrr a2, vlenb1077; RV64-NEXT:    li a3, 531078; RV64-NEXT:    mul a2, a2, a31079; RV64-NEXT:    add a2, sp, a21080; RV64-NEXT:    addi a2, a2, 161081; RV64-NEXT:    vl8r.v v16, (a2) # vscale x 64-byte Folded Reload1082; RV64-NEXT:    vmerge.vvm v24, v24, v16, v01083; RV64-NEXT:    vrgatherei16.vv v0, v24, v121084; RV64-NEXT:    csrr a2, vlenb1085; RV64-NEXT:    li a3, 371086; RV64-NEXT:    mul a2, a2, a31087; RV64-NEXT:    add a2, sp, a21088; RV64-NEXT:    addi a2, a2, 161089; RV64-NEXT:    vs8r.v v0, (a2) # vscale x 64-byte Folded Spill1090; RV64-NEXT:    vsetivli zero, 8, e64, m4, ta, mu1091; RV64-NEXT:    vslideup.vi v12, v8, 11092; RV64-NEXT:    csrr a2, vlenb1093; RV64-NEXT:    li a3, 611094; RV64-NEXT:    mul a2, a2, a31095; RV64-NEXT:    add a2, sp, a21096; RV64-NEXT:    addi a2, a2, 161097; RV64-NEXT:    vl1r.v v7, (a2) # vscale x 8-byte Folded Reload1098; RV64-NEXT:    vmv1r.v v0, v71099; RV64-NEXT:    csrr a2, vlenb1100; RV64-NEXT:    li a3, 771101; RV64-NEXT:    mul a2, a2, a31102; RV64-NEXT:    add a2, sp, a21103; RV64-NEXT:    addi a2, a2, 161104; RV64-NEXT:    vl8r.v v24, (a2) # vscale x 64-byte Folded Reload1105; RV64-NEXT:    vslideup.vi v12, v24, 4, v0.t1106; RV64-NEXT:    csrr a2, vlenb1107; RV64-NEXT:    li a3, 691108; RV64-NEXT:    mul a2, a2, a31109; RV64-NEXT:    add a2, sp, a21110; RV64-NEXT:    addi a2, a2, 161111; RV64-NEXT:    vs4r.v v12, (a2) # vscale x 32-byte Folded Spill1112; RV64-NEXT:    lui a2, 21113; RV64-NEXT:    lui a3, 41114; RV64-NEXT:    li a4, 321115; RV64-NEXT:    addi a2, a2, 1301116; RV64-NEXT:    vmv.s.x v0, a21117; RV64-NEXT:    addi a2, a3, 2601118; RV64-NEXT:    vmv8r.v v24, v161119; RV64-NEXT:    csrr a3, vlenb1120; RV64-NEXT:    li a5, 851121; RV64-NEXT:    mul a3, a3, a51122; RV64-NEXT:    add a3, sp, a31123; RV64-NEXT:    addi a3, a3, 161124; RV64-NEXT:    vl8r.v v16, (a3) # vscale x 64-byte Folded Reload1125; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, ma1126; RV64-NEXT:    vmerge.vvm v16, v16, v24, v01127; RV64-NEXT:    csrr a3, vlenb1128; RV64-NEXT:    slli a3, a3, 31129; RV64-NEXT:    add a3, sp, a31130; RV64-NEXT:    addi a3, a3, 161131; RV64-NEXT:    vs8r.v v16, (a3) # vscale x 64-byte Folded Spill1132; RV64-NEXT:    vmv.s.x v0, a21133; RV64-NEXT:    vmv.s.x v2, a41134; RV64-NEXT:    vmv4r.v v12, v81135; RV64-NEXT:    csrr a2, vlenb1136; RV64-NEXT:    li a3, 851137; RV64-NEXT:    mul a2, a2, a31138; RV64-NEXT:    add a2, sp, a21139; RV64-NEXT:    addi a2, a2, 161140; RV64-NEXT:    vl8r.v v16, (a2) # vscale x 64-byte Folded Reload1141; RV64-NEXT:    vmerge.vvm v16, v16, v24, v01142; RV64-NEXT:    csrr a2, vlenb1143; RV64-NEXT:    li a3, 291144; RV64-NEXT:    mul a2, a2, a31145; RV64-NEXT:    add a2, sp, a21146; RV64-NEXT:    addi a2, a2, 161147; RV64-NEXT:    vs8r.v v16, (a2) # vscale x 64-byte Folded Spill1148; RV64-NEXT:    vmv1r.v v0, v21149; RV64-NEXT:    csrr a2, vlenb1150; RV64-NEXT:    li a3, 451151; RV64-NEXT:    mul a2, a2, a31152; RV64-NEXT:    add a2, sp, a21153; RV64-NEXT:    addi a2, a2, 161154; RV64-NEXT:    vs8r.v v8, (a2) # vscale x 64-byte Folded Spill1155; RV64-NEXT:    vsetivli zero, 8, e64, m4, ta, mu1156; RV64-NEXT:    vslideup.vi v12, v8, 5, v0.t1157; RV64-NEXT:    vmv1r.v v0, v71158; RV64-NEXT:    csrr a2, vlenb1159; RV64-NEXT:    li a3, 771160; RV64-NEXT:    mul a2, a2, a31161; RV64-NEXT:    add a2, sp, a21162; RV64-NEXT:    addi a2, a2, 161163; RV64-NEXT:    vl8r.v v24, (a2) # vscale x 64-byte Folded Reload1164; RV64-NEXT:    vrgather.vi v12, v24, 4, v0.t1165; RV64-NEXT:    csrr a2, vlenb1166; RV64-NEXT:    slli a3, a2, 61167; RV64-NEXT:    add a2, a3, a21168; RV64-NEXT:    add a2, sp, a21169; RV64-NEXT:    addi a2, a2, 161170; RV64-NEXT:    vs4r.v v12, (a2) # vscale x 32-byte Folded Spill1171; RV64-NEXT:    vslidedown.vi v12, v8, 11172; RV64-NEXT:    vmv1r.v v0, v21173; RV64-NEXT:    vslideup.vi v12, v8, 4, v0.t1174; RV64-NEXT:    vmv1r.v v0, v71175; RV64-NEXT:    vrgather.vi v12, v24, 5, v0.t1176; RV64-NEXT:    csrr a2, vlenb1177; RV64-NEXT:    li a3, 251178; RV64-NEXT:    mul a2, a2, a31179; RV64-NEXT:    add a2, sp, a21180; RV64-NEXT:    addi a2, a2, 161181; RV64-NEXT:    vs4r.v v12, (a2) # vscale x 32-byte Folded Spill1182; RV64-NEXT:    lui a2, 81183; RV64-NEXT:    addi a2, a2, 5201184; RV64-NEXT:    vmv.s.x v0, a21185; RV64-NEXT:    vslideup.vi v12, v24, 61186; RV64-NEXT:    csrr a2, vlenb1187; RV64-NEXT:    li a3, 851188; RV64-NEXT:    mul a2, a2, a31189; RV64-NEXT:    add a2, sp, a21190; RV64-NEXT:    addi a2, a2, 161191; RV64-NEXT:    vl8r.v v16, (a2) # vscale x 64-byte Folded Reload1192; RV64-NEXT:    csrr a2, vlenb1193; RV64-NEXT:    li a3, 531194; RV64-NEXT:    mul a2, a2, a31195; RV64-NEXT:    add a2, sp, a21196; RV64-NEXT:    addi a2, a2, 161197; RV64-NEXT:    vl8r.v v24, (a2) # vscale x 64-byte Folded Reload1198; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, ma1199; RV64-NEXT:    vmerge.vvm v16, v16, v24, v01200; RV64-NEXT:    csrr a2, vlenb1201; RV64-NEXT:    slli a3, a2, 41202; RV64-NEXT:    add a2, a3, a21203; RV64-NEXT:    add a2, sp, a21204; RV64-NEXT:    addi a2, a2, 161205; RV64-NEXT:    vs8r.v v16, (a2) # vscale x 64-byte Folded Spill1206; RV64-NEXT:    vmv1r.v v0, v71207; RV64-NEXT:    csrr a2, vlenb1208; RV64-NEXT:    li a3, 771209; RV64-NEXT:    mul a2, a2, a31210; RV64-NEXT:    add a2, sp, a21211; RV64-NEXT:    addi a2, a2, 161212; RV64-NEXT:    vl8r.v v16, (a2) # vscale x 64-byte Folded Reload1213; RV64-NEXT:    vsetivli zero, 8, e64, m4, ta, mu1214; RV64-NEXT:    vslideup.vi v12, v16, 1, v0.t1215; RV64-NEXT:    lui a2, %hi(.LCPI27_1)1216; RV64-NEXT:    addi a2, a2, %lo(.LCPI27_1)1217; RV64-NEXT:    li a3, 1921218; RV64-NEXT:    vsetivli zero, 16, e16, m2, ta, ma1219; RV64-NEXT:    vle16.v v6, (a2)1220; RV64-NEXT:    vmv.s.x v0, a31221; RV64-NEXT:    csrr a2, vlenb1222; RV64-NEXT:    slli a2, a2, 41223; RV64-NEXT:    add a2, sp, a21224; RV64-NEXT:    addi a2, a2, 161225; RV64-NEXT:    vs1r.v v0, (a2) # vscale x 8-byte Folded Spill1226; RV64-NEXT:    csrr a2, vlenb1227; RV64-NEXT:    li a3, 451228; RV64-NEXT:    mul a2, a2, a31229; RV64-NEXT:    add a2, sp, a21230; RV64-NEXT:    addi a2, a2, 161231; RV64-NEXT:    vl8r.v v16, (a2) # vscale x 64-byte Folded Reload1232; RV64-NEXT:    vsetivli zero, 8, e64, m4, ta, ma1233; RV64-NEXT:    vrgather.vi v28, v16, 21234; RV64-NEXT:    vmerge.vvm v16, v28, v12, v01235; RV64-NEXT:    csrr a2, vlenb1236; RV64-NEXT:    li a3, 611237; RV64-NEXT:    mul a2, a2, a31238; RV64-NEXT:    add a2, sp, a21239; RV64-NEXT:    addi a2, a2, 161240; RV64-NEXT:    vs4r.v v16, (a2) # vscale x 32-byte Folded Spill1241; RV64-NEXT:    csrr a2, vlenb1242; RV64-NEXT:    slli a2, a2, 31243; RV64-NEXT:    add a2, sp, a21244; RV64-NEXT:    addi a2, a2, 161245; RV64-NEXT:    vl8r.v v16, (a2) # vscale x 64-byte Folded Reload1246; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, ma1247; RV64-NEXT:    vrgatherei16.vv v24, v16, v61248; RV64-NEXT:    addi a2, sp, 161249; RV64-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill1250; RV64-NEXT:    lui a2, %hi(.LCPI27_2)1251; RV64-NEXT:    addi a2, a2, %lo(.LCPI27_2)1252; RV64-NEXT:    li a3, 10401253; RV64-NEXT:    vmv.s.x v0, a31254; RV64-NEXT:    addi a1, a1, -20161255; RV64-NEXT:    csrr a3, vlenb1256; RV64-NEXT:    li a4, 851257; RV64-NEXT:    mul a3, a3, a41258; RV64-NEXT:    add a3, sp, a31259; RV64-NEXT:    addi a3, a3, 161260; RV64-NEXT:    vl8r.v v24, (a3) # vscale x 64-byte Folded Reload1261; RV64-NEXT:    csrr a3, vlenb1262; RV64-NEXT:    li a4, 531263; RV64-NEXT:    mul a3, a3, a41264; RV64-NEXT:    add a3, sp, a31265; RV64-NEXT:    addi a3, a3, 161266; RV64-NEXT:    vl8r.v v16, (a3) # vscale x 64-byte Folded Reload1267; RV64-NEXT:    vmerge.vvm v8, v24, v16, v01268; RV64-NEXT:    csrr a3, vlenb1269; RV64-NEXT:    slli a3, a3, 31270; RV64-NEXT:    add a3, sp, a31271; RV64-NEXT:    addi a3, a3, 161272; RV64-NEXT:    vs8r.v v8, (a3) # vscale x 64-byte Folded Spill1273; RV64-NEXT:    vmv.s.x v0, a11274; RV64-NEXT:    vle16.v v6, (a2)1275; RV64-NEXT:    li a1, 641276; RV64-NEXT:    vmerge.vvm v8, v24, v16, v01277; RV64-NEXT:    csrr a2, vlenb1278; RV64-NEXT:    li a3, 851279; RV64-NEXT:    mul a2, a2, a31280; RV64-NEXT:    add a2, sp, a21281; RV64-NEXT:    addi a2, a2, 161282; RV64-NEXT:    vs8r.v v8, (a2) # vscale x 64-byte Folded Spill1283; RV64-NEXT:    vmv.s.x v0, a11284; RV64-NEXT:    csrr a1, vlenb1285; RV64-NEXT:    li a2, 291286; RV64-NEXT:    mul a1, a1, a21287; RV64-NEXT:    add a1, sp, a11288; RV64-NEXT:    addi a1, a1, 161289; RV64-NEXT:    vl8r.v v16, (a1) # vscale x 64-byte Folded Reload1290; RV64-NEXT:    vrgatherei16.vv v24, v16, v61291; RV64-NEXT:    csrr a1, vlenb1292; RV64-NEXT:    li a2, 771293; RV64-NEXT:    mul a1, a1, a21294; RV64-NEXT:    add a1, sp, a11295; RV64-NEXT:    addi a1, a1, 161296; RV64-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload1297; RV64-NEXT:    vmv4r.v v28, v81298; RV64-NEXT:    vsetivli zero, 8, e64, m4, ta, mu1299; RV64-NEXT:    vslideup.vi v28, v8, 5, v0.t1300; RV64-NEXT:    csrr a1, vlenb1301; RV64-NEXT:    li a2, 731302; RV64-NEXT:    mul a1, a1, a21303; RV64-NEXT:    add a1, sp, a11304; RV64-NEXT:    addi a1, a1, 161305; RV64-NEXT:    vl4r.v v8, (a1) # vscale x 32-byte Folded Reload1306; RV64-NEXT:    csrr a1, vlenb1307; RV64-NEXT:    li a2, 371308; RV64-NEXT:    mul a1, a1, a21309; RV64-NEXT:    add a1, sp, a11310; RV64-NEXT:    addi a1, a1, 161311; RV64-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload1312; RV64-NEXT:    vsetivli zero, 6, e64, m4, tu, ma1313; RV64-NEXT:    vmv.v.v v8, v01314; RV64-NEXT:    csrr a1, vlenb1315; RV64-NEXT:    li a2, 731316; RV64-NEXT:    mul a1, a1, a21317; RV64-NEXT:    add a1, sp, a11318; RV64-NEXT:    addi a1, a1, 161319; RV64-NEXT:    vs4r.v v8, (a1) # vscale x 32-byte Folded Spill1320; RV64-NEXT:    csrr a1, vlenb1321; RV64-NEXT:    li a2, 691322; RV64-NEXT:    mul a1, a1, a21323; RV64-NEXT:    add a1, sp, a11324; RV64-NEXT:    addi a1, a1, 161325; RV64-NEXT:    vl4r.v v8, (a1) # vscale x 32-byte Folded Reload1326; RV64-NEXT:    addi a1, sp, 161327; RV64-NEXT:    vl8r.v v16, (a1) # vscale x 64-byte Folded Reload1328; RV64-NEXT:    vmv.v.v v8, v161329; RV64-NEXT:    csrr a1, vlenb1330; RV64-NEXT:    li a2, 691331; RV64-NEXT:    mul a1, a1, a21332; RV64-NEXT:    add a1, sp, a11333; RV64-NEXT:    addi a1, a1, 161334; RV64-NEXT:    vs4r.v v8, (a1) # vscale x 32-byte Folded Spill1335; RV64-NEXT:    lui a1, %hi(.LCPI27_3)1336; RV64-NEXT:    addi a1, a1, %lo(.LCPI27_3)1337; RV64-NEXT:    vsetivli zero, 16, e16, m2, ta, ma1338; RV64-NEXT:    vle16.v v20, (a1)1339; RV64-NEXT:    lui a1, %hi(.LCPI27_4)1340; RV64-NEXT:    addi a1, a1, %lo(.LCPI27_4)1341; RV64-NEXT:    vle16.v v8, (a1)1342; RV64-NEXT:    csrr a1, vlenb1343; RV64-NEXT:    li a2, 771344; RV64-NEXT:    mul a1, a1, a21345; RV64-NEXT:    add a1, sp, a11346; RV64-NEXT:    addi a1, a1, 161347; RV64-NEXT:    vs2r.v v8, (a1) # vscale x 16-byte Folded Spill1348; RV64-NEXT:    csrr a1, vlenb1349; RV64-NEXT:    slli a2, a1, 61350; RV64-NEXT:    add a1, a2, a11351; RV64-NEXT:    add a1, sp, a11352; RV64-NEXT:    addi a1, a1, 161353; RV64-NEXT:    vl4r.v v8, (a1) # vscale x 32-byte Folded Reload1354; RV64-NEXT:    vsetivli zero, 5, e64, m4, tu, ma1355; RV64-NEXT:    vmv.v.v v8, v241356; RV64-NEXT:    csrr a1, vlenb1357; RV64-NEXT:    slli a2, a1, 61358; RV64-NEXT:    add a1, a2, a11359; RV64-NEXT:    add a1, sp, a11360; RV64-NEXT:    addi a1, a1, 161361; RV64-NEXT:    vs4r.v v8, (a1) # vscale x 32-byte Folded Spill1362; RV64-NEXT:    csrr a1, vlenb1363; RV64-NEXT:    slli a2, a1, 41364; RV64-NEXT:    add a1, a2, a11365; RV64-NEXT:    add a1, sp, a11366; RV64-NEXT:    addi a1, a1, 161367; RV64-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload1368; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, ma1369; RV64-NEXT:    vrgatherei16.vv v0, v8, v201370; RV64-NEXT:    csrr a1, vlenb1371; RV64-NEXT:    li a2, 251372; RV64-NEXT:    mul a1, a1, a21373; RV64-NEXT:    add a1, sp, a11374; RV64-NEXT:    addi a1, a1, 161375; RV64-NEXT:    vl4r.v v12, (a1) # vscale x 32-byte Folded Reload1376; RV64-NEXT:    vsetivli zero, 5, e64, m4, tu, ma1377; RV64-NEXT:    vmv.v.v v12, v01378; RV64-NEXT:    csrr a1, vlenb1379; RV64-NEXT:    slli a1, a1, 31380; RV64-NEXT:    add a1, sp, a11381; RV64-NEXT:    addi a1, a1, 161382; RV64-NEXT:    vl8r.v v16, (a1) # vscale x 64-byte Folded Reload1383; RV64-NEXT:    csrr a1, vlenb1384; RV64-NEXT:    li a2, 771385; RV64-NEXT:    mul a1, a1, a21386; RV64-NEXT:    add a1, sp, a11387; RV64-NEXT:    addi a1, a1, 161388; RV64-NEXT:    vl2r.v v8, (a1) # vscale x 16-byte Folded Reload1389; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, ma1390; RV64-NEXT:    vrgatherei16.vv v0, v16, v81391; RV64-NEXT:    lui a1, %hi(.LCPI27_5)1392; RV64-NEXT:    addi a1, a1, %lo(.LCPI27_5)1393; RV64-NEXT:    vle16.v v20, (a1)1394; RV64-NEXT:    csrr a1, vlenb1395; RV64-NEXT:    li a2, 611396; RV64-NEXT:    mul a1, a1, a21397; RV64-NEXT:    add a1, sp, a11398; RV64-NEXT:    addi a1, a1, 161399; RV64-NEXT:    vl4r.v v8, (a1) # vscale x 32-byte Folded Reload1400; RV64-NEXT:    vsetivli zero, 5, e64, m4, tu, ma1401; RV64-NEXT:    vmv.v.v v8, v01402; RV64-NEXT:    csrr a1, vlenb1403; RV64-NEXT:    li a2, 611404; RV64-NEXT:    mul a1, a1, a21405; RV64-NEXT:    add a1, sp, a11406; RV64-NEXT:    addi a1, a1, 161407; RV64-NEXT:    vs4r.v v8, (a1) # vscale x 32-byte Folded Spill1408; RV64-NEXT:    csrr a1, vlenb1409; RV64-NEXT:    li a2, 451410; RV64-NEXT:    mul a1, a1, a21411; RV64-NEXT:    add a1, sp, a11412; RV64-NEXT:    addi a1, a1, 161413; RV64-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload1414; RV64-NEXT:    vsetivli zero, 8, e64, m4, ta, ma1415; RV64-NEXT:    vrgather.vi v8, v0, 31416; RV64-NEXT:    csrr a1, vlenb1417; RV64-NEXT:    slli a1, a1, 41418; RV64-NEXT:    add a1, sp, a11419; RV64-NEXT:    addi a1, a1, 161420; RV64-NEXT:    vl1r.v v0, (a1) # vscale x 8-byte Folded Reload1421; RV64-NEXT:    vmerge.vvm v8, v8, v28, v01422; RV64-NEXT:    csrr a1, vlenb1423; RV64-NEXT:    li a2, 851424; RV64-NEXT:    mul a1, a1, a21425; RV64-NEXT:    add a1, sp, a11426; RV64-NEXT:    addi a1, a1, 161427; RV64-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload1428; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, ma1429; RV64-NEXT:    vrgatherei16.vv v24, v0, v201430; RV64-NEXT:    vsetivli zero, 5, e64, m4, tu, ma1431; RV64-NEXT:    vmv.v.v v8, v241432; RV64-NEXT:    addi a1, a0, 3201433; RV64-NEXT:    vsetivli zero, 8, e64, m4, ta, ma1434; RV64-NEXT:    vse64.v v8, (a1)1435; RV64-NEXT:    addi a1, a0, 2561436; RV64-NEXT:    csrr a2, vlenb1437; RV64-NEXT:    li a3, 611438; RV64-NEXT:    mul a2, a2, a31439; RV64-NEXT:    add a2, sp, a21440; RV64-NEXT:    addi a2, a2, 161441; RV64-NEXT:    vl4r.v v8, (a2) # vscale x 32-byte Folded Reload1442; RV64-NEXT:    vse64.v v8, (a1)1443; RV64-NEXT:    addi a1, a0, 1921444; RV64-NEXT:    vse64.v v12, (a1)1445; RV64-NEXT:    addi a1, a0, 1281446; RV64-NEXT:    csrr a2, vlenb1447; RV64-NEXT:    slli a3, a2, 61448; RV64-NEXT:    add a2, a3, a21449; RV64-NEXT:    add a2, sp, a21450; RV64-NEXT:    addi a2, a2, 161451; RV64-NEXT:    vl4r.v v8, (a2) # vscale x 32-byte Folded Reload1452; RV64-NEXT:    vse64.v v8, (a1)1453; RV64-NEXT:    addi a1, a0, 641454; RV64-NEXT:    csrr a2, vlenb1455; RV64-NEXT:    li a3, 691456; RV64-NEXT:    mul a2, a2, a31457; RV64-NEXT:    add a2, sp, a21458; RV64-NEXT:    addi a2, a2, 161459; RV64-NEXT:    vl4r.v v8, (a2) # vscale x 32-byte Folded Reload1460; RV64-NEXT:    vse64.v v8, (a1)1461; RV64-NEXT:    csrr a1, vlenb1462; RV64-NEXT:    li a2, 731463; RV64-NEXT:    mul a1, a1, a21464; RV64-NEXT:    add a1, sp, a11465; RV64-NEXT:    addi a1, a1, 161466; RV64-NEXT:    vl4r.v v8, (a1) # vscale x 32-byte Folded Reload1467; RV64-NEXT:    vse64.v v8, (a0)1468; RV64-NEXT:    csrr a0, vlenb1469; RV64-NEXT:    li a1, 931470; RV64-NEXT:    mul a0, a0, a11471; RV64-NEXT:    add sp, sp, a01472; RV64-NEXT:    .cfi_def_cfa sp, 161473; RV64-NEXT:    addi sp, sp, 161474; RV64-NEXT:    .cfi_def_cfa_offset 01475; RV64-NEXT:    ret1476  %interleaved.vec = load <48 x i64>, ptr %ptr1477  %v0 = shufflevector <48 x i64> %interleaved.vec, <48 x i64> poison, <8 x i32> <i32 0, i32 6, i32 12, i32 18, i32 24, i32 30, i32 36, i32 42>1478  %v1 = shufflevector <48 x i64> %interleaved.vec, <48 x i64> poison, <8 x i32> <i32 1, i32 7, i32 13, i32 19, i32 25, i32 31, i32 37, i32 43>1479  %v2 = shufflevector <48 x i64> %interleaved.vec, <48 x i64> poison, <8 x i32> <i32 2, i32 8, i32 14, i32 20, i32 26, i32 32, i32 38, i32 44>1480  %v3 = shufflevector <48 x i64> %interleaved.vec, <48 x i64> poison, <8 x i32> <i32 3, i32 9, i32 15, i32 21, i32 27, i32 33, i32 39, i32 45>1481  %v4 = shufflevector <48 x i64> %interleaved.vec, <48 x i64> poison, <8 x i32> <i32 4, i32 10, i32 16, i32 22, i32 28, i32 34, i32 40, i32 46>1482  %v5 = shufflevector <48 x i64> %interleaved.vec, <48 x i64> poison, <8 x i32> <i32 5, i32 11, i32 17, i32 23, i32 29, i32 35, i32 41, i32 47>1483  %res0 = insertvalue {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} poison, <8 x i64> %v0, 01484  %res1 = insertvalue {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} %res0, <8 x i64> %v1, 11485  %res2 = insertvalue {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} %res1, <8 x i64> %v2, 21486  %res3 = insertvalue {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} %res2, <8 x i64> %v3, 31487  %res4 = insertvalue {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} %res3, <8 x i64> %v4, 41488  %res5 = insertvalue {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} %res4, <8 x i64> %v5, 51489  ret {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} %res51490}1491 1492 1493; ------------------------------------------------------------------------------1494; Stores1495; ------------------------------------------------------------------------------1496 1497define void @store_factor2(ptr %ptr, <4 x i32> %v0, <4 x i32> %v1) {1498; CHECK-LABEL: store_factor2:1499; CHECK:       # %bb.0:1500; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma1501; CHECK-NEXT:    vsseg2e32.v v8, (a0)1502; CHECK-NEXT:    ret1503  %interleaved.vec = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>1504  store <8 x i32> %interleaved.vec, ptr %ptr1505  ret void1506}1507 1508define void @store_factor3(ptr %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {1509; CHECK-LABEL: store_factor3:1510; CHECK:       # %bb.0:1511; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma1512; CHECK-NEXT:    vsseg3e32.v v8, (a0)1513; CHECK-NEXT:    ret1514  %s0 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>1515  %s1 = shufflevector <4 x i32> %v2, <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>1516  %interleaved.vec = shufflevector <8 x i32> %s0, <8 x i32> %s1, <12 x i32> <i32 0, i32 4, i32 8, i32 1, i32 5, i32 9, i32 2, i32 6, i32 10, i32 3, i32 7, i32 11>1517  store <12 x i32> %interleaved.vec, ptr %ptr1518  ret void1519}1520 1521define void @store_factor4(ptr %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3) {1522; CHECK-LABEL: store_factor4:1523; CHECK:       # %bb.0:1524; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma1525; CHECK-NEXT:    vsseg4e32.v v8, (a0)1526; CHECK-NEXT:    ret1527  %s0 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>1528  %s1 = shufflevector <4 x i32> %v2, <4 x i32> %v3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>1529  %interleaved.vec = shufflevector <8 x i32> %s0, <8 x i32> %s1, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 1, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15>1530  store <16 x i32> %interleaved.vec, ptr %ptr1531  ret void1532}1533 1534define void @store_factor5(ptr %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3, <4 x i32> %v4) {1535; CHECK-LABEL: store_factor5:1536; CHECK:       # %bb.0:1537; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma1538; CHECK-NEXT:    vsseg5e32.v v8, (a0)1539; CHECK-NEXT:    ret1540  %s0 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>1541  %s1 = shufflevector <4 x i32> %v2, <4 x i32> %v3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>1542  %s2 = shufflevector <8 x i32> %s0, <8 x i32> %s1, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>1543  %s3 = shufflevector <4 x i32> %v4, <4 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>1544  %interleaved.vec = shufflevector <16 x i32> %s2, <16 x i32> %s3, <20 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 1, i32 5, i32 9, i32 13, i32 17, i32 2, i32 6, i32 10, i32 14, i32 18, i32 3, i32 7, i32 11, i32 15, i32 19>1545  store <20 x i32> %interleaved.vec, ptr %ptr1546  ret void1547}1548 1549define void @store_factor6(ptr %ptr, <2 x i16> %v0, <2 x i16> %v1, <2 x i16> %v2, <2 x i16> %v3, <2 x i16> %v4, <2 x i16> %v5) {1550; CHECK-LABEL: store_factor6:1551; CHECK:       # %bb.0:1552; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma1553; CHECK-NEXT:    vsseg6e16.v v8, (a0)1554; CHECK-NEXT:    ret1555  %s0 = shufflevector <2 x i16> %v0, <2 x i16> %v1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>1556  %s1 = shufflevector <2 x i16> %v2, <2 x i16> %v3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>1557  %s2 = shufflevector <4 x i16> %s0, <4 x i16> %s1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>1558  %s3 = shufflevector <2 x i16> %v4, <2 x i16> %v5, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>1559  %interleaved.vec = shufflevector <8 x i16> %s2, <8 x i16> %s3, <12 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 1, i32 3, i32 5, i32 7, i32 9, i32 11>1560  store <12 x i16> %interleaved.vec, ptr %ptr1561  ret void1562}1563 1564define void @store_factor7(ptr %ptr, <2 x i16> %v0, <2 x i16> %v1, <2 x i16> %v2, <2 x i16> %v3, <2 x i16> %v4, <2 x i16> %v5, <2 x i16> %v6) {1565; CHECK-LABEL: store_factor7:1566; CHECK:       # %bb.0:1567; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma1568; CHECK-NEXT:    vsseg7e16.v v8, (a0)1569; CHECK-NEXT:    ret1570  %s0 = shufflevector <2 x i16> %v0, <2 x i16> %v1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>1571  %s1 = shufflevector <2 x i16> %v2, <2 x i16> %v3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>1572  %s2 = shufflevector <2 x i16> %v4, <2 x i16> %v5, <4 x i32> <i32 0, i32 1, i32 2, i32 3>1573  %s3 = shufflevector <4 x i16> %s0, <4 x i16> %s1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>1574  %s4 = shufflevector <2 x i16> %v6, <2 x i16> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>1575  %s5 = shufflevector <4 x i16> %s2, <4 x i16> %s4, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 poison, i32 poison>1576  %interleaved.vec = shufflevector <8 x i16> %s3, <8 x i16> %s5, <14 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13>1577  store <14 x i16> %interleaved.vec, ptr %ptr1578  ret void1579}1580 1581define void @store_factor8(ptr %ptr, <2 x i16> %v0, <2 x i16> %v1, <2 x i16> %v2, <2 x i16> %v3, <2 x i16> %v4, <2 x i16> %v5, <2 x i16> %v6, <2 x i16> %v7) {1582; CHECK-LABEL: store_factor8:1583; CHECK:       # %bb.0:1584; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma1585; CHECK-NEXT:    vsseg8e16.v v8, (a0)1586; CHECK-NEXT:    ret1587  %s0 = shufflevector <2 x i16> %v0, <2 x i16> %v1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>1588  %s1 = shufflevector <2 x i16> %v2, <2 x i16> %v3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>1589  %s2 = shufflevector <2 x i16> %v4, <2 x i16> %v5, <4 x i32> <i32 0, i32 1, i32 2, i32 3>1590  %s3 = shufflevector <4 x i16> %s0, <4 x i16> %s1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>1591  %s4 = shufflevector <2 x i16> %v6, <2 x i16> %v7, <4 x i32> <i32 0, i32 1, i32 2, i32 3>1592  %s5 = shufflevector <4 x i16> %s2, <4 x i16> %s4, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>1593  %interleaved.vec = shufflevector <8 x i16> %s3, <8 x i16> %s5, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>1594  store <16 x i16> %interleaved.vec, ptr %ptr1595  ret void1596}1597 1598define void @vpstore_factor2(ptr %ptr, <4 x i32> %v0, <4 x i32> %v1) {1599; CHECK-LABEL: vpstore_factor2:1600; CHECK:       # %bb.0:1601; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma1602; CHECK-NEXT:    vsseg2e32.v v8, (a0)1603; CHECK-NEXT:    ret1604  %interleaved.vec = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>1605  tail call void @llvm.vp.store.v8i32.p0(<8 x i32> %interleaved.vec, ptr %ptr, <8 x i1> splat (i1 true), i32 8)1606  ret void1607}1608 1609define void @vpstore_factor2_interleaved_mask_intrinsic(ptr %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i1> %m) {1610; CHECK-LABEL: vpstore_factor2_interleaved_mask_intrinsic:1611; CHECK:       # %bb.0:1612; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma1613; CHECK-NEXT:    vsseg2e32.v v8, (a0), v0.t1614; CHECK-NEXT:    ret1615  %interleaved.mask = call <8 x i1> @llvm.vector.interleave2(<4 x i1> %m, <4 x i1> %m)1616  %interleaved.vec = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>1617  tail call void @llvm.vp.store.v8i32.p0(<8 x i32> %interleaved.vec, ptr %ptr, <8 x i1> %interleaved.mask, i32 8)1618  ret void1619}1620 1621 1622define void @vpstore_factor3(ptr %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {1623; CHECK-LABEL: vpstore_factor3:1624; CHECK:       # %bb.0:1625; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma1626; CHECK-NEXT:    vsseg3e32.v v8, (a0)1627; CHECK-NEXT:    ret1628  %s0 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>1629  %s1 = shufflevector <4 x i32> %v2, <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>1630  %interleaved.vec = shufflevector <8 x i32> %s0, <8 x i32> %s1, <12 x i32> <i32 0, i32 4, i32 8, i32 1, i32 5, i32 9, i32 2, i32 6, i32 10, i32 3, i32 7, i32 11>1631  tail call void @llvm.vp.store.v12i32.p0(<12 x i32> %interleaved.vec, ptr %ptr, <12 x i1> splat (i1 true), i32 12)1632  ret void1633}1634 1635define void @vpstore_factor3_mask(ptr %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {1636; CHECK-LABEL: vpstore_factor3_mask:1637; CHECK:       # %bb.0:1638; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma1639; CHECK-NEXT:    vmv.v.i v0, 51640; CHECK-NEXT:    vsseg3e32.v v8, (a0), v0.t1641; CHECK-NEXT:    ret1642  %s0 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>1643  %s1 = shufflevector <4 x i32> %v2, <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>1644  %interleaved.vec = shufflevector <8 x i32> %s0, <8 x i32> %s1, <12 x i32> <i32 0, i32 4, i32 8, i32 1, i32 5, i32 9, i32 2, i32 6, i32 10, i32 3, i32 7, i32 11>1645  tail call void @llvm.vp.store.v12i32.p0(<12 x i32> %interleaved.vec, ptr %ptr, <12 x i1> <i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0>, i32 12)1646  ret void1647}1648 1649; mask = all ones, skip the last field.1650define void @vpstore_factor3_gap(ptr %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {1651; CHECK-LABEL: vpstore_factor3_gap:1652; CHECK:       # %bb.0:1653; CHECK-NEXT:    li a1, 121654; CHECK-NEXT:    vsetivli zero, 6, e32, m1, ta, ma1655; CHECK-NEXT:    vssseg2e32.v v8, (a0), a11656; CHECK-NEXT:    ret1657  %s0 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>1658  %s1 = shufflevector <4 x i32> %v2, <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>1659  %interleaved.vec = shufflevector <8 x i32> %s0, <8 x i32> %s1, <12 x i32> <i32 0, i32 4, i32 8, i32 1, i32 5, i32 9, i32 2, i32 6, i32 10, i32 3, i32 7, i32 11>1660  tail call void @llvm.vp.store.v12i32.p0(<12 x i32> %interleaved.vec, ptr %ptr, <12 x i1> <i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0>, i32 12)1661  ret void1662}1663 1664; mask = 1010, skip the last field.1665define void @vpstore_factor3_gap_with_mask(ptr %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {1666; CHECK-LABEL: vpstore_factor3_gap_with_mask:1667; CHECK:       # %bb.0:1668; CHECK-NEXT:    vsetivli zero, 6, e32, m1, ta, ma1669; CHECK-NEXT:    vmv.v.i v0, 51670; CHECK-NEXT:    li a1, 121671; CHECK-NEXT:    vssseg2e32.v v8, (a0), a1, v0.t1672; CHECK-NEXT:    ret1673  %s0 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>1674  %s1 = shufflevector <4 x i32> %v2, <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>1675  %interleaved.vec = shufflevector <8 x i32> %s0, <8 x i32> %s1, <12 x i32> <i32 0, i32 4, i32 8, i32 1, i32 5, i32 9, i32 2, i32 6, i32 10, i32 3, i32 7, i32 11>1676  tail call void @llvm.vp.store.v12i32.p0(<12 x i32> %interleaved.vec, ptr %ptr, <12 x i1> <i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0>, i32 12)1677  ret void1678}1679 1680define void @vpstore_factor4(ptr %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3) {1681; CHECK-LABEL: vpstore_factor4:1682; CHECK:       # %bb.0:1683; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma1684; CHECK-NEXT:    vsseg4e32.v v8, (a0)1685; CHECK-NEXT:    ret1686  %s0 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>1687  %s1 = shufflevector <4 x i32> %v2, <4 x i32> %v3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>1688  %interleaved.vec = shufflevector <8 x i32> %s0, <8 x i32> %s1, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 1, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15>1689  tail call void @llvm.vp.store.v16i32.p0(<16 x i32> %interleaved.vec, ptr %ptr, <16 x i1> splat (i1 true), i32 16)1690  ret void1691}1692 1693define void @vpstore_factor5(ptr %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3, <4 x i32> %v4) {1694; CHECK-LABEL: vpstore_factor5:1695; CHECK:       # %bb.0:1696; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma1697; CHECK-NEXT:    vsseg5e32.v v8, (a0)1698; CHECK-NEXT:    ret1699  %s0 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>1700  %s1 = shufflevector <4 x i32> %v2, <4 x i32> %v3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>1701  %s2 = shufflevector <8 x i32> %s0, <8 x i32> %s1, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>1702  %s3 = shufflevector <4 x i32> %v4, <4 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>1703  %interleaved.vec = shufflevector <16 x i32> %s2, <16 x i32> %s3, <20 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 1, i32 5, i32 9, i32 13, i32 17, i32 2, i32 6, i32 10, i32 14, i32 18, i32 3, i32 7, i32 11, i32 15, i32 19>1704  tail call void @llvm.vp.store.v20i32.p0(<20 x i32> %interleaved.vec, ptr %ptr, <20 x i1> splat (i1 true), i32 20)1705  ret void1706}1707 1708define void @vpstore_factor6(ptr %ptr, <2 x i16> %v0, <2 x i16> %v1, <2 x i16> %v2, <2 x i16> %v3, <2 x i16> %v4, <2 x i16> %v5) {1709; CHECK-LABEL: vpstore_factor6:1710; CHECK:       # %bb.0:1711; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma1712; CHECK-NEXT:    vsseg6e16.v v8, (a0)1713; CHECK-NEXT:    ret1714  %s0 = shufflevector <2 x i16> %v0, <2 x i16> %v1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>1715  %s1 = shufflevector <2 x i16> %v2, <2 x i16> %v3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>1716  %s2 = shufflevector <4 x i16> %s0, <4 x i16> %s1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>1717  %s3 = shufflevector <2 x i16> %v4, <2 x i16> %v5, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>1718  %interleaved.vec = shufflevector <8 x i16> %s2, <8 x i16> %s3, <12 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 1, i32 3, i32 5, i32 7, i32 9, i32 11>1719  tail call void @llvm.vp.store.v12i16.p0(<12 x i16> %interleaved.vec, ptr %ptr, <12 x i1> splat (i1 true), i32 12)1720  ret void1721}1722 1723define void @vpstore_factor7(ptr %ptr, <2 x i16> %v0, <2 x i16> %v1, <2 x i16> %v2, <2 x i16> %v3, <2 x i16> %v4, <2 x i16> %v5, <2 x i16> %v6) {1724; CHECK-LABEL: vpstore_factor7:1725; CHECK:       # %bb.0:1726; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma1727; CHECK-NEXT:    vsseg7e16.v v8, (a0)1728; CHECK-NEXT:    ret1729  %s0 = shufflevector <2 x i16> %v0, <2 x i16> %v1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>1730  %s1 = shufflevector <2 x i16> %v2, <2 x i16> %v3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>1731  %s2 = shufflevector <2 x i16> %v4, <2 x i16> %v5, <4 x i32> <i32 0, i32 1, i32 2, i32 3>1732  %s3 = shufflevector <4 x i16> %s0, <4 x i16> %s1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>1733  %s4 = shufflevector <2 x i16> %v6, <2 x i16> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>1734  %s5 = shufflevector <4 x i16> %s2, <4 x i16> %s4, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 poison, i32 poison>1735  %interleaved.vec = shufflevector <8 x i16> %s3, <8 x i16> %s5, <14 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13>1736  tail call void @llvm.vp.store.v14i16.p0(<14 x i16> %interleaved.vec, ptr %ptr, <14 x i1> splat (i1 true), i32 14)1737  ret void1738}1739 1740define void @vpstore_factor7_masked(ptr %ptr, <2 x i16> %v0, <2 x i16> %v1, <2 x i16> %v2, <2 x i16> %v3, <2 x i16> %v4, <2 x i16> %v5, <2 x i16> %v6, <2 x i1> %m) {1741; CHECK-LABEL: vpstore_factor7_masked:1742; CHECK:       # %bb.0:1743; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma1744; CHECK-NEXT:    vsseg7e16.v v8, (a0), v0.t1745; CHECK-NEXT:    ret1746  %interleaved.mask = shufflevector <2 x i1> %m, <2 x i1> poison, <14 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>1747  %s0 = shufflevector <2 x i16> %v0, <2 x i16> %v1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>1748  %s1 = shufflevector <2 x i16> %v2, <2 x i16> %v3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>1749  %s2 = shufflevector <2 x i16> %v4, <2 x i16> %v5, <4 x i32> <i32 0, i32 1, i32 2, i32 3>1750  %s3 = shufflevector <4 x i16> %s0, <4 x i16> %s1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>1751  %s4 = shufflevector <2 x i16> %v6, <2 x i16> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>1752  %s5 = shufflevector <4 x i16> %s2, <4 x i16> %s4, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 poison, i32 poison>1753  %interleaved.vec = shufflevector <8 x i16> %s3, <8 x i16> %s5, <14 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13>1754  tail call void @llvm.vp.store.v14i16.p0(<14 x i16> %interleaved.vec, ptr %ptr, <14 x i1> %interleaved.mask, i32 14)1755  ret void1756}1757 1758define void @vpstore_factor8(ptr %ptr, <2 x i16> %v0, <2 x i16> %v1, <2 x i16> %v2, <2 x i16> %v3, <2 x i16> %v4, <2 x i16> %v5, <2 x i16> %v6, <2 x i16> %v7) {1759; CHECK-LABEL: vpstore_factor8:1760; CHECK:       # %bb.0:1761; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma1762; CHECK-NEXT:    vsseg8e16.v v8, (a0)1763; CHECK-NEXT:    ret1764  %s0 = shufflevector <2 x i16> %v0, <2 x i16> %v1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>1765  %s1 = shufflevector <2 x i16> %v2, <2 x i16> %v3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>1766  %s2 = shufflevector <2 x i16> %v4, <2 x i16> %v5, <4 x i32> <i32 0, i32 1, i32 2, i32 3>1767  %s3 = shufflevector <4 x i16> %s0, <4 x i16> %s1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>1768  %s4 = shufflevector <2 x i16> %v6, <2 x i16> %v7, <4 x i32> <i32 0, i32 1, i32 2, i32 3>1769  %s5 = shufflevector <4 x i16> %s2, <4 x i16> %s4, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>1770  %interleaved.vec = shufflevector <8 x i16> %s3, <8 x i16> %s5, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>1771  tail call void @llvm.vp.store.v16i16.p0(<16 x i16> %interleaved.vec, ptr %ptr, <16 x i1> splat (i1 true), i32 16)1772  ret void1773}1774 1775define <4 x i32> @load_factor2_one_active(ptr %ptr) {1776; CHECK-LABEL: load_factor2_one_active:1777; CHECK:       # %bb.0:1778; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma1779; CHECK-NEXT:    vlseg2e32.v v8, (a0)1780; CHECK-NEXT:    ret1781  %interleaved.vec = load <8 x i32>, ptr %ptr1782  %v0 = shufflevector <8 x i32> %interleaved.vec, <8 x i32> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>1783  ret <4 x i32> %v01784}1785 1786 1787define <4 x i32> @load_factor3_one_active(ptr %ptr) {1788; CHECK-LABEL: load_factor3_one_active:1789; CHECK:       # %bb.0:1790; CHECK-NEXT:    li a1, 121791; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma1792; CHECK-NEXT:    vlse32.v v8, (a0), a11793; CHECK-NEXT:    ret1794  %interleaved.vec = load <12 x i32>, ptr %ptr1795  %v0 = shufflevector <12 x i32> %interleaved.vec, <12 x i32> poison, <4 x i32> <i32 0, i32 3, i32 6, i32 9>1796  ret <4 x i32> %v01797}1798 1799define <4 x i32> @load_factor4_one_active(ptr %ptr) {1800; CHECK-LABEL: load_factor4_one_active:1801; CHECK:       # %bb.0:1802; CHECK-NEXT:    li a1, 161803; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma1804; CHECK-NEXT:    vlse32.v v8, (a0), a11805; CHECK-NEXT:    ret1806  %interleaved.vec = load <16 x i32>, ptr %ptr1807  %v0 = shufflevector <16 x i32> %interleaved.vec, <16 x i32> poison, <4 x i32> <i32 0, i32 4, i32 8, i32 12>1808  ret <4 x i32> %v01809}1810 1811define <4 x i32> @load_factor5_one_active(ptr %ptr) {1812; CHECK-LABEL: load_factor5_one_active:1813; CHECK:       # %bb.0:1814; CHECK-NEXT:    li a1, 201815; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma1816; CHECK-NEXT:    vlse32.v v8, (a0), a11817; CHECK-NEXT:    ret1818  %interleaved.vec = load <20 x i32>, ptr %ptr1819  %v0 = shufflevector <20 x i32> %interleaved.vec, <20 x i32> poison, <4 x i32> <i32 0, i32 5, i32 10, i32 15>1820  ret <4 x i32> %v01821}1822 1823define <2 x i16> @load_factor6_one_active(ptr %ptr) {1824; CHECK-LABEL: load_factor6_one_active:1825; CHECK:       # %bb.0:1826; CHECK-NEXT:    addi a0, a0, 101827; CHECK-NEXT:    li a1, 121828; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma1829; CHECK-NEXT:    vlse16.v v8, (a0), a11830; CHECK-NEXT:    ret1831  %interleaved.vec = load <12 x i16>, ptr %ptr1832  %v0 = shufflevector <12 x i16> %interleaved.vec, <12 x i16> poison, <2 x i32> <i32 5, i32 11>1833  ret <2 x i16> %v01834}1835 1836define <4 x i8> @load_factor7_one_active(ptr %ptr) vscale_range(8,1024) {1837; CHECK-LABEL: load_factor7_one_active:1838; CHECK:       # %bb.0:1839; CHECK-NEXT:    addi a0, a0, 11840; CHECK-NEXT:    li a1, 71841; CHECK-NEXT:    vsetivli zero, 4, e8, mf8, ta, ma1842; CHECK-NEXT:    vlse8.v v8, (a0), a11843; CHECK-NEXT:    ret1844  %interleaved.vec = load <32 x i8>, ptr %ptr1845  %v0 = shufflevector <32 x i8> %interleaved.vec, <32 x i8> poison, <4 x i32> <i32 1, i32 8, i32 15, i32 22>1846  ret <4 x i8> %v01847}1848 1849define <4 x i8> @load_factor8_one_active(ptr %ptr) vscale_range(8,1024) {1850; CHECK-LABEL: load_factor8_one_active:1851; CHECK:       # %bb.0:1852; CHECK-NEXT:    li a1, 81853; CHECK-NEXT:    vsetivli zero, 4, e8, mf8, ta, ma1854; CHECK-NEXT:    vlse8.v v8, (a0), a11855; CHECK-NEXT:    ret1856  %interleaved.vec = load <32 x i8>, ptr %ptr1857  %v0 = shufflevector <32 x i8> %interleaved.vec, <32 x i8> poison, <4 x i32> <i32 0, i32 8, i32 16, i32 24>1858  ret <4 x i8> %v01859}1860 1861define <4 x ptr> @load_factor3_one_active_ptr(ptr %ptr) {1862; RV32-LABEL: load_factor3_one_active_ptr:1863; RV32:       # %bb.0:1864; RV32-NEXT:    li a1, 121865; RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, ma1866; RV32-NEXT:    vlse32.v v8, (a0), a11867; RV32-NEXT:    ret1868;1869; RV64-LABEL: load_factor3_one_active_ptr:1870; RV64:       # %bb.0:1871; RV64-NEXT:    li a1, 241872; RV64-NEXT:    vsetivli zero, 4, e64, m2, ta, ma1873; RV64-NEXT:    vlse64.v v8, (a0), a11874; RV64-NEXT:    ret1875  %interleaved.vec = load <12 x ptr>, ptr %ptr1876  %v0 = shufflevector <12 x ptr> %interleaved.vec, <12 x ptr> poison, <4 x i32> <i32 0, i32 3, i32 6, i32 9>1877  ret <4 x ptr> %v01878}1879 1880define void @load_factor4_one_active_storeback(ptr %ptr) {1881; CHECK-LABEL: load_factor4_one_active_storeback:1882; CHECK:       # %bb.0:1883; CHECK-NEXT:    li a1, 161884; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma1885; CHECK-NEXT:    vlse32.v v8, (a0), a11886; CHECK-NEXT:    vse32.v v8, (a0)1887; CHECK-NEXT:    ret1888  %interleaved.vec = load <16 x i32>, ptr %ptr1889  %v0 = shufflevector <16 x i32> %interleaved.vec, <16 x i32> poison, <4 x i32> <i32 0, i32 4, i32 8, i32 12>1890  store <4 x i32> %v0, ptr %ptr1891  ret void1892}1893 1894; TODO: This should be a strided load1895define void @load_factor4_one_active_storeback_full(ptr %ptr) {1896; CHECK-LABEL: load_factor4_one_active_storeback_full:1897; CHECK:       # %bb.0:1898; CHECK-NEXT:    vsetivli zero, 16, e32, m4, ta, ma1899; CHECK-NEXT:    vle32.v v8, (a0)1900; CHECK-NEXT:    vsetivli zero, 4, e32, m2, ta, ma1901; CHECK-NEXT:    vslidedown.vi v12, v8, 41902; CHECK-NEXT:    vmv1r.v v13, v81903; CHECK-NEXT:    vmv1r.v v14, v121904; CHECK-NEXT:    vsetivli zero, 4, e32, m4, ta, ma1905; CHECK-NEXT:    vslidedown.vi v16, v8, 81906; CHECK-NEXT:    vmv1r.v v15, v161907; CHECK-NEXT:    vslidedown.vi v16, v8, 121908; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma1909; CHECK-NEXT:    vsseg4e32.v v13, (a0)1910; CHECK-NEXT:    ret1911  %interleaved.vec = load <16 x i32>, ptr %ptr1912  %v0 = shufflevector <16 x i32> %interleaved.vec, <16 x i32> poison, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>1913  store <16 x i32> %v0, ptr %ptr1914  ret void1915}1916 1917define <4 x i32> @vp_load_factor3_one_active(ptr %ptr) {1918; CHECK-LABEL: vp_load_factor3_one_active:1919; CHECK:       # %bb.0:1920; CHECK-NEXT:    li a1, 121921; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma1922; CHECK-NEXT:    vlse32.v v8, (a0), a11923; CHECK-NEXT:    ret1924  %interleaved.vec = tail call <12 x i32> @llvm.vp.load.v12i32.p0(ptr %ptr, <12 x i1>  splat (i1 true), i32 12)1925  %v0 = shufflevector <12 x i32> %interleaved.vec, <12 x i32> poison, <4 x i32> <i32 0, i32 3, i32 6, i32 9>1926  ret <4 x i32> %v01927}1928 1929define <4 x i32> @vp_load_factor5_one_active(ptr %ptr) {1930; CHECK-LABEL: vp_load_factor5_one_active:1931; CHECK:       # %bb.0:1932; CHECK-NEXT:    li a1, 201933; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma1934; CHECK-NEXT:    vlse32.v v8, (a0), a11935; CHECK-NEXT:    ret1936 %interleaved.vec = tail call <20 x i32> @llvm.vp.load.v20i32.p0(ptr %ptr, <20 x i1>  splat (i1 true), i32 20)1937  %v0 = shufflevector <20 x i32> %interleaved.vec, <20 x i32> poison, <4 x i32> <i32 0, i32 5, i32 10, i32 15>1938  ret <4 x i32> %v01939}1940 1941define void @store_factor4_one_active(ptr %ptr, <4 x i32> %v) {1942; CHECK-LABEL: store_factor4_one_active:1943; CHECK:       # %bb.0:1944; CHECK-NEXT:    li a1, 161945; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma1946; CHECK-NEXT:    vsse32.v v8, (a0), a11947; CHECK-NEXT:    ret1948  %v0 = shufflevector <4 x i32> %v, <4 x i32> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 1, i32 poison, i32 poison, i32 poison, i32 2, i32 poison, i32 poison, i32 poison, i32 3,  i32 poison, i32 poison, i32 poison>1949  store <16 x i32> %v0, ptr %ptr1950  ret void1951}1952 1953define void @vpstore_factor4_one_active(ptr %ptr, <4 x i32> %v) {1954; CHECK-LABEL: vpstore_factor4_one_active:1955; CHECK:       # %bb.0:1956; CHECK-NEXT:    li a1, 161957; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma1958; CHECK-NEXT:    vsse32.v v8, (a0), a11959; CHECK-NEXT:    ret1960  %v0 = shufflevector <4 x i32> %v, <4 x i32> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 1, i32 poison, i32 poison, i32 poison, i32 2, i32 poison, i32 poison, i32 poison, i32 3,  i32 poison, i32 poison, i32 poison>1961  tail call void @llvm.vp.store.v16i32.p0(<16 x i32> %v0, ptr %ptr, <16 x i1> splat (i1 true), i32 16)1962  ret void1963}1964 1965define void @store_factor4_one_active_idx1(ptr %ptr, <4 x i32> %v) {1966; CHECK-LABEL: store_factor4_one_active_idx1:1967; CHECK:       # %bb.0:1968; CHECK-NEXT:    addi a0, a0, 41969; CHECK-NEXT:    li a1, 161970; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma1971; CHECK-NEXT:    vsse32.v v8, (a0), a11972; CHECK-NEXT:    ret1973  %v0 = shufflevector <4 x i32> %v, <4 x i32> poison, <16 x i32> <i32 poison, i32 0, i32 poison, i32 poison, i32 poison, i32 1, i32 poison, i32 poison, i32 poison, i32 2, i32 poison, i32 poison, i32 poison, i32 3,  i32 poison, i32 poison>1974  store <16 x i32> %v0, ptr %ptr1975  ret void1976}1977 1978define void @store_factor4_one_active_fullwidth(ptr %ptr, <16 x i32> %v) {1979; CHECK-LABEL: store_factor4_one_active_fullwidth:1980; CHECK:       # %bb.0:1981; CHECK-NEXT:    li a1, 161982; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma1983; CHECK-NEXT:    vsse32.v v8, (a0), a11984; CHECK-NEXT:    ret1985  %v0 = shufflevector <16 x i32> %v, <16 x i32> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 1, i32 poison, i32 poison, i32 poison, i32 2, i32 poison, i32 poison, i32 poison, i32 3,  i32 poison, i32 poison, i32 poison>1986  store <16 x i32> %v0, ptr %ptr1987  ret void1988}1989 1990define void @store_factor4_one_active_slidedown(ptr %ptr, <4 x i32> %v) {1991; CHECK-LABEL: store_factor4_one_active_slidedown:1992; CHECK:       # %bb.0:1993; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma1994; CHECK-NEXT:    vslidedown.vi v8, v8, 11995; CHECK-NEXT:    li a1, 161996; CHECK-NEXT:    vsse32.v v8, (a0), a11997; CHECK-NEXT:    ret1998  %v0 = shufflevector <4 x i32> %v, <4 x i32> poison, <16 x i32> <i32 1, i32 poison, i32 poison, i32 poison, i32 2, i32 poison, i32 poison, i32 poison, i32 3, i32 poison, i32 poison, i32 poison, i32 4,  i32 poison, i32 poison, i32 poison>1999  store <16 x i32> %v0, ptr %ptr2000  ret void2001}2002 2003define void @store_factor4_one_active_ptr(ptr %ptr, <4 x ptr> %v) {2004; RV32-LABEL: store_factor4_one_active_ptr:2005; RV32:       # %bb.0:2006; RV32-NEXT:    li a1, 162007; RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, ma2008; RV32-NEXT:    vsse32.v v8, (a0), a12009; RV32-NEXT:    ret2010;2011; RV64-LABEL: store_factor4_one_active_ptr:2012; RV64:       # %bb.0:2013; RV64-NEXT:    li a1, 322014; RV64-NEXT:    vsetivli zero, 4, e64, m2, ta, ma2015; RV64-NEXT:    vsse64.v v8, (a0), a12016; RV64-NEXT:    ret2017  %v0 = shufflevector <4 x ptr> %v, <4 x ptr> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 1, i32 poison, i32 poison, i32 poison, i32 2, i32 poison, i32 poison, i32 poison, i32 3,  i32 poison, i32 poison, i32 poison>2018  store <16 x ptr> %v0, ptr %ptr2019  ret void2020}2021 2022; Negative tests2023 2024define {<4 x i32>, <4 x i32>, <4 x i32>} @invalid_vp_mask(ptr %ptr) {2025; RV32-LABEL: invalid_vp_mask:2026; RV32:       # %bb.0:2027; RV32-NEXT:    li a1, 732028; RV32-NEXT:    vsetivli zero, 1, e8, m1, ta, ma2029; RV32-NEXT:    vmv.s.x v11, a12030; RV32-NEXT:    lui a1, 12031; RV32-NEXT:    vmv.v.i v10, 82032; RV32-NEXT:    addi a1, a1, -432033; RV32-NEXT:    vsetvli zero, zero, e16, m2, ta, ma2034; RV32-NEXT:    vmv.s.x v0, a12035; RV32-NEXT:    li a1, 1462036; RV32-NEXT:    vsetivli zero, 12, e32, m4, ta, ma2037; RV32-NEXT:    vle32.v v12, (a0), v0.t2038; RV32-NEXT:    li a0, 362039; RV32-NEXT:    vmv.s.x v20, a12040; RV32-NEXT:    lui a1, %hi(.LCPI65_0)2041; RV32-NEXT:    addi a1, a1, %lo(.LCPI65_0)2042; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma2043; RV32-NEXT:    vle16.v v21, (a1)2044; RV32-NEXT:    vcompress.vm v8, v12, v112045; RV32-NEXT:    vsetivli zero, 8, e32, m4, ta, ma2046; RV32-NEXT:    vslidedown.vi v16, v12, 82047; RV32-NEXT:    vmv1r.v v0, v102048; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, mu2049; RV32-NEXT:    vrgather.vi v8, v16, 1, v0.t2050; RV32-NEXT:    vcompress.vm v14, v12, v202051; RV32-NEXT:    vrgather.vi v14, v16, 2, v0.t2052; RV32-NEXT:    vmv.s.x v0, a02053; RV32-NEXT:    vmerge.vvm v12, v16, v12, v02054; RV32-NEXT:    vrgatherei16.vv v10, v12, v212055; RV32-NEXT:    vmv1r.v v9, v142056; RV32-NEXT:    ret2057;2058; RV64-LABEL: invalid_vp_mask:2059; RV64:       # %bb.0:2060; RV64-NEXT:    li a1, 732061; RV64-NEXT:    vsetivli zero, 1, e8, m1, ta, ma2062; RV64-NEXT:    vmv.s.x v11, a12063; RV64-NEXT:    li a1, 1462064; RV64-NEXT:    vmv.s.x v20, a12065; RV64-NEXT:    lui a1, 12066; RV64-NEXT:    vmv.v.i v10, 82067; RV64-NEXT:    addi a1, a1, -432068; RV64-NEXT:    vsetvli zero, zero, e16, m2, ta, ma2069; RV64-NEXT:    vmv.s.x v0, a12070; RV64-NEXT:    li a1, 362071; RV64-NEXT:    vsetivli zero, 12, e32, m4, ta, ma2072; RV64-NEXT:    vle32.v v12, (a0), v0.t2073; RV64-NEXT:    li a0, 32074; RV64-NEXT:    slli a0, a0, 322075; RV64-NEXT:    addi a0, a0, 52076; RV64-NEXT:    slli a0, a0, 162077; RV64-NEXT:    vsetivli zero, 8, e32, m2, ta, ma2078; RV64-NEXT:    vcompress.vm v8, v12, v112079; RV64-NEXT:    vsetivli zero, 8, e32, m4, ta, ma2080; RV64-NEXT:    vslidedown.vi v16, v12, 82081; RV64-NEXT:    vmv1r.v v0, v102082; RV64-NEXT:    vsetivli zero, 8, e32, m2, ta, mu2083; RV64-NEXT:    vrgather.vi v8, v16, 1, v0.t2084; RV64-NEXT:    vcompress.vm v14, v12, v202085; RV64-NEXT:    vrgather.vi v14, v16, 2, v0.t2086; RV64-NEXT:    vmv.s.x v0, a12087; RV64-NEXT:    addi a0, a0, 22088; RV64-NEXT:    vmerge.vvm v12, v16, v12, v02089; RV64-NEXT:    vsetivli zero, 2, e64, m1, ta, ma2090; RV64-NEXT:    vmv.v.x v9, a02091; RV64-NEXT:    vsetivli zero, 8, e32, m2, ta, ma2092; RV64-NEXT:    vrgatherei16.vv v10, v12, v92093; RV64-NEXT:    vmv1r.v v9, v142094; RV64-NEXT:    ret2095  %interleaved.vec = tail call <12 x i32> @llvm.vp.load.v12i32.p0(ptr %ptr, <12 x i1> <i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>, i32 12)2096  %v0 = shufflevector <12 x i32> %interleaved.vec, <12 x i32> poison, <4 x i32> <i32 0, i32 3, i32 6, i32 9>2097  %v1 = shufflevector <12 x i32> %interleaved.vec, <12 x i32> poison, <4 x i32> <i32 1, i32 4, i32 7, i32 10>2098  %v2 = shufflevector <12 x i32> %interleaved.vec, <12 x i32> poison, <4 x i32> <i32 2, i32 5, i32 8, i32 11>2099  %res0 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>} poison, <4 x i32> %v0, 02100  %res1 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>} %res0, <4 x i32> %v1, 12101  %res2 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>} %res1, <4 x i32> %v2, 22102  ret {<4 x i32>, <4 x i32>, <4 x i32>} %res22103}2104 2105define {<4 x i32>, <4 x i32>, <4 x i32>} @invalid_vp_evl(ptr %ptr) {2106; RV32-LABEL: invalid_vp_evl:2107; RV32:       # %bb.0:2108; RV32-NEXT:    vsetivli zero, 10, e32, m4, ta, ma2109; RV32-NEXT:    vle32.v v12, (a0)2110; RV32-NEXT:    li a0, 732111; RV32-NEXT:    vsetivli zero, 1, e8, mf8, ta, ma2112; RV32-NEXT:    vmv.v.i v0, 82113; RV32-NEXT:    vmv.s.x v10, a02114; RV32-NEXT:    li a0, 1462115; RV32-NEXT:    vmv.s.x v11, a02116; RV32-NEXT:    lui a0, %hi(.LCPI66_0)2117; RV32-NEXT:    addi a0, a0, %lo(.LCPI66_0)2118; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma2119; RV32-NEXT:    vle16.v v20, (a0)2120; RV32-NEXT:    li a0, 362121; RV32-NEXT:    vcompress.vm v8, v12, v102122; RV32-NEXT:    vsetivli zero, 8, e32, m4, ta, ma2123; RV32-NEXT:    vslidedown.vi v16, v12, 82124; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, mu2125; RV32-NEXT:    vrgather.vi v8, v16, 1, v0.t2126; RV32-NEXT:    vcompress.vm v14, v12, v112127; RV32-NEXT:    vrgather.vi v14, v16, 2, v0.t2128; RV32-NEXT:    vmv.s.x v0, a02129; RV32-NEXT:    vmerge.vvm v12, v16, v12, v02130; RV32-NEXT:    vrgatherei16.vv v10, v12, v202131; RV32-NEXT:    vmv1r.v v9, v142132; RV32-NEXT:    ret2133;2134; RV64-LABEL: invalid_vp_evl:2135; RV64:       # %bb.0:2136; RV64-NEXT:    vsetivli zero, 10, e32, m4, ta, ma2137; RV64-NEXT:    vle32.v v12, (a0)2138; RV64-NEXT:    li a0, 732139; RV64-NEXT:    vsetivli zero, 1, e8, mf8, ta, ma2140; RV64-NEXT:    vmv.v.i v0, 82141; RV64-NEXT:    vmv.s.x v10, a02142; RV64-NEXT:    li a0, 1462143; RV64-NEXT:    vmv.s.x v11, a02144; RV64-NEXT:    li a0, 362145; RV64-NEXT:    vsetivli zero, 8, e32, m2, ta, ma2146; RV64-NEXT:    vcompress.vm v8, v12, v102147; RV64-NEXT:    vsetivli zero, 8, e32, m4, ta, ma2148; RV64-NEXT:    vslidedown.vi v16, v12, 82149; RV64-NEXT:    vsetivli zero, 8, e32, m2, ta, mu2150; RV64-NEXT:    vrgather.vi v8, v16, 1, v0.t2151; RV64-NEXT:    vcompress.vm v14, v12, v112152; RV64-NEXT:    vrgather.vi v14, v16, 2, v0.t2153; RV64-NEXT:    vmv.s.x v0, a02154; RV64-NEXT:    li a0, 32155; RV64-NEXT:    slli a0, a0, 322156; RV64-NEXT:    addi a0, a0, 52157; RV64-NEXT:    slli a0, a0, 162158; RV64-NEXT:    addi a0, a0, 22159; RV64-NEXT:    vmerge.vvm v12, v16, v12, v02160; RV64-NEXT:    vsetivli zero, 2, e64, m1, ta, ma2161; RV64-NEXT:    vmv.v.x v9, a02162; RV64-NEXT:    vsetivli zero, 8, e32, m2, ta, ma2163; RV64-NEXT:    vrgatherei16.vv v10, v12, v92164; RV64-NEXT:    vmv1r.v v9, v142165; RV64-NEXT:    ret2166  %interleaved.vec = tail call <12 x i32> @llvm.vp.load.v12i32.p0(ptr %ptr, <12 x i1> splat (i1 true), i32 10)2167  %v0 = shufflevector <12 x i32> %interleaved.vec, <12 x i32> poison, <4 x i32> <i32 0, i32 3, i32 6, i32 9>2168  %v1 = shufflevector <12 x i32> %interleaved.vec, <12 x i32> poison, <4 x i32> <i32 1, i32 4, i32 7, i32 10>2169  %v2 = shufflevector <12 x i32> %interleaved.vec, <12 x i32> poison, <4 x i32> <i32 2, i32 5, i32 8, i32 11>2170  %res0 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>} poison, <4 x i32> %v0, 02171  %res1 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>} %res0, <4 x i32> %v1, 12172  %res2 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>} %res1, <4 x i32> %v2, 22173  ret {<4 x i32>, <4 x i32>, <4 x i32>} %res22174}2175 2176define {<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>} @maskedload_factor5(ptr %ptr) {2177; CHECK-LABEL: maskedload_factor5:2178; CHECK:       # %bb.0:2179; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma2180; CHECK-NEXT:    vlseg5e32.v v8, (a0)2181; CHECK-NEXT:    ret2182  %interleaved.vec = tail call <20 x i32> @llvm.masked.load(ptr %ptr, i32 4, <20 x i1> splat (i1 true), <20 x i32> poison)2183  %v0 = shufflevector <20 x i32> %interleaved.vec, <20 x i32> poison, <4 x i32> <i32 0, i32 5, i32 10, i32 15>2184  %v1 = shufflevector <20 x i32> %interleaved.vec, <20 x i32> poison, <4 x i32> <i32 1, i32 6, i32 11, i32 16>2185  %v2 = shufflevector <20 x i32> %interleaved.vec, <20 x i32> poison, <4 x i32> <i32 2, i32 7, i32 12, i32 17>2186  %v3 = shufflevector <20 x i32> %interleaved.vec, <20 x i32> poison, <4 x i32> <i32 3, i32 8, i32 13, i32 18>2187  %v4 = shufflevector <20 x i32> %interleaved.vec, <20 x i32> poison, <4 x i32> <i32 4, i32 9, i32 14, i32 19>2188  %res0 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>} poison, <4 x i32> %v0, 02189  %res1 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>} %res0, <4 x i32> %v1, 12190  %res2 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>} %res1, <4 x i32> %v2, 22191  %res3 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>} %res2, <4 x i32> %v3, 32192  %res4 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>} %res3, <4 x i32> %v4, 42193  ret {<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>} %res42194}2195 2196define void @maskedstore_factor2(ptr %ptr, <4 x i32> %v0, <4 x i32> %v1) {2197; CHECK-LABEL: maskedstore_factor2:2198; CHECK:       # %bb.0:2199; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma2200; CHECK-NEXT:    vsseg2e32.v v8, (a0)2201; CHECK-NEXT:    ret2202  %interleaved.vec = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>2203  tail call void @llvm.masked.store(<8 x i32> %interleaved.vec, ptr %ptr, i32 4, <8 x i1> splat (i1 true))2204  ret void2205}2206 2207; mask = all ones, skip the last field.2208define void @maskedstore_factor3_gap(ptr %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {2209; CHECK-LABEL: maskedstore_factor3_gap:2210; CHECK:       # %bb.0:2211; CHECK-NEXT:    li a1, 122212; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma2213; CHECK-NEXT:    vssseg2e32.v v8, (a0), a12214; CHECK-NEXT:    ret2215  %s0 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>2216  %s1 = shufflevector <4 x i32> %v2, <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>2217  %interleaved.vec = shufflevector <8 x i32> %s0, <8 x i32> %s1, <12 x i32> <i32 0, i32 4, i32 8, i32 1, i32 5, i32 9, i32 2, i32 6, i32 10, i32 3, i32 7, i32 11>2218  tail call void @llvm.masked.store(<12 x i32> %interleaved.vec, ptr %ptr, i32 4, <12 x i1> <i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0>)2219  ret void2220}2221 2222; mask = 1010, skip the last two fields.2223define void @maskedstore_factor4_gap_with_mask(ptr %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3) {2224; CHECK-LABEL: maskedstore_factor4_gap_with_mask:2225; CHECK:       # %bb.0:2226; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma2227; CHECK-NEXT:    vmv.v.i v0, 52228; CHECK-NEXT:    li a1, 162229; CHECK-NEXT:    vssseg2e32.v v8, (a0), a1, v0.t2230; CHECK-NEXT:    ret2231  %s0 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>2232  %s1 = shufflevector <4 x i32> %v2, <4 x i32> %v3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>2233  %interleaved.vec = shufflevector <8 x i32> %s0, <8 x i32> %s1, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 1, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15>2234  tail call void @llvm.masked.store(<16 x i32> %interleaved.vec, ptr %ptr, i32 4, <16 x i1> <i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0>)2235  ret void2236}2237 2238; mask = %m, skip the last two fields.2239define void @maskedstore_factor4_gap_by_intrinsic_with_mask(ptr %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3, <4 x i1> %m) {2240; CHECK-LABEL: maskedstore_factor4_gap_by_intrinsic_with_mask:2241; CHECK:       # %bb.0:2242; CHECK-NEXT:    li a1, 162243; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma2244; CHECK-NEXT:    vssseg2e32.v v8, (a0), a1, v0.t2245; CHECK-NEXT:    ret2246  %s0 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>2247  %s1 = shufflevector <4 x i32> %v2, <4 x i32> %v3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>2248  %interleaved.vec = shufflevector <8 x i32> %s0, <8 x i32> %s1, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 1, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15>2249  %interleaved.mask = call <16 x i1> @llvm.vector.interleave4(<4 x i1> %m, <4 x i1> %m, <4 x i1> splat (i1 false), <4 x i1> splat (i1 false))2250  tail call void @llvm.masked.store(<16 x i32> %interleaved.vec, ptr %ptr, i32 4, <16 x i1> %interleaved.mask)2251  ret void2252}2253 2254define {<4 x i32>, <4 x i32>, <4 x i32>} @maskedload_factor3_mask(ptr %ptr) {2255; CHECK-LABEL: maskedload_factor3_mask:2256; CHECK:       # %bb.0:2257; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma2258; CHECK-NEXT:    vmv.v.i v0, 52259; CHECK-NEXT:    vlseg3e32.v v8, (a0), v0.t2260; CHECK-NEXT:    ret2261  %interleaved.vec = tail call <12 x i32> @llvm.masked.load.v12i32.p0(ptr %ptr, i32 4, <12 x i1> <i1 1,i1 1,i1 1,i1 0,i1 0,i1 0,i1 1,i1 1,i1 1,i1 0,i1 0,i1 0>, <12 x i32> poison)2262  ; mask = 10102263  %v0 = shufflevector <12 x i32> %interleaved.vec, <12 x i32> poison, <4 x i32> <i32 0, i32 3, i32 6, i32 9>2264  %v1 = shufflevector <12 x i32> %interleaved.vec, <12 x i32> poison, <4 x i32> <i32 1, i32 4, i32 7, i32 10>2265  %v2 = shufflevector <12 x i32> %interleaved.vec, <12 x i32> poison, <4 x i32> <i32 2, i32 5, i32 8, i32 11>2266  %res0 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>} poison, <4 x i32> %v0, 02267  %res1 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>} %res0, <4 x i32> %v1, 12268  %res2 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>} %res1, <4 x i32> %v2, 22269  ret {<4 x i32>, <4 x i32>, <4 x i32>} %res22270}2271 2272define {<4 x i32>, <4 x i32>} @maskedload_factor3_skip_field(ptr %ptr) {2273; CHECK-LABEL: maskedload_factor3_skip_field:2274; CHECK:       # %bb.0:2275; CHECK-NEXT:    li a1, 122276; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma2277; CHECK-NEXT:    vlsseg2e32.v v8, (a0), a12278; CHECK-NEXT:    ret2279  %interleaved.vec = tail call <12 x i32> @llvm.masked.load.v12i32.p0(ptr %ptr, i32 4, <12 x i1> <i1 1,i1 1,i1 0,i1 1,i1 1,i1 0,i1 1,i1 1,i1 0,i1 1,i1 1,i1 0>, <12 x i32> poison)2280  ; mask = 1111, skip last field2281  %v0 = shufflevector <12 x i32> %interleaved.vec, <12 x i32> poison, <4 x i32> <i32 0, i32 3, i32 6, i32 9>2282  %v1 = shufflevector <12 x i32> %interleaved.vec, <12 x i32> poison, <4 x i32> <i32 1, i32 4, i32 7, i32 10>2283  %res0 = insertvalue {<4 x i32>, <4 x i32>} poison, <4 x i32> %v0, 02284  %res1 = insertvalue {<4 x i32>, <4 x i32>} %res0, <4 x i32> %v1, 12285  ret {<4 x i32>, <4 x i32>} %res12286}2287 2288define {<4 x i32>, <4 x i32>} @maskedload_factor3_mask_skip_field(ptr %ptr) {2289; CHECK-LABEL: maskedload_factor3_mask_skip_field:2290; CHECK:       # %bb.0:2291; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma2292; CHECK-NEXT:    vmv.v.i v0, 52293; CHECK-NEXT:    li a1, 122294; CHECK-NEXT:    vlsseg2e32.v v8, (a0), a1, v0.t2295; CHECK-NEXT:    ret2296  %interleaved.vec = tail call <12 x i32> @llvm.masked.load.v12i32.p0(ptr %ptr, i32 4, <12 x i1> <i1 1,i1 1,i1 0,i1 0,i1 0,i1 0,i1 1,i1 1,i1 0,i1 0,i1 0,i1 0>, <12 x i32> poison)2297  ; mask = 1010, skip the last field2298  %v0 = shufflevector <12 x i32> %interleaved.vec, <12 x i32> poison, <4 x i32> <i32 0, i32 3, i32 6, i32 9>2299  %v1 = shufflevector <12 x i32> %interleaved.vec, <12 x i32> poison, <4 x i32> <i32 1, i32 4, i32 7, i32 10>2300  %res0 = insertvalue {<4 x i32>, <4 x i32>} poison, <4 x i32> %v0, 02301  %res1 = insertvalue {<4 x i32>, <4 x i32>} %res0, <4 x i32> %v1, 12302  ret {<4 x i32>, <4 x i32>} %res12303}2304 2305define {<4 x i32>, <4 x i32>} @maskedload_factor3_combined_mask_skip_field(ptr %ptr, <4 x i1> %mask) {2306; CHECK-LABEL: maskedload_factor3_combined_mask_skip_field:2307; CHECK:       # %bb.0:2308; CHECK-NEXT:    li a1, 122309; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma2310; CHECK-NEXT:    vlsseg2e32.v v8, (a0), a1, v0.t2311; CHECK-NEXT:    ret2312  %interleaved.mask = shufflevector <4 x i1> %mask, <4 x i1> poison, <12 x i32> <i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 2, i32 2, i32 2, i32 3, i32 3, i32 3>2313  %combined = and <12 x i1> %interleaved.mask, <i1 true, i1 true, i1 false, i1 true, i1 true, i1 false, i1 true, i1 true, i1 false, i1 true, i1 true, i1 false>2314  %interleaved.vec = tail call <12 x i32> @llvm.masked.load.v12i32.p0(ptr %ptr, i32 4, <12 x i1> %combined, <12 x i32> poison)2315  ; mask = %mask, skip the last field2316  %v0 = shufflevector <12 x i32> %interleaved.vec, <12 x i32> poison, <4 x i32> <i32 0, i32 3, i32 6, i32 9>2317  %v1 = shufflevector <12 x i32> %interleaved.vec, <12 x i32> poison, <4 x i32> <i32 1, i32 4, i32 7, i32 10>2318  %res0 = insertvalue {<4 x i32>, <4 x i32>} poison, <4 x i32> %v0, 02319  %res1 = insertvalue {<4 x i32>, <4 x i32>} %res0, <4 x i32> %v1, 12320  ret {<4 x i32>, <4 x i32>} %res12321}2322 2323define {<4 x i32>, <4 x i32>} @maskedload_factor4_combined_mask_multi_skip_fields(ptr %ptr, <4 x i1> %mask) {2324; CHECK-LABEL: maskedload_factor4_combined_mask_multi_skip_fields:2325; CHECK:       # %bb.0:2326; CHECK-NEXT:    li a1, 162327; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma2328; CHECK-NEXT:    vlsseg2e32.v v8, (a0), a1, v0.t2329; CHECK-NEXT:    ret2330  %interleaved.mask = shufflevector <4 x i1> %mask, <4 x i1> poison, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1, i32 2, i32 2, i32 2, i32 2, i32 3, i32 3, i32 3, i32 3>2331  %combined = and <16 x i1> %interleaved.mask, <i1 true, i1 true, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false>2332  %combined1 = and <16 x i1> %combined, <i1 true, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false, i1 true>2333  %interleaved.vec = tail call <16 x i32> @llvm.masked.load.v16i32.p0(ptr %ptr, i32 4, <16 x i1> %combined1, <16 x i32> poison)2334  ; mask = %mask, skip the last 2 fields2335  %v0 = shufflevector <16 x i32> %interleaved.vec, <16 x i32> poison, <4 x i32> <i32 0, i32 4, i32 8, i32 12>2336  %v1 = shufflevector <16 x i32> %interleaved.vec, <16 x i32> poison, <4 x i32> <i32 1, i32 5, i32 9, i32 13>2337  %res0 = insertvalue {<4 x i32>, <4 x i32>} poison, <4 x i32> %v0, 02338  %res1 = insertvalue {<4 x i32>, <4 x i32>} %res0, <4 x i32> %v1, 12339  ret {<4 x i32>, <4 x i32>} %res12340}2341 2342define {<4 x i32>, <4 x i32>} @maskedload_factor4_combined_mask_multi_skip_fields_and_masks(ptr %ptr, <4 x i1> %mask, <4 x i1> %mask2) {2343; CHECK-LABEL: maskedload_factor4_combined_mask_multi_skip_fields_and_masks:2344; CHECK:       # %bb.0:2345; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma2346; CHECK-NEXT:    vmand.mm v0, v0, v82347; CHECK-NEXT:    li a1, 162348; CHECK-NEXT:    vlsseg2e32.v v8, (a0), a1, v0.t2349; CHECK-NEXT:    ret2350  %interleaved.mask = shufflevector <4 x i1> %mask, <4 x i1> poison, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1, i32 2, i32 2, i32 2, i32 2, i32 3, i32 3, i32 3, i32 3>2351  %combined = and <16 x i1> %interleaved.mask, <i1 true, i1 true, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false>2352 2353  %interleaved.mask2 = shufflevector <4 x i1> %mask2, <4 x i1> poison, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1, i32 2, i32 2, i32 2, i32 2, i32 3, i32 3, i32 3, i32 3>2354  %combined1 = and <16 x i1> %interleaved.mask2, <i1 true, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false, i1 true>2355 2356  %combined2 = and <16 x i1> %combined, %combined12357  %interleaved.vec = tail call <16 x i32> @llvm.masked.load.v16i32.p0(ptr %ptr, i32 4, <16 x i1> %combined2, <16 x i32> poison)2358  ; mask = %mask & %mask2, skip the last 2 fields2359  %v0 = shufflevector <16 x i32> %interleaved.vec, <16 x i32> poison, <4 x i32> <i32 0, i32 4, i32 8, i32 12>2360  %v1 = shufflevector <16 x i32> %interleaved.vec, <16 x i32> poison, <4 x i32> <i32 1, i32 5, i32 9, i32 13>2361  %res0 = insertvalue {<4 x i32>, <4 x i32>} poison, <4 x i32> %v0, 02362  %res1 = insertvalue {<4 x i32>, <4 x i32>} %res0, <4 x i32> %v1, 12363  ret {<4 x i32>, <4 x i32>} %res12364}2365 2366; We can only skip the last field for now.2367define {<4 x i32>, <4 x i32>, <4 x i32>} @maskedload_factor3_invalid_skip_field(ptr %ptr) {2368; RV32-LABEL: maskedload_factor3_invalid_skip_field:2369; RV32:       # %bb.0:2370; RV32-NEXT:    li a1, 732371; RV32-NEXT:    vsetivli zero, 1, e8, m1, ta, ma2372; RV32-NEXT:    vmv.s.x v11, a12373; RV32-NEXT:    lui a1, 12374; RV32-NEXT:    vmv.v.i v10, 82375; RV32-NEXT:    addi a1, a1, -11712376; RV32-NEXT:    vsetvli zero, zero, e16, m2, ta, ma2377; RV32-NEXT:    vmv.s.x v0, a12378; RV32-NEXT:    li a1, 1462379; RV32-NEXT:    vsetivli zero, 12, e32, m4, ta, ma2380; RV32-NEXT:    vle32.v v12, (a0), v0.t2381; RV32-NEXT:    li a0, 362382; RV32-NEXT:    vmv.s.x v20, a12383; RV32-NEXT:    lui a1, %hi(.LCPI78_0)2384; RV32-NEXT:    addi a1, a1, %lo(.LCPI78_0)2385; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma2386; RV32-NEXT:    vle16.v v21, (a1)2387; RV32-NEXT:    vcompress.vm v8, v12, v112388; RV32-NEXT:    vsetivli zero, 8, e32, m4, ta, ma2389; RV32-NEXT:    vslidedown.vi v16, v12, 82390; RV32-NEXT:    vmv1r.v v0, v102391; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, mu2392; RV32-NEXT:    vrgather.vi v8, v16, 1, v0.t2393; RV32-NEXT:    vcompress.vm v14, v12, v202394; RV32-NEXT:    vrgather.vi v14, v16, 2, v0.t2395; RV32-NEXT:    vmv.s.x v0, a02396; RV32-NEXT:    vmerge.vvm v12, v16, v12, v02397; RV32-NEXT:    vrgatherei16.vv v10, v12, v212398; RV32-NEXT:    vmv1r.v v9, v142399; RV32-NEXT:    ret2400;2401; RV64-LABEL: maskedload_factor3_invalid_skip_field:2402; RV64:       # %bb.0:2403; RV64-NEXT:    li a1, 732404; RV64-NEXT:    vsetivli zero, 1, e8, m1, ta, ma2405; RV64-NEXT:    vmv.s.x v11, a12406; RV64-NEXT:    li a1, 1462407; RV64-NEXT:    vmv.s.x v20, a12408; RV64-NEXT:    lui a1, 12409; RV64-NEXT:    vmv.v.i v10, 82410; RV64-NEXT:    addi a1, a1, -11712411; RV64-NEXT:    vsetvli zero, zero, e16, m2, ta, ma2412; RV64-NEXT:    vmv.s.x v0, a12413; RV64-NEXT:    li a1, 362414; RV64-NEXT:    vsetivli zero, 12, e32, m4, ta, ma2415; RV64-NEXT:    vle32.v v12, (a0), v0.t2416; RV64-NEXT:    li a0, 32417; RV64-NEXT:    slli a0, a0, 322418; RV64-NEXT:    addi a0, a0, 52419; RV64-NEXT:    slli a0, a0, 162420; RV64-NEXT:    vsetivli zero, 8, e32, m2, ta, ma2421; RV64-NEXT:    vcompress.vm v8, v12, v112422; RV64-NEXT:    vsetivli zero, 8, e32, m4, ta, ma2423; RV64-NEXT:    vslidedown.vi v16, v12, 82424; RV64-NEXT:    vmv1r.v v0, v102425; RV64-NEXT:    vsetivli zero, 8, e32, m2, ta, mu2426; RV64-NEXT:    vrgather.vi v8, v16, 1, v0.t2427; RV64-NEXT:    vcompress.vm v14, v12, v202428; RV64-NEXT:    vrgather.vi v14, v16, 2, v0.t2429; RV64-NEXT:    vmv.s.x v0, a12430; RV64-NEXT:    addi a0, a0, 22431; RV64-NEXT:    vmerge.vvm v12, v16, v12, v02432; RV64-NEXT:    vsetivli zero, 2, e64, m1, ta, ma2433; RV64-NEXT:    vmv.v.x v9, a02434; RV64-NEXT:    vsetivli zero, 8, e32, m2, ta, ma2435; RV64-NEXT:    vrgatherei16.vv v10, v12, v92436; RV64-NEXT:    vmv1r.v v9, v142437; RV64-NEXT:    ret2438  %interleaved.vec = tail call <12 x i32> @llvm.masked.load.v12i32.p0(ptr %ptr, i32 4, <12 x i1> <i1 1,i1 0,i1 1,i1 1,i1 0,i1 1,i1 1,i1 0,i1 1,i1 1,i1 0,i1 1>, <12 x i32> poison)2439  %v0 = shufflevector <12 x i32> %interleaved.vec, <12 x i32> poison, <4 x i32> <i32 0, i32 3, i32 6, i32 9>2440  %v1 = shufflevector <12 x i32> %interleaved.vec, <12 x i32> poison, <4 x i32> <i32 1, i32 4, i32 7, i32 10>2441  %v2 = shufflevector <12 x i32> %interleaved.vec, <12 x i32> poison, <4 x i32> <i32 2, i32 5, i32 8, i32 11>2442  %res0 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>} poison, <4 x i32> %v0, 02443  %res1 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>} %res0, <4 x i32> %v1, 12444  %res2 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>} %res1, <4 x i32> %v2, 22445  ret {<4 x i32>, <4 x i32>, <4 x i32>} %res22446}2447 2448define {<4 x i32>, <4 x i32>, <4 x i32>} @maskedload_factor5_skip_fields(ptr %ptr) {2449  ; mask = 1111, skip the last two fields.2450; CHECK-LABEL: maskedload_factor5_skip_fields:2451; CHECK:       # %bb.0:2452; CHECK-NEXT:    li a1, 202453; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma2454; CHECK-NEXT:    vlsseg3e32.v v8, (a0), a12455; CHECK-NEXT:    ret2456  %interleaved.vec = tail call <20 x i32> @llvm.masked.load(ptr %ptr, i32 4, <20 x i1> <i1 1, i1 1, i1 1, i1 0, i1 0, i1 1, i1 1, i1 1, i1 0, i1 0, i1 1, i1 1, i1 1, i1 0, i1 0, i1 1, i1 1, i1 1, i1 0, i1 0>, <20 x i32> poison)2457  %v0 = shufflevector <20 x i32> %interleaved.vec, <20 x i32> poison, <4 x i32> <i32 0, i32 5, i32 10, i32 15>2458  %v1 = shufflevector <20 x i32> %interleaved.vec, <20 x i32> poison, <4 x i32> <i32 1, i32 6, i32 11, i32 16>2459  %v2 = shufflevector <20 x i32> %interleaved.vec, <20 x i32> poison, <4 x i32> <i32 2, i32 7, i32 12, i32 17>2460  %v3 = shufflevector <20 x i32> %interleaved.vec, <20 x i32> poison, <4 x i32> <i32 3, i32 8, i32 13, i32 18>2461  %v4 = shufflevector <20 x i32> %interleaved.vec, <20 x i32> poison, <4 x i32> <i32 4, i32 9, i32 14, i32 19>2462  %res0 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>} poison, <4 x i32> %v0, 02463  %res1 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>} %res0, <4 x i32> %v1, 12464  %res2 = insertvalue {<4 x i32>, <4 x i32>, <4 x i32>} %res1, <4 x i32> %v2, 22465  ret {<4 x i32>, <4 x i32>, <4 x i32>} %res22466}2467 2468