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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v,+f,+d -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV324; RUN: llc -mtriple=riscv64 -mattr=+v,+f,+d -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV646 7define <1 x i64> @llrint_v1i64_v1f32(<1 x float> %x, <1 x i1> %m, i32 zeroext %evl) {8; RV32-LABEL: llrint_v1i64_v1f32:9; RV32: # %bb.0:10; RV32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma11; RV32-NEXT: vfwcvt.x.f.v v9, v8, v0.t12; RV32-NEXT: vmv1r.v v8, v913; RV32-NEXT: ret14;15; RV64-LABEL: llrint_v1i64_v1f32:16; RV64: # %bb.0:17; RV64-NEXT: vsetvli zero, a0, e32, mf2, ta, ma18; RV64-NEXT: vfwcvt.x.f.v v9, v8, v0.t19; RV64-NEXT: vmv1r.v v8, v920; RV64-NEXT: ret21 %a = call <1 x i64> @llvm.vp.llrint.v1i64.v1f32(<1 x float> %x, <1 x i1> %m, i32 %evl)22 ret <1 x i64> %a23}24 25define <2 x i64> @llrint_v2i64_v2f32(<2 x float> %x, <2 x i1> %m, i32 zeroext %evl) {26; RV32-LABEL: llrint_v2i64_v2f32:27; RV32: # %bb.0:28; RV32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma29; RV32-NEXT: vfwcvt.x.f.v v9, v8, v0.t30; RV32-NEXT: vmv1r.v v8, v931; RV32-NEXT: ret32;33; RV64-LABEL: llrint_v2i64_v2f32:34; RV64: # %bb.0:35; RV64-NEXT: vsetvli zero, a0, e32, mf2, ta, ma36; RV64-NEXT: vfwcvt.x.f.v v9, v8, v0.t37; RV64-NEXT: vmv1r.v v8, v938; RV64-NEXT: ret39 %a = call <2 x i64> @llvm.vp.llrint.v2i64.v2f32(<2 x float> %x, <2 x i1> %m, i32 %evl)40 ret <2 x i64> %a41}42 43define <3 x i64> @llrint_v3i64_v3f32(<3 x float> %x, <3 x i1> %m, i32 zeroext %evl) {44; RV32-LABEL: llrint_v3i64_v3f32:45; RV32: # %bb.0:46; RV32-NEXT: vsetvli zero, a0, e32, m1, ta, ma47; RV32-NEXT: vmv1r.v v10, v848; RV32-NEXT: vfwcvt.x.f.v v8, v10, v0.t49; RV32-NEXT: ret50;51; RV64-LABEL: llrint_v3i64_v3f32:52; RV64: # %bb.0:53; RV64-NEXT: vsetvli zero, a0, e32, m1, ta, ma54; RV64-NEXT: vmv1r.v v10, v855; RV64-NEXT: vfwcvt.x.f.v v8, v10, v0.t56; RV64-NEXT: ret57 %a = call <3 x i64> @llvm.vp.llrint.v3i64.v3f32(<3 x float> %x, <3 x i1> %m, i32 %evl)58 ret <3 x i64> %a59}60 61define <4 x i64> @llrint_v4i64_v4f32(<4 x float> %x, <4 x i1> %m, i32 zeroext %evl) {62; RV32-LABEL: llrint_v4i64_v4f32:63; RV32: # %bb.0:64; RV32-NEXT: vsetvli zero, a0, e32, m1, ta, ma65; RV32-NEXT: vmv1r.v v10, v866; RV32-NEXT: vfwcvt.x.f.v v8, v10, v0.t67; RV32-NEXT: ret68;69; RV64-LABEL: llrint_v4i64_v4f32:70; RV64: # %bb.0:71; RV64-NEXT: vsetvli zero, a0, e32, m1, ta, ma72; RV64-NEXT: vmv1r.v v10, v873; RV64-NEXT: vfwcvt.x.f.v v8, v10, v0.t74; RV64-NEXT: ret75 %a = call <4 x i64> @llvm.vp.llrint.v4i64.v4f32(<4 x float> %x, <4 x i1> %m, i32 %evl)76 ret <4 x i64> %a77}78 79define <8 x i64> @llrint_v8i64_v8f32(<8 x float> %x, <8 x i1> %m, i32 zeroext %evl) {80; RV32-LABEL: llrint_v8i64_v8f32:81; RV32: # %bb.0:82; RV32-NEXT: vsetvli zero, a0, e32, m2, ta, ma83; RV32-NEXT: vmv2r.v v12, v884; RV32-NEXT: vfwcvt.x.f.v v8, v12, v0.t85; RV32-NEXT: ret86;87; RV64-LABEL: llrint_v8i64_v8f32:88; RV64: # %bb.0:89; RV64-NEXT: vsetvli zero, a0, e32, m2, ta, ma90; RV64-NEXT: vmv2r.v v12, v891; RV64-NEXT: vfwcvt.x.f.v v8, v12, v0.t92; RV64-NEXT: ret93 %a = call <8 x i64> @llvm.vp.llrint.v8i64.v8f32(<8 x float> %x, <8 x i1> %m, i32 %evl)94 ret <8 x i64> %a95}96 97define <16 x i64> @llrint_v16i64_v16f32(<16 x float> %x, <16 x i1> %m, i32 zeroext %evl) {98; RV32-LABEL: llrint_v16i64_v16f32:99; RV32: # %bb.0:100; RV32-NEXT: vsetvli zero, a0, e32, m4, ta, ma101; RV32-NEXT: vmv4r.v v16, v8102; RV32-NEXT: vfwcvt.x.f.v v8, v16, v0.t103; RV32-NEXT: ret104;105; RV64-LABEL: llrint_v16i64_v16f32:106; RV64: # %bb.0:107; RV64-NEXT: vsetvli zero, a0, e32, m4, ta, ma108; RV64-NEXT: vmv4r.v v16, v8109; RV64-NEXT: vfwcvt.x.f.v v8, v16, v0.t110; RV64-NEXT: ret111 %a = call <16 x i64> @llvm.vp.llrint.v16i64.v16f32(<16 x float> %x, <16 x i1> %m, i32 %evl)112 ret <16 x i64> %a113}114 115define <1 x i64> @llrint_v1i64_v1f64(<1 x double> %x, <1 x i1> %m, i32 zeroext %evl) {116; RV32-LABEL: llrint_v1i64_v1f64:117; RV32: # %bb.0:118; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma119; RV32-NEXT: vfcvt.x.f.v v8, v8, v0.t120; RV32-NEXT: ret121;122; RV64-LABEL: llrint_v1i64_v1f64:123; RV64: # %bb.0:124; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma125; RV64-NEXT: vfcvt.x.f.v v8, v8, v0.t126; RV64-NEXT: ret127 %a = call <1 x i64> @llvm.vp.llrint.v1i64.v1f64(<1 x double> %x, <1 x i1> %m, i32 %evl)128 ret <1 x i64> %a129}130 131define <2 x i64> @llrint_v2i64_v2f64(<2 x double> %x, <2 x i1> %m, i32 zeroext %evl) {132; RV32-LABEL: llrint_v2i64_v2f64:133; RV32: # %bb.0:134; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma135; RV32-NEXT: vfcvt.x.f.v v8, v8, v0.t136; RV32-NEXT: ret137;138; RV64-LABEL: llrint_v2i64_v2f64:139; RV64: # %bb.0:140; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma141; RV64-NEXT: vfcvt.x.f.v v8, v8, v0.t142; RV64-NEXT: ret143 %a = call <2 x i64> @llvm.vp.llrint.v2i64.v2f64(<2 x double> %x, <2 x i1> %m, i32 %evl)144 ret <2 x i64> %a145}146 147define <4 x i64> @llrint_v4i64_v4f64(<4 x double> %x, <4 x i1> %m, i32 zeroext %evl) {148; RV32-LABEL: llrint_v4i64_v4f64:149; RV32: # %bb.0:150; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma151; RV32-NEXT: vfcvt.x.f.v v8, v8, v0.t152; RV32-NEXT: ret153;154; RV64-LABEL: llrint_v4i64_v4f64:155; RV64: # %bb.0:156; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma157; RV64-NEXT: vfcvt.x.f.v v8, v8, v0.t158; RV64-NEXT: ret159 %a = call <4 x i64> @llvm.vp.llrint.v4i64.v4f64(<4 x double> %x, <4 x i1> %m, i32 %evl)160 ret <4 x i64> %a161}162 163define <8 x i64> @llrint_v8i64_v8f64(<8 x double> %x, <8 x i1> %m, i32 zeroext %evl) {164; RV32-LABEL: llrint_v8i64_v8f64:165; RV32: # %bb.0:166; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma167; RV32-NEXT: vfcvt.x.f.v v8, v8, v0.t168; RV32-NEXT: ret169;170; RV64-LABEL: llrint_v8i64_v8f64:171; RV64: # %bb.0:172; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma173; RV64-NEXT: vfcvt.x.f.v v8, v8, v0.t174; RV64-NEXT: ret175 %a = call <8 x i64> @llvm.vp.llrint.v8i64.v8f64(<8 x double> %x, <8 x i1> %m, i32 %evl)176 ret <8 x i64> %a177}178