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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v,+f,+d,+zvfhmin,+zvfbfmin -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s4; RUN: llc -mtriple=riscv64 -mattr=+v,+f,+d,+zvfhmin,+zvfbfmin -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck %s6 7define <1 x i64> @llrint_v1i64_v1f32(<1 x float> %x) {8; CHECK-LABEL: llrint_v1i64_v1f32:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma11; CHECK-NEXT: vfwcvt.x.f.v v9, v812; CHECK-NEXT: vmv1r.v v8, v913; CHECK-NEXT: ret14 %a = call <1 x i64> @llvm.llrint.v1i64.v1f32(<1 x float> %x)15 ret <1 x i64> %a16}17 18define <2 x i64> @llrint_v2i64_v2f32(<2 x float> %x) {19; CHECK-LABEL: llrint_v2i64_v2f32:20; CHECK: # %bb.0:21; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma22; CHECK-NEXT: vfwcvt.x.f.v v9, v823; CHECK-NEXT: vmv1r.v v8, v924; CHECK-NEXT: ret25 %a = call <2 x i64> @llvm.llrint.v2i64.v2f32(<2 x float> %x)26 ret <2 x i64> %a27}28 29define <3 x i64> @llrint_v3i64_v3f32(<3 x float> %x) {30; CHECK-LABEL: llrint_v3i64_v3f32:31; CHECK: # %bb.0:32; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma33; CHECK-NEXT: vmv1r.v v10, v834; CHECK-NEXT: vfwcvt.x.f.v v8, v1035; CHECK-NEXT: ret36 %a = call <3 x i64> @llvm.llrint.v3i64.v3f32(<3 x float> %x)37 ret <3 x i64> %a38}39 40define <4 x i64> @llrint_v4i64_v4f32(<4 x float> %x) {41; CHECK-LABEL: llrint_v4i64_v4f32:42; CHECK: # %bb.0:43; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma44; CHECK-NEXT: vmv1r.v v10, v845; CHECK-NEXT: vfwcvt.x.f.v v8, v1046; CHECK-NEXT: ret47 %a = call <4 x i64> @llvm.llrint.v4i64.v4f32(<4 x float> %x)48 ret <4 x i64> %a49}50 51define <8 x i64> @llrint_v8i64_v8f32(<8 x float> %x) {52; CHECK-LABEL: llrint_v8i64_v8f32:53; CHECK: # %bb.0:54; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma55; CHECK-NEXT: vmv2r.v v12, v856; CHECK-NEXT: vfwcvt.x.f.v v8, v1257; CHECK-NEXT: ret58 %a = call <8 x i64> @llvm.llrint.v8i64.v8f32(<8 x float> %x)59 ret <8 x i64> %a60}61 62define <16 x i64> @llrint_v16i64_v16f32(<16 x float> %x) {63; CHECK-LABEL: llrint_v16i64_v16f32:64; CHECK: # %bb.0:65; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma66; CHECK-NEXT: vmv4r.v v16, v867; CHECK-NEXT: vfwcvt.x.f.v v8, v1668; CHECK-NEXT: ret69 %a = call <16 x i64> @llvm.llrint.v16i64.v16f32(<16 x float> %x)70 ret <16 x i64> %a71}72 73define <1 x i64> @llrint_v1i64_v1f64(<1 x double> %x) {74; CHECK-LABEL: llrint_v1i64_v1f64:75; CHECK: # %bb.0:76; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma77; CHECK-NEXT: vfcvt.x.f.v v8, v878; CHECK-NEXT: ret79 %a = call <1 x i64> @llvm.llrint.v1i64.v1f64(<1 x double> %x)80 ret <1 x i64> %a81}82 83define <2 x i64> @llrint_v2i64_v2f64(<2 x double> %x) {84; CHECK-LABEL: llrint_v2i64_v2f64:85; CHECK: # %bb.0:86; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma87; CHECK-NEXT: vfcvt.x.f.v v8, v888; CHECK-NEXT: ret89 %a = call <2 x i64> @llvm.llrint.v2i64.v2f64(<2 x double> %x)90 ret <2 x i64> %a91}92 93define <4 x i64> @llrint_v4i64_v4f64(<4 x double> %x) {94; CHECK-LABEL: llrint_v4i64_v4f64:95; CHECK: # %bb.0:96; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma97; CHECK-NEXT: vfcvt.x.f.v v8, v898; CHECK-NEXT: ret99 %a = call <4 x i64> @llvm.llrint.v4i64.v4f64(<4 x double> %x)100 ret <4 x i64> %a101}102 103define <8 x i64> @llrint_v8i64_v8f64(<8 x double> %x) {104; CHECK-LABEL: llrint_v8i64_v8f64:105; CHECK: # %bb.0:106; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma107; CHECK-NEXT: vfcvt.x.f.v v8, v8108; CHECK-NEXT: ret109 %a = call <8 x i64> @llvm.llrint.v8i64.v8f64(<8 x double> %x)110 ret <8 x i64> %a111}112 113define <1 x i64> @llrint_v1i64_v1f16(<1 x half> %x) {114; CHECK-LABEL: llrint_v1i64_v1f16:115; CHECK: # %bb.0:116; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma117; CHECK-NEXT: vfwcvt.f.f.v v9, v8118; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma119; CHECK-NEXT: vfwcvt.x.f.v v8, v9120; CHECK-NEXT: ret121 %a = call <1 x i64> @llvm.llrint.v1i64.v1f16(<1 x half> %x)122 ret <1 x i64> %a123}124 125define <2 x i64> @llrint_v2i64_v2f16(<2 x half> %x) {126; CHECK-LABEL: llrint_v2i64_v2f16:127; CHECK: # %bb.0:128; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma129; CHECK-NEXT: vfwcvt.f.f.v v9, v8130; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma131; CHECK-NEXT: vfwcvt.x.f.v v8, v9132; CHECK-NEXT: ret133 %a = call <2 x i64> @llvm.llrint.v2i64.v2f16(<2 x half> %x)134 ret <2 x i64> %a135}136 137define <3 x i64> @llrint_v3i64_v3f16(<3 x half> %x) {138; CHECK-LABEL: llrint_v3i64_v3f16:139; CHECK: # %bb.0:140; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma141; CHECK-NEXT: vfwcvt.f.f.v v10, v8142; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma143; CHECK-NEXT: vfwcvt.x.f.v v8, v10144; CHECK-NEXT: ret145 %a = call <3 x i64> @llvm.llrint.v3i64.v3f16(<3 x half> %x)146 ret <3 x i64> %a147}148 149define <4 x i64> @llrint_v4i64_v4f16(<4 x half> %x) {150; CHECK-LABEL: llrint_v4i64_v4f16:151; CHECK: # %bb.0:152; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma153; CHECK-NEXT: vfwcvt.f.f.v v10, v8154; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma155; CHECK-NEXT: vfwcvt.x.f.v v8, v10156; CHECK-NEXT: ret157 %a = call <4 x i64> @llvm.llrint.v4i64.v4f16(<4 x half> %x)158 ret <4 x i64> %a159}160 161define <8 x i64> @llrint_v8i64_v8f16(<8 x half> %x) {162; CHECK-LABEL: llrint_v8i64_v8f16:163; CHECK: # %bb.0:164; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma165; CHECK-NEXT: vfwcvt.f.f.v v12, v8166; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma167; CHECK-NEXT: vfwcvt.x.f.v v8, v12168; CHECK-NEXT: ret169 %a = call <8 x i64> @llvm.llrint.v8i64.v8f16(<8 x half> %x)170 ret <8 x i64> %a171}172 173define <16 x i64> @llrint_v16i64_v16f16(<16 x half> %x) {174; CHECK-LABEL: llrint_v16i64_v16f16:175; CHECK: # %bb.0:176; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma177; CHECK-NEXT: vfwcvt.f.f.v v16, v8178; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma179; CHECK-NEXT: vfwcvt.x.f.v v8, v16180; CHECK-NEXT: ret181 %a = call <16 x i64> @llvm.llrint.v16i64.v16f16(<16 x half> %x)182 ret <16 x i64> %a183}184 185define <1 x i64> @llrint_v1i64_v1bf16(<1 x bfloat> %x) {186; CHECK-LABEL: llrint_v1i64_v1bf16:187; CHECK: # %bb.0:188; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma189; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8190; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma191; CHECK-NEXT: vfwcvt.x.f.v v8, v9192; CHECK-NEXT: ret193 %a = call <1 x i64> @llvm.llrint.v1i64.v1bf16(<1 x bfloat> %x)194 ret <1 x i64> %a195}196 197define <2 x i64> @llrint_v2i64_v2bf16(<2 x bfloat> %x) {198; CHECK-LABEL: llrint_v2i64_v2bf16:199; CHECK: # %bb.0:200; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma201; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8202; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma203; CHECK-NEXT: vfwcvt.x.f.v v8, v9204; CHECK-NEXT: ret205 %a = call <2 x i64> @llvm.llrint.v2i64.v2bf16(<2 x bfloat> %x)206 ret <2 x i64> %a207}208 209define <3 x i64> @llrint_v3i64_v3bf16(<3 x bfloat> %x) {210; CHECK-LABEL: llrint_v3i64_v3bf16:211; CHECK: # %bb.0:212; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma213; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8214; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma215; CHECK-NEXT: vfwcvt.x.f.v v8, v10216; CHECK-NEXT: ret217 %a = call <3 x i64> @llvm.llrint.v3i64.v3bf16(<3 x bfloat> %x)218 ret <3 x i64> %a219}220 221define <4 x i64> @llrint_v4i64_v4bf16(<4 x bfloat> %x) {222; CHECK-LABEL: llrint_v4i64_v4bf16:223; CHECK: # %bb.0:224; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma225; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8226; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma227; CHECK-NEXT: vfwcvt.x.f.v v8, v10228; CHECK-NEXT: ret229 %a = call <4 x i64> @llvm.llrint.v4i64.v4bf16(<4 x bfloat> %x)230 ret <4 x i64> %a231}232 233define <8 x i64> @llrint_v8i64_v8bf16(<8 x bfloat> %x) {234; CHECK-LABEL: llrint_v8i64_v8bf16:235; CHECK: # %bb.0:236; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma237; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8238; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma239; CHECK-NEXT: vfwcvt.x.f.v v8, v12240; CHECK-NEXT: ret241 %a = call <8 x i64> @llvm.llrint.v8i64.v8bf16(<8 x bfloat> %x)242 ret <8 x i64> %a243}244 245define <16 x i64> @llrint_v16i64_v16bf16(<16 x bfloat> %x) {246; CHECK-LABEL: llrint_v16i64_v16bf16:247; CHECK: # %bb.0:248; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma249; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8250; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma251; CHECK-NEXT: vfwcvt.x.f.v v8, v16252; CHECK-NEXT: ret253 %a = call <16 x i64> @llvm.llrint.v16i64.v16bf16(<16 x bfloat> %x)254 ret <16 x i64> %a255}256