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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v,+f,+d,+zvfhmin,+zvfbfmin -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV324; RUN: llc -mtriple=riscv64 -mattr=+v,+f,+d,+zvfhmin,+zvfbfmin -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV646 7define <1 x i64> @llround_v1f16(<1 x half> %x) nounwind {8; RV32-LABEL: llround_v1f16:9; RV32: # %bb.0:10; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma11; RV32-NEXT: vfwcvt.f.f.v v9, v812; RV32-NEXT: fsrmi a0, 413; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma14; RV32-NEXT: vfwcvt.x.f.v v8, v915; RV32-NEXT: fsrm a016; RV32-NEXT: ret17;18; RV64-LABEL: llround_v1f16:19; RV64: # %bb.0:20; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma21; RV64-NEXT: vfwcvt.f.f.v v9, v822; RV64-NEXT: fsrmi a0, 423; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma24; RV64-NEXT: vfwcvt.x.f.v v8, v925; RV64-NEXT: fsrm a026; RV64-NEXT: ret27 %a = call <1 x i64> @llvm.llround.v1i64.v1f16(<1 x half> %x)28 ret <1 x i64> %a29}30 31define <2 x i64> @llround_v2f16(<2 x half> %x) nounwind {32; RV32-LABEL: llround_v2f16:33; RV32: # %bb.0:34; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, ma35; RV32-NEXT: vfwcvt.f.f.v v9, v836; RV32-NEXT: fsrmi a0, 437; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma38; RV32-NEXT: vfwcvt.x.f.v v8, v939; RV32-NEXT: fsrm a040; RV32-NEXT: ret41;42; RV64-LABEL: llround_v2f16:43; RV64: # %bb.0:44; RV64-NEXT: vsetivli zero, 2, e16, mf4, ta, ma45; RV64-NEXT: vfwcvt.f.f.v v9, v846; RV64-NEXT: fsrmi a0, 447; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma48; RV64-NEXT: vfwcvt.x.f.v v8, v949; RV64-NEXT: fsrm a050; RV64-NEXT: ret51 %a = call <2 x i64> @llvm.llround.v2i64.v2f16(<2 x half> %x)52 ret <2 x i64> %a53}54 55define <3 x i64> @llround_v3f16(<3 x half> %x) nounwind {56; RV32-LABEL: llround_v3f16:57; RV32: # %bb.0:58; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma59; RV32-NEXT: vfwcvt.f.f.v v10, v860; RV32-NEXT: fsrmi a0, 461; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma62; RV32-NEXT: vfwcvt.x.f.v v8, v1063; RV32-NEXT: fsrm a064; RV32-NEXT: ret65;66; RV64-LABEL: llround_v3f16:67; RV64: # %bb.0:68; RV64-NEXT: vsetivli zero, 4, e16, mf2, ta, ma69; RV64-NEXT: vfwcvt.f.f.v v10, v870; RV64-NEXT: fsrmi a0, 471; RV64-NEXT: vsetvli zero, zero, e32, m1, ta, ma72; RV64-NEXT: vfwcvt.x.f.v v8, v1073; RV64-NEXT: fsrm a074; RV64-NEXT: ret75 %a = call <3 x i64> @llvm.llround.v3i64.v3f16(<3 x half> %x)76 ret <3 x i64> %a77}78 79define <4 x i64> @llround_v4f16(<4 x half> %x) nounwind {80; RV32-LABEL: llround_v4f16:81; RV32: # %bb.0:82; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma83; RV32-NEXT: vfwcvt.f.f.v v10, v884; RV32-NEXT: fsrmi a0, 485; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma86; RV32-NEXT: vfwcvt.x.f.v v8, v1087; RV32-NEXT: fsrm a088; RV32-NEXT: ret89;90; RV64-LABEL: llround_v4f16:91; RV64: # %bb.0:92; RV64-NEXT: vsetivli zero, 4, e16, mf2, ta, ma93; RV64-NEXT: vfwcvt.f.f.v v10, v894; RV64-NEXT: fsrmi a0, 495; RV64-NEXT: vsetvli zero, zero, e32, m1, ta, ma96; RV64-NEXT: vfwcvt.x.f.v v8, v1097; RV64-NEXT: fsrm a098; RV64-NEXT: ret99 %a = call <4 x i64> @llvm.llround.v4i64.v4f16(<4 x half> %x)100 ret <4 x i64> %a101}102 103define <8 x i64> @llround_v8f16(<8 x half> %x) nounwind {104; RV32-LABEL: llround_v8f16:105; RV32: # %bb.0:106; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma107; RV32-NEXT: vfwcvt.f.f.v v12, v8108; RV32-NEXT: fsrmi a0, 4109; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma110; RV32-NEXT: vfwcvt.x.f.v v8, v12111; RV32-NEXT: fsrm a0112; RV32-NEXT: ret113;114; RV64-LABEL: llround_v8f16:115; RV64: # %bb.0:116; RV64-NEXT: vsetivli zero, 8, e16, m1, ta, ma117; RV64-NEXT: vfwcvt.f.f.v v12, v8118; RV64-NEXT: fsrmi a0, 4119; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, ma120; RV64-NEXT: vfwcvt.x.f.v v8, v12121; RV64-NEXT: fsrm a0122; RV64-NEXT: ret123 %a = call <8 x i64> @llvm.llround.v8i64.v8f16(<8 x half> %x)124 ret <8 x i64> %a125}126 127define <16 x i64> @llround_v16f16(<16 x half> %x) nounwind {128; RV32-LABEL: llround_v16f16:129; RV32: # %bb.0:130; RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma131; RV32-NEXT: vfwcvt.f.f.v v16, v8132; RV32-NEXT: fsrmi a0, 4133; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, ma134; RV32-NEXT: vfwcvt.x.f.v v8, v16135; RV32-NEXT: fsrm a0136; RV32-NEXT: ret137;138; RV64-LABEL: llround_v16f16:139; RV64: # %bb.0:140; RV64-NEXT: vsetivli zero, 16, e16, m2, ta, ma141; RV64-NEXT: vfwcvt.f.f.v v16, v8142; RV64-NEXT: fsrmi a0, 4143; RV64-NEXT: vsetvli zero, zero, e32, m4, ta, ma144; RV64-NEXT: vfwcvt.x.f.v v8, v16145; RV64-NEXT: fsrm a0146; RV64-NEXT: ret147 %a = call <16 x i64> @llvm.llround.v16i64.v16f16(<16 x half> %x)148 ret <16 x i64> %a149}150 151define <1 x i64> @llround_v1i64_v1f32(<1 x float> %x) nounwind {152; RV32-LABEL: llround_v1i64_v1f32:153; RV32: # %bb.0:154; RV32-NEXT: fsrmi a0, 4155; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma156; RV32-NEXT: vfwcvt.x.f.v v9, v8157; RV32-NEXT: fsrm a0158; RV32-NEXT: vmv1r.v v8, v9159; RV32-NEXT: ret160;161; RV64-LABEL: llround_v1i64_v1f32:162; RV64: # %bb.0:163; RV64-NEXT: fsrmi a0, 4164; RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma165; RV64-NEXT: vfwcvt.x.f.v v9, v8166; RV64-NEXT: fsrm a0167; RV64-NEXT: vmv1r.v v8, v9168; RV64-NEXT: ret169 %a = call <1 x i64> @llvm.llround.v1i64.v1f32(<1 x float> %x)170 ret <1 x i64> %a171}172 173define <2 x i64> @llround_v2i64_v2f32(<2 x float> %x) nounwind {174; RV32-LABEL: llround_v2i64_v2f32:175; RV32: # %bb.0:176; RV32-NEXT: fsrmi a0, 4177; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma178; RV32-NEXT: vfwcvt.x.f.v v9, v8179; RV32-NEXT: fsrm a0180; RV32-NEXT: vmv1r.v v8, v9181; RV32-NEXT: ret182;183; RV64-LABEL: llround_v2i64_v2f32:184; RV64: # %bb.0:185; RV64-NEXT: fsrmi a0, 4186; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma187; RV64-NEXT: vfwcvt.x.f.v v9, v8188; RV64-NEXT: fsrm a0189; RV64-NEXT: vmv1r.v v8, v9190; RV64-NEXT: ret191 %a = call <2 x i64> @llvm.llround.v2i64.v2f32(<2 x float> %x)192 ret <2 x i64> %a193}194 195define <3 x i64> @llround_v3i64_v3f32(<3 x float> %x) nounwind {196; RV32-LABEL: llround_v3i64_v3f32:197; RV32: # %bb.0:198; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma199; RV32-NEXT: vmv1r.v v10, v8200; RV32-NEXT: fsrmi a0, 4201; RV32-NEXT: vfwcvt.x.f.v v8, v10202; RV32-NEXT: fsrm a0203; RV32-NEXT: ret204;205; RV64-LABEL: llround_v3i64_v3f32:206; RV64: # %bb.0:207; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma208; RV64-NEXT: vmv1r.v v10, v8209; RV64-NEXT: fsrmi a0, 4210; RV64-NEXT: vfwcvt.x.f.v v8, v10211; RV64-NEXT: fsrm a0212; RV64-NEXT: ret213 %a = call <3 x i64> @llvm.llround.v3i64.v3f32(<3 x float> %x)214 ret <3 x i64> %a215}216 217define <4 x i64> @llround_v4i64_v4f32(<4 x float> %x) nounwind {218; RV32-LABEL: llround_v4i64_v4f32:219; RV32: # %bb.0:220; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma221; RV32-NEXT: vmv1r.v v10, v8222; RV32-NEXT: fsrmi a0, 4223; RV32-NEXT: vfwcvt.x.f.v v8, v10224; RV32-NEXT: fsrm a0225; RV32-NEXT: ret226;227; RV64-LABEL: llround_v4i64_v4f32:228; RV64: # %bb.0:229; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma230; RV64-NEXT: vmv1r.v v10, v8231; RV64-NEXT: fsrmi a0, 4232; RV64-NEXT: vfwcvt.x.f.v v8, v10233; RV64-NEXT: fsrm a0234; RV64-NEXT: ret235 %a = call <4 x i64> @llvm.llround.v4i64.v4f32(<4 x float> %x)236 ret <4 x i64> %a237}238 239define <8 x i64> @llround_v8i64_v8f32(<8 x float> %x) nounwind {240; RV32-LABEL: llround_v8i64_v8f32:241; RV32: # %bb.0:242; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma243; RV32-NEXT: vmv2r.v v12, v8244; RV32-NEXT: fsrmi a0, 4245; RV32-NEXT: vfwcvt.x.f.v v8, v12246; RV32-NEXT: fsrm a0247; RV32-NEXT: ret248;249; RV64-LABEL: llround_v8i64_v8f32:250; RV64: # %bb.0:251; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, ma252; RV64-NEXT: vmv2r.v v12, v8253; RV64-NEXT: fsrmi a0, 4254; RV64-NEXT: vfwcvt.x.f.v v8, v12255; RV64-NEXT: fsrm a0256; RV64-NEXT: ret257 %a = call <8 x i64> @llvm.llround.v8i64.v8f32(<8 x float> %x)258 ret <8 x i64> %a259}260 261define <16 x i64> @llround_v16i64_v16f32(<16 x float> %x) nounwind {262; RV32-LABEL: llround_v16i64_v16f32:263; RV32: # %bb.0:264; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma265; RV32-NEXT: vmv4r.v v16, v8266; RV32-NEXT: fsrmi a0, 4267; RV32-NEXT: vfwcvt.x.f.v v8, v16268; RV32-NEXT: fsrm a0269; RV32-NEXT: ret270;271; RV64-LABEL: llround_v16i64_v16f32:272; RV64: # %bb.0:273; RV64-NEXT: vsetivli zero, 16, e32, m4, ta, ma274; RV64-NEXT: vmv4r.v v16, v8275; RV64-NEXT: fsrmi a0, 4276; RV64-NEXT: vfwcvt.x.f.v v8, v16277; RV64-NEXT: fsrm a0278; RV64-NEXT: ret279 %a = call <16 x i64> @llvm.llround.v16i64.v16f32(<16 x float> %x)280 ret <16 x i64> %a281}282 283define <1 x i64> @llround_v1i64_v1f64(<1 x double> %x) nounwind {284; RV32-LABEL: llround_v1i64_v1f64:285; RV32: # %bb.0:286; RV32-NEXT: fsrmi a0, 4287; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma288; RV32-NEXT: vfcvt.x.f.v v8, v8289; RV32-NEXT: fsrm a0290; RV32-NEXT: ret291;292; RV64-LABEL: llround_v1i64_v1f64:293; RV64: # %bb.0:294; RV64-NEXT: fsrmi a0, 4295; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma296; RV64-NEXT: vfcvt.x.f.v v8, v8297; RV64-NEXT: fsrm a0298; RV64-NEXT: ret299 %a = call <1 x i64> @llvm.llround.v1i64.v1f64(<1 x double> %x)300 ret <1 x i64> %a301}302 303define <2 x i64> @llround_v2i64_v2f64(<2 x double> %x) nounwind {304; RV32-LABEL: llround_v2i64_v2f64:305; RV32: # %bb.0:306; RV32-NEXT: fsrmi a0, 4307; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma308; RV32-NEXT: vfcvt.x.f.v v8, v8309; RV32-NEXT: fsrm a0310; RV32-NEXT: ret311;312; RV64-LABEL: llround_v2i64_v2f64:313; RV64: # %bb.0:314; RV64-NEXT: fsrmi a0, 4315; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma316; RV64-NEXT: vfcvt.x.f.v v8, v8317; RV64-NEXT: fsrm a0318; RV64-NEXT: ret319 %a = call <2 x i64> @llvm.llround.v2i64.v2f64(<2 x double> %x)320 ret <2 x i64> %a321}322 323define <4 x i64> @llround_v4i64_v4f64(<4 x double> %x) nounwind {324; RV32-LABEL: llround_v4i64_v4f64:325; RV32: # %bb.0:326; RV32-NEXT: fsrmi a0, 4327; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma328; RV32-NEXT: vfcvt.x.f.v v8, v8329; RV32-NEXT: fsrm a0330; RV32-NEXT: ret331;332; RV64-LABEL: llround_v4i64_v4f64:333; RV64: # %bb.0:334; RV64-NEXT: fsrmi a0, 4335; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma336; RV64-NEXT: vfcvt.x.f.v v8, v8337; RV64-NEXT: fsrm a0338; RV64-NEXT: ret339 %a = call <4 x i64> @llvm.llround.v4i64.v4f64(<4 x double> %x)340 ret <4 x i64> %a341}342 343define <8 x i64> @llround_v8i64_v8f64(<8 x double> %x) nounwind {344; RV32-LABEL: llround_v8i64_v8f64:345; RV32: # %bb.0:346; RV32-NEXT: fsrmi a0, 4347; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma348; RV32-NEXT: vfcvt.x.f.v v8, v8349; RV32-NEXT: fsrm a0350; RV32-NEXT: ret351;352; RV64-LABEL: llround_v8i64_v8f64:353; RV64: # %bb.0:354; RV64-NEXT: fsrmi a0, 4355; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma356; RV64-NEXT: vfcvt.x.f.v v8, v8357; RV64-NEXT: fsrm a0358; RV64-NEXT: ret359 %a = call <8 x i64> @llvm.llround.v8i64.v8f64(<8 x double> %x)360 ret <8 x i64> %a361}362