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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfh,+zvfbfmin -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV32 %s3; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfh,+zvfbfmin -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV64 %s4 5define <5 x i8> @load_v5i8(ptr %p) {6; CHECK-LABEL: load_v5i8:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetivli zero, 5, e8, mf2, ta, ma9; CHECK-NEXT: vle8.v v8, (a0)10; CHECK-NEXT: ret11 %x = load <5 x i8>, ptr %p12 ret <5 x i8> %x13}14 15define <5 x i8> @load_v5i8_align1(ptr %p) {16; CHECK-LABEL: load_v5i8_align1:17; CHECK: # %bb.0:18; CHECK-NEXT: vsetivli zero, 5, e8, mf2, ta, ma19; CHECK-NEXT: vle8.v v8, (a0)20; CHECK-NEXT: ret21 %x = load <5 x i8>, ptr %p, align 122 ret <5 x i8> %x23}24 25define <6 x i8> @load_v6i8(ptr %p) {26; CHECK-LABEL: load_v6i8:27; CHECK: # %bb.0:28; CHECK-NEXT: vsetivli zero, 6, e8, mf2, ta, ma29; CHECK-NEXT: vle8.v v8, (a0)30; CHECK-NEXT: ret31 %x = load <6 x i8>, ptr %p32 ret <6 x i8> %x33}34 35define <12 x i8> @load_v12i8(ptr %p) {36; CHECK-LABEL: load_v12i8:37; CHECK: # %bb.0:38; CHECK-NEXT: vsetivli zero, 12, e8, m1, ta, ma39; CHECK-NEXT: vle8.v v8, (a0)40; CHECK-NEXT: ret41 %x = load <12 x i8>, ptr %p42 ret <12 x i8> %x43}44 45define <6 x i16> @load_v6i16(ptr %p) {46; CHECK-LABEL: load_v6i16:47; CHECK: # %bb.0:48; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma49; CHECK-NEXT: vle16.v v8, (a0)50; CHECK-NEXT: ret51 %x = load <6 x i16>, ptr %p52 ret <6 x i16> %x53}54 55define <6 x half> @load_v6f16(ptr %p) {56; CHECK-LABEL: load_v6f16:57; CHECK: # %bb.0:58; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma59; CHECK-NEXT: vle16.v v8, (a0)60; CHECK-NEXT: ret61 %x = load <6 x half>, ptr %p62 ret <6 x half> %x63}64 65define <6 x float> @load_v6f32(ptr %p) {66; CHECK-LABEL: load_v6f32:67; CHECK: # %bb.0:68; CHECK-NEXT: vsetivli zero, 6, e32, m2, ta, ma69; CHECK-NEXT: vle32.v v8, (a0)70; CHECK-NEXT: ret71 %x = load <6 x float>, ptr %p72 ret <6 x float> %x73}74 75define <6 x double> @load_v6f64(ptr %p) {76; CHECK-LABEL: load_v6f64:77; CHECK: # %bb.0:78; CHECK-NEXT: vsetivli zero, 6, e64, m4, ta, ma79; CHECK-NEXT: vle64.v v8, (a0)80; CHECK-NEXT: ret81 %x = load <6 x double>, ptr %p82 ret <6 x double> %x83}84 85define <6 x i1> @load_v6i1(ptr %p) {86; RV32-LABEL: load_v6i1:87; RV32: # %bb.0:88; RV32-NEXT: lbu a0, 0(a0)89; RV32-NEXT: srli a1, a0, 590; RV32-NEXT: slli a2, a0, 2791; RV32-NEXT: slli a3, a0, 2892; RV32-NEXT: slli a4, a0, 2993; RV32-NEXT: slli a5, a0, 3094; RV32-NEXT: andi a0, a0, 195; RV32-NEXT: srli a2, a2, 3196; RV32-NEXT: srli a3, a3, 3197; RV32-NEXT: srli a4, a4, 3198; RV32-NEXT: srli a5, a5, 3199; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma100; RV32-NEXT: vmv.v.x v8, a0101; RV32-NEXT: vslide1down.vx v8, v8, a5102; RV32-NEXT: vslide1down.vx v8, v8, a4103; RV32-NEXT: vslide1down.vx v8, v8, a3104; RV32-NEXT: vslide1down.vx v8, v8, a2105; RV32-NEXT: vslide1down.vx v8, v8, a1106; RV32-NEXT: vslidedown.vi v8, v8, 2107; RV32-NEXT: vand.vi v8, v8, 1108; RV32-NEXT: vmsne.vi v0, v8, 0109; RV32-NEXT: ret110;111; RV64-LABEL: load_v6i1:112; RV64: # %bb.0:113; RV64-NEXT: lbu a0, 0(a0)114; RV64-NEXT: srli a1, a0, 5115; RV64-NEXT: slli a2, a0, 59116; RV64-NEXT: slli a3, a0, 60117; RV64-NEXT: slli a4, a0, 61118; RV64-NEXT: slli a5, a0, 62119; RV64-NEXT: andi a0, a0, 1120; RV64-NEXT: srli a2, a2, 63121; RV64-NEXT: srli a3, a3, 63122; RV64-NEXT: srli a4, a4, 63123; RV64-NEXT: srli a5, a5, 63124; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, ma125; RV64-NEXT: vmv.v.x v8, a0126; RV64-NEXT: vslide1down.vx v8, v8, a5127; RV64-NEXT: vslide1down.vx v8, v8, a4128; RV64-NEXT: vslide1down.vx v8, v8, a3129; RV64-NEXT: vslide1down.vx v8, v8, a2130; RV64-NEXT: vslide1down.vx v8, v8, a1131; RV64-NEXT: vslidedown.vi v8, v8, 2132; RV64-NEXT: vand.vi v8, v8, 1133; RV64-NEXT: vmsne.vi v0, v8, 0134; RV64-NEXT: ret135 %x = load <6 x i1>, ptr %p136 ret <6 x i1> %x137}138 139 140define <4 x i32> @exact_vlen_i32_m1(ptr %p) vscale_range(2,2) {141; CHECK-LABEL: exact_vlen_i32_m1:142; CHECK: # %bb.0:143; CHECK-NEXT: vl1re32.v v8, (a0)144; CHECK-NEXT: ret145 %v = load <4 x i32>, ptr %p146 ret <4 x i32> %v147}148 149define <16 x i8> @exact_vlen_i8_m1(ptr %p) vscale_range(2,2) {150; CHECK-LABEL: exact_vlen_i8_m1:151; CHECK: # %bb.0:152; CHECK-NEXT: vl1r.v v8, (a0)153; CHECK-NEXT: ret154 %v = load <16 x i8>, ptr %p155 ret <16 x i8> %v156}157 158define <32 x i8> @exact_vlen_i8_m2(ptr %p) vscale_range(2,2) {159; CHECK-LABEL: exact_vlen_i8_m2:160; CHECK: # %bb.0:161; CHECK-NEXT: vl2r.v v8, (a0)162; CHECK-NEXT: ret163 %v = load <32 x i8>, ptr %p164 ret <32 x i8> %v165}166 167define <128 x i8> @exact_vlen_i8_m8(ptr %p) vscale_range(2,2) {168; CHECK-LABEL: exact_vlen_i8_m8:169; CHECK: # %bb.0:170; CHECK-NEXT: vl8r.v v8, (a0)171; CHECK-NEXT: ret172 %v = load <128 x i8>, ptr %p173 ret <128 x i8> %v174}175 176define <16 x i64> @exact_vlen_i64_m8(ptr %p) vscale_range(2,2) {177; CHECK-LABEL: exact_vlen_i64_m8:178; CHECK: # %bb.0:179; CHECK-NEXT: vl8re64.v v8, (a0)180; CHECK-NEXT: ret181 %v = load <16 x i64>, ptr %p182 ret <16 x i64> %v183}184 185define <6 x bfloat> @load_v6bf16(ptr %p) {186; CHECK-LABEL: load_v6bf16:187; CHECK: # %bb.0:188; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma189; CHECK-NEXT: vle16.v v8, (a0)190; CHECK-NEXT: ret191 %x = load <6 x bfloat>, ptr %p192 ret <6 x bfloat> %x193}194