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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+f,+d \3; RUN: -target-abi=ilp32d -verify-machineinstrs | FileCheck %s --check-prefix=RV324; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv64 -mattr=+v,+f,+d \5; RUN: -target-abi=lp64d -verify-machineinstrs | FileCheck %s --check-prefix=RV64-i326; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+f,+d \7; RUN: -target-abi=lp64d -verify-machineinstrs | FileCheck %s --check-prefix=RV64-i648 9define <1 x iXLen> @lrint_v1f32(<1 x float> %x, <1 x i1> %m, i32 zeroext %evl) {10; RV32-LABEL: lrint_v1f32:11; RV32: # %bb.0:12; RV32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma13; RV32-NEXT: vfcvt.x.f.v v8, v8, v0.t14; RV32-NEXT: ret15;16; RV64-i32-LABEL: lrint_v1f32:17; RV64-i32: # %bb.0:18; RV64-i32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma19; RV64-i32-NEXT: vfcvt.x.f.v v8, v8, v0.t20; RV64-i32-NEXT: ret21;22; RV64-i64-LABEL: lrint_v1f32:23; RV64-i64: # %bb.0:24; RV64-i64-NEXT: vsetvli zero, a0, e32, mf2, ta, ma25; RV64-i64-NEXT: vfwcvt.x.f.v v9, v8, v0.t26; RV64-i64-NEXT: vmv1r.v v8, v927; RV64-i64-NEXT: ret28 %a = call <1 x iXLen> @llvm.vp.lrint.v1iXLen.v1f32(<1 x float> %x, <1 x i1> %m, i32 %evl)29 ret <1 x iXLen> %a30}31 32define <2 x iXLen> @lrint_v2f32(<2 x float> %x, <2 x i1> %m, i32 zeroext %evl) {33; RV32-LABEL: lrint_v2f32:34; RV32: # %bb.0:35; RV32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma36; RV32-NEXT: vfcvt.x.f.v v8, v8, v0.t37; RV32-NEXT: ret38;39; RV64-i32-LABEL: lrint_v2f32:40; RV64-i32: # %bb.0:41; RV64-i32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma42; RV64-i32-NEXT: vfcvt.x.f.v v8, v8, v0.t43; RV64-i32-NEXT: ret44;45; RV64-i64-LABEL: lrint_v2f32:46; RV64-i64: # %bb.0:47; RV64-i64-NEXT: vsetvli zero, a0, e32, mf2, ta, ma48; RV64-i64-NEXT: vfwcvt.x.f.v v9, v8, v0.t49; RV64-i64-NEXT: vmv1r.v v8, v950; RV64-i64-NEXT: ret51 %a = call <2 x iXLen> @llvm.vp.lrint.v2iXLen.v2f32(<2 x float> %x, <2 x i1> %m, i32 %evl)52 ret <2 x iXLen> %a53}54 55define <3 x iXLen> @lrint_v3f32(<3 x float> %x, <3 x i1> %m, i32 zeroext %evl) {56; RV32-LABEL: lrint_v3f32:57; RV32: # %bb.0:58; RV32-NEXT: vsetvli zero, a0, e32, m1, ta, ma59; RV32-NEXT: vfcvt.x.f.v v8, v8, v0.t60; RV32-NEXT: ret61;62; RV64-i32-LABEL: lrint_v3f32:63; RV64-i32: # %bb.0:64; RV64-i32-NEXT: vsetvli zero, a0, e32, m1, ta, ma65; RV64-i32-NEXT: vfcvt.x.f.v v8, v8, v0.t66; RV64-i32-NEXT: ret67;68; RV64-i64-LABEL: lrint_v3f32:69; RV64-i64: # %bb.0:70; RV64-i64-NEXT: vsetvli zero, a0, e32, m1, ta, ma71; RV64-i64-NEXT: vmv1r.v v10, v872; RV64-i64-NEXT: vfwcvt.x.f.v v8, v10, v0.t73; RV64-i64-NEXT: ret74 %a = call <3 x iXLen> @llvm.vp.lrint.v3iXLen.v3f32(<3 x float> %x, <3 x i1> %m, i32 %evl)75 ret <3 x iXLen> %a76}77 78define <4 x iXLen> @lrint_v4f32(<4 x float> %x, <4 x i1> %m, i32 zeroext %evl) {79; RV32-LABEL: lrint_v4f32:80; RV32: # %bb.0:81; RV32-NEXT: vsetvli zero, a0, e32, m1, ta, ma82; RV32-NEXT: vfcvt.x.f.v v8, v8, v0.t83; RV32-NEXT: ret84;85; RV64-i32-LABEL: lrint_v4f32:86; RV64-i32: # %bb.0:87; RV64-i32-NEXT: vsetvli zero, a0, e32, m1, ta, ma88; RV64-i32-NEXT: vfcvt.x.f.v v8, v8, v0.t89; RV64-i32-NEXT: ret90;91; RV64-i64-LABEL: lrint_v4f32:92; RV64-i64: # %bb.0:93; RV64-i64-NEXT: vsetvli zero, a0, e32, m1, ta, ma94; RV64-i64-NEXT: vmv1r.v v10, v895; RV64-i64-NEXT: vfwcvt.x.f.v v8, v10, v0.t96; RV64-i64-NEXT: ret97 %a = call <4 x iXLen> @llvm.vp.lrint.v4iXLen.v4f32(<4 x float> %x, <4 x i1> %m, i32 %evl)98 ret <4 x iXLen> %a99}100 101define <8 x iXLen> @lrint_v8f32(<8 x float> %x, <8 x i1> %m, i32 zeroext %evl) {102; RV32-LABEL: lrint_v8f32:103; RV32: # %bb.0:104; RV32-NEXT: vsetvli zero, a0, e32, m2, ta, ma105; RV32-NEXT: vfcvt.x.f.v v8, v8, v0.t106; RV32-NEXT: ret107;108; RV64-i32-LABEL: lrint_v8f32:109; RV64-i32: # %bb.0:110; RV64-i32-NEXT: vsetvli zero, a0, e32, m2, ta, ma111; RV64-i32-NEXT: vfcvt.x.f.v v8, v8, v0.t112; RV64-i32-NEXT: ret113;114; RV64-i64-LABEL: lrint_v8f32:115; RV64-i64: # %bb.0:116; RV64-i64-NEXT: vsetvli zero, a0, e32, m2, ta, ma117; RV64-i64-NEXT: vmv2r.v v12, v8118; RV64-i64-NEXT: vfwcvt.x.f.v v8, v12, v0.t119; RV64-i64-NEXT: ret120 %a = call <8 x iXLen> @llvm.vp.lrint.v8iXLen.v8f32(<8 x float> %x, <8 x i1> %m, i32 %evl)121 ret <8 x iXLen> %a122}123 124define <16 x iXLen> @lrint_v16f32(<16 x float> %x, <16 x i1> %m, i32 zeroext %evl) {125; RV32-LABEL: lrint_v16f32:126; RV32: # %bb.0:127; RV32-NEXT: vsetvli zero, a0, e32, m4, ta, ma128; RV32-NEXT: vfcvt.x.f.v v8, v8, v0.t129; RV32-NEXT: ret130;131; RV64-i32-LABEL: lrint_v16f32:132; RV64-i32: # %bb.0:133; RV64-i32-NEXT: vsetvli zero, a0, e32, m4, ta, ma134; RV64-i32-NEXT: vfcvt.x.f.v v8, v8, v0.t135; RV64-i32-NEXT: ret136;137; RV64-i64-LABEL: lrint_v16f32:138; RV64-i64: # %bb.0:139; RV64-i64-NEXT: vsetvli zero, a0, e32, m4, ta, ma140; RV64-i64-NEXT: vmv4r.v v16, v8141; RV64-i64-NEXT: vfwcvt.x.f.v v8, v16, v0.t142; RV64-i64-NEXT: ret143 %a = call <16 x iXLen> @llvm.vp.lrint.v16iXLen.v16f32(<16 x float> %x, <16 x i1> %m, i32 %evl)144 ret <16 x iXLen> %a145}146 147define <1 x iXLen> @lrint_v1f64(<1 x double> %x, <1 x i1> %m, i32 zeroext %evl) {148; RV32-LABEL: lrint_v1f64:149; RV32: # %bb.0:150; RV32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma151; RV32-NEXT: vfncvt.x.f.w v9, v8, v0.t152; RV32-NEXT: vmv1r.v v8, v9153; RV32-NEXT: ret154;155; RV64-i32-LABEL: lrint_v1f64:156; RV64-i32: # %bb.0:157; RV64-i32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma158; RV64-i32-NEXT: vfncvt.x.f.w v9, v8, v0.t159; RV64-i32-NEXT: vmv1r.v v8, v9160; RV64-i32-NEXT: ret161;162; RV64-i64-LABEL: lrint_v1f64:163; RV64-i64: # %bb.0:164; RV64-i64-NEXT: vsetvli zero, a0, e64, m1, ta, ma165; RV64-i64-NEXT: vfcvt.x.f.v v8, v8, v0.t166; RV64-i64-NEXT: ret167 %a = call <1 x iXLen> @llvm.vp.lrint.v1iXLen.v1f64(<1 x double> %x, <1 x i1> %m, i32 %evl)168 ret <1 x iXLen> %a169}170 171define <2 x iXLen> @lrint_v2f64(<2 x double> %x, <2 x i1> %m, i32 zeroext %evl) {172; RV32-LABEL: lrint_v2f64:173; RV32: # %bb.0:174; RV32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma175; RV32-NEXT: vfncvt.x.f.w v9, v8, v0.t176; RV32-NEXT: vmv1r.v v8, v9177; RV32-NEXT: ret178;179; RV64-i32-LABEL: lrint_v2f64:180; RV64-i32: # %bb.0:181; RV64-i32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma182; RV64-i32-NEXT: vfncvt.x.f.w v9, v8, v0.t183; RV64-i32-NEXT: vmv1r.v v8, v9184; RV64-i32-NEXT: ret185;186; RV64-i64-LABEL: lrint_v2f64:187; RV64-i64: # %bb.0:188; RV64-i64-NEXT: vsetvli zero, a0, e64, m1, ta, ma189; RV64-i64-NEXT: vfcvt.x.f.v v8, v8, v0.t190; RV64-i64-NEXT: ret191 %a = call <2 x iXLen> @llvm.vp.lrint.v2iXLen.v2f64(<2 x double> %x, <2 x i1> %m, i32 %evl)192 ret <2 x iXLen> %a193}194 195define <4 x iXLen> @lrint_v4f64(<4 x double> %x, <4 x i1> %m, i32 zeroext %evl) {196; RV32-LABEL: lrint_v4f64:197; RV32: # %bb.0:198; RV32-NEXT: vsetvli zero, a0, e32, m1, ta, ma199; RV32-NEXT: vfncvt.x.f.w v10, v8, v0.t200; RV32-NEXT: vmv.v.v v8, v10201; RV32-NEXT: ret202;203; RV64-i32-LABEL: lrint_v4f64:204; RV64-i32: # %bb.0:205; RV64-i32-NEXT: vsetvli zero, a0, e32, m1, ta, ma206; RV64-i32-NEXT: vfncvt.x.f.w v10, v8, v0.t207; RV64-i32-NEXT: vmv.v.v v8, v10208; RV64-i32-NEXT: ret209;210; RV64-i64-LABEL: lrint_v4f64:211; RV64-i64: # %bb.0:212; RV64-i64-NEXT: vsetvli zero, a0, e64, m2, ta, ma213; RV64-i64-NEXT: vfcvt.x.f.v v8, v8, v0.t214; RV64-i64-NEXT: ret215 %a = call <4 x iXLen> @llvm.vp.lrint.v4iXLen.v4f64(<4 x double> %x, <4 x i1> %m, i32 %evl)216 ret <4 x iXLen> %a217}218 219define <8 x iXLen> @lrint_v8f64(<8 x double> %x, <8 x i1> %m, i32 zeroext %evl) {220; RV32-LABEL: lrint_v8f64:221; RV32: # %bb.0:222; RV32-NEXT: vsetvli zero, a0, e32, m2, ta, ma223; RV32-NEXT: vfncvt.x.f.w v12, v8, v0.t224; RV32-NEXT: vmv.v.v v8, v12225; RV32-NEXT: ret226;227; RV64-i32-LABEL: lrint_v8f64:228; RV64-i32: # %bb.0:229; RV64-i32-NEXT: vsetvli zero, a0, e32, m2, ta, ma230; RV64-i32-NEXT: vfncvt.x.f.w v12, v8, v0.t231; RV64-i32-NEXT: vmv.v.v v8, v12232; RV64-i32-NEXT: ret233;234; RV64-i64-LABEL: lrint_v8f64:235; RV64-i64: # %bb.0:236; RV64-i64-NEXT: vsetvli zero, a0, e64, m4, ta, ma237; RV64-i64-NEXT: vfcvt.x.f.v v8, v8, v0.t238; RV64-i64-NEXT: ret239 %a = call <8 x iXLen> @llvm.vp.lrint.v8iXLen.v8f64(<8 x double> %x, <8 x i1> %m, i32 %evl)240 ret <8 x iXLen> %a241}242