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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+f,+d,+zvfhmin,+zvfbfmin \3; RUN: -target-abi=ilp32d -verify-machineinstrs | FileCheck %s --check-prefix=RV324; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv64 -mattr=+v,+f,+d,+zvfhmin,+zvfbfmin \5; RUN: -target-abi=lp64d -verify-machineinstrs | FileCheck %s --check-prefix=RV64-i326; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+f,+d,+zvfhmin,+zvfbfmin \7; RUN: -target-abi=lp64d -verify-machineinstrs | FileCheck %s --check-prefix=RV64-i648 9define <1 x iXLen> @lrint_v1f32(<1 x float> %x) {10; RV32-LABEL: lrint_v1f32:11; RV32: # %bb.0:12; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma13; RV32-NEXT: vfcvt.x.f.v v8, v814; RV32-NEXT: ret15;16; RV64-i32-LABEL: lrint_v1f32:17; RV64-i32: # %bb.0:18; RV64-i32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma19; RV64-i32-NEXT: vfcvt.x.f.v v8, v820; RV64-i32-NEXT: ret21;22; RV64-i64-LABEL: lrint_v1f32:23; RV64-i64: # %bb.0:24; RV64-i64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma25; RV64-i64-NEXT: vfwcvt.x.f.v v9, v826; RV64-i64-NEXT: vmv1r.v v8, v927; RV64-i64-NEXT: ret28 %a = call <1 x iXLen> @llvm.lrint.v1iXLen.v1f32(<1 x float> %x)29 ret <1 x iXLen> %a30}31 32define <2 x iXLen> @lrint_v2f32(<2 x float> %x) {33; RV32-LABEL: lrint_v2f32:34; RV32: # %bb.0:35; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma36; RV32-NEXT: vfcvt.x.f.v v8, v837; RV32-NEXT: ret38;39; RV64-i32-LABEL: lrint_v2f32:40; RV64-i32: # %bb.0:41; RV64-i32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma42; RV64-i32-NEXT: vfcvt.x.f.v v8, v843; RV64-i32-NEXT: ret44;45; RV64-i64-LABEL: lrint_v2f32:46; RV64-i64: # %bb.0:47; RV64-i64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma48; RV64-i64-NEXT: vfwcvt.x.f.v v9, v849; RV64-i64-NEXT: vmv1r.v v8, v950; RV64-i64-NEXT: ret51 %a = call <2 x iXLen> @llvm.lrint.v2iXLen.v2f32(<2 x float> %x)52 ret <2 x iXLen> %a53}54 55define <3 x iXLen> @lrint_v3f32(<3 x float> %x) {56; RV32-LABEL: lrint_v3f32:57; RV32: # %bb.0:58; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma59; RV32-NEXT: vfcvt.x.f.v v8, v860; RV32-NEXT: ret61;62; RV64-i32-LABEL: lrint_v3f32:63; RV64-i32: # %bb.0:64; RV64-i32-NEXT: vsetivli zero, 4, e32, m1, ta, ma65; RV64-i32-NEXT: vfcvt.x.f.v v8, v866; RV64-i32-NEXT: ret67;68; RV64-i64-LABEL: lrint_v3f32:69; RV64-i64: # %bb.0:70; RV64-i64-NEXT: vsetivli zero, 4, e32, m1, ta, ma71; RV64-i64-NEXT: vmv1r.v v10, v872; RV64-i64-NEXT: vfwcvt.x.f.v v8, v1073; RV64-i64-NEXT: ret74 %a = call <3 x iXLen> @llvm.lrint.v3iXLen.v3f32(<3 x float> %x)75 ret <3 x iXLen> %a76}77 78define <4 x iXLen> @lrint_v4f32(<4 x float> %x) {79; RV32-LABEL: lrint_v4f32:80; RV32: # %bb.0:81; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma82; RV32-NEXT: vfcvt.x.f.v v8, v883; RV32-NEXT: ret84;85; RV64-i32-LABEL: lrint_v4f32:86; RV64-i32: # %bb.0:87; RV64-i32-NEXT: vsetivli zero, 4, e32, m1, ta, ma88; RV64-i32-NEXT: vfcvt.x.f.v v8, v889; RV64-i32-NEXT: ret90;91; RV64-i64-LABEL: lrint_v4f32:92; RV64-i64: # %bb.0:93; RV64-i64-NEXT: vsetivli zero, 4, e32, m1, ta, ma94; RV64-i64-NEXT: vmv1r.v v10, v895; RV64-i64-NEXT: vfwcvt.x.f.v v8, v1096; RV64-i64-NEXT: ret97 %a = call <4 x iXLen> @llvm.lrint.v4iXLen.v4f32(<4 x float> %x)98 ret <4 x iXLen> %a99}100 101define <8 x iXLen> @lrint_v8f32(<8 x float> %x) {102; RV32-LABEL: lrint_v8f32:103; RV32: # %bb.0:104; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma105; RV32-NEXT: vfcvt.x.f.v v8, v8106; RV32-NEXT: ret107;108; RV64-i32-LABEL: lrint_v8f32:109; RV64-i32: # %bb.0:110; RV64-i32-NEXT: vsetivli zero, 8, e32, m2, ta, ma111; RV64-i32-NEXT: vfcvt.x.f.v v8, v8112; RV64-i32-NEXT: ret113;114; RV64-i64-LABEL: lrint_v8f32:115; RV64-i64: # %bb.0:116; RV64-i64-NEXT: vsetivli zero, 8, e32, m2, ta, ma117; RV64-i64-NEXT: vmv2r.v v12, v8118; RV64-i64-NEXT: vfwcvt.x.f.v v8, v12119; RV64-i64-NEXT: ret120 %a = call <8 x iXLen> @llvm.lrint.v8iXLen.v8f32(<8 x float> %x)121 ret <8 x iXLen> %a122}123 124define <16 x iXLen> @lrint_v16f32(<16 x float> %x) {125; RV32-LABEL: lrint_v16f32:126; RV32: # %bb.0:127; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma128; RV32-NEXT: vfcvt.x.f.v v8, v8129; RV32-NEXT: ret130;131; RV64-i32-LABEL: lrint_v16f32:132; RV64-i32: # %bb.0:133; RV64-i32-NEXT: vsetivli zero, 16, e32, m4, ta, ma134; RV64-i32-NEXT: vfcvt.x.f.v v8, v8135; RV64-i32-NEXT: ret136;137; RV64-i64-LABEL: lrint_v16f32:138; RV64-i64: # %bb.0:139; RV64-i64-NEXT: vsetivli zero, 16, e32, m4, ta, ma140; RV64-i64-NEXT: vmv4r.v v16, v8141; RV64-i64-NEXT: vfwcvt.x.f.v v8, v16142; RV64-i64-NEXT: ret143 %a = call <16 x iXLen> @llvm.lrint.v16iXLen.v16f32(<16 x float> %x)144 ret <16 x iXLen> %a145}146 147define <1 x iXLen> @lrint_v1f64(<1 x double> %x) {148; RV32-LABEL: lrint_v1f64:149; RV32: # %bb.0:150; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma151; RV32-NEXT: vfncvt.x.f.w v9, v8152; RV32-NEXT: vmv1r.v v8, v9153; RV32-NEXT: ret154;155; RV64-i32-LABEL: lrint_v1f64:156; RV64-i32: # %bb.0:157; RV64-i32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma158; RV64-i32-NEXT: vfncvt.x.f.w v9, v8159; RV64-i32-NEXT: vmv1r.v v8, v9160; RV64-i32-NEXT: ret161;162; RV64-i64-LABEL: lrint_v1f64:163; RV64-i64: # %bb.0:164; RV64-i64-NEXT: vsetivli zero, 1, e64, m1, ta, ma165; RV64-i64-NEXT: vfcvt.x.f.v v8, v8166; RV64-i64-NEXT: ret167 %a = call <1 x iXLen> @llvm.lrint.v1iXLen.v1f64(<1 x double> %x)168 ret <1 x iXLen> %a169}170 171define <2 x iXLen> @lrint_v2f64(<2 x double> %x) {172; RV32-LABEL: lrint_v2f64:173; RV32: # %bb.0:174; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma175; RV32-NEXT: vfncvt.x.f.w v9, v8176; RV32-NEXT: vmv1r.v v8, v9177; RV32-NEXT: ret178;179; RV64-i32-LABEL: lrint_v2f64:180; RV64-i32: # %bb.0:181; RV64-i32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma182; RV64-i32-NEXT: vfncvt.x.f.w v9, v8183; RV64-i32-NEXT: vmv1r.v v8, v9184; RV64-i32-NEXT: ret185;186; RV64-i64-LABEL: lrint_v2f64:187; RV64-i64: # %bb.0:188; RV64-i64-NEXT: vsetivli zero, 2, e64, m1, ta, ma189; RV64-i64-NEXT: vfcvt.x.f.v v8, v8190; RV64-i64-NEXT: ret191 %a = call <2 x iXLen> @llvm.lrint.v2iXLen.v2f64(<2 x double> %x)192 ret <2 x iXLen> %a193}194 195define <4 x iXLen> @lrint_v4f64(<4 x double> %x) {196; RV32-LABEL: lrint_v4f64:197; RV32: # %bb.0:198; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma199; RV32-NEXT: vfncvt.x.f.w v10, v8200; RV32-NEXT: vmv.v.v v8, v10201; RV32-NEXT: ret202;203; RV64-i32-LABEL: lrint_v4f64:204; RV64-i32: # %bb.0:205; RV64-i32-NEXT: vsetivli zero, 4, e32, m1, ta, ma206; RV64-i32-NEXT: vfncvt.x.f.w v10, v8207; RV64-i32-NEXT: vmv.v.v v8, v10208; RV64-i32-NEXT: ret209;210; RV64-i64-LABEL: lrint_v4f64:211; RV64-i64: # %bb.0:212; RV64-i64-NEXT: vsetivli zero, 4, e64, m2, ta, ma213; RV64-i64-NEXT: vfcvt.x.f.v v8, v8214; RV64-i64-NEXT: ret215 %a = call <4 x iXLen> @llvm.lrint.v4iXLen.v4f64(<4 x double> %x)216 ret <4 x iXLen> %a217}218 219define <8 x iXLen> @lrint_v8f64(<8 x double> %x) {220; RV32-LABEL: lrint_v8f64:221; RV32: # %bb.0:222; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma223; RV32-NEXT: vfncvt.x.f.w v12, v8224; RV32-NEXT: vmv.v.v v8, v12225; RV32-NEXT: ret226;227; RV64-i32-LABEL: lrint_v8f64:228; RV64-i32: # %bb.0:229; RV64-i32-NEXT: vsetivli zero, 8, e32, m2, ta, ma230; RV64-i32-NEXT: vfncvt.x.f.w v12, v8231; RV64-i32-NEXT: vmv.v.v v8, v12232; RV64-i32-NEXT: ret233;234; RV64-i64-LABEL: lrint_v8f64:235; RV64-i64: # %bb.0:236; RV64-i64-NEXT: vsetivli zero, 8, e64, m4, ta, ma237; RV64-i64-NEXT: vfcvt.x.f.v v8, v8238; RV64-i64-NEXT: ret239 %a = call <8 x iXLen> @llvm.lrint.v8iXLen.v8f64(<8 x double> %x)240 ret <8 x iXLen> %a241}242 243define <1 x iXLen> @lrint_v1f16(<1 x half> %x) {244; RV32-LABEL: lrint_v1f16:245; RV32: # %bb.0:246; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma247; RV32-NEXT: vfwcvt.f.f.v v9, v8248; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma249; RV32-NEXT: vfcvt.x.f.v v8, v9250; RV32-NEXT: ret251;252; RV64-i32-LABEL: lrint_v1f16:253; RV64-i32: # %bb.0:254; RV64-i32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma255; RV64-i32-NEXT: vfwcvt.f.f.v v9, v8256; RV64-i32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma257; RV64-i32-NEXT: vfcvt.x.f.v v8, v9258; RV64-i32-NEXT: ret259;260; RV64-i64-LABEL: lrint_v1f16:261; RV64-i64: # %bb.0:262; RV64-i64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma263; RV64-i64-NEXT: vfwcvt.f.f.v v9, v8264; RV64-i64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma265; RV64-i64-NEXT: vfwcvt.x.f.v v8, v9266; RV64-i64-NEXT: ret267 %a = call <1 x iXLen> @llvm.lrint.v1iXLen.v1f16(<1 x half> %x)268 ret <1 x iXLen> %a269}270 271define <2 x iXLen> @lrint_v2f16(<2 x half> %x) {272; RV32-LABEL: lrint_v2f16:273; RV32: # %bb.0:274; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, ma275; RV32-NEXT: vfwcvt.f.f.v v9, v8276; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma277; RV32-NEXT: vfcvt.x.f.v v8, v9278; RV32-NEXT: ret279;280; RV64-i32-LABEL: lrint_v2f16:281; RV64-i32: # %bb.0:282; RV64-i32-NEXT: vsetivli zero, 2, e16, mf4, ta, ma283; RV64-i32-NEXT: vfwcvt.f.f.v v9, v8284; RV64-i32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma285; RV64-i32-NEXT: vfcvt.x.f.v v8, v9286; RV64-i32-NEXT: ret287;288; RV64-i64-LABEL: lrint_v2f16:289; RV64-i64: # %bb.0:290; RV64-i64-NEXT: vsetivli zero, 2, e16, mf4, ta, ma291; RV64-i64-NEXT: vfwcvt.f.f.v v9, v8292; RV64-i64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma293; RV64-i64-NEXT: vfwcvt.x.f.v v8, v9294; RV64-i64-NEXT: ret295 %a = call <2 x iXLen> @llvm.lrint.v2iXLen.v2f16(<2 x half> %x)296 ret <2 x iXLen> %a297}298 299define <3 x iXLen> @lrint_v3f16(<3 x half> %x) {300; RV32-LABEL: lrint_v3f16:301; RV32: # %bb.0:302; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma303; RV32-NEXT: vfwcvt.f.f.v v9, v8304; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma305; RV32-NEXT: vfcvt.x.f.v v8, v9306; RV32-NEXT: ret307;308; RV64-i32-LABEL: lrint_v3f16:309; RV64-i32: # %bb.0:310; RV64-i32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma311; RV64-i32-NEXT: vfwcvt.f.f.v v9, v8312; RV64-i32-NEXT: vsetvli zero, zero, e32, m1, ta, ma313; RV64-i32-NEXT: vfcvt.x.f.v v8, v9314; RV64-i32-NEXT: ret315;316; RV64-i64-LABEL: lrint_v3f16:317; RV64-i64: # %bb.0:318; RV64-i64-NEXT: vsetivli zero, 4, e16, mf2, ta, ma319; RV64-i64-NEXT: vfwcvt.f.f.v v10, v8320; RV64-i64-NEXT: vsetvli zero, zero, e32, m1, ta, ma321; RV64-i64-NEXT: vfwcvt.x.f.v v8, v10322; RV64-i64-NEXT: ret323 %a = call <3 x iXLen> @llvm.lrint.v3iXLen.v3f16(<3 x half> %x)324 ret <3 x iXLen> %a325}326 327define <4 x iXLen> @lrint_v4f16(<4 x half> %x) {328; RV32-LABEL: lrint_v4f16:329; RV32: # %bb.0:330; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma331; RV32-NEXT: vfwcvt.f.f.v v9, v8332; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma333; RV32-NEXT: vfcvt.x.f.v v8, v9334; RV32-NEXT: ret335;336; RV64-i32-LABEL: lrint_v4f16:337; RV64-i32: # %bb.0:338; RV64-i32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma339; RV64-i32-NEXT: vfwcvt.f.f.v v9, v8340; RV64-i32-NEXT: vsetvli zero, zero, e32, m1, ta, ma341; RV64-i32-NEXT: vfcvt.x.f.v v8, v9342; RV64-i32-NEXT: ret343;344; RV64-i64-LABEL: lrint_v4f16:345; RV64-i64: # %bb.0:346; RV64-i64-NEXT: vsetivli zero, 4, e16, mf2, ta, ma347; RV64-i64-NEXT: vfwcvt.f.f.v v10, v8348; RV64-i64-NEXT: vsetvli zero, zero, e32, m1, ta, ma349; RV64-i64-NEXT: vfwcvt.x.f.v v8, v10350; RV64-i64-NEXT: ret351 %a = call <4 x iXLen> @llvm.lrint.v4iXLen.v4f16(<4 x half> %x)352 ret <4 x iXLen> %a353}354 355define <8 x iXLen> @lrint_v8f16(<8 x half> %x) {356; RV32-LABEL: lrint_v8f16:357; RV32: # %bb.0:358; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma359; RV32-NEXT: vfwcvt.f.f.v v10, v8360; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma361; RV32-NEXT: vfcvt.x.f.v v8, v10362; RV32-NEXT: ret363;364; RV64-i32-LABEL: lrint_v8f16:365; RV64-i32: # %bb.0:366; RV64-i32-NEXT: vsetivli zero, 8, e16, m1, ta, ma367; RV64-i32-NEXT: vfwcvt.f.f.v v10, v8368; RV64-i32-NEXT: vsetvli zero, zero, e32, m2, ta, ma369; RV64-i32-NEXT: vfcvt.x.f.v v8, v10370; RV64-i32-NEXT: ret371;372; RV64-i64-LABEL: lrint_v8f16:373; RV64-i64: # %bb.0:374; RV64-i64-NEXT: vsetivli zero, 8, e16, m1, ta, ma375; RV64-i64-NEXT: vfwcvt.f.f.v v12, v8376; RV64-i64-NEXT: vsetvli zero, zero, e32, m2, ta, ma377; RV64-i64-NEXT: vfwcvt.x.f.v v8, v12378; RV64-i64-NEXT: ret379 %a = call <8 x iXLen> @llvm.lrint.v8iXLen.v8f16(<8 x half> %x)380 ret <8 x iXLen> %a381}382 383define <16 x iXLen> @lrint_v16f16(<16 x half> %x) {384; RV32-LABEL: lrint_v16f16:385; RV32: # %bb.0:386; RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma387; RV32-NEXT: vfwcvt.f.f.v v12, v8388; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, ma389; RV32-NEXT: vfcvt.x.f.v v8, v12390; RV32-NEXT: ret391;392; RV64-i32-LABEL: lrint_v16f16:393; RV64-i32: # %bb.0:394; RV64-i32-NEXT: vsetivli zero, 16, e16, m2, ta, ma395; RV64-i32-NEXT: vfwcvt.f.f.v v12, v8396; RV64-i32-NEXT: vsetvli zero, zero, e32, m4, ta, ma397; RV64-i32-NEXT: vfcvt.x.f.v v8, v12398; RV64-i32-NEXT: ret399;400; RV64-i64-LABEL: lrint_v16f16:401; RV64-i64: # %bb.0:402; RV64-i64-NEXT: vsetivli zero, 16, e16, m2, ta, ma403; RV64-i64-NEXT: vfwcvt.f.f.v v16, v8404; RV64-i64-NEXT: vsetvli zero, zero, e32, m4, ta, ma405; RV64-i64-NEXT: vfwcvt.x.f.v v8, v16406; RV64-i64-NEXT: ret407 %a = call <16 x iXLen> @llvm.lrint.v16iXLen.v16f16(<16 x half> %x)408 ret <16 x iXLen> %a409}410 411define <1 x iXLen> @lrint_v1bf16(<1 x bfloat> %x) {412; RV32-LABEL: lrint_v1bf16:413; RV32: # %bb.0:414; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma415; RV32-NEXT: vfwcvtbf16.f.f.v v9, v8416; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma417; RV32-NEXT: vfcvt.x.f.v v8, v9418; RV32-NEXT: ret419;420; RV64-i32-LABEL: lrint_v1bf16:421; RV64-i32: # %bb.0:422; RV64-i32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma423; RV64-i32-NEXT: vfwcvtbf16.f.f.v v9, v8424; RV64-i32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma425; RV64-i32-NEXT: vfcvt.x.f.v v8, v9426; RV64-i32-NEXT: ret427;428; RV64-i64-LABEL: lrint_v1bf16:429; RV64-i64: # %bb.0:430; RV64-i64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma431; RV64-i64-NEXT: vfwcvtbf16.f.f.v v9, v8432; RV64-i64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma433; RV64-i64-NEXT: vfwcvt.x.f.v v8, v9434; RV64-i64-NEXT: ret435 %a = call <1 x iXLen> @llvm.lrint.v1iXLen.v1bf16(<1 x bfloat> %x)436 ret <1 x iXLen> %a437}438 439define <2 x iXLen> @lrint_v2bf16(<2 x bfloat> %x) {440; RV32-LABEL: lrint_v2bf16:441; RV32: # %bb.0:442; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, ma443; RV32-NEXT: vfwcvtbf16.f.f.v v9, v8444; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma445; RV32-NEXT: vfcvt.x.f.v v8, v9446; RV32-NEXT: ret447;448; RV64-i32-LABEL: lrint_v2bf16:449; RV64-i32: # %bb.0:450; RV64-i32-NEXT: vsetivli zero, 2, e16, mf4, ta, ma451; RV64-i32-NEXT: vfwcvtbf16.f.f.v v9, v8452; RV64-i32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma453; RV64-i32-NEXT: vfcvt.x.f.v v8, v9454; RV64-i32-NEXT: ret455;456; RV64-i64-LABEL: lrint_v2bf16:457; RV64-i64: # %bb.0:458; RV64-i64-NEXT: vsetivli zero, 2, e16, mf4, ta, ma459; RV64-i64-NEXT: vfwcvtbf16.f.f.v v9, v8460; RV64-i64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma461; RV64-i64-NEXT: vfwcvt.x.f.v v8, v9462; RV64-i64-NEXT: ret463 %a = call <2 x iXLen> @llvm.lrint.v2iXLen.v2bf16(<2 x bfloat> %x)464 ret <2 x iXLen> %a465}466 467define <3 x iXLen> @lrint_v3bf16(<3 x bfloat> %x) {468; RV32-LABEL: lrint_v3bf16:469; RV32: # %bb.0:470; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma471; RV32-NEXT: vfwcvtbf16.f.f.v v9, v8472; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma473; RV32-NEXT: vfcvt.x.f.v v8, v9474; RV32-NEXT: ret475;476; RV64-i32-LABEL: lrint_v3bf16:477; RV64-i32: # %bb.0:478; RV64-i32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma479; RV64-i32-NEXT: vfwcvtbf16.f.f.v v9, v8480; RV64-i32-NEXT: vsetvli zero, zero, e32, m1, ta, ma481; RV64-i32-NEXT: vfcvt.x.f.v v8, v9482; RV64-i32-NEXT: ret483;484; RV64-i64-LABEL: lrint_v3bf16:485; RV64-i64: # %bb.0:486; RV64-i64-NEXT: vsetivli zero, 4, e16, mf2, ta, ma487; RV64-i64-NEXT: vfwcvtbf16.f.f.v v10, v8488; RV64-i64-NEXT: vsetvli zero, zero, e32, m1, ta, ma489; RV64-i64-NEXT: vfwcvt.x.f.v v8, v10490; RV64-i64-NEXT: ret491 %a = call <3 x iXLen> @llvm.lrint.v3iXLen.v3bf16(<3 x bfloat> %x)492 ret <3 x iXLen> %a493}494 495define <4 x iXLen> @lrint_v4bf16(<4 x bfloat> %x) {496; RV32-LABEL: lrint_v4bf16:497; RV32: # %bb.0:498; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma499; RV32-NEXT: vfwcvtbf16.f.f.v v9, v8500; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma501; RV32-NEXT: vfcvt.x.f.v v8, v9502; RV32-NEXT: ret503;504; RV64-i32-LABEL: lrint_v4bf16:505; RV64-i32: # %bb.0:506; RV64-i32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma507; RV64-i32-NEXT: vfwcvtbf16.f.f.v v9, v8508; RV64-i32-NEXT: vsetvli zero, zero, e32, m1, ta, ma509; RV64-i32-NEXT: vfcvt.x.f.v v8, v9510; RV64-i32-NEXT: ret511;512; RV64-i64-LABEL: lrint_v4bf16:513; RV64-i64: # %bb.0:514; RV64-i64-NEXT: vsetivli zero, 4, e16, mf2, ta, ma515; RV64-i64-NEXT: vfwcvtbf16.f.f.v v10, v8516; RV64-i64-NEXT: vsetvli zero, zero, e32, m1, ta, ma517; RV64-i64-NEXT: vfwcvt.x.f.v v8, v10518; RV64-i64-NEXT: ret519 %a = call <4 x iXLen> @llvm.lrint.v4iXLen.v4bf16(<4 x bfloat> %x)520 ret <4 x iXLen> %a521}522 523define <8 x iXLen> @lrint_v8bf16(<8 x bfloat> %x) {524; RV32-LABEL: lrint_v8bf16:525; RV32: # %bb.0:526; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma527; RV32-NEXT: vfwcvtbf16.f.f.v v10, v8528; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma529; RV32-NEXT: vfcvt.x.f.v v8, v10530; RV32-NEXT: ret531;532; RV64-i32-LABEL: lrint_v8bf16:533; RV64-i32: # %bb.0:534; RV64-i32-NEXT: vsetivli zero, 8, e16, m1, ta, ma535; RV64-i32-NEXT: vfwcvtbf16.f.f.v v10, v8536; RV64-i32-NEXT: vsetvli zero, zero, e32, m2, ta, ma537; RV64-i32-NEXT: vfcvt.x.f.v v8, v10538; RV64-i32-NEXT: ret539;540; RV64-i64-LABEL: lrint_v8bf16:541; RV64-i64: # %bb.0:542; RV64-i64-NEXT: vsetivli zero, 8, e16, m1, ta, ma543; RV64-i64-NEXT: vfwcvtbf16.f.f.v v12, v8544; RV64-i64-NEXT: vsetvli zero, zero, e32, m2, ta, ma545; RV64-i64-NEXT: vfwcvt.x.f.v v8, v12546; RV64-i64-NEXT: ret547 %a = call <8 x iXLen> @llvm.lrint.v8iXLen.v8bf16(<8 x bfloat> %x)548 ret <8 x iXLen> %a549}550 551define <16 x iXLen> @lrint_v16bf16(<16 x bfloat> %x) {552; RV32-LABEL: lrint_v16bf16:553; RV32: # %bb.0:554; RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma555; RV32-NEXT: vfwcvtbf16.f.f.v v12, v8556; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, ma557; RV32-NEXT: vfcvt.x.f.v v8, v12558; RV32-NEXT: ret559;560; RV64-i32-LABEL: lrint_v16bf16:561; RV64-i32: # %bb.0:562; RV64-i32-NEXT: vsetivli zero, 16, e16, m2, ta, ma563; RV64-i32-NEXT: vfwcvtbf16.f.f.v v12, v8564; RV64-i32-NEXT: vsetvli zero, zero, e32, m4, ta, ma565; RV64-i32-NEXT: vfcvt.x.f.v v8, v12566; RV64-i32-NEXT: ret567;568; RV64-i64-LABEL: lrint_v16bf16:569; RV64-i64: # %bb.0:570; RV64-i64-NEXT: vsetivli zero, 16, e16, m2, ta, ma571; RV64-i64-NEXT: vfwcvtbf16.f.f.v v16, v8572; RV64-i64-NEXT: vsetvli zero, zero, e32, m4, ta, ma573; RV64-i64-NEXT: vfwcvt.x.f.v v8, v16574; RV64-i64-NEXT: ret575 %a = call <16 x iXLen> @llvm.lrint.v16iXLen.v16bf16(<16 x bfloat> %x)576 ret <16 x iXLen> %a577}578 579define <32 x iXLen> @lrint_v32bf16(<32 x bfloat> %x) {580; RV32-LABEL: lrint_v32bf16:581; RV32: # %bb.0:582; RV32-NEXT: li a0, 32583; RV32-NEXT: vsetvli zero, a0, e16, m4, ta, ma584; RV32-NEXT: vfwcvtbf16.f.f.v v16, v8585; RV32-NEXT: vsetvli zero, zero, e32, m8, ta, ma586; RV32-NEXT: vfcvt.x.f.v v8, v16587; RV32-NEXT: ret588;589; RV64-i32-LABEL: lrint_v32bf16:590; RV64-i32: # %bb.0:591; RV64-i32-NEXT: li a0, 32592; RV64-i32-NEXT: vsetvli zero, a0, e16, m4, ta, ma593; RV64-i32-NEXT: vfwcvtbf16.f.f.v v16, v8594; RV64-i32-NEXT: vsetvli zero, zero, e32, m8, ta, ma595; RV64-i32-NEXT: vfcvt.x.f.v v8, v16596; RV64-i32-NEXT: ret597;598; RV64-i64-LABEL: lrint_v32bf16:599; RV64-i64: # %bb.0:600; RV64-i64-NEXT: vsetivli zero, 16, e16, m2, ta, ma601; RV64-i64-NEXT: vfwcvtbf16.f.f.v v16, v8602; RV64-i64-NEXT: vsetivli zero, 16, e16, m4, ta, ma603; RV64-i64-NEXT: vslidedown.vi v20, v8, 16604; RV64-i64-NEXT: vsetivli zero, 16, e32, m4, ta, ma605; RV64-i64-NEXT: vfwcvt.x.f.v v8, v16606; RV64-i64-NEXT: vsetvli zero, zero, e16, m2, ta, ma607; RV64-i64-NEXT: vfwcvtbf16.f.f.v v24, v20608; RV64-i64-NEXT: vsetvli zero, zero, e32, m4, ta, ma609; RV64-i64-NEXT: vfwcvt.x.f.v v16, v24610; RV64-i64-NEXT: ret611 %a = call <32 x iXLen> @llvm.lrint.v32iXLen.v32bf16(<32 x bfloat> %x)612 ret <32 x iXLen> %a613}614