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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+f,+d,+zvfhmin,+zvfbfmin \3; RUN: -target-abi=ilp32d -verify-machineinstrs | FileCheck %s --check-prefix=RV324; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv64 -mattr=+v,+f,+d,+zvfhmin,+zvfbfmin \5; RUN: -target-abi=lp64d -verify-machineinstrs | FileCheck %s --check-prefix=RV64-i326; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+f,+d,+zvfhmin,+zvfbfmin \7; RUN: -target-abi=lp64d -verify-machineinstrs | FileCheck %s --check-prefix=RV64-i648 9define <1 x iXLen> @lround_v1f16(<1 x half> %x) nounwind {10; RV32-LABEL: lround_v1f16:11; RV32: # %bb.0:12; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma13; RV32-NEXT: vfwcvt.f.f.v v9, v814; RV32-NEXT: fsrmi a0, 415; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma16; RV32-NEXT: vfcvt.x.f.v v8, v917; RV32-NEXT: fsrm a018; RV32-NEXT: ret19;20; RV64-i32-LABEL: lround_v1f16:21; RV64-i32: # %bb.0:22; RV64-i32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma23; RV64-i32-NEXT: vfwcvt.f.f.v v9, v824; RV64-i32-NEXT: fsrmi a0, 425; RV64-i32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma26; RV64-i32-NEXT: vfcvt.x.f.v v8, v927; RV64-i32-NEXT: fsrm a028; RV64-i32-NEXT: ret29;30; RV64-i64-LABEL: lround_v1f16:31; RV64-i64: # %bb.0:32; RV64-i64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma33; RV64-i64-NEXT: vfwcvt.f.f.v v9, v834; RV64-i64-NEXT: fsrmi a0, 435; RV64-i64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma36; RV64-i64-NEXT: vfwcvt.x.f.v v8, v937; RV64-i64-NEXT: fsrm a038; RV64-i64-NEXT: ret39 %a = call <1 x iXLen> @llvm.lround.v1iXLen.v1f16(<1 x half> %x)40 ret <1 x iXLen> %a41}42 43define <2 x iXLen> @lround_v2f16(<2 x half> %x) nounwind {44; RV32-LABEL: lround_v2f16:45; RV32: # %bb.0:46; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, ma47; RV32-NEXT: vfwcvt.f.f.v v9, v848; RV32-NEXT: fsrmi a0, 449; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma50; RV32-NEXT: vfcvt.x.f.v v8, v951; RV32-NEXT: fsrm a052; RV32-NEXT: ret53;54; RV64-i32-LABEL: lround_v2f16:55; RV64-i32: # %bb.0:56; RV64-i32-NEXT: vsetivli zero, 2, e16, mf4, ta, ma57; RV64-i32-NEXT: vfwcvt.f.f.v v9, v858; RV64-i32-NEXT: fsrmi a0, 459; RV64-i32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma60; RV64-i32-NEXT: vfcvt.x.f.v v8, v961; RV64-i32-NEXT: fsrm a062; RV64-i32-NEXT: ret63;64; RV64-i64-LABEL: lround_v2f16:65; RV64-i64: # %bb.0:66; RV64-i64-NEXT: vsetivli zero, 2, e16, mf4, ta, ma67; RV64-i64-NEXT: vfwcvt.f.f.v v9, v868; RV64-i64-NEXT: fsrmi a0, 469; RV64-i64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma70; RV64-i64-NEXT: vfwcvt.x.f.v v8, v971; RV64-i64-NEXT: fsrm a072; RV64-i64-NEXT: ret73 %a = call <2 x iXLen> @llvm.lround.v2iXLen.v2f16(<2 x half> %x)74 ret <2 x iXLen> %a75}76 77define <3 x iXLen> @lround_v3f16(<3 x half> %x) nounwind {78; RV32-LABEL: lround_v3f16:79; RV32: # %bb.0:80; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma81; RV32-NEXT: vfwcvt.f.f.v v9, v882; RV32-NEXT: fsrmi a0, 483; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma84; RV32-NEXT: vfcvt.x.f.v v8, v985; RV32-NEXT: fsrm a086; RV32-NEXT: ret87;88; RV64-i32-LABEL: lround_v3f16:89; RV64-i32: # %bb.0:90; RV64-i32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma91; RV64-i32-NEXT: vfwcvt.f.f.v v9, v892; RV64-i32-NEXT: fsrmi a0, 493; RV64-i32-NEXT: vsetvli zero, zero, e32, m1, ta, ma94; RV64-i32-NEXT: vfcvt.x.f.v v8, v995; RV64-i32-NEXT: fsrm a096; RV64-i32-NEXT: ret97;98; RV64-i64-LABEL: lround_v3f16:99; RV64-i64: # %bb.0:100; RV64-i64-NEXT: vsetivli zero, 4, e16, mf2, ta, ma101; RV64-i64-NEXT: vfwcvt.f.f.v v10, v8102; RV64-i64-NEXT: fsrmi a0, 4103; RV64-i64-NEXT: vsetvli zero, zero, e32, m1, ta, ma104; RV64-i64-NEXT: vfwcvt.x.f.v v8, v10105; RV64-i64-NEXT: fsrm a0106; RV64-i64-NEXT: ret107 %a = call <3 x iXLen> @llvm.lround.v3iXLen.v3f16(<3 x half> %x)108 ret <3 x iXLen> %a109}110 111define <4 x iXLen> @lround_v4f16(<4 x half> %x) nounwind {112; RV32-LABEL: lround_v4f16:113; RV32: # %bb.0:114; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma115; RV32-NEXT: vfwcvt.f.f.v v9, v8116; RV32-NEXT: fsrmi a0, 4117; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma118; RV32-NEXT: vfcvt.x.f.v v8, v9119; RV32-NEXT: fsrm a0120; RV32-NEXT: ret121;122; RV64-i32-LABEL: lround_v4f16:123; RV64-i32: # %bb.0:124; RV64-i32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma125; RV64-i32-NEXT: vfwcvt.f.f.v v9, v8126; RV64-i32-NEXT: fsrmi a0, 4127; RV64-i32-NEXT: vsetvli zero, zero, e32, m1, ta, ma128; RV64-i32-NEXT: vfcvt.x.f.v v8, v9129; RV64-i32-NEXT: fsrm a0130; RV64-i32-NEXT: ret131;132; RV64-i64-LABEL: lround_v4f16:133; RV64-i64: # %bb.0:134; RV64-i64-NEXT: vsetivli zero, 4, e16, mf2, ta, ma135; RV64-i64-NEXT: vfwcvt.f.f.v v10, v8136; RV64-i64-NEXT: fsrmi a0, 4137; RV64-i64-NEXT: vsetvli zero, zero, e32, m1, ta, ma138; RV64-i64-NEXT: vfwcvt.x.f.v v8, v10139; RV64-i64-NEXT: fsrm a0140; RV64-i64-NEXT: ret141 %a = call <4 x iXLen> @llvm.lround.v4iXLen.v4f16(<4 x half> %x)142 ret <4 x iXLen> %a143}144 145define <8 x iXLen> @lround_v8f16(<8 x half> %x) nounwind {146; RV32-LABEL: lround_v8f16:147; RV32: # %bb.0:148; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma149; RV32-NEXT: vfwcvt.f.f.v v10, v8150; RV32-NEXT: fsrmi a0, 4151; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma152; RV32-NEXT: vfcvt.x.f.v v8, v10153; RV32-NEXT: fsrm a0154; RV32-NEXT: ret155;156; RV64-i32-LABEL: lround_v8f16:157; RV64-i32: # %bb.0:158; RV64-i32-NEXT: vsetivli zero, 8, e16, m1, ta, ma159; RV64-i32-NEXT: vfwcvt.f.f.v v10, v8160; RV64-i32-NEXT: fsrmi a0, 4161; RV64-i32-NEXT: vsetvli zero, zero, e32, m2, ta, ma162; RV64-i32-NEXT: vfcvt.x.f.v v8, v10163; RV64-i32-NEXT: fsrm a0164; RV64-i32-NEXT: ret165;166; RV64-i64-LABEL: lround_v8f16:167; RV64-i64: # %bb.0:168; RV64-i64-NEXT: vsetivli zero, 8, e16, m1, ta, ma169; RV64-i64-NEXT: vfwcvt.f.f.v v12, v8170; RV64-i64-NEXT: fsrmi a0, 4171; RV64-i64-NEXT: vsetvli zero, zero, e32, m2, ta, ma172; RV64-i64-NEXT: vfwcvt.x.f.v v8, v12173; RV64-i64-NEXT: fsrm a0174; RV64-i64-NEXT: ret175 %a = call <8 x iXLen> @llvm.lround.v8iXLen.v8f16(<8 x half> %x)176 ret <8 x iXLen> %a177}178 179define <16 x iXLen> @lround_v16f16(<16 x half> %x) nounwind {180; RV32-LABEL: lround_v16f16:181; RV32: # %bb.0:182; RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma183; RV32-NEXT: vfwcvt.f.f.v v12, v8184; RV32-NEXT: fsrmi a0, 4185; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, ma186; RV32-NEXT: vfcvt.x.f.v v8, v12187; RV32-NEXT: fsrm a0188; RV32-NEXT: ret189;190; RV64-i32-LABEL: lround_v16f16:191; RV64-i32: # %bb.0:192; RV64-i32-NEXT: vsetivli zero, 16, e16, m2, ta, ma193; RV64-i32-NEXT: vfwcvt.f.f.v v12, v8194; RV64-i32-NEXT: fsrmi a0, 4195; RV64-i32-NEXT: vsetvli zero, zero, e32, m4, ta, ma196; RV64-i32-NEXT: vfcvt.x.f.v v8, v12197; RV64-i32-NEXT: fsrm a0198; RV64-i32-NEXT: ret199;200; RV64-i64-LABEL: lround_v16f16:201; RV64-i64: # %bb.0:202; RV64-i64-NEXT: vsetivli zero, 16, e16, m2, ta, ma203; RV64-i64-NEXT: vfwcvt.f.f.v v16, v8204; RV64-i64-NEXT: fsrmi a0, 4205; RV64-i64-NEXT: vsetvli zero, zero, e32, m4, ta, ma206; RV64-i64-NEXT: vfwcvt.x.f.v v8, v16207; RV64-i64-NEXT: fsrm a0208; RV64-i64-NEXT: ret209 %a = call <16 x iXLen> @llvm.lround.v16iXLen.v16f16(<16 x half> %x)210 ret <16 x iXLen> %a211}212 213define <1 x iXLen> @lround_v1f32(<1 x float> %x) nounwind {214; RV32-LABEL: lround_v1f32:215; RV32: # %bb.0:216; RV32-NEXT: fsrmi a0, 4217; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma218; RV32-NEXT: vfcvt.x.f.v v8, v8219; RV32-NEXT: fsrm a0220; RV32-NEXT: ret221;222; RV64-i32-LABEL: lround_v1f32:223; RV64-i32: # %bb.0:224; RV64-i32-NEXT: fsrmi a0, 4225; RV64-i32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma226; RV64-i32-NEXT: vfcvt.x.f.v v8, v8227; RV64-i32-NEXT: fsrm a0228; RV64-i32-NEXT: ret229;230; RV64-i64-LABEL: lround_v1f32:231; RV64-i64: # %bb.0:232; RV64-i64-NEXT: fsrmi a0, 4233; RV64-i64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma234; RV64-i64-NEXT: vfwcvt.x.f.v v9, v8235; RV64-i64-NEXT: fsrm a0236; RV64-i64-NEXT: vmv1r.v v8, v9237; RV64-i64-NEXT: ret238 %a = call <1 x iXLen> @llvm.lround.v1iXLen.v1f32(<1 x float> %x)239 ret <1 x iXLen> %a240}241 242define <2 x iXLen> @lround_v2f32(<2 x float> %x) nounwind {243; RV32-LABEL: lround_v2f32:244; RV32: # %bb.0:245; RV32-NEXT: fsrmi a0, 4246; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma247; RV32-NEXT: vfcvt.x.f.v v8, v8248; RV32-NEXT: fsrm a0249; RV32-NEXT: ret250;251; RV64-i32-LABEL: lround_v2f32:252; RV64-i32: # %bb.0:253; RV64-i32-NEXT: fsrmi a0, 4254; RV64-i32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma255; RV64-i32-NEXT: vfcvt.x.f.v v8, v8256; RV64-i32-NEXT: fsrm a0257; RV64-i32-NEXT: ret258;259; RV64-i64-LABEL: lround_v2f32:260; RV64-i64: # %bb.0:261; RV64-i64-NEXT: fsrmi a0, 4262; RV64-i64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma263; RV64-i64-NEXT: vfwcvt.x.f.v v9, v8264; RV64-i64-NEXT: fsrm a0265; RV64-i64-NEXT: vmv1r.v v8, v9266; RV64-i64-NEXT: ret267 %a = call <2 x iXLen> @llvm.lround.v2iXLen.v2f32(<2 x float> %x)268 ret <2 x iXLen> %a269}270 271define <3 x iXLen> @lround_v3f32(<3 x float> %x) nounwind {272; RV32-LABEL: lround_v3f32:273; RV32: # %bb.0:274; RV32-NEXT: fsrmi a0, 4275; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma276; RV32-NEXT: vfcvt.x.f.v v8, v8277; RV32-NEXT: fsrm a0278; RV32-NEXT: ret279;280; RV64-i32-LABEL: lround_v3f32:281; RV64-i32: # %bb.0:282; RV64-i32-NEXT: fsrmi a0, 4283; RV64-i32-NEXT: vsetivli zero, 4, e32, m1, ta, ma284; RV64-i32-NEXT: vfcvt.x.f.v v8, v8285; RV64-i32-NEXT: fsrm a0286; RV64-i32-NEXT: ret287;288; RV64-i64-LABEL: lround_v3f32:289; RV64-i64: # %bb.0:290; RV64-i64-NEXT: vsetivli zero, 4, e32, m1, ta, ma291; RV64-i64-NEXT: vmv1r.v v10, v8292; RV64-i64-NEXT: fsrmi a0, 4293; RV64-i64-NEXT: vfwcvt.x.f.v v8, v10294; RV64-i64-NEXT: fsrm a0295; RV64-i64-NEXT: ret296 %a = call <3 x iXLen> @llvm.lround.v3iXLen.v3f32(<3 x float> %x)297 ret <3 x iXLen> %a298}299 300define <4 x iXLen> @lround_v4f32(<4 x float> %x) nounwind {301; RV32-LABEL: lround_v4f32:302; RV32: # %bb.0:303; RV32-NEXT: fsrmi a0, 4304; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma305; RV32-NEXT: vfcvt.x.f.v v8, v8306; RV32-NEXT: fsrm a0307; RV32-NEXT: ret308;309; RV64-i32-LABEL: lround_v4f32:310; RV64-i32: # %bb.0:311; RV64-i32-NEXT: fsrmi a0, 4312; RV64-i32-NEXT: vsetivli zero, 4, e32, m1, ta, ma313; RV64-i32-NEXT: vfcvt.x.f.v v8, v8314; RV64-i32-NEXT: fsrm a0315; RV64-i32-NEXT: ret316;317; RV64-i64-LABEL: lround_v4f32:318; RV64-i64: # %bb.0:319; RV64-i64-NEXT: vsetivli zero, 4, e32, m1, ta, ma320; RV64-i64-NEXT: vmv1r.v v10, v8321; RV64-i64-NEXT: fsrmi a0, 4322; RV64-i64-NEXT: vfwcvt.x.f.v v8, v10323; RV64-i64-NEXT: fsrm a0324; RV64-i64-NEXT: ret325 %a = call <4 x iXLen> @llvm.lround.v4iXLen.v4f32(<4 x float> %x)326 ret <4 x iXLen> %a327}328 329define <8 x iXLen> @lround_v8f32(<8 x float> %x) nounwind {330; RV32-LABEL: lround_v8f32:331; RV32: # %bb.0:332; RV32-NEXT: fsrmi a0, 4333; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma334; RV32-NEXT: vfcvt.x.f.v v8, v8335; RV32-NEXT: fsrm a0336; RV32-NEXT: ret337;338; RV64-i32-LABEL: lround_v8f32:339; RV64-i32: # %bb.0:340; RV64-i32-NEXT: fsrmi a0, 4341; RV64-i32-NEXT: vsetivli zero, 8, e32, m2, ta, ma342; RV64-i32-NEXT: vfcvt.x.f.v v8, v8343; RV64-i32-NEXT: fsrm a0344; RV64-i32-NEXT: ret345;346; RV64-i64-LABEL: lround_v8f32:347; RV64-i64: # %bb.0:348; RV64-i64-NEXT: vsetivli zero, 8, e32, m2, ta, ma349; RV64-i64-NEXT: vmv2r.v v12, v8350; RV64-i64-NEXT: fsrmi a0, 4351; RV64-i64-NEXT: vfwcvt.x.f.v v8, v12352; RV64-i64-NEXT: fsrm a0353; RV64-i64-NEXT: ret354 %a = call <8 x iXLen> @llvm.lround.v8iXLen.v8f32(<8 x float> %x)355 ret <8 x iXLen> %a356}357 358define <16 x iXLen> @lround_v16f32(<16 x float> %x) nounwind {359; RV32-LABEL: lround_v16f32:360; RV32: # %bb.0:361; RV32-NEXT: fsrmi a0, 4362; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma363; RV32-NEXT: vfcvt.x.f.v v8, v8364; RV32-NEXT: fsrm a0365; RV32-NEXT: ret366;367; RV64-i32-LABEL: lround_v16f32:368; RV64-i32: # %bb.0:369; RV64-i32-NEXT: fsrmi a0, 4370; RV64-i32-NEXT: vsetivli zero, 16, e32, m4, ta, ma371; RV64-i32-NEXT: vfcvt.x.f.v v8, v8372; RV64-i32-NEXT: fsrm a0373; RV64-i32-NEXT: ret374;375; RV64-i64-LABEL: lround_v16f32:376; RV64-i64: # %bb.0:377; RV64-i64-NEXT: vsetivli zero, 16, e32, m4, ta, ma378; RV64-i64-NEXT: vmv4r.v v16, v8379; RV64-i64-NEXT: fsrmi a0, 4380; RV64-i64-NEXT: vfwcvt.x.f.v v8, v16381; RV64-i64-NEXT: fsrm a0382; RV64-i64-NEXT: ret383 %a = call <16 x iXLen> @llvm.lround.v16iXLen.v16f32(<16 x float> %x)384 ret <16 x iXLen> %a385}386 387define <1 x iXLen> @lround_v1f64(<1 x double> %x) nounwind {388; RV32-LABEL: lround_v1f64:389; RV32: # %bb.0:390; RV32-NEXT: fsrmi a0, 4391; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma392; RV32-NEXT: vfncvt.x.f.w v9, v8393; RV32-NEXT: fsrm a0394; RV32-NEXT: vmv1r.v v8, v9395; RV32-NEXT: ret396;397; RV64-i32-LABEL: lround_v1f64:398; RV64-i32: # %bb.0:399; RV64-i32-NEXT: fsrmi a0, 4400; RV64-i32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma401; RV64-i32-NEXT: vfncvt.x.f.w v9, v8402; RV64-i32-NEXT: fsrm a0403; RV64-i32-NEXT: vmv1r.v v8, v9404; RV64-i32-NEXT: ret405;406; RV64-i64-LABEL: lround_v1f64:407; RV64-i64: # %bb.0:408; RV64-i64-NEXT: fsrmi a0, 4409; RV64-i64-NEXT: vsetivli zero, 1, e64, m1, ta, ma410; RV64-i64-NEXT: vfcvt.x.f.v v8, v8411; RV64-i64-NEXT: fsrm a0412; RV64-i64-NEXT: ret413 %a = call <1 x iXLen> @llvm.lround.v1iXLen.v1f64(<1 x double> %x)414 ret <1 x iXLen> %a415}416 417define <2 x iXLen> @lround_v2f64(<2 x double> %x) nounwind {418; RV32-LABEL: lround_v2f64:419; RV32: # %bb.0:420; RV32-NEXT: fsrmi a0, 4421; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma422; RV32-NEXT: vfncvt.x.f.w v9, v8423; RV32-NEXT: fsrm a0424; RV32-NEXT: vmv1r.v v8, v9425; RV32-NEXT: ret426;427; RV64-i32-LABEL: lround_v2f64:428; RV64-i32: # %bb.0:429; RV64-i32-NEXT: fsrmi a0, 4430; RV64-i32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma431; RV64-i32-NEXT: vfncvt.x.f.w v9, v8432; RV64-i32-NEXT: fsrm a0433; RV64-i32-NEXT: vmv1r.v v8, v9434; RV64-i32-NEXT: ret435;436; RV64-i64-LABEL: lround_v2f64:437; RV64-i64: # %bb.0:438; RV64-i64-NEXT: fsrmi a0, 4439; RV64-i64-NEXT: vsetivli zero, 2, e64, m1, ta, ma440; RV64-i64-NEXT: vfcvt.x.f.v v8, v8441; RV64-i64-NEXT: fsrm a0442; RV64-i64-NEXT: ret443 %a = call <2 x iXLen> @llvm.lround.v2iXLen.v2f64(<2 x double> %x)444 ret <2 x iXLen> %a445}446 447define <4 x iXLen> @lround_v4f64(<4 x double> %x) nounwind {448; RV32-LABEL: lround_v4f64:449; RV32: # %bb.0:450; RV32-NEXT: fsrmi a0, 4451; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma452; RV32-NEXT: vfncvt.x.f.w v10, v8453; RV32-NEXT: fsrm a0454; RV32-NEXT: vmv.v.v v8, v10455; RV32-NEXT: ret456;457; RV64-i32-LABEL: lround_v4f64:458; RV64-i32: # %bb.0:459; RV64-i32-NEXT: fsrmi a0, 4460; RV64-i32-NEXT: vsetivli zero, 4, e32, m1, ta, ma461; RV64-i32-NEXT: vfncvt.x.f.w v10, v8462; RV64-i32-NEXT: fsrm a0463; RV64-i32-NEXT: vmv.v.v v8, v10464; RV64-i32-NEXT: ret465;466; RV64-i64-LABEL: lround_v4f64:467; RV64-i64: # %bb.0:468; RV64-i64-NEXT: fsrmi a0, 4469; RV64-i64-NEXT: vsetivli zero, 4, e64, m2, ta, ma470; RV64-i64-NEXT: vfcvt.x.f.v v8, v8471; RV64-i64-NEXT: fsrm a0472; RV64-i64-NEXT: ret473 %a = call <4 x iXLen> @llvm.lround.v4iXLen.v4f64(<4 x double> %x)474 ret <4 x iXLen> %a475}476 477define <8 x iXLen> @lround_v8f64(<8 x double> %x) nounwind {478; RV32-LABEL: lround_v8f64:479; RV32: # %bb.0:480; RV32-NEXT: fsrmi a0, 4481; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma482; RV32-NEXT: vfncvt.x.f.w v12, v8483; RV32-NEXT: fsrm a0484; RV32-NEXT: vmv.v.v v8, v12485; RV32-NEXT: ret486;487; RV64-i32-LABEL: lround_v8f64:488; RV64-i32: # %bb.0:489; RV64-i32-NEXT: fsrmi a0, 4490; RV64-i32-NEXT: vsetivli zero, 8, e32, m2, ta, ma491; RV64-i32-NEXT: vfncvt.x.f.w v12, v8492; RV64-i32-NEXT: fsrm a0493; RV64-i32-NEXT: vmv.v.v v8, v12494; RV64-i32-NEXT: ret495;496; RV64-i64-LABEL: lround_v8f64:497; RV64-i64: # %bb.0:498; RV64-i64-NEXT: fsrmi a0, 4499; RV64-i64-NEXT: vsetivli zero, 8, e64, m4, ta, ma500; RV64-i64-NEXT: vfcvt.x.f.v v8, v8501; RV64-i64-NEXT: fsrm a0502; RV64-i64-NEXT: ret503 %a = call <8 x iXLen> @llvm.lround.v8iXLen.v8f64(<8 x double> %x)504 ret <8 x iXLen> %a505}506 507define <32 x iXLen> @lround_v32bf16(<32 x bfloat> %x) {508; RV32-LABEL: lround_v32bf16:509; RV32: # %bb.0:510; RV32-NEXT: li a0, 32511; RV32-NEXT: vsetvli zero, a0, e16, m4, ta, ma512; RV32-NEXT: vfwcvtbf16.f.f.v v16, v8513; RV32-NEXT: fsrmi a0, 4514; RV32-NEXT: vsetvli zero, zero, e32, m8, ta, ma515; RV32-NEXT: vfcvt.x.f.v v8, v16516; RV32-NEXT: fsrm a0517; RV32-NEXT: ret518;519; RV64-i32-LABEL: lround_v32bf16:520; RV64-i32: # %bb.0:521; RV64-i32-NEXT: li a0, 32522; RV64-i32-NEXT: vsetvli zero, a0, e16, m4, ta, ma523; RV64-i32-NEXT: vfwcvtbf16.f.f.v v16, v8524; RV64-i32-NEXT: fsrmi a0, 4525; RV64-i32-NEXT: vsetvli zero, zero, e32, m8, ta, ma526; RV64-i32-NEXT: vfcvt.x.f.v v8, v16527; RV64-i32-NEXT: fsrm a0528; RV64-i32-NEXT: ret529;530; RV64-i64-LABEL: lround_v32bf16:531; RV64-i64: # %bb.0:532; RV64-i64-NEXT: vsetivli zero, 16, e16, m2, ta, ma533; RV64-i64-NEXT: vfwcvtbf16.f.f.v v16, v8534; RV64-i64-NEXT: fsrmi a0, 4535; RV64-i64-NEXT: vsetivli zero, 16, e16, m4, ta, ma536; RV64-i64-NEXT: vslidedown.vi v20, v8, 16537; RV64-i64-NEXT: vsetivli zero, 16, e32, m4, ta, ma538; RV64-i64-NEXT: vfwcvt.x.f.v v8, v16539; RV64-i64-NEXT: vsetvli zero, zero, e16, m2, ta, ma540; RV64-i64-NEXT: vfwcvtbf16.f.f.v v24, v20541; RV64-i64-NEXT: vsetvli zero, zero, e32, m4, ta, ma542; RV64-i64-NEXT: vfwcvt.x.f.v v16, v24543; RV64-i64-NEXT: fsrm a0544; RV64-i64-NEXT: ret545 %a = call <32 x iXLen> @llvm.lround.v32iXLen.v32bf16(<32 x bfloat> %x)546 ret <32 x iXLen> %a547}548