156 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \3; RUN: | FileCheck %s4; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \5; RUN: | FileCheck %s6 7define <1 x i1> @and_v1i1(<1 x i1> %b, <1 x i1> %c, <1 x i1> %a, i32 zeroext %evl) {8; CHECK-LABEL: and_v1i1:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma11; CHECK-NEXT: vmand.mm v0, v0, v812; CHECK-NEXT: ret13 %v = call <1 x i1> @llvm.vp.and.v1i1(<1 x i1> %b, <1 x i1> %c, <1 x i1> %a, i32 %evl)14 ret <1 x i1> %v15}16 17define <2 x i1> @and_v2i1(<2 x i1> %b, <2 x i1> %c, <2 x i1> %a, i32 zeroext %evl) {18; CHECK-LABEL: and_v2i1:19; CHECK: # %bb.0:20; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma21; CHECK-NEXT: vmand.mm v0, v0, v822; CHECK-NEXT: ret23 %v = call <2 x i1> @llvm.vp.and.v2i1(<2 x i1> %b, <2 x i1> %c, <2 x i1> %a, i32 %evl)24 ret <2 x i1> %v25}26 27define <4 x i1> @and_v4i1(<4 x i1> %b, <4 x i1> %c, <4 x i1> %a, i32 zeroext %evl) {28; CHECK-LABEL: and_v4i1:29; CHECK: # %bb.0:30; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma31; CHECK-NEXT: vmand.mm v0, v0, v832; CHECK-NEXT: ret33 %v = call <4 x i1> @llvm.vp.and.v4i1(<4 x i1> %b, <4 x i1> %c, <4 x i1> %a, i32 %evl)34 ret <4 x i1> %v35}36 37define <8 x i1> @and_v8i1(<8 x i1> %b, <8 x i1> %c, <8 x i1> %a, i32 zeroext %evl) {38; CHECK-LABEL: and_v8i1:39; CHECK: # %bb.0:40; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma41; CHECK-NEXT: vmand.mm v0, v0, v842; CHECK-NEXT: ret43 %v = call <8 x i1> @llvm.vp.and.v8i1(<8 x i1> %b, <8 x i1> %c, <8 x i1> %a, i32 %evl)44 ret <8 x i1> %v45}46 47define <16 x i1> @and_v16i1(<16 x i1> %b, <16 x i1> %c, <16 x i1> %a, i32 zeroext %evl) {48; CHECK-LABEL: and_v16i1:49; CHECK: # %bb.0:50; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma51; CHECK-NEXT: vmand.mm v0, v0, v852; CHECK-NEXT: ret53 %v = call <16 x i1> @llvm.vp.and.v16i1(<16 x i1> %b, <16 x i1> %c, <16 x i1> %a, i32 %evl)54 ret <16 x i1> %v55}56 57define <1 x i1> @or_v1i1(<1 x i1> %b, <1 x i1> %c, <1 x i1> %a, i32 zeroext %evl) {58; CHECK-LABEL: or_v1i1:59; CHECK: # %bb.0:60; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma61; CHECK-NEXT: vmor.mm v0, v0, v862; CHECK-NEXT: ret63 %v = call <1 x i1> @llvm.vp.or.v1i1(<1 x i1> %b, <1 x i1> %c, <1 x i1> %a, i32 %evl)64 ret <1 x i1> %v65}66 67define <2 x i1> @or_v2i1(<2 x i1> %b, <2 x i1> %c, <2 x i1> %a, i32 zeroext %evl) {68; CHECK-LABEL: or_v2i1:69; CHECK: # %bb.0:70; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma71; CHECK-NEXT: vmor.mm v0, v0, v872; CHECK-NEXT: ret73 %v = call <2 x i1> @llvm.vp.or.v2i1(<2 x i1> %b, <2 x i1> %c, <2 x i1> %a, i32 %evl)74 ret <2 x i1> %v75}76 77define <4 x i1> @or_v4i1(<4 x i1> %b, <4 x i1> %c, <4 x i1> %a, i32 zeroext %evl) {78; CHECK-LABEL: or_v4i1:79; CHECK: # %bb.0:80; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma81; CHECK-NEXT: vmor.mm v0, v0, v882; CHECK-NEXT: ret83 %v = call <4 x i1> @llvm.vp.or.v4i1(<4 x i1> %b, <4 x i1> %c, <4 x i1> %a, i32 %evl)84 ret <4 x i1> %v85}86 87define <8 x i1> @or_v8i1(<8 x i1> %b, <8 x i1> %c, <8 x i1> %a, i32 zeroext %evl) {88; CHECK-LABEL: or_v8i1:89; CHECK: # %bb.0:90; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma91; CHECK-NEXT: vmor.mm v0, v0, v892; CHECK-NEXT: ret93 %v = call <8 x i1> @llvm.vp.or.v8i1(<8 x i1> %b, <8 x i1> %c, <8 x i1> %a, i32 %evl)94 ret <8 x i1> %v95}96 97define <16 x i1> @or_v16i1(<16 x i1> %b, <16 x i1> %c, <16 x i1> %a, i32 zeroext %evl) {98; CHECK-LABEL: or_v16i1:99; CHECK: # %bb.0:100; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma101; CHECK-NEXT: vmor.mm v0, v0, v8102; CHECK-NEXT: ret103 %v = call <16 x i1> @llvm.vp.or.v16i1(<16 x i1> %b, <16 x i1> %c, <16 x i1> %a, i32 %evl)104 ret <16 x i1> %v105}106 107define <1 x i1> @xor_v1i1(<1 x i1> %b, <1 x i1> %c, <1 x i1> %a, i32 zeroext %evl) {108; CHECK-LABEL: xor_v1i1:109; CHECK: # %bb.0:110; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma111; CHECK-NEXT: vmxor.mm v0, v0, v8112; CHECK-NEXT: ret113 %v = call <1 x i1> @llvm.vp.xor.v1i1(<1 x i1> %b, <1 x i1> %c, <1 x i1> %a, i32 %evl)114 ret <1 x i1> %v115}116 117define <2 x i1> @xor_v2i1(<2 x i1> %b, <2 x i1> %c, <2 x i1> %a, i32 zeroext %evl) {118; CHECK-LABEL: xor_v2i1:119; CHECK: # %bb.0:120; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma121; CHECK-NEXT: vmxor.mm v0, v0, v8122; CHECK-NEXT: ret123 %v = call <2 x i1> @llvm.vp.xor.v2i1(<2 x i1> %b, <2 x i1> %c, <2 x i1> %a, i32 %evl)124 ret <2 x i1> %v125}126 127define <4 x i1> @xor_v4i1(<4 x i1> %b, <4 x i1> %c, <4 x i1> %a, i32 zeroext %evl) {128; CHECK-LABEL: xor_v4i1:129; CHECK: # %bb.0:130; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma131; CHECK-NEXT: vmxor.mm v0, v0, v8132; CHECK-NEXT: ret133 %v = call <4 x i1> @llvm.vp.xor.v4i1(<4 x i1> %b, <4 x i1> %c, <4 x i1> %a, i32 %evl)134 ret <4 x i1> %v135}136 137define <8 x i1> @xor_v8i1(<8 x i1> %b, <8 x i1> %c, <8 x i1> %a, i32 zeroext %evl) {138; CHECK-LABEL: xor_v8i1:139; CHECK: # %bb.0:140; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma141; CHECK-NEXT: vmxor.mm v0, v0, v8142; CHECK-NEXT: ret143 %v = call <8 x i1> @llvm.vp.xor.v8i1(<8 x i1> %b, <8 x i1> %c, <8 x i1> %a, i32 %evl)144 ret <8 x i1> %v145}146 147define <16 x i1> @xor_v16i1(<16 x i1> %b, <16 x i1> %c, <16 x i1> %a, i32 zeroext %evl) {148; CHECK-LABEL: xor_v16i1:149; CHECK: # %bb.0:150; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma151; CHECK-NEXT: vmxor.mm v0, v0, v8152; CHECK-NEXT: ret153 %v = call <16 x i1> @llvm.vp.xor.v16i1(<16 x i1> %b, <16 x i1> %c, <16 x i1> %a, i32 %evl)154 ret <16 x i1> %v155}156