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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV323; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV644; Test with ELEN limited5; RUN: llc -mtriple=riscv32 -mattr=+f,+zve32f,+zvl128b -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVE32F6; RUN: llc -mtriple=riscv64 -mattr=+f,+zve32f,+zvl128b -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVE32F7 8define <1 x i1> @buildvec_mask_nonconst_v1i1(i1 %x) {9; CHECK-LABEL: buildvec_mask_nonconst_v1i1:10; CHECK: # %bb.0:11; CHECK-NEXT: andi a0, a0, 112; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma13; CHECK-NEXT: vmv.s.x v8, a014; CHECK-NEXT: vmsne.vi v0, v8, 015; CHECK-NEXT: ret16;17; ZVE32F-LABEL: buildvec_mask_nonconst_v1i1:18; ZVE32F: # %bb.0:19; ZVE32F-NEXT: andi a0, a0, 120; ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma21; ZVE32F-NEXT: vmv.s.x v8, a022; ZVE32F-NEXT: vmsne.vi v0, v8, 023; ZVE32F-NEXT: ret24 %1 = insertelement <1 x i1> poison, i1 %x, i32 025 ret <1 x i1> %126}27 28define <1 x i1> @buildvec_mask_optsize_nonconst_v1i1(i1 %x) optsize {29; CHECK-LABEL: buildvec_mask_optsize_nonconst_v1i1:30; CHECK: # %bb.0:31; CHECK-NEXT: andi a0, a0, 132; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma33; CHECK-NEXT: vmv.s.x v8, a034; CHECK-NEXT: vmsne.vi v0, v8, 035; CHECK-NEXT: ret36;37; ZVE32F-LABEL: buildvec_mask_optsize_nonconst_v1i1:38; ZVE32F: # %bb.0:39; ZVE32F-NEXT: andi a0, a0, 140; ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma41; ZVE32F-NEXT: vmv.s.x v8, a042; ZVE32F-NEXT: vmsne.vi v0, v8, 043; ZVE32F-NEXT: ret44 %1 = insertelement <1 x i1> poison, i1 %x, i32 045 ret <1 x i1> %146}47 48define <2 x i1> @buildvec_mask_nonconst_v2i1(i1 %x, i1 %y) {49; CHECK-LABEL: buildvec_mask_nonconst_v2i1:50; CHECK: # %bb.0:51; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma52; CHECK-NEXT: vmv.v.x v8, a053; CHECK-NEXT: vslide1down.vx v8, v8, a154; CHECK-NEXT: vand.vi v8, v8, 155; CHECK-NEXT: vmsne.vi v0, v8, 056; CHECK-NEXT: ret57;58; ZVE32F-LABEL: buildvec_mask_nonconst_v2i1:59; ZVE32F: # %bb.0:60; ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma61; ZVE32F-NEXT: vmv.v.x v8, a062; ZVE32F-NEXT: vslide1down.vx v8, v8, a163; ZVE32F-NEXT: vand.vi v8, v8, 164; ZVE32F-NEXT: vmsne.vi v0, v8, 065; ZVE32F-NEXT: ret66 %1 = insertelement <2 x i1> poison, i1 %x, i32 067 %2 = insertelement <2 x i1> %1, i1 %y, i32 168 ret <2 x i1> %269}70 71; FIXME: optsize isn't smaller than the code above72define <2 x i1> @buildvec_mask_optsize_nonconst_v2i1(i1 %x, i1 %y) optsize {73; CHECK-LABEL: buildvec_mask_optsize_nonconst_v2i1:74; CHECK: # %bb.0:75; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma76; CHECK-NEXT: vmv.v.x v8, a077; CHECK-NEXT: vslide1down.vx v8, v8, a178; CHECK-NEXT: vand.vi v8, v8, 179; CHECK-NEXT: vmsne.vi v0, v8, 080; CHECK-NEXT: ret81;82; ZVE32F-LABEL: buildvec_mask_optsize_nonconst_v2i1:83; ZVE32F: # %bb.0:84; ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma85; ZVE32F-NEXT: vmv.v.x v8, a086; ZVE32F-NEXT: vslide1down.vx v8, v8, a187; ZVE32F-NEXT: vand.vi v8, v8, 188; ZVE32F-NEXT: vmsne.vi v0, v8, 089; ZVE32F-NEXT: ret90 %1 = insertelement <2 x i1> poison, i1 %x, i32 091 %2 = insertelement <2 x i1> %1, i1 %y, i32 192 ret <2 x i1> %293}94 95define <3 x i1> @buildvec_mask_v1i1() {96; CHECK-LABEL: buildvec_mask_v1i1:97; CHECK: # %bb.0:98; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma99; CHECK-NEXT: vmv.v.i v0, 2100; CHECK-NEXT: ret101;102; ZVE32F-LABEL: buildvec_mask_v1i1:103; ZVE32F: # %bb.0:104; ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma105; ZVE32F-NEXT: vmv.v.i v0, 2106; ZVE32F-NEXT: ret107 ret <3 x i1> <i1 0, i1 1, i1 0>108}109 110define <3 x i1> @buildvec_mask_optsize_v1i1() optsize {111; CHECK-LABEL: buildvec_mask_optsize_v1i1:112; CHECK: # %bb.0:113; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma114; CHECK-NEXT: vmv.v.i v0, 2115; CHECK-NEXT: ret116;117; ZVE32F-LABEL: buildvec_mask_optsize_v1i1:118; ZVE32F: # %bb.0:119; ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma120; ZVE32F-NEXT: vmv.v.i v0, 2121; ZVE32F-NEXT: ret122 ret <3 x i1> <i1 0, i1 1, i1 0>123}124 125define <4 x i1> @buildvec_mask_v4i1() {126; CHECK-LABEL: buildvec_mask_v4i1:127; CHECK: # %bb.0:128; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma129; CHECK-NEXT: vmv.v.i v0, 6130; CHECK-NEXT: ret131;132; ZVE32F-LABEL: buildvec_mask_v4i1:133; ZVE32F: # %bb.0:134; ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma135; ZVE32F-NEXT: vmv.v.i v0, 6136; ZVE32F-NEXT: ret137 ret <4 x i1> <i1 0, i1 1, i1 1, i1 0>138}139 140define <4 x i1> @buildvec_mask_nonconst_v4i1(i1 %x, i1 %y) {141; CHECK-LABEL: buildvec_mask_nonconst_v4i1:142; CHECK: # %bb.0:143; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma144; CHECK-NEXT: vmv.v.i v0, 3145; CHECK-NEXT: vmv.v.x v8, a1146; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0147; CHECK-NEXT: vand.vi v8, v8, 1148; CHECK-NEXT: vmsne.vi v0, v8, 0149; CHECK-NEXT: ret150;151; ZVE32F-LABEL: buildvec_mask_nonconst_v4i1:152; ZVE32F: # %bb.0:153; ZVE32F-NEXT: vsetivli zero, 4, e8, mf4, ta, ma154; ZVE32F-NEXT: vmv.v.i v0, 3155; ZVE32F-NEXT: vmv.v.x v8, a1156; ZVE32F-NEXT: vmerge.vxm v8, v8, a0, v0157; ZVE32F-NEXT: vand.vi v8, v8, 1158; ZVE32F-NEXT: vmsne.vi v0, v8, 0159; ZVE32F-NEXT: ret160 %1 = insertelement <4 x i1> poison, i1 %x, i32 0161 %2 = insertelement <4 x i1> %1, i1 %x, i32 1162 %3 = insertelement <4 x i1> %2, i1 %y, i32 2163 %4 = insertelement <4 x i1> %3, i1 %y, i32 3164 ret <4 x i1> %4165}166 167; FIXME: optsize isn't smaller than the code above168define <4 x i1> @buildvec_mask_optsize_nonconst_v4i1(i1 %x, i1 %y) optsize {169; CHECK-LABEL: buildvec_mask_optsize_nonconst_v4i1:170; CHECK: # %bb.0:171; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma172; CHECK-NEXT: vmv.v.x v8, a0173; CHECK-NEXT: vslide1down.vx v8, v8, a0174; CHECK-NEXT: vslide1down.vx v8, v8, a1175; CHECK-NEXT: vslide1down.vx v8, v8, a1176; CHECK-NEXT: vand.vi v8, v8, 1177; CHECK-NEXT: vmsne.vi v0, v8, 0178; CHECK-NEXT: ret179;180; ZVE32F-LABEL: buildvec_mask_optsize_nonconst_v4i1:181; ZVE32F: # %bb.0:182; ZVE32F-NEXT: vsetivli zero, 4, e8, mf4, ta, ma183; ZVE32F-NEXT: vmv.v.x v8, a0184; ZVE32F-NEXT: vslide1down.vx v8, v8, a0185; ZVE32F-NEXT: vslide1down.vx v8, v8, a1186; ZVE32F-NEXT: vslide1down.vx v8, v8, a1187; ZVE32F-NEXT: vand.vi v8, v8, 1188; ZVE32F-NEXT: vmsne.vi v0, v8, 0189; ZVE32F-NEXT: ret190 %1 = insertelement <4 x i1> poison, i1 %x, i32 0191 %2 = insertelement <4 x i1> %1, i1 %x, i32 1192 %3 = insertelement <4 x i1> %2, i1 %y, i32 2193 %4 = insertelement <4 x i1> %3, i1 %y, i32 3194 ret <4 x i1> %4195}196 197define <4 x i1> @buildvec_mask_nonconst_v4i1_2(i1 %x, i1 %y) {198; CHECK-LABEL: buildvec_mask_nonconst_v4i1_2:199; CHECK: # %bb.0:200; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma201; CHECK-NEXT: vmv.v.i v8, 0202; CHECK-NEXT: vslide1down.vx v8, v8, a0203; CHECK-NEXT: li a0, 1204; CHECK-NEXT: vslide1down.vx v8, v8, a0205; CHECK-NEXT: vslide1down.vx v8, v8, a1206; CHECK-NEXT: vand.vi v8, v8, 1207; CHECK-NEXT: vmsne.vi v0, v8, 0208; CHECK-NEXT: ret209;210; ZVE32F-LABEL: buildvec_mask_nonconst_v4i1_2:211; ZVE32F: # %bb.0:212; ZVE32F-NEXT: vsetivli zero, 4, e8, mf4, ta, ma213; ZVE32F-NEXT: vmv.v.i v8, 0214; ZVE32F-NEXT: vslide1down.vx v8, v8, a0215; ZVE32F-NEXT: li a0, 1216; ZVE32F-NEXT: vslide1down.vx v8, v8, a0217; ZVE32F-NEXT: vslide1down.vx v8, v8, a1218; ZVE32F-NEXT: vand.vi v8, v8, 1219; ZVE32F-NEXT: vmsne.vi v0, v8, 0220; ZVE32F-NEXT: ret221 %1 = insertelement <4 x i1> poison, i1 0, i32 0222 %2 = insertelement <4 x i1> %1, i1 %x, i32 1223 %3 = insertelement <4 x i1> %2, i1 1, i32 2224 %4 = insertelement <4 x i1> %3, i1 %y, i32 3225 ret <4 x i1> %4226}227 228define <8 x i1> @buildvec_mask_v8i1() {229; CHECK-LABEL: buildvec_mask_v8i1:230; CHECK: # %bb.0:231; CHECK-NEXT: li a0, 182232; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma233; CHECK-NEXT: vmv.s.x v0, a0234; CHECK-NEXT: ret235;236; ZVE32F-LABEL: buildvec_mask_v8i1:237; ZVE32F: # %bb.0:238; ZVE32F-NEXT: li a0, 182239; ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma240; ZVE32F-NEXT: vmv.s.x v0, a0241; ZVE32F-NEXT: ret242 ret <8 x i1> <i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1>243}244 245define <8 x i1> @buildvec_mask_nonconst_v8i1(i1 %x, i1 %y) {246; CHECK-LABEL: buildvec_mask_nonconst_v8i1:247; CHECK: # %bb.0:248; CHECK-NEXT: li a2, 19249; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma250; CHECK-NEXT: vmv.s.x v0, a2251; CHECK-NEXT: vmv.v.x v8, a1252; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0253; CHECK-NEXT: vand.vi v8, v8, 1254; CHECK-NEXT: vmsne.vi v0, v8, 0255; CHECK-NEXT: ret256;257; ZVE32F-LABEL: buildvec_mask_nonconst_v8i1:258; ZVE32F: # %bb.0:259; ZVE32F-NEXT: li a2, 19260; ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma261; ZVE32F-NEXT: vmv.s.x v0, a2262; ZVE32F-NEXT: vmv.v.x v8, a1263; ZVE32F-NEXT: vmerge.vxm v8, v8, a0, v0264; ZVE32F-NEXT: vand.vi v8, v8, 1265; ZVE32F-NEXT: vmsne.vi v0, v8, 0266; ZVE32F-NEXT: ret267 %1 = insertelement <8 x i1> poison, i1 %x, i32 0268 %2 = insertelement <8 x i1> %1, i1 %x, i32 1269 %3 = insertelement <8 x i1> %2, i1 %y, i32 2270 %4 = insertelement <8 x i1> %3, i1 %y, i32 3271 %5 = insertelement <8 x i1> %4, i1 %x, i32 4272 %6 = insertelement <8 x i1> %5, i1 %y, i32 5273 %7 = insertelement <8 x i1> %6, i1 %y, i32 6274 %8 = insertelement <8 x i1> %7, i1 %y, i32 7275 ret <8 x i1> %8276}277 278define <8 x i1> @buildvec_mask_nonconst_v8i1_2(i1 %x, i1 %y, i1 %z, i1 %w) {279; CHECK-LABEL: buildvec_mask_nonconst_v8i1_2:280; CHECK: # %bb.0:281; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu282; CHECK-NEXT: vmv.v.x v8, a0283; CHECK-NEXT: vslide1down.vx v9, v8, a3284; CHECK-NEXT: li a3, 1285; CHECK-NEXT: vmv.v.i v0, 15286; CHECK-NEXT: vslide1down.vx v8, v8, a0287; CHECK-NEXT: vslide1down.vx v9, v9, zero288; CHECK-NEXT: vslide1down.vx v8, v8, a3289; CHECK-NEXT: vslide1down.vx v9, v9, a2290; CHECK-NEXT: vslide1down.vx v8, v8, a1291; CHECK-NEXT: vslidedown.vi v9, v8, 4, v0.t292; CHECK-NEXT: vand.vi v8, v9, 1293; CHECK-NEXT: vmsne.vi v0, v8, 0294; CHECK-NEXT: ret295;296; ZVE32F-LABEL: buildvec_mask_nonconst_v8i1_2:297; ZVE32F: # %bb.0:298; ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, mu299; ZVE32F-NEXT: vmv.v.x v8, a0300; ZVE32F-NEXT: vslide1down.vx v9, v8, a3301; ZVE32F-NEXT: li a3, 1302; ZVE32F-NEXT: vmv.v.i v0, 15303; ZVE32F-NEXT: vslide1down.vx v8, v8, a0304; ZVE32F-NEXT: vslide1down.vx v9, v9, zero305; ZVE32F-NEXT: vslide1down.vx v8, v8, a3306; ZVE32F-NEXT: vslide1down.vx v9, v9, a2307; ZVE32F-NEXT: vslide1down.vx v8, v8, a1308; ZVE32F-NEXT: vslidedown.vi v9, v8, 4, v0.t309; ZVE32F-NEXT: vand.vi v8, v9, 1310; ZVE32F-NEXT: vmsne.vi v0, v8, 0311; ZVE32F-NEXT: ret312 %1 = insertelement <8 x i1> poison, i1 %x, i32 0313 %2 = insertelement <8 x i1> %1, i1 %x, i32 1314 %3 = insertelement <8 x i1> %2, i1 1, i32 2315 %4 = insertelement <8 x i1> %3, i1 %y, i32 3316 %5 = insertelement <8 x i1> %4, i1 %x, i32 4317 %6 = insertelement <8 x i1> %5, i1 %w, i32 5318 %7 = insertelement <8 x i1> %6, i1 0, i32 6319 %8 = insertelement <8 x i1> %7, i1 %z, i32 7320 ret <8 x i1> %8321}322 323define <8 x i1> @buildvec_mask_optsize_nonconst_v8i1_2(i1 %x, i1 %y, i1 %z, i1 %w) optsize {324; CHECK-LABEL: buildvec_mask_optsize_nonconst_v8i1_2:325; CHECK: # %bb.0:326; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu327; CHECK-NEXT: vmv.v.x v8, a0328; CHECK-NEXT: vslide1down.vx v9, v8, a3329; CHECK-NEXT: li a3, 1330; CHECK-NEXT: vmv.v.i v0, 15331; CHECK-NEXT: vslide1down.vx v8, v8, a0332; CHECK-NEXT: vslide1down.vx v9, v9, zero333; CHECK-NEXT: vslide1down.vx v8, v8, a3334; CHECK-NEXT: vslide1down.vx v9, v9, a2335; CHECK-NEXT: vslide1down.vx v8, v8, a1336; CHECK-NEXT: vslidedown.vi v9, v8, 4, v0.t337; CHECK-NEXT: vand.vi v8, v9, 1338; CHECK-NEXT: vmsne.vi v0, v8, 0339; CHECK-NEXT: ret340;341; ZVE32F-LABEL: buildvec_mask_optsize_nonconst_v8i1_2:342; ZVE32F: # %bb.0:343; ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, mu344; ZVE32F-NEXT: vmv.v.x v8, a0345; ZVE32F-NEXT: vslide1down.vx v9, v8, a3346; ZVE32F-NEXT: li a3, 1347; ZVE32F-NEXT: vmv.v.i v0, 15348; ZVE32F-NEXT: vslide1down.vx v8, v8, a0349; ZVE32F-NEXT: vslide1down.vx v9, v9, zero350; ZVE32F-NEXT: vslide1down.vx v8, v8, a3351; ZVE32F-NEXT: vslide1down.vx v9, v9, a2352; ZVE32F-NEXT: vslide1down.vx v8, v8, a1353; ZVE32F-NEXT: vslidedown.vi v9, v8, 4, v0.t354; ZVE32F-NEXT: vand.vi v8, v9, 1355; ZVE32F-NEXT: vmsne.vi v0, v8, 0356; ZVE32F-NEXT: ret357 %1 = insertelement <8 x i1> poison, i1 %x, i32 0358 %2 = insertelement <8 x i1> %1, i1 %x, i32 1359 %3 = insertelement <8 x i1> %2, i1 1, i32 2360 %4 = insertelement <8 x i1> %3, i1 %y, i32 3361 %5 = insertelement <8 x i1> %4, i1 %x, i32 4362 %6 = insertelement <8 x i1> %5, i1 %w, i32 5363 %7 = insertelement <8 x i1> %6, i1 0, i32 6364 %8 = insertelement <8 x i1> %7, i1 %z, i32 7365 ret <8 x i1> %8366}367 368define <8 x i1> @buildvec_mask_optsize_nonconst_v8i1(i1 %x, i1 %y) optsize {369; CHECK-LABEL: buildvec_mask_optsize_nonconst_v8i1:370; CHECK: # %bb.0:371; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu372; CHECK-NEXT: vmv.v.x v8, a0373; CHECK-NEXT: vmv.v.i v0, 15374; CHECK-NEXT: vslide1down.vx v9, v8, a1375; CHECK-NEXT: vslide1down.vx v8, v8, a0376; CHECK-NEXT: vslide1down.vx v9, v9, a1377; CHECK-NEXT: vslide1down.vx v8, v8, a1378; CHECK-NEXT: vslide1down.vx v9, v9, a1379; CHECK-NEXT: vslide1down.vx v8, v8, a1380; CHECK-NEXT: vslidedown.vi v9, v8, 4, v0.t381; CHECK-NEXT: vand.vi v8, v9, 1382; CHECK-NEXT: vmsne.vi v0, v8, 0383; CHECK-NEXT: ret384;385; ZVE32F-LABEL: buildvec_mask_optsize_nonconst_v8i1:386; ZVE32F: # %bb.0:387; ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, mu388; ZVE32F-NEXT: vmv.v.x v8, a0389; ZVE32F-NEXT: vmv.v.i v0, 15390; ZVE32F-NEXT: vslide1down.vx v9, v8, a1391; ZVE32F-NEXT: vslide1down.vx v8, v8, a0392; ZVE32F-NEXT: vslide1down.vx v9, v9, a1393; ZVE32F-NEXT: vslide1down.vx v8, v8, a1394; ZVE32F-NEXT: vslide1down.vx v9, v9, a1395; ZVE32F-NEXT: vslide1down.vx v8, v8, a1396; ZVE32F-NEXT: vslidedown.vi v9, v8, 4, v0.t397; ZVE32F-NEXT: vand.vi v8, v9, 1398; ZVE32F-NEXT: vmsne.vi v0, v8, 0399; ZVE32F-NEXT: ret400 %1 = insertelement <8 x i1> poison, i1 %x, i32 0401 %2 = insertelement <8 x i1> %1, i1 %x, i32 1402 %3 = insertelement <8 x i1> %2, i1 %y, i32 2403 %4 = insertelement <8 x i1> %3, i1 %y, i32 3404 %5 = insertelement <8 x i1> %4, i1 %x, i32 4405 %6 = insertelement <8 x i1> %5, i1 %y, i32 5406 %7 = insertelement <8 x i1> %6, i1 %y, i32 6407 %8 = insertelement <8 x i1> %7, i1 %y, i32 7408 ret <8 x i1> %8409}410 411define <10 x i1> @buildvec_mask_v10i1() {412; CHECK-LABEL: buildvec_mask_v10i1:413; CHECK: # %bb.0:414; CHECK-NEXT: li a0, 949415; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma416; CHECK-NEXT: vmv.s.x v0, a0417; CHECK-NEXT: ret418;419; ZVE32F-LABEL: buildvec_mask_v10i1:420; ZVE32F: # %bb.0:421; ZVE32F-NEXT: li a0, 949422; ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma423; ZVE32F-NEXT: vmv.s.x v0, a0424; ZVE32F-NEXT: ret425 ret <10 x i1> <i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 1>426}427 428define <16 x i1> @buildvec_mask_v16i1() {429; CHECK-LABEL: buildvec_mask_v16i1:430; CHECK: # %bb.0:431; CHECK-NEXT: lui a0, 11432; CHECK-NEXT: addi a0, a0, 1718433; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma434; CHECK-NEXT: vmv.s.x v0, a0435; CHECK-NEXT: ret436;437; ZVE32F-LABEL: buildvec_mask_v16i1:438; ZVE32F: # %bb.0:439; ZVE32F-NEXT: lui a0, 11440; ZVE32F-NEXT: addi a0, a0, 1718441; ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma442; ZVE32F-NEXT: vmv.s.x v0, a0443; ZVE32F-NEXT: ret444 ret <16 x i1> <i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1>445}446 447define <16 x i1> @buildvec_mask_v16i1_undefs() {448; CHECK-LABEL: buildvec_mask_v16i1_undefs:449; CHECK: # %bb.0:450; CHECK-NEXT: li a0, 1722451; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma452; CHECK-NEXT: vmv.s.x v0, a0453; CHECK-NEXT: ret454;455; ZVE32F-LABEL: buildvec_mask_v16i1_undefs:456; ZVE32F: # %bb.0:457; ZVE32F-NEXT: li a0, 1722458; ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma459; ZVE32F-NEXT: vmv.s.x v0, a0460; ZVE32F-NEXT: ret461 ret <16 x i1> <i1 poison, i1 1, i1 poison, i1 1, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 poison, i1 poison, i1 poison, i1 poison, i1 poison>462}463 464define <32 x i1> @buildvec_mask_v32i1() {465; CHECK-LABEL: buildvec_mask_v32i1:466; CHECK: # %bb.0:467; CHECK-NEXT: lui a0, 748384468; CHECK-NEXT: addi a0, a0, 1776469; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma470; CHECK-NEXT: vmv.s.x v0, a0471; CHECK-NEXT: ret472;473; ZVE32F-LABEL: buildvec_mask_v32i1:474; ZVE32F: # %bb.0:475; ZVE32F-NEXT: lui a0, 748384476; ZVE32F-NEXT: addi a0, a0, 1776477; ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma478; ZVE32F-NEXT: vmv.s.x v0, a0479; ZVE32F-NEXT: ret480 ret <32 x i1> <i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1>481}482 483define <64 x i1> @buildvec_mask_v64i1() {484; RV32-LABEL: buildvec_mask_v64i1:485; RV32: # %bb.0:486; RV32-NEXT: lui a0, 748388487; RV32-NEXT: addi a0, a0, -1793488; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma489; RV32-NEXT: vmv.v.x v0, a0490; RV32-NEXT: lui a0, 748384491; RV32-NEXT: addi a0, a0, 1776492; RV32-NEXT: vsetvli zero, zero, e32, mf2, tu, ma493; RV32-NEXT: vmv.s.x v0, a0494; RV32-NEXT: ret495;496; RV64-LABEL: buildvec_mask_v64i1:497; RV64: # %bb.0:498; RV64-NEXT: lui a0, %hi(.LCPI19_0)499; RV64-NEXT: addi a0, a0, %lo(.LCPI19_0)500; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma501; RV64-NEXT: vle64.v v0, (a0)502; RV64-NEXT: ret503;504; ZVE32F-LABEL: buildvec_mask_v64i1:505; ZVE32F: # %bb.0:506; ZVE32F-NEXT: lui a0, 748388507; ZVE32F-NEXT: addi a0, a0, -1793508; ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma509; ZVE32F-NEXT: vmv.v.x v0, a0510; ZVE32F-NEXT: lui a0, 748384511; ZVE32F-NEXT: addi a0, a0, 1776512; ZVE32F-NEXT: vsetvli zero, zero, e32, m1, tu, ma513; ZVE32F-NEXT: vmv.s.x v0, a0514; ZVE32F-NEXT: ret515 ret <64 x i1> <i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1>516}517 518define <128 x i1> @buildvec_mask_v128i1() {519; RV32-LABEL: buildvec_mask_v128i1:520; RV32: # %bb.0:521; RV32-NEXT: lui a0, %hi(.LCPI20_0)522; RV32-NEXT: addi a0, a0, %lo(.LCPI20_0)523; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma524; RV32-NEXT: vle32.v v0, (a0)525; RV32-NEXT: ret526;527; RV64-LABEL: buildvec_mask_v128i1:528; RV64: # %bb.0:529; RV64-NEXT: lui a0, %hi(.LCPI20_0)530; RV64-NEXT: ld a0, %lo(.LCPI20_0)(a0)531; RV64-NEXT: lui a1, %hi(.LCPI20_1)532; RV64-NEXT: ld a1, %lo(.LCPI20_1)(a1)533; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma534; RV64-NEXT: vmv.v.x v0, a0535; RV64-NEXT: vsetvli zero, zero, e64, m1, tu, ma536; RV64-NEXT: vmv.s.x v0, a1537; RV64-NEXT: ret538;539; ZVE32F-LABEL: buildvec_mask_v128i1:540; ZVE32F: # %bb.0:541; ZVE32F-NEXT: lui a0, %hi(.LCPI20_0)542; ZVE32F-NEXT: addi a0, a0, %lo(.LCPI20_0)543; ZVE32F-NEXT: vsetivli zero, 4, e32, m1, ta, ma544; ZVE32F-NEXT: vle32.v v0, (a0)545; ZVE32F-NEXT: ret546 ret <128 x i1> <i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 0, i1 1, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 1, i1 1>547}548 549define <128 x i1> @buildvec_mask_optsize_v128i1() optsize {550; CHECK-LABEL: buildvec_mask_optsize_v128i1:551; CHECK: # %bb.0:552; CHECK-NEXT: li a0, 128553; CHECK-NEXT: lui a1, %hi(.LCPI21_0)554; CHECK-NEXT: addi a1, a1, %lo(.LCPI21_0)555; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma556; CHECK-NEXT: vlm.v v0, (a1)557; CHECK-NEXT: ret558;559; ZVE32F-LABEL: buildvec_mask_optsize_v128i1:560; ZVE32F: # %bb.0:561; ZVE32F-NEXT: li a0, 128562; ZVE32F-NEXT: lui a1, %hi(.LCPI21_0)563; ZVE32F-NEXT: addi a1, a1, %lo(.LCPI21_0)564; ZVE32F-NEXT: vsetvli zero, a0, e8, m8, ta, ma565; ZVE32F-NEXT: vlm.v v0, (a1)566; ZVE32F-NEXT: ret567 ret <128 x i1> <i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 0, i1 1, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 1, i1 1>568}569 570define <4 x i1> @buildvec_mask_splat(i1 %e1) {571; CHECK-LABEL: buildvec_mask_splat:572; CHECK: # %bb.0:573; CHECK-NEXT: andi a0, a0, 1574; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma575; CHECK-NEXT: vmv.v.x v8, a0576; CHECK-NEXT: vmsne.vi v0, v8, 0577; CHECK-NEXT: ret578;579; ZVE32F-LABEL: buildvec_mask_splat:580; ZVE32F: # %bb.0:581; ZVE32F-NEXT: andi a0, a0, 1582; ZVE32F-NEXT: vsetivli zero, 4, e8, mf4, ta, ma583; ZVE32F-NEXT: vmv.v.x v8, a0584; ZVE32F-NEXT: vmsne.vi v0, v8, 0585; ZVE32F-NEXT: ret586 %v1 = insertelement <4 x i1> poison, i1 %e1, i32 0587 %v2 = insertelement <4 x i1> %v1, i1 %e1, i32 1588 %v3 = insertelement <4 x i1> %v2, i1 %e1, i32 2589 %v4 = insertelement <4 x i1> %v3, i1 %e1, i32 3590 ret <4 x i1> %v4591}592