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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zvfh,+zfbfmin,+zvfbfmin,+v -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32V,RV32V-ZVFH4; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zvfh,+zfbfmin,+zvfbfmin,+v -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64V,RV64V-ZVFH6; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v -target-abi=ilp32d \7; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32V,RV32V-ZVFHMIN8; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v -target-abi=lp64d \9; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64V,RV64V-ZVFHMIN10 11; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zvfh,+zfbfmin,+zvfbfmin,+zve32f,+zvl128b -target-abi=ilp32d \12; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32ZVE32F,RV32ZVE32F-ZVFH13; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zvfh,+zfbfmin,+zvfbfmin,+zve32f,+zvl128b -target-abi=lp64d \14; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64ZVE32F,RV64ZVE32F-ZVFH15; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+zve32f,+zvl128b -target-abi=ilp32d \16; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32ZVE32F,RV32ZVE32F-ZVFHMIN17; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+zve32f,+zvl128b -target-abi=lp64d \18; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64ZVE32F,RV64ZVE32F-ZVFHMIN19 20define <1 x i8> @mgather_v1i8(<1 x ptr> %ptrs, <1 x i1> %m, <1 x i8> %passthru) {21; RV32V-LABEL: mgather_v1i8:22; RV32V: # %bb.0:23; RV32V-NEXT: vsetivli zero, 1, e8, mf8, ta, mu24; RV32V-NEXT: vluxei32.v v9, (zero), v8, v0.t25; RV32V-NEXT: vmv1r.v v8, v926; RV32V-NEXT: ret27;28; RV64V-LABEL: mgather_v1i8:29; RV64V: # %bb.0:30; RV64V-NEXT: vsetivli zero, 1, e8, mf8, ta, mu31; RV64V-NEXT: vluxei64.v v9, (zero), v8, v0.t32; RV64V-NEXT: vmv1r.v v8, v933; RV64V-NEXT: ret34;35; RV32ZVE32F-LABEL: mgather_v1i8:36; RV32ZVE32F: # %bb.0:37; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, mu38; RV32ZVE32F-NEXT: vluxei32.v v9, (zero), v8, v0.t39; RV32ZVE32F-NEXT: vmv1r.v v8, v940; RV32ZVE32F-NEXT: ret41;42; RV64ZVE32F-LABEL: mgather_v1i8:43; RV64ZVE32F: # %bb.0:44; RV64ZVE32F-NEXT: vsetvli a1, zero, e8, mf4, ta, ma45; RV64ZVE32F-NEXT: vfirst.m a1, v046; RV64ZVE32F-NEXT: bnez a1, .LBB0_247; RV64ZVE32F-NEXT: # %bb.1: # %cond.load48; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma49; RV64ZVE32F-NEXT: vle8.v v8, (a0)50; RV64ZVE32F-NEXT: .LBB0_2: # %else51; RV64ZVE32F-NEXT: ret52 %v = call <1 x i8> @llvm.masked.gather.v1i8.v1p0(<1 x ptr> %ptrs, i32 1, <1 x i1> %m, <1 x i8> %passthru)53 ret <1 x i8> %v54}55 56define <2 x i8> @mgather_v2i8(<2 x ptr> %ptrs, <2 x i1> %m, <2 x i8> %passthru) {57; RV32V-LABEL: mgather_v2i8:58; RV32V: # %bb.0:59; RV32V-NEXT: vsetivli zero, 2, e8, mf8, ta, mu60; RV32V-NEXT: vluxei32.v v9, (zero), v8, v0.t61; RV32V-NEXT: vmv1r.v v8, v962; RV32V-NEXT: ret63;64; RV64V-LABEL: mgather_v2i8:65; RV64V: # %bb.0:66; RV64V-NEXT: vsetivli zero, 2, e8, mf8, ta, mu67; RV64V-NEXT: vluxei64.v v9, (zero), v8, v0.t68; RV64V-NEXT: vmv1r.v v8, v969; RV64V-NEXT: ret70;71; RV32ZVE32F-LABEL: mgather_v2i8:72; RV32ZVE32F: # %bb.0:73; RV32ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, mu74; RV32ZVE32F-NEXT: vluxei32.v v9, (zero), v8, v0.t75; RV32ZVE32F-NEXT: vmv1r.v v8, v976; RV32ZVE32F-NEXT: ret77;78; RV64ZVE32F-LABEL: mgather_v2i8:79; RV64ZVE32F: # %bb.0:80; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma81; RV64ZVE32F-NEXT: vmv.x.s a2, v082; RV64ZVE32F-NEXT: andi a3, a2, 183; RV64ZVE32F-NEXT: bnez a3, .LBB1_384; RV64ZVE32F-NEXT: # %bb.1: # %else85; RV64ZVE32F-NEXT: andi a2, a2, 286; RV64ZVE32F-NEXT: bnez a2, .LBB1_487; RV64ZVE32F-NEXT: .LBB1_2: # %else288; RV64ZVE32F-NEXT: ret89; RV64ZVE32F-NEXT: .LBB1_3: # %cond.load90; RV64ZVE32F-NEXT: lbu a0, 0(a0)91; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, m1, tu, ma92; RV64ZVE32F-NEXT: vmv.s.x v8, a093; RV64ZVE32F-NEXT: andi a2, a2, 294; RV64ZVE32F-NEXT: beqz a2, .LBB1_295; RV64ZVE32F-NEXT: .LBB1_4: # %cond.load196; RV64ZVE32F-NEXT: lbu a0, 0(a1)97; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, m1, ta, ma98; RV64ZVE32F-NEXT: vmv.s.x v9, a099; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma100; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1101; RV64ZVE32F-NEXT: ret102 %v = call <2 x i8> @llvm.masked.gather.v2i8.v2p0(<2 x ptr> %ptrs, i32 1, <2 x i1> %m, <2 x i8> %passthru)103 ret <2 x i8> %v104}105 106define <2 x i16> @mgather_v2i8_sextload_v2i16(<2 x ptr> %ptrs, <2 x i1> %m, <2 x i8> %passthru) {107; RV32V-LABEL: mgather_v2i8_sextload_v2i16:108; RV32V: # %bb.0:109; RV32V-NEXT: vsetivli zero, 2, e8, mf8, ta, mu110; RV32V-NEXT: vluxei32.v v9, (zero), v8, v0.t111; RV32V-NEXT: vsetvli zero, zero, e16, mf4, ta, ma112; RV32V-NEXT: vsext.vf2 v8, v9113; RV32V-NEXT: ret114;115; RV64V-LABEL: mgather_v2i8_sextload_v2i16:116; RV64V: # %bb.0:117; RV64V-NEXT: vsetivli zero, 2, e8, mf8, ta, mu118; RV64V-NEXT: vluxei64.v v9, (zero), v8, v0.t119; RV64V-NEXT: vsetvli zero, zero, e16, mf4, ta, ma120; RV64V-NEXT: vsext.vf2 v8, v9121; RV64V-NEXT: ret122;123; RV32ZVE32F-LABEL: mgather_v2i8_sextload_v2i16:124; RV32ZVE32F: # %bb.0:125; RV32ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, mu126; RV32ZVE32F-NEXT: vluxei32.v v9, (zero), v8, v0.t127; RV32ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma128; RV32ZVE32F-NEXT: vsext.vf2 v8, v9129; RV32ZVE32F-NEXT: ret130;131; RV64ZVE32F-LABEL: mgather_v2i8_sextload_v2i16:132; RV64ZVE32F: # %bb.0:133; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma134; RV64ZVE32F-NEXT: vmv.x.s a2, v0135; RV64ZVE32F-NEXT: andi a3, a2, 1136; RV64ZVE32F-NEXT: beqz a3, .LBB2_2137; RV64ZVE32F-NEXT: # %bb.1: # %cond.load138; RV64ZVE32F-NEXT: lbu a0, 0(a0)139; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, m1, tu, ma140; RV64ZVE32F-NEXT: vmv.s.x v8, a0141; RV64ZVE32F-NEXT: .LBB2_2: # %else142; RV64ZVE32F-NEXT: andi a2, a2, 2143; RV64ZVE32F-NEXT: beqz a2, .LBB2_4144; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1145; RV64ZVE32F-NEXT: lbu a0, 0(a1)146; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, m1, ta, ma147; RV64ZVE32F-NEXT: vmv.s.x v9, a0148; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma149; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1150; RV64ZVE32F-NEXT: .LBB2_4: # %else2151; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma152; RV64ZVE32F-NEXT: vsext.vf2 v9, v8153; RV64ZVE32F-NEXT: vmv1r.v v8, v9154; RV64ZVE32F-NEXT: ret155 %v = call <2 x i8> @llvm.masked.gather.v2i8.v2p0(<2 x ptr> %ptrs, i32 1, <2 x i1> %m, <2 x i8> %passthru)156 %ev = sext <2 x i8> %v to <2 x i16>157 ret <2 x i16> %ev158}159 160define <2 x i16> @mgather_v2i8_zextload_v2i16(<2 x ptr> %ptrs, <2 x i1> %m, <2 x i8> %passthru) {161; RV32V-LABEL: mgather_v2i8_zextload_v2i16:162; RV32V: # %bb.0:163; RV32V-NEXT: vsetivli zero, 2, e8, mf8, ta, mu164; RV32V-NEXT: vluxei32.v v9, (zero), v8, v0.t165; RV32V-NEXT: vsetvli zero, zero, e16, mf4, ta, ma166; RV32V-NEXT: vzext.vf2 v8, v9167; RV32V-NEXT: ret168;169; RV64V-LABEL: mgather_v2i8_zextload_v2i16:170; RV64V: # %bb.0:171; RV64V-NEXT: vsetivli zero, 2, e8, mf8, ta, mu172; RV64V-NEXT: vluxei64.v v9, (zero), v8, v0.t173; RV64V-NEXT: vsetvli zero, zero, e16, mf4, ta, ma174; RV64V-NEXT: vzext.vf2 v8, v9175; RV64V-NEXT: ret176;177; RV32ZVE32F-LABEL: mgather_v2i8_zextload_v2i16:178; RV32ZVE32F: # %bb.0:179; RV32ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, mu180; RV32ZVE32F-NEXT: vluxei32.v v9, (zero), v8, v0.t181; RV32ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma182; RV32ZVE32F-NEXT: vzext.vf2 v8, v9183; RV32ZVE32F-NEXT: ret184;185; RV64ZVE32F-LABEL: mgather_v2i8_zextload_v2i16:186; RV64ZVE32F: # %bb.0:187; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma188; RV64ZVE32F-NEXT: vmv.x.s a2, v0189; RV64ZVE32F-NEXT: andi a3, a2, 1190; RV64ZVE32F-NEXT: beqz a3, .LBB3_2191; RV64ZVE32F-NEXT: # %bb.1: # %cond.load192; RV64ZVE32F-NEXT: lbu a0, 0(a0)193; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, m1, tu, ma194; RV64ZVE32F-NEXT: vmv.s.x v8, a0195; RV64ZVE32F-NEXT: .LBB3_2: # %else196; RV64ZVE32F-NEXT: andi a2, a2, 2197; RV64ZVE32F-NEXT: beqz a2, .LBB3_4198; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1199; RV64ZVE32F-NEXT: lbu a0, 0(a1)200; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, m1, ta, ma201; RV64ZVE32F-NEXT: vmv.s.x v9, a0202; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma203; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1204; RV64ZVE32F-NEXT: .LBB3_4: # %else2205; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma206; RV64ZVE32F-NEXT: vzext.vf2 v9, v8207; RV64ZVE32F-NEXT: vmv1r.v v8, v9208; RV64ZVE32F-NEXT: ret209 %v = call <2 x i8> @llvm.masked.gather.v2i8.v2p0(<2 x ptr> %ptrs, i32 1, <2 x i1> %m, <2 x i8> %passthru)210 %ev = zext <2 x i8> %v to <2 x i16>211 ret <2 x i16> %ev212}213 214define <2 x i32> @mgather_v2i8_sextload_v2i32(<2 x ptr> %ptrs, <2 x i1> %m, <2 x i8> %passthru) {215; RV32V-LABEL: mgather_v2i8_sextload_v2i32:216; RV32V: # %bb.0:217; RV32V-NEXT: vsetivli zero, 2, e8, mf8, ta, mu218; RV32V-NEXT: vluxei32.v v9, (zero), v8, v0.t219; RV32V-NEXT: vsetvli zero, zero, e32, mf2, ta, ma220; RV32V-NEXT: vsext.vf4 v8, v9221; RV32V-NEXT: ret222;223; RV64V-LABEL: mgather_v2i8_sextload_v2i32:224; RV64V: # %bb.0:225; RV64V-NEXT: vsetivli zero, 2, e8, mf8, ta, mu226; RV64V-NEXT: vluxei64.v v9, (zero), v8, v0.t227; RV64V-NEXT: vsetvli zero, zero, e32, mf2, ta, ma228; RV64V-NEXT: vsext.vf4 v8, v9229; RV64V-NEXT: ret230;231; RV32ZVE32F-LABEL: mgather_v2i8_sextload_v2i32:232; RV32ZVE32F: # %bb.0:233; RV32ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, mu234; RV32ZVE32F-NEXT: vluxei32.v v9, (zero), v8, v0.t235; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma236; RV32ZVE32F-NEXT: vsext.vf4 v8, v9237; RV32ZVE32F-NEXT: ret238;239; RV64ZVE32F-LABEL: mgather_v2i8_sextload_v2i32:240; RV64ZVE32F: # %bb.0:241; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma242; RV64ZVE32F-NEXT: vmv.x.s a2, v0243; RV64ZVE32F-NEXT: andi a3, a2, 1244; RV64ZVE32F-NEXT: beqz a3, .LBB4_2245; RV64ZVE32F-NEXT: # %bb.1: # %cond.load246; RV64ZVE32F-NEXT: lbu a0, 0(a0)247; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, m1, tu, ma248; RV64ZVE32F-NEXT: vmv.s.x v8, a0249; RV64ZVE32F-NEXT: .LBB4_2: # %else250; RV64ZVE32F-NEXT: andi a2, a2, 2251; RV64ZVE32F-NEXT: beqz a2, .LBB4_4252; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1253; RV64ZVE32F-NEXT: lbu a0, 0(a1)254; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, m1, ta, ma255; RV64ZVE32F-NEXT: vmv.s.x v9, a0256; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma257; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1258; RV64ZVE32F-NEXT: .LBB4_4: # %else2259; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma260; RV64ZVE32F-NEXT: vsext.vf4 v9, v8261; RV64ZVE32F-NEXT: vmv.v.v v8, v9262; RV64ZVE32F-NEXT: ret263 %v = call <2 x i8> @llvm.masked.gather.v2i8.v2p0(<2 x ptr> %ptrs, i32 1, <2 x i1> %m, <2 x i8> %passthru)264 %ev = sext <2 x i8> %v to <2 x i32>265 ret <2 x i32> %ev266}267 268define <2 x i32> @mgather_v2i8_zextload_v2i32(<2 x ptr> %ptrs, <2 x i1> %m, <2 x i8> %passthru) {269; RV32V-LABEL: mgather_v2i8_zextload_v2i32:270; RV32V: # %bb.0:271; RV32V-NEXT: vsetivli zero, 2, e8, mf8, ta, mu272; RV32V-NEXT: vluxei32.v v9, (zero), v8, v0.t273; RV32V-NEXT: vsetvli zero, zero, e32, mf2, ta, ma274; RV32V-NEXT: vzext.vf4 v8, v9275; RV32V-NEXT: ret276;277; RV64V-LABEL: mgather_v2i8_zextload_v2i32:278; RV64V: # %bb.0:279; RV64V-NEXT: vsetivli zero, 2, e8, mf8, ta, mu280; RV64V-NEXT: vluxei64.v v9, (zero), v8, v0.t281; RV64V-NEXT: vsetvli zero, zero, e32, mf2, ta, ma282; RV64V-NEXT: vzext.vf4 v8, v9283; RV64V-NEXT: ret284;285; RV32ZVE32F-LABEL: mgather_v2i8_zextload_v2i32:286; RV32ZVE32F: # %bb.0:287; RV32ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, mu288; RV32ZVE32F-NEXT: vluxei32.v v9, (zero), v8, v0.t289; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma290; RV32ZVE32F-NEXT: vzext.vf4 v8, v9291; RV32ZVE32F-NEXT: ret292;293; RV64ZVE32F-LABEL: mgather_v2i8_zextload_v2i32:294; RV64ZVE32F: # %bb.0:295; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma296; RV64ZVE32F-NEXT: vmv.x.s a2, v0297; RV64ZVE32F-NEXT: andi a3, a2, 1298; RV64ZVE32F-NEXT: beqz a3, .LBB5_2299; RV64ZVE32F-NEXT: # %bb.1: # %cond.load300; RV64ZVE32F-NEXT: lbu a0, 0(a0)301; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, m1, tu, ma302; RV64ZVE32F-NEXT: vmv.s.x v8, a0303; RV64ZVE32F-NEXT: .LBB5_2: # %else304; RV64ZVE32F-NEXT: andi a2, a2, 2305; RV64ZVE32F-NEXT: beqz a2, .LBB5_4306; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1307; RV64ZVE32F-NEXT: lbu a0, 0(a1)308; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, m1, ta, ma309; RV64ZVE32F-NEXT: vmv.s.x v9, a0310; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma311; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1312; RV64ZVE32F-NEXT: .LBB5_4: # %else2313; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma314; RV64ZVE32F-NEXT: vzext.vf4 v9, v8315; RV64ZVE32F-NEXT: vmv.v.v v8, v9316; RV64ZVE32F-NEXT: ret317 %v = call <2 x i8> @llvm.masked.gather.v2i8.v2p0(<2 x ptr> %ptrs, i32 1, <2 x i1> %m, <2 x i8> %passthru)318 %ev = zext <2 x i8> %v to <2 x i32>319 ret <2 x i32> %ev320}321 322define <2 x i64> @mgather_v2i8_sextload_v2i64(<2 x ptr> %ptrs, <2 x i1> %m, <2 x i8> %passthru) {323; RV32V-LABEL: mgather_v2i8_sextload_v2i64:324; RV32V: # %bb.0:325; RV32V-NEXT: vsetivli zero, 2, e8, mf8, ta, mu326; RV32V-NEXT: vluxei32.v v9, (zero), v8, v0.t327; RV32V-NEXT: vsetvli zero, zero, e64, m1, ta, ma328; RV32V-NEXT: vsext.vf8 v8, v9329; RV32V-NEXT: ret330;331; RV64V-LABEL: mgather_v2i8_sextload_v2i64:332; RV64V: # %bb.0:333; RV64V-NEXT: vsetivli zero, 2, e8, mf8, ta, mu334; RV64V-NEXT: vluxei64.v v9, (zero), v8, v0.t335; RV64V-NEXT: vsetvli zero, zero, e64, m1, ta, ma336; RV64V-NEXT: vsext.vf8 v8, v9337; RV64V-NEXT: ret338;339; RV32ZVE32F-LABEL: mgather_v2i8_sextload_v2i64:340; RV32ZVE32F: # %bb.0:341; RV32ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, mu342; RV32ZVE32F-NEXT: vluxei32.v v9, (zero), v8, v0.t343; RV32ZVE32F-NEXT: vslidedown.vi v8, v9, 1344; RV32ZVE32F-NEXT: vmv.x.s a1, v9345; RV32ZVE32F-NEXT: vmv.x.s a2, v8346; RV32ZVE32F-NEXT: srai a3, a1, 31347; RV32ZVE32F-NEXT: srai a4, a2, 31348; RV32ZVE32F-NEXT: sw a1, 0(a0)349; RV32ZVE32F-NEXT: sw a3, 4(a0)350; RV32ZVE32F-NEXT: sw a2, 8(a0)351; RV32ZVE32F-NEXT: sw a4, 12(a0)352; RV32ZVE32F-NEXT: ret353;354; RV64ZVE32F-LABEL: mgather_v2i8_sextload_v2i64:355; RV64ZVE32F: # %bb.0:356; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma357; RV64ZVE32F-NEXT: vmv.x.s a2, v0358; RV64ZVE32F-NEXT: andi a3, a2, 1359; RV64ZVE32F-NEXT: beqz a3, .LBB6_2360; RV64ZVE32F-NEXT: # %bb.1: # %cond.load361; RV64ZVE32F-NEXT: lbu a0, 0(a0)362; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, m1, tu, ma363; RV64ZVE32F-NEXT: vmv.s.x v8, a0364; RV64ZVE32F-NEXT: .LBB6_2: # %else365; RV64ZVE32F-NEXT: andi a2, a2, 2366; RV64ZVE32F-NEXT: beqz a2, .LBB6_4367; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1368; RV64ZVE32F-NEXT: lbu a0, 0(a1)369; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, m1, ta, ma370; RV64ZVE32F-NEXT: vmv.s.x v9, a0371; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma372; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1373; RV64ZVE32F-NEXT: .LBB6_4: # %else2374; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma375; RV64ZVE32F-NEXT: vmv.x.s a0, v8376; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1377; RV64ZVE32F-NEXT: vmv.x.s a1, v8378; RV64ZVE32F-NEXT: ret379 %v = call <2 x i8> @llvm.masked.gather.v2i8.v2p0(<2 x ptr> %ptrs, i32 1, <2 x i1> %m, <2 x i8> %passthru)380 %ev = sext <2 x i8> %v to <2 x i64>381 ret <2 x i64> %ev382}383 384define <2 x i64> @mgather_v2i8_zextload_v2i64(<2 x ptr> %ptrs, <2 x i1> %m, <2 x i8> %passthru) {385; RV32V-LABEL: mgather_v2i8_zextload_v2i64:386; RV32V: # %bb.0:387; RV32V-NEXT: vsetivli zero, 2, e8, mf8, ta, mu388; RV32V-NEXT: vluxei32.v v9, (zero), v8, v0.t389; RV32V-NEXT: vsetvli zero, zero, e64, m1, ta, ma390; RV32V-NEXT: vzext.vf8 v8, v9391; RV32V-NEXT: ret392;393; RV64V-LABEL: mgather_v2i8_zextload_v2i64:394; RV64V: # %bb.0:395; RV64V-NEXT: vsetivli zero, 2, e8, mf8, ta, mu396; RV64V-NEXT: vluxei64.v v9, (zero), v8, v0.t397; RV64V-NEXT: vsetvli zero, zero, e64, m1, ta, ma398; RV64V-NEXT: vzext.vf8 v8, v9399; RV64V-NEXT: ret400;401; RV32ZVE32F-LABEL: mgather_v2i8_zextload_v2i64:402; RV32ZVE32F: # %bb.0:403; RV32ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, mu404; RV32ZVE32F-NEXT: vluxei32.v v9, (zero), v8, v0.t405; RV32ZVE32F-NEXT: sw zero, 12(a0)406; RV32ZVE32F-NEXT: vslidedown.vi v8, v9, 1407; RV32ZVE32F-NEXT: vmv.x.s a1, v9408; RV32ZVE32F-NEXT: vmv.x.s a2, v8409; RV32ZVE32F-NEXT: zext.b a1, a1410; RV32ZVE32F-NEXT: zext.b a2, a2411; RV32ZVE32F-NEXT: sw a1, 0(a0)412; RV32ZVE32F-NEXT: sw zero, 4(a0)413; RV32ZVE32F-NEXT: sw a2, 8(a0)414; RV32ZVE32F-NEXT: ret415;416; RV64ZVE32F-LABEL: mgather_v2i8_zextload_v2i64:417; RV64ZVE32F: # %bb.0:418; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma419; RV64ZVE32F-NEXT: vmv.x.s a2, v0420; RV64ZVE32F-NEXT: andi a3, a2, 1421; RV64ZVE32F-NEXT: beqz a3, .LBB7_2422; RV64ZVE32F-NEXT: # %bb.1: # %cond.load423; RV64ZVE32F-NEXT: lbu a0, 0(a0)424; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, m1, tu, ma425; RV64ZVE32F-NEXT: vmv.s.x v8, a0426; RV64ZVE32F-NEXT: .LBB7_2: # %else427; RV64ZVE32F-NEXT: andi a2, a2, 2428; RV64ZVE32F-NEXT: beqz a2, .LBB7_4429; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1430; RV64ZVE32F-NEXT: lbu a0, 0(a1)431; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, m1, ta, ma432; RV64ZVE32F-NEXT: vmv.s.x v9, a0433; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma434; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1435; RV64ZVE32F-NEXT: .LBB7_4: # %else2436; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma437; RV64ZVE32F-NEXT: vmv.x.s a0, v8438; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1439; RV64ZVE32F-NEXT: zext.b a0, a0440; RV64ZVE32F-NEXT: vmv.x.s a1, v8441; RV64ZVE32F-NEXT: zext.b a1, a1442; RV64ZVE32F-NEXT: ret443 %v = call <2 x i8> @llvm.masked.gather.v2i8.v2p0(<2 x ptr> %ptrs, i32 1, <2 x i1> %m, <2 x i8> %passthru)444 %ev = zext <2 x i8> %v to <2 x i64>445 ret <2 x i64> %ev446}447 448define <4 x i8> @mgather_v4i8(<4 x ptr> %ptrs, <4 x i1> %m, <4 x i8> %passthru) {449; RV32-LABEL: mgather_v4i8:450; RV32: # %bb.0:451; RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, mu452; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t453; RV32-NEXT: vmv1r.v v8, v9454; RV32-NEXT: ret455;456; RV64V-LABEL: mgather_v4i8:457; RV64V: # %bb.0:458; RV64V-NEXT: vsetivli zero, 4, e8, mf4, ta, mu459; RV64V-NEXT: vluxei64.v v10, (zero), v8, v0.t460; RV64V-NEXT: vmv1r.v v8, v10461; RV64V-NEXT: ret462;463; RV64ZVE32F-LABEL: mgather_v4i8:464; RV64ZVE32F: # %bb.0:465; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma466; RV64ZVE32F-NEXT: vmv.x.s a1, v0467; RV64ZVE32F-NEXT: andi a2, a1, 1468; RV64ZVE32F-NEXT: bnez a2, .LBB8_5469; RV64ZVE32F-NEXT: # %bb.1: # %else470; RV64ZVE32F-NEXT: andi a2, a1, 2471; RV64ZVE32F-NEXT: bnez a2, .LBB8_6472; RV64ZVE32F-NEXT: .LBB8_2: # %else2473; RV64ZVE32F-NEXT: andi a2, a1, 4474; RV64ZVE32F-NEXT: bnez a2, .LBB8_7475; RV64ZVE32F-NEXT: .LBB8_3: # %else5476; RV64ZVE32F-NEXT: andi a1, a1, 8477; RV64ZVE32F-NEXT: bnez a1, .LBB8_8478; RV64ZVE32F-NEXT: .LBB8_4: # %else8479; RV64ZVE32F-NEXT: ret480; RV64ZVE32F-NEXT: .LBB8_5: # %cond.load481; RV64ZVE32F-NEXT: ld a2, 0(a0)482; RV64ZVE32F-NEXT: lbu a2, 0(a2)483; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, m1, tu, ma484; RV64ZVE32F-NEXT: vmv.s.x v8, a2485; RV64ZVE32F-NEXT: andi a2, a1, 2486; RV64ZVE32F-NEXT: beqz a2, .LBB8_2487; RV64ZVE32F-NEXT: .LBB8_6: # %cond.load1488; RV64ZVE32F-NEXT: ld a2, 8(a0)489; RV64ZVE32F-NEXT: lbu a2, 0(a2)490; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, m1, ta, ma491; RV64ZVE32F-NEXT: vmv.s.x v9, a2492; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, tu, ma493; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1494; RV64ZVE32F-NEXT: andi a2, a1, 4495; RV64ZVE32F-NEXT: beqz a2, .LBB8_3496; RV64ZVE32F-NEXT: .LBB8_7: # %cond.load4497; RV64ZVE32F-NEXT: ld a2, 16(a0)498; RV64ZVE32F-NEXT: lbu a2, 0(a2)499; RV64ZVE32F-NEXT: vsetivli zero, 3, e8, mf4, tu, ma500; RV64ZVE32F-NEXT: vmv.s.x v9, a2501; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 2502; RV64ZVE32F-NEXT: andi a1, a1, 8503; RV64ZVE32F-NEXT: beqz a1, .LBB8_4504; RV64ZVE32F-NEXT: .LBB8_8: # %cond.load7505; RV64ZVE32F-NEXT: ld a0, 24(a0)506; RV64ZVE32F-NEXT: lbu a0, 0(a0)507; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf4, ta, ma508; RV64ZVE32F-NEXT: vmv.s.x v9, a0509; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 3510; RV64ZVE32F-NEXT: ret511 %v = call <4 x i8> @llvm.masked.gather.v4i8.v4p0(<4 x ptr> %ptrs, i32 1, <4 x i1> %m, <4 x i8> %passthru)512 ret <4 x i8> %v513}514 515define <4 x i8> @mgather_truemask_v4i8(<4 x ptr> %ptrs, <4 x i8> %passthru) {516; RV32-LABEL: mgather_truemask_v4i8:517; RV32: # %bb.0:518; RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, ma519; RV32-NEXT: vluxei32.v v9, (zero), v8520; RV32-NEXT: vmv1r.v v8, v9521; RV32-NEXT: ret522;523; RV64V-LABEL: mgather_truemask_v4i8:524; RV64V: # %bb.0:525; RV64V-NEXT: vsetivli zero, 4, e8, mf4, ta, ma526; RV64V-NEXT: vluxei64.v v10, (zero), v8527; RV64V-NEXT: vmv1r.v v8, v10528; RV64V-NEXT: ret529;530; RV64ZVE32F-LABEL: mgather_truemask_v4i8:531; RV64ZVE32F: # %bb.0:532; RV64ZVE32F-NEXT: ld a1, 0(a0)533; RV64ZVE32F-NEXT: ld a2, 8(a0)534; RV64ZVE32F-NEXT: ld a3, 16(a0)535; RV64ZVE32F-NEXT: ld a0, 24(a0)536; RV64ZVE32F-NEXT: lbu a1, 0(a1)537; RV64ZVE32F-NEXT: lbu a2, 0(a2)538; RV64ZVE32F-NEXT: lbu a3, 0(a3)539; RV64ZVE32F-NEXT: lbu a0, 0(a0)540; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf4, ta, ma541; RV64ZVE32F-NEXT: vmv.v.x v8, a1542; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a2543; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a3544; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a0545; RV64ZVE32F-NEXT: ret546 %v = call <4 x i8> @llvm.masked.gather.v4i8.v4p0(<4 x ptr> %ptrs, i32 1, <4 x i1> splat (i1 1), <4 x i8> %passthru)547 ret <4 x i8> %v548}549 550define <4 x i8> @mgather_falsemask_v4i8(<4 x ptr> %ptrs, <4 x i8> %passthru) {551; RV32-LABEL: mgather_falsemask_v4i8:552; RV32: # %bb.0:553; RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma554; RV32-NEXT: vmv1r.v v8, v9555; RV32-NEXT: ret556;557; RV64V-LABEL: mgather_falsemask_v4i8:558; RV64V: # %bb.0:559; RV64V-NEXT: vsetivli zero, 1, e8, m1, ta, ma560; RV64V-NEXT: vmv1r.v v8, v10561; RV64V-NEXT: ret562;563; RV64ZVE32F-LABEL: mgather_falsemask_v4i8:564; RV64ZVE32F: # %bb.0:565; RV64ZVE32F-NEXT: ret566 %v = call <4 x i8> @llvm.masked.gather.v4i8.v4p0(<4 x ptr> %ptrs, i32 1, <4 x i1> zeroinitializer, <4 x i8> %passthru)567 ret <4 x i8> %v568}569 570define <8 x i8> @mgather_v8i8(<8 x ptr> %ptrs, <8 x i1> %m, <8 x i8> %passthru) {571; RV32-LABEL: mgather_v8i8:572; RV32: # %bb.0:573; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu574; RV32-NEXT: vluxei32.v v10, (zero), v8, v0.t575; RV32-NEXT: vmv1r.v v8, v10576; RV32-NEXT: ret577;578; RV64V-LABEL: mgather_v8i8:579; RV64V: # %bb.0:580; RV64V-NEXT: vsetivli zero, 8, e8, mf2, ta, mu581; RV64V-NEXT: vluxei64.v v12, (zero), v8, v0.t582; RV64V-NEXT: vmv1r.v v8, v12583; RV64V-NEXT: ret584;585; RV64ZVE32F-LABEL: mgather_v8i8:586; RV64ZVE32F: # %bb.0:587; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma588; RV64ZVE32F-NEXT: vmv.x.s a1, v0589; RV64ZVE32F-NEXT: andi a2, a1, 1590; RV64ZVE32F-NEXT: bnez a2, .LBB11_9591; RV64ZVE32F-NEXT: # %bb.1: # %else592; RV64ZVE32F-NEXT: andi a2, a1, 2593; RV64ZVE32F-NEXT: bnez a2, .LBB11_10594; RV64ZVE32F-NEXT: .LBB11_2: # %else2595; RV64ZVE32F-NEXT: andi a2, a1, 4596; RV64ZVE32F-NEXT: bnez a2, .LBB11_11597; RV64ZVE32F-NEXT: .LBB11_3: # %else5598; RV64ZVE32F-NEXT: andi a2, a1, 8599; RV64ZVE32F-NEXT: bnez a2, .LBB11_12600; RV64ZVE32F-NEXT: .LBB11_4: # %else8601; RV64ZVE32F-NEXT: andi a2, a1, 16602; RV64ZVE32F-NEXT: bnez a2, .LBB11_13603; RV64ZVE32F-NEXT: .LBB11_5: # %else11604; RV64ZVE32F-NEXT: andi a2, a1, 32605; RV64ZVE32F-NEXT: bnez a2, .LBB11_14606; RV64ZVE32F-NEXT: .LBB11_6: # %else14607; RV64ZVE32F-NEXT: andi a2, a1, 64608; RV64ZVE32F-NEXT: bnez a2, .LBB11_15609; RV64ZVE32F-NEXT: .LBB11_7: # %else17610; RV64ZVE32F-NEXT: andi a1, a1, -128611; RV64ZVE32F-NEXT: bnez a1, .LBB11_16612; RV64ZVE32F-NEXT: .LBB11_8: # %else20613; RV64ZVE32F-NEXT: ret614; RV64ZVE32F-NEXT: .LBB11_9: # %cond.load615; RV64ZVE32F-NEXT: ld a2, 0(a0)616; RV64ZVE32F-NEXT: lbu a2, 0(a2)617; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, m1, tu, ma618; RV64ZVE32F-NEXT: vmv.s.x v8, a2619; RV64ZVE32F-NEXT: andi a2, a1, 2620; RV64ZVE32F-NEXT: beqz a2, .LBB11_2621; RV64ZVE32F-NEXT: .LBB11_10: # %cond.load1622; RV64ZVE32F-NEXT: ld a2, 8(a0)623; RV64ZVE32F-NEXT: lbu a2, 0(a2)624; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, m1, ta, ma625; RV64ZVE32F-NEXT: vmv.s.x v9, a2626; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf2, tu, ma627; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1628; RV64ZVE32F-NEXT: andi a2, a1, 4629; RV64ZVE32F-NEXT: beqz a2, .LBB11_3630; RV64ZVE32F-NEXT: .LBB11_11: # %cond.load4631; RV64ZVE32F-NEXT: ld a2, 16(a0)632; RV64ZVE32F-NEXT: lbu a2, 0(a2)633; RV64ZVE32F-NEXT: vsetivli zero, 3, e8, mf2, tu, ma634; RV64ZVE32F-NEXT: vmv.s.x v9, a2635; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 2636; RV64ZVE32F-NEXT: andi a2, a1, 8637; RV64ZVE32F-NEXT: beqz a2, .LBB11_4638; RV64ZVE32F-NEXT: .LBB11_12: # %cond.load7639; RV64ZVE32F-NEXT: ld a2, 24(a0)640; RV64ZVE32F-NEXT: lbu a2, 0(a2)641; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, tu, ma642; RV64ZVE32F-NEXT: vmv.s.x v9, a2643; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 3644; RV64ZVE32F-NEXT: andi a2, a1, 16645; RV64ZVE32F-NEXT: beqz a2, .LBB11_5646; RV64ZVE32F-NEXT: .LBB11_13: # %cond.load10647; RV64ZVE32F-NEXT: ld a2, 32(a0)648; RV64ZVE32F-NEXT: lbu a2, 0(a2)649; RV64ZVE32F-NEXT: vsetivli zero, 5, e8, mf2, tu, ma650; RV64ZVE32F-NEXT: vmv.s.x v9, a2651; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 4652; RV64ZVE32F-NEXT: andi a2, a1, 32653; RV64ZVE32F-NEXT: beqz a2, .LBB11_6654; RV64ZVE32F-NEXT: .LBB11_14: # %cond.load13655; RV64ZVE32F-NEXT: ld a2, 40(a0)656; RV64ZVE32F-NEXT: lbu a2, 0(a2)657; RV64ZVE32F-NEXT: vsetivli zero, 6, e8, mf2, tu, ma658; RV64ZVE32F-NEXT: vmv.s.x v9, a2659; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 5660; RV64ZVE32F-NEXT: andi a2, a1, 64661; RV64ZVE32F-NEXT: beqz a2, .LBB11_7662; RV64ZVE32F-NEXT: .LBB11_15: # %cond.load16663; RV64ZVE32F-NEXT: ld a2, 48(a0)664; RV64ZVE32F-NEXT: lbu a2, 0(a2)665; RV64ZVE32F-NEXT: vsetivli zero, 7, e8, mf2, tu, ma666; RV64ZVE32F-NEXT: vmv.s.x v9, a2667; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 6668; RV64ZVE32F-NEXT: andi a1, a1, -128669; RV64ZVE32F-NEXT: beqz a1, .LBB11_8670; RV64ZVE32F-NEXT: .LBB11_16: # %cond.load19671; RV64ZVE32F-NEXT: ld a0, 56(a0)672; RV64ZVE32F-NEXT: lbu a0, 0(a0)673; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma674; RV64ZVE32F-NEXT: vmv.s.x v9, a0675; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 7676; RV64ZVE32F-NEXT: ret677 %v = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> %ptrs, i32 1, <8 x i1> %m, <8 x i8> %passthru)678 ret <8 x i8> %v679}680 681define <8 x i8> @mgather_baseidx_v8i8(ptr %base, <8 x i8> %idxs, <8 x i1> %m, <8 x i8> %passthru) {682; RV32-LABEL: mgather_baseidx_v8i8:683; RV32: # %bb.0:684; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma685; RV32-NEXT: vsext.vf4 v10, v8686; RV32-NEXT: vsetvli zero, zero, e8, mf2, ta, mu687; RV32-NEXT: vluxei32.v v9, (a0), v10, v0.t688; RV32-NEXT: vmv1r.v v8, v9689; RV32-NEXT: ret690;691; RV64V-LABEL: mgather_baseidx_v8i8:692; RV64V: # %bb.0:693; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma694; RV64V-NEXT: vsext.vf8 v12, v8695; RV64V-NEXT: vsetvli zero, zero, e8, mf2, ta, mu696; RV64V-NEXT: vluxei64.v v9, (a0), v12, v0.t697; RV64V-NEXT: vmv1r.v v8, v9698; RV64V-NEXT: ret699;700; RV64ZVE32F-LABEL: mgather_baseidx_v8i8:701; RV64ZVE32F: # %bb.0:702; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma703; RV64ZVE32F-NEXT: vmv.x.s a1, v0704; RV64ZVE32F-NEXT: andi a2, a1, 1705; RV64ZVE32F-NEXT: beqz a2, .LBB12_2706; RV64ZVE32F-NEXT: # %bb.1: # %cond.load707; RV64ZVE32F-NEXT: vmv.x.s a2, v8708; RV64ZVE32F-NEXT: add a2, a0, a2709; RV64ZVE32F-NEXT: lbu a2, 0(a2)710; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, m1, tu, ma711; RV64ZVE32F-NEXT: vmv.s.x v9, a2712; RV64ZVE32F-NEXT: .LBB12_2: # %else713; RV64ZVE32F-NEXT: andi a2, a1, 2714; RV64ZVE32F-NEXT: beqz a2, .LBB12_4715; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1716; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma717; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1718; RV64ZVE32F-NEXT: vmv.x.s a2, v10719; RV64ZVE32F-NEXT: add a2, a0, a2720; RV64ZVE32F-NEXT: lbu a2, 0(a2)721; RV64ZVE32F-NEXT: vmv.s.x v10, a2722; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf2, tu, ma723; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 1724; RV64ZVE32F-NEXT: .LBB12_4: # %else2725; RV64ZVE32F-NEXT: andi a2, a1, 4726; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma727; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2728; RV64ZVE32F-NEXT: beqz a2, .LBB12_6729; RV64ZVE32F-NEXT: # %bb.5: # %cond.load4730; RV64ZVE32F-NEXT: vmv.x.s a2, v10731; RV64ZVE32F-NEXT: add a2, a0, a2732; RV64ZVE32F-NEXT: lbu a2, 0(a2)733; RV64ZVE32F-NEXT: vmv.s.x v11, a2734; RV64ZVE32F-NEXT: vsetivli zero, 3, e8, mf2, tu, ma735; RV64ZVE32F-NEXT: vslideup.vi v9, v11, 2736; RV64ZVE32F-NEXT: .LBB12_6: # %else5737; RV64ZVE32F-NEXT: andi a2, a1, 8738; RV64ZVE32F-NEXT: beqz a2, .LBB12_8739; RV64ZVE32F-NEXT: # %bb.7: # %cond.load7740; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma741; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1742; RV64ZVE32F-NEXT: vmv.x.s a2, v10743; RV64ZVE32F-NEXT: add a2, a0, a2744; RV64ZVE32F-NEXT: lbu a2, 0(a2)745; RV64ZVE32F-NEXT: vmv.s.x v10, a2746; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, tu, ma747; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 3748; RV64ZVE32F-NEXT: .LBB12_8: # %else8749; RV64ZVE32F-NEXT: andi a2, a1, 16750; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma751; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4752; RV64ZVE32F-NEXT: beqz a2, .LBB12_10753; RV64ZVE32F-NEXT: # %bb.9: # %cond.load10754; RV64ZVE32F-NEXT: vmv.x.s a2, v8755; RV64ZVE32F-NEXT: add a2, a0, a2756; RV64ZVE32F-NEXT: lbu a2, 0(a2)757; RV64ZVE32F-NEXT: vmv.s.x v10, a2758; RV64ZVE32F-NEXT: vsetivli zero, 5, e8, mf2, tu, ma759; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 4760; RV64ZVE32F-NEXT: .LBB12_10: # %else11761; RV64ZVE32F-NEXT: andi a2, a1, 32762; RV64ZVE32F-NEXT: beqz a2, .LBB12_12763; RV64ZVE32F-NEXT: # %bb.11: # %cond.load13764; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma765; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1766; RV64ZVE32F-NEXT: vmv.x.s a2, v10767; RV64ZVE32F-NEXT: add a2, a0, a2768; RV64ZVE32F-NEXT: lbu a2, 0(a2)769; RV64ZVE32F-NEXT: vmv.s.x v10, a2770; RV64ZVE32F-NEXT: vsetivli zero, 6, e8, mf2, tu, ma771; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 5772; RV64ZVE32F-NEXT: .LBB12_12: # %else14773; RV64ZVE32F-NEXT: andi a2, a1, 64774; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma775; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2776; RV64ZVE32F-NEXT: beqz a2, .LBB12_14777; RV64ZVE32F-NEXT: # %bb.13: # %cond.load16778; RV64ZVE32F-NEXT: vmv.x.s a2, v8779; RV64ZVE32F-NEXT: add a2, a0, a2780; RV64ZVE32F-NEXT: lbu a2, 0(a2)781; RV64ZVE32F-NEXT: vmv.s.x v10, a2782; RV64ZVE32F-NEXT: vsetivli zero, 7, e8, mf2, tu, ma783; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 6784; RV64ZVE32F-NEXT: .LBB12_14: # %else17785; RV64ZVE32F-NEXT: andi a1, a1, -128786; RV64ZVE32F-NEXT: beqz a1, .LBB12_16787; RV64ZVE32F-NEXT: # %bb.15: # %cond.load19788; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma789; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1790; RV64ZVE32F-NEXT: vmv.x.s a1, v8791; RV64ZVE32F-NEXT: add a0, a0, a1792; RV64ZVE32F-NEXT: lbu a0, 0(a0)793; RV64ZVE32F-NEXT: vmv.s.x v8, a0794; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma795; RV64ZVE32F-NEXT: vslideup.vi v9, v8, 7796; RV64ZVE32F-NEXT: .LBB12_16: # %else20797; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma798; RV64ZVE32F-NEXT: vmv1r.v v8, v9799; RV64ZVE32F-NEXT: ret800 %ptrs = getelementptr inbounds i8, ptr %base, <8 x i8> %idxs801 %v = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> %ptrs, i32 1, <8 x i1> %m, <8 x i8> %passthru)802 ret <8 x i8> %v803}804 805define <1 x i16> @mgather_v1i16(<1 x ptr> %ptrs, <1 x i1> %m, <1 x i16> %passthru) {806; RV32V-LABEL: mgather_v1i16:807; RV32V: # %bb.0:808; RV32V-NEXT: vsetivli zero, 1, e16, mf4, ta, mu809; RV32V-NEXT: vluxei32.v v9, (zero), v8, v0.t810; RV32V-NEXT: vmv1r.v v8, v9811; RV32V-NEXT: ret812;813; RV64V-LABEL: mgather_v1i16:814; RV64V: # %bb.0:815; RV64V-NEXT: vsetivli zero, 1, e16, mf4, ta, mu816; RV64V-NEXT: vluxei64.v v9, (zero), v8, v0.t817; RV64V-NEXT: vmv1r.v v8, v9818; RV64V-NEXT: ret819;820; RV32ZVE32F-LABEL: mgather_v1i16:821; RV32ZVE32F: # %bb.0:822; RV32ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, mu823; RV32ZVE32F-NEXT: vluxei32.v v9, (zero), v8, v0.t824; RV32ZVE32F-NEXT: vmv1r.v v8, v9825; RV32ZVE32F-NEXT: ret826;827; RV64ZVE32F-LABEL: mgather_v1i16:828; RV64ZVE32F: # %bb.0:829; RV64ZVE32F-NEXT: vsetvli a1, zero, e8, mf4, ta, ma830; RV64ZVE32F-NEXT: vfirst.m a1, v0831; RV64ZVE32F-NEXT: bnez a1, .LBB13_2832; RV64ZVE32F-NEXT: # %bb.1: # %cond.load833; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma834; RV64ZVE32F-NEXT: vle16.v v8, (a0)835; RV64ZVE32F-NEXT: .LBB13_2: # %else836; RV64ZVE32F-NEXT: ret837 %v = call <1 x i16> @llvm.masked.gather.v1i16.v1p0(<1 x ptr> %ptrs, i32 2, <1 x i1> %m, <1 x i16> %passthru)838 ret <1 x i16> %v839}840 841define <2 x i16> @mgather_v2i16(<2 x ptr> %ptrs, <2 x i1> %m, <2 x i16> %passthru) {842; RV32V-LABEL: mgather_v2i16:843; RV32V: # %bb.0:844; RV32V-NEXT: vsetivli zero, 2, e16, mf4, ta, mu845; RV32V-NEXT: vluxei32.v v9, (zero), v8, v0.t846; RV32V-NEXT: vmv1r.v v8, v9847; RV32V-NEXT: ret848;849; RV64V-LABEL: mgather_v2i16:850; RV64V: # %bb.0:851; RV64V-NEXT: vsetivli zero, 2, e16, mf4, ta, mu852; RV64V-NEXT: vluxei64.v v9, (zero), v8, v0.t853; RV64V-NEXT: vmv1r.v v8, v9854; RV64V-NEXT: ret855;856; RV32ZVE32F-LABEL: mgather_v2i16:857; RV32ZVE32F: # %bb.0:858; RV32ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, mu859; RV32ZVE32F-NEXT: vluxei32.v v9, (zero), v8, v0.t860; RV32ZVE32F-NEXT: vmv1r.v v8, v9861; RV32ZVE32F-NEXT: ret862;863; RV64ZVE32F-LABEL: mgather_v2i16:864; RV64ZVE32F: # %bb.0:865; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma866; RV64ZVE32F-NEXT: vmv.x.s a2, v0867; RV64ZVE32F-NEXT: andi a3, a2, 1868; RV64ZVE32F-NEXT: bnez a3, .LBB14_3869; RV64ZVE32F-NEXT: # %bb.1: # %else870; RV64ZVE32F-NEXT: andi a2, a2, 2871; RV64ZVE32F-NEXT: bnez a2, .LBB14_4872; RV64ZVE32F-NEXT: .LBB14_2: # %else2873; RV64ZVE32F-NEXT: ret874; RV64ZVE32F-NEXT: .LBB14_3: # %cond.load875; RV64ZVE32F-NEXT: lh a0, 0(a0)876; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, tu, ma877; RV64ZVE32F-NEXT: vmv.s.x v8, a0878; RV64ZVE32F-NEXT: andi a2, a2, 2879; RV64ZVE32F-NEXT: beqz a2, .LBB14_2880; RV64ZVE32F-NEXT: .LBB14_4: # %cond.load1881; RV64ZVE32F-NEXT: lh a0, 0(a1)882; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma883; RV64ZVE32F-NEXT: vmv.s.x v9, a0884; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma885; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1886; RV64ZVE32F-NEXT: ret887 %v = call <2 x i16> @llvm.masked.gather.v2i16.v2p0(<2 x ptr> %ptrs, i32 2, <2 x i1> %m, <2 x i16> %passthru)888 ret <2 x i16> %v889}890 891define <2 x i32> @mgather_v2i16_sextload_v2i32(<2 x ptr> %ptrs, <2 x i1> %m, <2 x i16> %passthru) {892; RV32V-LABEL: mgather_v2i16_sextload_v2i32:893; RV32V: # %bb.0:894; RV32V-NEXT: vsetivli zero, 2, e16, mf4, ta, mu895; RV32V-NEXT: vluxei32.v v9, (zero), v8, v0.t896; RV32V-NEXT: vsetvli zero, zero, e32, mf2, ta, ma897; RV32V-NEXT: vsext.vf2 v8, v9898; RV32V-NEXT: ret899;900; RV64V-LABEL: mgather_v2i16_sextload_v2i32:901; RV64V: # %bb.0:902; RV64V-NEXT: vsetivli zero, 2, e16, mf4, ta, mu903; RV64V-NEXT: vluxei64.v v9, (zero), v8, v0.t904; RV64V-NEXT: vsetvli zero, zero, e32, mf2, ta, ma905; RV64V-NEXT: vsext.vf2 v8, v9906; RV64V-NEXT: ret907;908; RV32ZVE32F-LABEL: mgather_v2i16_sextload_v2i32:909; RV32ZVE32F: # %bb.0:910; RV32ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, mu911; RV32ZVE32F-NEXT: vluxei32.v v9, (zero), v8, v0.t912; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma913; RV32ZVE32F-NEXT: vsext.vf2 v8, v9914; RV32ZVE32F-NEXT: ret915;916; RV64ZVE32F-LABEL: mgather_v2i16_sextload_v2i32:917; RV64ZVE32F: # %bb.0:918; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma919; RV64ZVE32F-NEXT: vmv.x.s a2, v0920; RV64ZVE32F-NEXT: andi a3, a2, 1921; RV64ZVE32F-NEXT: beqz a3, .LBB15_2922; RV64ZVE32F-NEXT: # %bb.1: # %cond.load923; RV64ZVE32F-NEXT: lh a0, 0(a0)924; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, tu, ma925; RV64ZVE32F-NEXT: vmv.s.x v8, a0926; RV64ZVE32F-NEXT: .LBB15_2: # %else927; RV64ZVE32F-NEXT: andi a2, a2, 2928; RV64ZVE32F-NEXT: beqz a2, .LBB15_4929; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1930; RV64ZVE32F-NEXT: lh a0, 0(a1)931; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma932; RV64ZVE32F-NEXT: vmv.s.x v9, a0933; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma934; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1935; RV64ZVE32F-NEXT: .LBB15_4: # %else2936; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma937; RV64ZVE32F-NEXT: vsext.vf2 v9, v8938; RV64ZVE32F-NEXT: vmv.v.v v8, v9939; RV64ZVE32F-NEXT: ret940 %v = call <2 x i16> @llvm.masked.gather.v2i16.v2p0(<2 x ptr> %ptrs, i32 2, <2 x i1> %m, <2 x i16> %passthru)941 %ev = sext <2 x i16> %v to <2 x i32>942 ret <2 x i32> %ev943}944 945define <2 x i32> @mgather_v2i16_zextload_v2i32(<2 x ptr> %ptrs, <2 x i1> %m, <2 x i16> %passthru) {946; RV32V-LABEL: mgather_v2i16_zextload_v2i32:947; RV32V: # %bb.0:948; RV32V-NEXT: vsetivli zero, 2, e16, mf4, ta, mu949; RV32V-NEXT: vluxei32.v v9, (zero), v8, v0.t950; RV32V-NEXT: vsetvli zero, zero, e32, mf2, ta, ma951; RV32V-NEXT: vzext.vf2 v8, v9952; RV32V-NEXT: ret953;954; RV64V-LABEL: mgather_v2i16_zextload_v2i32:955; RV64V: # %bb.0:956; RV64V-NEXT: vsetivli zero, 2, e16, mf4, ta, mu957; RV64V-NEXT: vluxei64.v v9, (zero), v8, v0.t958; RV64V-NEXT: vsetvli zero, zero, e32, mf2, ta, ma959; RV64V-NEXT: vzext.vf2 v8, v9960; RV64V-NEXT: ret961;962; RV32ZVE32F-LABEL: mgather_v2i16_zextload_v2i32:963; RV32ZVE32F: # %bb.0:964; RV32ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, mu965; RV32ZVE32F-NEXT: vluxei32.v v9, (zero), v8, v0.t966; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma967; RV32ZVE32F-NEXT: vzext.vf2 v8, v9968; RV32ZVE32F-NEXT: ret969;970; RV64ZVE32F-LABEL: mgather_v2i16_zextload_v2i32:971; RV64ZVE32F: # %bb.0:972; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma973; RV64ZVE32F-NEXT: vmv.x.s a2, v0974; RV64ZVE32F-NEXT: andi a3, a2, 1975; RV64ZVE32F-NEXT: beqz a3, .LBB16_2976; RV64ZVE32F-NEXT: # %bb.1: # %cond.load977; RV64ZVE32F-NEXT: lh a0, 0(a0)978; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, tu, ma979; RV64ZVE32F-NEXT: vmv.s.x v8, a0980; RV64ZVE32F-NEXT: .LBB16_2: # %else981; RV64ZVE32F-NEXT: andi a2, a2, 2982; RV64ZVE32F-NEXT: beqz a2, .LBB16_4983; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1984; RV64ZVE32F-NEXT: lh a0, 0(a1)985; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma986; RV64ZVE32F-NEXT: vmv.s.x v9, a0987; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma988; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1989; RV64ZVE32F-NEXT: .LBB16_4: # %else2990; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma991; RV64ZVE32F-NEXT: vzext.vf2 v9, v8992; RV64ZVE32F-NEXT: vmv.v.v v8, v9993; RV64ZVE32F-NEXT: ret994 %v = call <2 x i16> @llvm.masked.gather.v2i16.v2p0(<2 x ptr> %ptrs, i32 2, <2 x i1> %m, <2 x i16> %passthru)995 %ev = zext <2 x i16> %v to <2 x i32>996 ret <2 x i32> %ev997}998 999define <2 x i64> @mgather_v2i16_sextload_v2i64(<2 x ptr> %ptrs, <2 x i1> %m, <2 x i16> %passthru) {1000; RV32V-LABEL: mgather_v2i16_sextload_v2i64:1001; RV32V: # %bb.0:1002; RV32V-NEXT: vsetivli zero, 2, e16, mf4, ta, mu1003; RV32V-NEXT: vluxei32.v v9, (zero), v8, v0.t1004; RV32V-NEXT: vsetvli zero, zero, e64, m1, ta, ma1005; RV32V-NEXT: vsext.vf4 v8, v91006; RV32V-NEXT: ret1007;1008; RV64V-LABEL: mgather_v2i16_sextload_v2i64:1009; RV64V: # %bb.0:1010; RV64V-NEXT: vsetivli zero, 2, e16, mf4, ta, mu1011; RV64V-NEXT: vluxei64.v v9, (zero), v8, v0.t1012; RV64V-NEXT: vsetvli zero, zero, e64, m1, ta, ma1013; RV64V-NEXT: vsext.vf4 v8, v91014; RV64V-NEXT: ret1015;1016; RV32ZVE32F-LABEL: mgather_v2i16_sextload_v2i64:1017; RV32ZVE32F: # %bb.0:1018; RV32ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, mu1019; RV32ZVE32F-NEXT: vluxei32.v v9, (zero), v8, v0.t1020; RV32ZVE32F-NEXT: vslidedown.vi v8, v9, 11021; RV32ZVE32F-NEXT: vmv.x.s a1, v91022; RV32ZVE32F-NEXT: vmv.x.s a2, v81023; RV32ZVE32F-NEXT: srai a3, a1, 311024; RV32ZVE32F-NEXT: srai a4, a2, 311025; RV32ZVE32F-NEXT: sw a1, 0(a0)1026; RV32ZVE32F-NEXT: sw a3, 4(a0)1027; RV32ZVE32F-NEXT: sw a2, 8(a0)1028; RV32ZVE32F-NEXT: sw a4, 12(a0)1029; RV32ZVE32F-NEXT: ret1030;1031; RV64ZVE32F-LABEL: mgather_v2i16_sextload_v2i64:1032; RV64ZVE32F: # %bb.0:1033; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma1034; RV64ZVE32F-NEXT: vmv.x.s a2, v01035; RV64ZVE32F-NEXT: andi a3, a2, 11036; RV64ZVE32F-NEXT: beqz a3, .LBB17_21037; RV64ZVE32F-NEXT: # %bb.1: # %cond.load1038; RV64ZVE32F-NEXT: lh a0, 0(a0)1039; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, tu, ma1040; RV64ZVE32F-NEXT: vmv.s.x v8, a01041; RV64ZVE32F-NEXT: .LBB17_2: # %else1042; RV64ZVE32F-NEXT: andi a2, a2, 21043; RV64ZVE32F-NEXT: beqz a2, .LBB17_41044; RV64ZVE32F-NEXT: # %bb.3: # %cond.load11045; RV64ZVE32F-NEXT: lh a0, 0(a1)1046; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma1047; RV64ZVE32F-NEXT: vmv.s.x v9, a01048; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma1049; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 11050; RV64ZVE32F-NEXT: .LBB17_4: # %else21051; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma1052; RV64ZVE32F-NEXT: vmv.x.s a0, v81053; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 11054; RV64ZVE32F-NEXT: vmv.x.s a1, v81055; RV64ZVE32F-NEXT: ret1056 %v = call <2 x i16> @llvm.masked.gather.v2i16.v2p0(<2 x ptr> %ptrs, i32 2, <2 x i1> %m, <2 x i16> %passthru)1057 %ev = sext <2 x i16> %v to <2 x i64>1058 ret <2 x i64> %ev1059}1060 1061define <2 x i64> @mgather_v2i16_zextload_v2i64(<2 x ptr> %ptrs, <2 x i1> %m, <2 x i16> %passthru) {1062; RV32V-LABEL: mgather_v2i16_zextload_v2i64:1063; RV32V: # %bb.0:1064; RV32V-NEXT: vsetivli zero, 2, e16, mf4, ta, mu1065; RV32V-NEXT: vluxei32.v v9, (zero), v8, v0.t1066; RV32V-NEXT: vsetvli zero, zero, e64, m1, ta, ma1067; RV32V-NEXT: vzext.vf4 v8, v91068; RV32V-NEXT: ret1069;1070; RV64V-LABEL: mgather_v2i16_zextload_v2i64:1071; RV64V: # %bb.0:1072; RV64V-NEXT: vsetivli zero, 2, e16, mf4, ta, mu1073; RV64V-NEXT: vluxei64.v v9, (zero), v8, v0.t1074; RV64V-NEXT: vsetvli zero, zero, e64, m1, ta, ma1075; RV64V-NEXT: vzext.vf4 v8, v91076; RV64V-NEXT: ret1077;1078; RV32ZVE32F-LABEL: mgather_v2i16_zextload_v2i64:1079; RV32ZVE32F: # %bb.0:1080; RV32ZVE32F-NEXT: lui a1, 161081; RV32ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, mu1082; RV32ZVE32F-NEXT: vluxei32.v v9, (zero), v8, v0.t1083; RV32ZVE32F-NEXT: addi a1, a1, -11084; RV32ZVE32F-NEXT: vslidedown.vi v8, v9, 11085; RV32ZVE32F-NEXT: vmv.x.s a2, v91086; RV32ZVE32F-NEXT: vmv.x.s a3, v81087; RV32ZVE32F-NEXT: and a2, a2, a11088; RV32ZVE32F-NEXT: and a1, a3, a11089; RV32ZVE32F-NEXT: sw a2, 0(a0)1090; RV32ZVE32F-NEXT: sw zero, 4(a0)1091; RV32ZVE32F-NEXT: sw a1, 8(a0)1092; RV32ZVE32F-NEXT: sw zero, 12(a0)1093; RV32ZVE32F-NEXT: ret1094;1095; RV64ZVE32F-LABEL: mgather_v2i16_zextload_v2i64:1096; RV64ZVE32F: # %bb.0:1097; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma1098; RV64ZVE32F-NEXT: vmv.x.s a2, v01099; RV64ZVE32F-NEXT: andi a3, a2, 11100; RV64ZVE32F-NEXT: beqz a3, .LBB18_21101; RV64ZVE32F-NEXT: # %bb.1: # %cond.load1102; RV64ZVE32F-NEXT: lh a0, 0(a0)1103; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, tu, ma1104; RV64ZVE32F-NEXT: vmv.s.x v8, a01105; RV64ZVE32F-NEXT: .LBB18_2: # %else1106; RV64ZVE32F-NEXT: andi a2, a2, 21107; RV64ZVE32F-NEXT: beqz a2, .LBB18_41108; RV64ZVE32F-NEXT: # %bb.3: # %cond.load11109; RV64ZVE32F-NEXT: lh a0, 0(a1)1110; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma1111; RV64ZVE32F-NEXT: vmv.s.x v9, a01112; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma1113; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 11114; RV64ZVE32F-NEXT: .LBB18_4: # %else21115; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma1116; RV64ZVE32F-NEXT: vmv.x.s a0, v81117; RV64ZVE32F-NEXT: lui a1, 161118; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 11119; RV64ZVE32F-NEXT: addi a1, a1, -11120; RV64ZVE32F-NEXT: vmv.x.s a2, v81121; RV64ZVE32F-NEXT: and a0, a0, a11122; RV64ZVE32F-NEXT: and a1, a2, a11123; RV64ZVE32F-NEXT: ret1124 %v = call <2 x i16> @llvm.masked.gather.v2i16.v2p0(<2 x ptr> %ptrs, i32 2, <2 x i1> %m, <2 x i16> %passthru)1125 %ev = zext <2 x i16> %v to <2 x i64>1126 ret <2 x i64> %ev1127}1128 1129define <4 x i16> @mgather_v4i16(<4 x ptr> %ptrs, <4 x i1> %m, <4 x i16> %passthru) {1130; RV32-LABEL: mgather_v4i16:1131; RV32: # %bb.0:1132; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, mu1133; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t1134; RV32-NEXT: vmv1r.v v8, v91135; RV32-NEXT: ret1136;1137; RV64V-LABEL: mgather_v4i16:1138; RV64V: # %bb.0:1139; RV64V-NEXT: vsetivli zero, 4, e16, mf2, ta, mu1140; RV64V-NEXT: vluxei64.v v10, (zero), v8, v0.t1141; RV64V-NEXT: vmv1r.v v8, v101142; RV64V-NEXT: ret1143;1144; RV64ZVE32F-LABEL: mgather_v4i16:1145; RV64ZVE32F: # %bb.0:1146; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma1147; RV64ZVE32F-NEXT: vmv.x.s a1, v01148; RV64ZVE32F-NEXT: andi a2, a1, 11149; RV64ZVE32F-NEXT: bnez a2, .LBB19_51150; RV64ZVE32F-NEXT: # %bb.1: # %else1151; RV64ZVE32F-NEXT: andi a2, a1, 21152; RV64ZVE32F-NEXT: bnez a2, .LBB19_61153; RV64ZVE32F-NEXT: .LBB19_2: # %else21154; RV64ZVE32F-NEXT: andi a2, a1, 41155; RV64ZVE32F-NEXT: bnez a2, .LBB19_71156; RV64ZVE32F-NEXT: .LBB19_3: # %else51157; RV64ZVE32F-NEXT: andi a1, a1, 81158; RV64ZVE32F-NEXT: bnez a1, .LBB19_81159; RV64ZVE32F-NEXT: .LBB19_4: # %else81160; RV64ZVE32F-NEXT: ret1161; RV64ZVE32F-NEXT: .LBB19_5: # %cond.load1162; RV64ZVE32F-NEXT: ld a2, 0(a0)1163; RV64ZVE32F-NEXT: lh a2, 0(a2)1164; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, tu, ma1165; RV64ZVE32F-NEXT: vmv.s.x v8, a21166; RV64ZVE32F-NEXT: andi a2, a1, 21167; RV64ZVE32F-NEXT: beqz a2, .LBB19_21168; RV64ZVE32F-NEXT: .LBB19_6: # %cond.load11169; RV64ZVE32F-NEXT: ld a2, 8(a0)1170; RV64ZVE32F-NEXT: lh a2, 0(a2)1171; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma1172; RV64ZVE32F-NEXT: vmv.s.x v9, a21173; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, tu, ma1174; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 11175; RV64ZVE32F-NEXT: andi a2, a1, 41176; RV64ZVE32F-NEXT: beqz a2, .LBB19_31177; RV64ZVE32F-NEXT: .LBB19_7: # %cond.load41178; RV64ZVE32F-NEXT: ld a2, 16(a0)1179; RV64ZVE32F-NEXT: lh a2, 0(a2)1180; RV64ZVE32F-NEXT: vsetivli zero, 3, e16, mf2, tu, ma1181; RV64ZVE32F-NEXT: vmv.s.x v9, a21182; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 21183; RV64ZVE32F-NEXT: andi a1, a1, 81184; RV64ZVE32F-NEXT: beqz a1, .LBB19_41185; RV64ZVE32F-NEXT: .LBB19_8: # %cond.load71186; RV64ZVE32F-NEXT: ld a0, 24(a0)1187; RV64ZVE32F-NEXT: lh a0, 0(a0)1188; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, mf2, ta, ma1189; RV64ZVE32F-NEXT: vmv.s.x v9, a01190; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 31191; RV64ZVE32F-NEXT: ret1192 %v = call <4 x i16> @llvm.masked.gather.v4i16.v4p0(<4 x ptr> %ptrs, i32 2, <4 x i1> %m, <4 x i16> %passthru)1193 ret <4 x i16> %v1194}1195 1196define <4 x i16> @mgather_truemask_v4i16(<4 x ptr> %ptrs, <4 x i16> %passthru) {1197; RV32-LABEL: mgather_truemask_v4i16:1198; RV32: # %bb.0:1199; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma1200; RV32-NEXT: vluxei32.v v9, (zero), v81201; RV32-NEXT: vmv1r.v v8, v91202; RV32-NEXT: ret1203;1204; RV64V-LABEL: mgather_truemask_v4i16:1205; RV64V: # %bb.0:1206; RV64V-NEXT: vsetivli zero, 4, e16, mf2, ta, ma1207; RV64V-NEXT: vluxei64.v v10, (zero), v81208; RV64V-NEXT: vmv1r.v v8, v101209; RV64V-NEXT: ret1210;1211; RV64ZVE32F-LABEL: mgather_truemask_v4i16:1212; RV64ZVE32F: # %bb.0:1213; RV64ZVE32F-NEXT: ld a1, 0(a0)1214; RV64ZVE32F-NEXT: ld a2, 8(a0)1215; RV64ZVE32F-NEXT: ld a3, 16(a0)1216; RV64ZVE32F-NEXT: ld a0, 24(a0)1217; RV64ZVE32F-NEXT: lh a1, 0(a1)1218; RV64ZVE32F-NEXT: lh a2, 0(a2)1219; RV64ZVE32F-NEXT: lh a3, 0(a3)1220; RV64ZVE32F-NEXT: lh a0, 0(a0)1221; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, mf2, ta, ma1222; RV64ZVE32F-NEXT: vmv.v.x v8, a11223; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a21224; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a31225; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a01226; RV64ZVE32F-NEXT: ret1227 %v = call <4 x i16> @llvm.masked.gather.v4i16.v4p0(<4 x ptr> %ptrs, i32 2, <4 x i1> splat (i1 1), <4 x i16> %passthru)1228 ret <4 x i16> %v1229}1230 1231define <4 x i16> @mgather_falsemask_v4i16(<4 x ptr> %ptrs, <4 x i16> %passthru) {1232; RV32-LABEL: mgather_falsemask_v4i16:1233; RV32: # %bb.0:1234; RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma1235; RV32-NEXT: vmv1r.v v8, v91236; RV32-NEXT: ret1237;1238; RV64V-LABEL: mgather_falsemask_v4i16:1239; RV64V: # %bb.0:1240; RV64V-NEXT: vsetivli zero, 1, e8, m1, ta, ma1241; RV64V-NEXT: vmv1r.v v8, v101242; RV64V-NEXT: ret1243;1244; RV64ZVE32F-LABEL: mgather_falsemask_v4i16:1245; RV64ZVE32F: # %bb.0:1246; RV64ZVE32F-NEXT: ret1247 %v = call <4 x i16> @llvm.masked.gather.v4i16.v4p0(<4 x ptr> %ptrs, i32 2, <4 x i1> zeroinitializer, <4 x i16> %passthru)1248 ret <4 x i16> %v1249}1250 1251define <8 x i16> @mgather_v8i16(<8 x ptr> %ptrs, <8 x i1> %m, <8 x i16> %passthru) {1252; RV32-LABEL: mgather_v8i16:1253; RV32: # %bb.0:1254; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu1255; RV32-NEXT: vluxei32.v v10, (zero), v8, v0.t1256; RV32-NEXT: vmv.v.v v8, v101257; RV32-NEXT: ret1258;1259; RV64V-LABEL: mgather_v8i16:1260; RV64V: # %bb.0:1261; RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, mu1262; RV64V-NEXT: vluxei64.v v12, (zero), v8, v0.t1263; RV64V-NEXT: vmv.v.v v8, v121264; RV64V-NEXT: ret1265;1266; RV64ZVE32F-LABEL: mgather_v8i16:1267; RV64ZVE32F: # %bb.0:1268; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma1269; RV64ZVE32F-NEXT: vmv.x.s a1, v01270; RV64ZVE32F-NEXT: andi a2, a1, 11271; RV64ZVE32F-NEXT: bnez a2, .LBB22_91272; RV64ZVE32F-NEXT: # %bb.1: # %else1273; RV64ZVE32F-NEXT: andi a2, a1, 21274; RV64ZVE32F-NEXT: bnez a2, .LBB22_101275; RV64ZVE32F-NEXT: .LBB22_2: # %else21276; RV64ZVE32F-NEXT: andi a2, a1, 41277; RV64ZVE32F-NEXT: bnez a2, .LBB22_111278; RV64ZVE32F-NEXT: .LBB22_3: # %else51279; RV64ZVE32F-NEXT: andi a2, a1, 81280; RV64ZVE32F-NEXT: bnez a2, .LBB22_121281; RV64ZVE32F-NEXT: .LBB22_4: # %else81282; RV64ZVE32F-NEXT: andi a2, a1, 161283; RV64ZVE32F-NEXT: bnez a2, .LBB22_131284; RV64ZVE32F-NEXT: .LBB22_5: # %else111285; RV64ZVE32F-NEXT: andi a2, a1, 321286; RV64ZVE32F-NEXT: bnez a2, .LBB22_141287; RV64ZVE32F-NEXT: .LBB22_6: # %else141288; RV64ZVE32F-NEXT: andi a2, a1, 641289; RV64ZVE32F-NEXT: bnez a2, .LBB22_151290; RV64ZVE32F-NEXT: .LBB22_7: # %else171291; RV64ZVE32F-NEXT: andi a1, a1, -1281292; RV64ZVE32F-NEXT: bnez a1, .LBB22_161293; RV64ZVE32F-NEXT: .LBB22_8: # %else201294; RV64ZVE32F-NEXT: ret1295; RV64ZVE32F-NEXT: .LBB22_9: # %cond.load1296; RV64ZVE32F-NEXT: ld a2, 0(a0)1297; RV64ZVE32F-NEXT: lh a2, 0(a2)1298; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, tu, ma1299; RV64ZVE32F-NEXT: vmv.s.x v8, a21300; RV64ZVE32F-NEXT: andi a2, a1, 21301; RV64ZVE32F-NEXT: beqz a2, .LBB22_21302; RV64ZVE32F-NEXT: .LBB22_10: # %cond.load11303; RV64ZVE32F-NEXT: ld a2, 8(a0)1304; RV64ZVE32F-NEXT: lh a2, 0(a2)1305; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma1306; RV64ZVE32F-NEXT: vmv.s.x v9, a21307; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, m1, tu, ma1308; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 11309; RV64ZVE32F-NEXT: andi a2, a1, 41310; RV64ZVE32F-NEXT: beqz a2, .LBB22_31311; RV64ZVE32F-NEXT: .LBB22_11: # %cond.load41312; RV64ZVE32F-NEXT: ld a2, 16(a0)1313; RV64ZVE32F-NEXT: lh a2, 0(a2)1314; RV64ZVE32F-NEXT: vsetivli zero, 3, e16, m1, tu, ma1315; RV64ZVE32F-NEXT: vmv.s.x v9, a21316; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 21317; RV64ZVE32F-NEXT: andi a2, a1, 81318; RV64ZVE32F-NEXT: beqz a2, .LBB22_41319; RV64ZVE32F-NEXT: .LBB22_12: # %cond.load71320; RV64ZVE32F-NEXT: ld a2, 24(a0)1321; RV64ZVE32F-NEXT: lh a2, 0(a2)1322; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma1323; RV64ZVE32F-NEXT: vmv.s.x v9, a21324; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 31325; RV64ZVE32F-NEXT: andi a2, a1, 161326; RV64ZVE32F-NEXT: beqz a2, .LBB22_51327; RV64ZVE32F-NEXT: .LBB22_13: # %cond.load101328; RV64ZVE32F-NEXT: ld a2, 32(a0)1329; RV64ZVE32F-NEXT: lh a2, 0(a2)1330; RV64ZVE32F-NEXT: vsetivli zero, 5, e16, m1, tu, ma1331; RV64ZVE32F-NEXT: vmv.s.x v9, a21332; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 41333; RV64ZVE32F-NEXT: andi a2, a1, 321334; RV64ZVE32F-NEXT: beqz a2, .LBB22_61335; RV64ZVE32F-NEXT: .LBB22_14: # %cond.load131336; RV64ZVE32F-NEXT: ld a2, 40(a0)1337; RV64ZVE32F-NEXT: lh a2, 0(a2)1338; RV64ZVE32F-NEXT: vsetivli zero, 6, e16, m1, tu, ma1339; RV64ZVE32F-NEXT: vmv.s.x v9, a21340; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 51341; RV64ZVE32F-NEXT: andi a2, a1, 641342; RV64ZVE32F-NEXT: beqz a2, .LBB22_71343; RV64ZVE32F-NEXT: .LBB22_15: # %cond.load161344; RV64ZVE32F-NEXT: ld a2, 48(a0)1345; RV64ZVE32F-NEXT: lh a2, 0(a2)1346; RV64ZVE32F-NEXT: vsetivli zero, 7, e16, m1, tu, ma1347; RV64ZVE32F-NEXT: vmv.s.x v9, a21348; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 61349; RV64ZVE32F-NEXT: andi a1, a1, -1281350; RV64ZVE32F-NEXT: beqz a1, .LBB22_81351; RV64ZVE32F-NEXT: .LBB22_16: # %cond.load191352; RV64ZVE32F-NEXT: ld a0, 56(a0)1353; RV64ZVE32F-NEXT: lh a0, 0(a0)1354; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma1355; RV64ZVE32F-NEXT: vmv.s.x v9, a01356; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 71357; RV64ZVE32F-NEXT: ret1358 %v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 2, <8 x i1> %m, <8 x i16> %passthru)1359 ret <8 x i16> %v1360}1361 1362define <8 x i16> @mgather_baseidx_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8 x i1> %m, <8 x i16> %passthru) {1363; RV32-LABEL: mgather_baseidx_v8i8_v8i16:1364; RV32: # %bb.0:1365; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma1366; RV32-NEXT: vsext.vf4 v10, v81367; RV32-NEXT: vadd.vv v10, v10, v101368; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu1369; RV32-NEXT: vluxei32.v v9, (a0), v10, v0.t1370; RV32-NEXT: vmv.v.v v8, v91371; RV32-NEXT: ret1372;1373; RV64V-LABEL: mgather_baseidx_v8i8_v8i16:1374; RV64V: # %bb.0:1375; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma1376; RV64V-NEXT: vsext.vf8 v12, v81377; RV64V-NEXT: vadd.vv v12, v12, v121378; RV64V-NEXT: vsetvli zero, zero, e16, m1, ta, mu1379; RV64V-NEXT: vluxei64.v v9, (a0), v12, v0.t1380; RV64V-NEXT: vmv.v.v v8, v91381; RV64V-NEXT: ret1382;1383; RV64ZVE32F-LABEL: mgather_baseidx_v8i8_v8i16:1384; RV64ZVE32F: # %bb.0:1385; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma1386; RV64ZVE32F-NEXT: vmv.x.s a1, v01387; RV64ZVE32F-NEXT: andi a2, a1, 11388; RV64ZVE32F-NEXT: beqz a2, .LBB23_21389; RV64ZVE32F-NEXT: # %bb.1: # %cond.load1390; RV64ZVE32F-NEXT: vmv.x.s a2, v81391; RV64ZVE32F-NEXT: slli a2, a2, 11392; RV64ZVE32F-NEXT: add a2, a0, a21393; RV64ZVE32F-NEXT: lh a2, 0(a2)1394; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, tu, ma1395; RV64ZVE32F-NEXT: vmv.s.x v9, a21396; RV64ZVE32F-NEXT: .LBB23_2: # %else1397; RV64ZVE32F-NEXT: andi a2, a1, 21398; RV64ZVE32F-NEXT: beqz a2, .LBB23_41399; RV64ZVE32F-NEXT: # %bb.3: # %cond.load11400; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma1401; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 11402; RV64ZVE32F-NEXT: vmv.x.s a2, v101403; RV64ZVE32F-NEXT: slli a2, a2, 11404; RV64ZVE32F-NEXT: add a2, a0, a21405; RV64ZVE32F-NEXT: lh a2, 0(a2)1406; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma1407; RV64ZVE32F-NEXT: vmv.s.x v10, a21408; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, m1, tu, ma1409; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 11410; RV64ZVE32F-NEXT: .LBB23_4: # %else21411; RV64ZVE32F-NEXT: andi a2, a1, 41412; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma1413; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 21414; RV64ZVE32F-NEXT: beqz a2, .LBB23_61415; RV64ZVE32F-NEXT: # %bb.5: # %cond.load41416; RV64ZVE32F-NEXT: vmv.x.s a2, v101417; RV64ZVE32F-NEXT: slli a2, a2, 11418; RV64ZVE32F-NEXT: add a2, a0, a21419; RV64ZVE32F-NEXT: lh a2, 0(a2)1420; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma1421; RV64ZVE32F-NEXT: vmv.s.x v11, a21422; RV64ZVE32F-NEXT: vsetivli zero, 3, e16, m1, tu, ma1423; RV64ZVE32F-NEXT: vslideup.vi v9, v11, 21424; RV64ZVE32F-NEXT: .LBB23_6: # %else51425; RV64ZVE32F-NEXT: andi a2, a1, 81426; RV64ZVE32F-NEXT: beqz a2, .LBB23_81427; RV64ZVE32F-NEXT: # %bb.7: # %cond.load71428; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma1429; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 11430; RV64ZVE32F-NEXT: vmv.x.s a2, v101431; RV64ZVE32F-NEXT: slli a2, a2, 11432; RV64ZVE32F-NEXT: add a2, a0, a21433; RV64ZVE32F-NEXT: lh a2, 0(a2)1434; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma1435; RV64ZVE32F-NEXT: vmv.s.x v10, a21436; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma1437; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 31438; RV64ZVE32F-NEXT: .LBB23_8: # %else81439; RV64ZVE32F-NEXT: andi a2, a1, 161440; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma1441; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 41442; RV64ZVE32F-NEXT: beqz a2, .LBB23_101443; RV64ZVE32F-NEXT: # %bb.9: # %cond.load101444; RV64ZVE32F-NEXT: vmv.x.s a2, v81445; RV64ZVE32F-NEXT: slli a2, a2, 11446; RV64ZVE32F-NEXT: add a2, a0, a21447; RV64ZVE32F-NEXT: lh a2, 0(a2)1448; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma1449; RV64ZVE32F-NEXT: vmv.s.x v10, a21450; RV64ZVE32F-NEXT: vsetivli zero, 5, e16, m1, tu, ma1451; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 41452; RV64ZVE32F-NEXT: .LBB23_10: # %else111453; RV64ZVE32F-NEXT: andi a2, a1, 321454; RV64ZVE32F-NEXT: beqz a2, .LBB23_121455; RV64ZVE32F-NEXT: # %bb.11: # %cond.load131456; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma1457; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 11458; RV64ZVE32F-NEXT: vmv.x.s a2, v101459; RV64ZVE32F-NEXT: slli a2, a2, 11460; RV64ZVE32F-NEXT: add a2, a0, a21461; RV64ZVE32F-NEXT: lh a2, 0(a2)1462; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma1463; RV64ZVE32F-NEXT: vmv.s.x v10, a21464; RV64ZVE32F-NEXT: vsetivli zero, 6, e16, m1, tu, ma1465; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 51466; RV64ZVE32F-NEXT: .LBB23_12: # %else141467; RV64ZVE32F-NEXT: andi a2, a1, 641468; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma1469; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 21470; RV64ZVE32F-NEXT: beqz a2, .LBB23_141471; RV64ZVE32F-NEXT: # %bb.13: # %cond.load161472; RV64ZVE32F-NEXT: vmv.x.s a2, v81473; RV64ZVE32F-NEXT: slli a2, a2, 11474; RV64ZVE32F-NEXT: add a2, a0, a21475; RV64ZVE32F-NEXT: lh a2, 0(a2)1476; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma1477; RV64ZVE32F-NEXT: vmv.s.x v10, a21478; RV64ZVE32F-NEXT: vsetivli zero, 7, e16, m1, tu, ma1479; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 61480; RV64ZVE32F-NEXT: .LBB23_14: # %else171481; RV64ZVE32F-NEXT: andi a1, a1, -1281482; RV64ZVE32F-NEXT: beqz a1, .LBB23_161483; RV64ZVE32F-NEXT: # %bb.15: # %cond.load191484; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma1485; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 11486; RV64ZVE32F-NEXT: vmv.x.s a1, v81487; RV64ZVE32F-NEXT: slli a1, a1, 11488; RV64ZVE32F-NEXT: add a0, a0, a11489; RV64ZVE32F-NEXT: lh a0, 0(a0)1490; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma1491; RV64ZVE32F-NEXT: vmv.s.x v8, a01492; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma1493; RV64ZVE32F-NEXT: vslideup.vi v9, v8, 71494; RV64ZVE32F-NEXT: .LBB23_16: # %else201495; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma1496; RV64ZVE32F-NEXT: vmv1r.v v8, v91497; RV64ZVE32F-NEXT: ret1498 %ptrs = getelementptr inbounds i16, ptr %base, <8 x i8> %idxs1499 %v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 2, <8 x i1> %m, <8 x i16> %passthru)1500 ret <8 x i16> %v1501}1502 1503define <8 x i16> @mgather_baseidx_sext_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8 x i1> %m, <8 x i16> %passthru) {1504; RV32-LABEL: mgather_baseidx_sext_v8i8_v8i16:1505; RV32: # %bb.0:1506; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma1507; RV32-NEXT: vsext.vf4 v10, v81508; RV32-NEXT: vadd.vv v10, v10, v101509; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu1510; RV32-NEXT: vluxei32.v v9, (a0), v10, v0.t1511; RV32-NEXT: vmv.v.v v8, v91512; RV32-NEXT: ret1513;1514; RV64V-LABEL: mgather_baseidx_sext_v8i8_v8i16:1515; RV64V: # %bb.0:1516; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma1517; RV64V-NEXT: vsext.vf8 v12, v81518; RV64V-NEXT: vadd.vv v12, v12, v121519; RV64V-NEXT: vsetvli zero, zero, e16, m1, ta, mu1520; RV64V-NEXT: vluxei64.v v9, (a0), v12, v0.t1521; RV64V-NEXT: vmv.v.v v8, v91522; RV64V-NEXT: ret1523;1524; RV64ZVE32F-LABEL: mgather_baseidx_sext_v8i8_v8i16:1525; RV64ZVE32F: # %bb.0:1526; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma1527; RV64ZVE32F-NEXT: vmv.x.s a1, v01528; RV64ZVE32F-NEXT: andi a2, a1, 11529; RV64ZVE32F-NEXT: beqz a2, .LBB24_21530; RV64ZVE32F-NEXT: # %bb.1: # %cond.load1531; RV64ZVE32F-NEXT: vmv.x.s a2, v81532; RV64ZVE32F-NEXT: slli a2, a2, 11533; RV64ZVE32F-NEXT: add a2, a0, a21534; RV64ZVE32F-NEXT: lh a2, 0(a2)1535; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, tu, ma1536; RV64ZVE32F-NEXT: vmv.s.x v9, a21537; RV64ZVE32F-NEXT: .LBB24_2: # %else1538; RV64ZVE32F-NEXT: andi a2, a1, 21539; RV64ZVE32F-NEXT: beqz a2, .LBB24_41540; RV64ZVE32F-NEXT: # %bb.3: # %cond.load11541; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma1542; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 11543; RV64ZVE32F-NEXT: vmv.x.s a2, v101544; RV64ZVE32F-NEXT: slli a2, a2, 11545; RV64ZVE32F-NEXT: add a2, a0, a21546; RV64ZVE32F-NEXT: lh a2, 0(a2)1547; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma1548; RV64ZVE32F-NEXT: vmv.s.x v10, a21549; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, m1, tu, ma1550; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 11551; RV64ZVE32F-NEXT: .LBB24_4: # %else21552; RV64ZVE32F-NEXT: andi a2, a1, 41553; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma1554; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 21555; RV64ZVE32F-NEXT: beqz a2, .LBB24_61556; RV64ZVE32F-NEXT: # %bb.5: # %cond.load41557; RV64ZVE32F-NEXT: vmv.x.s a2, v101558; RV64ZVE32F-NEXT: slli a2, a2, 11559; RV64ZVE32F-NEXT: add a2, a0, a21560; RV64ZVE32F-NEXT: lh a2, 0(a2)1561; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma1562; RV64ZVE32F-NEXT: vmv.s.x v11, a21563; RV64ZVE32F-NEXT: vsetivli zero, 3, e16, m1, tu, ma1564; RV64ZVE32F-NEXT: vslideup.vi v9, v11, 21565; RV64ZVE32F-NEXT: .LBB24_6: # %else51566; RV64ZVE32F-NEXT: andi a2, a1, 81567; RV64ZVE32F-NEXT: beqz a2, .LBB24_81568; RV64ZVE32F-NEXT: # %bb.7: # %cond.load71569; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma1570; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 11571; RV64ZVE32F-NEXT: vmv.x.s a2, v101572; RV64ZVE32F-NEXT: slli a2, a2, 11573; RV64ZVE32F-NEXT: add a2, a0, a21574; RV64ZVE32F-NEXT: lh a2, 0(a2)1575; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma1576; RV64ZVE32F-NEXT: vmv.s.x v10, a21577; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma1578; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 31579; RV64ZVE32F-NEXT: .LBB24_8: # %else81580; RV64ZVE32F-NEXT: andi a2, a1, 161581; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma1582; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 41583; RV64ZVE32F-NEXT: beqz a2, .LBB24_101584; RV64ZVE32F-NEXT: # %bb.9: # %cond.load101585; RV64ZVE32F-NEXT: vmv.x.s a2, v81586; RV64ZVE32F-NEXT: slli a2, a2, 11587; RV64ZVE32F-NEXT: add a2, a0, a21588; RV64ZVE32F-NEXT: lh a2, 0(a2)1589; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma1590; RV64ZVE32F-NEXT: vmv.s.x v10, a21591; RV64ZVE32F-NEXT: vsetivli zero, 5, e16, m1, tu, ma1592; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 41593; RV64ZVE32F-NEXT: .LBB24_10: # %else111594; RV64ZVE32F-NEXT: andi a2, a1, 321595; RV64ZVE32F-NEXT: beqz a2, .LBB24_121596; RV64ZVE32F-NEXT: # %bb.11: # %cond.load131597; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma1598; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 11599; RV64ZVE32F-NEXT: vmv.x.s a2, v101600; RV64ZVE32F-NEXT: slli a2, a2, 11601; RV64ZVE32F-NEXT: add a2, a0, a21602; RV64ZVE32F-NEXT: lh a2, 0(a2)1603; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma1604; RV64ZVE32F-NEXT: vmv.s.x v10, a21605; RV64ZVE32F-NEXT: vsetivli zero, 6, e16, m1, tu, ma1606; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 51607; RV64ZVE32F-NEXT: .LBB24_12: # %else141608; RV64ZVE32F-NEXT: andi a2, a1, 641609; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma1610; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 21611; RV64ZVE32F-NEXT: beqz a2, .LBB24_141612; RV64ZVE32F-NEXT: # %bb.13: # %cond.load161613; RV64ZVE32F-NEXT: vmv.x.s a2, v81614; RV64ZVE32F-NEXT: slli a2, a2, 11615; RV64ZVE32F-NEXT: add a2, a0, a21616; RV64ZVE32F-NEXT: lh a2, 0(a2)1617; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma1618; RV64ZVE32F-NEXT: vmv.s.x v10, a21619; RV64ZVE32F-NEXT: vsetivli zero, 7, e16, m1, tu, ma1620; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 61621; RV64ZVE32F-NEXT: .LBB24_14: # %else171622; RV64ZVE32F-NEXT: andi a1, a1, -1281623; RV64ZVE32F-NEXT: beqz a1, .LBB24_161624; RV64ZVE32F-NEXT: # %bb.15: # %cond.load191625; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma1626; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 11627; RV64ZVE32F-NEXT: vmv.x.s a1, v81628; RV64ZVE32F-NEXT: slli a1, a1, 11629; RV64ZVE32F-NEXT: add a0, a0, a11630; RV64ZVE32F-NEXT: lh a0, 0(a0)1631; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma1632; RV64ZVE32F-NEXT: vmv.s.x v8, a01633; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma1634; RV64ZVE32F-NEXT: vslideup.vi v9, v8, 71635; RV64ZVE32F-NEXT: .LBB24_16: # %else201636; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma1637; RV64ZVE32F-NEXT: vmv1r.v v8, v91638; RV64ZVE32F-NEXT: ret1639 %eidxs = sext <8 x i8> %idxs to <8 x i16>1640 %ptrs = getelementptr inbounds i16, ptr %base, <8 x i16> %eidxs1641 %v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 2, <8 x i1> %m, <8 x i16> %passthru)1642 ret <8 x i16> %v1643}1644 1645define <8 x i16> @mgather_baseidx_zext_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8 x i1> %m, <8 x i16> %passthru) {1646; RV32-LABEL: mgather_baseidx_zext_v8i8_v8i16:1647; RV32: # %bb.0:1648; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma1649; RV32-NEXT: vwaddu.vv v10, v8, v81650; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu1651; RV32-NEXT: vluxei16.v v9, (a0), v10, v0.t1652; RV32-NEXT: vmv.v.v v8, v91653; RV32-NEXT: ret1654;1655; RV64V-LABEL: mgather_baseidx_zext_v8i8_v8i16:1656; RV64V: # %bb.0:1657; RV64V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma1658; RV64V-NEXT: vwaddu.vv v10, v8, v81659; RV64V-NEXT: vsetvli zero, zero, e16, m1, ta, mu1660; RV64V-NEXT: vluxei16.v v9, (a0), v10, v0.t1661; RV64V-NEXT: vmv.v.v v8, v91662; RV64V-NEXT: ret1663;1664; RV64ZVE32F-LABEL: mgather_baseidx_zext_v8i8_v8i16:1665; RV64ZVE32F: # %bb.0:1666; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma1667; RV64ZVE32F-NEXT: vmv.x.s a1, v01668; RV64ZVE32F-NEXT: andi a2, a1, 11669; RV64ZVE32F-NEXT: beqz a2, .LBB25_21670; RV64ZVE32F-NEXT: # %bb.1: # %cond.load1671; RV64ZVE32F-NEXT: vmv.x.s a2, v81672; RV64ZVE32F-NEXT: zext.b a2, a21673; RV64ZVE32F-NEXT: slli a2, a2, 11674; RV64ZVE32F-NEXT: add a2, a0, a21675; RV64ZVE32F-NEXT: lh a2, 0(a2)1676; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, tu, ma1677; RV64ZVE32F-NEXT: vmv.s.x v9, a21678; RV64ZVE32F-NEXT: .LBB25_2: # %else1679; RV64ZVE32F-NEXT: andi a2, a1, 21680; RV64ZVE32F-NEXT: beqz a2, .LBB25_41681; RV64ZVE32F-NEXT: # %bb.3: # %cond.load11682; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma1683; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 11684; RV64ZVE32F-NEXT: vmv.x.s a2, v101685; RV64ZVE32F-NEXT: zext.b a2, a21686; RV64ZVE32F-NEXT: slli a2, a2, 11687; RV64ZVE32F-NEXT: add a2, a0, a21688; RV64ZVE32F-NEXT: lh a2, 0(a2)1689; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma1690; RV64ZVE32F-NEXT: vmv.s.x v10, a21691; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, m1, tu, ma1692; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 11693; RV64ZVE32F-NEXT: .LBB25_4: # %else21694; RV64ZVE32F-NEXT: andi a2, a1, 41695; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma1696; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 21697; RV64ZVE32F-NEXT: beqz a2, .LBB25_61698; RV64ZVE32F-NEXT: # %bb.5: # %cond.load41699; RV64ZVE32F-NEXT: vmv.x.s a2, v101700; RV64ZVE32F-NEXT: zext.b a2, a21701; RV64ZVE32F-NEXT: slli a2, a2, 11702; RV64ZVE32F-NEXT: add a2, a0, a21703; RV64ZVE32F-NEXT: lh a2, 0(a2)1704; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma1705; RV64ZVE32F-NEXT: vmv.s.x v11, a21706; RV64ZVE32F-NEXT: vsetivli zero, 3, e16, m1, tu, ma1707; RV64ZVE32F-NEXT: vslideup.vi v9, v11, 21708; RV64ZVE32F-NEXT: .LBB25_6: # %else51709; RV64ZVE32F-NEXT: andi a2, a1, 81710; RV64ZVE32F-NEXT: beqz a2, .LBB25_81711; RV64ZVE32F-NEXT: # %bb.7: # %cond.load71712; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma1713; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 11714; RV64ZVE32F-NEXT: vmv.x.s a2, v101715; RV64ZVE32F-NEXT: zext.b a2, a21716; RV64ZVE32F-NEXT: slli a2, a2, 11717; RV64ZVE32F-NEXT: add a2, a0, a21718; RV64ZVE32F-NEXT: lh a2, 0(a2)1719; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma1720; RV64ZVE32F-NEXT: vmv.s.x v10, a21721; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma1722; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 31723; RV64ZVE32F-NEXT: .LBB25_8: # %else81724; RV64ZVE32F-NEXT: andi a2, a1, 161725; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma1726; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 41727; RV64ZVE32F-NEXT: beqz a2, .LBB25_101728; RV64ZVE32F-NEXT: # %bb.9: # %cond.load101729; RV64ZVE32F-NEXT: vmv.x.s a2, v81730; RV64ZVE32F-NEXT: zext.b a2, a21731; RV64ZVE32F-NEXT: slli a2, a2, 11732; RV64ZVE32F-NEXT: add a2, a0, a21733; RV64ZVE32F-NEXT: lh a2, 0(a2)1734; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma1735; RV64ZVE32F-NEXT: vmv.s.x v10, a21736; RV64ZVE32F-NEXT: vsetivli zero, 5, e16, m1, tu, ma1737; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 41738; RV64ZVE32F-NEXT: .LBB25_10: # %else111739; RV64ZVE32F-NEXT: andi a2, a1, 321740; RV64ZVE32F-NEXT: beqz a2, .LBB25_121741; RV64ZVE32F-NEXT: # %bb.11: # %cond.load131742; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma1743; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 11744; RV64ZVE32F-NEXT: vmv.x.s a2, v101745; RV64ZVE32F-NEXT: zext.b a2, a21746; RV64ZVE32F-NEXT: slli a2, a2, 11747; RV64ZVE32F-NEXT: add a2, a0, a21748; RV64ZVE32F-NEXT: lh a2, 0(a2)1749; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma1750; RV64ZVE32F-NEXT: vmv.s.x v10, a21751; RV64ZVE32F-NEXT: vsetivli zero, 6, e16, m1, tu, ma1752; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 51753; RV64ZVE32F-NEXT: .LBB25_12: # %else141754; RV64ZVE32F-NEXT: andi a2, a1, 641755; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma1756; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 21757; RV64ZVE32F-NEXT: beqz a2, .LBB25_141758; RV64ZVE32F-NEXT: # %bb.13: # %cond.load161759; RV64ZVE32F-NEXT: vmv.x.s a2, v81760; RV64ZVE32F-NEXT: zext.b a2, a21761; RV64ZVE32F-NEXT: slli a2, a2, 11762; RV64ZVE32F-NEXT: add a2, a0, a21763; RV64ZVE32F-NEXT: lh a2, 0(a2)1764; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma1765; RV64ZVE32F-NEXT: vmv.s.x v10, a21766; RV64ZVE32F-NEXT: vsetivli zero, 7, e16, m1, tu, ma1767; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 61768; RV64ZVE32F-NEXT: .LBB25_14: # %else171769; RV64ZVE32F-NEXT: andi a1, a1, -1281770; RV64ZVE32F-NEXT: beqz a1, .LBB25_161771; RV64ZVE32F-NEXT: # %bb.15: # %cond.load191772; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma1773; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 11774; RV64ZVE32F-NEXT: vmv.x.s a1, v81775; RV64ZVE32F-NEXT: zext.b a1, a11776; RV64ZVE32F-NEXT: slli a1, a1, 11777; RV64ZVE32F-NEXT: add a0, a0, a11778; RV64ZVE32F-NEXT: lh a0, 0(a0)1779; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma1780; RV64ZVE32F-NEXT: vmv.s.x v8, a01781; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma1782; RV64ZVE32F-NEXT: vslideup.vi v9, v8, 71783; RV64ZVE32F-NEXT: .LBB25_16: # %else201784; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma1785; RV64ZVE32F-NEXT: vmv1r.v v8, v91786; RV64ZVE32F-NEXT: ret1787 %eidxs = zext <8 x i8> %idxs to <8 x i16>1788 %ptrs = getelementptr inbounds i16, ptr %base, <8 x i16> %eidxs1789 %v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 2, <8 x i1> %m, <8 x i16> %passthru)1790 ret <8 x i16> %v1791}1792 1793define <8 x i16> @mgather_baseidx_v8i16(ptr %base, <8 x i16> %idxs, <8 x i1> %m, <8 x i16> %passthru) {1794; RV32-LABEL: mgather_baseidx_v8i16:1795; RV32: # %bb.0:1796; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu1797; RV32-NEXT: vwadd.vv v10, v8, v81798; RV32-NEXT: vluxei32.v v9, (a0), v10, v0.t1799; RV32-NEXT: vmv.v.v v8, v91800; RV32-NEXT: ret1801;1802; RV64V-LABEL: mgather_baseidx_v8i16:1803; RV64V: # %bb.0:1804; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma1805; RV64V-NEXT: vsext.vf4 v12, v81806; RV64V-NEXT: vadd.vv v12, v12, v121807; RV64V-NEXT: vsetvli zero, zero, e16, m1, ta, mu1808; RV64V-NEXT: vluxei64.v v9, (a0), v12, v0.t1809; RV64V-NEXT: vmv.v.v v8, v91810; RV64V-NEXT: ret1811;1812; RV64ZVE32F-LABEL: mgather_baseidx_v8i16:1813; RV64ZVE32F: # %bb.0:1814; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma1815; RV64ZVE32F-NEXT: vmv.x.s a1, v01816; RV64ZVE32F-NEXT: andi a2, a1, 11817; RV64ZVE32F-NEXT: beqz a2, .LBB26_21818; RV64ZVE32F-NEXT: # %bb.1: # %cond.load1819; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, tu, ma1820; RV64ZVE32F-NEXT: vmv.x.s a2, v81821; RV64ZVE32F-NEXT: slli a2, a2, 11822; RV64ZVE32F-NEXT: add a2, a0, a21823; RV64ZVE32F-NEXT: lh a2, 0(a2)1824; RV64ZVE32F-NEXT: vmv.s.x v9, a21825; RV64ZVE32F-NEXT: .LBB26_2: # %else1826; RV64ZVE32F-NEXT: andi a2, a1, 21827; RV64ZVE32F-NEXT: beqz a2, .LBB26_41828; RV64ZVE32F-NEXT: # %bb.3: # %cond.load11829; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma1830; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 11831; RV64ZVE32F-NEXT: vmv.x.s a2, v101832; RV64ZVE32F-NEXT: slli a2, a2, 11833; RV64ZVE32F-NEXT: add a2, a0, a21834; RV64ZVE32F-NEXT: lh a2, 0(a2)1835; RV64ZVE32F-NEXT: vmv.s.x v10, a21836; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, m1, tu, ma1837; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 11838; RV64ZVE32F-NEXT: .LBB26_4: # %else21839; RV64ZVE32F-NEXT: andi a2, a1, 41840; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma1841; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 21842; RV64ZVE32F-NEXT: beqz a2, .LBB26_61843; RV64ZVE32F-NEXT: # %bb.5: # %cond.load41844; RV64ZVE32F-NEXT: vmv.x.s a2, v101845; RV64ZVE32F-NEXT: slli a2, a2, 11846; RV64ZVE32F-NEXT: add a2, a0, a21847; RV64ZVE32F-NEXT: lh a2, 0(a2)1848; RV64ZVE32F-NEXT: vmv.s.x v11, a21849; RV64ZVE32F-NEXT: vsetivli zero, 3, e16, m1, tu, ma1850; RV64ZVE32F-NEXT: vslideup.vi v9, v11, 21851; RV64ZVE32F-NEXT: .LBB26_6: # %else51852; RV64ZVE32F-NEXT: andi a2, a1, 81853; RV64ZVE32F-NEXT: beqz a2, .LBB26_81854; RV64ZVE32F-NEXT: # %bb.7: # %cond.load71855; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma1856; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 11857; RV64ZVE32F-NEXT: vmv.x.s a2, v101858; RV64ZVE32F-NEXT: slli a2, a2, 11859; RV64ZVE32F-NEXT: add a2, a0, a21860; RV64ZVE32F-NEXT: lh a2, 0(a2)1861; RV64ZVE32F-NEXT: vmv.s.x v10, a21862; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma1863; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 31864; RV64ZVE32F-NEXT: .LBB26_8: # %else81865; RV64ZVE32F-NEXT: andi a2, a1, 161866; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma1867; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 41868; RV64ZVE32F-NEXT: beqz a2, .LBB26_101869; RV64ZVE32F-NEXT: # %bb.9: # %cond.load101870; RV64ZVE32F-NEXT: vmv.x.s a2, v81871; RV64ZVE32F-NEXT: slli a2, a2, 11872; RV64ZVE32F-NEXT: add a2, a0, a21873; RV64ZVE32F-NEXT: lh a2, 0(a2)1874; RV64ZVE32F-NEXT: vmv.s.x v10, a21875; RV64ZVE32F-NEXT: vsetivli zero, 5, e16, m1, tu, ma1876; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 41877; RV64ZVE32F-NEXT: .LBB26_10: # %else111878; RV64ZVE32F-NEXT: andi a2, a1, 321879; RV64ZVE32F-NEXT: beqz a2, .LBB26_121880; RV64ZVE32F-NEXT: # %bb.11: # %cond.load131881; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma1882; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 11883; RV64ZVE32F-NEXT: vmv.x.s a2, v101884; RV64ZVE32F-NEXT: slli a2, a2, 11885; RV64ZVE32F-NEXT: add a2, a0, a21886; RV64ZVE32F-NEXT: lh a2, 0(a2)1887; RV64ZVE32F-NEXT: vmv.s.x v10, a21888; RV64ZVE32F-NEXT: vsetivli zero, 6, e16, m1, tu, ma1889; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 51890; RV64ZVE32F-NEXT: .LBB26_12: # %else141891; RV64ZVE32F-NEXT: andi a2, a1, 641892; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma1893; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 21894; RV64ZVE32F-NEXT: beqz a2, .LBB26_141895; RV64ZVE32F-NEXT: # %bb.13: # %cond.load161896; RV64ZVE32F-NEXT: vmv.x.s a2, v81897; RV64ZVE32F-NEXT: slli a2, a2, 11898; RV64ZVE32F-NEXT: add a2, a0, a21899; RV64ZVE32F-NEXT: lh a2, 0(a2)1900; RV64ZVE32F-NEXT: vmv.s.x v10, a21901; RV64ZVE32F-NEXT: vsetivli zero, 7, e16, m1, tu, ma1902; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 61903; RV64ZVE32F-NEXT: .LBB26_14: # %else171904; RV64ZVE32F-NEXT: andi a1, a1, -1281905; RV64ZVE32F-NEXT: beqz a1, .LBB26_161906; RV64ZVE32F-NEXT: # %bb.15: # %cond.load191907; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma1908; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 11909; RV64ZVE32F-NEXT: vmv.x.s a1, v81910; RV64ZVE32F-NEXT: slli a1, a1, 11911; RV64ZVE32F-NEXT: add a0, a0, a11912; RV64ZVE32F-NEXT: lh a0, 0(a0)1913; RV64ZVE32F-NEXT: vmv.s.x v8, a01914; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma1915; RV64ZVE32F-NEXT: vslideup.vi v9, v8, 71916; RV64ZVE32F-NEXT: .LBB26_16: # %else201917; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma1918; RV64ZVE32F-NEXT: vmv1r.v v8, v91919; RV64ZVE32F-NEXT: ret1920 %ptrs = getelementptr inbounds i16, ptr %base, <8 x i16> %idxs1921 %v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 2, <8 x i1> %m, <8 x i16> %passthru)1922 ret <8 x i16> %v1923}1924 1925define <1 x i32> @mgather_v1i32(<1 x ptr> %ptrs, <1 x i1> %m, <1 x i32> %passthru) {1926; RV32V-LABEL: mgather_v1i32:1927; RV32V: # %bb.0:1928; RV32V-NEXT: vsetivli zero, 1, e32, mf2, ta, mu1929; RV32V-NEXT: vluxei32.v v9, (zero), v8, v0.t1930; RV32V-NEXT: vmv1r.v v8, v91931; RV32V-NEXT: ret1932;1933; RV64V-LABEL: mgather_v1i32:1934; RV64V: # %bb.0:1935; RV64V-NEXT: vsetivli zero, 1, e32, mf2, ta, mu1936; RV64V-NEXT: vluxei64.v v9, (zero), v8, v0.t1937; RV64V-NEXT: vmv1r.v v8, v91938; RV64V-NEXT: ret1939;1940; RV32ZVE32F-LABEL: mgather_v1i32:1941; RV32ZVE32F: # %bb.0:1942; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, mu1943; RV32ZVE32F-NEXT: vluxei32.v v9, (zero), v8, v0.t1944; RV32ZVE32F-NEXT: vmv.v.v v8, v91945; RV32ZVE32F-NEXT: ret1946;1947; RV64ZVE32F-LABEL: mgather_v1i32:1948; RV64ZVE32F: # %bb.0:1949; RV64ZVE32F-NEXT: vsetvli a1, zero, e8, mf4, ta, ma1950; RV64ZVE32F-NEXT: vfirst.m a1, v01951; RV64ZVE32F-NEXT: bnez a1, .LBB27_21952; RV64ZVE32F-NEXT: # %bb.1: # %cond.load1953; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma1954; RV64ZVE32F-NEXT: vle32.v v8, (a0)1955; RV64ZVE32F-NEXT: .LBB27_2: # %else1956; RV64ZVE32F-NEXT: ret1957 %v = call <1 x i32> @llvm.masked.gather.v1i32.v1p0(<1 x ptr> %ptrs, i32 4, <1 x i1> %m, <1 x i32> %passthru)1958 ret <1 x i32> %v1959}1960 1961define <2 x i32> @mgather_v2i32(<2 x ptr> %ptrs, <2 x i1> %m, <2 x i32> %passthru) {1962; RV32V-LABEL: mgather_v2i32:1963; RV32V: # %bb.0:1964; RV32V-NEXT: vsetivli zero, 2, e32, mf2, ta, mu1965; RV32V-NEXT: vluxei32.v v9, (zero), v8, v0.t1966; RV32V-NEXT: vmv1r.v v8, v91967; RV32V-NEXT: ret1968;1969; RV64V-LABEL: mgather_v2i32:1970; RV64V: # %bb.0:1971; RV64V-NEXT: vsetivli zero, 2, e32, mf2, ta, mu1972; RV64V-NEXT: vluxei64.v v9, (zero), v8, v0.t1973; RV64V-NEXT: vmv1r.v v8, v91974; RV64V-NEXT: ret1975;1976; RV32ZVE32F-LABEL: mgather_v2i32:1977; RV32ZVE32F: # %bb.0:1978; RV32ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, mu1979; RV32ZVE32F-NEXT: vluxei32.v v9, (zero), v8, v0.t1980; RV32ZVE32F-NEXT: vmv.v.v v8, v91981; RV32ZVE32F-NEXT: ret1982;1983; RV64ZVE32F-LABEL: mgather_v2i32:1984; RV64ZVE32F: # %bb.0:1985; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma1986; RV64ZVE32F-NEXT: vmv.x.s a2, v01987; RV64ZVE32F-NEXT: andi a3, a2, 11988; RV64ZVE32F-NEXT: bnez a3, .LBB28_31989; RV64ZVE32F-NEXT: # %bb.1: # %else1990; RV64ZVE32F-NEXT: andi a2, a2, 21991; RV64ZVE32F-NEXT: bnez a2, .LBB28_41992; RV64ZVE32F-NEXT: .LBB28_2: # %else21993; RV64ZVE32F-NEXT: ret1994; RV64ZVE32F-NEXT: .LBB28_3: # %cond.load1995; RV64ZVE32F-NEXT: lw a0, 0(a0)1996; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma1997; RV64ZVE32F-NEXT: vmv.s.x v8, a01998; RV64ZVE32F-NEXT: andi a2, a2, 21999; RV64ZVE32F-NEXT: beqz a2, .LBB28_22000; RV64ZVE32F-NEXT: .LBB28_4: # %cond.load12001; RV64ZVE32F-NEXT: lw a0, 0(a1)2002; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma2003; RV64ZVE32F-NEXT: vmv.s.x v9, a02004; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma2005; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 12006; RV64ZVE32F-NEXT: ret2007 %v = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> %ptrs, i32 4, <2 x i1> %m, <2 x i32> %passthru)2008 ret <2 x i32> %v2009}2010 2011define <2 x i64> @mgather_v2i32_sextload_v2i64(<2 x ptr> %ptrs, <2 x i1> %m, <2 x i32> %passthru) {2012; RV32V-LABEL: mgather_v2i32_sextload_v2i64:2013; RV32V: # %bb.0:2014; RV32V-NEXT: vsetivli zero, 2, e32, mf2, ta, mu2015; RV32V-NEXT: vluxei32.v v9, (zero), v8, v0.t2016; RV32V-NEXT: vsetvli zero, zero, e64, m1, ta, ma2017; RV32V-NEXT: vsext.vf2 v8, v92018; RV32V-NEXT: ret2019;2020; RV64V-LABEL: mgather_v2i32_sextload_v2i64:2021; RV64V: # %bb.0:2022; RV64V-NEXT: vsetivli zero, 2, e32, mf2, ta, mu2023; RV64V-NEXT: vluxei64.v v9, (zero), v8, v0.t2024; RV64V-NEXT: vsetvli zero, zero, e64, m1, ta, ma2025; RV64V-NEXT: vsext.vf2 v8, v92026; RV64V-NEXT: ret2027;2028; RV32ZVE32F-LABEL: mgather_v2i32_sextload_v2i64:2029; RV32ZVE32F: # %bb.0:2030; RV32ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, mu2031; RV32ZVE32F-NEXT: vluxei32.v v9, (zero), v8, v0.t2032; RV32ZVE32F-NEXT: vslidedown.vi v8, v9, 12033; RV32ZVE32F-NEXT: vmv.x.s a1, v92034; RV32ZVE32F-NEXT: vmv.x.s a2, v82035; RV32ZVE32F-NEXT: srai a3, a1, 312036; RV32ZVE32F-NEXT: srai a4, a2, 312037; RV32ZVE32F-NEXT: sw a1, 0(a0)2038; RV32ZVE32F-NEXT: sw a3, 4(a0)2039; RV32ZVE32F-NEXT: sw a2, 8(a0)2040; RV32ZVE32F-NEXT: sw a4, 12(a0)2041; RV32ZVE32F-NEXT: ret2042;2043; RV64ZVE32F-LABEL: mgather_v2i32_sextload_v2i64:2044; RV64ZVE32F: # %bb.0:2045; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma2046; RV64ZVE32F-NEXT: vmv.x.s a2, v02047; RV64ZVE32F-NEXT: andi a3, a2, 12048; RV64ZVE32F-NEXT: beqz a3, .LBB29_22049; RV64ZVE32F-NEXT: # %bb.1: # %cond.load2050; RV64ZVE32F-NEXT: lw a0, 0(a0)2051; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma2052; RV64ZVE32F-NEXT: vmv.s.x v8, a02053; RV64ZVE32F-NEXT: .LBB29_2: # %else2054; RV64ZVE32F-NEXT: andi a2, a2, 22055; RV64ZVE32F-NEXT: beqz a2, .LBB29_42056; RV64ZVE32F-NEXT: # %bb.3: # %cond.load12057; RV64ZVE32F-NEXT: lw a0, 0(a1)2058; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma2059; RV64ZVE32F-NEXT: vmv.s.x v9, a02060; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma2061; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 12062; RV64ZVE32F-NEXT: .LBB29_4: # %else22063; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma2064; RV64ZVE32F-NEXT: vmv.x.s a0, v82065; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 12066; RV64ZVE32F-NEXT: vmv.x.s a1, v82067; RV64ZVE32F-NEXT: ret2068 %v = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> %ptrs, i32 4, <2 x i1> %m, <2 x i32> %passthru)2069 %ev = sext <2 x i32> %v to <2 x i64>2070 ret <2 x i64> %ev2071}2072 2073define <2 x i64> @mgather_v2i32_zextload_v2i64(<2 x ptr> %ptrs, <2 x i1> %m, <2 x i32> %passthru) {2074; RV32V-LABEL: mgather_v2i32_zextload_v2i64:2075; RV32V: # %bb.0:2076; RV32V-NEXT: vsetivli zero, 2, e32, mf2, ta, mu2077; RV32V-NEXT: vluxei32.v v9, (zero), v8, v0.t2078; RV32V-NEXT: vsetvli zero, zero, e64, m1, ta, ma2079; RV32V-NEXT: vzext.vf2 v8, v92080; RV32V-NEXT: ret2081;2082; RV64V-LABEL: mgather_v2i32_zextload_v2i64:2083; RV64V: # %bb.0:2084; RV64V-NEXT: vsetivli zero, 2, e32, mf2, ta, mu2085; RV64V-NEXT: vluxei64.v v9, (zero), v8, v0.t2086; RV64V-NEXT: vsetvli zero, zero, e64, m1, ta, ma2087; RV64V-NEXT: vzext.vf2 v8, v92088; RV64V-NEXT: ret2089;2090; RV32ZVE32F-LABEL: mgather_v2i32_zextload_v2i64:2091; RV32ZVE32F: # %bb.0:2092; RV32ZVE32F-NEXT: addi a1, a0, 82093; RV32ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, mu2094; RV32ZVE32F-NEXT: vluxei32.v v9, (zero), v8, v0.t2095; RV32ZVE32F-NEXT: sw zero, 4(a0)2096; RV32ZVE32F-NEXT: sw zero, 12(a0)2097; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma2098; RV32ZVE32F-NEXT: vse32.v v9, (a0)2099; RV32ZVE32F-NEXT: vslidedown.vi v8, v9, 12100; RV32ZVE32F-NEXT: vse32.v v8, (a1)2101; RV32ZVE32F-NEXT: ret2102;2103; RV64ZVE32F-LABEL: mgather_v2i32_zextload_v2i64:2104; RV64ZVE32F: # %bb.0:2105; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma2106; RV64ZVE32F-NEXT: vmv.x.s a2, v02107; RV64ZVE32F-NEXT: andi a3, a2, 12108; RV64ZVE32F-NEXT: beqz a3, .LBB30_22109; RV64ZVE32F-NEXT: # %bb.1: # %cond.load2110; RV64ZVE32F-NEXT: lw a0, 0(a0)2111; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma2112; RV64ZVE32F-NEXT: vmv.s.x v8, a02113; RV64ZVE32F-NEXT: .LBB30_2: # %else2114; RV64ZVE32F-NEXT: andi a2, a2, 22115; RV64ZVE32F-NEXT: beqz a2, .LBB30_42116; RV64ZVE32F-NEXT: # %bb.3: # %cond.load12117; RV64ZVE32F-NEXT: lw a0, 0(a1)2118; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma2119; RV64ZVE32F-NEXT: vmv.s.x v9, a02120; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma2121; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 12122; RV64ZVE32F-NEXT: .LBB30_4: # %else22123; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma2124; RV64ZVE32F-NEXT: vmv.x.s a0, v82125; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 12126; RV64ZVE32F-NEXT: slli a0, a0, 322127; RV64ZVE32F-NEXT: vmv.x.s a1, v82128; RV64ZVE32F-NEXT: srli a0, a0, 322129; RV64ZVE32F-NEXT: slli a1, a1, 322130; RV64ZVE32F-NEXT: srli a1, a1, 322131; RV64ZVE32F-NEXT: ret2132 %v = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> %ptrs, i32 4, <2 x i1> %m, <2 x i32> %passthru)2133 %ev = zext <2 x i32> %v to <2 x i64>2134 ret <2 x i64> %ev2135}2136 2137define <4 x i32> @mgather_v4i32(<4 x ptr> %ptrs, <4 x i1> %m, <4 x i32> %passthru) {2138; RV32-LABEL: mgather_v4i32:2139; RV32: # %bb.0:2140; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu2141; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t2142; RV32-NEXT: vmv.v.v v8, v92143; RV32-NEXT: ret2144;2145; RV64V-LABEL: mgather_v4i32:2146; RV64V: # %bb.0:2147; RV64V-NEXT: vsetivli zero, 4, e32, m1, ta, mu2148; RV64V-NEXT: vluxei64.v v10, (zero), v8, v0.t2149; RV64V-NEXT: vmv.v.v v8, v102150; RV64V-NEXT: ret2151;2152; RV64ZVE32F-LABEL: mgather_v4i32:2153; RV64ZVE32F: # %bb.0:2154; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma2155; RV64ZVE32F-NEXT: vmv.x.s a1, v02156; RV64ZVE32F-NEXT: andi a2, a1, 12157; RV64ZVE32F-NEXT: bnez a2, .LBB31_52158; RV64ZVE32F-NEXT: # %bb.1: # %else2159; RV64ZVE32F-NEXT: andi a2, a1, 22160; RV64ZVE32F-NEXT: bnez a2, .LBB31_62161; RV64ZVE32F-NEXT: .LBB31_2: # %else22162; RV64ZVE32F-NEXT: andi a2, a1, 42163; RV64ZVE32F-NEXT: bnez a2, .LBB31_72164; RV64ZVE32F-NEXT: .LBB31_3: # %else52165; RV64ZVE32F-NEXT: andi a1, a1, 82166; RV64ZVE32F-NEXT: bnez a1, .LBB31_82167; RV64ZVE32F-NEXT: .LBB31_4: # %else82168; RV64ZVE32F-NEXT: ret2169; RV64ZVE32F-NEXT: .LBB31_5: # %cond.load2170; RV64ZVE32F-NEXT: ld a2, 0(a0)2171; RV64ZVE32F-NEXT: lw a2, 0(a2)2172; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma2173; RV64ZVE32F-NEXT: vmv.s.x v8, a22174; RV64ZVE32F-NEXT: andi a2, a1, 22175; RV64ZVE32F-NEXT: beqz a2, .LBB31_22176; RV64ZVE32F-NEXT: .LBB31_6: # %cond.load12177; RV64ZVE32F-NEXT: ld a2, 8(a0)2178; RV64ZVE32F-NEXT: lw a2, 0(a2)2179; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma2180; RV64ZVE32F-NEXT: vmv.s.x v9, a22181; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma2182; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 12183; RV64ZVE32F-NEXT: andi a2, a1, 42184; RV64ZVE32F-NEXT: beqz a2, .LBB31_32185; RV64ZVE32F-NEXT: .LBB31_7: # %cond.load42186; RV64ZVE32F-NEXT: ld a2, 16(a0)2187; RV64ZVE32F-NEXT: lw a2, 0(a2)2188; RV64ZVE32F-NEXT: vsetivli zero, 3, e32, m1, tu, ma2189; RV64ZVE32F-NEXT: vmv.s.x v9, a22190; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 22191; RV64ZVE32F-NEXT: andi a1, a1, 82192; RV64ZVE32F-NEXT: beqz a1, .LBB31_42193; RV64ZVE32F-NEXT: .LBB31_8: # %cond.load72194; RV64ZVE32F-NEXT: ld a0, 24(a0)2195; RV64ZVE32F-NEXT: lw a0, 0(a0)2196; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, ta, ma2197; RV64ZVE32F-NEXT: vmv.s.x v9, a02198; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 32199; RV64ZVE32F-NEXT: ret2200 %v = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %m, <4 x i32> %passthru)2201 ret <4 x i32> %v2202}2203 2204define <4 x i32> @mgather_truemask_v4i32(<4 x ptr> %ptrs, <4 x i32> %passthru) {2205; RV32-LABEL: mgather_truemask_v4i32:2206; RV32: # %bb.0:2207; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma2208; RV32-NEXT: vluxei32.v v8, (zero), v82209; RV32-NEXT: ret2210;2211; RV64V-LABEL: mgather_truemask_v4i32:2212; RV64V: # %bb.0:2213; RV64V-NEXT: vsetivli zero, 4, e32, m1, ta, ma2214; RV64V-NEXT: vluxei64.v v10, (zero), v82215; RV64V-NEXT: vmv.v.v v8, v102216; RV64V-NEXT: ret2217;2218; RV64ZVE32F-LABEL: mgather_truemask_v4i32:2219; RV64ZVE32F: # %bb.0:2220; RV64ZVE32F-NEXT: ld a1, 0(a0)2221; RV64ZVE32F-NEXT: ld a2, 8(a0)2222; RV64ZVE32F-NEXT: ld a3, 16(a0)2223; RV64ZVE32F-NEXT: ld a0, 24(a0)2224; RV64ZVE32F-NEXT: lw a1, 0(a1)2225; RV64ZVE32F-NEXT: lw a2, 0(a2)2226; RV64ZVE32F-NEXT: lw a3, 0(a3)2227; RV64ZVE32F-NEXT: lw a0, 0(a0)2228; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, ta, ma2229; RV64ZVE32F-NEXT: vmv.v.x v8, a12230; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a22231; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a32232; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a02233; RV64ZVE32F-NEXT: ret2234 %v = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> splat (i1 1), <4 x i32> %passthru)2235 ret <4 x i32> %v2236}2237 2238define <4 x i32> @mgather_falsemask_v4i32(<4 x ptr> %ptrs, <4 x i32> %passthru) {2239; RV32-LABEL: mgather_falsemask_v4i32:2240; RV32: # %bb.0:2241; RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma2242; RV32-NEXT: vmv1r.v v8, v92243; RV32-NEXT: ret2244;2245; RV64V-LABEL: mgather_falsemask_v4i32:2246; RV64V: # %bb.0:2247; RV64V-NEXT: vsetivli zero, 1, e8, m1, ta, ma2248; RV64V-NEXT: vmv1r.v v8, v102249; RV64V-NEXT: ret2250;2251; RV64ZVE32F-LABEL: mgather_falsemask_v4i32:2252; RV64ZVE32F: # %bb.0:2253; RV64ZVE32F-NEXT: ret2254 %v = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> zeroinitializer, <4 x i32> %passthru)2255 ret <4 x i32> %v2256}2257 2258define <8 x i32> @mgather_v8i32(<8 x ptr> %ptrs, <8 x i1> %m, <8 x i32> %passthru) {2259; RV32-LABEL: mgather_v8i32:2260; RV32: # %bb.0:2261; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu2262; RV32-NEXT: vluxei32.v v10, (zero), v8, v0.t2263; RV32-NEXT: vmv.v.v v8, v102264; RV32-NEXT: ret2265;2266; RV64V-LABEL: mgather_v8i32:2267; RV64V: # %bb.0:2268; RV64V-NEXT: vsetivli zero, 8, e32, m2, ta, mu2269; RV64V-NEXT: vluxei64.v v12, (zero), v8, v0.t2270; RV64V-NEXT: vmv.v.v v8, v122271; RV64V-NEXT: ret2272;2273; RV64ZVE32F-LABEL: mgather_v8i32:2274; RV64ZVE32F: # %bb.0:2275; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma2276; RV64ZVE32F-NEXT: vmv.x.s a1, v02277; RV64ZVE32F-NEXT: andi a2, a1, 12278; RV64ZVE32F-NEXT: bnez a2, .LBB34_92279; RV64ZVE32F-NEXT: # %bb.1: # %else2280; RV64ZVE32F-NEXT: andi a2, a1, 22281; RV64ZVE32F-NEXT: bnez a2, .LBB34_102282; RV64ZVE32F-NEXT: .LBB34_2: # %else22283; RV64ZVE32F-NEXT: andi a2, a1, 42284; RV64ZVE32F-NEXT: bnez a2, .LBB34_112285; RV64ZVE32F-NEXT: .LBB34_3: # %else52286; RV64ZVE32F-NEXT: andi a2, a1, 82287; RV64ZVE32F-NEXT: bnez a2, .LBB34_122288; RV64ZVE32F-NEXT: .LBB34_4: # %else82289; RV64ZVE32F-NEXT: andi a2, a1, 162290; RV64ZVE32F-NEXT: bnez a2, .LBB34_132291; RV64ZVE32F-NEXT: .LBB34_5: # %else112292; RV64ZVE32F-NEXT: andi a2, a1, 322293; RV64ZVE32F-NEXT: bnez a2, .LBB34_142294; RV64ZVE32F-NEXT: .LBB34_6: # %else142295; RV64ZVE32F-NEXT: andi a2, a1, 642296; RV64ZVE32F-NEXT: bnez a2, .LBB34_152297; RV64ZVE32F-NEXT: .LBB34_7: # %else172298; RV64ZVE32F-NEXT: andi a1, a1, -1282299; RV64ZVE32F-NEXT: bnez a1, .LBB34_162300; RV64ZVE32F-NEXT: .LBB34_8: # %else202301; RV64ZVE32F-NEXT: ret2302; RV64ZVE32F-NEXT: .LBB34_9: # %cond.load2303; RV64ZVE32F-NEXT: ld a2, 0(a0)2304; RV64ZVE32F-NEXT: lw a2, 0(a2)2305; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma2306; RV64ZVE32F-NEXT: vmv.s.x v8, a22307; RV64ZVE32F-NEXT: andi a2, a1, 22308; RV64ZVE32F-NEXT: beqz a2, .LBB34_22309; RV64ZVE32F-NEXT: .LBB34_10: # %cond.load12310; RV64ZVE32F-NEXT: ld a2, 8(a0)2311; RV64ZVE32F-NEXT: lw a2, 0(a2)2312; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma2313; RV64ZVE32F-NEXT: vmv.s.x v10, a22314; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma2315; RV64ZVE32F-NEXT: vslideup.vi v8, v10, 12316; RV64ZVE32F-NEXT: andi a2, a1, 42317; RV64ZVE32F-NEXT: beqz a2, .LBB34_32318; RV64ZVE32F-NEXT: .LBB34_11: # %cond.load42319; RV64ZVE32F-NEXT: ld a2, 16(a0)2320; RV64ZVE32F-NEXT: lw a2, 0(a2)2321; RV64ZVE32F-NEXT: vsetivli zero, 3, e32, m1, tu, ma2322; RV64ZVE32F-NEXT: vmv.s.x v10, a22323; RV64ZVE32F-NEXT: vslideup.vi v8, v10, 22324; RV64ZVE32F-NEXT: andi a2, a1, 82325; RV64ZVE32F-NEXT: beqz a2, .LBB34_42326; RV64ZVE32F-NEXT: .LBB34_12: # %cond.load72327; RV64ZVE32F-NEXT: ld a2, 24(a0)2328; RV64ZVE32F-NEXT: lw a2, 0(a2)2329; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma2330; RV64ZVE32F-NEXT: vmv.s.x v10, a22331; RV64ZVE32F-NEXT: vslideup.vi v8, v10, 32332; RV64ZVE32F-NEXT: andi a2, a1, 162333; RV64ZVE32F-NEXT: beqz a2, .LBB34_52334; RV64ZVE32F-NEXT: .LBB34_13: # %cond.load102335; RV64ZVE32F-NEXT: ld a2, 32(a0)2336; RV64ZVE32F-NEXT: lw a2, 0(a2)2337; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma2338; RV64ZVE32F-NEXT: vmv.s.x v10, a22339; RV64ZVE32F-NEXT: vslideup.vi v8, v10, 42340; RV64ZVE32F-NEXT: andi a2, a1, 322341; RV64ZVE32F-NEXT: beqz a2, .LBB34_62342; RV64ZVE32F-NEXT: .LBB34_14: # %cond.load132343; RV64ZVE32F-NEXT: ld a2, 40(a0)2344; RV64ZVE32F-NEXT: lw a2, 0(a2)2345; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma2346; RV64ZVE32F-NEXT: vmv.s.x v10, a22347; RV64ZVE32F-NEXT: vslideup.vi v8, v10, 52348; RV64ZVE32F-NEXT: andi a2, a1, 642349; RV64ZVE32F-NEXT: beqz a2, .LBB34_72350; RV64ZVE32F-NEXT: .LBB34_15: # %cond.load162351; RV64ZVE32F-NEXT: ld a2, 48(a0)2352; RV64ZVE32F-NEXT: lw a2, 0(a2)2353; RV64ZVE32F-NEXT: vsetivli zero, 7, e32, m2, tu, ma2354; RV64ZVE32F-NEXT: vmv.s.x v10, a22355; RV64ZVE32F-NEXT: vslideup.vi v8, v10, 62356; RV64ZVE32F-NEXT: andi a1, a1, -1282357; RV64ZVE32F-NEXT: beqz a1, .LBB34_82358; RV64ZVE32F-NEXT: .LBB34_16: # %cond.load192359; RV64ZVE32F-NEXT: ld a0, 56(a0)2360; RV64ZVE32F-NEXT: lw a0, 0(a0)2361; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma2362; RV64ZVE32F-NEXT: vmv.s.x v10, a02363; RV64ZVE32F-NEXT: vslideup.vi v8, v10, 72364; RV64ZVE32F-NEXT: ret2365 %v = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> %m, <8 x i32> %passthru)2366 ret <8 x i32> %v2367}2368 2369define <8 x i32> @mgather_baseidx_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8 x i1> %m, <8 x i32> %passthru) {2370; RV32-LABEL: mgather_baseidx_v8i8_v8i32:2371; RV32: # %bb.0:2372; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu2373; RV32-NEXT: vsext.vf4 v12, v82374; RV32-NEXT: vsll.vi v8, v12, 22375; RV32-NEXT: vluxei32.v v10, (a0), v8, v0.t2376; RV32-NEXT: vmv.v.v v8, v102377; RV32-NEXT: ret2378;2379; RV64V-LABEL: mgather_baseidx_v8i8_v8i32:2380; RV64V: # %bb.0:2381; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma2382; RV64V-NEXT: vsext.vf8 v12, v82383; RV64V-NEXT: vsll.vi v12, v12, 22384; RV64V-NEXT: vsetvli zero, zero, e32, m2, ta, mu2385; RV64V-NEXT: vluxei64.v v10, (a0), v12, v0.t2386; RV64V-NEXT: vmv.v.v v8, v102387; RV64V-NEXT: ret2388;2389; RV64ZVE32F-LABEL: mgather_baseidx_v8i8_v8i32:2390; RV64ZVE32F: # %bb.0:2391; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma2392; RV64ZVE32F-NEXT: vmv.x.s a1, v02393; RV64ZVE32F-NEXT: andi a2, a1, 12394; RV64ZVE32F-NEXT: beqz a2, .LBB35_22395; RV64ZVE32F-NEXT: # %bb.1: # %cond.load2396; RV64ZVE32F-NEXT: vmv.x.s a2, v82397; RV64ZVE32F-NEXT: slli a2, a2, 22398; RV64ZVE32F-NEXT: add a2, a0, a22399; RV64ZVE32F-NEXT: lw a2, 0(a2)2400; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma2401; RV64ZVE32F-NEXT: vmv.s.x v10, a22402; RV64ZVE32F-NEXT: .LBB35_2: # %else2403; RV64ZVE32F-NEXT: andi a2, a1, 22404; RV64ZVE32F-NEXT: beqz a2, .LBB35_42405; RV64ZVE32F-NEXT: # %bb.3: # %cond.load12406; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma2407; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 12408; RV64ZVE32F-NEXT: vmv.x.s a2, v92409; RV64ZVE32F-NEXT: slli a2, a2, 22410; RV64ZVE32F-NEXT: add a2, a0, a22411; RV64ZVE32F-NEXT: lw a2, 0(a2)2412; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma2413; RV64ZVE32F-NEXT: vmv.s.x v9, a22414; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma2415; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 12416; RV64ZVE32F-NEXT: .LBB35_4: # %else22417; RV64ZVE32F-NEXT: andi a2, a1, 42418; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma2419; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 22420; RV64ZVE32F-NEXT: beqz a2, .LBB35_62421; RV64ZVE32F-NEXT: # %bb.5: # %cond.load42422; RV64ZVE32F-NEXT: vmv.x.s a2, v92423; RV64ZVE32F-NEXT: slli a2, a2, 22424; RV64ZVE32F-NEXT: add a2, a0, a22425; RV64ZVE32F-NEXT: lw a2, 0(a2)2426; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma2427; RV64ZVE32F-NEXT: vmv.s.x v12, a22428; RV64ZVE32F-NEXT: vsetivli zero, 3, e32, m1, tu, ma2429; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 22430; RV64ZVE32F-NEXT: .LBB35_6: # %else52431; RV64ZVE32F-NEXT: andi a2, a1, 82432; RV64ZVE32F-NEXT: beqz a2, .LBB35_82433; RV64ZVE32F-NEXT: # %bb.7: # %cond.load72434; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma2435; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 12436; RV64ZVE32F-NEXT: vmv.x.s a2, v92437; RV64ZVE32F-NEXT: slli a2, a2, 22438; RV64ZVE32F-NEXT: add a2, a0, a22439; RV64ZVE32F-NEXT: lw a2, 0(a2)2440; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma2441; RV64ZVE32F-NEXT: vmv.s.x v9, a22442; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma2443; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 32444; RV64ZVE32F-NEXT: .LBB35_8: # %else82445; RV64ZVE32F-NEXT: andi a2, a1, 162446; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma2447; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 42448; RV64ZVE32F-NEXT: beqz a2, .LBB35_102449; RV64ZVE32F-NEXT: # %bb.9: # %cond.load102450; RV64ZVE32F-NEXT: vmv.x.s a2, v82451; RV64ZVE32F-NEXT: slli a2, a2, 22452; RV64ZVE32F-NEXT: add a2, a0, a22453; RV64ZVE32F-NEXT: lw a2, 0(a2)2454; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma2455; RV64ZVE32F-NEXT: vmv.s.x v12, a22456; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma2457; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 42458; RV64ZVE32F-NEXT: .LBB35_10: # %else112459; RV64ZVE32F-NEXT: andi a2, a1, 322460; RV64ZVE32F-NEXT: beqz a2, .LBB35_122461; RV64ZVE32F-NEXT: # %bb.11: # %cond.load132462; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma2463; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 12464; RV64ZVE32F-NEXT: vmv.x.s a2, v92465; RV64ZVE32F-NEXT: slli a2, a2, 22466; RV64ZVE32F-NEXT: add a2, a0, a22467; RV64ZVE32F-NEXT: lw a2, 0(a2)2468; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma2469; RV64ZVE32F-NEXT: vmv.s.x v12, a22470; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma2471; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 52472; RV64ZVE32F-NEXT: .LBB35_12: # %else142473; RV64ZVE32F-NEXT: andi a2, a1, 642474; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma2475; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 22476; RV64ZVE32F-NEXT: beqz a2, .LBB35_142477; RV64ZVE32F-NEXT: # %bb.13: # %cond.load162478; RV64ZVE32F-NEXT: vmv.x.s a2, v82479; RV64ZVE32F-NEXT: slli a2, a2, 22480; RV64ZVE32F-NEXT: add a2, a0, a22481; RV64ZVE32F-NEXT: lw a2, 0(a2)2482; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma2483; RV64ZVE32F-NEXT: vmv.s.x v12, a22484; RV64ZVE32F-NEXT: vsetivli zero, 7, e32, m2, tu, ma2485; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 62486; RV64ZVE32F-NEXT: .LBB35_14: # %else172487; RV64ZVE32F-NEXT: andi a1, a1, -1282488; RV64ZVE32F-NEXT: beqz a1, .LBB35_162489; RV64ZVE32F-NEXT: # %bb.15: # %cond.load192490; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma2491; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 12492; RV64ZVE32F-NEXT: vmv.x.s a1, v82493; RV64ZVE32F-NEXT: slli a1, a1, 22494; RV64ZVE32F-NEXT: add a0, a0, a12495; RV64ZVE32F-NEXT: lw a0, 0(a0)2496; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma2497; RV64ZVE32F-NEXT: vmv.s.x v8, a02498; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma2499; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 72500; RV64ZVE32F-NEXT: .LBB35_16: # %else202501; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma2502; RV64ZVE32F-NEXT: vmv2r.v v8, v102503; RV64ZVE32F-NEXT: ret2504 %ptrs = getelementptr inbounds i32, ptr %base, <8 x i8> %idxs2505 %v = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> %m, <8 x i32> %passthru)2506 ret <8 x i32> %v2507}2508 2509define <8 x i32> @mgather_baseidx_sext_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8 x i1> %m, <8 x i32> %passthru) {2510; RV32-LABEL: mgather_baseidx_sext_v8i8_v8i32:2511; RV32: # %bb.0:2512; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu2513; RV32-NEXT: vsext.vf4 v12, v82514; RV32-NEXT: vsll.vi v8, v12, 22515; RV32-NEXT: vluxei32.v v10, (a0), v8, v0.t2516; RV32-NEXT: vmv.v.v v8, v102517; RV32-NEXT: ret2518;2519; RV64V-LABEL: mgather_baseidx_sext_v8i8_v8i32:2520; RV64V: # %bb.0:2521; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma2522; RV64V-NEXT: vsext.vf8 v12, v82523; RV64V-NEXT: vsll.vi v12, v12, 22524; RV64V-NEXT: vsetvli zero, zero, e32, m2, ta, mu2525; RV64V-NEXT: vluxei64.v v10, (a0), v12, v0.t2526; RV64V-NEXT: vmv.v.v v8, v102527; RV64V-NEXT: ret2528;2529; RV64ZVE32F-LABEL: mgather_baseidx_sext_v8i8_v8i32:2530; RV64ZVE32F: # %bb.0:2531; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma2532; RV64ZVE32F-NEXT: vmv.x.s a1, v02533; RV64ZVE32F-NEXT: andi a2, a1, 12534; RV64ZVE32F-NEXT: beqz a2, .LBB36_22535; RV64ZVE32F-NEXT: # %bb.1: # %cond.load2536; RV64ZVE32F-NEXT: vmv.x.s a2, v82537; RV64ZVE32F-NEXT: slli a2, a2, 22538; RV64ZVE32F-NEXT: add a2, a0, a22539; RV64ZVE32F-NEXT: lw a2, 0(a2)2540; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma2541; RV64ZVE32F-NEXT: vmv.s.x v10, a22542; RV64ZVE32F-NEXT: .LBB36_2: # %else2543; RV64ZVE32F-NEXT: andi a2, a1, 22544; RV64ZVE32F-NEXT: beqz a2, .LBB36_42545; RV64ZVE32F-NEXT: # %bb.3: # %cond.load12546; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma2547; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 12548; RV64ZVE32F-NEXT: vmv.x.s a2, v92549; RV64ZVE32F-NEXT: slli a2, a2, 22550; RV64ZVE32F-NEXT: add a2, a0, a22551; RV64ZVE32F-NEXT: lw a2, 0(a2)2552; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma2553; RV64ZVE32F-NEXT: vmv.s.x v9, a22554; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma2555; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 12556; RV64ZVE32F-NEXT: .LBB36_4: # %else22557; RV64ZVE32F-NEXT: andi a2, a1, 42558; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma2559; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 22560; RV64ZVE32F-NEXT: beqz a2, .LBB36_62561; RV64ZVE32F-NEXT: # %bb.5: # %cond.load42562; RV64ZVE32F-NEXT: vmv.x.s a2, v92563; RV64ZVE32F-NEXT: slli a2, a2, 22564; RV64ZVE32F-NEXT: add a2, a0, a22565; RV64ZVE32F-NEXT: lw a2, 0(a2)2566; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma2567; RV64ZVE32F-NEXT: vmv.s.x v12, a22568; RV64ZVE32F-NEXT: vsetivli zero, 3, e32, m1, tu, ma2569; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 22570; RV64ZVE32F-NEXT: .LBB36_6: # %else52571; RV64ZVE32F-NEXT: andi a2, a1, 82572; RV64ZVE32F-NEXT: beqz a2, .LBB36_82573; RV64ZVE32F-NEXT: # %bb.7: # %cond.load72574; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma2575; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 12576; RV64ZVE32F-NEXT: vmv.x.s a2, v92577; RV64ZVE32F-NEXT: slli a2, a2, 22578; RV64ZVE32F-NEXT: add a2, a0, a22579; RV64ZVE32F-NEXT: lw a2, 0(a2)2580; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma2581; RV64ZVE32F-NEXT: vmv.s.x v9, a22582; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma2583; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 32584; RV64ZVE32F-NEXT: .LBB36_8: # %else82585; RV64ZVE32F-NEXT: andi a2, a1, 162586; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma2587; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 42588; RV64ZVE32F-NEXT: beqz a2, .LBB36_102589; RV64ZVE32F-NEXT: # %bb.9: # %cond.load102590; RV64ZVE32F-NEXT: vmv.x.s a2, v82591; RV64ZVE32F-NEXT: slli a2, a2, 22592; RV64ZVE32F-NEXT: add a2, a0, a22593; RV64ZVE32F-NEXT: lw a2, 0(a2)2594; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma2595; RV64ZVE32F-NEXT: vmv.s.x v12, a22596; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma2597; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 42598; RV64ZVE32F-NEXT: .LBB36_10: # %else112599; RV64ZVE32F-NEXT: andi a2, a1, 322600; RV64ZVE32F-NEXT: beqz a2, .LBB36_122601; RV64ZVE32F-NEXT: # %bb.11: # %cond.load132602; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma2603; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 12604; RV64ZVE32F-NEXT: vmv.x.s a2, v92605; RV64ZVE32F-NEXT: slli a2, a2, 22606; RV64ZVE32F-NEXT: add a2, a0, a22607; RV64ZVE32F-NEXT: lw a2, 0(a2)2608; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma2609; RV64ZVE32F-NEXT: vmv.s.x v12, a22610; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma2611; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 52612; RV64ZVE32F-NEXT: .LBB36_12: # %else142613; RV64ZVE32F-NEXT: andi a2, a1, 642614; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma2615; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 22616; RV64ZVE32F-NEXT: beqz a2, .LBB36_142617; RV64ZVE32F-NEXT: # %bb.13: # %cond.load162618; RV64ZVE32F-NEXT: vmv.x.s a2, v82619; RV64ZVE32F-NEXT: slli a2, a2, 22620; RV64ZVE32F-NEXT: add a2, a0, a22621; RV64ZVE32F-NEXT: lw a2, 0(a2)2622; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma2623; RV64ZVE32F-NEXT: vmv.s.x v12, a22624; RV64ZVE32F-NEXT: vsetivli zero, 7, e32, m2, tu, ma2625; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 62626; RV64ZVE32F-NEXT: .LBB36_14: # %else172627; RV64ZVE32F-NEXT: andi a1, a1, -1282628; RV64ZVE32F-NEXT: beqz a1, .LBB36_162629; RV64ZVE32F-NEXT: # %bb.15: # %cond.load192630; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma2631; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 12632; RV64ZVE32F-NEXT: vmv.x.s a1, v82633; RV64ZVE32F-NEXT: slli a1, a1, 22634; RV64ZVE32F-NEXT: add a0, a0, a12635; RV64ZVE32F-NEXT: lw a0, 0(a0)2636; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma2637; RV64ZVE32F-NEXT: vmv.s.x v8, a02638; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma2639; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 72640; RV64ZVE32F-NEXT: .LBB36_16: # %else202641; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma2642; RV64ZVE32F-NEXT: vmv2r.v v8, v102643; RV64ZVE32F-NEXT: ret2644 %eidxs = sext <8 x i8> %idxs to <8 x i32>2645 %ptrs = getelementptr inbounds i32, ptr %base, <8 x i32> %eidxs2646 %v = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> %m, <8 x i32> %passthru)2647 ret <8 x i32> %v2648}2649 2650define <8 x i32> @mgather_baseidx_zext_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8 x i1> %m, <8 x i32> %passthru) {2651; RV32-LABEL: mgather_baseidx_zext_v8i8_v8i32:2652; RV32: # %bb.0:2653; RV32-NEXT: li a1, 42654; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma2655; RV32-NEXT: vwmulu.vx v9, v8, a12656; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, mu2657; RV32-NEXT: vluxei16.v v10, (a0), v9, v0.t2658; RV32-NEXT: vmv.v.v v8, v102659; RV32-NEXT: ret2660;2661; RV64V-LABEL: mgather_baseidx_zext_v8i8_v8i32:2662; RV64V: # %bb.0:2663; RV64V-NEXT: li a1, 42664; RV64V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma2665; RV64V-NEXT: vwmulu.vx v9, v8, a12666; RV64V-NEXT: vsetvli zero, zero, e32, m2, ta, mu2667; RV64V-NEXT: vluxei16.v v10, (a0), v9, v0.t2668; RV64V-NEXT: vmv.v.v v8, v102669; RV64V-NEXT: ret2670;2671; RV64ZVE32F-LABEL: mgather_baseidx_zext_v8i8_v8i32:2672; RV64ZVE32F: # %bb.0:2673; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma2674; RV64ZVE32F-NEXT: vmv.x.s a1, v02675; RV64ZVE32F-NEXT: andi a2, a1, 12676; RV64ZVE32F-NEXT: beqz a2, .LBB37_22677; RV64ZVE32F-NEXT: # %bb.1: # %cond.load2678; RV64ZVE32F-NEXT: vmv.x.s a2, v82679; RV64ZVE32F-NEXT: zext.b a2, a22680; RV64ZVE32F-NEXT: slli a2, a2, 22681; RV64ZVE32F-NEXT: add a2, a0, a22682; RV64ZVE32F-NEXT: lw a2, 0(a2)2683; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma2684; RV64ZVE32F-NEXT: vmv.s.x v10, a22685; RV64ZVE32F-NEXT: .LBB37_2: # %else2686; RV64ZVE32F-NEXT: andi a2, a1, 22687; RV64ZVE32F-NEXT: beqz a2, .LBB37_42688; RV64ZVE32F-NEXT: # %bb.3: # %cond.load12689; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma2690; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 12691; RV64ZVE32F-NEXT: vmv.x.s a2, v92692; RV64ZVE32F-NEXT: zext.b a2, a22693; RV64ZVE32F-NEXT: slli a2, a2, 22694; RV64ZVE32F-NEXT: add a2, a0, a22695; RV64ZVE32F-NEXT: lw a2, 0(a2)2696; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma2697; RV64ZVE32F-NEXT: vmv.s.x v9, a22698; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma2699; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 12700; RV64ZVE32F-NEXT: .LBB37_4: # %else22701; RV64ZVE32F-NEXT: andi a2, a1, 42702; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma2703; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 22704; RV64ZVE32F-NEXT: beqz a2, .LBB37_62705; RV64ZVE32F-NEXT: # %bb.5: # %cond.load42706; RV64ZVE32F-NEXT: vmv.x.s a2, v92707; RV64ZVE32F-NEXT: zext.b a2, a22708; RV64ZVE32F-NEXT: slli a2, a2, 22709; RV64ZVE32F-NEXT: add a2, a0, a22710; RV64ZVE32F-NEXT: lw a2, 0(a2)2711; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma2712; RV64ZVE32F-NEXT: vmv.s.x v12, a22713; RV64ZVE32F-NEXT: vsetivli zero, 3, e32, m1, tu, ma2714; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 22715; RV64ZVE32F-NEXT: .LBB37_6: # %else52716; RV64ZVE32F-NEXT: andi a2, a1, 82717; RV64ZVE32F-NEXT: beqz a2, .LBB37_82718; RV64ZVE32F-NEXT: # %bb.7: # %cond.load72719; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma2720; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 12721; RV64ZVE32F-NEXT: vmv.x.s a2, v92722; RV64ZVE32F-NEXT: zext.b a2, a22723; RV64ZVE32F-NEXT: slli a2, a2, 22724; RV64ZVE32F-NEXT: add a2, a0, a22725; RV64ZVE32F-NEXT: lw a2, 0(a2)2726; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma2727; RV64ZVE32F-NEXT: vmv.s.x v9, a22728; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma2729; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 32730; RV64ZVE32F-NEXT: .LBB37_8: # %else82731; RV64ZVE32F-NEXT: andi a2, a1, 162732; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma2733; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 42734; RV64ZVE32F-NEXT: beqz a2, .LBB37_102735; RV64ZVE32F-NEXT: # %bb.9: # %cond.load102736; RV64ZVE32F-NEXT: vmv.x.s a2, v82737; RV64ZVE32F-NEXT: zext.b a2, a22738; RV64ZVE32F-NEXT: slli a2, a2, 22739; RV64ZVE32F-NEXT: add a2, a0, a22740; RV64ZVE32F-NEXT: lw a2, 0(a2)2741; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma2742; RV64ZVE32F-NEXT: vmv.s.x v12, a22743; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma2744; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 42745; RV64ZVE32F-NEXT: .LBB37_10: # %else112746; RV64ZVE32F-NEXT: andi a2, a1, 322747; RV64ZVE32F-NEXT: beqz a2, .LBB37_122748; RV64ZVE32F-NEXT: # %bb.11: # %cond.load132749; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma2750; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 12751; RV64ZVE32F-NEXT: vmv.x.s a2, v92752; RV64ZVE32F-NEXT: zext.b a2, a22753; RV64ZVE32F-NEXT: slli a2, a2, 22754; RV64ZVE32F-NEXT: add a2, a0, a22755; RV64ZVE32F-NEXT: lw a2, 0(a2)2756; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma2757; RV64ZVE32F-NEXT: vmv.s.x v12, a22758; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma2759; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 52760; RV64ZVE32F-NEXT: .LBB37_12: # %else142761; RV64ZVE32F-NEXT: andi a2, a1, 642762; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma2763; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 22764; RV64ZVE32F-NEXT: beqz a2, .LBB37_142765; RV64ZVE32F-NEXT: # %bb.13: # %cond.load162766; RV64ZVE32F-NEXT: vmv.x.s a2, v82767; RV64ZVE32F-NEXT: zext.b a2, a22768; RV64ZVE32F-NEXT: slli a2, a2, 22769; RV64ZVE32F-NEXT: add a2, a0, a22770; RV64ZVE32F-NEXT: lw a2, 0(a2)2771; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma2772; RV64ZVE32F-NEXT: vmv.s.x v12, a22773; RV64ZVE32F-NEXT: vsetivli zero, 7, e32, m2, tu, ma2774; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 62775; RV64ZVE32F-NEXT: .LBB37_14: # %else172776; RV64ZVE32F-NEXT: andi a1, a1, -1282777; RV64ZVE32F-NEXT: beqz a1, .LBB37_162778; RV64ZVE32F-NEXT: # %bb.15: # %cond.load192779; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma2780; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 12781; RV64ZVE32F-NEXT: vmv.x.s a1, v82782; RV64ZVE32F-NEXT: zext.b a1, a12783; RV64ZVE32F-NEXT: slli a1, a1, 22784; RV64ZVE32F-NEXT: add a0, a0, a12785; RV64ZVE32F-NEXT: lw a0, 0(a0)2786; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma2787; RV64ZVE32F-NEXT: vmv.s.x v8, a02788; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma2789; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 72790; RV64ZVE32F-NEXT: .LBB37_16: # %else202791; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma2792; RV64ZVE32F-NEXT: vmv2r.v v8, v102793; RV64ZVE32F-NEXT: ret2794 %eidxs = zext <8 x i8> %idxs to <8 x i32>2795 %ptrs = getelementptr inbounds i32, ptr %base, <8 x i32> %eidxs2796 %v = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> %m, <8 x i32> %passthru)2797 ret <8 x i32> %v2798}2799 2800define <8 x i32> @mgather_baseidx_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <8 x i1> %m, <8 x i32> %passthru) {2801; RV32-LABEL: mgather_baseidx_v8i16_v8i32:2802; RV32: # %bb.0:2803; RV32-NEXT: li a1, 42804; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma2805; RV32-NEXT: vwmulsu.vx v12, v8, a12806; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, mu2807; RV32-NEXT: vluxei32.v v10, (a0), v12, v0.t2808; RV32-NEXT: vmv.v.v v8, v102809; RV32-NEXT: ret2810;2811; RV64V-LABEL: mgather_baseidx_v8i16_v8i32:2812; RV64V: # %bb.0:2813; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma2814; RV64V-NEXT: vsext.vf4 v12, v82815; RV64V-NEXT: vsll.vi v12, v12, 22816; RV64V-NEXT: vsetvli zero, zero, e32, m2, ta, mu2817; RV64V-NEXT: vluxei64.v v10, (a0), v12, v0.t2818; RV64V-NEXT: vmv.v.v v8, v102819; RV64V-NEXT: ret2820;2821; RV64ZVE32F-LABEL: mgather_baseidx_v8i16_v8i32:2822; RV64ZVE32F: # %bb.0:2823; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma2824; RV64ZVE32F-NEXT: vmv.x.s a1, v02825; RV64ZVE32F-NEXT: andi a2, a1, 12826; RV64ZVE32F-NEXT: beqz a2, .LBB38_22827; RV64ZVE32F-NEXT: # %bb.1: # %cond.load2828; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma2829; RV64ZVE32F-NEXT: vmv.x.s a2, v82830; RV64ZVE32F-NEXT: slli a2, a2, 22831; RV64ZVE32F-NEXT: add a2, a0, a22832; RV64ZVE32F-NEXT: lw a2, 0(a2)2833; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma2834; RV64ZVE32F-NEXT: vmv.s.x v10, a22835; RV64ZVE32F-NEXT: .LBB38_2: # %else2836; RV64ZVE32F-NEXT: andi a2, a1, 22837; RV64ZVE32F-NEXT: beqz a2, .LBB38_42838; RV64ZVE32F-NEXT: # %bb.3: # %cond.load12839; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma2840; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 12841; RV64ZVE32F-NEXT: vmv.x.s a2, v92842; RV64ZVE32F-NEXT: slli a2, a2, 22843; RV64ZVE32F-NEXT: add a2, a0, a22844; RV64ZVE32F-NEXT: lw a2, 0(a2)2845; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma2846; RV64ZVE32F-NEXT: vmv.s.x v9, a22847; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma2848; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 12849; RV64ZVE32F-NEXT: .LBB38_4: # %else22850; RV64ZVE32F-NEXT: andi a2, a1, 42851; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma2852; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 22853; RV64ZVE32F-NEXT: beqz a2, .LBB38_62854; RV64ZVE32F-NEXT: # %bb.5: # %cond.load42855; RV64ZVE32F-NEXT: vmv.x.s a2, v92856; RV64ZVE32F-NEXT: slli a2, a2, 22857; RV64ZVE32F-NEXT: add a2, a0, a22858; RV64ZVE32F-NEXT: lw a2, 0(a2)2859; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma2860; RV64ZVE32F-NEXT: vmv.s.x v12, a22861; RV64ZVE32F-NEXT: vsetivli zero, 3, e32, m1, tu, ma2862; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 22863; RV64ZVE32F-NEXT: .LBB38_6: # %else52864; RV64ZVE32F-NEXT: andi a2, a1, 82865; RV64ZVE32F-NEXT: beqz a2, .LBB38_82866; RV64ZVE32F-NEXT: # %bb.7: # %cond.load72867; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma2868; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 12869; RV64ZVE32F-NEXT: vmv.x.s a2, v92870; RV64ZVE32F-NEXT: slli a2, a2, 22871; RV64ZVE32F-NEXT: add a2, a0, a22872; RV64ZVE32F-NEXT: lw a2, 0(a2)2873; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma2874; RV64ZVE32F-NEXT: vmv.s.x v9, a22875; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma2876; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 32877; RV64ZVE32F-NEXT: .LBB38_8: # %else82878; RV64ZVE32F-NEXT: andi a2, a1, 162879; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma2880; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 42881; RV64ZVE32F-NEXT: beqz a2, .LBB38_102882; RV64ZVE32F-NEXT: # %bb.9: # %cond.load102883; RV64ZVE32F-NEXT: vmv.x.s a2, v82884; RV64ZVE32F-NEXT: slli a2, a2, 22885; RV64ZVE32F-NEXT: add a2, a0, a22886; RV64ZVE32F-NEXT: lw a2, 0(a2)2887; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma2888; RV64ZVE32F-NEXT: vmv.s.x v12, a22889; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma2890; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 42891; RV64ZVE32F-NEXT: .LBB38_10: # %else112892; RV64ZVE32F-NEXT: andi a2, a1, 322893; RV64ZVE32F-NEXT: beqz a2, .LBB38_122894; RV64ZVE32F-NEXT: # %bb.11: # %cond.load132895; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma2896; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 12897; RV64ZVE32F-NEXT: vmv.x.s a2, v92898; RV64ZVE32F-NEXT: slli a2, a2, 22899; RV64ZVE32F-NEXT: add a2, a0, a22900; RV64ZVE32F-NEXT: lw a2, 0(a2)2901; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma2902; RV64ZVE32F-NEXT: vmv.s.x v12, a22903; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma2904; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 52905; RV64ZVE32F-NEXT: .LBB38_12: # %else142906; RV64ZVE32F-NEXT: andi a2, a1, 642907; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma2908; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 22909; RV64ZVE32F-NEXT: beqz a2, .LBB38_142910; RV64ZVE32F-NEXT: # %bb.13: # %cond.load162911; RV64ZVE32F-NEXT: vmv.x.s a2, v82912; RV64ZVE32F-NEXT: slli a2, a2, 22913; RV64ZVE32F-NEXT: add a2, a0, a22914; RV64ZVE32F-NEXT: lw a2, 0(a2)2915; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma2916; RV64ZVE32F-NEXT: vmv.s.x v12, a22917; RV64ZVE32F-NEXT: vsetivli zero, 7, e32, m2, tu, ma2918; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 62919; RV64ZVE32F-NEXT: .LBB38_14: # %else172920; RV64ZVE32F-NEXT: andi a1, a1, -1282921; RV64ZVE32F-NEXT: beqz a1, .LBB38_162922; RV64ZVE32F-NEXT: # %bb.15: # %cond.load192923; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma2924; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 12925; RV64ZVE32F-NEXT: vmv.x.s a1, v82926; RV64ZVE32F-NEXT: slli a1, a1, 22927; RV64ZVE32F-NEXT: add a0, a0, a12928; RV64ZVE32F-NEXT: lw a0, 0(a0)2929; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma2930; RV64ZVE32F-NEXT: vmv.s.x v8, a02931; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma2932; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 72933; RV64ZVE32F-NEXT: .LBB38_16: # %else202934; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma2935; RV64ZVE32F-NEXT: vmv2r.v v8, v102936; RV64ZVE32F-NEXT: ret2937 %ptrs = getelementptr inbounds i32, ptr %base, <8 x i16> %idxs2938 %v = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> %m, <8 x i32> %passthru)2939 ret <8 x i32> %v2940}2941 2942define <8 x i32> @mgather_baseidx_sext_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <8 x i1> %m, <8 x i32> %passthru) {2943; RV32-LABEL: mgather_baseidx_sext_v8i16_v8i32:2944; RV32: # %bb.0:2945; RV32-NEXT: li a1, 42946; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma2947; RV32-NEXT: vwmulsu.vx v12, v8, a12948; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, mu2949; RV32-NEXT: vluxei32.v v10, (a0), v12, v0.t2950; RV32-NEXT: vmv.v.v v8, v102951; RV32-NEXT: ret2952;2953; RV64V-LABEL: mgather_baseidx_sext_v8i16_v8i32:2954; RV64V: # %bb.0:2955; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma2956; RV64V-NEXT: vsext.vf4 v12, v82957; RV64V-NEXT: vsll.vi v12, v12, 22958; RV64V-NEXT: vsetvli zero, zero, e32, m2, ta, mu2959; RV64V-NEXT: vluxei64.v v10, (a0), v12, v0.t2960; RV64V-NEXT: vmv.v.v v8, v102961; RV64V-NEXT: ret2962;2963; RV64ZVE32F-LABEL: mgather_baseidx_sext_v8i16_v8i32:2964; RV64ZVE32F: # %bb.0:2965; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma2966; RV64ZVE32F-NEXT: vmv.x.s a1, v02967; RV64ZVE32F-NEXT: andi a2, a1, 12968; RV64ZVE32F-NEXT: beqz a2, .LBB39_22969; RV64ZVE32F-NEXT: # %bb.1: # %cond.load2970; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma2971; RV64ZVE32F-NEXT: vmv.x.s a2, v82972; RV64ZVE32F-NEXT: slli a2, a2, 22973; RV64ZVE32F-NEXT: add a2, a0, a22974; RV64ZVE32F-NEXT: lw a2, 0(a2)2975; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma2976; RV64ZVE32F-NEXT: vmv.s.x v10, a22977; RV64ZVE32F-NEXT: .LBB39_2: # %else2978; RV64ZVE32F-NEXT: andi a2, a1, 22979; RV64ZVE32F-NEXT: beqz a2, .LBB39_42980; RV64ZVE32F-NEXT: # %bb.3: # %cond.load12981; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma2982; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 12983; RV64ZVE32F-NEXT: vmv.x.s a2, v92984; RV64ZVE32F-NEXT: slli a2, a2, 22985; RV64ZVE32F-NEXT: add a2, a0, a22986; RV64ZVE32F-NEXT: lw a2, 0(a2)2987; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma2988; RV64ZVE32F-NEXT: vmv.s.x v9, a22989; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma2990; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 12991; RV64ZVE32F-NEXT: .LBB39_4: # %else22992; RV64ZVE32F-NEXT: andi a2, a1, 42993; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma2994; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 22995; RV64ZVE32F-NEXT: beqz a2, .LBB39_62996; RV64ZVE32F-NEXT: # %bb.5: # %cond.load42997; RV64ZVE32F-NEXT: vmv.x.s a2, v92998; RV64ZVE32F-NEXT: slli a2, a2, 22999; RV64ZVE32F-NEXT: add a2, a0, a23000; RV64ZVE32F-NEXT: lw a2, 0(a2)3001; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma3002; RV64ZVE32F-NEXT: vmv.s.x v12, a23003; RV64ZVE32F-NEXT: vsetivli zero, 3, e32, m1, tu, ma3004; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 23005; RV64ZVE32F-NEXT: .LBB39_6: # %else53006; RV64ZVE32F-NEXT: andi a2, a1, 83007; RV64ZVE32F-NEXT: beqz a2, .LBB39_83008; RV64ZVE32F-NEXT: # %bb.7: # %cond.load73009; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma3010; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 13011; RV64ZVE32F-NEXT: vmv.x.s a2, v93012; RV64ZVE32F-NEXT: slli a2, a2, 23013; RV64ZVE32F-NEXT: add a2, a0, a23014; RV64ZVE32F-NEXT: lw a2, 0(a2)3015; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma3016; RV64ZVE32F-NEXT: vmv.s.x v9, a23017; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma3018; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 33019; RV64ZVE32F-NEXT: .LBB39_8: # %else83020; RV64ZVE32F-NEXT: andi a2, a1, 163021; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma3022; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 43023; RV64ZVE32F-NEXT: beqz a2, .LBB39_103024; RV64ZVE32F-NEXT: # %bb.9: # %cond.load103025; RV64ZVE32F-NEXT: vmv.x.s a2, v83026; RV64ZVE32F-NEXT: slli a2, a2, 23027; RV64ZVE32F-NEXT: add a2, a0, a23028; RV64ZVE32F-NEXT: lw a2, 0(a2)3029; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma3030; RV64ZVE32F-NEXT: vmv.s.x v12, a23031; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma3032; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 43033; RV64ZVE32F-NEXT: .LBB39_10: # %else113034; RV64ZVE32F-NEXT: andi a2, a1, 323035; RV64ZVE32F-NEXT: beqz a2, .LBB39_123036; RV64ZVE32F-NEXT: # %bb.11: # %cond.load133037; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma3038; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 13039; RV64ZVE32F-NEXT: vmv.x.s a2, v93040; RV64ZVE32F-NEXT: slli a2, a2, 23041; RV64ZVE32F-NEXT: add a2, a0, a23042; RV64ZVE32F-NEXT: lw a2, 0(a2)3043; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma3044; RV64ZVE32F-NEXT: vmv.s.x v12, a23045; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma3046; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 53047; RV64ZVE32F-NEXT: .LBB39_12: # %else143048; RV64ZVE32F-NEXT: andi a2, a1, 643049; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma3050; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 23051; RV64ZVE32F-NEXT: beqz a2, .LBB39_143052; RV64ZVE32F-NEXT: # %bb.13: # %cond.load163053; RV64ZVE32F-NEXT: vmv.x.s a2, v83054; RV64ZVE32F-NEXT: slli a2, a2, 23055; RV64ZVE32F-NEXT: add a2, a0, a23056; RV64ZVE32F-NEXT: lw a2, 0(a2)3057; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma3058; RV64ZVE32F-NEXT: vmv.s.x v12, a23059; RV64ZVE32F-NEXT: vsetivli zero, 7, e32, m2, tu, ma3060; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 63061; RV64ZVE32F-NEXT: .LBB39_14: # %else173062; RV64ZVE32F-NEXT: andi a1, a1, -1283063; RV64ZVE32F-NEXT: beqz a1, .LBB39_163064; RV64ZVE32F-NEXT: # %bb.15: # %cond.load193065; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma3066; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 13067; RV64ZVE32F-NEXT: vmv.x.s a1, v83068; RV64ZVE32F-NEXT: slli a1, a1, 23069; RV64ZVE32F-NEXT: add a0, a0, a13070; RV64ZVE32F-NEXT: lw a0, 0(a0)3071; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma3072; RV64ZVE32F-NEXT: vmv.s.x v8, a03073; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma3074; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 73075; RV64ZVE32F-NEXT: .LBB39_16: # %else203076; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma3077; RV64ZVE32F-NEXT: vmv2r.v v8, v103078; RV64ZVE32F-NEXT: ret3079 %eidxs = sext <8 x i16> %idxs to <8 x i32>3080 %ptrs = getelementptr inbounds i32, ptr %base, <8 x i32> %eidxs3081 %v = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> %m, <8 x i32> %passthru)3082 ret <8 x i32> %v3083}3084 3085define <8 x i32> @mgather_baseidx_zext_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <8 x i1> %m, <8 x i32> %passthru) {3086; RV32-LABEL: mgather_baseidx_zext_v8i16_v8i32:3087; RV32: # %bb.0:3088; RV32-NEXT: li a1, 43089; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma3090; RV32-NEXT: vwmulu.vx v12, v8, a13091; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, mu3092; RV32-NEXT: vluxei32.v v10, (a0), v12, v0.t3093; RV32-NEXT: vmv.v.v v8, v103094; RV32-NEXT: ret3095;3096; RV64V-LABEL: mgather_baseidx_zext_v8i16_v8i32:3097; RV64V: # %bb.0:3098; RV64V-NEXT: li a1, 43099; RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, ma3100; RV64V-NEXT: vwmulu.vx v12, v8, a13101; RV64V-NEXT: vsetvli zero, zero, e32, m2, ta, mu3102; RV64V-NEXT: vluxei32.v v10, (a0), v12, v0.t3103; RV64V-NEXT: vmv.v.v v8, v103104; RV64V-NEXT: ret3105;3106; RV64ZVE32F-LABEL: mgather_baseidx_zext_v8i16_v8i32:3107; RV64ZVE32F: # %bb.0:3108; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma3109; RV64ZVE32F-NEXT: vmv.x.s a1, v03110; RV64ZVE32F-NEXT: andi a2, a1, 13111; RV64ZVE32F-NEXT: beqz a2, .LBB40_23112; RV64ZVE32F-NEXT: # %bb.1: # %cond.load3113; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma3114; RV64ZVE32F-NEXT: vmv.x.s a2, v83115; RV64ZVE32F-NEXT: slli a2, a2, 483116; RV64ZVE32F-NEXT: srli a2, a2, 463117; RV64ZVE32F-NEXT: add a2, a0, a23118; RV64ZVE32F-NEXT: lw a2, 0(a2)3119; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma3120; RV64ZVE32F-NEXT: vmv.s.x v10, a23121; RV64ZVE32F-NEXT: .LBB40_2: # %else3122; RV64ZVE32F-NEXT: andi a2, a1, 23123; RV64ZVE32F-NEXT: beqz a2, .LBB40_43124; RV64ZVE32F-NEXT: # %bb.3: # %cond.load13125; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma3126; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 13127; RV64ZVE32F-NEXT: vmv.x.s a2, v93128; RV64ZVE32F-NEXT: slli a2, a2, 483129; RV64ZVE32F-NEXT: srli a2, a2, 463130; RV64ZVE32F-NEXT: add a2, a0, a23131; RV64ZVE32F-NEXT: lw a2, 0(a2)3132; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma3133; RV64ZVE32F-NEXT: vmv.s.x v9, a23134; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma3135; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 13136; RV64ZVE32F-NEXT: .LBB40_4: # %else23137; RV64ZVE32F-NEXT: andi a2, a1, 43138; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma3139; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 23140; RV64ZVE32F-NEXT: beqz a2, .LBB40_63141; RV64ZVE32F-NEXT: # %bb.5: # %cond.load43142; RV64ZVE32F-NEXT: vmv.x.s a2, v93143; RV64ZVE32F-NEXT: slli a2, a2, 483144; RV64ZVE32F-NEXT: srli a2, a2, 463145; RV64ZVE32F-NEXT: add a2, a0, a23146; RV64ZVE32F-NEXT: lw a2, 0(a2)3147; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma3148; RV64ZVE32F-NEXT: vmv.s.x v12, a23149; RV64ZVE32F-NEXT: vsetivli zero, 3, e32, m1, tu, ma3150; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 23151; RV64ZVE32F-NEXT: .LBB40_6: # %else53152; RV64ZVE32F-NEXT: andi a2, a1, 83153; RV64ZVE32F-NEXT: beqz a2, .LBB40_83154; RV64ZVE32F-NEXT: # %bb.7: # %cond.load73155; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma3156; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 13157; RV64ZVE32F-NEXT: vmv.x.s a2, v93158; RV64ZVE32F-NEXT: slli a2, a2, 483159; RV64ZVE32F-NEXT: srli a2, a2, 463160; RV64ZVE32F-NEXT: add a2, a0, a23161; RV64ZVE32F-NEXT: lw a2, 0(a2)3162; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma3163; RV64ZVE32F-NEXT: vmv.s.x v9, a23164; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma3165; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 33166; RV64ZVE32F-NEXT: .LBB40_8: # %else83167; RV64ZVE32F-NEXT: andi a2, a1, 163168; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma3169; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 43170; RV64ZVE32F-NEXT: beqz a2, .LBB40_103171; RV64ZVE32F-NEXT: # %bb.9: # %cond.load103172; RV64ZVE32F-NEXT: vmv.x.s a2, v83173; RV64ZVE32F-NEXT: slli a2, a2, 483174; RV64ZVE32F-NEXT: srli a2, a2, 463175; RV64ZVE32F-NEXT: add a2, a0, a23176; RV64ZVE32F-NEXT: lw a2, 0(a2)3177; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma3178; RV64ZVE32F-NEXT: vmv.s.x v12, a23179; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma3180; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 43181; RV64ZVE32F-NEXT: .LBB40_10: # %else113182; RV64ZVE32F-NEXT: andi a2, a1, 323183; RV64ZVE32F-NEXT: beqz a2, .LBB40_123184; RV64ZVE32F-NEXT: # %bb.11: # %cond.load133185; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma3186; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 13187; RV64ZVE32F-NEXT: vmv.x.s a2, v93188; RV64ZVE32F-NEXT: slli a2, a2, 483189; RV64ZVE32F-NEXT: srli a2, a2, 463190; RV64ZVE32F-NEXT: add a2, a0, a23191; RV64ZVE32F-NEXT: lw a2, 0(a2)3192; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma3193; RV64ZVE32F-NEXT: vmv.s.x v12, a23194; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma3195; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 53196; RV64ZVE32F-NEXT: .LBB40_12: # %else143197; RV64ZVE32F-NEXT: andi a2, a1, 643198; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma3199; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 23200; RV64ZVE32F-NEXT: beqz a2, .LBB40_143201; RV64ZVE32F-NEXT: # %bb.13: # %cond.load163202; RV64ZVE32F-NEXT: vmv.x.s a2, v83203; RV64ZVE32F-NEXT: slli a2, a2, 483204; RV64ZVE32F-NEXT: srli a2, a2, 463205; RV64ZVE32F-NEXT: add a2, a0, a23206; RV64ZVE32F-NEXT: lw a2, 0(a2)3207; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma3208; RV64ZVE32F-NEXT: vmv.s.x v12, a23209; RV64ZVE32F-NEXT: vsetivli zero, 7, e32, m2, tu, ma3210; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 63211; RV64ZVE32F-NEXT: .LBB40_14: # %else173212; RV64ZVE32F-NEXT: andi a1, a1, -1283213; RV64ZVE32F-NEXT: beqz a1, .LBB40_163214; RV64ZVE32F-NEXT: # %bb.15: # %cond.load193215; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma3216; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 13217; RV64ZVE32F-NEXT: vmv.x.s a1, v83218; RV64ZVE32F-NEXT: slli a1, a1, 483219; RV64ZVE32F-NEXT: srli a1, a1, 463220; RV64ZVE32F-NEXT: add a0, a0, a13221; RV64ZVE32F-NEXT: lw a0, 0(a0)3222; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma3223; RV64ZVE32F-NEXT: vmv.s.x v8, a03224; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma3225; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 73226; RV64ZVE32F-NEXT: .LBB40_16: # %else203227; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma3228; RV64ZVE32F-NEXT: vmv2r.v v8, v103229; RV64ZVE32F-NEXT: ret3230 %eidxs = zext <8 x i16> %idxs to <8 x i32>3231 %ptrs = getelementptr inbounds i32, ptr %base, <8 x i32> %eidxs3232 %v = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> %m, <8 x i32> %passthru)3233 ret <8 x i32> %v3234}3235 3236define <8 x i32> @mgather_baseidx_v8i32(ptr %base, <8 x i32> %idxs, <8 x i1> %m, <8 x i32> %passthru) {3237; RV32-LABEL: mgather_baseidx_v8i32:3238; RV32: # %bb.0:3239; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu3240; RV32-NEXT: vsll.vi v8, v8, 23241; RV32-NEXT: vluxei32.v v10, (a0), v8, v0.t3242; RV32-NEXT: vmv.v.v v8, v103243; RV32-NEXT: ret3244;3245; RV64V-LABEL: mgather_baseidx_v8i32:3246; RV64V: # %bb.0:3247; RV64V-NEXT: li a1, 43248; RV64V-NEXT: vsetivli zero, 8, e32, m2, ta, mu3249; RV64V-NEXT: vwmulsu.vx v12, v8, a13250; RV64V-NEXT: vluxei64.v v10, (a0), v12, v0.t3251; RV64V-NEXT: vmv.v.v v8, v103252; RV64V-NEXT: ret3253;3254; RV64ZVE32F-LABEL: mgather_baseidx_v8i32:3255; RV64ZVE32F: # %bb.0:3256; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma3257; RV64ZVE32F-NEXT: vmv.x.s a1, v03258; RV64ZVE32F-NEXT: andi a2, a1, 13259; RV64ZVE32F-NEXT: beqz a2, .LBB41_23260; RV64ZVE32F-NEXT: # %bb.1: # %cond.load3261; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma3262; RV64ZVE32F-NEXT: vmv.x.s a2, v83263; RV64ZVE32F-NEXT: slli a2, a2, 23264; RV64ZVE32F-NEXT: add a2, a0, a23265; RV64ZVE32F-NEXT: lw a2, 0(a2)3266; RV64ZVE32F-NEXT: vmv.s.x v10, a23267; RV64ZVE32F-NEXT: .LBB41_2: # %else3268; RV64ZVE32F-NEXT: andi a2, a1, 23269; RV64ZVE32F-NEXT: beqz a2, .LBB41_43270; RV64ZVE32F-NEXT: # %bb.3: # %cond.load13271; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma3272; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 13273; RV64ZVE32F-NEXT: vmv.x.s a2, v123274; RV64ZVE32F-NEXT: slli a2, a2, 23275; RV64ZVE32F-NEXT: add a2, a0, a23276; RV64ZVE32F-NEXT: lw a2, 0(a2)3277; RV64ZVE32F-NEXT: vmv.s.x v12, a23278; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 13279; RV64ZVE32F-NEXT: .LBB41_4: # %else23280; RV64ZVE32F-NEXT: andi a2, a1, 43281; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma3282; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 23283; RV64ZVE32F-NEXT: beqz a2, .LBB41_63284; RV64ZVE32F-NEXT: # %bb.5: # %cond.load43285; RV64ZVE32F-NEXT: vmv.x.s a2, v123286; RV64ZVE32F-NEXT: slli a2, a2, 23287; RV64ZVE32F-NEXT: add a2, a0, a23288; RV64ZVE32F-NEXT: lw a2, 0(a2)3289; RV64ZVE32F-NEXT: vmv.s.x v13, a23290; RV64ZVE32F-NEXT: vsetivli zero, 3, e32, m1, tu, ma3291; RV64ZVE32F-NEXT: vslideup.vi v10, v13, 23292; RV64ZVE32F-NEXT: .LBB41_6: # %else53293; RV64ZVE32F-NEXT: andi a2, a1, 83294; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, ta, ma3295; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 43296; RV64ZVE32F-NEXT: bnez a2, .LBB41_153297; RV64ZVE32F-NEXT: # %bb.7: # %else83298; RV64ZVE32F-NEXT: andi a2, a1, 163299; RV64ZVE32F-NEXT: bnez a2, .LBB41_163300; RV64ZVE32F-NEXT: .LBB41_8: # %else113301; RV64ZVE32F-NEXT: andi a2, a1, 323302; RV64ZVE32F-NEXT: beqz a2, .LBB41_103303; RV64ZVE32F-NEXT: .LBB41_9: # %cond.load133304; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma3305; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 13306; RV64ZVE32F-NEXT: vmv.x.s a2, v93307; RV64ZVE32F-NEXT: slli a2, a2, 23308; RV64ZVE32F-NEXT: add a2, a0, a23309; RV64ZVE32F-NEXT: lw a2, 0(a2)3310; RV64ZVE32F-NEXT: vmv.s.x v12, a23311; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma3312; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 53313; RV64ZVE32F-NEXT: .LBB41_10: # %else143314; RV64ZVE32F-NEXT: andi a2, a1, 643315; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma3316; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 23317; RV64ZVE32F-NEXT: beqz a2, .LBB41_123318; RV64ZVE32F-NEXT: # %bb.11: # %cond.load163319; RV64ZVE32F-NEXT: vmv.x.s a2, v83320; RV64ZVE32F-NEXT: slli a2, a2, 23321; RV64ZVE32F-NEXT: add a2, a0, a23322; RV64ZVE32F-NEXT: lw a2, 0(a2)3323; RV64ZVE32F-NEXT: vmv.s.x v12, a23324; RV64ZVE32F-NEXT: vsetivli zero, 7, e32, m2, tu, ma3325; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 63326; RV64ZVE32F-NEXT: .LBB41_12: # %else173327; RV64ZVE32F-NEXT: andi a1, a1, -1283328; RV64ZVE32F-NEXT: beqz a1, .LBB41_143329; RV64ZVE32F-NEXT: # %bb.13: # %cond.load193330; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma3331; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 13332; RV64ZVE32F-NEXT: vmv.x.s a1, v83333; RV64ZVE32F-NEXT: slli a1, a1, 23334; RV64ZVE32F-NEXT: add a0, a0, a13335; RV64ZVE32F-NEXT: lw a0, 0(a0)3336; RV64ZVE32F-NEXT: vmv.s.x v8, a03337; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma3338; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 73339; RV64ZVE32F-NEXT: .LBB41_14: # %else203340; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma3341; RV64ZVE32F-NEXT: vmv2r.v v8, v103342; RV64ZVE32F-NEXT: ret3343; RV64ZVE32F-NEXT: .LBB41_15: # %cond.load73344; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma3345; RV64ZVE32F-NEXT: vslidedown.vi v9, v12, 13346; RV64ZVE32F-NEXT: vmv.x.s a2, v93347; RV64ZVE32F-NEXT: slli a2, a2, 23348; RV64ZVE32F-NEXT: add a2, a0, a23349; RV64ZVE32F-NEXT: lw a2, 0(a2)3350; RV64ZVE32F-NEXT: vmv.s.x v9, a23351; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 33352; RV64ZVE32F-NEXT: andi a2, a1, 163353; RV64ZVE32F-NEXT: beqz a2, .LBB41_83354; RV64ZVE32F-NEXT: .LBB41_16: # %cond.load103355; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma3356; RV64ZVE32F-NEXT: vmv.x.s a2, v83357; RV64ZVE32F-NEXT: slli a2, a2, 23358; RV64ZVE32F-NEXT: add a2, a0, a23359; RV64ZVE32F-NEXT: lw a2, 0(a2)3360; RV64ZVE32F-NEXT: vmv.s.x v12, a23361; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 43362; RV64ZVE32F-NEXT: andi a2, a1, 323363; RV64ZVE32F-NEXT: bnez a2, .LBB41_93364; RV64ZVE32F-NEXT: j .LBB41_103365 %ptrs = getelementptr inbounds i32, ptr %base, <8 x i32> %idxs3366 %v = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> %m, <8 x i32> %passthru)3367 ret <8 x i32> %v3368}3369 3370define <1 x i64> @mgather_v1i64(<1 x ptr> %ptrs, <1 x i1> %m, <1 x i64> %passthru) {3371; RV32V-LABEL: mgather_v1i64:3372; RV32V: # %bb.0:3373; RV32V-NEXT: vsetivli zero, 1, e64, m1, ta, mu3374; RV32V-NEXT: vluxei32.v v9, (zero), v8, v0.t3375; RV32V-NEXT: vmv.v.v v8, v93376; RV32V-NEXT: ret3377;3378; RV64V-LABEL: mgather_v1i64:3379; RV64V: # %bb.0:3380; RV64V-NEXT: vsetivli zero, 1, e64, m1, ta, mu3381; RV64V-NEXT: vluxei64.v v9, (zero), v8, v0.t3382; RV64V-NEXT: vmv.v.v v8, v93383; RV64V-NEXT: ret3384;3385; RV32ZVE32F-LABEL: mgather_v1i64:3386; RV32ZVE32F: # %bb.0:3387; RV32ZVE32F-NEXT: vsetvli a2, zero, e8, mf4, ta, ma3388; RV32ZVE32F-NEXT: vfirst.m a2, v03389; RV32ZVE32F-NEXT: bnez a2, .LBB42_23390; RV32ZVE32F-NEXT: # %bb.1: # %cond.load3391; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma3392; RV32ZVE32F-NEXT: vmv.x.s a1, v83393; RV32ZVE32F-NEXT: lw a0, 0(a1)3394; RV32ZVE32F-NEXT: lw a1, 4(a1)3395; RV32ZVE32F-NEXT: .LBB42_2: # %else3396; RV32ZVE32F-NEXT: ret3397;3398; RV64ZVE32F-LABEL: mgather_v1i64:3399; RV64ZVE32F: # %bb.0:3400; RV64ZVE32F-NEXT: vsetvli a2, zero, e8, mf4, ta, ma3401; RV64ZVE32F-NEXT: vfirst.m a2, v03402; RV64ZVE32F-NEXT: bnez a2, .LBB42_23403; RV64ZVE32F-NEXT: # %bb.1: # %cond.load3404; RV64ZVE32F-NEXT: ld a1, 0(a0)3405; RV64ZVE32F-NEXT: .LBB42_2: # %else3406; RV64ZVE32F-NEXT: mv a0, a13407; RV64ZVE32F-NEXT: ret3408 %v = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> %ptrs, i32 8, <1 x i1> %m, <1 x i64> %passthru)3409 ret <1 x i64> %v3410}3411 3412define <2 x i64> @mgather_v2i64(<2 x ptr> %ptrs, <2 x i1> %m, <2 x i64> %passthru) {3413; RV32V-LABEL: mgather_v2i64:3414; RV32V: # %bb.0:3415; RV32V-NEXT: vsetivli zero, 2, e64, m1, ta, mu3416; RV32V-NEXT: vluxei32.v v9, (zero), v8, v0.t3417; RV32V-NEXT: vmv.v.v v8, v93418; RV32V-NEXT: ret3419;3420; RV64V-LABEL: mgather_v2i64:3421; RV64V: # %bb.0:3422; RV64V-NEXT: vsetivli zero, 2, e64, m1, ta, mu3423; RV64V-NEXT: vluxei64.v v9, (zero), v8, v0.t3424; RV64V-NEXT: vmv.v.v v8, v93425; RV64V-NEXT: ret3426;3427; RV32ZVE32F-LABEL: mgather_v2i64:3428; RV32ZVE32F: # %bb.0:3429; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma3430; RV32ZVE32F-NEXT: vmv.x.s a4, v03431; RV32ZVE32F-NEXT: andi a2, a4, 13432; RV32ZVE32F-NEXT: beqz a2, .LBB43_33433; RV32ZVE32F-NEXT: # %bb.1: # %cond.load3434; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma3435; RV32ZVE32F-NEXT: vmv.x.s a3, v83436; RV32ZVE32F-NEXT: lw a2, 0(a3)3437; RV32ZVE32F-NEXT: lw a3, 4(a3)3438; RV32ZVE32F-NEXT: andi a4, a4, 23439; RV32ZVE32F-NEXT: bnez a4, .LBB43_43440; RV32ZVE32F-NEXT: .LBB43_2:3441; RV32ZVE32F-NEXT: lw a4, 8(a1)3442; RV32ZVE32F-NEXT: lw a1, 12(a1)3443; RV32ZVE32F-NEXT: j .LBB43_53444; RV32ZVE32F-NEXT: .LBB43_3:3445; RV32ZVE32F-NEXT: lw a2, 0(a1)3446; RV32ZVE32F-NEXT: lw a3, 4(a1)3447; RV32ZVE32F-NEXT: andi a4, a4, 23448; RV32ZVE32F-NEXT: beqz a4, .LBB43_23449; RV32ZVE32F-NEXT: .LBB43_4: # %cond.load13450; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma3451; RV32ZVE32F-NEXT: vslidedown.vi v8, v8, 13452; RV32ZVE32F-NEXT: vmv.x.s a1, v83453; RV32ZVE32F-NEXT: lw a4, 0(a1)3454; RV32ZVE32F-NEXT: lw a1, 4(a1)3455; RV32ZVE32F-NEXT: .LBB43_5: # %else23456; RV32ZVE32F-NEXT: sw a2, 0(a0)3457; RV32ZVE32F-NEXT: sw a3, 4(a0)3458; RV32ZVE32F-NEXT: sw a4, 8(a0)3459; RV32ZVE32F-NEXT: sw a1, 12(a0)3460; RV32ZVE32F-NEXT: ret3461;3462; RV64ZVE32F-LABEL: mgather_v2i64:3463; RV64ZVE32F: # %bb.0:3464; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma3465; RV64ZVE32F-NEXT: vmv.x.s a4, v03466; RV64ZVE32F-NEXT: andi a5, a4, 13467; RV64ZVE32F-NEXT: beqz a5, .LBB43_23468; RV64ZVE32F-NEXT: # %bb.1: # %cond.load3469; RV64ZVE32F-NEXT: ld a2, 0(a0)3470; RV64ZVE32F-NEXT: .LBB43_2: # %else3471; RV64ZVE32F-NEXT: andi a4, a4, 23472; RV64ZVE32F-NEXT: beqz a4, .LBB43_43473; RV64ZVE32F-NEXT: # %bb.3: # %cond.load13474; RV64ZVE32F-NEXT: ld a3, 0(a1)3475; RV64ZVE32F-NEXT: .LBB43_4: # %else23476; RV64ZVE32F-NEXT: mv a0, a23477; RV64ZVE32F-NEXT: mv a1, a33478; RV64ZVE32F-NEXT: ret3479 %v = call <2 x i64> @llvm.masked.gather.v2i64.v2p0(<2 x ptr> %ptrs, i32 8, <2 x i1> %m, <2 x i64> %passthru)3480 ret <2 x i64> %v3481}3482 3483define <4 x i64> @mgather_v4i64(<4 x ptr> %ptrs, <4 x i1> %m, <4 x i64> %passthru) {3484; RV32V-LABEL: mgather_v4i64:3485; RV32V: # %bb.0:3486; RV32V-NEXT: vsetivli zero, 4, e64, m2, ta, mu3487; RV32V-NEXT: vluxei32.v v10, (zero), v8, v0.t3488; RV32V-NEXT: vmv.v.v v8, v103489; RV32V-NEXT: ret3490;3491; RV64V-LABEL: mgather_v4i64:3492; RV64V: # %bb.0:3493; RV64V-NEXT: vsetivli zero, 4, e64, m2, ta, mu3494; RV64V-NEXT: vluxei64.v v10, (zero), v8, v0.t3495; RV64V-NEXT: vmv.v.v v8, v103496; RV64V-NEXT: ret3497;3498; RV32ZVE32F-LABEL: mgather_v4i64:3499; RV32ZVE32F: # %bb.0:3500; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma3501; RV32ZVE32F-NEXT: vmv.x.s a6, v03502; RV32ZVE32F-NEXT: andi a2, a6, 13503; RV32ZVE32F-NEXT: beqz a2, .LBB44_53504; RV32ZVE32F-NEXT: # %bb.1: # %cond.load3505; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma3506; RV32ZVE32F-NEXT: vmv.x.s a3, v83507; RV32ZVE32F-NEXT: lw a2, 0(a3)3508; RV32ZVE32F-NEXT: lw a3, 4(a3)3509; RV32ZVE32F-NEXT: andi a4, a6, 23510; RV32ZVE32F-NEXT: bnez a4, .LBB44_63511; RV32ZVE32F-NEXT: .LBB44_2:3512; RV32ZVE32F-NEXT: lw a4, 8(a1)3513; RV32ZVE32F-NEXT: lw a5, 12(a1)3514; RV32ZVE32F-NEXT: andi a7, a6, 43515; RV32ZVE32F-NEXT: bnez a7, .LBB44_73516; RV32ZVE32F-NEXT: .LBB44_3:3517; RV32ZVE32F-NEXT: lw a7, 16(a1)3518; RV32ZVE32F-NEXT: lw t0, 20(a1)3519; RV32ZVE32F-NEXT: andi a6, a6, 83520; RV32ZVE32F-NEXT: bnez a6, .LBB44_83521; RV32ZVE32F-NEXT: .LBB44_4:3522; RV32ZVE32F-NEXT: lw a6, 24(a1)3523; RV32ZVE32F-NEXT: lw a1, 28(a1)3524; RV32ZVE32F-NEXT: j .LBB44_93525; RV32ZVE32F-NEXT: .LBB44_5:3526; RV32ZVE32F-NEXT: lw a2, 0(a1)3527; RV32ZVE32F-NEXT: lw a3, 4(a1)3528; RV32ZVE32F-NEXT: andi a4, a6, 23529; RV32ZVE32F-NEXT: beqz a4, .LBB44_23530; RV32ZVE32F-NEXT: .LBB44_6: # %cond.load13531; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma3532; RV32ZVE32F-NEXT: vslidedown.vi v9, v8, 13533; RV32ZVE32F-NEXT: vmv.x.s a5, v93534; RV32ZVE32F-NEXT: lw a4, 0(a5)3535; RV32ZVE32F-NEXT: lw a5, 4(a5)3536; RV32ZVE32F-NEXT: andi a7, a6, 43537; RV32ZVE32F-NEXT: beqz a7, .LBB44_33538; RV32ZVE32F-NEXT: .LBB44_7: # %cond.load43539; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma3540; RV32ZVE32F-NEXT: vslidedown.vi v9, v8, 23541; RV32ZVE32F-NEXT: vmv.x.s t0, v93542; RV32ZVE32F-NEXT: lw a7, 0(t0)3543; RV32ZVE32F-NEXT: lw t0, 4(t0)3544; RV32ZVE32F-NEXT: andi a6, a6, 83545; RV32ZVE32F-NEXT: beqz a6, .LBB44_43546; RV32ZVE32F-NEXT: .LBB44_8: # %cond.load73547; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma3548; RV32ZVE32F-NEXT: vslidedown.vi v8, v8, 33549; RV32ZVE32F-NEXT: vmv.x.s a1, v83550; RV32ZVE32F-NEXT: lw a6, 0(a1)3551; RV32ZVE32F-NEXT: lw a1, 4(a1)3552; RV32ZVE32F-NEXT: .LBB44_9: # %else83553; RV32ZVE32F-NEXT: sw a2, 0(a0)3554; RV32ZVE32F-NEXT: sw a3, 4(a0)3555; RV32ZVE32F-NEXT: sw a4, 8(a0)3556; RV32ZVE32F-NEXT: sw a5, 12(a0)3557; RV32ZVE32F-NEXT: sw a7, 16(a0)3558; RV32ZVE32F-NEXT: sw t0, 20(a0)3559; RV32ZVE32F-NEXT: sw a6, 24(a0)3560; RV32ZVE32F-NEXT: sw a1, 28(a0)3561; RV32ZVE32F-NEXT: ret3562;3563; RV64ZVE32F-LABEL: mgather_v4i64:3564; RV64ZVE32F: # %bb.0:3565; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma3566; RV64ZVE32F-NEXT: vmv.x.s a5, v03567; RV64ZVE32F-NEXT: andi a3, a5, 13568; RV64ZVE32F-NEXT: beqz a3, .LBB44_53569; RV64ZVE32F-NEXT: # %bb.1: # %cond.load3570; RV64ZVE32F-NEXT: ld a3, 0(a1)3571; RV64ZVE32F-NEXT: ld a3, 0(a3)3572; RV64ZVE32F-NEXT: andi a4, a5, 23573; RV64ZVE32F-NEXT: bnez a4, .LBB44_63574; RV64ZVE32F-NEXT: .LBB44_2:3575; RV64ZVE32F-NEXT: ld a4, 8(a2)3576; RV64ZVE32F-NEXT: andi a6, a5, 43577; RV64ZVE32F-NEXT: bnez a6, .LBB44_73578; RV64ZVE32F-NEXT: .LBB44_3:3579; RV64ZVE32F-NEXT: ld a6, 16(a2)3580; RV64ZVE32F-NEXT: andi a5, a5, 83581; RV64ZVE32F-NEXT: bnez a5, .LBB44_83582; RV64ZVE32F-NEXT: .LBB44_4:3583; RV64ZVE32F-NEXT: ld a1, 24(a2)3584; RV64ZVE32F-NEXT: j .LBB44_93585; RV64ZVE32F-NEXT: .LBB44_5:3586; RV64ZVE32F-NEXT: ld a3, 0(a2)3587; RV64ZVE32F-NEXT: andi a4, a5, 23588; RV64ZVE32F-NEXT: beqz a4, .LBB44_23589; RV64ZVE32F-NEXT: .LBB44_6: # %cond.load13590; RV64ZVE32F-NEXT: ld a4, 8(a1)3591; RV64ZVE32F-NEXT: ld a4, 0(a4)3592; RV64ZVE32F-NEXT: andi a6, a5, 43593; RV64ZVE32F-NEXT: beqz a6, .LBB44_33594; RV64ZVE32F-NEXT: .LBB44_7: # %cond.load43595; RV64ZVE32F-NEXT: ld a6, 16(a1)3596; RV64ZVE32F-NEXT: ld a6, 0(a6)3597; RV64ZVE32F-NEXT: andi a5, a5, 83598; RV64ZVE32F-NEXT: beqz a5, .LBB44_43599; RV64ZVE32F-NEXT: .LBB44_8: # %cond.load73600; RV64ZVE32F-NEXT: ld a1, 24(a1)3601; RV64ZVE32F-NEXT: ld a1, 0(a1)3602; RV64ZVE32F-NEXT: .LBB44_9: # %else83603; RV64ZVE32F-NEXT: sd a3, 0(a0)3604; RV64ZVE32F-NEXT: sd a4, 8(a0)3605; RV64ZVE32F-NEXT: sd a6, 16(a0)3606; RV64ZVE32F-NEXT: sd a1, 24(a0)3607; RV64ZVE32F-NEXT: ret3608 %v = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> %ptrs, i32 8, <4 x i1> %m, <4 x i64> %passthru)3609 ret <4 x i64> %v3610}3611 3612define <4 x i64> @mgather_truemask_v4i64(<4 x ptr> %ptrs, <4 x i64> %passthru) {3613; RV32V-LABEL: mgather_truemask_v4i64:3614; RV32V: # %bb.0:3615; RV32V-NEXT: vsetivli zero, 4, e64, m2, ta, ma3616; RV32V-NEXT: vmv1r.v v10, v83617; RV32V-NEXT: vluxei32.v v8, (zero), v103618; RV32V-NEXT: ret3619;3620; RV64V-LABEL: mgather_truemask_v4i64:3621; RV64V: # %bb.0:3622; RV64V-NEXT: vsetivli zero, 4, e64, m2, ta, ma3623; RV64V-NEXT: vluxei64.v v8, (zero), v83624; RV64V-NEXT: ret3625;3626; RV32ZVE32F-LABEL: mgather_truemask_v4i64:3627; RV32ZVE32F: # %bb.0:3628; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma3629; RV32ZVE32F-NEXT: vmv.x.s a1, v83630; RV32ZVE32F-NEXT: vslidedown.vi v9, v8, 13631; RV32ZVE32F-NEXT: vmv.x.s a2, v93632; RV32ZVE32F-NEXT: vslidedown.vi v9, v8, 23633; RV32ZVE32F-NEXT: vslidedown.vi v8, v8, 33634; RV32ZVE32F-NEXT: lw a3, 0(a1)3635; RV32ZVE32F-NEXT: lw a1, 4(a1)3636; RV32ZVE32F-NEXT: vmv.x.s a4, v93637; RV32ZVE32F-NEXT: vmv.x.s a5, v83638; RV32ZVE32F-NEXT: lw a6, 0(a2)3639; RV32ZVE32F-NEXT: lw a2, 4(a2)3640; RV32ZVE32F-NEXT: lw a7, 0(a4)3641; RV32ZVE32F-NEXT: lw a4, 4(a4)3642; RV32ZVE32F-NEXT: lw t0, 0(a5)3643; RV32ZVE32F-NEXT: lw a5, 4(a5)3644; RV32ZVE32F-NEXT: sw a7, 16(a0)3645; RV32ZVE32F-NEXT: sw a4, 20(a0)3646; RV32ZVE32F-NEXT: sw t0, 24(a0)3647; RV32ZVE32F-NEXT: sw a5, 28(a0)3648; RV32ZVE32F-NEXT: sw a3, 0(a0)3649; RV32ZVE32F-NEXT: sw a1, 4(a0)3650; RV32ZVE32F-NEXT: sw a6, 8(a0)3651; RV32ZVE32F-NEXT: sw a2, 12(a0)3652; RV32ZVE32F-NEXT: ret3653;3654; RV64ZVE32F-LABEL: mgather_truemask_v4i64:3655; RV64ZVE32F: # %bb.0:3656; RV64ZVE32F-NEXT: ld a2, 0(a1)3657; RV64ZVE32F-NEXT: ld a3, 8(a1)3658; RV64ZVE32F-NEXT: ld a4, 16(a1)3659; RV64ZVE32F-NEXT: ld a1, 24(a1)3660; RV64ZVE32F-NEXT: ld a2, 0(a2)3661; RV64ZVE32F-NEXT: ld a3, 0(a3)3662; RV64ZVE32F-NEXT: ld a4, 0(a4)3663; RV64ZVE32F-NEXT: ld a1, 0(a1)3664; RV64ZVE32F-NEXT: sd a2, 0(a0)3665; RV64ZVE32F-NEXT: sd a3, 8(a0)3666; RV64ZVE32F-NEXT: sd a4, 16(a0)3667; RV64ZVE32F-NEXT: sd a1, 24(a0)3668; RV64ZVE32F-NEXT: ret3669 %v = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> %ptrs, i32 8, <4 x i1> splat (i1 1), <4 x i64> %passthru)3670 ret <4 x i64> %v3671}3672 3673define <4 x i64> @mgather_falsemask_v4i64(<4 x ptr> %ptrs, <4 x i64> %passthru) {3674; RV32V-LABEL: mgather_falsemask_v4i64:3675; RV32V: # %bb.0:3676; RV32V-NEXT: vsetivli zero, 1, e8, m1, ta, ma3677; RV32V-NEXT: vmv2r.v v8, v103678; RV32V-NEXT: ret3679;3680; RV64V-LABEL: mgather_falsemask_v4i64:3681; RV64V: # %bb.0:3682; RV64V-NEXT: vsetivli zero, 1, e8, m1, ta, ma3683; RV64V-NEXT: vmv2r.v v8, v103684; RV64V-NEXT: ret3685;3686; RV32ZVE32F-LABEL: mgather_falsemask_v4i64:3687; RV32ZVE32F: # %bb.0:3688; RV32ZVE32F-NEXT: lw a2, 0(a1)3689; RV32ZVE32F-NEXT: lw a3, 4(a1)3690; RV32ZVE32F-NEXT: lw a4, 8(a1)3691; RV32ZVE32F-NEXT: lw a5, 12(a1)3692; RV32ZVE32F-NEXT: lw a6, 16(a1)3693; RV32ZVE32F-NEXT: lw a7, 20(a1)3694; RV32ZVE32F-NEXT: lw t0, 24(a1)3695; RV32ZVE32F-NEXT: lw a1, 28(a1)3696; RV32ZVE32F-NEXT: sw a6, 16(a0)3697; RV32ZVE32F-NEXT: sw a7, 20(a0)3698; RV32ZVE32F-NEXT: sw t0, 24(a0)3699; RV32ZVE32F-NEXT: sw a1, 28(a0)3700; RV32ZVE32F-NEXT: sw a2, 0(a0)3701; RV32ZVE32F-NEXT: sw a3, 4(a0)3702; RV32ZVE32F-NEXT: sw a4, 8(a0)3703; RV32ZVE32F-NEXT: sw a5, 12(a0)3704; RV32ZVE32F-NEXT: ret3705;3706; RV64ZVE32F-LABEL: mgather_falsemask_v4i64:3707; RV64ZVE32F: # %bb.0:3708; RV64ZVE32F-NEXT: ld a1, 0(a2)3709; RV64ZVE32F-NEXT: ld a3, 8(a2)3710; RV64ZVE32F-NEXT: ld a4, 16(a2)3711; RV64ZVE32F-NEXT: ld a2, 24(a2)3712; RV64ZVE32F-NEXT: sd a1, 0(a0)3713; RV64ZVE32F-NEXT: sd a3, 8(a0)3714; RV64ZVE32F-NEXT: sd a4, 16(a0)3715; RV64ZVE32F-NEXT: sd a2, 24(a0)3716; RV64ZVE32F-NEXT: ret3717 %v = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> %ptrs, i32 8, <4 x i1> zeroinitializer, <4 x i64> %passthru)3718 ret <4 x i64> %v3719}3720 3721define <8 x i64> @mgather_v8i64(<8 x ptr> %ptrs, <8 x i1> %m, <8 x i64> %passthru) {3722; RV32V-LABEL: mgather_v8i64:3723; RV32V: # %bb.0:3724; RV32V-NEXT: vsetivli zero, 8, e64, m4, ta, mu3725; RV32V-NEXT: vluxei32.v v12, (zero), v8, v0.t3726; RV32V-NEXT: vmv.v.v v8, v123727; RV32V-NEXT: ret3728;3729; RV64V-LABEL: mgather_v8i64:3730; RV64V: # %bb.0:3731; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, mu3732; RV64V-NEXT: vluxei64.v v12, (zero), v8, v0.t3733; RV64V-NEXT: vmv.v.v v8, v123734; RV64V-NEXT: ret3735;3736; RV32ZVE32F-LABEL: mgather_v8i64:3737; RV32ZVE32F: # %bb.0:3738; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma3739; RV32ZVE32F-NEXT: vmv.x.s t0, v03740; RV32ZVE32F-NEXT: andi a2, t0, 13741; RV32ZVE32F-NEXT: beqz a2, .LBB47_73742; RV32ZVE32F-NEXT: # %bb.1: # %cond.load3743; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma3744; RV32ZVE32F-NEXT: vmv.x.s a3, v83745; RV32ZVE32F-NEXT: lw a2, 0(a3)3746; RV32ZVE32F-NEXT: lw a3, 4(a3)3747; RV32ZVE32F-NEXT: andi a4, t0, 23748; RV32ZVE32F-NEXT: bnez a4, .LBB47_83749; RV32ZVE32F-NEXT: .LBB47_2:3750; RV32ZVE32F-NEXT: lw a4, 8(a1)3751; RV32ZVE32F-NEXT: lw a5, 12(a1)3752; RV32ZVE32F-NEXT: andi a6, t0, 43753; RV32ZVE32F-NEXT: bnez a6, .LBB47_93754; RV32ZVE32F-NEXT: .LBB47_3:3755; RV32ZVE32F-NEXT: lw a6, 16(a1)3756; RV32ZVE32F-NEXT: lw a7, 20(a1)3757; RV32ZVE32F-NEXT: andi t1, t0, 83758; RV32ZVE32F-NEXT: bnez t1, .LBB47_103759; RV32ZVE32F-NEXT: .LBB47_4:3760; RV32ZVE32F-NEXT: lw t1, 24(a1)3761; RV32ZVE32F-NEXT: lw t2, 28(a1)3762; RV32ZVE32F-NEXT: andi t3, t0, 163763; RV32ZVE32F-NEXT: bnez t3, .LBB47_113764; RV32ZVE32F-NEXT: .LBB47_5:3765; RV32ZVE32F-NEXT: lw t3, 32(a1)3766; RV32ZVE32F-NEXT: lw t4, 36(a1)3767; RV32ZVE32F-NEXT: andi t5, t0, 323768; RV32ZVE32F-NEXT: bnez t5, .LBB47_123769; RV32ZVE32F-NEXT: .LBB47_6:3770; RV32ZVE32F-NEXT: lw t5, 40(a1)3771; RV32ZVE32F-NEXT: lw t6, 44(a1)3772; RV32ZVE32F-NEXT: j .LBB47_133773; RV32ZVE32F-NEXT: .LBB47_7:3774; RV32ZVE32F-NEXT: lw a2, 0(a1)3775; RV32ZVE32F-NEXT: lw a3, 4(a1)3776; RV32ZVE32F-NEXT: andi a4, t0, 23777; RV32ZVE32F-NEXT: beqz a4, .LBB47_23778; RV32ZVE32F-NEXT: .LBB47_8: # %cond.load13779; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma3780; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 13781; RV32ZVE32F-NEXT: vmv.x.s a5, v103782; RV32ZVE32F-NEXT: lw a4, 0(a5)3783; RV32ZVE32F-NEXT: lw a5, 4(a5)3784; RV32ZVE32F-NEXT: andi a6, t0, 43785; RV32ZVE32F-NEXT: beqz a6, .LBB47_33786; RV32ZVE32F-NEXT: .LBB47_9: # %cond.load43787; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma3788; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 23789; RV32ZVE32F-NEXT: vmv.x.s a7, v103790; RV32ZVE32F-NEXT: lw a6, 0(a7)3791; RV32ZVE32F-NEXT: lw a7, 4(a7)3792; RV32ZVE32F-NEXT: andi t1, t0, 83793; RV32ZVE32F-NEXT: beqz t1, .LBB47_43794; RV32ZVE32F-NEXT: .LBB47_10: # %cond.load73795; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma3796; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 33797; RV32ZVE32F-NEXT: vmv.x.s t2, v103798; RV32ZVE32F-NEXT: lw t1, 0(t2)3799; RV32ZVE32F-NEXT: lw t2, 4(t2)3800; RV32ZVE32F-NEXT: andi t3, t0, 163801; RV32ZVE32F-NEXT: beqz t3, .LBB47_53802; RV32ZVE32F-NEXT: .LBB47_11: # %cond.load103803; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma3804; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 43805; RV32ZVE32F-NEXT: vmv.x.s t4, v103806; RV32ZVE32F-NEXT: lw t3, 0(t4)3807; RV32ZVE32F-NEXT: lw t4, 4(t4)3808; RV32ZVE32F-NEXT: andi t5, t0, 323809; RV32ZVE32F-NEXT: beqz t5, .LBB47_63810; RV32ZVE32F-NEXT: .LBB47_12: # %cond.load133811; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma3812; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 53813; RV32ZVE32F-NEXT: vmv.x.s t6, v103814; RV32ZVE32F-NEXT: lw t5, 0(t6)3815; RV32ZVE32F-NEXT: lw t6, 4(t6)3816; RV32ZVE32F-NEXT: .LBB47_13: # %else143817; RV32ZVE32F-NEXT: addi sp, sp, -163818; RV32ZVE32F-NEXT: .cfi_def_cfa_offset 163819; RV32ZVE32F-NEXT: sw s0, 12(sp) # 4-byte Folded Spill3820; RV32ZVE32F-NEXT: sw s1, 8(sp) # 4-byte Folded Spill3821; RV32ZVE32F-NEXT: .cfi_offset s0, -43822; RV32ZVE32F-NEXT: .cfi_offset s1, -83823; RV32ZVE32F-NEXT: andi s0, t0, 643824; RV32ZVE32F-NEXT: beqz s0, .LBB47_163825; RV32ZVE32F-NEXT: # %bb.14: # %cond.load163826; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma3827; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 63828; RV32ZVE32F-NEXT: vmv.x.s s1, v103829; RV32ZVE32F-NEXT: lw s0, 0(s1)3830; RV32ZVE32F-NEXT: lw s1, 4(s1)3831; RV32ZVE32F-NEXT: andi t0, t0, -1283832; RV32ZVE32F-NEXT: bnez t0, .LBB47_173833; RV32ZVE32F-NEXT: .LBB47_15:3834; RV32ZVE32F-NEXT: lw t0, 56(a1)3835; RV32ZVE32F-NEXT: lw a1, 60(a1)3836; RV32ZVE32F-NEXT: j .LBB47_183837; RV32ZVE32F-NEXT: .LBB47_16:3838; RV32ZVE32F-NEXT: lw s0, 48(a1)3839; RV32ZVE32F-NEXT: lw s1, 52(a1)3840; RV32ZVE32F-NEXT: andi t0, t0, -1283841; RV32ZVE32F-NEXT: beqz t0, .LBB47_153842; RV32ZVE32F-NEXT: .LBB47_17: # %cond.load193843; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma3844; RV32ZVE32F-NEXT: vslidedown.vi v8, v8, 73845; RV32ZVE32F-NEXT: vmv.x.s a1, v83846; RV32ZVE32F-NEXT: lw t0, 0(a1)3847; RV32ZVE32F-NEXT: lw a1, 4(a1)3848; RV32ZVE32F-NEXT: .LBB47_18: # %else203849; RV32ZVE32F-NEXT: sw a2, 0(a0)3850; RV32ZVE32F-NEXT: sw a3, 4(a0)3851; RV32ZVE32F-NEXT: sw a4, 8(a0)3852; RV32ZVE32F-NEXT: sw a5, 12(a0)3853; RV32ZVE32F-NEXT: sw a6, 16(a0)3854; RV32ZVE32F-NEXT: sw a7, 20(a0)3855; RV32ZVE32F-NEXT: sw t1, 24(a0)3856; RV32ZVE32F-NEXT: sw t2, 28(a0)3857; RV32ZVE32F-NEXT: sw t3, 32(a0)3858; RV32ZVE32F-NEXT: sw t4, 36(a0)3859; RV32ZVE32F-NEXT: sw t5, 40(a0)3860; RV32ZVE32F-NEXT: sw t6, 44(a0)3861; RV32ZVE32F-NEXT: sw s0, 48(a0)3862; RV32ZVE32F-NEXT: sw s1, 52(a0)3863; RV32ZVE32F-NEXT: sw t0, 56(a0)3864; RV32ZVE32F-NEXT: sw a1, 60(a0)3865; RV32ZVE32F-NEXT: lw s0, 12(sp) # 4-byte Folded Reload3866; RV32ZVE32F-NEXT: lw s1, 8(sp) # 4-byte Folded Reload3867; RV32ZVE32F-NEXT: .cfi_restore s03868; RV32ZVE32F-NEXT: .cfi_restore s13869; RV32ZVE32F-NEXT: addi sp, sp, 163870; RV32ZVE32F-NEXT: .cfi_def_cfa_offset 03871; RV32ZVE32F-NEXT: ret3872;3873; RV64ZVE32F-LABEL: mgather_v8i64:3874; RV64ZVE32F: # %bb.0:3875; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma3876; RV64ZVE32F-NEXT: vmv.x.s a6, v03877; RV64ZVE32F-NEXT: andi a3, a6, 13878; RV64ZVE32F-NEXT: beqz a3, .LBB47_93879; RV64ZVE32F-NEXT: # %bb.1: # %cond.load3880; RV64ZVE32F-NEXT: ld a3, 0(a1)3881; RV64ZVE32F-NEXT: ld a3, 0(a3)3882; RV64ZVE32F-NEXT: andi a4, a6, 23883; RV64ZVE32F-NEXT: bnez a4, .LBB47_103884; RV64ZVE32F-NEXT: .LBB47_2:3885; RV64ZVE32F-NEXT: ld a4, 8(a2)3886; RV64ZVE32F-NEXT: andi a5, a6, 43887; RV64ZVE32F-NEXT: bnez a5, .LBB47_113888; RV64ZVE32F-NEXT: .LBB47_3:3889; RV64ZVE32F-NEXT: ld a5, 16(a2)3890; RV64ZVE32F-NEXT: andi a7, a6, 83891; RV64ZVE32F-NEXT: bnez a7, .LBB47_123892; RV64ZVE32F-NEXT: .LBB47_4:3893; RV64ZVE32F-NEXT: ld a7, 24(a2)3894; RV64ZVE32F-NEXT: andi t0, a6, 163895; RV64ZVE32F-NEXT: bnez t0, .LBB47_133896; RV64ZVE32F-NEXT: .LBB47_5:3897; RV64ZVE32F-NEXT: ld t0, 32(a2)3898; RV64ZVE32F-NEXT: andi t1, a6, 323899; RV64ZVE32F-NEXT: bnez t1, .LBB47_143900; RV64ZVE32F-NEXT: .LBB47_6:3901; RV64ZVE32F-NEXT: ld t1, 40(a2)3902; RV64ZVE32F-NEXT: andi t2, a6, 643903; RV64ZVE32F-NEXT: bnez t2, .LBB47_153904; RV64ZVE32F-NEXT: .LBB47_7:3905; RV64ZVE32F-NEXT: ld t2, 48(a2)3906; RV64ZVE32F-NEXT: andi a6, a6, -1283907; RV64ZVE32F-NEXT: bnez a6, .LBB47_163908; RV64ZVE32F-NEXT: .LBB47_8:3909; RV64ZVE32F-NEXT: ld a1, 56(a2)3910; RV64ZVE32F-NEXT: j .LBB47_173911; RV64ZVE32F-NEXT: .LBB47_9:3912; RV64ZVE32F-NEXT: ld a3, 0(a2)3913; RV64ZVE32F-NEXT: andi a4, a6, 23914; RV64ZVE32F-NEXT: beqz a4, .LBB47_23915; RV64ZVE32F-NEXT: .LBB47_10: # %cond.load13916; RV64ZVE32F-NEXT: ld a4, 8(a1)3917; RV64ZVE32F-NEXT: ld a4, 0(a4)3918; RV64ZVE32F-NEXT: andi a5, a6, 43919; RV64ZVE32F-NEXT: beqz a5, .LBB47_33920; RV64ZVE32F-NEXT: .LBB47_11: # %cond.load43921; RV64ZVE32F-NEXT: ld a5, 16(a1)3922; RV64ZVE32F-NEXT: ld a5, 0(a5)3923; RV64ZVE32F-NEXT: andi a7, a6, 83924; RV64ZVE32F-NEXT: beqz a7, .LBB47_43925; RV64ZVE32F-NEXT: .LBB47_12: # %cond.load73926; RV64ZVE32F-NEXT: ld a7, 24(a1)3927; RV64ZVE32F-NEXT: ld a7, 0(a7)3928; RV64ZVE32F-NEXT: andi t0, a6, 163929; RV64ZVE32F-NEXT: beqz t0, .LBB47_53930; RV64ZVE32F-NEXT: .LBB47_13: # %cond.load103931; RV64ZVE32F-NEXT: ld t0, 32(a1)3932; RV64ZVE32F-NEXT: ld t0, 0(t0)3933; RV64ZVE32F-NEXT: andi t1, a6, 323934; RV64ZVE32F-NEXT: beqz t1, .LBB47_63935; RV64ZVE32F-NEXT: .LBB47_14: # %cond.load133936; RV64ZVE32F-NEXT: ld t1, 40(a1)3937; RV64ZVE32F-NEXT: ld t1, 0(t1)3938; RV64ZVE32F-NEXT: andi t2, a6, 643939; RV64ZVE32F-NEXT: beqz t2, .LBB47_73940; RV64ZVE32F-NEXT: .LBB47_15: # %cond.load163941; RV64ZVE32F-NEXT: ld t2, 48(a1)3942; RV64ZVE32F-NEXT: ld t2, 0(t2)3943; RV64ZVE32F-NEXT: andi a6, a6, -1283944; RV64ZVE32F-NEXT: beqz a6, .LBB47_83945; RV64ZVE32F-NEXT: .LBB47_16: # %cond.load193946; RV64ZVE32F-NEXT: ld a1, 56(a1)3947; RV64ZVE32F-NEXT: ld a1, 0(a1)3948; RV64ZVE32F-NEXT: .LBB47_17: # %else203949; RV64ZVE32F-NEXT: sd a3, 0(a0)3950; RV64ZVE32F-NEXT: sd a4, 8(a0)3951; RV64ZVE32F-NEXT: sd a5, 16(a0)3952; RV64ZVE32F-NEXT: sd a7, 24(a0)3953; RV64ZVE32F-NEXT: sd t0, 32(a0)3954; RV64ZVE32F-NEXT: sd t1, 40(a0)3955; RV64ZVE32F-NEXT: sd t2, 48(a0)3956; RV64ZVE32F-NEXT: sd a1, 56(a0)3957; RV64ZVE32F-NEXT: ret3958 %v = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> %ptrs, i32 8, <8 x i1> %m, <8 x i64> %passthru)3959 ret <8 x i64> %v3960}3961 3962define <8 x i64> @mgather_baseidx_v8i8_v8i64(ptr %base, <8 x i8> %idxs, <8 x i1> %m, <8 x i64> %passthru) {3963; RV32V-LABEL: mgather_baseidx_v8i8_v8i64:3964; RV32V: # %bb.0:3965; RV32V-NEXT: vsetivli zero, 8, e32, m2, ta, ma3966; RV32V-NEXT: vsext.vf4 v10, v83967; RV32V-NEXT: vsll.vi v8, v10, 33968; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, mu3969; RV32V-NEXT: vluxei32.v v12, (a0), v8, v0.t3970; RV32V-NEXT: vmv.v.v v8, v123971; RV32V-NEXT: ret3972;3973; RV64V-LABEL: mgather_baseidx_v8i8_v8i64:3974; RV64V: # %bb.0:3975; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, mu3976; RV64V-NEXT: vsext.vf8 v16, v83977; RV64V-NEXT: vsll.vi v8, v16, 33978; RV64V-NEXT: vluxei64.v v12, (a0), v8, v0.t3979; RV64V-NEXT: vmv.v.v v8, v123980; RV64V-NEXT: ret3981;3982; RV32ZVE32F-LABEL: mgather_baseidx_v8i8_v8i64:3983; RV32ZVE32F: # %bb.0:3984; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma3985; RV32ZVE32F-NEXT: vsext.vf4 v10, v83986; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma3987; RV32ZVE32F-NEXT: vmv.x.s t0, v03988; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma3989; RV32ZVE32F-NEXT: vsll.vi v8, v10, 33990; RV32ZVE32F-NEXT: andi a3, t0, 13991; RV32ZVE32F-NEXT: vadd.vx v8, v8, a13992; RV32ZVE32F-NEXT: beqz a3, .LBB48_73993; RV32ZVE32F-NEXT: # %bb.1: # %cond.load3994; RV32ZVE32F-NEXT: vmv.x.s a3, v83995; RV32ZVE32F-NEXT: lw a1, 0(a3)3996; RV32ZVE32F-NEXT: lw a3, 4(a3)3997; RV32ZVE32F-NEXT: andi a4, t0, 23998; RV32ZVE32F-NEXT: bnez a4, .LBB48_83999; RV32ZVE32F-NEXT: .LBB48_2:4000; RV32ZVE32F-NEXT: lw a4, 8(a2)4001; RV32ZVE32F-NEXT: lw a5, 12(a2)4002; RV32ZVE32F-NEXT: andi a6, t0, 44003; RV32ZVE32F-NEXT: bnez a6, .LBB48_94004; RV32ZVE32F-NEXT: .LBB48_3:4005; RV32ZVE32F-NEXT: lw a6, 16(a2)4006; RV32ZVE32F-NEXT: lw a7, 20(a2)4007; RV32ZVE32F-NEXT: andi t1, t0, 84008; RV32ZVE32F-NEXT: bnez t1, .LBB48_104009; RV32ZVE32F-NEXT: .LBB48_4:4010; RV32ZVE32F-NEXT: lw t1, 24(a2)4011; RV32ZVE32F-NEXT: lw t2, 28(a2)4012; RV32ZVE32F-NEXT: andi t3, t0, 164013; RV32ZVE32F-NEXT: bnez t3, .LBB48_114014; RV32ZVE32F-NEXT: .LBB48_5:4015; RV32ZVE32F-NEXT: lw t3, 32(a2)4016; RV32ZVE32F-NEXT: lw t4, 36(a2)4017; RV32ZVE32F-NEXT: andi t5, t0, 324018; RV32ZVE32F-NEXT: bnez t5, .LBB48_124019; RV32ZVE32F-NEXT: .LBB48_6:4020; RV32ZVE32F-NEXT: lw t5, 40(a2)4021; RV32ZVE32F-NEXT: lw t6, 44(a2)4022; RV32ZVE32F-NEXT: j .LBB48_134023; RV32ZVE32F-NEXT: .LBB48_7:4024; RV32ZVE32F-NEXT: lw a1, 0(a2)4025; RV32ZVE32F-NEXT: lw a3, 4(a2)4026; RV32ZVE32F-NEXT: andi a4, t0, 24027; RV32ZVE32F-NEXT: beqz a4, .LBB48_24028; RV32ZVE32F-NEXT: .LBB48_8: # %cond.load14029; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma4030; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 14031; RV32ZVE32F-NEXT: vmv.x.s a5, v104032; RV32ZVE32F-NEXT: lw a4, 0(a5)4033; RV32ZVE32F-NEXT: lw a5, 4(a5)4034; RV32ZVE32F-NEXT: andi a6, t0, 44035; RV32ZVE32F-NEXT: beqz a6, .LBB48_34036; RV32ZVE32F-NEXT: .LBB48_9: # %cond.load44037; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma4038; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 24039; RV32ZVE32F-NEXT: vmv.x.s a7, v104040; RV32ZVE32F-NEXT: lw a6, 0(a7)4041; RV32ZVE32F-NEXT: lw a7, 4(a7)4042; RV32ZVE32F-NEXT: andi t1, t0, 84043; RV32ZVE32F-NEXT: beqz t1, .LBB48_44044; RV32ZVE32F-NEXT: .LBB48_10: # %cond.load74045; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma4046; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 34047; RV32ZVE32F-NEXT: vmv.x.s t2, v104048; RV32ZVE32F-NEXT: lw t1, 0(t2)4049; RV32ZVE32F-NEXT: lw t2, 4(t2)4050; RV32ZVE32F-NEXT: andi t3, t0, 164051; RV32ZVE32F-NEXT: beqz t3, .LBB48_54052; RV32ZVE32F-NEXT: .LBB48_11: # %cond.load104053; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma4054; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 44055; RV32ZVE32F-NEXT: vmv.x.s t4, v104056; RV32ZVE32F-NEXT: lw t3, 0(t4)4057; RV32ZVE32F-NEXT: lw t4, 4(t4)4058; RV32ZVE32F-NEXT: andi t5, t0, 324059; RV32ZVE32F-NEXT: beqz t5, .LBB48_64060; RV32ZVE32F-NEXT: .LBB48_12: # %cond.load134061; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma4062; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 54063; RV32ZVE32F-NEXT: vmv.x.s t6, v104064; RV32ZVE32F-NEXT: lw t5, 0(t6)4065; RV32ZVE32F-NEXT: lw t6, 4(t6)4066; RV32ZVE32F-NEXT: .LBB48_13: # %else144067; RV32ZVE32F-NEXT: addi sp, sp, -164068; RV32ZVE32F-NEXT: .cfi_def_cfa_offset 164069; RV32ZVE32F-NEXT: sw s0, 12(sp) # 4-byte Folded Spill4070; RV32ZVE32F-NEXT: sw s1, 8(sp) # 4-byte Folded Spill4071; RV32ZVE32F-NEXT: .cfi_offset s0, -44072; RV32ZVE32F-NEXT: .cfi_offset s1, -84073; RV32ZVE32F-NEXT: andi s0, t0, 644074; RV32ZVE32F-NEXT: beqz s0, .LBB48_164075; RV32ZVE32F-NEXT: # %bb.14: # %cond.load164076; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma4077; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 64078; RV32ZVE32F-NEXT: vmv.x.s s1, v104079; RV32ZVE32F-NEXT: lw s0, 0(s1)4080; RV32ZVE32F-NEXT: lw s1, 4(s1)4081; RV32ZVE32F-NEXT: andi t0, t0, -1284082; RV32ZVE32F-NEXT: bnez t0, .LBB48_174083; RV32ZVE32F-NEXT: .LBB48_15:4084; RV32ZVE32F-NEXT: lw t0, 56(a2)4085; RV32ZVE32F-NEXT: lw a2, 60(a2)4086; RV32ZVE32F-NEXT: j .LBB48_184087; RV32ZVE32F-NEXT: .LBB48_16:4088; RV32ZVE32F-NEXT: lw s0, 48(a2)4089; RV32ZVE32F-NEXT: lw s1, 52(a2)4090; RV32ZVE32F-NEXT: andi t0, t0, -1284091; RV32ZVE32F-NEXT: beqz t0, .LBB48_154092; RV32ZVE32F-NEXT: .LBB48_17: # %cond.load194093; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma4094; RV32ZVE32F-NEXT: vslidedown.vi v8, v8, 74095; RV32ZVE32F-NEXT: vmv.x.s a2, v84096; RV32ZVE32F-NEXT: lw t0, 0(a2)4097; RV32ZVE32F-NEXT: lw a2, 4(a2)4098; RV32ZVE32F-NEXT: .LBB48_18: # %else204099; RV32ZVE32F-NEXT: sw a1, 0(a0)4100; RV32ZVE32F-NEXT: sw a3, 4(a0)4101; RV32ZVE32F-NEXT: sw a4, 8(a0)4102; RV32ZVE32F-NEXT: sw a5, 12(a0)4103; RV32ZVE32F-NEXT: sw a6, 16(a0)4104; RV32ZVE32F-NEXT: sw a7, 20(a0)4105; RV32ZVE32F-NEXT: sw t1, 24(a0)4106; RV32ZVE32F-NEXT: sw t2, 28(a0)4107; RV32ZVE32F-NEXT: sw t3, 32(a0)4108; RV32ZVE32F-NEXT: sw t4, 36(a0)4109; RV32ZVE32F-NEXT: sw t5, 40(a0)4110; RV32ZVE32F-NEXT: sw t6, 44(a0)4111; RV32ZVE32F-NEXT: sw s0, 48(a0)4112; RV32ZVE32F-NEXT: sw s1, 52(a0)4113; RV32ZVE32F-NEXT: sw t0, 56(a0)4114; RV32ZVE32F-NEXT: sw a2, 60(a0)4115; RV32ZVE32F-NEXT: lw s0, 12(sp) # 4-byte Folded Reload4116; RV32ZVE32F-NEXT: lw s1, 8(sp) # 4-byte Folded Reload4117; RV32ZVE32F-NEXT: .cfi_restore s04118; RV32ZVE32F-NEXT: .cfi_restore s14119; RV32ZVE32F-NEXT: addi sp, sp, 164120; RV32ZVE32F-NEXT: .cfi_def_cfa_offset 04121; RV32ZVE32F-NEXT: ret4122;4123; RV64ZVE32F-LABEL: mgather_baseidx_v8i8_v8i64:4124; RV64ZVE32F: # %bb.0:4125; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma4126; RV64ZVE32F-NEXT: vmv.x.s a5, v04127; RV64ZVE32F-NEXT: andi a3, a5, 14128; RV64ZVE32F-NEXT: beqz a3, .LBB48_34129; RV64ZVE32F-NEXT: # %bb.1: # %cond.load4130; RV64ZVE32F-NEXT: vmv.x.s a3, v84131; RV64ZVE32F-NEXT: slli a3, a3, 34132; RV64ZVE32F-NEXT: add a3, a1, a34133; RV64ZVE32F-NEXT: ld a3, 0(a3)4134; RV64ZVE32F-NEXT: andi a4, a5, 24135; RV64ZVE32F-NEXT: bnez a4, .LBB48_44136; RV64ZVE32F-NEXT: .LBB48_2:4137; RV64ZVE32F-NEXT: ld a4, 8(a2)4138; RV64ZVE32F-NEXT: j .LBB48_54139; RV64ZVE32F-NEXT: .LBB48_3:4140; RV64ZVE32F-NEXT: ld a3, 0(a2)4141; RV64ZVE32F-NEXT: andi a4, a5, 24142; RV64ZVE32F-NEXT: beqz a4, .LBB48_24143; RV64ZVE32F-NEXT: .LBB48_4: # %cond.load14144; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma4145; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 14146; RV64ZVE32F-NEXT: vmv.x.s a4, v94147; RV64ZVE32F-NEXT: slli a4, a4, 34148; RV64ZVE32F-NEXT: add a4, a1, a44149; RV64ZVE32F-NEXT: ld a4, 0(a4)4150; RV64ZVE32F-NEXT: .LBB48_5: # %else24151; RV64ZVE32F-NEXT: andi a6, a5, 44152; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma4153; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 24154; RV64ZVE32F-NEXT: beqz a6, .LBB48_84155; RV64ZVE32F-NEXT: # %bb.6: # %cond.load44156; RV64ZVE32F-NEXT: vmv.x.s a6, v94157; RV64ZVE32F-NEXT: slli a6, a6, 34158; RV64ZVE32F-NEXT: add a6, a1, a64159; RV64ZVE32F-NEXT: ld a6, 0(a6)4160; RV64ZVE32F-NEXT: andi a7, a5, 84161; RV64ZVE32F-NEXT: bnez a7, .LBB48_94162; RV64ZVE32F-NEXT: .LBB48_7:4163; RV64ZVE32F-NEXT: ld a7, 24(a2)4164; RV64ZVE32F-NEXT: j .LBB48_104165; RV64ZVE32F-NEXT: .LBB48_8:4166; RV64ZVE32F-NEXT: ld a6, 16(a2)4167; RV64ZVE32F-NEXT: andi a7, a5, 84168; RV64ZVE32F-NEXT: beqz a7, .LBB48_74169; RV64ZVE32F-NEXT: .LBB48_9: # %cond.load74170; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 14171; RV64ZVE32F-NEXT: vmv.x.s a7, v94172; RV64ZVE32F-NEXT: slli a7, a7, 34173; RV64ZVE32F-NEXT: add a7, a1, a74174; RV64ZVE32F-NEXT: ld a7, 0(a7)4175; RV64ZVE32F-NEXT: .LBB48_10: # %else84176; RV64ZVE32F-NEXT: andi t0, a5, 164177; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma4178; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 44179; RV64ZVE32F-NEXT: beqz t0, .LBB48_134180; RV64ZVE32F-NEXT: # %bb.11: # %cond.load104181; RV64ZVE32F-NEXT: vmv.x.s t0, v84182; RV64ZVE32F-NEXT: slli t0, t0, 34183; RV64ZVE32F-NEXT: add t0, a1, t04184; RV64ZVE32F-NEXT: ld t0, 0(t0)4185; RV64ZVE32F-NEXT: andi t1, a5, 324186; RV64ZVE32F-NEXT: bnez t1, .LBB48_144187; RV64ZVE32F-NEXT: .LBB48_12:4188; RV64ZVE32F-NEXT: ld t1, 40(a2)4189; RV64ZVE32F-NEXT: j .LBB48_154190; RV64ZVE32F-NEXT: .LBB48_13:4191; RV64ZVE32F-NEXT: ld t0, 32(a2)4192; RV64ZVE32F-NEXT: andi t1, a5, 324193; RV64ZVE32F-NEXT: beqz t1, .LBB48_124194; RV64ZVE32F-NEXT: .LBB48_14: # %cond.load134195; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma4196; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 14197; RV64ZVE32F-NEXT: vmv.x.s t1, v94198; RV64ZVE32F-NEXT: slli t1, t1, 34199; RV64ZVE32F-NEXT: add t1, a1, t14200; RV64ZVE32F-NEXT: ld t1, 0(t1)4201; RV64ZVE32F-NEXT: .LBB48_15: # %else144202; RV64ZVE32F-NEXT: andi t2, a5, 644203; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma4204; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 24205; RV64ZVE32F-NEXT: beqz t2, .LBB48_184206; RV64ZVE32F-NEXT: # %bb.16: # %cond.load164207; RV64ZVE32F-NEXT: vmv.x.s t2, v84208; RV64ZVE32F-NEXT: slli t2, t2, 34209; RV64ZVE32F-NEXT: add t2, a1, t24210; RV64ZVE32F-NEXT: ld t2, 0(t2)4211; RV64ZVE32F-NEXT: andi a5, a5, -1284212; RV64ZVE32F-NEXT: bnez a5, .LBB48_194213; RV64ZVE32F-NEXT: .LBB48_17:4214; RV64ZVE32F-NEXT: ld a1, 56(a2)4215; RV64ZVE32F-NEXT: j .LBB48_204216; RV64ZVE32F-NEXT: .LBB48_18:4217; RV64ZVE32F-NEXT: ld t2, 48(a2)4218; RV64ZVE32F-NEXT: andi a5, a5, -1284219; RV64ZVE32F-NEXT: beqz a5, .LBB48_174220; RV64ZVE32F-NEXT: .LBB48_19: # %cond.load194221; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 14222; RV64ZVE32F-NEXT: vmv.x.s a2, v84223; RV64ZVE32F-NEXT: slli a2, a2, 34224; RV64ZVE32F-NEXT: add a1, a1, a24225; RV64ZVE32F-NEXT: ld a1, 0(a1)4226; RV64ZVE32F-NEXT: .LBB48_20: # %else204227; RV64ZVE32F-NEXT: sd a3, 0(a0)4228; RV64ZVE32F-NEXT: sd a4, 8(a0)4229; RV64ZVE32F-NEXT: sd a6, 16(a0)4230; RV64ZVE32F-NEXT: sd a7, 24(a0)4231; RV64ZVE32F-NEXT: sd t0, 32(a0)4232; RV64ZVE32F-NEXT: sd t1, 40(a0)4233; RV64ZVE32F-NEXT: sd t2, 48(a0)4234; RV64ZVE32F-NEXT: sd a1, 56(a0)4235; RV64ZVE32F-NEXT: ret4236 %ptrs = getelementptr inbounds i64, ptr %base, <8 x i8> %idxs4237 %v = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> %ptrs, i32 8, <8 x i1> %m, <8 x i64> %passthru)4238 ret <8 x i64> %v4239}4240 4241define <8 x i64> @mgather_baseidx_sext_v8i8_v8i64(ptr %base, <8 x i8> %idxs, <8 x i1> %m, <8 x i64> %passthru) {4242; RV32V-LABEL: mgather_baseidx_sext_v8i8_v8i64:4243; RV32V: # %bb.0:4244; RV32V-NEXT: vsetivli zero, 8, e32, m2, ta, ma4245; RV32V-NEXT: vsext.vf4 v10, v84246; RV32V-NEXT: vsll.vi v8, v10, 34247; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, mu4248; RV32V-NEXT: vluxei32.v v12, (a0), v8, v0.t4249; RV32V-NEXT: vmv.v.v v8, v124250; RV32V-NEXT: ret4251;4252; RV64V-LABEL: mgather_baseidx_sext_v8i8_v8i64:4253; RV64V: # %bb.0:4254; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, mu4255; RV64V-NEXT: vsext.vf8 v16, v84256; RV64V-NEXT: vsll.vi v8, v16, 34257; RV64V-NEXT: vluxei64.v v12, (a0), v8, v0.t4258; RV64V-NEXT: vmv.v.v v8, v124259; RV64V-NEXT: ret4260;4261; RV32ZVE32F-LABEL: mgather_baseidx_sext_v8i8_v8i64:4262; RV32ZVE32F: # %bb.0:4263; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma4264; RV32ZVE32F-NEXT: vsext.vf4 v10, v84265; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma4266; RV32ZVE32F-NEXT: vmv.x.s t0, v04267; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma4268; RV32ZVE32F-NEXT: vsll.vi v8, v10, 34269; RV32ZVE32F-NEXT: andi a3, t0, 14270; RV32ZVE32F-NEXT: vadd.vx v8, v8, a14271; RV32ZVE32F-NEXT: beqz a3, .LBB49_74272; RV32ZVE32F-NEXT: # %bb.1: # %cond.load4273; RV32ZVE32F-NEXT: vmv.x.s a3, v84274; RV32ZVE32F-NEXT: lw a1, 0(a3)4275; RV32ZVE32F-NEXT: lw a3, 4(a3)4276; RV32ZVE32F-NEXT: andi a4, t0, 24277; RV32ZVE32F-NEXT: bnez a4, .LBB49_84278; RV32ZVE32F-NEXT: .LBB49_2:4279; RV32ZVE32F-NEXT: lw a4, 8(a2)4280; RV32ZVE32F-NEXT: lw a5, 12(a2)4281; RV32ZVE32F-NEXT: andi a6, t0, 44282; RV32ZVE32F-NEXT: bnez a6, .LBB49_94283; RV32ZVE32F-NEXT: .LBB49_3:4284; RV32ZVE32F-NEXT: lw a6, 16(a2)4285; RV32ZVE32F-NEXT: lw a7, 20(a2)4286; RV32ZVE32F-NEXT: andi t1, t0, 84287; RV32ZVE32F-NEXT: bnez t1, .LBB49_104288; RV32ZVE32F-NEXT: .LBB49_4:4289; RV32ZVE32F-NEXT: lw t1, 24(a2)4290; RV32ZVE32F-NEXT: lw t2, 28(a2)4291; RV32ZVE32F-NEXT: andi t3, t0, 164292; RV32ZVE32F-NEXT: bnez t3, .LBB49_114293; RV32ZVE32F-NEXT: .LBB49_5:4294; RV32ZVE32F-NEXT: lw t3, 32(a2)4295; RV32ZVE32F-NEXT: lw t4, 36(a2)4296; RV32ZVE32F-NEXT: andi t5, t0, 324297; RV32ZVE32F-NEXT: bnez t5, .LBB49_124298; RV32ZVE32F-NEXT: .LBB49_6:4299; RV32ZVE32F-NEXT: lw t5, 40(a2)4300; RV32ZVE32F-NEXT: lw t6, 44(a2)4301; RV32ZVE32F-NEXT: j .LBB49_134302; RV32ZVE32F-NEXT: .LBB49_7:4303; RV32ZVE32F-NEXT: lw a1, 0(a2)4304; RV32ZVE32F-NEXT: lw a3, 4(a2)4305; RV32ZVE32F-NEXT: andi a4, t0, 24306; RV32ZVE32F-NEXT: beqz a4, .LBB49_24307; RV32ZVE32F-NEXT: .LBB49_8: # %cond.load14308; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma4309; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 14310; RV32ZVE32F-NEXT: vmv.x.s a5, v104311; RV32ZVE32F-NEXT: lw a4, 0(a5)4312; RV32ZVE32F-NEXT: lw a5, 4(a5)4313; RV32ZVE32F-NEXT: andi a6, t0, 44314; RV32ZVE32F-NEXT: beqz a6, .LBB49_34315; RV32ZVE32F-NEXT: .LBB49_9: # %cond.load44316; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma4317; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 24318; RV32ZVE32F-NEXT: vmv.x.s a7, v104319; RV32ZVE32F-NEXT: lw a6, 0(a7)4320; RV32ZVE32F-NEXT: lw a7, 4(a7)4321; RV32ZVE32F-NEXT: andi t1, t0, 84322; RV32ZVE32F-NEXT: beqz t1, .LBB49_44323; RV32ZVE32F-NEXT: .LBB49_10: # %cond.load74324; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma4325; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 34326; RV32ZVE32F-NEXT: vmv.x.s t2, v104327; RV32ZVE32F-NEXT: lw t1, 0(t2)4328; RV32ZVE32F-NEXT: lw t2, 4(t2)4329; RV32ZVE32F-NEXT: andi t3, t0, 164330; RV32ZVE32F-NEXT: beqz t3, .LBB49_54331; RV32ZVE32F-NEXT: .LBB49_11: # %cond.load104332; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma4333; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 44334; RV32ZVE32F-NEXT: vmv.x.s t4, v104335; RV32ZVE32F-NEXT: lw t3, 0(t4)4336; RV32ZVE32F-NEXT: lw t4, 4(t4)4337; RV32ZVE32F-NEXT: andi t5, t0, 324338; RV32ZVE32F-NEXT: beqz t5, .LBB49_64339; RV32ZVE32F-NEXT: .LBB49_12: # %cond.load134340; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma4341; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 54342; RV32ZVE32F-NEXT: vmv.x.s t6, v104343; RV32ZVE32F-NEXT: lw t5, 0(t6)4344; RV32ZVE32F-NEXT: lw t6, 4(t6)4345; RV32ZVE32F-NEXT: .LBB49_13: # %else144346; RV32ZVE32F-NEXT: addi sp, sp, -164347; RV32ZVE32F-NEXT: .cfi_def_cfa_offset 164348; RV32ZVE32F-NEXT: sw s0, 12(sp) # 4-byte Folded Spill4349; RV32ZVE32F-NEXT: sw s1, 8(sp) # 4-byte Folded Spill4350; RV32ZVE32F-NEXT: .cfi_offset s0, -44351; RV32ZVE32F-NEXT: .cfi_offset s1, -84352; RV32ZVE32F-NEXT: andi s0, t0, 644353; RV32ZVE32F-NEXT: beqz s0, .LBB49_164354; RV32ZVE32F-NEXT: # %bb.14: # %cond.load164355; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma4356; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 64357; RV32ZVE32F-NEXT: vmv.x.s s1, v104358; RV32ZVE32F-NEXT: lw s0, 0(s1)4359; RV32ZVE32F-NEXT: lw s1, 4(s1)4360; RV32ZVE32F-NEXT: andi t0, t0, -1284361; RV32ZVE32F-NEXT: bnez t0, .LBB49_174362; RV32ZVE32F-NEXT: .LBB49_15:4363; RV32ZVE32F-NEXT: lw t0, 56(a2)4364; RV32ZVE32F-NEXT: lw a2, 60(a2)4365; RV32ZVE32F-NEXT: j .LBB49_184366; RV32ZVE32F-NEXT: .LBB49_16:4367; RV32ZVE32F-NEXT: lw s0, 48(a2)4368; RV32ZVE32F-NEXT: lw s1, 52(a2)4369; RV32ZVE32F-NEXT: andi t0, t0, -1284370; RV32ZVE32F-NEXT: beqz t0, .LBB49_154371; RV32ZVE32F-NEXT: .LBB49_17: # %cond.load194372; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma4373; RV32ZVE32F-NEXT: vslidedown.vi v8, v8, 74374; RV32ZVE32F-NEXT: vmv.x.s a2, v84375; RV32ZVE32F-NEXT: lw t0, 0(a2)4376; RV32ZVE32F-NEXT: lw a2, 4(a2)4377; RV32ZVE32F-NEXT: .LBB49_18: # %else204378; RV32ZVE32F-NEXT: sw a1, 0(a0)4379; RV32ZVE32F-NEXT: sw a3, 4(a0)4380; RV32ZVE32F-NEXT: sw a4, 8(a0)4381; RV32ZVE32F-NEXT: sw a5, 12(a0)4382; RV32ZVE32F-NEXT: sw a6, 16(a0)4383; RV32ZVE32F-NEXT: sw a7, 20(a0)4384; RV32ZVE32F-NEXT: sw t1, 24(a0)4385; RV32ZVE32F-NEXT: sw t2, 28(a0)4386; RV32ZVE32F-NEXT: sw t3, 32(a0)4387; RV32ZVE32F-NEXT: sw t4, 36(a0)4388; RV32ZVE32F-NEXT: sw t5, 40(a0)4389; RV32ZVE32F-NEXT: sw t6, 44(a0)4390; RV32ZVE32F-NEXT: sw s0, 48(a0)4391; RV32ZVE32F-NEXT: sw s1, 52(a0)4392; RV32ZVE32F-NEXT: sw t0, 56(a0)4393; RV32ZVE32F-NEXT: sw a2, 60(a0)4394; RV32ZVE32F-NEXT: lw s0, 12(sp) # 4-byte Folded Reload4395; RV32ZVE32F-NEXT: lw s1, 8(sp) # 4-byte Folded Reload4396; RV32ZVE32F-NEXT: .cfi_restore s04397; RV32ZVE32F-NEXT: .cfi_restore s14398; RV32ZVE32F-NEXT: addi sp, sp, 164399; RV32ZVE32F-NEXT: .cfi_def_cfa_offset 04400; RV32ZVE32F-NEXT: ret4401;4402; RV64ZVE32F-LABEL: mgather_baseidx_sext_v8i8_v8i64:4403; RV64ZVE32F: # %bb.0:4404; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma4405; RV64ZVE32F-NEXT: vmv.x.s a5, v04406; RV64ZVE32F-NEXT: andi a3, a5, 14407; RV64ZVE32F-NEXT: beqz a3, .LBB49_34408; RV64ZVE32F-NEXT: # %bb.1: # %cond.load4409; RV64ZVE32F-NEXT: vmv.x.s a3, v84410; RV64ZVE32F-NEXT: slli a3, a3, 34411; RV64ZVE32F-NEXT: add a3, a1, a34412; RV64ZVE32F-NEXT: ld a3, 0(a3)4413; RV64ZVE32F-NEXT: andi a4, a5, 24414; RV64ZVE32F-NEXT: bnez a4, .LBB49_44415; RV64ZVE32F-NEXT: .LBB49_2:4416; RV64ZVE32F-NEXT: ld a4, 8(a2)4417; RV64ZVE32F-NEXT: j .LBB49_54418; RV64ZVE32F-NEXT: .LBB49_3:4419; RV64ZVE32F-NEXT: ld a3, 0(a2)4420; RV64ZVE32F-NEXT: andi a4, a5, 24421; RV64ZVE32F-NEXT: beqz a4, .LBB49_24422; RV64ZVE32F-NEXT: .LBB49_4: # %cond.load14423; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma4424; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 14425; RV64ZVE32F-NEXT: vmv.x.s a4, v94426; RV64ZVE32F-NEXT: slli a4, a4, 34427; RV64ZVE32F-NEXT: add a4, a1, a44428; RV64ZVE32F-NEXT: ld a4, 0(a4)4429; RV64ZVE32F-NEXT: .LBB49_5: # %else24430; RV64ZVE32F-NEXT: andi a6, a5, 44431; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma4432; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 24433; RV64ZVE32F-NEXT: beqz a6, .LBB49_84434; RV64ZVE32F-NEXT: # %bb.6: # %cond.load44435; RV64ZVE32F-NEXT: vmv.x.s a6, v94436; RV64ZVE32F-NEXT: slli a6, a6, 34437; RV64ZVE32F-NEXT: add a6, a1, a64438; RV64ZVE32F-NEXT: ld a6, 0(a6)4439; RV64ZVE32F-NEXT: andi a7, a5, 84440; RV64ZVE32F-NEXT: bnez a7, .LBB49_94441; RV64ZVE32F-NEXT: .LBB49_7:4442; RV64ZVE32F-NEXT: ld a7, 24(a2)4443; RV64ZVE32F-NEXT: j .LBB49_104444; RV64ZVE32F-NEXT: .LBB49_8:4445; RV64ZVE32F-NEXT: ld a6, 16(a2)4446; RV64ZVE32F-NEXT: andi a7, a5, 84447; RV64ZVE32F-NEXT: beqz a7, .LBB49_74448; RV64ZVE32F-NEXT: .LBB49_9: # %cond.load74449; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 14450; RV64ZVE32F-NEXT: vmv.x.s a7, v94451; RV64ZVE32F-NEXT: slli a7, a7, 34452; RV64ZVE32F-NEXT: add a7, a1, a74453; RV64ZVE32F-NEXT: ld a7, 0(a7)4454; RV64ZVE32F-NEXT: .LBB49_10: # %else84455; RV64ZVE32F-NEXT: andi t0, a5, 164456; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma4457; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 44458; RV64ZVE32F-NEXT: beqz t0, .LBB49_134459; RV64ZVE32F-NEXT: # %bb.11: # %cond.load104460; RV64ZVE32F-NEXT: vmv.x.s t0, v84461; RV64ZVE32F-NEXT: slli t0, t0, 34462; RV64ZVE32F-NEXT: add t0, a1, t04463; RV64ZVE32F-NEXT: ld t0, 0(t0)4464; RV64ZVE32F-NEXT: andi t1, a5, 324465; RV64ZVE32F-NEXT: bnez t1, .LBB49_144466; RV64ZVE32F-NEXT: .LBB49_12:4467; RV64ZVE32F-NEXT: ld t1, 40(a2)4468; RV64ZVE32F-NEXT: j .LBB49_154469; RV64ZVE32F-NEXT: .LBB49_13:4470; RV64ZVE32F-NEXT: ld t0, 32(a2)4471; RV64ZVE32F-NEXT: andi t1, a5, 324472; RV64ZVE32F-NEXT: beqz t1, .LBB49_124473; RV64ZVE32F-NEXT: .LBB49_14: # %cond.load134474; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma4475; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 14476; RV64ZVE32F-NEXT: vmv.x.s t1, v94477; RV64ZVE32F-NEXT: slli t1, t1, 34478; RV64ZVE32F-NEXT: add t1, a1, t14479; RV64ZVE32F-NEXT: ld t1, 0(t1)4480; RV64ZVE32F-NEXT: .LBB49_15: # %else144481; RV64ZVE32F-NEXT: andi t2, a5, 644482; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma4483; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 24484; RV64ZVE32F-NEXT: beqz t2, .LBB49_184485; RV64ZVE32F-NEXT: # %bb.16: # %cond.load164486; RV64ZVE32F-NEXT: vmv.x.s t2, v84487; RV64ZVE32F-NEXT: slli t2, t2, 34488; RV64ZVE32F-NEXT: add t2, a1, t24489; RV64ZVE32F-NEXT: ld t2, 0(t2)4490; RV64ZVE32F-NEXT: andi a5, a5, -1284491; RV64ZVE32F-NEXT: bnez a5, .LBB49_194492; RV64ZVE32F-NEXT: .LBB49_17:4493; RV64ZVE32F-NEXT: ld a1, 56(a2)4494; RV64ZVE32F-NEXT: j .LBB49_204495; RV64ZVE32F-NEXT: .LBB49_18:4496; RV64ZVE32F-NEXT: ld t2, 48(a2)4497; RV64ZVE32F-NEXT: andi a5, a5, -1284498; RV64ZVE32F-NEXT: beqz a5, .LBB49_174499; RV64ZVE32F-NEXT: .LBB49_19: # %cond.load194500; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 14501; RV64ZVE32F-NEXT: vmv.x.s a2, v84502; RV64ZVE32F-NEXT: slli a2, a2, 34503; RV64ZVE32F-NEXT: add a1, a1, a24504; RV64ZVE32F-NEXT: ld a1, 0(a1)4505; RV64ZVE32F-NEXT: .LBB49_20: # %else204506; RV64ZVE32F-NEXT: sd a3, 0(a0)4507; RV64ZVE32F-NEXT: sd a4, 8(a0)4508; RV64ZVE32F-NEXT: sd a6, 16(a0)4509; RV64ZVE32F-NEXT: sd a7, 24(a0)4510; RV64ZVE32F-NEXT: sd t0, 32(a0)4511; RV64ZVE32F-NEXT: sd t1, 40(a0)4512; RV64ZVE32F-NEXT: sd t2, 48(a0)4513; RV64ZVE32F-NEXT: sd a1, 56(a0)4514; RV64ZVE32F-NEXT: ret4515 %eidxs = sext <8 x i8> %idxs to <8 x i64>4516 %ptrs = getelementptr inbounds i64, ptr %base, <8 x i64> %eidxs4517 %v = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> %ptrs, i32 8, <8 x i1> %m, <8 x i64> %passthru)4518 ret <8 x i64> %v4519}4520 4521define <8 x i64> @mgather_baseidx_zext_v8i8_v8i64(ptr %base, <8 x i8> %idxs, <8 x i1> %m, <8 x i64> %passthru) {4522; RV32V-LABEL: mgather_baseidx_zext_v8i8_v8i64:4523; RV32V: # %bb.0:4524; RV32V-NEXT: li a1, 84525; RV32V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma4526; RV32V-NEXT: vwmulu.vx v9, v8, a14527; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, mu4528; RV32V-NEXT: vluxei16.v v12, (a0), v9, v0.t4529; RV32V-NEXT: vmv.v.v v8, v124530; RV32V-NEXT: ret4531;4532; RV64V-LABEL: mgather_baseidx_zext_v8i8_v8i64:4533; RV64V: # %bb.0:4534; RV64V-NEXT: li a1, 84535; RV64V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma4536; RV64V-NEXT: vwmulu.vx v9, v8, a14537; RV64V-NEXT: vsetvli zero, zero, e64, m4, ta, mu4538; RV64V-NEXT: vluxei16.v v12, (a0), v9, v0.t4539; RV64V-NEXT: vmv.v.v v8, v124540; RV64V-NEXT: ret4541;4542; RV32ZVE32F-LABEL: mgather_baseidx_zext_v8i8_v8i64:4543; RV32ZVE32F: # %bb.0:4544; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma4545; RV32ZVE32F-NEXT: vzext.vf4 v10, v84546; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma4547; RV32ZVE32F-NEXT: vmv.x.s t0, v04548; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma4549; RV32ZVE32F-NEXT: vsll.vi v8, v10, 34550; RV32ZVE32F-NEXT: andi a3, t0, 14551; RV32ZVE32F-NEXT: vadd.vx v8, v8, a14552; RV32ZVE32F-NEXT: beqz a3, .LBB50_74553; RV32ZVE32F-NEXT: # %bb.1: # %cond.load4554; RV32ZVE32F-NEXT: vmv.x.s a3, v84555; RV32ZVE32F-NEXT: lw a1, 0(a3)4556; RV32ZVE32F-NEXT: lw a3, 4(a3)4557; RV32ZVE32F-NEXT: andi a4, t0, 24558; RV32ZVE32F-NEXT: bnez a4, .LBB50_84559; RV32ZVE32F-NEXT: .LBB50_2:4560; RV32ZVE32F-NEXT: lw a4, 8(a2)4561; RV32ZVE32F-NEXT: lw a5, 12(a2)4562; RV32ZVE32F-NEXT: andi a6, t0, 44563; RV32ZVE32F-NEXT: bnez a6, .LBB50_94564; RV32ZVE32F-NEXT: .LBB50_3:4565; RV32ZVE32F-NEXT: lw a6, 16(a2)4566; RV32ZVE32F-NEXT: lw a7, 20(a2)4567; RV32ZVE32F-NEXT: andi t1, t0, 84568; RV32ZVE32F-NEXT: bnez t1, .LBB50_104569; RV32ZVE32F-NEXT: .LBB50_4:4570; RV32ZVE32F-NEXT: lw t1, 24(a2)4571; RV32ZVE32F-NEXT: lw t2, 28(a2)4572; RV32ZVE32F-NEXT: andi t3, t0, 164573; RV32ZVE32F-NEXT: bnez t3, .LBB50_114574; RV32ZVE32F-NEXT: .LBB50_5:4575; RV32ZVE32F-NEXT: lw t3, 32(a2)4576; RV32ZVE32F-NEXT: lw t4, 36(a2)4577; RV32ZVE32F-NEXT: andi t5, t0, 324578; RV32ZVE32F-NEXT: bnez t5, .LBB50_124579; RV32ZVE32F-NEXT: .LBB50_6:4580; RV32ZVE32F-NEXT: lw t5, 40(a2)4581; RV32ZVE32F-NEXT: lw t6, 44(a2)4582; RV32ZVE32F-NEXT: j .LBB50_134583; RV32ZVE32F-NEXT: .LBB50_7:4584; RV32ZVE32F-NEXT: lw a1, 0(a2)4585; RV32ZVE32F-NEXT: lw a3, 4(a2)4586; RV32ZVE32F-NEXT: andi a4, t0, 24587; RV32ZVE32F-NEXT: beqz a4, .LBB50_24588; RV32ZVE32F-NEXT: .LBB50_8: # %cond.load14589; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma4590; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 14591; RV32ZVE32F-NEXT: vmv.x.s a5, v104592; RV32ZVE32F-NEXT: lw a4, 0(a5)4593; RV32ZVE32F-NEXT: lw a5, 4(a5)4594; RV32ZVE32F-NEXT: andi a6, t0, 44595; RV32ZVE32F-NEXT: beqz a6, .LBB50_34596; RV32ZVE32F-NEXT: .LBB50_9: # %cond.load44597; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma4598; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 24599; RV32ZVE32F-NEXT: vmv.x.s a7, v104600; RV32ZVE32F-NEXT: lw a6, 0(a7)4601; RV32ZVE32F-NEXT: lw a7, 4(a7)4602; RV32ZVE32F-NEXT: andi t1, t0, 84603; RV32ZVE32F-NEXT: beqz t1, .LBB50_44604; RV32ZVE32F-NEXT: .LBB50_10: # %cond.load74605; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma4606; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 34607; RV32ZVE32F-NEXT: vmv.x.s t2, v104608; RV32ZVE32F-NEXT: lw t1, 0(t2)4609; RV32ZVE32F-NEXT: lw t2, 4(t2)4610; RV32ZVE32F-NEXT: andi t3, t0, 164611; RV32ZVE32F-NEXT: beqz t3, .LBB50_54612; RV32ZVE32F-NEXT: .LBB50_11: # %cond.load104613; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma4614; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 44615; RV32ZVE32F-NEXT: vmv.x.s t4, v104616; RV32ZVE32F-NEXT: lw t3, 0(t4)4617; RV32ZVE32F-NEXT: lw t4, 4(t4)4618; RV32ZVE32F-NEXT: andi t5, t0, 324619; RV32ZVE32F-NEXT: beqz t5, .LBB50_64620; RV32ZVE32F-NEXT: .LBB50_12: # %cond.load134621; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma4622; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 54623; RV32ZVE32F-NEXT: vmv.x.s t6, v104624; RV32ZVE32F-NEXT: lw t5, 0(t6)4625; RV32ZVE32F-NEXT: lw t6, 4(t6)4626; RV32ZVE32F-NEXT: .LBB50_13: # %else144627; RV32ZVE32F-NEXT: addi sp, sp, -164628; RV32ZVE32F-NEXT: .cfi_def_cfa_offset 164629; RV32ZVE32F-NEXT: sw s0, 12(sp) # 4-byte Folded Spill4630; RV32ZVE32F-NEXT: sw s1, 8(sp) # 4-byte Folded Spill4631; RV32ZVE32F-NEXT: .cfi_offset s0, -44632; RV32ZVE32F-NEXT: .cfi_offset s1, -84633; RV32ZVE32F-NEXT: andi s0, t0, 644634; RV32ZVE32F-NEXT: beqz s0, .LBB50_164635; RV32ZVE32F-NEXT: # %bb.14: # %cond.load164636; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma4637; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 64638; RV32ZVE32F-NEXT: vmv.x.s s1, v104639; RV32ZVE32F-NEXT: lw s0, 0(s1)4640; RV32ZVE32F-NEXT: lw s1, 4(s1)4641; RV32ZVE32F-NEXT: andi t0, t0, -1284642; RV32ZVE32F-NEXT: bnez t0, .LBB50_174643; RV32ZVE32F-NEXT: .LBB50_15:4644; RV32ZVE32F-NEXT: lw t0, 56(a2)4645; RV32ZVE32F-NEXT: lw a2, 60(a2)4646; RV32ZVE32F-NEXT: j .LBB50_184647; RV32ZVE32F-NEXT: .LBB50_16:4648; RV32ZVE32F-NEXT: lw s0, 48(a2)4649; RV32ZVE32F-NEXT: lw s1, 52(a2)4650; RV32ZVE32F-NEXT: andi t0, t0, -1284651; RV32ZVE32F-NEXT: beqz t0, .LBB50_154652; RV32ZVE32F-NEXT: .LBB50_17: # %cond.load194653; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma4654; RV32ZVE32F-NEXT: vslidedown.vi v8, v8, 74655; RV32ZVE32F-NEXT: vmv.x.s a2, v84656; RV32ZVE32F-NEXT: lw t0, 0(a2)4657; RV32ZVE32F-NEXT: lw a2, 4(a2)4658; RV32ZVE32F-NEXT: .LBB50_18: # %else204659; RV32ZVE32F-NEXT: sw a1, 0(a0)4660; RV32ZVE32F-NEXT: sw a3, 4(a0)4661; RV32ZVE32F-NEXT: sw a4, 8(a0)4662; RV32ZVE32F-NEXT: sw a5, 12(a0)4663; RV32ZVE32F-NEXT: sw a6, 16(a0)4664; RV32ZVE32F-NEXT: sw a7, 20(a0)4665; RV32ZVE32F-NEXT: sw t1, 24(a0)4666; RV32ZVE32F-NEXT: sw t2, 28(a0)4667; RV32ZVE32F-NEXT: sw t3, 32(a0)4668; RV32ZVE32F-NEXT: sw t4, 36(a0)4669; RV32ZVE32F-NEXT: sw t5, 40(a0)4670; RV32ZVE32F-NEXT: sw t6, 44(a0)4671; RV32ZVE32F-NEXT: sw s0, 48(a0)4672; RV32ZVE32F-NEXT: sw s1, 52(a0)4673; RV32ZVE32F-NEXT: sw t0, 56(a0)4674; RV32ZVE32F-NEXT: sw a2, 60(a0)4675; RV32ZVE32F-NEXT: lw s0, 12(sp) # 4-byte Folded Reload4676; RV32ZVE32F-NEXT: lw s1, 8(sp) # 4-byte Folded Reload4677; RV32ZVE32F-NEXT: .cfi_restore s04678; RV32ZVE32F-NEXT: .cfi_restore s14679; RV32ZVE32F-NEXT: addi sp, sp, 164680; RV32ZVE32F-NEXT: .cfi_def_cfa_offset 04681; RV32ZVE32F-NEXT: ret4682;4683; RV64ZVE32F-LABEL: mgather_baseidx_zext_v8i8_v8i64:4684; RV64ZVE32F: # %bb.0:4685; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma4686; RV64ZVE32F-NEXT: vmv.x.s a5, v04687; RV64ZVE32F-NEXT: andi a3, a5, 14688; RV64ZVE32F-NEXT: beqz a3, .LBB50_34689; RV64ZVE32F-NEXT: # %bb.1: # %cond.load4690; RV64ZVE32F-NEXT: vmv.x.s a3, v84691; RV64ZVE32F-NEXT: zext.b a3, a34692; RV64ZVE32F-NEXT: slli a3, a3, 34693; RV64ZVE32F-NEXT: add a3, a1, a34694; RV64ZVE32F-NEXT: ld a3, 0(a3)4695; RV64ZVE32F-NEXT: andi a4, a5, 24696; RV64ZVE32F-NEXT: bnez a4, .LBB50_44697; RV64ZVE32F-NEXT: .LBB50_2:4698; RV64ZVE32F-NEXT: ld a4, 8(a2)4699; RV64ZVE32F-NEXT: j .LBB50_54700; RV64ZVE32F-NEXT: .LBB50_3:4701; RV64ZVE32F-NEXT: ld a3, 0(a2)4702; RV64ZVE32F-NEXT: andi a4, a5, 24703; RV64ZVE32F-NEXT: beqz a4, .LBB50_24704; RV64ZVE32F-NEXT: .LBB50_4: # %cond.load14705; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma4706; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 14707; RV64ZVE32F-NEXT: vmv.x.s a4, v94708; RV64ZVE32F-NEXT: zext.b a4, a44709; RV64ZVE32F-NEXT: slli a4, a4, 34710; RV64ZVE32F-NEXT: add a4, a1, a44711; RV64ZVE32F-NEXT: ld a4, 0(a4)4712; RV64ZVE32F-NEXT: .LBB50_5: # %else24713; RV64ZVE32F-NEXT: andi a6, a5, 44714; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma4715; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 24716; RV64ZVE32F-NEXT: beqz a6, .LBB50_84717; RV64ZVE32F-NEXT: # %bb.6: # %cond.load44718; RV64ZVE32F-NEXT: vmv.x.s a6, v94719; RV64ZVE32F-NEXT: zext.b a6, a64720; RV64ZVE32F-NEXT: slli a6, a6, 34721; RV64ZVE32F-NEXT: add a6, a1, a64722; RV64ZVE32F-NEXT: ld a6, 0(a6)4723; RV64ZVE32F-NEXT: andi a7, a5, 84724; RV64ZVE32F-NEXT: bnez a7, .LBB50_94725; RV64ZVE32F-NEXT: .LBB50_7:4726; RV64ZVE32F-NEXT: ld a7, 24(a2)4727; RV64ZVE32F-NEXT: j .LBB50_104728; RV64ZVE32F-NEXT: .LBB50_8:4729; RV64ZVE32F-NEXT: ld a6, 16(a2)4730; RV64ZVE32F-NEXT: andi a7, a5, 84731; RV64ZVE32F-NEXT: beqz a7, .LBB50_74732; RV64ZVE32F-NEXT: .LBB50_9: # %cond.load74733; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 14734; RV64ZVE32F-NEXT: vmv.x.s a7, v94735; RV64ZVE32F-NEXT: zext.b a7, a74736; RV64ZVE32F-NEXT: slli a7, a7, 34737; RV64ZVE32F-NEXT: add a7, a1, a74738; RV64ZVE32F-NEXT: ld a7, 0(a7)4739; RV64ZVE32F-NEXT: .LBB50_10: # %else84740; RV64ZVE32F-NEXT: andi t0, a5, 164741; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma4742; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 44743; RV64ZVE32F-NEXT: beqz t0, .LBB50_134744; RV64ZVE32F-NEXT: # %bb.11: # %cond.load104745; RV64ZVE32F-NEXT: vmv.x.s t0, v84746; RV64ZVE32F-NEXT: zext.b t0, t04747; RV64ZVE32F-NEXT: slli t0, t0, 34748; RV64ZVE32F-NEXT: add t0, a1, t04749; RV64ZVE32F-NEXT: ld t0, 0(t0)4750; RV64ZVE32F-NEXT: andi t1, a5, 324751; RV64ZVE32F-NEXT: bnez t1, .LBB50_144752; RV64ZVE32F-NEXT: .LBB50_12:4753; RV64ZVE32F-NEXT: ld t1, 40(a2)4754; RV64ZVE32F-NEXT: j .LBB50_154755; RV64ZVE32F-NEXT: .LBB50_13:4756; RV64ZVE32F-NEXT: ld t0, 32(a2)4757; RV64ZVE32F-NEXT: andi t1, a5, 324758; RV64ZVE32F-NEXT: beqz t1, .LBB50_124759; RV64ZVE32F-NEXT: .LBB50_14: # %cond.load134760; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma4761; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 14762; RV64ZVE32F-NEXT: vmv.x.s t1, v94763; RV64ZVE32F-NEXT: zext.b t1, t14764; RV64ZVE32F-NEXT: slli t1, t1, 34765; RV64ZVE32F-NEXT: add t1, a1, t14766; RV64ZVE32F-NEXT: ld t1, 0(t1)4767; RV64ZVE32F-NEXT: .LBB50_15: # %else144768; RV64ZVE32F-NEXT: andi t2, a5, 644769; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma4770; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 24771; RV64ZVE32F-NEXT: beqz t2, .LBB50_184772; RV64ZVE32F-NEXT: # %bb.16: # %cond.load164773; RV64ZVE32F-NEXT: vmv.x.s t2, v84774; RV64ZVE32F-NEXT: zext.b t2, t24775; RV64ZVE32F-NEXT: slli t2, t2, 34776; RV64ZVE32F-NEXT: add t2, a1, t24777; RV64ZVE32F-NEXT: ld t2, 0(t2)4778; RV64ZVE32F-NEXT: andi a5, a5, -1284779; RV64ZVE32F-NEXT: bnez a5, .LBB50_194780; RV64ZVE32F-NEXT: .LBB50_17:4781; RV64ZVE32F-NEXT: ld a1, 56(a2)4782; RV64ZVE32F-NEXT: j .LBB50_204783; RV64ZVE32F-NEXT: .LBB50_18:4784; RV64ZVE32F-NEXT: ld t2, 48(a2)4785; RV64ZVE32F-NEXT: andi a5, a5, -1284786; RV64ZVE32F-NEXT: beqz a5, .LBB50_174787; RV64ZVE32F-NEXT: .LBB50_19: # %cond.load194788; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 14789; RV64ZVE32F-NEXT: vmv.x.s a2, v84790; RV64ZVE32F-NEXT: zext.b a2, a24791; RV64ZVE32F-NEXT: slli a2, a2, 34792; RV64ZVE32F-NEXT: add a1, a1, a24793; RV64ZVE32F-NEXT: ld a1, 0(a1)4794; RV64ZVE32F-NEXT: .LBB50_20: # %else204795; RV64ZVE32F-NEXT: sd a3, 0(a0)4796; RV64ZVE32F-NEXT: sd a4, 8(a0)4797; RV64ZVE32F-NEXT: sd a6, 16(a0)4798; RV64ZVE32F-NEXT: sd a7, 24(a0)4799; RV64ZVE32F-NEXT: sd t0, 32(a0)4800; RV64ZVE32F-NEXT: sd t1, 40(a0)4801; RV64ZVE32F-NEXT: sd t2, 48(a0)4802; RV64ZVE32F-NEXT: sd a1, 56(a0)4803; RV64ZVE32F-NEXT: ret4804 %eidxs = zext <8 x i8> %idxs to <8 x i64>4805 %ptrs = getelementptr inbounds i64, ptr %base, <8 x i64> %eidxs4806 %v = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> %ptrs, i32 8, <8 x i1> %m, <8 x i64> %passthru)4807 ret <8 x i64> %v4808}4809 4810define <8 x i64> @mgather_baseidx_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <8 x i1> %m, <8 x i64> %passthru) {4811; RV32V-LABEL: mgather_baseidx_v8i16_v8i64:4812; RV32V: # %bb.0:4813; RV32V-NEXT: li a1, 84814; RV32V-NEXT: vsetivli zero, 8, e16, m1, ta, ma4815; RV32V-NEXT: vwmulsu.vx v10, v8, a14816; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, mu4817; RV32V-NEXT: vluxei32.v v12, (a0), v10, v0.t4818; RV32V-NEXT: vmv.v.v v8, v124819; RV32V-NEXT: ret4820;4821; RV64V-LABEL: mgather_baseidx_v8i16_v8i64:4822; RV64V: # %bb.0:4823; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, mu4824; RV64V-NEXT: vsext.vf4 v16, v84825; RV64V-NEXT: vsll.vi v8, v16, 34826; RV64V-NEXT: vluxei64.v v12, (a0), v8, v0.t4827; RV64V-NEXT: vmv.v.v v8, v124828; RV64V-NEXT: ret4829;4830; RV32ZVE32F-LABEL: mgather_baseidx_v8i16_v8i64:4831; RV32ZVE32F: # %bb.0:4832; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma4833; RV32ZVE32F-NEXT: vmv.v.x v10, a14834; RV32ZVE32F-NEXT: li a1, 84835; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma4836; RV32ZVE32F-NEXT: vmv.x.s t0, v04837; RV32ZVE32F-NEXT: andi a3, t0, 14838; RV32ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma4839; RV32ZVE32F-NEXT: vwmaccus.vx v10, a1, v84840; RV32ZVE32F-NEXT: beqz a3, .LBB51_74841; RV32ZVE32F-NEXT: # %bb.1: # %cond.load4842; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma4843; RV32ZVE32F-NEXT: vmv.x.s a3, v104844; RV32ZVE32F-NEXT: lw a1, 0(a3)4845; RV32ZVE32F-NEXT: lw a3, 4(a3)4846; RV32ZVE32F-NEXT: andi a4, t0, 24847; RV32ZVE32F-NEXT: bnez a4, .LBB51_84848; RV32ZVE32F-NEXT: .LBB51_2:4849; RV32ZVE32F-NEXT: lw a4, 8(a2)4850; RV32ZVE32F-NEXT: lw a5, 12(a2)4851; RV32ZVE32F-NEXT: andi a6, t0, 44852; RV32ZVE32F-NEXT: bnez a6, .LBB51_94853; RV32ZVE32F-NEXT: .LBB51_3:4854; RV32ZVE32F-NEXT: lw a6, 16(a2)4855; RV32ZVE32F-NEXT: lw a7, 20(a2)4856; RV32ZVE32F-NEXT: andi t1, t0, 84857; RV32ZVE32F-NEXT: bnez t1, .LBB51_104858; RV32ZVE32F-NEXT: .LBB51_4:4859; RV32ZVE32F-NEXT: lw t1, 24(a2)4860; RV32ZVE32F-NEXT: lw t2, 28(a2)4861; RV32ZVE32F-NEXT: andi t3, t0, 164862; RV32ZVE32F-NEXT: bnez t3, .LBB51_114863; RV32ZVE32F-NEXT: .LBB51_5:4864; RV32ZVE32F-NEXT: lw t3, 32(a2)4865; RV32ZVE32F-NEXT: lw t4, 36(a2)4866; RV32ZVE32F-NEXT: andi t5, t0, 324867; RV32ZVE32F-NEXT: bnez t5, .LBB51_124868; RV32ZVE32F-NEXT: .LBB51_6:4869; RV32ZVE32F-NEXT: lw t5, 40(a2)4870; RV32ZVE32F-NEXT: lw t6, 44(a2)4871; RV32ZVE32F-NEXT: j .LBB51_134872; RV32ZVE32F-NEXT: .LBB51_7:4873; RV32ZVE32F-NEXT: lw a1, 0(a2)4874; RV32ZVE32F-NEXT: lw a3, 4(a2)4875; RV32ZVE32F-NEXT: andi a4, t0, 24876; RV32ZVE32F-NEXT: beqz a4, .LBB51_24877; RV32ZVE32F-NEXT: .LBB51_8: # %cond.load14878; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma4879; RV32ZVE32F-NEXT: vslidedown.vi v8, v10, 14880; RV32ZVE32F-NEXT: vmv.x.s a5, v84881; RV32ZVE32F-NEXT: lw a4, 0(a5)4882; RV32ZVE32F-NEXT: lw a5, 4(a5)4883; RV32ZVE32F-NEXT: andi a6, t0, 44884; RV32ZVE32F-NEXT: beqz a6, .LBB51_34885; RV32ZVE32F-NEXT: .LBB51_9: # %cond.load44886; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma4887; RV32ZVE32F-NEXT: vslidedown.vi v8, v10, 24888; RV32ZVE32F-NEXT: vmv.x.s a7, v84889; RV32ZVE32F-NEXT: lw a6, 0(a7)4890; RV32ZVE32F-NEXT: lw a7, 4(a7)4891; RV32ZVE32F-NEXT: andi t1, t0, 84892; RV32ZVE32F-NEXT: beqz t1, .LBB51_44893; RV32ZVE32F-NEXT: .LBB51_10: # %cond.load74894; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma4895; RV32ZVE32F-NEXT: vslidedown.vi v8, v10, 34896; RV32ZVE32F-NEXT: vmv.x.s t2, v84897; RV32ZVE32F-NEXT: lw t1, 0(t2)4898; RV32ZVE32F-NEXT: lw t2, 4(t2)4899; RV32ZVE32F-NEXT: andi t3, t0, 164900; RV32ZVE32F-NEXT: beqz t3, .LBB51_54901; RV32ZVE32F-NEXT: .LBB51_11: # %cond.load104902; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma4903; RV32ZVE32F-NEXT: vslidedown.vi v8, v10, 44904; RV32ZVE32F-NEXT: vmv.x.s t4, v84905; RV32ZVE32F-NEXT: lw t3, 0(t4)4906; RV32ZVE32F-NEXT: lw t4, 4(t4)4907; RV32ZVE32F-NEXT: andi t5, t0, 324908; RV32ZVE32F-NEXT: beqz t5, .LBB51_64909; RV32ZVE32F-NEXT: .LBB51_12: # %cond.load134910; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma4911; RV32ZVE32F-NEXT: vslidedown.vi v8, v10, 54912; RV32ZVE32F-NEXT: vmv.x.s t6, v84913; RV32ZVE32F-NEXT: lw t5, 0(t6)4914; RV32ZVE32F-NEXT: lw t6, 4(t6)4915; RV32ZVE32F-NEXT: .LBB51_13: # %else144916; RV32ZVE32F-NEXT: addi sp, sp, -164917; RV32ZVE32F-NEXT: .cfi_def_cfa_offset 164918; RV32ZVE32F-NEXT: sw s0, 12(sp) # 4-byte Folded Spill4919; RV32ZVE32F-NEXT: sw s1, 8(sp) # 4-byte Folded Spill4920; RV32ZVE32F-NEXT: .cfi_offset s0, -44921; RV32ZVE32F-NEXT: .cfi_offset s1, -84922; RV32ZVE32F-NEXT: andi s0, t0, 644923; RV32ZVE32F-NEXT: beqz s0, .LBB51_164924; RV32ZVE32F-NEXT: # %bb.14: # %cond.load164925; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma4926; RV32ZVE32F-NEXT: vslidedown.vi v8, v10, 64927; RV32ZVE32F-NEXT: vmv.x.s s1, v84928; RV32ZVE32F-NEXT: lw s0, 0(s1)4929; RV32ZVE32F-NEXT: lw s1, 4(s1)4930; RV32ZVE32F-NEXT: andi t0, t0, -1284931; RV32ZVE32F-NEXT: bnez t0, .LBB51_174932; RV32ZVE32F-NEXT: .LBB51_15:4933; RV32ZVE32F-NEXT: lw t0, 56(a2)4934; RV32ZVE32F-NEXT: lw a2, 60(a2)4935; RV32ZVE32F-NEXT: j .LBB51_184936; RV32ZVE32F-NEXT: .LBB51_16:4937; RV32ZVE32F-NEXT: lw s0, 48(a2)4938; RV32ZVE32F-NEXT: lw s1, 52(a2)4939; RV32ZVE32F-NEXT: andi t0, t0, -1284940; RV32ZVE32F-NEXT: beqz t0, .LBB51_154941; RV32ZVE32F-NEXT: .LBB51_17: # %cond.load194942; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma4943; RV32ZVE32F-NEXT: vslidedown.vi v8, v10, 74944; RV32ZVE32F-NEXT: vmv.x.s a2, v84945; RV32ZVE32F-NEXT: lw t0, 0(a2)4946; RV32ZVE32F-NEXT: lw a2, 4(a2)4947; RV32ZVE32F-NEXT: .LBB51_18: # %else204948; RV32ZVE32F-NEXT: sw a1, 0(a0)4949; RV32ZVE32F-NEXT: sw a3, 4(a0)4950; RV32ZVE32F-NEXT: sw a4, 8(a0)4951; RV32ZVE32F-NEXT: sw a5, 12(a0)4952; RV32ZVE32F-NEXT: sw a6, 16(a0)4953; RV32ZVE32F-NEXT: sw a7, 20(a0)4954; RV32ZVE32F-NEXT: sw t1, 24(a0)4955; RV32ZVE32F-NEXT: sw t2, 28(a0)4956; RV32ZVE32F-NEXT: sw t3, 32(a0)4957; RV32ZVE32F-NEXT: sw t4, 36(a0)4958; RV32ZVE32F-NEXT: sw t5, 40(a0)4959; RV32ZVE32F-NEXT: sw t6, 44(a0)4960; RV32ZVE32F-NEXT: sw s0, 48(a0)4961; RV32ZVE32F-NEXT: sw s1, 52(a0)4962; RV32ZVE32F-NEXT: sw t0, 56(a0)4963; RV32ZVE32F-NEXT: sw a2, 60(a0)4964; RV32ZVE32F-NEXT: lw s0, 12(sp) # 4-byte Folded Reload4965; RV32ZVE32F-NEXT: lw s1, 8(sp) # 4-byte Folded Reload4966; RV32ZVE32F-NEXT: .cfi_restore s04967; RV32ZVE32F-NEXT: .cfi_restore s14968; RV32ZVE32F-NEXT: addi sp, sp, 164969; RV32ZVE32F-NEXT: .cfi_def_cfa_offset 04970; RV32ZVE32F-NEXT: ret4971;4972; RV64ZVE32F-LABEL: mgather_baseidx_v8i16_v8i64:4973; RV64ZVE32F: # %bb.0:4974; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma4975; RV64ZVE32F-NEXT: vmv.x.s a5, v04976; RV64ZVE32F-NEXT: andi a3, a5, 14977; RV64ZVE32F-NEXT: beqz a3, .LBB51_34978; RV64ZVE32F-NEXT: # %bb.1: # %cond.load4979; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma4980; RV64ZVE32F-NEXT: vmv.x.s a3, v84981; RV64ZVE32F-NEXT: slli a3, a3, 34982; RV64ZVE32F-NEXT: add a3, a1, a34983; RV64ZVE32F-NEXT: ld a3, 0(a3)4984; RV64ZVE32F-NEXT: andi a4, a5, 24985; RV64ZVE32F-NEXT: bnez a4, .LBB51_44986; RV64ZVE32F-NEXT: .LBB51_2:4987; RV64ZVE32F-NEXT: ld a4, 8(a2)4988; RV64ZVE32F-NEXT: j .LBB51_54989; RV64ZVE32F-NEXT: .LBB51_3:4990; RV64ZVE32F-NEXT: ld a3, 0(a2)4991; RV64ZVE32F-NEXT: andi a4, a5, 24992; RV64ZVE32F-NEXT: beqz a4, .LBB51_24993; RV64ZVE32F-NEXT: .LBB51_4: # %cond.load14994; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma4995; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 14996; RV64ZVE32F-NEXT: vmv.x.s a4, v94997; RV64ZVE32F-NEXT: slli a4, a4, 34998; RV64ZVE32F-NEXT: add a4, a1, a44999; RV64ZVE32F-NEXT: ld a4, 0(a4)5000; RV64ZVE32F-NEXT: .LBB51_5: # %else25001; RV64ZVE32F-NEXT: andi a6, a5, 45002; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma5003; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 25004; RV64ZVE32F-NEXT: beqz a6, .LBB51_85005; RV64ZVE32F-NEXT: # %bb.6: # %cond.load45006; RV64ZVE32F-NEXT: vmv.x.s a6, v95007; RV64ZVE32F-NEXT: slli a6, a6, 35008; RV64ZVE32F-NEXT: add a6, a1, a65009; RV64ZVE32F-NEXT: ld a6, 0(a6)5010; RV64ZVE32F-NEXT: andi a7, a5, 85011; RV64ZVE32F-NEXT: bnez a7, .LBB51_95012; RV64ZVE32F-NEXT: .LBB51_7:5013; RV64ZVE32F-NEXT: ld a7, 24(a2)5014; RV64ZVE32F-NEXT: j .LBB51_105015; RV64ZVE32F-NEXT: .LBB51_8:5016; RV64ZVE32F-NEXT: ld a6, 16(a2)5017; RV64ZVE32F-NEXT: andi a7, a5, 85018; RV64ZVE32F-NEXT: beqz a7, .LBB51_75019; RV64ZVE32F-NEXT: .LBB51_9: # %cond.load75020; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 15021; RV64ZVE32F-NEXT: vmv.x.s a7, v95022; RV64ZVE32F-NEXT: slli a7, a7, 35023; RV64ZVE32F-NEXT: add a7, a1, a75024; RV64ZVE32F-NEXT: ld a7, 0(a7)5025; RV64ZVE32F-NEXT: .LBB51_10: # %else85026; RV64ZVE32F-NEXT: andi t0, a5, 165027; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma5028; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 45029; RV64ZVE32F-NEXT: beqz t0, .LBB51_135030; RV64ZVE32F-NEXT: # %bb.11: # %cond.load105031; RV64ZVE32F-NEXT: vmv.x.s t0, v85032; RV64ZVE32F-NEXT: slli t0, t0, 35033; RV64ZVE32F-NEXT: add t0, a1, t05034; RV64ZVE32F-NEXT: ld t0, 0(t0)5035; RV64ZVE32F-NEXT: andi t1, a5, 325036; RV64ZVE32F-NEXT: bnez t1, .LBB51_145037; RV64ZVE32F-NEXT: .LBB51_12:5038; RV64ZVE32F-NEXT: ld t1, 40(a2)5039; RV64ZVE32F-NEXT: j .LBB51_155040; RV64ZVE32F-NEXT: .LBB51_13:5041; RV64ZVE32F-NEXT: ld t0, 32(a2)5042; RV64ZVE32F-NEXT: andi t1, a5, 325043; RV64ZVE32F-NEXT: beqz t1, .LBB51_125044; RV64ZVE32F-NEXT: .LBB51_14: # %cond.load135045; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma5046; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 15047; RV64ZVE32F-NEXT: vmv.x.s t1, v95048; RV64ZVE32F-NEXT: slli t1, t1, 35049; RV64ZVE32F-NEXT: add t1, a1, t15050; RV64ZVE32F-NEXT: ld t1, 0(t1)5051; RV64ZVE32F-NEXT: .LBB51_15: # %else145052; RV64ZVE32F-NEXT: andi t2, a5, 645053; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma5054; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 25055; RV64ZVE32F-NEXT: beqz t2, .LBB51_185056; RV64ZVE32F-NEXT: # %bb.16: # %cond.load165057; RV64ZVE32F-NEXT: vmv.x.s t2, v85058; RV64ZVE32F-NEXT: slli t2, t2, 35059; RV64ZVE32F-NEXT: add t2, a1, t25060; RV64ZVE32F-NEXT: ld t2, 0(t2)5061; RV64ZVE32F-NEXT: andi a5, a5, -1285062; RV64ZVE32F-NEXT: bnez a5, .LBB51_195063; RV64ZVE32F-NEXT: .LBB51_17:5064; RV64ZVE32F-NEXT: ld a1, 56(a2)5065; RV64ZVE32F-NEXT: j .LBB51_205066; RV64ZVE32F-NEXT: .LBB51_18:5067; RV64ZVE32F-NEXT: ld t2, 48(a2)5068; RV64ZVE32F-NEXT: andi a5, a5, -1285069; RV64ZVE32F-NEXT: beqz a5, .LBB51_175070; RV64ZVE32F-NEXT: .LBB51_19: # %cond.load195071; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 15072; RV64ZVE32F-NEXT: vmv.x.s a2, v85073; RV64ZVE32F-NEXT: slli a2, a2, 35074; RV64ZVE32F-NEXT: add a1, a1, a25075; RV64ZVE32F-NEXT: ld a1, 0(a1)5076; RV64ZVE32F-NEXT: .LBB51_20: # %else205077; RV64ZVE32F-NEXT: sd a3, 0(a0)5078; RV64ZVE32F-NEXT: sd a4, 8(a0)5079; RV64ZVE32F-NEXT: sd a6, 16(a0)5080; RV64ZVE32F-NEXT: sd a7, 24(a0)5081; RV64ZVE32F-NEXT: sd t0, 32(a0)5082; RV64ZVE32F-NEXT: sd t1, 40(a0)5083; RV64ZVE32F-NEXT: sd t2, 48(a0)5084; RV64ZVE32F-NEXT: sd a1, 56(a0)5085; RV64ZVE32F-NEXT: ret5086 %ptrs = getelementptr inbounds i64, ptr %base, <8 x i16> %idxs5087 %v = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> %ptrs, i32 8, <8 x i1> %m, <8 x i64> %passthru)5088 ret <8 x i64> %v5089}5090 5091define <8 x i64> @mgather_baseidx_sext_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <8 x i1> %m, <8 x i64> %passthru) {5092; RV32V-LABEL: mgather_baseidx_sext_v8i16_v8i64:5093; RV32V: # %bb.0:5094; RV32V-NEXT: li a1, 85095; RV32V-NEXT: vsetivli zero, 8, e16, m1, ta, ma5096; RV32V-NEXT: vwmulsu.vx v10, v8, a15097; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, mu5098; RV32V-NEXT: vluxei32.v v12, (a0), v10, v0.t5099; RV32V-NEXT: vmv.v.v v8, v125100; RV32V-NEXT: ret5101;5102; RV64V-LABEL: mgather_baseidx_sext_v8i16_v8i64:5103; RV64V: # %bb.0:5104; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, mu5105; RV64V-NEXT: vsext.vf4 v16, v85106; RV64V-NEXT: vsll.vi v8, v16, 35107; RV64V-NEXT: vluxei64.v v12, (a0), v8, v0.t5108; RV64V-NEXT: vmv.v.v v8, v125109; RV64V-NEXT: ret5110;5111; RV32ZVE32F-LABEL: mgather_baseidx_sext_v8i16_v8i64:5112; RV32ZVE32F: # %bb.0:5113; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma5114; RV32ZVE32F-NEXT: vmv.v.x v10, a15115; RV32ZVE32F-NEXT: li a1, 85116; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma5117; RV32ZVE32F-NEXT: vmv.x.s t0, v05118; RV32ZVE32F-NEXT: andi a3, t0, 15119; RV32ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma5120; RV32ZVE32F-NEXT: vwmaccus.vx v10, a1, v85121; RV32ZVE32F-NEXT: beqz a3, .LBB52_75122; RV32ZVE32F-NEXT: # %bb.1: # %cond.load5123; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma5124; RV32ZVE32F-NEXT: vmv.x.s a3, v105125; RV32ZVE32F-NEXT: lw a1, 0(a3)5126; RV32ZVE32F-NEXT: lw a3, 4(a3)5127; RV32ZVE32F-NEXT: andi a4, t0, 25128; RV32ZVE32F-NEXT: bnez a4, .LBB52_85129; RV32ZVE32F-NEXT: .LBB52_2:5130; RV32ZVE32F-NEXT: lw a4, 8(a2)5131; RV32ZVE32F-NEXT: lw a5, 12(a2)5132; RV32ZVE32F-NEXT: andi a6, t0, 45133; RV32ZVE32F-NEXT: bnez a6, .LBB52_95134; RV32ZVE32F-NEXT: .LBB52_3:5135; RV32ZVE32F-NEXT: lw a6, 16(a2)5136; RV32ZVE32F-NEXT: lw a7, 20(a2)5137; RV32ZVE32F-NEXT: andi t1, t0, 85138; RV32ZVE32F-NEXT: bnez t1, .LBB52_105139; RV32ZVE32F-NEXT: .LBB52_4:5140; RV32ZVE32F-NEXT: lw t1, 24(a2)5141; RV32ZVE32F-NEXT: lw t2, 28(a2)5142; RV32ZVE32F-NEXT: andi t3, t0, 165143; RV32ZVE32F-NEXT: bnez t3, .LBB52_115144; RV32ZVE32F-NEXT: .LBB52_5:5145; RV32ZVE32F-NEXT: lw t3, 32(a2)5146; RV32ZVE32F-NEXT: lw t4, 36(a2)5147; RV32ZVE32F-NEXT: andi t5, t0, 325148; RV32ZVE32F-NEXT: bnez t5, .LBB52_125149; RV32ZVE32F-NEXT: .LBB52_6:5150; RV32ZVE32F-NEXT: lw t5, 40(a2)5151; RV32ZVE32F-NEXT: lw t6, 44(a2)5152; RV32ZVE32F-NEXT: j .LBB52_135153; RV32ZVE32F-NEXT: .LBB52_7:5154; RV32ZVE32F-NEXT: lw a1, 0(a2)5155; RV32ZVE32F-NEXT: lw a3, 4(a2)5156; RV32ZVE32F-NEXT: andi a4, t0, 25157; RV32ZVE32F-NEXT: beqz a4, .LBB52_25158; RV32ZVE32F-NEXT: .LBB52_8: # %cond.load15159; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma5160; RV32ZVE32F-NEXT: vslidedown.vi v8, v10, 15161; RV32ZVE32F-NEXT: vmv.x.s a5, v85162; RV32ZVE32F-NEXT: lw a4, 0(a5)5163; RV32ZVE32F-NEXT: lw a5, 4(a5)5164; RV32ZVE32F-NEXT: andi a6, t0, 45165; RV32ZVE32F-NEXT: beqz a6, .LBB52_35166; RV32ZVE32F-NEXT: .LBB52_9: # %cond.load45167; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma5168; RV32ZVE32F-NEXT: vslidedown.vi v8, v10, 25169; RV32ZVE32F-NEXT: vmv.x.s a7, v85170; RV32ZVE32F-NEXT: lw a6, 0(a7)5171; RV32ZVE32F-NEXT: lw a7, 4(a7)5172; RV32ZVE32F-NEXT: andi t1, t0, 85173; RV32ZVE32F-NEXT: beqz t1, .LBB52_45174; RV32ZVE32F-NEXT: .LBB52_10: # %cond.load75175; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma5176; RV32ZVE32F-NEXT: vslidedown.vi v8, v10, 35177; RV32ZVE32F-NEXT: vmv.x.s t2, v85178; RV32ZVE32F-NEXT: lw t1, 0(t2)5179; RV32ZVE32F-NEXT: lw t2, 4(t2)5180; RV32ZVE32F-NEXT: andi t3, t0, 165181; RV32ZVE32F-NEXT: beqz t3, .LBB52_55182; RV32ZVE32F-NEXT: .LBB52_11: # %cond.load105183; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma5184; RV32ZVE32F-NEXT: vslidedown.vi v8, v10, 45185; RV32ZVE32F-NEXT: vmv.x.s t4, v85186; RV32ZVE32F-NEXT: lw t3, 0(t4)5187; RV32ZVE32F-NEXT: lw t4, 4(t4)5188; RV32ZVE32F-NEXT: andi t5, t0, 325189; RV32ZVE32F-NEXT: beqz t5, .LBB52_65190; RV32ZVE32F-NEXT: .LBB52_12: # %cond.load135191; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma5192; RV32ZVE32F-NEXT: vslidedown.vi v8, v10, 55193; RV32ZVE32F-NEXT: vmv.x.s t6, v85194; RV32ZVE32F-NEXT: lw t5, 0(t6)5195; RV32ZVE32F-NEXT: lw t6, 4(t6)5196; RV32ZVE32F-NEXT: .LBB52_13: # %else145197; RV32ZVE32F-NEXT: addi sp, sp, -165198; RV32ZVE32F-NEXT: .cfi_def_cfa_offset 165199; RV32ZVE32F-NEXT: sw s0, 12(sp) # 4-byte Folded Spill5200; RV32ZVE32F-NEXT: sw s1, 8(sp) # 4-byte Folded Spill5201; RV32ZVE32F-NEXT: .cfi_offset s0, -45202; RV32ZVE32F-NEXT: .cfi_offset s1, -85203; RV32ZVE32F-NEXT: andi s0, t0, 645204; RV32ZVE32F-NEXT: beqz s0, .LBB52_165205; RV32ZVE32F-NEXT: # %bb.14: # %cond.load165206; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma5207; RV32ZVE32F-NEXT: vslidedown.vi v8, v10, 65208; RV32ZVE32F-NEXT: vmv.x.s s1, v85209; RV32ZVE32F-NEXT: lw s0, 0(s1)5210; RV32ZVE32F-NEXT: lw s1, 4(s1)5211; RV32ZVE32F-NEXT: andi t0, t0, -1285212; RV32ZVE32F-NEXT: bnez t0, .LBB52_175213; RV32ZVE32F-NEXT: .LBB52_15:5214; RV32ZVE32F-NEXT: lw t0, 56(a2)5215; RV32ZVE32F-NEXT: lw a2, 60(a2)5216; RV32ZVE32F-NEXT: j .LBB52_185217; RV32ZVE32F-NEXT: .LBB52_16:5218; RV32ZVE32F-NEXT: lw s0, 48(a2)5219; RV32ZVE32F-NEXT: lw s1, 52(a2)5220; RV32ZVE32F-NEXT: andi t0, t0, -1285221; RV32ZVE32F-NEXT: beqz t0, .LBB52_155222; RV32ZVE32F-NEXT: .LBB52_17: # %cond.load195223; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma5224; RV32ZVE32F-NEXT: vslidedown.vi v8, v10, 75225; RV32ZVE32F-NEXT: vmv.x.s a2, v85226; RV32ZVE32F-NEXT: lw t0, 0(a2)5227; RV32ZVE32F-NEXT: lw a2, 4(a2)5228; RV32ZVE32F-NEXT: .LBB52_18: # %else205229; RV32ZVE32F-NEXT: sw a1, 0(a0)5230; RV32ZVE32F-NEXT: sw a3, 4(a0)5231; RV32ZVE32F-NEXT: sw a4, 8(a0)5232; RV32ZVE32F-NEXT: sw a5, 12(a0)5233; RV32ZVE32F-NEXT: sw a6, 16(a0)5234; RV32ZVE32F-NEXT: sw a7, 20(a0)5235; RV32ZVE32F-NEXT: sw t1, 24(a0)5236; RV32ZVE32F-NEXT: sw t2, 28(a0)5237; RV32ZVE32F-NEXT: sw t3, 32(a0)5238; RV32ZVE32F-NEXT: sw t4, 36(a0)5239; RV32ZVE32F-NEXT: sw t5, 40(a0)5240; RV32ZVE32F-NEXT: sw t6, 44(a0)5241; RV32ZVE32F-NEXT: sw s0, 48(a0)5242; RV32ZVE32F-NEXT: sw s1, 52(a0)5243; RV32ZVE32F-NEXT: sw t0, 56(a0)5244; RV32ZVE32F-NEXT: sw a2, 60(a0)5245; RV32ZVE32F-NEXT: lw s0, 12(sp) # 4-byte Folded Reload5246; RV32ZVE32F-NEXT: lw s1, 8(sp) # 4-byte Folded Reload5247; RV32ZVE32F-NEXT: .cfi_restore s05248; RV32ZVE32F-NEXT: .cfi_restore s15249; RV32ZVE32F-NEXT: addi sp, sp, 165250; RV32ZVE32F-NEXT: .cfi_def_cfa_offset 05251; RV32ZVE32F-NEXT: ret5252;5253; RV64ZVE32F-LABEL: mgather_baseidx_sext_v8i16_v8i64:5254; RV64ZVE32F: # %bb.0:5255; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma5256; RV64ZVE32F-NEXT: vmv.x.s a5, v05257; RV64ZVE32F-NEXT: andi a3, a5, 15258; RV64ZVE32F-NEXT: beqz a3, .LBB52_35259; RV64ZVE32F-NEXT: # %bb.1: # %cond.load5260; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma5261; RV64ZVE32F-NEXT: vmv.x.s a3, v85262; RV64ZVE32F-NEXT: slli a3, a3, 35263; RV64ZVE32F-NEXT: add a3, a1, a35264; RV64ZVE32F-NEXT: ld a3, 0(a3)5265; RV64ZVE32F-NEXT: andi a4, a5, 25266; RV64ZVE32F-NEXT: bnez a4, .LBB52_45267; RV64ZVE32F-NEXT: .LBB52_2:5268; RV64ZVE32F-NEXT: ld a4, 8(a2)5269; RV64ZVE32F-NEXT: j .LBB52_55270; RV64ZVE32F-NEXT: .LBB52_3:5271; RV64ZVE32F-NEXT: ld a3, 0(a2)5272; RV64ZVE32F-NEXT: andi a4, a5, 25273; RV64ZVE32F-NEXT: beqz a4, .LBB52_25274; RV64ZVE32F-NEXT: .LBB52_4: # %cond.load15275; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma5276; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 15277; RV64ZVE32F-NEXT: vmv.x.s a4, v95278; RV64ZVE32F-NEXT: slli a4, a4, 35279; RV64ZVE32F-NEXT: add a4, a1, a45280; RV64ZVE32F-NEXT: ld a4, 0(a4)5281; RV64ZVE32F-NEXT: .LBB52_5: # %else25282; RV64ZVE32F-NEXT: andi a6, a5, 45283; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma5284; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 25285; RV64ZVE32F-NEXT: beqz a6, .LBB52_85286; RV64ZVE32F-NEXT: # %bb.6: # %cond.load45287; RV64ZVE32F-NEXT: vmv.x.s a6, v95288; RV64ZVE32F-NEXT: slli a6, a6, 35289; RV64ZVE32F-NEXT: add a6, a1, a65290; RV64ZVE32F-NEXT: ld a6, 0(a6)5291; RV64ZVE32F-NEXT: andi a7, a5, 85292; RV64ZVE32F-NEXT: bnez a7, .LBB52_95293; RV64ZVE32F-NEXT: .LBB52_7:5294; RV64ZVE32F-NEXT: ld a7, 24(a2)5295; RV64ZVE32F-NEXT: j .LBB52_105296; RV64ZVE32F-NEXT: .LBB52_8:5297; RV64ZVE32F-NEXT: ld a6, 16(a2)5298; RV64ZVE32F-NEXT: andi a7, a5, 85299; RV64ZVE32F-NEXT: beqz a7, .LBB52_75300; RV64ZVE32F-NEXT: .LBB52_9: # %cond.load75301; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 15302; RV64ZVE32F-NEXT: vmv.x.s a7, v95303; RV64ZVE32F-NEXT: slli a7, a7, 35304; RV64ZVE32F-NEXT: add a7, a1, a75305; RV64ZVE32F-NEXT: ld a7, 0(a7)5306; RV64ZVE32F-NEXT: .LBB52_10: # %else85307; RV64ZVE32F-NEXT: andi t0, a5, 165308; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma5309; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 45310; RV64ZVE32F-NEXT: beqz t0, .LBB52_135311; RV64ZVE32F-NEXT: # %bb.11: # %cond.load105312; RV64ZVE32F-NEXT: vmv.x.s t0, v85313; RV64ZVE32F-NEXT: slli t0, t0, 35314; RV64ZVE32F-NEXT: add t0, a1, t05315; RV64ZVE32F-NEXT: ld t0, 0(t0)5316; RV64ZVE32F-NEXT: andi t1, a5, 325317; RV64ZVE32F-NEXT: bnez t1, .LBB52_145318; RV64ZVE32F-NEXT: .LBB52_12:5319; RV64ZVE32F-NEXT: ld t1, 40(a2)5320; RV64ZVE32F-NEXT: j .LBB52_155321; RV64ZVE32F-NEXT: .LBB52_13:5322; RV64ZVE32F-NEXT: ld t0, 32(a2)5323; RV64ZVE32F-NEXT: andi t1, a5, 325324; RV64ZVE32F-NEXT: beqz t1, .LBB52_125325; RV64ZVE32F-NEXT: .LBB52_14: # %cond.load135326; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma5327; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 15328; RV64ZVE32F-NEXT: vmv.x.s t1, v95329; RV64ZVE32F-NEXT: slli t1, t1, 35330; RV64ZVE32F-NEXT: add t1, a1, t15331; RV64ZVE32F-NEXT: ld t1, 0(t1)5332; RV64ZVE32F-NEXT: .LBB52_15: # %else145333; RV64ZVE32F-NEXT: andi t2, a5, 645334; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma5335; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 25336; RV64ZVE32F-NEXT: beqz t2, .LBB52_185337; RV64ZVE32F-NEXT: # %bb.16: # %cond.load165338; RV64ZVE32F-NEXT: vmv.x.s t2, v85339; RV64ZVE32F-NEXT: slli t2, t2, 35340; RV64ZVE32F-NEXT: add t2, a1, t25341; RV64ZVE32F-NEXT: ld t2, 0(t2)5342; RV64ZVE32F-NEXT: andi a5, a5, -1285343; RV64ZVE32F-NEXT: bnez a5, .LBB52_195344; RV64ZVE32F-NEXT: .LBB52_17:5345; RV64ZVE32F-NEXT: ld a1, 56(a2)5346; RV64ZVE32F-NEXT: j .LBB52_205347; RV64ZVE32F-NEXT: .LBB52_18:5348; RV64ZVE32F-NEXT: ld t2, 48(a2)5349; RV64ZVE32F-NEXT: andi a5, a5, -1285350; RV64ZVE32F-NEXT: beqz a5, .LBB52_175351; RV64ZVE32F-NEXT: .LBB52_19: # %cond.load195352; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 15353; RV64ZVE32F-NEXT: vmv.x.s a2, v85354; RV64ZVE32F-NEXT: slli a2, a2, 35355; RV64ZVE32F-NEXT: add a1, a1, a25356; RV64ZVE32F-NEXT: ld a1, 0(a1)5357; RV64ZVE32F-NEXT: .LBB52_20: # %else205358; RV64ZVE32F-NEXT: sd a3, 0(a0)5359; RV64ZVE32F-NEXT: sd a4, 8(a0)5360; RV64ZVE32F-NEXT: sd a6, 16(a0)5361; RV64ZVE32F-NEXT: sd a7, 24(a0)5362; RV64ZVE32F-NEXT: sd t0, 32(a0)5363; RV64ZVE32F-NEXT: sd t1, 40(a0)5364; RV64ZVE32F-NEXT: sd t2, 48(a0)5365; RV64ZVE32F-NEXT: sd a1, 56(a0)5366; RV64ZVE32F-NEXT: ret5367 %eidxs = sext <8 x i16> %idxs to <8 x i64>5368 %ptrs = getelementptr inbounds i64, ptr %base, <8 x i64> %eidxs5369 %v = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> %ptrs, i32 8, <8 x i1> %m, <8 x i64> %passthru)5370 ret <8 x i64> %v5371}5372 5373define <8 x i64> @mgather_baseidx_zext_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <8 x i1> %m, <8 x i64> %passthru) {5374; RV32V-LABEL: mgather_baseidx_zext_v8i16_v8i64:5375; RV32V: # %bb.0:5376; RV32V-NEXT: li a1, 85377; RV32V-NEXT: vsetivli zero, 8, e16, m1, ta, ma5378; RV32V-NEXT: vwmulu.vx v10, v8, a15379; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, mu5380; RV32V-NEXT: vluxei32.v v12, (a0), v10, v0.t5381; RV32V-NEXT: vmv.v.v v8, v125382; RV32V-NEXT: ret5383;5384; RV64V-LABEL: mgather_baseidx_zext_v8i16_v8i64:5385; RV64V: # %bb.0:5386; RV64V-NEXT: li a1, 85387; RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, ma5388; RV64V-NEXT: vwmulu.vx v10, v8, a15389; RV64V-NEXT: vsetvli zero, zero, e64, m4, ta, mu5390; RV64V-NEXT: vluxei32.v v12, (a0), v10, v0.t5391; RV64V-NEXT: vmv.v.v v8, v125392; RV64V-NEXT: ret5393;5394; RV32ZVE32F-LABEL: mgather_baseidx_zext_v8i16_v8i64:5395; RV32ZVE32F: # %bb.0:5396; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma5397; RV32ZVE32F-NEXT: vmv.v.x v10, a15398; RV32ZVE32F-NEXT: li a1, 85399; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma5400; RV32ZVE32F-NEXT: vmv.x.s t0, v05401; RV32ZVE32F-NEXT: andi a3, t0, 15402; RV32ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma5403; RV32ZVE32F-NEXT: vwmaccu.vx v10, a1, v85404; RV32ZVE32F-NEXT: beqz a3, .LBB53_75405; RV32ZVE32F-NEXT: # %bb.1: # %cond.load5406; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma5407; RV32ZVE32F-NEXT: vmv.x.s a3, v105408; RV32ZVE32F-NEXT: lw a1, 0(a3)5409; RV32ZVE32F-NEXT: lw a3, 4(a3)5410; RV32ZVE32F-NEXT: andi a4, t0, 25411; RV32ZVE32F-NEXT: bnez a4, .LBB53_85412; RV32ZVE32F-NEXT: .LBB53_2:5413; RV32ZVE32F-NEXT: lw a4, 8(a2)5414; RV32ZVE32F-NEXT: lw a5, 12(a2)5415; RV32ZVE32F-NEXT: andi a6, t0, 45416; RV32ZVE32F-NEXT: bnez a6, .LBB53_95417; RV32ZVE32F-NEXT: .LBB53_3:5418; RV32ZVE32F-NEXT: lw a6, 16(a2)5419; RV32ZVE32F-NEXT: lw a7, 20(a2)5420; RV32ZVE32F-NEXT: andi t1, t0, 85421; RV32ZVE32F-NEXT: bnez t1, .LBB53_105422; RV32ZVE32F-NEXT: .LBB53_4:5423; RV32ZVE32F-NEXT: lw t1, 24(a2)5424; RV32ZVE32F-NEXT: lw t2, 28(a2)5425; RV32ZVE32F-NEXT: andi t3, t0, 165426; RV32ZVE32F-NEXT: bnez t3, .LBB53_115427; RV32ZVE32F-NEXT: .LBB53_5:5428; RV32ZVE32F-NEXT: lw t3, 32(a2)5429; RV32ZVE32F-NEXT: lw t4, 36(a2)5430; RV32ZVE32F-NEXT: andi t5, t0, 325431; RV32ZVE32F-NEXT: bnez t5, .LBB53_125432; RV32ZVE32F-NEXT: .LBB53_6:5433; RV32ZVE32F-NEXT: lw t5, 40(a2)5434; RV32ZVE32F-NEXT: lw t6, 44(a2)5435; RV32ZVE32F-NEXT: j .LBB53_135436; RV32ZVE32F-NEXT: .LBB53_7:5437; RV32ZVE32F-NEXT: lw a1, 0(a2)5438; RV32ZVE32F-NEXT: lw a3, 4(a2)5439; RV32ZVE32F-NEXT: andi a4, t0, 25440; RV32ZVE32F-NEXT: beqz a4, .LBB53_25441; RV32ZVE32F-NEXT: .LBB53_8: # %cond.load15442; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma5443; RV32ZVE32F-NEXT: vslidedown.vi v8, v10, 15444; RV32ZVE32F-NEXT: vmv.x.s a5, v85445; RV32ZVE32F-NEXT: lw a4, 0(a5)5446; RV32ZVE32F-NEXT: lw a5, 4(a5)5447; RV32ZVE32F-NEXT: andi a6, t0, 45448; RV32ZVE32F-NEXT: beqz a6, .LBB53_35449; RV32ZVE32F-NEXT: .LBB53_9: # %cond.load45450; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma5451; RV32ZVE32F-NEXT: vslidedown.vi v8, v10, 25452; RV32ZVE32F-NEXT: vmv.x.s a7, v85453; RV32ZVE32F-NEXT: lw a6, 0(a7)5454; RV32ZVE32F-NEXT: lw a7, 4(a7)5455; RV32ZVE32F-NEXT: andi t1, t0, 85456; RV32ZVE32F-NEXT: beqz t1, .LBB53_45457; RV32ZVE32F-NEXT: .LBB53_10: # %cond.load75458; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma5459; RV32ZVE32F-NEXT: vslidedown.vi v8, v10, 35460; RV32ZVE32F-NEXT: vmv.x.s t2, v85461; RV32ZVE32F-NEXT: lw t1, 0(t2)5462; RV32ZVE32F-NEXT: lw t2, 4(t2)5463; RV32ZVE32F-NEXT: andi t3, t0, 165464; RV32ZVE32F-NEXT: beqz t3, .LBB53_55465; RV32ZVE32F-NEXT: .LBB53_11: # %cond.load105466; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma5467; RV32ZVE32F-NEXT: vslidedown.vi v8, v10, 45468; RV32ZVE32F-NEXT: vmv.x.s t4, v85469; RV32ZVE32F-NEXT: lw t3, 0(t4)5470; RV32ZVE32F-NEXT: lw t4, 4(t4)5471; RV32ZVE32F-NEXT: andi t5, t0, 325472; RV32ZVE32F-NEXT: beqz t5, .LBB53_65473; RV32ZVE32F-NEXT: .LBB53_12: # %cond.load135474; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma5475; RV32ZVE32F-NEXT: vslidedown.vi v8, v10, 55476; RV32ZVE32F-NEXT: vmv.x.s t6, v85477; RV32ZVE32F-NEXT: lw t5, 0(t6)5478; RV32ZVE32F-NEXT: lw t6, 4(t6)5479; RV32ZVE32F-NEXT: .LBB53_13: # %else145480; RV32ZVE32F-NEXT: addi sp, sp, -165481; RV32ZVE32F-NEXT: .cfi_def_cfa_offset 165482; RV32ZVE32F-NEXT: sw s0, 12(sp) # 4-byte Folded Spill5483; RV32ZVE32F-NEXT: sw s1, 8(sp) # 4-byte Folded Spill5484; RV32ZVE32F-NEXT: .cfi_offset s0, -45485; RV32ZVE32F-NEXT: .cfi_offset s1, -85486; RV32ZVE32F-NEXT: andi s0, t0, 645487; RV32ZVE32F-NEXT: beqz s0, .LBB53_165488; RV32ZVE32F-NEXT: # %bb.14: # %cond.load165489; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma5490; RV32ZVE32F-NEXT: vslidedown.vi v8, v10, 65491; RV32ZVE32F-NEXT: vmv.x.s s1, v85492; RV32ZVE32F-NEXT: lw s0, 0(s1)5493; RV32ZVE32F-NEXT: lw s1, 4(s1)5494; RV32ZVE32F-NEXT: andi t0, t0, -1285495; RV32ZVE32F-NEXT: bnez t0, .LBB53_175496; RV32ZVE32F-NEXT: .LBB53_15:5497; RV32ZVE32F-NEXT: lw t0, 56(a2)5498; RV32ZVE32F-NEXT: lw a2, 60(a2)5499; RV32ZVE32F-NEXT: j .LBB53_185500; RV32ZVE32F-NEXT: .LBB53_16:5501; RV32ZVE32F-NEXT: lw s0, 48(a2)5502; RV32ZVE32F-NEXT: lw s1, 52(a2)5503; RV32ZVE32F-NEXT: andi t0, t0, -1285504; RV32ZVE32F-NEXT: beqz t0, .LBB53_155505; RV32ZVE32F-NEXT: .LBB53_17: # %cond.load195506; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma5507; RV32ZVE32F-NEXT: vslidedown.vi v8, v10, 75508; RV32ZVE32F-NEXT: vmv.x.s a2, v85509; RV32ZVE32F-NEXT: lw t0, 0(a2)5510; RV32ZVE32F-NEXT: lw a2, 4(a2)5511; RV32ZVE32F-NEXT: .LBB53_18: # %else205512; RV32ZVE32F-NEXT: sw a1, 0(a0)5513; RV32ZVE32F-NEXT: sw a3, 4(a0)5514; RV32ZVE32F-NEXT: sw a4, 8(a0)5515; RV32ZVE32F-NEXT: sw a5, 12(a0)5516; RV32ZVE32F-NEXT: sw a6, 16(a0)5517; RV32ZVE32F-NEXT: sw a7, 20(a0)5518; RV32ZVE32F-NEXT: sw t1, 24(a0)5519; RV32ZVE32F-NEXT: sw t2, 28(a0)5520; RV32ZVE32F-NEXT: sw t3, 32(a0)5521; RV32ZVE32F-NEXT: sw t4, 36(a0)5522; RV32ZVE32F-NEXT: sw t5, 40(a0)5523; RV32ZVE32F-NEXT: sw t6, 44(a0)5524; RV32ZVE32F-NEXT: sw s0, 48(a0)5525; RV32ZVE32F-NEXT: sw s1, 52(a0)5526; RV32ZVE32F-NEXT: sw t0, 56(a0)5527; RV32ZVE32F-NEXT: sw a2, 60(a0)5528; RV32ZVE32F-NEXT: lw s0, 12(sp) # 4-byte Folded Reload5529; RV32ZVE32F-NEXT: lw s1, 8(sp) # 4-byte Folded Reload5530; RV32ZVE32F-NEXT: .cfi_restore s05531; RV32ZVE32F-NEXT: .cfi_restore s15532; RV32ZVE32F-NEXT: addi sp, sp, 165533; RV32ZVE32F-NEXT: .cfi_def_cfa_offset 05534; RV32ZVE32F-NEXT: ret5535;5536; RV64ZVE32F-LABEL: mgather_baseidx_zext_v8i16_v8i64:5537; RV64ZVE32F: # %bb.0:5538; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma5539; RV64ZVE32F-NEXT: vmv.x.s a5, v05540; RV64ZVE32F-NEXT: andi a3, a5, 15541; RV64ZVE32F-NEXT: beqz a3, .LBB53_35542; RV64ZVE32F-NEXT: # %bb.1: # %cond.load5543; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma5544; RV64ZVE32F-NEXT: vmv.x.s a3, v85545; RV64ZVE32F-NEXT: slli a3, a3, 485546; RV64ZVE32F-NEXT: srli a3, a3, 455547; RV64ZVE32F-NEXT: add a3, a1, a35548; RV64ZVE32F-NEXT: ld a3, 0(a3)5549; RV64ZVE32F-NEXT: andi a4, a5, 25550; RV64ZVE32F-NEXT: bnez a4, .LBB53_45551; RV64ZVE32F-NEXT: .LBB53_2:5552; RV64ZVE32F-NEXT: ld a4, 8(a2)5553; RV64ZVE32F-NEXT: j .LBB53_55554; RV64ZVE32F-NEXT: .LBB53_3:5555; RV64ZVE32F-NEXT: ld a3, 0(a2)5556; RV64ZVE32F-NEXT: andi a4, a5, 25557; RV64ZVE32F-NEXT: beqz a4, .LBB53_25558; RV64ZVE32F-NEXT: .LBB53_4: # %cond.load15559; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma5560; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 15561; RV64ZVE32F-NEXT: vmv.x.s a4, v95562; RV64ZVE32F-NEXT: slli a4, a4, 485563; RV64ZVE32F-NEXT: srli a4, a4, 455564; RV64ZVE32F-NEXT: add a4, a1, a45565; RV64ZVE32F-NEXT: ld a4, 0(a4)5566; RV64ZVE32F-NEXT: .LBB53_5: # %else25567; RV64ZVE32F-NEXT: andi a6, a5, 45568; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma5569; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 25570; RV64ZVE32F-NEXT: beqz a6, .LBB53_85571; RV64ZVE32F-NEXT: # %bb.6: # %cond.load45572; RV64ZVE32F-NEXT: vmv.x.s a6, v95573; RV64ZVE32F-NEXT: slli a6, a6, 485574; RV64ZVE32F-NEXT: srli a6, a6, 455575; RV64ZVE32F-NEXT: add a6, a1, a65576; RV64ZVE32F-NEXT: ld a6, 0(a6)5577; RV64ZVE32F-NEXT: andi a7, a5, 85578; RV64ZVE32F-NEXT: bnez a7, .LBB53_95579; RV64ZVE32F-NEXT: .LBB53_7:5580; RV64ZVE32F-NEXT: ld a7, 24(a2)5581; RV64ZVE32F-NEXT: j .LBB53_105582; RV64ZVE32F-NEXT: .LBB53_8:5583; RV64ZVE32F-NEXT: ld a6, 16(a2)5584; RV64ZVE32F-NEXT: andi a7, a5, 85585; RV64ZVE32F-NEXT: beqz a7, .LBB53_75586; RV64ZVE32F-NEXT: .LBB53_9: # %cond.load75587; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 15588; RV64ZVE32F-NEXT: vmv.x.s a7, v95589; RV64ZVE32F-NEXT: slli a7, a7, 485590; RV64ZVE32F-NEXT: srli a7, a7, 455591; RV64ZVE32F-NEXT: add a7, a1, a75592; RV64ZVE32F-NEXT: ld a7, 0(a7)5593; RV64ZVE32F-NEXT: .LBB53_10: # %else85594; RV64ZVE32F-NEXT: andi t0, a5, 165595; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma5596; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 45597; RV64ZVE32F-NEXT: beqz t0, .LBB53_135598; RV64ZVE32F-NEXT: # %bb.11: # %cond.load105599; RV64ZVE32F-NEXT: vmv.x.s t0, v85600; RV64ZVE32F-NEXT: slli t0, t0, 485601; RV64ZVE32F-NEXT: srli t0, t0, 455602; RV64ZVE32F-NEXT: add t0, a1, t05603; RV64ZVE32F-NEXT: ld t0, 0(t0)5604; RV64ZVE32F-NEXT: andi t1, a5, 325605; RV64ZVE32F-NEXT: bnez t1, .LBB53_145606; RV64ZVE32F-NEXT: .LBB53_12:5607; RV64ZVE32F-NEXT: ld t1, 40(a2)5608; RV64ZVE32F-NEXT: j .LBB53_155609; RV64ZVE32F-NEXT: .LBB53_13:5610; RV64ZVE32F-NEXT: ld t0, 32(a2)5611; RV64ZVE32F-NEXT: andi t1, a5, 325612; RV64ZVE32F-NEXT: beqz t1, .LBB53_125613; RV64ZVE32F-NEXT: .LBB53_14: # %cond.load135614; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma5615; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 15616; RV64ZVE32F-NEXT: vmv.x.s t1, v95617; RV64ZVE32F-NEXT: slli t1, t1, 485618; RV64ZVE32F-NEXT: srli t1, t1, 455619; RV64ZVE32F-NEXT: add t1, a1, t15620; RV64ZVE32F-NEXT: ld t1, 0(t1)5621; RV64ZVE32F-NEXT: .LBB53_15: # %else145622; RV64ZVE32F-NEXT: andi t2, a5, 645623; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma5624; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 25625; RV64ZVE32F-NEXT: beqz t2, .LBB53_185626; RV64ZVE32F-NEXT: # %bb.16: # %cond.load165627; RV64ZVE32F-NEXT: vmv.x.s t2, v85628; RV64ZVE32F-NEXT: slli t2, t2, 485629; RV64ZVE32F-NEXT: srli t2, t2, 455630; RV64ZVE32F-NEXT: add t2, a1, t25631; RV64ZVE32F-NEXT: ld t2, 0(t2)5632; RV64ZVE32F-NEXT: andi a5, a5, -1285633; RV64ZVE32F-NEXT: bnez a5, .LBB53_195634; RV64ZVE32F-NEXT: .LBB53_17:5635; RV64ZVE32F-NEXT: ld a1, 56(a2)5636; RV64ZVE32F-NEXT: j .LBB53_205637; RV64ZVE32F-NEXT: .LBB53_18:5638; RV64ZVE32F-NEXT: ld t2, 48(a2)5639; RV64ZVE32F-NEXT: andi a5, a5, -1285640; RV64ZVE32F-NEXT: beqz a5, .LBB53_175641; RV64ZVE32F-NEXT: .LBB53_19: # %cond.load195642; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 15643; RV64ZVE32F-NEXT: vmv.x.s a2, v85644; RV64ZVE32F-NEXT: slli a2, a2, 485645; RV64ZVE32F-NEXT: srli a2, a2, 455646; RV64ZVE32F-NEXT: add a1, a1, a25647; RV64ZVE32F-NEXT: ld a1, 0(a1)5648; RV64ZVE32F-NEXT: .LBB53_20: # %else205649; RV64ZVE32F-NEXT: sd a3, 0(a0)5650; RV64ZVE32F-NEXT: sd a4, 8(a0)5651; RV64ZVE32F-NEXT: sd a6, 16(a0)5652; RV64ZVE32F-NEXT: sd a7, 24(a0)5653; RV64ZVE32F-NEXT: sd t0, 32(a0)5654; RV64ZVE32F-NEXT: sd t1, 40(a0)5655; RV64ZVE32F-NEXT: sd t2, 48(a0)5656; RV64ZVE32F-NEXT: sd a1, 56(a0)5657; RV64ZVE32F-NEXT: ret5658 %eidxs = zext <8 x i16> %idxs to <8 x i64>5659 %ptrs = getelementptr inbounds i64, ptr %base, <8 x i64> %eidxs5660 %v = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> %ptrs, i32 8, <8 x i1> %m, <8 x i64> %passthru)5661 ret <8 x i64> %v5662}5663 5664define <8 x i64> @mgather_baseidx_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <8 x i1> %m, <8 x i64> %passthru) {5665; RV32V-LABEL: mgather_baseidx_v8i32_v8i64:5666; RV32V: # %bb.0:5667; RV32V-NEXT: vsetivli zero, 8, e32, m2, ta, ma5668; RV32V-NEXT: vsll.vi v8, v8, 35669; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, mu5670; RV32V-NEXT: vluxei32.v v12, (a0), v8, v0.t5671; RV32V-NEXT: vmv.v.v v8, v125672; RV32V-NEXT: ret5673;5674; RV64V-LABEL: mgather_baseidx_v8i32_v8i64:5675; RV64V: # %bb.0:5676; RV64V-NEXT: li a1, 85677; RV64V-NEXT: vsetivli zero, 8, e32, m2, ta, ma5678; RV64V-NEXT: vwmulsu.vx v16, v8, a15679; RV64V-NEXT: vsetvli zero, zero, e64, m4, ta, mu5680; RV64V-NEXT: vluxei64.v v12, (a0), v16, v0.t5681; RV64V-NEXT: vmv.v.v v8, v125682; RV64V-NEXT: ret5683;5684; RV32ZVE32F-LABEL: mgather_baseidx_v8i32_v8i64:5685; RV32ZVE32F: # %bb.0:5686; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma5687; RV32ZVE32F-NEXT: vsll.vi v8, v8, 35688; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma5689; RV32ZVE32F-NEXT: vmv.x.s t0, v05690; RV32ZVE32F-NEXT: andi a3, t0, 15691; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma5692; RV32ZVE32F-NEXT: vadd.vx v8, v8, a15693; RV32ZVE32F-NEXT: beqz a3, .LBB54_75694; RV32ZVE32F-NEXT: # %bb.1: # %cond.load5695; RV32ZVE32F-NEXT: vmv.x.s a3, v85696; RV32ZVE32F-NEXT: lw a1, 0(a3)5697; RV32ZVE32F-NEXT: lw a3, 4(a3)5698; RV32ZVE32F-NEXT: andi a4, t0, 25699; RV32ZVE32F-NEXT: bnez a4, .LBB54_85700; RV32ZVE32F-NEXT: .LBB54_2:5701; RV32ZVE32F-NEXT: lw a4, 8(a2)5702; RV32ZVE32F-NEXT: lw a5, 12(a2)5703; RV32ZVE32F-NEXT: andi a6, t0, 45704; RV32ZVE32F-NEXT: bnez a6, .LBB54_95705; RV32ZVE32F-NEXT: .LBB54_3:5706; RV32ZVE32F-NEXT: lw a6, 16(a2)5707; RV32ZVE32F-NEXT: lw a7, 20(a2)5708; RV32ZVE32F-NEXT: andi t1, t0, 85709; RV32ZVE32F-NEXT: bnez t1, .LBB54_105710; RV32ZVE32F-NEXT: .LBB54_4:5711; RV32ZVE32F-NEXT: lw t1, 24(a2)5712; RV32ZVE32F-NEXT: lw t2, 28(a2)5713; RV32ZVE32F-NEXT: andi t3, t0, 165714; RV32ZVE32F-NEXT: bnez t3, .LBB54_115715; RV32ZVE32F-NEXT: .LBB54_5:5716; RV32ZVE32F-NEXT: lw t3, 32(a2)5717; RV32ZVE32F-NEXT: lw t4, 36(a2)5718; RV32ZVE32F-NEXT: andi t5, t0, 325719; RV32ZVE32F-NEXT: bnez t5, .LBB54_125720; RV32ZVE32F-NEXT: .LBB54_6:5721; RV32ZVE32F-NEXT: lw t5, 40(a2)5722; RV32ZVE32F-NEXT: lw t6, 44(a2)5723; RV32ZVE32F-NEXT: j .LBB54_135724; RV32ZVE32F-NEXT: .LBB54_7:5725; RV32ZVE32F-NEXT: lw a1, 0(a2)5726; RV32ZVE32F-NEXT: lw a3, 4(a2)5727; RV32ZVE32F-NEXT: andi a4, t0, 25728; RV32ZVE32F-NEXT: beqz a4, .LBB54_25729; RV32ZVE32F-NEXT: .LBB54_8: # %cond.load15730; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma5731; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 15732; RV32ZVE32F-NEXT: vmv.x.s a5, v105733; RV32ZVE32F-NEXT: lw a4, 0(a5)5734; RV32ZVE32F-NEXT: lw a5, 4(a5)5735; RV32ZVE32F-NEXT: andi a6, t0, 45736; RV32ZVE32F-NEXT: beqz a6, .LBB54_35737; RV32ZVE32F-NEXT: .LBB54_9: # %cond.load45738; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma5739; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 25740; RV32ZVE32F-NEXT: vmv.x.s a7, v105741; RV32ZVE32F-NEXT: lw a6, 0(a7)5742; RV32ZVE32F-NEXT: lw a7, 4(a7)5743; RV32ZVE32F-NEXT: andi t1, t0, 85744; RV32ZVE32F-NEXT: beqz t1, .LBB54_45745; RV32ZVE32F-NEXT: .LBB54_10: # %cond.load75746; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma5747; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 35748; RV32ZVE32F-NEXT: vmv.x.s t2, v105749; RV32ZVE32F-NEXT: lw t1, 0(t2)5750; RV32ZVE32F-NEXT: lw t2, 4(t2)5751; RV32ZVE32F-NEXT: andi t3, t0, 165752; RV32ZVE32F-NEXT: beqz t3, .LBB54_55753; RV32ZVE32F-NEXT: .LBB54_11: # %cond.load105754; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma5755; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 45756; RV32ZVE32F-NEXT: vmv.x.s t4, v105757; RV32ZVE32F-NEXT: lw t3, 0(t4)5758; RV32ZVE32F-NEXT: lw t4, 4(t4)5759; RV32ZVE32F-NEXT: andi t5, t0, 325760; RV32ZVE32F-NEXT: beqz t5, .LBB54_65761; RV32ZVE32F-NEXT: .LBB54_12: # %cond.load135762; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma5763; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 55764; RV32ZVE32F-NEXT: vmv.x.s t6, v105765; RV32ZVE32F-NEXT: lw t5, 0(t6)5766; RV32ZVE32F-NEXT: lw t6, 4(t6)5767; RV32ZVE32F-NEXT: .LBB54_13: # %else145768; RV32ZVE32F-NEXT: addi sp, sp, -165769; RV32ZVE32F-NEXT: .cfi_def_cfa_offset 165770; RV32ZVE32F-NEXT: sw s0, 12(sp) # 4-byte Folded Spill5771; RV32ZVE32F-NEXT: sw s1, 8(sp) # 4-byte Folded Spill5772; RV32ZVE32F-NEXT: .cfi_offset s0, -45773; RV32ZVE32F-NEXT: .cfi_offset s1, -85774; RV32ZVE32F-NEXT: andi s0, t0, 645775; RV32ZVE32F-NEXT: beqz s0, .LBB54_165776; RV32ZVE32F-NEXT: # %bb.14: # %cond.load165777; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma5778; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 65779; RV32ZVE32F-NEXT: vmv.x.s s1, v105780; RV32ZVE32F-NEXT: lw s0, 0(s1)5781; RV32ZVE32F-NEXT: lw s1, 4(s1)5782; RV32ZVE32F-NEXT: andi t0, t0, -1285783; RV32ZVE32F-NEXT: bnez t0, .LBB54_175784; RV32ZVE32F-NEXT: .LBB54_15:5785; RV32ZVE32F-NEXT: lw t0, 56(a2)5786; RV32ZVE32F-NEXT: lw a2, 60(a2)5787; RV32ZVE32F-NEXT: j .LBB54_185788; RV32ZVE32F-NEXT: .LBB54_16:5789; RV32ZVE32F-NEXT: lw s0, 48(a2)5790; RV32ZVE32F-NEXT: lw s1, 52(a2)5791; RV32ZVE32F-NEXT: andi t0, t0, -1285792; RV32ZVE32F-NEXT: beqz t0, .LBB54_155793; RV32ZVE32F-NEXT: .LBB54_17: # %cond.load195794; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma5795; RV32ZVE32F-NEXT: vslidedown.vi v8, v8, 75796; RV32ZVE32F-NEXT: vmv.x.s a2, v85797; RV32ZVE32F-NEXT: lw t0, 0(a2)5798; RV32ZVE32F-NEXT: lw a2, 4(a2)5799; RV32ZVE32F-NEXT: .LBB54_18: # %else205800; RV32ZVE32F-NEXT: sw a1, 0(a0)5801; RV32ZVE32F-NEXT: sw a3, 4(a0)5802; RV32ZVE32F-NEXT: sw a4, 8(a0)5803; RV32ZVE32F-NEXT: sw a5, 12(a0)5804; RV32ZVE32F-NEXT: sw a6, 16(a0)5805; RV32ZVE32F-NEXT: sw a7, 20(a0)5806; RV32ZVE32F-NEXT: sw t1, 24(a0)5807; RV32ZVE32F-NEXT: sw t2, 28(a0)5808; RV32ZVE32F-NEXT: sw t3, 32(a0)5809; RV32ZVE32F-NEXT: sw t4, 36(a0)5810; RV32ZVE32F-NEXT: sw t5, 40(a0)5811; RV32ZVE32F-NEXT: sw t6, 44(a0)5812; RV32ZVE32F-NEXT: sw s0, 48(a0)5813; RV32ZVE32F-NEXT: sw s1, 52(a0)5814; RV32ZVE32F-NEXT: sw t0, 56(a0)5815; RV32ZVE32F-NEXT: sw a2, 60(a0)5816; RV32ZVE32F-NEXT: lw s0, 12(sp) # 4-byte Folded Reload5817; RV32ZVE32F-NEXT: lw s1, 8(sp) # 4-byte Folded Reload5818; RV32ZVE32F-NEXT: .cfi_restore s05819; RV32ZVE32F-NEXT: .cfi_restore s15820; RV32ZVE32F-NEXT: addi sp, sp, 165821; RV32ZVE32F-NEXT: .cfi_def_cfa_offset 05822; RV32ZVE32F-NEXT: ret5823;5824; RV64ZVE32F-LABEL: mgather_baseidx_v8i32_v8i64:5825; RV64ZVE32F: # %bb.0:5826; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma5827; RV64ZVE32F-NEXT: vmv.x.s a5, v05828; RV64ZVE32F-NEXT: andi a3, a5, 15829; RV64ZVE32F-NEXT: beqz a3, .LBB54_35830; RV64ZVE32F-NEXT: # %bb.1: # %cond.load5831; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma5832; RV64ZVE32F-NEXT: vmv.x.s a3, v85833; RV64ZVE32F-NEXT: slli a3, a3, 35834; RV64ZVE32F-NEXT: add a3, a1, a35835; RV64ZVE32F-NEXT: ld a3, 0(a3)5836; RV64ZVE32F-NEXT: andi a4, a5, 25837; RV64ZVE32F-NEXT: bnez a4, .LBB54_45838; RV64ZVE32F-NEXT: .LBB54_2:5839; RV64ZVE32F-NEXT: ld a4, 8(a2)5840; RV64ZVE32F-NEXT: j .LBB54_55841; RV64ZVE32F-NEXT: .LBB54_3:5842; RV64ZVE32F-NEXT: ld a3, 0(a2)5843; RV64ZVE32F-NEXT: andi a4, a5, 25844; RV64ZVE32F-NEXT: beqz a4, .LBB54_25845; RV64ZVE32F-NEXT: .LBB54_4: # %cond.load15846; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma5847; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 15848; RV64ZVE32F-NEXT: vmv.x.s a4, v105849; RV64ZVE32F-NEXT: slli a4, a4, 35850; RV64ZVE32F-NEXT: add a4, a1, a45851; RV64ZVE32F-NEXT: ld a4, 0(a4)5852; RV64ZVE32F-NEXT: .LBB54_5: # %else25853; RV64ZVE32F-NEXT: andi a6, a5, 45854; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma5855; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 25856; RV64ZVE32F-NEXT: beqz a6, .LBB54_75857; RV64ZVE32F-NEXT: # %bb.6: # %cond.load45858; RV64ZVE32F-NEXT: vmv.x.s a6, v105859; RV64ZVE32F-NEXT: slli a6, a6, 35860; RV64ZVE32F-NEXT: add a6, a1, a65861; RV64ZVE32F-NEXT: ld a6, 0(a6)5862; RV64ZVE32F-NEXT: j .LBB54_85863; RV64ZVE32F-NEXT: .LBB54_7:5864; RV64ZVE32F-NEXT: ld a6, 16(a2)5865; RV64ZVE32F-NEXT: .LBB54_8: # %else55866; RV64ZVE32F-NEXT: andi a7, a5, 85867; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, ta, ma5868; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 45869; RV64ZVE32F-NEXT: beqz a7, .LBB54_125870; RV64ZVE32F-NEXT: # %bb.9: # %cond.load75871; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma5872; RV64ZVE32F-NEXT: vslidedown.vi v9, v10, 15873; RV64ZVE32F-NEXT: vmv.x.s a7, v95874; RV64ZVE32F-NEXT: slli a7, a7, 35875; RV64ZVE32F-NEXT: add a7, a1, a75876; RV64ZVE32F-NEXT: ld a7, 0(a7)5877; RV64ZVE32F-NEXT: andi t0, a5, 165878; RV64ZVE32F-NEXT: bnez t0, .LBB54_135879; RV64ZVE32F-NEXT: .LBB54_10:5880; RV64ZVE32F-NEXT: ld t0, 32(a2)5881; RV64ZVE32F-NEXT: andi t1, a5, 325882; RV64ZVE32F-NEXT: bnez t1, .LBB54_145883; RV64ZVE32F-NEXT: .LBB54_11:5884; RV64ZVE32F-NEXT: ld t1, 40(a2)5885; RV64ZVE32F-NEXT: j .LBB54_155886; RV64ZVE32F-NEXT: .LBB54_12:5887; RV64ZVE32F-NEXT: ld a7, 24(a2)5888; RV64ZVE32F-NEXT: andi t0, a5, 165889; RV64ZVE32F-NEXT: beqz t0, .LBB54_105890; RV64ZVE32F-NEXT: .LBB54_13: # %cond.load105891; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma5892; RV64ZVE32F-NEXT: vmv.x.s t0, v85893; RV64ZVE32F-NEXT: slli t0, t0, 35894; RV64ZVE32F-NEXT: add t0, a1, t05895; RV64ZVE32F-NEXT: ld t0, 0(t0)5896; RV64ZVE32F-NEXT: andi t1, a5, 325897; RV64ZVE32F-NEXT: beqz t1, .LBB54_115898; RV64ZVE32F-NEXT: .LBB54_14: # %cond.load135899; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma5900; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 15901; RV64ZVE32F-NEXT: vmv.x.s t1, v95902; RV64ZVE32F-NEXT: slli t1, t1, 35903; RV64ZVE32F-NEXT: add t1, a1, t15904; RV64ZVE32F-NEXT: ld t1, 0(t1)5905; RV64ZVE32F-NEXT: .LBB54_15: # %else145906; RV64ZVE32F-NEXT: andi t2, a5, 645907; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma5908; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 25909; RV64ZVE32F-NEXT: beqz t2, .LBB54_185910; RV64ZVE32F-NEXT: # %bb.16: # %cond.load165911; RV64ZVE32F-NEXT: vmv.x.s t2, v85912; RV64ZVE32F-NEXT: slli t2, t2, 35913; RV64ZVE32F-NEXT: add t2, a1, t25914; RV64ZVE32F-NEXT: ld t2, 0(t2)5915; RV64ZVE32F-NEXT: andi a5, a5, -1285916; RV64ZVE32F-NEXT: bnez a5, .LBB54_195917; RV64ZVE32F-NEXT: .LBB54_17:5918; RV64ZVE32F-NEXT: ld a1, 56(a2)5919; RV64ZVE32F-NEXT: j .LBB54_205920; RV64ZVE32F-NEXT: .LBB54_18:5921; RV64ZVE32F-NEXT: ld t2, 48(a2)5922; RV64ZVE32F-NEXT: andi a5, a5, -1285923; RV64ZVE32F-NEXT: beqz a5, .LBB54_175924; RV64ZVE32F-NEXT: .LBB54_19: # %cond.load195925; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 15926; RV64ZVE32F-NEXT: vmv.x.s a2, v85927; RV64ZVE32F-NEXT: slli a2, a2, 35928; RV64ZVE32F-NEXT: add a1, a1, a25929; RV64ZVE32F-NEXT: ld a1, 0(a1)5930; RV64ZVE32F-NEXT: .LBB54_20: # %else205931; RV64ZVE32F-NEXT: sd a3, 0(a0)5932; RV64ZVE32F-NEXT: sd a4, 8(a0)5933; RV64ZVE32F-NEXT: sd a6, 16(a0)5934; RV64ZVE32F-NEXT: sd a7, 24(a0)5935; RV64ZVE32F-NEXT: sd t0, 32(a0)5936; RV64ZVE32F-NEXT: sd t1, 40(a0)5937; RV64ZVE32F-NEXT: sd t2, 48(a0)5938; RV64ZVE32F-NEXT: sd a1, 56(a0)5939; RV64ZVE32F-NEXT: ret5940 %ptrs = getelementptr inbounds i64, ptr %base, <8 x i32> %idxs5941 %v = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> %ptrs, i32 8, <8 x i1> %m, <8 x i64> %passthru)5942 ret <8 x i64> %v5943}5944 5945define <8 x i64> @mgather_baseidx_sext_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <8 x i1> %m, <8 x i64> %passthru) {5946; RV32V-LABEL: mgather_baseidx_sext_v8i32_v8i64:5947; RV32V: # %bb.0:5948; RV32V-NEXT: vsetivli zero, 8, e32, m2, ta, ma5949; RV32V-NEXT: vsll.vi v8, v8, 35950; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, mu5951; RV32V-NEXT: vluxei32.v v12, (a0), v8, v0.t5952; RV32V-NEXT: vmv.v.v v8, v125953; RV32V-NEXT: ret5954;5955; RV64V-LABEL: mgather_baseidx_sext_v8i32_v8i64:5956; RV64V: # %bb.0:5957; RV64V-NEXT: li a1, 85958; RV64V-NEXT: vsetivli zero, 8, e32, m2, ta, ma5959; RV64V-NEXT: vwmulsu.vx v16, v8, a15960; RV64V-NEXT: vsetvli zero, zero, e64, m4, ta, mu5961; RV64V-NEXT: vluxei64.v v12, (a0), v16, v0.t5962; RV64V-NEXT: vmv.v.v v8, v125963; RV64V-NEXT: ret5964;5965; RV32ZVE32F-LABEL: mgather_baseidx_sext_v8i32_v8i64:5966; RV32ZVE32F: # %bb.0:5967; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma5968; RV32ZVE32F-NEXT: vsll.vi v8, v8, 35969; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma5970; RV32ZVE32F-NEXT: vmv.x.s t0, v05971; RV32ZVE32F-NEXT: andi a3, t0, 15972; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma5973; RV32ZVE32F-NEXT: vadd.vx v8, v8, a15974; RV32ZVE32F-NEXT: beqz a3, .LBB55_75975; RV32ZVE32F-NEXT: # %bb.1: # %cond.load5976; RV32ZVE32F-NEXT: vmv.x.s a3, v85977; RV32ZVE32F-NEXT: lw a1, 0(a3)5978; RV32ZVE32F-NEXT: lw a3, 4(a3)5979; RV32ZVE32F-NEXT: andi a4, t0, 25980; RV32ZVE32F-NEXT: bnez a4, .LBB55_85981; RV32ZVE32F-NEXT: .LBB55_2:5982; RV32ZVE32F-NEXT: lw a4, 8(a2)5983; RV32ZVE32F-NEXT: lw a5, 12(a2)5984; RV32ZVE32F-NEXT: andi a6, t0, 45985; RV32ZVE32F-NEXT: bnez a6, .LBB55_95986; RV32ZVE32F-NEXT: .LBB55_3:5987; RV32ZVE32F-NEXT: lw a6, 16(a2)5988; RV32ZVE32F-NEXT: lw a7, 20(a2)5989; RV32ZVE32F-NEXT: andi t1, t0, 85990; RV32ZVE32F-NEXT: bnez t1, .LBB55_105991; RV32ZVE32F-NEXT: .LBB55_4:5992; RV32ZVE32F-NEXT: lw t1, 24(a2)5993; RV32ZVE32F-NEXT: lw t2, 28(a2)5994; RV32ZVE32F-NEXT: andi t3, t0, 165995; RV32ZVE32F-NEXT: bnez t3, .LBB55_115996; RV32ZVE32F-NEXT: .LBB55_5:5997; RV32ZVE32F-NEXT: lw t3, 32(a2)5998; RV32ZVE32F-NEXT: lw t4, 36(a2)5999; RV32ZVE32F-NEXT: andi t5, t0, 326000; RV32ZVE32F-NEXT: bnez t5, .LBB55_126001; RV32ZVE32F-NEXT: .LBB55_6:6002; RV32ZVE32F-NEXT: lw t5, 40(a2)6003; RV32ZVE32F-NEXT: lw t6, 44(a2)6004; RV32ZVE32F-NEXT: j .LBB55_136005; RV32ZVE32F-NEXT: .LBB55_7:6006; RV32ZVE32F-NEXT: lw a1, 0(a2)6007; RV32ZVE32F-NEXT: lw a3, 4(a2)6008; RV32ZVE32F-NEXT: andi a4, t0, 26009; RV32ZVE32F-NEXT: beqz a4, .LBB55_26010; RV32ZVE32F-NEXT: .LBB55_8: # %cond.load16011; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma6012; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 16013; RV32ZVE32F-NEXT: vmv.x.s a5, v106014; RV32ZVE32F-NEXT: lw a4, 0(a5)6015; RV32ZVE32F-NEXT: lw a5, 4(a5)6016; RV32ZVE32F-NEXT: andi a6, t0, 46017; RV32ZVE32F-NEXT: beqz a6, .LBB55_36018; RV32ZVE32F-NEXT: .LBB55_9: # %cond.load46019; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma6020; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 26021; RV32ZVE32F-NEXT: vmv.x.s a7, v106022; RV32ZVE32F-NEXT: lw a6, 0(a7)6023; RV32ZVE32F-NEXT: lw a7, 4(a7)6024; RV32ZVE32F-NEXT: andi t1, t0, 86025; RV32ZVE32F-NEXT: beqz t1, .LBB55_46026; RV32ZVE32F-NEXT: .LBB55_10: # %cond.load76027; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma6028; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 36029; RV32ZVE32F-NEXT: vmv.x.s t2, v106030; RV32ZVE32F-NEXT: lw t1, 0(t2)6031; RV32ZVE32F-NEXT: lw t2, 4(t2)6032; RV32ZVE32F-NEXT: andi t3, t0, 166033; RV32ZVE32F-NEXT: beqz t3, .LBB55_56034; RV32ZVE32F-NEXT: .LBB55_11: # %cond.load106035; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma6036; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 46037; RV32ZVE32F-NEXT: vmv.x.s t4, v106038; RV32ZVE32F-NEXT: lw t3, 0(t4)6039; RV32ZVE32F-NEXT: lw t4, 4(t4)6040; RV32ZVE32F-NEXT: andi t5, t0, 326041; RV32ZVE32F-NEXT: beqz t5, .LBB55_66042; RV32ZVE32F-NEXT: .LBB55_12: # %cond.load136043; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma6044; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 56045; RV32ZVE32F-NEXT: vmv.x.s t6, v106046; RV32ZVE32F-NEXT: lw t5, 0(t6)6047; RV32ZVE32F-NEXT: lw t6, 4(t6)6048; RV32ZVE32F-NEXT: .LBB55_13: # %else146049; RV32ZVE32F-NEXT: addi sp, sp, -166050; RV32ZVE32F-NEXT: .cfi_def_cfa_offset 166051; RV32ZVE32F-NEXT: sw s0, 12(sp) # 4-byte Folded Spill6052; RV32ZVE32F-NEXT: sw s1, 8(sp) # 4-byte Folded Spill6053; RV32ZVE32F-NEXT: .cfi_offset s0, -46054; RV32ZVE32F-NEXT: .cfi_offset s1, -86055; RV32ZVE32F-NEXT: andi s0, t0, 646056; RV32ZVE32F-NEXT: beqz s0, .LBB55_166057; RV32ZVE32F-NEXT: # %bb.14: # %cond.load166058; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma6059; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 66060; RV32ZVE32F-NEXT: vmv.x.s s1, v106061; RV32ZVE32F-NEXT: lw s0, 0(s1)6062; RV32ZVE32F-NEXT: lw s1, 4(s1)6063; RV32ZVE32F-NEXT: andi t0, t0, -1286064; RV32ZVE32F-NEXT: bnez t0, .LBB55_176065; RV32ZVE32F-NEXT: .LBB55_15:6066; RV32ZVE32F-NEXT: lw t0, 56(a2)6067; RV32ZVE32F-NEXT: lw a2, 60(a2)6068; RV32ZVE32F-NEXT: j .LBB55_186069; RV32ZVE32F-NEXT: .LBB55_16:6070; RV32ZVE32F-NEXT: lw s0, 48(a2)6071; RV32ZVE32F-NEXT: lw s1, 52(a2)6072; RV32ZVE32F-NEXT: andi t0, t0, -1286073; RV32ZVE32F-NEXT: beqz t0, .LBB55_156074; RV32ZVE32F-NEXT: .LBB55_17: # %cond.load196075; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma6076; RV32ZVE32F-NEXT: vslidedown.vi v8, v8, 76077; RV32ZVE32F-NEXT: vmv.x.s a2, v86078; RV32ZVE32F-NEXT: lw t0, 0(a2)6079; RV32ZVE32F-NEXT: lw a2, 4(a2)6080; RV32ZVE32F-NEXT: .LBB55_18: # %else206081; RV32ZVE32F-NEXT: sw a1, 0(a0)6082; RV32ZVE32F-NEXT: sw a3, 4(a0)6083; RV32ZVE32F-NEXT: sw a4, 8(a0)6084; RV32ZVE32F-NEXT: sw a5, 12(a0)6085; RV32ZVE32F-NEXT: sw a6, 16(a0)6086; RV32ZVE32F-NEXT: sw a7, 20(a0)6087; RV32ZVE32F-NEXT: sw t1, 24(a0)6088; RV32ZVE32F-NEXT: sw t2, 28(a0)6089; RV32ZVE32F-NEXT: sw t3, 32(a0)6090; RV32ZVE32F-NEXT: sw t4, 36(a0)6091; RV32ZVE32F-NEXT: sw t5, 40(a0)6092; RV32ZVE32F-NEXT: sw t6, 44(a0)6093; RV32ZVE32F-NEXT: sw s0, 48(a0)6094; RV32ZVE32F-NEXT: sw s1, 52(a0)6095; RV32ZVE32F-NEXT: sw t0, 56(a0)6096; RV32ZVE32F-NEXT: sw a2, 60(a0)6097; RV32ZVE32F-NEXT: lw s0, 12(sp) # 4-byte Folded Reload6098; RV32ZVE32F-NEXT: lw s1, 8(sp) # 4-byte Folded Reload6099; RV32ZVE32F-NEXT: .cfi_restore s06100; RV32ZVE32F-NEXT: .cfi_restore s16101; RV32ZVE32F-NEXT: addi sp, sp, 166102; RV32ZVE32F-NEXT: .cfi_def_cfa_offset 06103; RV32ZVE32F-NEXT: ret6104;6105; RV64ZVE32F-LABEL: mgather_baseidx_sext_v8i32_v8i64:6106; RV64ZVE32F: # %bb.0:6107; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma6108; RV64ZVE32F-NEXT: vmv.x.s a5, v06109; RV64ZVE32F-NEXT: andi a3, a5, 16110; RV64ZVE32F-NEXT: beqz a3, .LBB55_36111; RV64ZVE32F-NEXT: # %bb.1: # %cond.load6112; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma6113; RV64ZVE32F-NEXT: vmv.x.s a3, v86114; RV64ZVE32F-NEXT: slli a3, a3, 36115; RV64ZVE32F-NEXT: add a3, a1, a36116; RV64ZVE32F-NEXT: ld a3, 0(a3)6117; RV64ZVE32F-NEXT: andi a4, a5, 26118; RV64ZVE32F-NEXT: bnez a4, .LBB55_46119; RV64ZVE32F-NEXT: .LBB55_2:6120; RV64ZVE32F-NEXT: ld a4, 8(a2)6121; RV64ZVE32F-NEXT: j .LBB55_56122; RV64ZVE32F-NEXT: .LBB55_3:6123; RV64ZVE32F-NEXT: ld a3, 0(a2)6124; RV64ZVE32F-NEXT: andi a4, a5, 26125; RV64ZVE32F-NEXT: beqz a4, .LBB55_26126; RV64ZVE32F-NEXT: .LBB55_4: # %cond.load16127; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma6128; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 16129; RV64ZVE32F-NEXT: vmv.x.s a4, v106130; RV64ZVE32F-NEXT: slli a4, a4, 36131; RV64ZVE32F-NEXT: add a4, a1, a46132; RV64ZVE32F-NEXT: ld a4, 0(a4)6133; RV64ZVE32F-NEXT: .LBB55_5: # %else26134; RV64ZVE32F-NEXT: andi a6, a5, 46135; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma6136; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 26137; RV64ZVE32F-NEXT: beqz a6, .LBB55_76138; RV64ZVE32F-NEXT: # %bb.6: # %cond.load46139; RV64ZVE32F-NEXT: vmv.x.s a6, v106140; RV64ZVE32F-NEXT: slli a6, a6, 36141; RV64ZVE32F-NEXT: add a6, a1, a66142; RV64ZVE32F-NEXT: ld a6, 0(a6)6143; RV64ZVE32F-NEXT: j .LBB55_86144; RV64ZVE32F-NEXT: .LBB55_7:6145; RV64ZVE32F-NEXT: ld a6, 16(a2)6146; RV64ZVE32F-NEXT: .LBB55_8: # %else56147; RV64ZVE32F-NEXT: andi a7, a5, 86148; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, ta, ma6149; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 46150; RV64ZVE32F-NEXT: beqz a7, .LBB55_126151; RV64ZVE32F-NEXT: # %bb.9: # %cond.load76152; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma6153; RV64ZVE32F-NEXT: vslidedown.vi v9, v10, 16154; RV64ZVE32F-NEXT: vmv.x.s a7, v96155; RV64ZVE32F-NEXT: slli a7, a7, 36156; RV64ZVE32F-NEXT: add a7, a1, a76157; RV64ZVE32F-NEXT: ld a7, 0(a7)6158; RV64ZVE32F-NEXT: andi t0, a5, 166159; RV64ZVE32F-NEXT: bnez t0, .LBB55_136160; RV64ZVE32F-NEXT: .LBB55_10:6161; RV64ZVE32F-NEXT: ld t0, 32(a2)6162; RV64ZVE32F-NEXT: andi t1, a5, 326163; RV64ZVE32F-NEXT: bnez t1, .LBB55_146164; RV64ZVE32F-NEXT: .LBB55_11:6165; RV64ZVE32F-NEXT: ld t1, 40(a2)6166; RV64ZVE32F-NEXT: j .LBB55_156167; RV64ZVE32F-NEXT: .LBB55_12:6168; RV64ZVE32F-NEXT: ld a7, 24(a2)6169; RV64ZVE32F-NEXT: andi t0, a5, 166170; RV64ZVE32F-NEXT: beqz t0, .LBB55_106171; RV64ZVE32F-NEXT: .LBB55_13: # %cond.load106172; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma6173; RV64ZVE32F-NEXT: vmv.x.s t0, v86174; RV64ZVE32F-NEXT: slli t0, t0, 36175; RV64ZVE32F-NEXT: add t0, a1, t06176; RV64ZVE32F-NEXT: ld t0, 0(t0)6177; RV64ZVE32F-NEXT: andi t1, a5, 326178; RV64ZVE32F-NEXT: beqz t1, .LBB55_116179; RV64ZVE32F-NEXT: .LBB55_14: # %cond.load136180; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma6181; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 16182; RV64ZVE32F-NEXT: vmv.x.s t1, v96183; RV64ZVE32F-NEXT: slli t1, t1, 36184; RV64ZVE32F-NEXT: add t1, a1, t16185; RV64ZVE32F-NEXT: ld t1, 0(t1)6186; RV64ZVE32F-NEXT: .LBB55_15: # %else146187; RV64ZVE32F-NEXT: andi t2, a5, 646188; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma6189; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 26190; RV64ZVE32F-NEXT: beqz t2, .LBB55_186191; RV64ZVE32F-NEXT: # %bb.16: # %cond.load166192; RV64ZVE32F-NEXT: vmv.x.s t2, v86193; RV64ZVE32F-NEXT: slli t2, t2, 36194; RV64ZVE32F-NEXT: add t2, a1, t26195; RV64ZVE32F-NEXT: ld t2, 0(t2)6196; RV64ZVE32F-NEXT: andi a5, a5, -1286197; RV64ZVE32F-NEXT: bnez a5, .LBB55_196198; RV64ZVE32F-NEXT: .LBB55_17:6199; RV64ZVE32F-NEXT: ld a1, 56(a2)6200; RV64ZVE32F-NEXT: j .LBB55_206201; RV64ZVE32F-NEXT: .LBB55_18:6202; RV64ZVE32F-NEXT: ld t2, 48(a2)6203; RV64ZVE32F-NEXT: andi a5, a5, -1286204; RV64ZVE32F-NEXT: beqz a5, .LBB55_176205; RV64ZVE32F-NEXT: .LBB55_19: # %cond.load196206; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 16207; RV64ZVE32F-NEXT: vmv.x.s a2, v86208; RV64ZVE32F-NEXT: slli a2, a2, 36209; RV64ZVE32F-NEXT: add a1, a1, a26210; RV64ZVE32F-NEXT: ld a1, 0(a1)6211; RV64ZVE32F-NEXT: .LBB55_20: # %else206212; RV64ZVE32F-NEXT: sd a3, 0(a0)6213; RV64ZVE32F-NEXT: sd a4, 8(a0)6214; RV64ZVE32F-NEXT: sd a6, 16(a0)6215; RV64ZVE32F-NEXT: sd a7, 24(a0)6216; RV64ZVE32F-NEXT: sd t0, 32(a0)6217; RV64ZVE32F-NEXT: sd t1, 40(a0)6218; RV64ZVE32F-NEXT: sd t2, 48(a0)6219; RV64ZVE32F-NEXT: sd a1, 56(a0)6220; RV64ZVE32F-NEXT: ret6221 %eidxs = sext <8 x i32> %idxs to <8 x i64>6222 %ptrs = getelementptr inbounds i64, ptr %base, <8 x i64> %eidxs6223 %v = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> %ptrs, i32 8, <8 x i1> %m, <8 x i64> %passthru)6224 ret <8 x i64> %v6225}6226 6227define <8 x i64> @mgather_baseidx_zext_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <8 x i1> %m, <8 x i64> %passthru) {6228; RV32V-LABEL: mgather_baseidx_zext_v8i32_v8i64:6229; RV32V: # %bb.0:6230; RV32V-NEXT: vsetivli zero, 8, e32, m2, ta, ma6231; RV32V-NEXT: vsll.vi v8, v8, 36232; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, mu6233; RV32V-NEXT: vluxei32.v v12, (a0), v8, v0.t6234; RV32V-NEXT: vmv.v.v v8, v126235; RV32V-NEXT: ret6236;6237; RV64V-LABEL: mgather_baseidx_zext_v8i32_v8i64:6238; RV64V: # %bb.0:6239; RV64V-NEXT: li a1, 86240; RV64V-NEXT: vsetivli zero, 8, e32, m2, ta, ma6241; RV64V-NEXT: vwmulu.vx v16, v8, a16242; RV64V-NEXT: vsetvli zero, zero, e64, m4, ta, mu6243; RV64V-NEXT: vluxei64.v v12, (a0), v16, v0.t6244; RV64V-NEXT: vmv.v.v v8, v126245; RV64V-NEXT: ret6246;6247; RV32ZVE32F-LABEL: mgather_baseidx_zext_v8i32_v8i64:6248; RV32ZVE32F: # %bb.0:6249; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma6250; RV32ZVE32F-NEXT: vsll.vi v8, v8, 36251; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma6252; RV32ZVE32F-NEXT: vmv.x.s t0, v06253; RV32ZVE32F-NEXT: andi a3, t0, 16254; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma6255; RV32ZVE32F-NEXT: vadd.vx v8, v8, a16256; RV32ZVE32F-NEXT: beqz a3, .LBB56_76257; RV32ZVE32F-NEXT: # %bb.1: # %cond.load6258; RV32ZVE32F-NEXT: vmv.x.s a3, v86259; RV32ZVE32F-NEXT: lw a1, 0(a3)6260; RV32ZVE32F-NEXT: lw a3, 4(a3)6261; RV32ZVE32F-NEXT: andi a4, t0, 26262; RV32ZVE32F-NEXT: bnez a4, .LBB56_86263; RV32ZVE32F-NEXT: .LBB56_2:6264; RV32ZVE32F-NEXT: lw a4, 8(a2)6265; RV32ZVE32F-NEXT: lw a5, 12(a2)6266; RV32ZVE32F-NEXT: andi a6, t0, 46267; RV32ZVE32F-NEXT: bnez a6, .LBB56_96268; RV32ZVE32F-NEXT: .LBB56_3:6269; RV32ZVE32F-NEXT: lw a6, 16(a2)6270; RV32ZVE32F-NEXT: lw a7, 20(a2)6271; RV32ZVE32F-NEXT: andi t1, t0, 86272; RV32ZVE32F-NEXT: bnez t1, .LBB56_106273; RV32ZVE32F-NEXT: .LBB56_4:6274; RV32ZVE32F-NEXT: lw t1, 24(a2)6275; RV32ZVE32F-NEXT: lw t2, 28(a2)6276; RV32ZVE32F-NEXT: andi t3, t0, 166277; RV32ZVE32F-NEXT: bnez t3, .LBB56_116278; RV32ZVE32F-NEXT: .LBB56_5:6279; RV32ZVE32F-NEXT: lw t3, 32(a2)6280; RV32ZVE32F-NEXT: lw t4, 36(a2)6281; RV32ZVE32F-NEXT: andi t5, t0, 326282; RV32ZVE32F-NEXT: bnez t5, .LBB56_126283; RV32ZVE32F-NEXT: .LBB56_6:6284; RV32ZVE32F-NEXT: lw t5, 40(a2)6285; RV32ZVE32F-NEXT: lw t6, 44(a2)6286; RV32ZVE32F-NEXT: j .LBB56_136287; RV32ZVE32F-NEXT: .LBB56_7:6288; RV32ZVE32F-NEXT: lw a1, 0(a2)6289; RV32ZVE32F-NEXT: lw a3, 4(a2)6290; RV32ZVE32F-NEXT: andi a4, t0, 26291; RV32ZVE32F-NEXT: beqz a4, .LBB56_26292; RV32ZVE32F-NEXT: .LBB56_8: # %cond.load16293; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma6294; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 16295; RV32ZVE32F-NEXT: vmv.x.s a5, v106296; RV32ZVE32F-NEXT: lw a4, 0(a5)6297; RV32ZVE32F-NEXT: lw a5, 4(a5)6298; RV32ZVE32F-NEXT: andi a6, t0, 46299; RV32ZVE32F-NEXT: beqz a6, .LBB56_36300; RV32ZVE32F-NEXT: .LBB56_9: # %cond.load46301; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma6302; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 26303; RV32ZVE32F-NEXT: vmv.x.s a7, v106304; RV32ZVE32F-NEXT: lw a6, 0(a7)6305; RV32ZVE32F-NEXT: lw a7, 4(a7)6306; RV32ZVE32F-NEXT: andi t1, t0, 86307; RV32ZVE32F-NEXT: beqz t1, .LBB56_46308; RV32ZVE32F-NEXT: .LBB56_10: # %cond.load76309; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma6310; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 36311; RV32ZVE32F-NEXT: vmv.x.s t2, v106312; RV32ZVE32F-NEXT: lw t1, 0(t2)6313; RV32ZVE32F-NEXT: lw t2, 4(t2)6314; RV32ZVE32F-NEXT: andi t3, t0, 166315; RV32ZVE32F-NEXT: beqz t3, .LBB56_56316; RV32ZVE32F-NEXT: .LBB56_11: # %cond.load106317; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma6318; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 46319; RV32ZVE32F-NEXT: vmv.x.s t4, v106320; RV32ZVE32F-NEXT: lw t3, 0(t4)6321; RV32ZVE32F-NEXT: lw t4, 4(t4)6322; RV32ZVE32F-NEXT: andi t5, t0, 326323; RV32ZVE32F-NEXT: beqz t5, .LBB56_66324; RV32ZVE32F-NEXT: .LBB56_12: # %cond.load136325; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma6326; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 56327; RV32ZVE32F-NEXT: vmv.x.s t6, v106328; RV32ZVE32F-NEXT: lw t5, 0(t6)6329; RV32ZVE32F-NEXT: lw t6, 4(t6)6330; RV32ZVE32F-NEXT: .LBB56_13: # %else146331; RV32ZVE32F-NEXT: addi sp, sp, -166332; RV32ZVE32F-NEXT: .cfi_def_cfa_offset 166333; RV32ZVE32F-NEXT: sw s0, 12(sp) # 4-byte Folded Spill6334; RV32ZVE32F-NEXT: sw s1, 8(sp) # 4-byte Folded Spill6335; RV32ZVE32F-NEXT: .cfi_offset s0, -46336; RV32ZVE32F-NEXT: .cfi_offset s1, -86337; RV32ZVE32F-NEXT: andi s0, t0, 646338; RV32ZVE32F-NEXT: beqz s0, .LBB56_166339; RV32ZVE32F-NEXT: # %bb.14: # %cond.load166340; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma6341; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 66342; RV32ZVE32F-NEXT: vmv.x.s s1, v106343; RV32ZVE32F-NEXT: lw s0, 0(s1)6344; RV32ZVE32F-NEXT: lw s1, 4(s1)6345; RV32ZVE32F-NEXT: andi t0, t0, -1286346; RV32ZVE32F-NEXT: bnez t0, .LBB56_176347; RV32ZVE32F-NEXT: .LBB56_15:6348; RV32ZVE32F-NEXT: lw t0, 56(a2)6349; RV32ZVE32F-NEXT: lw a2, 60(a2)6350; RV32ZVE32F-NEXT: j .LBB56_186351; RV32ZVE32F-NEXT: .LBB56_16:6352; RV32ZVE32F-NEXT: lw s0, 48(a2)6353; RV32ZVE32F-NEXT: lw s1, 52(a2)6354; RV32ZVE32F-NEXT: andi t0, t0, -1286355; RV32ZVE32F-NEXT: beqz t0, .LBB56_156356; RV32ZVE32F-NEXT: .LBB56_17: # %cond.load196357; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma6358; RV32ZVE32F-NEXT: vslidedown.vi v8, v8, 76359; RV32ZVE32F-NEXT: vmv.x.s a2, v86360; RV32ZVE32F-NEXT: lw t0, 0(a2)6361; RV32ZVE32F-NEXT: lw a2, 4(a2)6362; RV32ZVE32F-NEXT: .LBB56_18: # %else206363; RV32ZVE32F-NEXT: sw a1, 0(a0)6364; RV32ZVE32F-NEXT: sw a3, 4(a0)6365; RV32ZVE32F-NEXT: sw a4, 8(a0)6366; RV32ZVE32F-NEXT: sw a5, 12(a0)6367; RV32ZVE32F-NEXT: sw a6, 16(a0)6368; RV32ZVE32F-NEXT: sw a7, 20(a0)6369; RV32ZVE32F-NEXT: sw t1, 24(a0)6370; RV32ZVE32F-NEXT: sw t2, 28(a0)6371; RV32ZVE32F-NEXT: sw t3, 32(a0)6372; RV32ZVE32F-NEXT: sw t4, 36(a0)6373; RV32ZVE32F-NEXT: sw t5, 40(a0)6374; RV32ZVE32F-NEXT: sw t6, 44(a0)6375; RV32ZVE32F-NEXT: sw s0, 48(a0)6376; RV32ZVE32F-NEXT: sw s1, 52(a0)6377; RV32ZVE32F-NEXT: sw t0, 56(a0)6378; RV32ZVE32F-NEXT: sw a2, 60(a0)6379; RV32ZVE32F-NEXT: lw s0, 12(sp) # 4-byte Folded Reload6380; RV32ZVE32F-NEXT: lw s1, 8(sp) # 4-byte Folded Reload6381; RV32ZVE32F-NEXT: .cfi_restore s06382; RV32ZVE32F-NEXT: .cfi_restore s16383; RV32ZVE32F-NEXT: addi sp, sp, 166384; RV32ZVE32F-NEXT: .cfi_def_cfa_offset 06385; RV32ZVE32F-NEXT: ret6386;6387; RV64ZVE32F-LABEL: mgather_baseidx_zext_v8i32_v8i64:6388; RV64ZVE32F: # %bb.0:6389; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma6390; RV64ZVE32F-NEXT: vmv.x.s a5, v06391; RV64ZVE32F-NEXT: andi a3, a5, 16392; RV64ZVE32F-NEXT: beqz a3, .LBB56_36393; RV64ZVE32F-NEXT: # %bb.1: # %cond.load6394; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma6395; RV64ZVE32F-NEXT: vmv.x.s a3, v86396; RV64ZVE32F-NEXT: slli a3, a3, 326397; RV64ZVE32F-NEXT: srli a3, a3, 296398; RV64ZVE32F-NEXT: add a3, a1, a36399; RV64ZVE32F-NEXT: ld a3, 0(a3)6400; RV64ZVE32F-NEXT: andi a4, a5, 26401; RV64ZVE32F-NEXT: bnez a4, .LBB56_46402; RV64ZVE32F-NEXT: .LBB56_2:6403; RV64ZVE32F-NEXT: ld a4, 8(a2)6404; RV64ZVE32F-NEXT: j .LBB56_56405; RV64ZVE32F-NEXT: .LBB56_3:6406; RV64ZVE32F-NEXT: ld a3, 0(a2)6407; RV64ZVE32F-NEXT: andi a4, a5, 26408; RV64ZVE32F-NEXT: beqz a4, .LBB56_26409; RV64ZVE32F-NEXT: .LBB56_4: # %cond.load16410; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma6411; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 16412; RV64ZVE32F-NEXT: vmv.x.s a4, v106413; RV64ZVE32F-NEXT: slli a4, a4, 326414; RV64ZVE32F-NEXT: srli a4, a4, 296415; RV64ZVE32F-NEXT: add a4, a1, a46416; RV64ZVE32F-NEXT: ld a4, 0(a4)6417; RV64ZVE32F-NEXT: .LBB56_5: # %else26418; RV64ZVE32F-NEXT: andi a6, a5, 46419; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma6420; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 26421; RV64ZVE32F-NEXT: beqz a6, .LBB56_76422; RV64ZVE32F-NEXT: # %bb.6: # %cond.load46423; RV64ZVE32F-NEXT: vmv.x.s a6, v106424; RV64ZVE32F-NEXT: slli a6, a6, 326425; RV64ZVE32F-NEXT: srli a6, a6, 296426; RV64ZVE32F-NEXT: add a6, a1, a66427; RV64ZVE32F-NEXT: ld a6, 0(a6)6428; RV64ZVE32F-NEXT: j .LBB56_86429; RV64ZVE32F-NEXT: .LBB56_7:6430; RV64ZVE32F-NEXT: ld a6, 16(a2)6431; RV64ZVE32F-NEXT: .LBB56_8: # %else56432; RV64ZVE32F-NEXT: andi a7, a5, 86433; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, ta, ma6434; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 46435; RV64ZVE32F-NEXT: beqz a7, .LBB56_126436; RV64ZVE32F-NEXT: # %bb.9: # %cond.load76437; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma6438; RV64ZVE32F-NEXT: vslidedown.vi v9, v10, 16439; RV64ZVE32F-NEXT: vmv.x.s a7, v96440; RV64ZVE32F-NEXT: slli a7, a7, 326441; RV64ZVE32F-NEXT: srli a7, a7, 296442; RV64ZVE32F-NEXT: add a7, a1, a76443; RV64ZVE32F-NEXT: ld a7, 0(a7)6444; RV64ZVE32F-NEXT: andi t0, a5, 166445; RV64ZVE32F-NEXT: bnez t0, .LBB56_136446; RV64ZVE32F-NEXT: .LBB56_10:6447; RV64ZVE32F-NEXT: ld t0, 32(a2)6448; RV64ZVE32F-NEXT: andi t1, a5, 326449; RV64ZVE32F-NEXT: bnez t1, .LBB56_146450; RV64ZVE32F-NEXT: .LBB56_11:6451; RV64ZVE32F-NEXT: ld t1, 40(a2)6452; RV64ZVE32F-NEXT: j .LBB56_156453; RV64ZVE32F-NEXT: .LBB56_12:6454; RV64ZVE32F-NEXT: ld a7, 24(a2)6455; RV64ZVE32F-NEXT: andi t0, a5, 166456; RV64ZVE32F-NEXT: beqz t0, .LBB56_106457; RV64ZVE32F-NEXT: .LBB56_13: # %cond.load106458; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma6459; RV64ZVE32F-NEXT: vmv.x.s t0, v86460; RV64ZVE32F-NEXT: slli t0, t0, 326461; RV64ZVE32F-NEXT: srli t0, t0, 296462; RV64ZVE32F-NEXT: add t0, a1, t06463; RV64ZVE32F-NEXT: ld t0, 0(t0)6464; RV64ZVE32F-NEXT: andi t1, a5, 326465; RV64ZVE32F-NEXT: beqz t1, .LBB56_116466; RV64ZVE32F-NEXT: .LBB56_14: # %cond.load136467; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma6468; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 16469; RV64ZVE32F-NEXT: vmv.x.s t1, v96470; RV64ZVE32F-NEXT: slli t1, t1, 326471; RV64ZVE32F-NEXT: srli t1, t1, 296472; RV64ZVE32F-NEXT: add t1, a1, t16473; RV64ZVE32F-NEXT: ld t1, 0(t1)6474; RV64ZVE32F-NEXT: .LBB56_15: # %else146475; RV64ZVE32F-NEXT: andi t2, a5, 646476; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma6477; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 26478; RV64ZVE32F-NEXT: beqz t2, .LBB56_186479; RV64ZVE32F-NEXT: # %bb.16: # %cond.load166480; RV64ZVE32F-NEXT: vmv.x.s t2, v86481; RV64ZVE32F-NEXT: slli t2, t2, 326482; RV64ZVE32F-NEXT: srli t2, t2, 296483; RV64ZVE32F-NEXT: add t2, a1, t26484; RV64ZVE32F-NEXT: ld t2, 0(t2)6485; RV64ZVE32F-NEXT: andi a5, a5, -1286486; RV64ZVE32F-NEXT: bnez a5, .LBB56_196487; RV64ZVE32F-NEXT: .LBB56_17:6488; RV64ZVE32F-NEXT: ld a1, 56(a2)6489; RV64ZVE32F-NEXT: j .LBB56_206490; RV64ZVE32F-NEXT: .LBB56_18:6491; RV64ZVE32F-NEXT: ld t2, 48(a2)6492; RV64ZVE32F-NEXT: andi a5, a5, -1286493; RV64ZVE32F-NEXT: beqz a5, .LBB56_176494; RV64ZVE32F-NEXT: .LBB56_19: # %cond.load196495; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 16496; RV64ZVE32F-NEXT: vmv.x.s a2, v86497; RV64ZVE32F-NEXT: slli a2, a2, 326498; RV64ZVE32F-NEXT: srli a2, a2, 296499; RV64ZVE32F-NEXT: add a1, a1, a26500; RV64ZVE32F-NEXT: ld a1, 0(a1)6501; RV64ZVE32F-NEXT: .LBB56_20: # %else206502; RV64ZVE32F-NEXT: sd a3, 0(a0)6503; RV64ZVE32F-NEXT: sd a4, 8(a0)6504; RV64ZVE32F-NEXT: sd a6, 16(a0)6505; RV64ZVE32F-NEXT: sd a7, 24(a0)6506; RV64ZVE32F-NEXT: sd t0, 32(a0)6507; RV64ZVE32F-NEXT: sd t1, 40(a0)6508; RV64ZVE32F-NEXT: sd t2, 48(a0)6509; RV64ZVE32F-NEXT: sd a1, 56(a0)6510; RV64ZVE32F-NEXT: ret6511 %eidxs = zext <8 x i32> %idxs to <8 x i64>6512 %ptrs = getelementptr inbounds i64, ptr %base, <8 x i64> %eidxs6513 %v = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> %ptrs, i32 8, <8 x i1> %m, <8 x i64> %passthru)6514 ret <8 x i64> %v6515}6516 6517define <8 x i64> @mgather_baseidx_v8i64(ptr %base, <8 x i64> %idxs, <8 x i1> %m, <8 x i64> %passthru) {6518; RV32V-LABEL: mgather_baseidx_v8i64:6519; RV32V: # %bb.0:6520; RV32V-NEXT: vsetivli zero, 8, e32, m2, ta, ma6521; RV32V-NEXT: vnsrl.wi v16, v8, 06522; RV32V-NEXT: vsll.vi v8, v16, 36523; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, mu6524; RV32V-NEXT: vluxei32.v v12, (a0), v8, v0.t6525; RV32V-NEXT: vmv.v.v v8, v126526; RV32V-NEXT: ret6527;6528; RV64V-LABEL: mgather_baseidx_v8i64:6529; RV64V: # %bb.0:6530; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, mu6531; RV64V-NEXT: vsll.vi v8, v8, 36532; RV64V-NEXT: vluxei64.v v12, (a0), v8, v0.t6533; RV64V-NEXT: vmv.v.v v8, v126534; RV64V-NEXT: ret6535;6536; RV32ZVE32F-LABEL: mgather_baseidx_v8i64:6537; RV32ZVE32F: # %bb.0:6538; RV32ZVE32F-NEXT: lw a4, 32(a2)6539; RV32ZVE32F-NEXT: lw a5, 40(a2)6540; RV32ZVE32F-NEXT: lw a6, 48(a2)6541; RV32ZVE32F-NEXT: lw a7, 56(a2)6542; RV32ZVE32F-NEXT: lw t0, 0(a2)6543; RV32ZVE32F-NEXT: lw t1, 8(a2)6544; RV32ZVE32F-NEXT: lw t2, 16(a2)6545; RV32ZVE32F-NEXT: lw a2, 24(a2)6546; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma6547; RV32ZVE32F-NEXT: vmv.v.x v8, t06548; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma6549; RV32ZVE32F-NEXT: vmv.x.s t0, v06550; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma6551; RV32ZVE32F-NEXT: vslide1down.vx v8, v8, t16552; RV32ZVE32F-NEXT: vslide1down.vx v8, v8, t26553; RV32ZVE32F-NEXT: vslide1down.vx v8, v8, a26554; RV32ZVE32F-NEXT: vslide1down.vx v8, v8, a46555; RV32ZVE32F-NEXT: vslide1down.vx v8, v8, a56556; RV32ZVE32F-NEXT: vslide1down.vx v8, v8, a66557; RV32ZVE32F-NEXT: vslide1down.vx v8, v8, a76558; RV32ZVE32F-NEXT: vsll.vi v8, v8, 36559; RV32ZVE32F-NEXT: andi a2, t0, 16560; RV32ZVE32F-NEXT: vadd.vx v8, v8, a16561; RV32ZVE32F-NEXT: beqz a2, .LBB57_76562; RV32ZVE32F-NEXT: # %bb.1: # %cond.load6563; RV32ZVE32F-NEXT: vmv.x.s a2, v86564; RV32ZVE32F-NEXT: lw a1, 0(a2)6565; RV32ZVE32F-NEXT: lw a2, 4(a2)6566; RV32ZVE32F-NEXT: andi a4, t0, 26567; RV32ZVE32F-NEXT: bnez a4, .LBB57_86568; RV32ZVE32F-NEXT: .LBB57_2:6569; RV32ZVE32F-NEXT: lw a4, 8(a3)6570; RV32ZVE32F-NEXT: lw a5, 12(a3)6571; RV32ZVE32F-NEXT: andi a6, t0, 46572; RV32ZVE32F-NEXT: bnez a6, .LBB57_96573; RV32ZVE32F-NEXT: .LBB57_3:6574; RV32ZVE32F-NEXT: lw a6, 16(a3)6575; RV32ZVE32F-NEXT: lw a7, 20(a3)6576; RV32ZVE32F-NEXT: andi t1, t0, 86577; RV32ZVE32F-NEXT: bnez t1, .LBB57_106578; RV32ZVE32F-NEXT: .LBB57_4:6579; RV32ZVE32F-NEXT: lw t1, 24(a3)6580; RV32ZVE32F-NEXT: lw t2, 28(a3)6581; RV32ZVE32F-NEXT: andi t3, t0, 166582; RV32ZVE32F-NEXT: bnez t3, .LBB57_116583; RV32ZVE32F-NEXT: .LBB57_5:6584; RV32ZVE32F-NEXT: lw t3, 32(a3)6585; RV32ZVE32F-NEXT: lw t4, 36(a3)6586; RV32ZVE32F-NEXT: andi t5, t0, 326587; RV32ZVE32F-NEXT: bnez t5, .LBB57_126588; RV32ZVE32F-NEXT: .LBB57_6:6589; RV32ZVE32F-NEXT: lw t5, 40(a3)6590; RV32ZVE32F-NEXT: lw t6, 44(a3)6591; RV32ZVE32F-NEXT: j .LBB57_136592; RV32ZVE32F-NEXT: .LBB57_7:6593; RV32ZVE32F-NEXT: lw a1, 0(a3)6594; RV32ZVE32F-NEXT: lw a2, 4(a3)6595; RV32ZVE32F-NEXT: andi a4, t0, 26596; RV32ZVE32F-NEXT: beqz a4, .LBB57_26597; RV32ZVE32F-NEXT: .LBB57_8: # %cond.load16598; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma6599; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 16600; RV32ZVE32F-NEXT: vmv.x.s a5, v106601; RV32ZVE32F-NEXT: lw a4, 0(a5)6602; RV32ZVE32F-NEXT: lw a5, 4(a5)6603; RV32ZVE32F-NEXT: andi a6, t0, 46604; RV32ZVE32F-NEXT: beqz a6, .LBB57_36605; RV32ZVE32F-NEXT: .LBB57_9: # %cond.load46606; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma6607; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 26608; RV32ZVE32F-NEXT: vmv.x.s a7, v106609; RV32ZVE32F-NEXT: lw a6, 0(a7)6610; RV32ZVE32F-NEXT: lw a7, 4(a7)6611; RV32ZVE32F-NEXT: andi t1, t0, 86612; RV32ZVE32F-NEXT: beqz t1, .LBB57_46613; RV32ZVE32F-NEXT: .LBB57_10: # %cond.load76614; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma6615; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 36616; RV32ZVE32F-NEXT: vmv.x.s t2, v106617; RV32ZVE32F-NEXT: lw t1, 0(t2)6618; RV32ZVE32F-NEXT: lw t2, 4(t2)6619; RV32ZVE32F-NEXT: andi t3, t0, 166620; RV32ZVE32F-NEXT: beqz t3, .LBB57_56621; RV32ZVE32F-NEXT: .LBB57_11: # %cond.load106622; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma6623; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 46624; RV32ZVE32F-NEXT: vmv.x.s t4, v106625; RV32ZVE32F-NEXT: lw t3, 0(t4)6626; RV32ZVE32F-NEXT: lw t4, 4(t4)6627; RV32ZVE32F-NEXT: andi t5, t0, 326628; RV32ZVE32F-NEXT: beqz t5, .LBB57_66629; RV32ZVE32F-NEXT: .LBB57_12: # %cond.load136630; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma6631; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 56632; RV32ZVE32F-NEXT: vmv.x.s t6, v106633; RV32ZVE32F-NEXT: lw t5, 0(t6)6634; RV32ZVE32F-NEXT: lw t6, 4(t6)6635; RV32ZVE32F-NEXT: .LBB57_13: # %else146636; RV32ZVE32F-NEXT: addi sp, sp, -166637; RV32ZVE32F-NEXT: .cfi_def_cfa_offset 166638; RV32ZVE32F-NEXT: sw s0, 12(sp) # 4-byte Folded Spill6639; RV32ZVE32F-NEXT: sw s1, 8(sp) # 4-byte Folded Spill6640; RV32ZVE32F-NEXT: .cfi_offset s0, -46641; RV32ZVE32F-NEXT: .cfi_offset s1, -86642; RV32ZVE32F-NEXT: andi s0, t0, 646643; RV32ZVE32F-NEXT: beqz s0, .LBB57_166644; RV32ZVE32F-NEXT: # %bb.14: # %cond.load166645; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma6646; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 66647; RV32ZVE32F-NEXT: vmv.x.s s1, v106648; RV32ZVE32F-NEXT: lw s0, 0(s1)6649; RV32ZVE32F-NEXT: lw s1, 4(s1)6650; RV32ZVE32F-NEXT: andi t0, t0, -1286651; RV32ZVE32F-NEXT: bnez t0, .LBB57_176652; RV32ZVE32F-NEXT: .LBB57_15:6653; RV32ZVE32F-NEXT: lw t0, 56(a3)6654; RV32ZVE32F-NEXT: lw a3, 60(a3)6655; RV32ZVE32F-NEXT: j .LBB57_186656; RV32ZVE32F-NEXT: .LBB57_16:6657; RV32ZVE32F-NEXT: lw s0, 48(a3)6658; RV32ZVE32F-NEXT: lw s1, 52(a3)6659; RV32ZVE32F-NEXT: andi t0, t0, -1286660; RV32ZVE32F-NEXT: beqz t0, .LBB57_156661; RV32ZVE32F-NEXT: .LBB57_17: # %cond.load196662; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma6663; RV32ZVE32F-NEXT: vslidedown.vi v8, v8, 76664; RV32ZVE32F-NEXT: vmv.x.s a3, v86665; RV32ZVE32F-NEXT: lw t0, 0(a3)6666; RV32ZVE32F-NEXT: lw a3, 4(a3)6667; RV32ZVE32F-NEXT: .LBB57_18: # %else206668; RV32ZVE32F-NEXT: sw a1, 0(a0)6669; RV32ZVE32F-NEXT: sw a2, 4(a0)6670; RV32ZVE32F-NEXT: sw a4, 8(a0)6671; RV32ZVE32F-NEXT: sw a5, 12(a0)6672; RV32ZVE32F-NEXT: sw a6, 16(a0)6673; RV32ZVE32F-NEXT: sw a7, 20(a0)6674; RV32ZVE32F-NEXT: sw t1, 24(a0)6675; RV32ZVE32F-NEXT: sw t2, 28(a0)6676; RV32ZVE32F-NEXT: sw t3, 32(a0)6677; RV32ZVE32F-NEXT: sw t4, 36(a0)6678; RV32ZVE32F-NEXT: sw t5, 40(a0)6679; RV32ZVE32F-NEXT: sw t6, 44(a0)6680; RV32ZVE32F-NEXT: sw s0, 48(a0)6681; RV32ZVE32F-NEXT: sw s1, 52(a0)6682; RV32ZVE32F-NEXT: sw t0, 56(a0)6683; RV32ZVE32F-NEXT: sw a3, 60(a0)6684; RV32ZVE32F-NEXT: lw s0, 12(sp) # 4-byte Folded Reload6685; RV32ZVE32F-NEXT: lw s1, 8(sp) # 4-byte Folded Reload6686; RV32ZVE32F-NEXT: .cfi_restore s06687; RV32ZVE32F-NEXT: .cfi_restore s16688; RV32ZVE32F-NEXT: addi sp, sp, 166689; RV32ZVE32F-NEXT: .cfi_def_cfa_offset 06690; RV32ZVE32F-NEXT: ret6691;6692; RV64ZVE32F-LABEL: mgather_baseidx_v8i64:6693; RV64ZVE32F: # %bb.0:6694; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma6695; RV64ZVE32F-NEXT: vmv.x.s a7, v06696; RV64ZVE32F-NEXT: andi a4, a7, 16697; RV64ZVE32F-NEXT: beqz a4, .LBB57_96698; RV64ZVE32F-NEXT: # %bb.1: # %cond.load6699; RV64ZVE32F-NEXT: ld a4, 0(a2)6700; RV64ZVE32F-NEXT: slli a4, a4, 36701; RV64ZVE32F-NEXT: add a4, a1, a46702; RV64ZVE32F-NEXT: ld a4, 0(a4)6703; RV64ZVE32F-NEXT: andi a5, a7, 26704; RV64ZVE32F-NEXT: bnez a5, .LBB57_106705; RV64ZVE32F-NEXT: .LBB57_2:6706; RV64ZVE32F-NEXT: ld a5, 8(a3)6707; RV64ZVE32F-NEXT: andi a6, a7, 46708; RV64ZVE32F-NEXT: bnez a6, .LBB57_116709; RV64ZVE32F-NEXT: .LBB57_3:6710; RV64ZVE32F-NEXT: ld a6, 16(a3)6711; RV64ZVE32F-NEXT: andi t0, a7, 86712; RV64ZVE32F-NEXT: bnez t0, .LBB57_126713; RV64ZVE32F-NEXT: .LBB57_4:6714; RV64ZVE32F-NEXT: ld t0, 24(a3)6715; RV64ZVE32F-NEXT: andi t1, a7, 166716; RV64ZVE32F-NEXT: bnez t1, .LBB57_136717; RV64ZVE32F-NEXT: .LBB57_5:6718; RV64ZVE32F-NEXT: ld t1, 32(a3)6719; RV64ZVE32F-NEXT: andi t2, a7, 326720; RV64ZVE32F-NEXT: bnez t2, .LBB57_146721; RV64ZVE32F-NEXT: .LBB57_6:6722; RV64ZVE32F-NEXT: ld t2, 40(a3)6723; RV64ZVE32F-NEXT: andi t3, a7, 646724; RV64ZVE32F-NEXT: bnez t3, .LBB57_156725; RV64ZVE32F-NEXT: .LBB57_7:6726; RV64ZVE32F-NEXT: ld t3, 48(a3)6727; RV64ZVE32F-NEXT: andi a7, a7, -1286728; RV64ZVE32F-NEXT: bnez a7, .LBB57_166729; RV64ZVE32F-NEXT: .LBB57_8:6730; RV64ZVE32F-NEXT: ld a1, 56(a3)6731; RV64ZVE32F-NEXT: j .LBB57_176732; RV64ZVE32F-NEXT: .LBB57_9:6733; RV64ZVE32F-NEXT: ld a4, 0(a3)6734; RV64ZVE32F-NEXT: andi a5, a7, 26735; RV64ZVE32F-NEXT: beqz a5, .LBB57_26736; RV64ZVE32F-NEXT: .LBB57_10: # %cond.load16737; RV64ZVE32F-NEXT: ld a5, 8(a2)6738; RV64ZVE32F-NEXT: slli a5, a5, 36739; RV64ZVE32F-NEXT: add a5, a1, a56740; RV64ZVE32F-NEXT: ld a5, 0(a5)6741; RV64ZVE32F-NEXT: andi a6, a7, 46742; RV64ZVE32F-NEXT: beqz a6, .LBB57_36743; RV64ZVE32F-NEXT: .LBB57_11: # %cond.load46744; RV64ZVE32F-NEXT: ld a6, 16(a2)6745; RV64ZVE32F-NEXT: slli a6, a6, 36746; RV64ZVE32F-NEXT: add a6, a1, a66747; RV64ZVE32F-NEXT: ld a6, 0(a6)6748; RV64ZVE32F-NEXT: andi t0, a7, 86749; RV64ZVE32F-NEXT: beqz t0, .LBB57_46750; RV64ZVE32F-NEXT: .LBB57_12: # %cond.load76751; RV64ZVE32F-NEXT: ld t0, 24(a2)6752; RV64ZVE32F-NEXT: slli t0, t0, 36753; RV64ZVE32F-NEXT: add t0, a1, t06754; RV64ZVE32F-NEXT: ld t0, 0(t0)6755; RV64ZVE32F-NEXT: andi t1, a7, 166756; RV64ZVE32F-NEXT: beqz t1, .LBB57_56757; RV64ZVE32F-NEXT: .LBB57_13: # %cond.load106758; RV64ZVE32F-NEXT: ld t1, 32(a2)6759; RV64ZVE32F-NEXT: slli t1, t1, 36760; RV64ZVE32F-NEXT: add t1, a1, t16761; RV64ZVE32F-NEXT: ld t1, 0(t1)6762; RV64ZVE32F-NEXT: andi t2, a7, 326763; RV64ZVE32F-NEXT: beqz t2, .LBB57_66764; RV64ZVE32F-NEXT: .LBB57_14: # %cond.load136765; RV64ZVE32F-NEXT: ld t2, 40(a2)6766; RV64ZVE32F-NEXT: slli t2, t2, 36767; RV64ZVE32F-NEXT: add t2, a1, t26768; RV64ZVE32F-NEXT: ld t2, 0(t2)6769; RV64ZVE32F-NEXT: andi t3, a7, 646770; RV64ZVE32F-NEXT: beqz t3, .LBB57_76771; RV64ZVE32F-NEXT: .LBB57_15: # %cond.load166772; RV64ZVE32F-NEXT: ld t3, 48(a2)6773; RV64ZVE32F-NEXT: slli t3, t3, 36774; RV64ZVE32F-NEXT: add t3, a1, t36775; RV64ZVE32F-NEXT: ld t3, 0(t3)6776; RV64ZVE32F-NEXT: andi a7, a7, -1286777; RV64ZVE32F-NEXT: beqz a7, .LBB57_86778; RV64ZVE32F-NEXT: .LBB57_16: # %cond.load196779; RV64ZVE32F-NEXT: ld a2, 56(a2)6780; RV64ZVE32F-NEXT: slli a2, a2, 36781; RV64ZVE32F-NEXT: add a1, a1, a26782; RV64ZVE32F-NEXT: ld a1, 0(a1)6783; RV64ZVE32F-NEXT: .LBB57_17: # %else206784; RV64ZVE32F-NEXT: sd a4, 0(a0)6785; RV64ZVE32F-NEXT: sd a5, 8(a0)6786; RV64ZVE32F-NEXT: sd a6, 16(a0)6787; RV64ZVE32F-NEXT: sd t0, 24(a0)6788; RV64ZVE32F-NEXT: sd t1, 32(a0)6789; RV64ZVE32F-NEXT: sd t2, 40(a0)6790; RV64ZVE32F-NEXT: sd t3, 48(a0)6791; RV64ZVE32F-NEXT: sd a1, 56(a0)6792; RV64ZVE32F-NEXT: ret6793 %ptrs = getelementptr inbounds i64, ptr %base, <8 x i64> %idxs6794 %v = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> %ptrs, i32 8, <8 x i1> %m, <8 x i64> %passthru)6795 ret <8 x i64> %v6796}6797 6798define <1 x bfloat> @mgather_v1bf16(<1 x ptr> %ptrs, <1 x i1> %m, <1 x bfloat> %passthru) {6799; RV32V-LABEL: mgather_v1bf16:6800; RV32V: # %bb.0:6801; RV32V-NEXT: vsetivli zero, 1, e16, mf4, ta, mu6802; RV32V-NEXT: vluxei32.v v9, (zero), v8, v0.t6803; RV32V-NEXT: vmv1r.v v8, v96804; RV32V-NEXT: ret6805;6806; RV64V-LABEL: mgather_v1bf16:6807; RV64V: # %bb.0:6808; RV64V-NEXT: vsetivli zero, 1, e16, mf4, ta, mu6809; RV64V-NEXT: vluxei64.v v9, (zero), v8, v0.t6810; RV64V-NEXT: vmv1r.v v8, v96811; RV64V-NEXT: ret6812;6813; RV32ZVE32F-LABEL: mgather_v1bf16:6814; RV32ZVE32F: # %bb.0:6815; RV32ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, mu6816; RV32ZVE32F-NEXT: vluxei32.v v9, (zero), v8, v0.t6817; RV32ZVE32F-NEXT: vmv1r.v v8, v96818; RV32ZVE32F-NEXT: ret6819;6820; RV64ZVE32F-LABEL: mgather_v1bf16:6821; RV64ZVE32F: # %bb.0:6822; RV64ZVE32F-NEXT: vsetvli a1, zero, e8, mf4, ta, ma6823; RV64ZVE32F-NEXT: vfirst.m a1, v06824; RV64ZVE32F-NEXT: bnez a1, .LBB58_26825; RV64ZVE32F-NEXT: # %bb.1: # %cond.load6826; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma6827; RV64ZVE32F-NEXT: vle16.v v8, (a0)6828; RV64ZVE32F-NEXT: .LBB58_2: # %else6829; RV64ZVE32F-NEXT: ret6830 %v = call <1 x bfloat> @llvm.masked.gather.v1bf16.v1p0(<1 x ptr> %ptrs, i32 2, <1 x i1> %m, <1 x bfloat> %passthru)6831 ret <1 x bfloat> %v6832}6833 6834define <2 x bfloat> @mgather_v2bf16(<2 x ptr> %ptrs, <2 x i1> %m, <2 x bfloat> %passthru) {6835; RV32V-LABEL: mgather_v2bf16:6836; RV32V: # %bb.0:6837; RV32V-NEXT: vsetivli zero, 2, e16, mf4, ta, mu6838; RV32V-NEXT: vluxei32.v v9, (zero), v8, v0.t6839; RV32V-NEXT: vmv1r.v v8, v96840; RV32V-NEXT: ret6841;6842; RV64V-LABEL: mgather_v2bf16:6843; RV64V: # %bb.0:6844; RV64V-NEXT: vsetivli zero, 2, e16, mf4, ta, mu6845; RV64V-NEXT: vluxei64.v v9, (zero), v8, v0.t6846; RV64V-NEXT: vmv1r.v v8, v96847; RV64V-NEXT: ret6848;6849; RV32ZVE32F-LABEL: mgather_v2bf16:6850; RV32ZVE32F: # %bb.0:6851; RV32ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, mu6852; RV32ZVE32F-NEXT: vluxei32.v v9, (zero), v8, v0.t6853; RV32ZVE32F-NEXT: vmv1r.v v8, v96854; RV32ZVE32F-NEXT: ret6855;6856; RV64ZVE32F-LABEL: mgather_v2bf16:6857; RV64ZVE32F: # %bb.0:6858; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma6859; RV64ZVE32F-NEXT: vmv.x.s a2, v06860; RV64ZVE32F-NEXT: andi a3, a2, 16861; RV64ZVE32F-NEXT: bnez a3, .LBB59_36862; RV64ZVE32F-NEXT: # %bb.1: # %else6863; RV64ZVE32F-NEXT: andi a2, a2, 26864; RV64ZVE32F-NEXT: bnez a2, .LBB59_46865; RV64ZVE32F-NEXT: .LBB59_2: # %else26866; RV64ZVE32F-NEXT: ret6867; RV64ZVE32F-NEXT: .LBB59_3: # %cond.load6868; RV64ZVE32F-NEXT: lh a0, 0(a0)6869; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, tu, ma6870; RV64ZVE32F-NEXT: vmv.s.x v8, a06871; RV64ZVE32F-NEXT: andi a2, a2, 26872; RV64ZVE32F-NEXT: beqz a2, .LBB59_26873; RV64ZVE32F-NEXT: .LBB59_4: # %cond.load16874; RV64ZVE32F-NEXT: lh a0, 0(a1)6875; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma6876; RV64ZVE32F-NEXT: vmv.s.x v9, a06877; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma6878; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 16879; RV64ZVE32F-NEXT: ret6880 %v = call <2 x bfloat> @llvm.masked.gather.v2bf16.v2p0(<2 x ptr> %ptrs, i32 2, <2 x i1> %m, <2 x bfloat> %passthru)6881 ret <2 x bfloat> %v6882}6883 6884define <4 x bfloat> @mgather_v4bf16(<4 x ptr> %ptrs, <4 x i1> %m, <4 x bfloat> %passthru) {6885; RV32-LABEL: mgather_v4bf16:6886; RV32: # %bb.0:6887; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, mu6888; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t6889; RV32-NEXT: vmv1r.v v8, v96890; RV32-NEXT: ret6891;6892; RV64V-LABEL: mgather_v4bf16:6893; RV64V: # %bb.0:6894; RV64V-NEXT: vsetivli zero, 4, e16, mf2, ta, mu6895; RV64V-NEXT: vluxei64.v v10, (zero), v8, v0.t6896; RV64V-NEXT: vmv1r.v v8, v106897; RV64V-NEXT: ret6898;6899; RV64ZVE32F-LABEL: mgather_v4bf16:6900; RV64ZVE32F: # %bb.0:6901; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma6902; RV64ZVE32F-NEXT: vmv.x.s a1, v06903; RV64ZVE32F-NEXT: andi a2, a1, 16904; RV64ZVE32F-NEXT: bnez a2, .LBB60_56905; RV64ZVE32F-NEXT: # %bb.1: # %else6906; RV64ZVE32F-NEXT: andi a2, a1, 26907; RV64ZVE32F-NEXT: bnez a2, .LBB60_66908; RV64ZVE32F-NEXT: .LBB60_2: # %else26909; RV64ZVE32F-NEXT: andi a2, a1, 46910; RV64ZVE32F-NEXT: bnez a2, .LBB60_76911; RV64ZVE32F-NEXT: .LBB60_3: # %else56912; RV64ZVE32F-NEXT: andi a1, a1, 86913; RV64ZVE32F-NEXT: bnez a1, .LBB60_86914; RV64ZVE32F-NEXT: .LBB60_4: # %else86915; RV64ZVE32F-NEXT: ret6916; RV64ZVE32F-NEXT: .LBB60_5: # %cond.load6917; RV64ZVE32F-NEXT: ld a2, 0(a0)6918; RV64ZVE32F-NEXT: lh a2, 0(a2)6919; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, tu, ma6920; RV64ZVE32F-NEXT: vmv.s.x v8, a26921; RV64ZVE32F-NEXT: andi a2, a1, 26922; RV64ZVE32F-NEXT: beqz a2, .LBB60_26923; RV64ZVE32F-NEXT: .LBB60_6: # %cond.load16924; RV64ZVE32F-NEXT: ld a2, 8(a0)6925; RV64ZVE32F-NEXT: lh a2, 0(a2)6926; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma6927; RV64ZVE32F-NEXT: vmv.s.x v9, a26928; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, tu, ma6929; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 16930; RV64ZVE32F-NEXT: andi a2, a1, 46931; RV64ZVE32F-NEXT: beqz a2, .LBB60_36932; RV64ZVE32F-NEXT: .LBB60_7: # %cond.load46933; RV64ZVE32F-NEXT: ld a2, 16(a0)6934; RV64ZVE32F-NEXT: lh a2, 0(a2)6935; RV64ZVE32F-NEXT: vsetivli zero, 3, e16, mf2, tu, ma6936; RV64ZVE32F-NEXT: vmv.s.x v9, a26937; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 26938; RV64ZVE32F-NEXT: andi a1, a1, 86939; RV64ZVE32F-NEXT: beqz a1, .LBB60_46940; RV64ZVE32F-NEXT: .LBB60_8: # %cond.load76941; RV64ZVE32F-NEXT: ld a0, 24(a0)6942; RV64ZVE32F-NEXT: lh a0, 0(a0)6943; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, mf2, ta, ma6944; RV64ZVE32F-NEXT: vmv.s.x v9, a06945; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 36946; RV64ZVE32F-NEXT: ret6947 %v = call <4 x bfloat> @llvm.masked.gather.v4bf16.v4p0(<4 x ptr> %ptrs, i32 2, <4 x i1> %m, <4 x bfloat> %passthru)6948 ret <4 x bfloat> %v6949}6950 6951define <4 x bfloat> @mgather_truemask_v4bf16(<4 x ptr> %ptrs, <4 x bfloat> %passthru) {6952; RV32-LABEL: mgather_truemask_v4bf16:6953; RV32: # %bb.0:6954; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma6955; RV32-NEXT: vluxei32.v v9, (zero), v86956; RV32-NEXT: vmv1r.v v8, v96957; RV32-NEXT: ret6958;6959; RV64V-LABEL: mgather_truemask_v4bf16:6960; RV64V: # %bb.0:6961; RV64V-NEXT: vsetivli zero, 4, e16, mf2, ta, ma6962; RV64V-NEXT: vluxei64.v v10, (zero), v86963; RV64V-NEXT: vmv1r.v v8, v106964; RV64V-NEXT: ret6965;6966; RV64ZVE32F-LABEL: mgather_truemask_v4bf16:6967; RV64ZVE32F: # %bb.0:6968; RV64ZVE32F-NEXT: ld a1, 0(a0)6969; RV64ZVE32F-NEXT: ld a2, 8(a0)6970; RV64ZVE32F-NEXT: ld a3, 16(a0)6971; RV64ZVE32F-NEXT: ld a0, 24(a0)6972; RV64ZVE32F-NEXT: lh a1, 0(a1)6973; RV64ZVE32F-NEXT: lh a2, 0(a2)6974; RV64ZVE32F-NEXT: lh a3, 0(a3)6975; RV64ZVE32F-NEXT: lh a0, 0(a0)6976; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, mf2, ta, ma6977; RV64ZVE32F-NEXT: vmv.v.x v8, a16978; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a26979; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a36980; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a06981; RV64ZVE32F-NEXT: ret6982 %v = call <4 x bfloat> @llvm.masked.gather.v4bf16.v4p0(<4 x ptr> %ptrs, i32 2, <4 x i1> splat (i1 1), <4 x bfloat> %passthru)6983 ret <4 x bfloat> %v6984}6985 6986define <4 x bfloat> @mgather_falsemask_v4bf16(<4 x ptr> %ptrs, <4 x bfloat> %passthru) {6987; RV32-LABEL: mgather_falsemask_v4bf16:6988; RV32: # %bb.0:6989; RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma6990; RV32-NEXT: vmv1r.v v8, v96991; RV32-NEXT: ret6992;6993; RV64V-LABEL: mgather_falsemask_v4bf16:6994; RV64V: # %bb.0:6995; RV64V-NEXT: vsetivli zero, 1, e8, m1, ta, ma6996; RV64V-NEXT: vmv1r.v v8, v106997; RV64V-NEXT: ret6998;6999; RV64ZVE32F-LABEL: mgather_falsemask_v4bf16:7000; RV64ZVE32F: # %bb.0:7001; RV64ZVE32F-NEXT: ret7002 %v = call <4 x bfloat> @llvm.masked.gather.v4bf16.v4p0(<4 x ptr> %ptrs, i32 2, <4 x i1> zeroinitializer, <4 x bfloat> %passthru)7003 ret <4 x bfloat> %v7004}7005 7006define <8 x bfloat> @mgather_v8bf16(<8 x ptr> %ptrs, <8 x i1> %m, <8 x bfloat> %passthru) {7007; RV32-LABEL: mgather_v8bf16:7008; RV32: # %bb.0:7009; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu7010; RV32-NEXT: vluxei32.v v10, (zero), v8, v0.t7011; RV32-NEXT: vmv.v.v v8, v107012; RV32-NEXT: ret7013;7014; RV64V-LABEL: mgather_v8bf16:7015; RV64V: # %bb.0:7016; RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, mu7017; RV64V-NEXT: vluxei64.v v12, (zero), v8, v0.t7018; RV64V-NEXT: vmv.v.v v8, v127019; RV64V-NEXT: ret7020;7021; RV64ZVE32F-LABEL: mgather_v8bf16:7022; RV64ZVE32F: # %bb.0:7023; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma7024; RV64ZVE32F-NEXT: vmv.x.s a1, v07025; RV64ZVE32F-NEXT: andi a2, a1, 17026; RV64ZVE32F-NEXT: bnez a2, .LBB63_97027; RV64ZVE32F-NEXT: # %bb.1: # %else7028; RV64ZVE32F-NEXT: andi a2, a1, 27029; RV64ZVE32F-NEXT: bnez a2, .LBB63_107030; RV64ZVE32F-NEXT: .LBB63_2: # %else27031; RV64ZVE32F-NEXT: andi a2, a1, 47032; RV64ZVE32F-NEXT: bnez a2, .LBB63_117033; RV64ZVE32F-NEXT: .LBB63_3: # %else57034; RV64ZVE32F-NEXT: andi a2, a1, 87035; RV64ZVE32F-NEXT: bnez a2, .LBB63_127036; RV64ZVE32F-NEXT: .LBB63_4: # %else87037; RV64ZVE32F-NEXT: andi a2, a1, 167038; RV64ZVE32F-NEXT: bnez a2, .LBB63_137039; RV64ZVE32F-NEXT: .LBB63_5: # %else117040; RV64ZVE32F-NEXT: andi a2, a1, 327041; RV64ZVE32F-NEXT: bnez a2, .LBB63_147042; RV64ZVE32F-NEXT: .LBB63_6: # %else147043; RV64ZVE32F-NEXT: andi a2, a1, 647044; RV64ZVE32F-NEXT: bnez a2, .LBB63_157045; RV64ZVE32F-NEXT: .LBB63_7: # %else177046; RV64ZVE32F-NEXT: andi a1, a1, -1287047; RV64ZVE32F-NEXT: bnez a1, .LBB63_167048; RV64ZVE32F-NEXT: .LBB63_8: # %else207049; RV64ZVE32F-NEXT: ret7050; RV64ZVE32F-NEXT: .LBB63_9: # %cond.load7051; RV64ZVE32F-NEXT: ld a2, 0(a0)7052; RV64ZVE32F-NEXT: lh a2, 0(a2)7053; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, tu, ma7054; RV64ZVE32F-NEXT: vmv.s.x v8, a27055; RV64ZVE32F-NEXT: andi a2, a1, 27056; RV64ZVE32F-NEXT: beqz a2, .LBB63_27057; RV64ZVE32F-NEXT: .LBB63_10: # %cond.load17058; RV64ZVE32F-NEXT: ld a2, 8(a0)7059; RV64ZVE32F-NEXT: lh a2, 0(a2)7060; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma7061; RV64ZVE32F-NEXT: vmv.s.x v9, a27062; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, m1, tu, ma7063; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 17064; RV64ZVE32F-NEXT: andi a2, a1, 47065; RV64ZVE32F-NEXT: beqz a2, .LBB63_37066; RV64ZVE32F-NEXT: .LBB63_11: # %cond.load47067; RV64ZVE32F-NEXT: ld a2, 16(a0)7068; RV64ZVE32F-NEXT: lh a2, 0(a2)7069; RV64ZVE32F-NEXT: vsetivli zero, 3, e16, m1, tu, ma7070; RV64ZVE32F-NEXT: vmv.s.x v9, a27071; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 27072; RV64ZVE32F-NEXT: andi a2, a1, 87073; RV64ZVE32F-NEXT: beqz a2, .LBB63_47074; RV64ZVE32F-NEXT: .LBB63_12: # %cond.load77075; RV64ZVE32F-NEXT: ld a2, 24(a0)7076; RV64ZVE32F-NEXT: lh a2, 0(a2)7077; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma7078; RV64ZVE32F-NEXT: vmv.s.x v9, a27079; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 37080; RV64ZVE32F-NEXT: andi a2, a1, 167081; RV64ZVE32F-NEXT: beqz a2, .LBB63_57082; RV64ZVE32F-NEXT: .LBB63_13: # %cond.load107083; RV64ZVE32F-NEXT: ld a2, 32(a0)7084; RV64ZVE32F-NEXT: lh a2, 0(a2)7085; RV64ZVE32F-NEXT: vsetivli zero, 5, e16, m1, tu, ma7086; RV64ZVE32F-NEXT: vmv.s.x v9, a27087; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 47088; RV64ZVE32F-NEXT: andi a2, a1, 327089; RV64ZVE32F-NEXT: beqz a2, .LBB63_67090; RV64ZVE32F-NEXT: .LBB63_14: # %cond.load137091; RV64ZVE32F-NEXT: ld a2, 40(a0)7092; RV64ZVE32F-NEXT: lh a2, 0(a2)7093; RV64ZVE32F-NEXT: vsetivli zero, 6, e16, m1, tu, ma7094; RV64ZVE32F-NEXT: vmv.s.x v9, a27095; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 57096; RV64ZVE32F-NEXT: andi a2, a1, 647097; RV64ZVE32F-NEXT: beqz a2, .LBB63_77098; RV64ZVE32F-NEXT: .LBB63_15: # %cond.load167099; RV64ZVE32F-NEXT: ld a2, 48(a0)7100; RV64ZVE32F-NEXT: lh a2, 0(a2)7101; RV64ZVE32F-NEXT: vsetivli zero, 7, e16, m1, tu, ma7102; RV64ZVE32F-NEXT: vmv.s.x v9, a27103; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 67104; RV64ZVE32F-NEXT: andi a1, a1, -1287105; RV64ZVE32F-NEXT: beqz a1, .LBB63_87106; RV64ZVE32F-NEXT: .LBB63_16: # %cond.load197107; RV64ZVE32F-NEXT: ld a0, 56(a0)7108; RV64ZVE32F-NEXT: lh a0, 0(a0)7109; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma7110; RV64ZVE32F-NEXT: vmv.s.x v9, a07111; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 77112; RV64ZVE32F-NEXT: ret7113 %v = call <8 x bfloat> @llvm.masked.gather.v8bf16.v8p0(<8 x ptr> %ptrs, i32 2, <8 x i1> %m, <8 x bfloat> %passthru)7114 ret <8 x bfloat> %v7115}7116 7117define <8 x bfloat> @mgather_baseidx_v8i8_v8bf16(ptr %base, <8 x i8> %idxs, <8 x i1> %m, <8 x bfloat> %passthru) {7118; RV32-LABEL: mgather_baseidx_v8i8_v8bf16:7119; RV32: # %bb.0:7120; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma7121; RV32-NEXT: vsext.vf4 v10, v87122; RV32-NEXT: vadd.vv v10, v10, v107123; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu7124; RV32-NEXT: vluxei32.v v9, (a0), v10, v0.t7125; RV32-NEXT: vmv.v.v v8, v97126; RV32-NEXT: ret7127;7128; RV64V-LABEL: mgather_baseidx_v8i8_v8bf16:7129; RV64V: # %bb.0:7130; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma7131; RV64V-NEXT: vsext.vf8 v12, v87132; RV64V-NEXT: vadd.vv v12, v12, v127133; RV64V-NEXT: vsetvli zero, zero, e16, m1, ta, mu7134; RV64V-NEXT: vluxei64.v v9, (a0), v12, v0.t7135; RV64V-NEXT: vmv.v.v v8, v97136; RV64V-NEXT: ret7137;7138; RV64ZVE32F-LABEL: mgather_baseidx_v8i8_v8bf16:7139; RV64ZVE32F: # %bb.0:7140; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma7141; RV64ZVE32F-NEXT: vmv.x.s a1, v07142; RV64ZVE32F-NEXT: andi a2, a1, 17143; RV64ZVE32F-NEXT: beqz a2, .LBB64_27144; RV64ZVE32F-NEXT: # %bb.1: # %cond.load7145; RV64ZVE32F-NEXT: vmv.x.s a2, v87146; RV64ZVE32F-NEXT: slli a2, a2, 17147; RV64ZVE32F-NEXT: add a2, a0, a27148; RV64ZVE32F-NEXT: lh a2, 0(a2)7149; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, tu, ma7150; RV64ZVE32F-NEXT: vmv.s.x v9, a27151; RV64ZVE32F-NEXT: .LBB64_2: # %else7152; RV64ZVE32F-NEXT: andi a2, a1, 27153; RV64ZVE32F-NEXT: beqz a2, .LBB64_47154; RV64ZVE32F-NEXT: # %bb.3: # %cond.load17155; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma7156; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 17157; RV64ZVE32F-NEXT: vmv.x.s a2, v107158; RV64ZVE32F-NEXT: slli a2, a2, 17159; RV64ZVE32F-NEXT: add a2, a0, a27160; RV64ZVE32F-NEXT: lh a2, 0(a2)7161; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma7162; RV64ZVE32F-NEXT: vmv.s.x v10, a27163; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, m1, tu, ma7164; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 17165; RV64ZVE32F-NEXT: .LBB64_4: # %else27166; RV64ZVE32F-NEXT: andi a2, a1, 47167; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma7168; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 27169; RV64ZVE32F-NEXT: beqz a2, .LBB64_67170; RV64ZVE32F-NEXT: # %bb.5: # %cond.load47171; RV64ZVE32F-NEXT: vmv.x.s a2, v107172; RV64ZVE32F-NEXT: slli a2, a2, 17173; RV64ZVE32F-NEXT: add a2, a0, a27174; RV64ZVE32F-NEXT: lh a2, 0(a2)7175; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma7176; RV64ZVE32F-NEXT: vmv.s.x v11, a27177; RV64ZVE32F-NEXT: vsetivli zero, 3, e16, m1, tu, ma7178; RV64ZVE32F-NEXT: vslideup.vi v9, v11, 27179; RV64ZVE32F-NEXT: .LBB64_6: # %else57180; RV64ZVE32F-NEXT: andi a2, a1, 87181; RV64ZVE32F-NEXT: beqz a2, .LBB64_87182; RV64ZVE32F-NEXT: # %bb.7: # %cond.load77183; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma7184; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 17185; RV64ZVE32F-NEXT: vmv.x.s a2, v107186; RV64ZVE32F-NEXT: slli a2, a2, 17187; RV64ZVE32F-NEXT: add a2, a0, a27188; RV64ZVE32F-NEXT: lh a2, 0(a2)7189; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma7190; RV64ZVE32F-NEXT: vmv.s.x v10, a27191; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma7192; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 37193; RV64ZVE32F-NEXT: .LBB64_8: # %else87194; RV64ZVE32F-NEXT: andi a2, a1, 167195; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma7196; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 47197; RV64ZVE32F-NEXT: beqz a2, .LBB64_107198; RV64ZVE32F-NEXT: # %bb.9: # %cond.load107199; RV64ZVE32F-NEXT: vmv.x.s a2, v87200; RV64ZVE32F-NEXT: slli a2, a2, 17201; RV64ZVE32F-NEXT: add a2, a0, a27202; RV64ZVE32F-NEXT: lh a2, 0(a2)7203; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma7204; RV64ZVE32F-NEXT: vmv.s.x v10, a27205; RV64ZVE32F-NEXT: vsetivli zero, 5, e16, m1, tu, ma7206; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 47207; RV64ZVE32F-NEXT: .LBB64_10: # %else117208; RV64ZVE32F-NEXT: andi a2, a1, 327209; RV64ZVE32F-NEXT: beqz a2, .LBB64_127210; RV64ZVE32F-NEXT: # %bb.11: # %cond.load137211; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma7212; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 17213; RV64ZVE32F-NEXT: vmv.x.s a2, v107214; RV64ZVE32F-NEXT: slli a2, a2, 17215; RV64ZVE32F-NEXT: add a2, a0, a27216; RV64ZVE32F-NEXT: lh a2, 0(a2)7217; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma7218; RV64ZVE32F-NEXT: vmv.s.x v10, a27219; RV64ZVE32F-NEXT: vsetivli zero, 6, e16, m1, tu, ma7220; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 57221; RV64ZVE32F-NEXT: .LBB64_12: # %else147222; RV64ZVE32F-NEXT: andi a2, a1, 647223; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma7224; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 27225; RV64ZVE32F-NEXT: beqz a2, .LBB64_147226; RV64ZVE32F-NEXT: # %bb.13: # %cond.load167227; RV64ZVE32F-NEXT: vmv.x.s a2, v87228; RV64ZVE32F-NEXT: slli a2, a2, 17229; RV64ZVE32F-NEXT: add a2, a0, a27230; RV64ZVE32F-NEXT: lh a2, 0(a2)7231; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma7232; RV64ZVE32F-NEXT: vmv.s.x v10, a27233; RV64ZVE32F-NEXT: vsetivli zero, 7, e16, m1, tu, ma7234; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 67235; RV64ZVE32F-NEXT: .LBB64_14: # %else177236; RV64ZVE32F-NEXT: andi a1, a1, -1287237; RV64ZVE32F-NEXT: beqz a1, .LBB64_167238; RV64ZVE32F-NEXT: # %bb.15: # %cond.load197239; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma7240; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 17241; RV64ZVE32F-NEXT: vmv.x.s a1, v87242; RV64ZVE32F-NEXT: slli a1, a1, 17243; RV64ZVE32F-NEXT: add a0, a0, a17244; RV64ZVE32F-NEXT: lh a0, 0(a0)7245; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma7246; RV64ZVE32F-NEXT: vmv.s.x v8, a07247; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma7248; RV64ZVE32F-NEXT: vslideup.vi v9, v8, 77249; RV64ZVE32F-NEXT: .LBB64_16: # %else207250; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma7251; RV64ZVE32F-NEXT: vmv1r.v v8, v97252; RV64ZVE32F-NEXT: ret7253 %ptrs = getelementptr inbounds bfloat, ptr %base, <8 x i8> %idxs7254 %v = call <8 x bfloat> @llvm.masked.gather.v8bf16.v8p0(<8 x ptr> %ptrs, i32 2, <8 x i1> %m, <8 x bfloat> %passthru)7255 ret <8 x bfloat> %v7256}7257 7258define <8 x bfloat> @mgather_baseidx_sext_v8i8_v8bf16(ptr %base, <8 x i8> %idxs, <8 x i1> %m, <8 x bfloat> %passthru) {7259; RV32-LABEL: mgather_baseidx_sext_v8i8_v8bf16:7260; RV32: # %bb.0:7261; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma7262; RV32-NEXT: vsext.vf4 v10, v87263; RV32-NEXT: vadd.vv v10, v10, v107264; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu7265; RV32-NEXT: vluxei32.v v9, (a0), v10, v0.t7266; RV32-NEXT: vmv.v.v v8, v97267; RV32-NEXT: ret7268;7269; RV64V-LABEL: mgather_baseidx_sext_v8i8_v8bf16:7270; RV64V: # %bb.0:7271; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma7272; RV64V-NEXT: vsext.vf8 v12, v87273; RV64V-NEXT: vadd.vv v12, v12, v127274; RV64V-NEXT: vsetvli zero, zero, e16, m1, ta, mu7275; RV64V-NEXT: vluxei64.v v9, (a0), v12, v0.t7276; RV64V-NEXT: vmv.v.v v8, v97277; RV64V-NEXT: ret7278;7279; RV64ZVE32F-LABEL: mgather_baseidx_sext_v8i8_v8bf16:7280; RV64ZVE32F: # %bb.0:7281; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma7282; RV64ZVE32F-NEXT: vmv.x.s a1, v07283; RV64ZVE32F-NEXT: andi a2, a1, 17284; RV64ZVE32F-NEXT: beqz a2, .LBB65_27285; RV64ZVE32F-NEXT: # %bb.1: # %cond.load7286; RV64ZVE32F-NEXT: vmv.x.s a2, v87287; RV64ZVE32F-NEXT: slli a2, a2, 17288; RV64ZVE32F-NEXT: add a2, a0, a27289; RV64ZVE32F-NEXT: lh a2, 0(a2)7290; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, tu, ma7291; RV64ZVE32F-NEXT: vmv.s.x v9, a27292; RV64ZVE32F-NEXT: .LBB65_2: # %else7293; RV64ZVE32F-NEXT: andi a2, a1, 27294; RV64ZVE32F-NEXT: beqz a2, .LBB65_47295; RV64ZVE32F-NEXT: # %bb.3: # %cond.load17296; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma7297; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 17298; RV64ZVE32F-NEXT: vmv.x.s a2, v107299; RV64ZVE32F-NEXT: slli a2, a2, 17300; RV64ZVE32F-NEXT: add a2, a0, a27301; RV64ZVE32F-NEXT: lh a2, 0(a2)7302; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma7303; RV64ZVE32F-NEXT: vmv.s.x v10, a27304; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, m1, tu, ma7305; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 17306; RV64ZVE32F-NEXT: .LBB65_4: # %else27307; RV64ZVE32F-NEXT: andi a2, a1, 47308; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma7309; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 27310; RV64ZVE32F-NEXT: beqz a2, .LBB65_67311; RV64ZVE32F-NEXT: # %bb.5: # %cond.load47312; RV64ZVE32F-NEXT: vmv.x.s a2, v107313; RV64ZVE32F-NEXT: slli a2, a2, 17314; RV64ZVE32F-NEXT: add a2, a0, a27315; RV64ZVE32F-NEXT: lh a2, 0(a2)7316; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma7317; RV64ZVE32F-NEXT: vmv.s.x v11, a27318; RV64ZVE32F-NEXT: vsetivli zero, 3, e16, m1, tu, ma7319; RV64ZVE32F-NEXT: vslideup.vi v9, v11, 27320; RV64ZVE32F-NEXT: .LBB65_6: # %else57321; RV64ZVE32F-NEXT: andi a2, a1, 87322; RV64ZVE32F-NEXT: beqz a2, .LBB65_87323; RV64ZVE32F-NEXT: # %bb.7: # %cond.load77324; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma7325; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 17326; RV64ZVE32F-NEXT: vmv.x.s a2, v107327; RV64ZVE32F-NEXT: slli a2, a2, 17328; RV64ZVE32F-NEXT: add a2, a0, a27329; RV64ZVE32F-NEXT: lh a2, 0(a2)7330; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma7331; RV64ZVE32F-NEXT: vmv.s.x v10, a27332; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma7333; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 37334; RV64ZVE32F-NEXT: .LBB65_8: # %else87335; RV64ZVE32F-NEXT: andi a2, a1, 167336; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma7337; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 47338; RV64ZVE32F-NEXT: beqz a2, .LBB65_107339; RV64ZVE32F-NEXT: # %bb.9: # %cond.load107340; RV64ZVE32F-NEXT: vmv.x.s a2, v87341; RV64ZVE32F-NEXT: slli a2, a2, 17342; RV64ZVE32F-NEXT: add a2, a0, a27343; RV64ZVE32F-NEXT: lh a2, 0(a2)7344; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma7345; RV64ZVE32F-NEXT: vmv.s.x v10, a27346; RV64ZVE32F-NEXT: vsetivli zero, 5, e16, m1, tu, ma7347; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 47348; RV64ZVE32F-NEXT: .LBB65_10: # %else117349; RV64ZVE32F-NEXT: andi a2, a1, 327350; RV64ZVE32F-NEXT: beqz a2, .LBB65_127351; RV64ZVE32F-NEXT: # %bb.11: # %cond.load137352; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma7353; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 17354; RV64ZVE32F-NEXT: vmv.x.s a2, v107355; RV64ZVE32F-NEXT: slli a2, a2, 17356; RV64ZVE32F-NEXT: add a2, a0, a27357; RV64ZVE32F-NEXT: lh a2, 0(a2)7358; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma7359; RV64ZVE32F-NEXT: vmv.s.x v10, a27360; RV64ZVE32F-NEXT: vsetivli zero, 6, e16, m1, tu, ma7361; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 57362; RV64ZVE32F-NEXT: .LBB65_12: # %else147363; RV64ZVE32F-NEXT: andi a2, a1, 647364; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma7365; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 27366; RV64ZVE32F-NEXT: beqz a2, .LBB65_147367; RV64ZVE32F-NEXT: # %bb.13: # %cond.load167368; RV64ZVE32F-NEXT: vmv.x.s a2, v87369; RV64ZVE32F-NEXT: slli a2, a2, 17370; RV64ZVE32F-NEXT: add a2, a0, a27371; RV64ZVE32F-NEXT: lh a2, 0(a2)7372; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma7373; RV64ZVE32F-NEXT: vmv.s.x v10, a27374; RV64ZVE32F-NEXT: vsetivli zero, 7, e16, m1, tu, ma7375; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 67376; RV64ZVE32F-NEXT: .LBB65_14: # %else177377; RV64ZVE32F-NEXT: andi a1, a1, -1287378; RV64ZVE32F-NEXT: beqz a1, .LBB65_167379; RV64ZVE32F-NEXT: # %bb.15: # %cond.load197380; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma7381; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 17382; RV64ZVE32F-NEXT: vmv.x.s a1, v87383; RV64ZVE32F-NEXT: slli a1, a1, 17384; RV64ZVE32F-NEXT: add a0, a0, a17385; RV64ZVE32F-NEXT: lh a0, 0(a0)7386; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma7387; RV64ZVE32F-NEXT: vmv.s.x v8, a07388; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma7389; RV64ZVE32F-NEXT: vslideup.vi v9, v8, 77390; RV64ZVE32F-NEXT: .LBB65_16: # %else207391; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma7392; RV64ZVE32F-NEXT: vmv1r.v v8, v97393; RV64ZVE32F-NEXT: ret7394 %eidxs = sext <8 x i8> %idxs to <8 x i16>7395 %ptrs = getelementptr inbounds bfloat, ptr %base, <8 x i16> %eidxs7396 %v = call <8 x bfloat> @llvm.masked.gather.v8bf16.v8p0(<8 x ptr> %ptrs, i32 2, <8 x i1> %m, <8 x bfloat> %passthru)7397 ret <8 x bfloat> %v7398}7399 7400define <8 x bfloat> @mgather_baseidx_zext_v8i8_v8bf16(ptr %base, <8 x i8> %idxs, <8 x i1> %m, <8 x bfloat> %passthru) {7401; RV32-LABEL: mgather_baseidx_zext_v8i8_v8bf16:7402; RV32: # %bb.0:7403; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma7404; RV32-NEXT: vwaddu.vv v10, v8, v87405; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu7406; RV32-NEXT: vluxei16.v v9, (a0), v10, v0.t7407; RV32-NEXT: vmv.v.v v8, v97408; RV32-NEXT: ret7409;7410; RV64V-LABEL: mgather_baseidx_zext_v8i8_v8bf16:7411; RV64V: # %bb.0:7412; RV64V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma7413; RV64V-NEXT: vwaddu.vv v10, v8, v87414; RV64V-NEXT: vsetvli zero, zero, e16, m1, ta, mu7415; RV64V-NEXT: vluxei16.v v9, (a0), v10, v0.t7416; RV64V-NEXT: vmv.v.v v8, v97417; RV64V-NEXT: ret7418;7419; RV64ZVE32F-LABEL: mgather_baseidx_zext_v8i8_v8bf16:7420; RV64ZVE32F: # %bb.0:7421; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma7422; RV64ZVE32F-NEXT: vmv.x.s a1, v07423; RV64ZVE32F-NEXT: andi a2, a1, 17424; RV64ZVE32F-NEXT: beqz a2, .LBB66_27425; RV64ZVE32F-NEXT: # %bb.1: # %cond.load7426; RV64ZVE32F-NEXT: vmv.x.s a2, v87427; RV64ZVE32F-NEXT: zext.b a2, a27428; RV64ZVE32F-NEXT: slli a2, a2, 17429; RV64ZVE32F-NEXT: add a2, a0, a27430; RV64ZVE32F-NEXT: lh a2, 0(a2)7431; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, tu, ma7432; RV64ZVE32F-NEXT: vmv.s.x v9, a27433; RV64ZVE32F-NEXT: .LBB66_2: # %else7434; RV64ZVE32F-NEXT: andi a2, a1, 27435; RV64ZVE32F-NEXT: beqz a2, .LBB66_47436; RV64ZVE32F-NEXT: # %bb.3: # %cond.load17437; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma7438; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 17439; RV64ZVE32F-NEXT: vmv.x.s a2, v107440; RV64ZVE32F-NEXT: zext.b a2, a27441; RV64ZVE32F-NEXT: slli a2, a2, 17442; RV64ZVE32F-NEXT: add a2, a0, a27443; RV64ZVE32F-NEXT: lh a2, 0(a2)7444; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma7445; RV64ZVE32F-NEXT: vmv.s.x v10, a27446; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, m1, tu, ma7447; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 17448; RV64ZVE32F-NEXT: .LBB66_4: # %else27449; RV64ZVE32F-NEXT: andi a2, a1, 47450; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma7451; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 27452; RV64ZVE32F-NEXT: beqz a2, .LBB66_67453; RV64ZVE32F-NEXT: # %bb.5: # %cond.load47454; RV64ZVE32F-NEXT: vmv.x.s a2, v107455; RV64ZVE32F-NEXT: zext.b a2, a27456; RV64ZVE32F-NEXT: slli a2, a2, 17457; RV64ZVE32F-NEXT: add a2, a0, a27458; RV64ZVE32F-NEXT: lh a2, 0(a2)7459; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma7460; RV64ZVE32F-NEXT: vmv.s.x v11, a27461; RV64ZVE32F-NEXT: vsetivli zero, 3, e16, m1, tu, ma7462; RV64ZVE32F-NEXT: vslideup.vi v9, v11, 27463; RV64ZVE32F-NEXT: .LBB66_6: # %else57464; RV64ZVE32F-NEXT: andi a2, a1, 87465; RV64ZVE32F-NEXT: beqz a2, .LBB66_87466; RV64ZVE32F-NEXT: # %bb.7: # %cond.load77467; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma7468; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 17469; RV64ZVE32F-NEXT: vmv.x.s a2, v107470; RV64ZVE32F-NEXT: zext.b a2, a27471; RV64ZVE32F-NEXT: slli a2, a2, 17472; RV64ZVE32F-NEXT: add a2, a0, a27473; RV64ZVE32F-NEXT: lh a2, 0(a2)7474; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma7475; RV64ZVE32F-NEXT: vmv.s.x v10, a27476; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma7477; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 37478; RV64ZVE32F-NEXT: .LBB66_8: # %else87479; RV64ZVE32F-NEXT: andi a2, a1, 167480; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma7481; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 47482; RV64ZVE32F-NEXT: beqz a2, .LBB66_107483; RV64ZVE32F-NEXT: # %bb.9: # %cond.load107484; RV64ZVE32F-NEXT: vmv.x.s a2, v87485; RV64ZVE32F-NEXT: zext.b a2, a27486; RV64ZVE32F-NEXT: slli a2, a2, 17487; RV64ZVE32F-NEXT: add a2, a0, a27488; RV64ZVE32F-NEXT: lh a2, 0(a2)7489; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma7490; RV64ZVE32F-NEXT: vmv.s.x v10, a27491; RV64ZVE32F-NEXT: vsetivli zero, 5, e16, m1, tu, ma7492; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 47493; RV64ZVE32F-NEXT: .LBB66_10: # %else117494; RV64ZVE32F-NEXT: andi a2, a1, 327495; RV64ZVE32F-NEXT: beqz a2, .LBB66_127496; RV64ZVE32F-NEXT: # %bb.11: # %cond.load137497; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma7498; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 17499; RV64ZVE32F-NEXT: vmv.x.s a2, v107500; RV64ZVE32F-NEXT: zext.b a2, a27501; RV64ZVE32F-NEXT: slli a2, a2, 17502; RV64ZVE32F-NEXT: add a2, a0, a27503; RV64ZVE32F-NEXT: lh a2, 0(a2)7504; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma7505; RV64ZVE32F-NEXT: vmv.s.x v10, a27506; RV64ZVE32F-NEXT: vsetivli zero, 6, e16, m1, tu, ma7507; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 57508; RV64ZVE32F-NEXT: .LBB66_12: # %else147509; RV64ZVE32F-NEXT: andi a2, a1, 647510; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma7511; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 27512; RV64ZVE32F-NEXT: beqz a2, .LBB66_147513; RV64ZVE32F-NEXT: # %bb.13: # %cond.load167514; RV64ZVE32F-NEXT: vmv.x.s a2, v87515; RV64ZVE32F-NEXT: zext.b a2, a27516; RV64ZVE32F-NEXT: slli a2, a2, 17517; RV64ZVE32F-NEXT: add a2, a0, a27518; RV64ZVE32F-NEXT: lh a2, 0(a2)7519; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma7520; RV64ZVE32F-NEXT: vmv.s.x v10, a27521; RV64ZVE32F-NEXT: vsetivli zero, 7, e16, m1, tu, ma7522; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 67523; RV64ZVE32F-NEXT: .LBB66_14: # %else177524; RV64ZVE32F-NEXT: andi a1, a1, -1287525; RV64ZVE32F-NEXT: beqz a1, .LBB66_167526; RV64ZVE32F-NEXT: # %bb.15: # %cond.load197527; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma7528; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 17529; RV64ZVE32F-NEXT: vmv.x.s a1, v87530; RV64ZVE32F-NEXT: zext.b a1, a17531; RV64ZVE32F-NEXT: slli a1, a1, 17532; RV64ZVE32F-NEXT: add a0, a0, a17533; RV64ZVE32F-NEXT: lh a0, 0(a0)7534; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma7535; RV64ZVE32F-NEXT: vmv.s.x v8, a07536; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma7537; RV64ZVE32F-NEXT: vslideup.vi v9, v8, 77538; RV64ZVE32F-NEXT: .LBB66_16: # %else207539; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma7540; RV64ZVE32F-NEXT: vmv1r.v v8, v97541; RV64ZVE32F-NEXT: ret7542 %eidxs = zext <8 x i8> %idxs to <8 x i16>7543 %ptrs = getelementptr inbounds bfloat, ptr %base, <8 x i16> %eidxs7544 %v = call <8 x bfloat> @llvm.masked.gather.v8bf16.v8p0(<8 x ptr> %ptrs, i32 2, <8 x i1> %m, <8 x bfloat> %passthru)7545 ret <8 x bfloat> %v7546}7547 7548define <8 x bfloat> @mgather_baseidx_v8bf16(ptr %base, <8 x i16> %idxs, <8 x i1> %m, <8 x bfloat> %passthru) {7549; RV32-LABEL: mgather_baseidx_v8bf16:7550; RV32: # %bb.0:7551; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu7552; RV32-NEXT: vwadd.vv v10, v8, v87553; RV32-NEXT: vluxei32.v v9, (a0), v10, v0.t7554; RV32-NEXT: vmv.v.v v8, v97555; RV32-NEXT: ret7556;7557; RV64V-LABEL: mgather_baseidx_v8bf16:7558; RV64V: # %bb.0:7559; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma7560; RV64V-NEXT: vsext.vf4 v12, v87561; RV64V-NEXT: vadd.vv v12, v12, v127562; RV64V-NEXT: vsetvli zero, zero, e16, m1, ta, mu7563; RV64V-NEXT: vluxei64.v v9, (a0), v12, v0.t7564; RV64V-NEXT: vmv.v.v v8, v97565; RV64V-NEXT: ret7566;7567; RV64ZVE32F-LABEL: mgather_baseidx_v8bf16:7568; RV64ZVE32F: # %bb.0:7569; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma7570; RV64ZVE32F-NEXT: vmv.x.s a1, v07571; RV64ZVE32F-NEXT: andi a2, a1, 17572; RV64ZVE32F-NEXT: beqz a2, .LBB67_27573; RV64ZVE32F-NEXT: # %bb.1: # %cond.load7574; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, tu, ma7575; RV64ZVE32F-NEXT: vmv.x.s a2, v87576; RV64ZVE32F-NEXT: slli a2, a2, 17577; RV64ZVE32F-NEXT: add a2, a0, a27578; RV64ZVE32F-NEXT: lh a2, 0(a2)7579; RV64ZVE32F-NEXT: vmv.s.x v9, a27580; RV64ZVE32F-NEXT: .LBB67_2: # %else7581; RV64ZVE32F-NEXT: andi a2, a1, 27582; RV64ZVE32F-NEXT: beqz a2, .LBB67_47583; RV64ZVE32F-NEXT: # %bb.3: # %cond.load17584; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma7585; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 17586; RV64ZVE32F-NEXT: vmv.x.s a2, v107587; RV64ZVE32F-NEXT: slli a2, a2, 17588; RV64ZVE32F-NEXT: add a2, a0, a27589; RV64ZVE32F-NEXT: lh a2, 0(a2)7590; RV64ZVE32F-NEXT: vmv.s.x v10, a27591; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, m1, tu, ma7592; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 17593; RV64ZVE32F-NEXT: .LBB67_4: # %else27594; RV64ZVE32F-NEXT: andi a2, a1, 47595; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma7596; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 27597; RV64ZVE32F-NEXT: beqz a2, .LBB67_67598; RV64ZVE32F-NEXT: # %bb.5: # %cond.load47599; RV64ZVE32F-NEXT: vmv.x.s a2, v107600; RV64ZVE32F-NEXT: slli a2, a2, 17601; RV64ZVE32F-NEXT: add a2, a0, a27602; RV64ZVE32F-NEXT: lh a2, 0(a2)7603; RV64ZVE32F-NEXT: vmv.s.x v11, a27604; RV64ZVE32F-NEXT: vsetivli zero, 3, e16, m1, tu, ma7605; RV64ZVE32F-NEXT: vslideup.vi v9, v11, 27606; RV64ZVE32F-NEXT: .LBB67_6: # %else57607; RV64ZVE32F-NEXT: andi a2, a1, 87608; RV64ZVE32F-NEXT: beqz a2, .LBB67_87609; RV64ZVE32F-NEXT: # %bb.7: # %cond.load77610; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma7611; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 17612; RV64ZVE32F-NEXT: vmv.x.s a2, v107613; RV64ZVE32F-NEXT: slli a2, a2, 17614; RV64ZVE32F-NEXT: add a2, a0, a27615; RV64ZVE32F-NEXT: lh a2, 0(a2)7616; RV64ZVE32F-NEXT: vmv.s.x v10, a27617; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma7618; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 37619; RV64ZVE32F-NEXT: .LBB67_8: # %else87620; RV64ZVE32F-NEXT: andi a2, a1, 167621; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma7622; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 47623; RV64ZVE32F-NEXT: beqz a2, .LBB67_107624; RV64ZVE32F-NEXT: # %bb.9: # %cond.load107625; RV64ZVE32F-NEXT: vmv.x.s a2, v87626; RV64ZVE32F-NEXT: slli a2, a2, 17627; RV64ZVE32F-NEXT: add a2, a0, a27628; RV64ZVE32F-NEXT: lh a2, 0(a2)7629; RV64ZVE32F-NEXT: vmv.s.x v10, a27630; RV64ZVE32F-NEXT: vsetivli zero, 5, e16, m1, tu, ma7631; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 47632; RV64ZVE32F-NEXT: .LBB67_10: # %else117633; RV64ZVE32F-NEXT: andi a2, a1, 327634; RV64ZVE32F-NEXT: beqz a2, .LBB67_127635; RV64ZVE32F-NEXT: # %bb.11: # %cond.load137636; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma7637; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 17638; RV64ZVE32F-NEXT: vmv.x.s a2, v107639; RV64ZVE32F-NEXT: slli a2, a2, 17640; RV64ZVE32F-NEXT: add a2, a0, a27641; RV64ZVE32F-NEXT: lh a2, 0(a2)7642; RV64ZVE32F-NEXT: vmv.s.x v10, a27643; RV64ZVE32F-NEXT: vsetivli zero, 6, e16, m1, tu, ma7644; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 57645; RV64ZVE32F-NEXT: .LBB67_12: # %else147646; RV64ZVE32F-NEXT: andi a2, a1, 647647; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma7648; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 27649; RV64ZVE32F-NEXT: beqz a2, .LBB67_147650; RV64ZVE32F-NEXT: # %bb.13: # %cond.load167651; RV64ZVE32F-NEXT: vmv.x.s a2, v87652; RV64ZVE32F-NEXT: slli a2, a2, 17653; RV64ZVE32F-NEXT: add a2, a0, a27654; RV64ZVE32F-NEXT: lh a2, 0(a2)7655; RV64ZVE32F-NEXT: vmv.s.x v10, a27656; RV64ZVE32F-NEXT: vsetivli zero, 7, e16, m1, tu, ma7657; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 67658; RV64ZVE32F-NEXT: .LBB67_14: # %else177659; RV64ZVE32F-NEXT: andi a1, a1, -1287660; RV64ZVE32F-NEXT: beqz a1, .LBB67_167661; RV64ZVE32F-NEXT: # %bb.15: # %cond.load197662; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma7663; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 17664; RV64ZVE32F-NEXT: vmv.x.s a1, v87665; RV64ZVE32F-NEXT: slli a1, a1, 17666; RV64ZVE32F-NEXT: add a0, a0, a17667; RV64ZVE32F-NEXT: lh a0, 0(a0)7668; RV64ZVE32F-NEXT: vmv.s.x v8, a07669; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma7670; RV64ZVE32F-NEXT: vslideup.vi v9, v8, 77671; RV64ZVE32F-NEXT: .LBB67_16: # %else207672; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma7673; RV64ZVE32F-NEXT: vmv1r.v v8, v97674; RV64ZVE32F-NEXT: ret7675 %ptrs = getelementptr inbounds bfloat, ptr %base, <8 x i16> %idxs7676 %v = call <8 x bfloat> @llvm.masked.gather.v8bf16.v8p0(<8 x ptr> %ptrs, i32 2, <8 x i1> %m, <8 x bfloat> %passthru)7677 ret <8 x bfloat> %v7678}7679 7680define <1 x half> @mgather_v1f16(<1 x ptr> %ptrs, <1 x i1> %m, <1 x half> %passthru) {7681; RV32V-LABEL: mgather_v1f16:7682; RV32V: # %bb.0:7683; RV32V-NEXT: vsetivli zero, 1, e16, mf4, ta, mu7684; RV32V-NEXT: vluxei32.v v9, (zero), v8, v0.t7685; RV32V-NEXT: vmv1r.v v8, v97686; RV32V-NEXT: ret7687;7688; RV64V-LABEL: mgather_v1f16:7689; RV64V: # %bb.0:7690; RV64V-NEXT: vsetivli zero, 1, e16, mf4, ta, mu7691; RV64V-NEXT: vluxei64.v v9, (zero), v8, v0.t7692; RV64V-NEXT: vmv1r.v v8, v97693; RV64V-NEXT: ret7694;7695; RV32ZVE32F-LABEL: mgather_v1f16:7696; RV32ZVE32F: # %bb.0:7697; RV32ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, mu7698; RV32ZVE32F-NEXT: vluxei32.v v9, (zero), v8, v0.t7699; RV32ZVE32F-NEXT: vmv1r.v v8, v97700; RV32ZVE32F-NEXT: ret7701;7702; RV64ZVE32F-LABEL: mgather_v1f16:7703; RV64ZVE32F: # %bb.0:7704; RV64ZVE32F-NEXT: vsetvli a1, zero, e8, mf4, ta, ma7705; RV64ZVE32F-NEXT: vfirst.m a1, v07706; RV64ZVE32F-NEXT: bnez a1, .LBB68_27707; RV64ZVE32F-NEXT: # %bb.1: # %cond.load7708; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma7709; RV64ZVE32F-NEXT: vle16.v v8, (a0)7710; RV64ZVE32F-NEXT: .LBB68_2: # %else7711; RV64ZVE32F-NEXT: ret7712 %v = call <1 x half> @llvm.masked.gather.v1f16.v1p0(<1 x ptr> %ptrs, i32 2, <1 x i1> %m, <1 x half> %passthru)7713 ret <1 x half> %v7714}7715 7716define <2 x half> @mgather_v2f16(<2 x ptr> %ptrs, <2 x i1> %m, <2 x half> %passthru) {7717; RV32V-LABEL: mgather_v2f16:7718; RV32V: # %bb.0:7719; RV32V-NEXT: vsetivli zero, 2, e16, mf4, ta, mu7720; RV32V-NEXT: vluxei32.v v9, (zero), v8, v0.t7721; RV32V-NEXT: vmv1r.v v8, v97722; RV32V-NEXT: ret7723;7724; RV64V-LABEL: mgather_v2f16:7725; RV64V: # %bb.0:7726; RV64V-NEXT: vsetivli zero, 2, e16, mf4, ta, mu7727; RV64V-NEXT: vluxei64.v v9, (zero), v8, v0.t7728; RV64V-NEXT: vmv1r.v v8, v97729; RV64V-NEXT: ret7730;7731; RV32ZVE32F-LABEL: mgather_v2f16:7732; RV32ZVE32F: # %bb.0:7733; RV32ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, mu7734; RV32ZVE32F-NEXT: vluxei32.v v9, (zero), v8, v0.t7735; RV32ZVE32F-NEXT: vmv1r.v v8, v97736; RV32ZVE32F-NEXT: ret7737;7738; RV64ZVE32F-ZVFH-LABEL: mgather_v2f16:7739; RV64ZVE32F-ZVFH: # %bb.0:7740; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, m1, ta, ma7741; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v07742; RV64ZVE32F-ZVFH-NEXT: andi a3, a2, 17743; RV64ZVE32F-ZVFH-NEXT: bnez a3, .LBB69_37744; RV64ZVE32F-ZVFH-NEXT: # %bb.1: # %else7745; RV64ZVE32F-ZVFH-NEXT: andi a2, a2, 27746; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB69_47747; RV64ZVE32F-ZVFH-NEXT: .LBB69_2: # %else27748; RV64ZVE32F-ZVFH-NEXT: ret7749; RV64ZVE32F-ZVFH-NEXT: .LBB69_3: # %cond.load7750; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a0)7751; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, m2, tu, ma7752; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v8, fa57753; RV64ZVE32F-ZVFH-NEXT: andi a2, a2, 27754; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB69_27755; RV64ZVE32F-ZVFH-NEXT: .LBB69_4: # %cond.load17756; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a1)7757; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, ma7758; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v9, fa57759; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 2, e16, mf2, ta, ma7760; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v8, v9, 17761; RV64ZVE32F-ZVFH-NEXT: ret7762;7763; RV64ZVE32F-ZVFHMIN-LABEL: mgather_v2f16:7764; RV64ZVE32F-ZVFHMIN: # %bb.0:7765; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, m1, ta, ma7766; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v07767; RV64ZVE32F-ZVFHMIN-NEXT: andi a3, a2, 17768; RV64ZVE32F-ZVFHMIN-NEXT: bnez a3, .LBB69_37769; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.1: # %else7770; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a2, 27771; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB69_47772; RV64ZVE32F-ZVFHMIN-NEXT: .LBB69_2: # %else27773; RV64ZVE32F-ZVFHMIN-NEXT: ret7774; RV64ZVE32F-ZVFHMIN-NEXT: .LBB69_3: # %cond.load7775; RV64ZVE32F-ZVFHMIN-NEXT: lh a0, 0(a0)7776; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, tu, ma7777; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v8, a07778; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a2, 27779; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB69_27780; RV64ZVE32F-ZVFHMIN-NEXT: .LBB69_4: # %cond.load17781; RV64ZVE32F-ZVFHMIN-NEXT: lh a0, 0(a1)7782; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma7783; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v9, a07784; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf2, ta, ma7785; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v8, v9, 17786; RV64ZVE32F-ZVFHMIN-NEXT: ret7787 %v = call <2 x half> @llvm.masked.gather.v2f16.v2p0(<2 x ptr> %ptrs, i32 2, <2 x i1> %m, <2 x half> %passthru)7788 ret <2 x half> %v7789}7790 7791define <4 x half> @mgather_v4f16(<4 x ptr> %ptrs, <4 x i1> %m, <4 x half> %passthru) {7792; RV32-LABEL: mgather_v4f16:7793; RV32: # %bb.0:7794; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, mu7795; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t7796; RV32-NEXT: vmv1r.v v8, v97797; RV32-NEXT: ret7798;7799; RV64V-LABEL: mgather_v4f16:7800; RV64V: # %bb.0:7801; RV64V-NEXT: vsetivli zero, 4, e16, mf2, ta, mu7802; RV64V-NEXT: vluxei64.v v10, (zero), v8, v0.t7803; RV64V-NEXT: vmv1r.v v8, v107804; RV64V-NEXT: ret7805;7806; RV64ZVE32F-ZVFH-LABEL: mgather_v4f16:7807; RV64ZVE32F-ZVFH: # %bb.0:7808; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, m1, ta, ma7809; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a1, v07810; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 17811; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB70_57812; RV64ZVE32F-ZVFH-NEXT: # %bb.1: # %else7813; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 27814; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB70_67815; RV64ZVE32F-ZVFH-NEXT: .LBB70_2: # %else27816; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 47817; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB70_77818; RV64ZVE32F-ZVFH-NEXT: .LBB70_3: # %else57819; RV64ZVE32F-ZVFH-NEXT: andi a1, a1, 87820; RV64ZVE32F-ZVFH-NEXT: bnez a1, .LBB70_87821; RV64ZVE32F-ZVFH-NEXT: .LBB70_4: # %else87822; RV64ZVE32F-ZVFH-NEXT: ret7823; RV64ZVE32F-ZVFH-NEXT: .LBB70_5: # %cond.load7824; RV64ZVE32F-ZVFH-NEXT: ld a2, 0(a0)7825; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)7826; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, m2, tu, ma7827; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v8, fa57828; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 27829; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB70_27830; RV64ZVE32F-ZVFH-NEXT: .LBB70_6: # %cond.load17831; RV64ZVE32F-ZVFH-NEXT: ld a2, 8(a0)7832; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)7833; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, ma7834; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v9, fa57835; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 2, e16, mf2, tu, ma7836; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v8, v9, 17837; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 47838; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB70_37839; RV64ZVE32F-ZVFH-NEXT: .LBB70_7: # %cond.load47840; RV64ZVE32F-ZVFH-NEXT: ld a2, 16(a0)7841; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)7842; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 3, e16, mf2, tu, ma7843; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v9, fa57844; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v8, v9, 27845; RV64ZVE32F-ZVFH-NEXT: andi a1, a1, 87846; RV64ZVE32F-ZVFH-NEXT: beqz a1, .LBB70_47847; RV64ZVE32F-ZVFH-NEXT: .LBB70_8: # %cond.load77848; RV64ZVE32F-ZVFH-NEXT: ld a0, 24(a0)7849; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a0)7850; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 4, e16, mf2, ta, ma7851; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v9, fa57852; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v8, v9, 37853; RV64ZVE32F-ZVFH-NEXT: ret7854;7855; RV64ZVE32F-ZVFHMIN-LABEL: mgather_v4f16:7856; RV64ZVE32F-ZVFHMIN: # %bb.0:7857; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, m1, ta, ma7858; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a1, v07859; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 17860; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB70_57861; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.1: # %else7862; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 27863; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB70_67864; RV64ZVE32F-ZVFHMIN-NEXT: .LBB70_2: # %else27865; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 47866; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB70_77867; RV64ZVE32F-ZVFHMIN-NEXT: .LBB70_3: # %else57868; RV64ZVE32F-ZVFHMIN-NEXT: andi a1, a1, 87869; RV64ZVE32F-ZVFHMIN-NEXT: bnez a1, .LBB70_87870; RV64ZVE32F-ZVFHMIN-NEXT: .LBB70_4: # %else87871; RV64ZVE32F-ZVFHMIN-NEXT: ret7872; RV64ZVE32F-ZVFHMIN-NEXT: .LBB70_5: # %cond.load7873; RV64ZVE32F-ZVFHMIN-NEXT: ld a2, 0(a0)7874; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)7875; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, tu, ma7876; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v8, a27877; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 27878; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB70_27879; RV64ZVE32F-ZVFHMIN-NEXT: .LBB70_6: # %cond.load17880; RV64ZVE32F-ZVFHMIN-NEXT: ld a2, 8(a0)7881; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)7882; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma7883; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v9, a27884; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf2, tu, ma7885; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v8, v9, 17886; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 47887; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB70_37888; RV64ZVE32F-ZVFHMIN-NEXT: .LBB70_7: # %cond.load47889; RV64ZVE32F-ZVFHMIN-NEXT: ld a2, 16(a0)7890; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)7891; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 3, e16, mf2, tu, ma7892; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v9, a27893; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v8, v9, 27894; RV64ZVE32F-ZVFHMIN-NEXT: andi a1, a1, 87895; RV64ZVE32F-ZVFHMIN-NEXT: beqz a1, .LBB70_47896; RV64ZVE32F-ZVFHMIN-NEXT: .LBB70_8: # %cond.load77897; RV64ZVE32F-ZVFHMIN-NEXT: ld a0, 24(a0)7898; RV64ZVE32F-ZVFHMIN-NEXT: lh a0, 0(a0)7899; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma7900; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v9, a07901; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v8, v9, 37902; RV64ZVE32F-ZVFHMIN-NEXT: ret7903 %v = call <4 x half> @llvm.masked.gather.v4f16.v4p0(<4 x ptr> %ptrs, i32 2, <4 x i1> %m, <4 x half> %passthru)7904 ret <4 x half> %v7905}7906 7907define <4 x half> @mgather_truemask_v4f16(<4 x ptr> %ptrs, <4 x half> %passthru) {7908; RV32-LABEL: mgather_truemask_v4f16:7909; RV32: # %bb.0:7910; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma7911; RV32-NEXT: vluxei32.v v9, (zero), v87912; RV32-NEXT: vmv1r.v v8, v97913; RV32-NEXT: ret7914;7915; RV64V-LABEL: mgather_truemask_v4f16:7916; RV64V: # %bb.0:7917; RV64V-NEXT: vsetivli zero, 4, e16, mf2, ta, ma7918; RV64V-NEXT: vluxei64.v v10, (zero), v87919; RV64V-NEXT: vmv1r.v v8, v107920; RV64V-NEXT: ret7921;7922; RV64ZVE32F-ZVFH-LABEL: mgather_truemask_v4f16:7923; RV64ZVE32F-ZVFH: # %bb.0:7924; RV64ZVE32F-ZVFH-NEXT: ld a1, 0(a0)7925; RV64ZVE32F-ZVFH-NEXT: ld a2, 8(a0)7926; RV64ZVE32F-ZVFH-NEXT: ld a3, 16(a0)7927; RV64ZVE32F-ZVFH-NEXT: ld a0, 24(a0)7928; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a1)7929; RV64ZVE32F-ZVFH-NEXT: flh fa4, 0(a2)7930; RV64ZVE32F-ZVFH-NEXT: flh fa3, 0(a3)7931; RV64ZVE32F-ZVFH-NEXT: flh fa2, 0(a0)7932; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 4, e16, mf2, ta, ma7933; RV64ZVE32F-ZVFH-NEXT: vfmv.v.f v8, fa57934; RV64ZVE32F-ZVFH-NEXT: vfslide1down.vf v8, v8, fa47935; RV64ZVE32F-ZVFH-NEXT: vfslide1down.vf v8, v8, fa37936; RV64ZVE32F-ZVFH-NEXT: vfslide1down.vf v8, v8, fa27937; RV64ZVE32F-ZVFH-NEXT: ret7938;7939; RV64ZVE32F-ZVFHMIN-LABEL: mgather_truemask_v4f16:7940; RV64ZVE32F-ZVFHMIN: # %bb.0:7941; RV64ZVE32F-ZVFHMIN-NEXT: ld a1, 0(a0)7942; RV64ZVE32F-ZVFHMIN-NEXT: ld a2, 8(a0)7943; RV64ZVE32F-ZVFHMIN-NEXT: ld a3, 16(a0)7944; RV64ZVE32F-ZVFHMIN-NEXT: ld a0, 24(a0)7945; RV64ZVE32F-ZVFHMIN-NEXT: lh a1, 0(a1)7946; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)7947; RV64ZVE32F-ZVFHMIN-NEXT: lh a3, 0(a3)7948; RV64ZVE32F-ZVFHMIN-NEXT: lh a0, 0(a0)7949; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma7950; RV64ZVE32F-ZVFHMIN-NEXT: vmv.v.x v8, a17951; RV64ZVE32F-ZVFHMIN-NEXT: vslide1down.vx v8, v8, a27952; RV64ZVE32F-ZVFHMIN-NEXT: vslide1down.vx v8, v8, a37953; RV64ZVE32F-ZVFHMIN-NEXT: vslide1down.vx v8, v8, a07954; RV64ZVE32F-ZVFHMIN-NEXT: ret7955 %v = call <4 x half> @llvm.masked.gather.v4f16.v4p0(<4 x ptr> %ptrs, i32 2, <4 x i1> splat (i1 1), <4 x half> %passthru)7956 ret <4 x half> %v7957}7958 7959define <4 x half> @mgather_falsemask_v4f16(<4 x ptr> %ptrs, <4 x half> %passthru) {7960; RV32-LABEL: mgather_falsemask_v4f16:7961; RV32: # %bb.0:7962; RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma7963; RV32-NEXT: vmv1r.v v8, v97964; RV32-NEXT: ret7965;7966; RV64V-LABEL: mgather_falsemask_v4f16:7967; RV64V: # %bb.0:7968; RV64V-NEXT: vsetivli zero, 1, e8, m1, ta, ma7969; RV64V-NEXT: vmv1r.v v8, v107970; RV64V-NEXT: ret7971;7972; RV64ZVE32F-LABEL: mgather_falsemask_v4f16:7973; RV64ZVE32F: # %bb.0:7974; RV64ZVE32F-NEXT: ret7975 %v = call <4 x half> @llvm.masked.gather.v4f16.v4p0(<4 x ptr> %ptrs, i32 2, <4 x i1> zeroinitializer, <4 x half> %passthru)7976 ret <4 x half> %v7977}7978 7979define <8 x half> @mgather_v8f16(<8 x ptr> %ptrs, <8 x i1> %m, <8 x half> %passthru) {7980; RV32-LABEL: mgather_v8f16:7981; RV32: # %bb.0:7982; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu7983; RV32-NEXT: vluxei32.v v10, (zero), v8, v0.t7984; RV32-NEXT: vmv.v.v v8, v107985; RV32-NEXT: ret7986;7987; RV64V-LABEL: mgather_v8f16:7988; RV64V: # %bb.0:7989; RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, mu7990; RV64V-NEXT: vluxei64.v v12, (zero), v8, v0.t7991; RV64V-NEXT: vmv.v.v v8, v127992; RV64V-NEXT: ret7993;7994; RV64ZVE32F-ZVFH-LABEL: mgather_v8f16:7995; RV64ZVE32F-ZVFH: # %bb.0:7996; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, m1, ta, ma7997; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a1, v07998; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 17999; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB73_98000; RV64ZVE32F-ZVFH-NEXT: # %bb.1: # %else8001; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 28002; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB73_108003; RV64ZVE32F-ZVFH-NEXT: .LBB73_2: # %else28004; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 48005; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB73_118006; RV64ZVE32F-ZVFH-NEXT: .LBB73_3: # %else58007; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 88008; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB73_128009; RV64ZVE32F-ZVFH-NEXT: .LBB73_4: # %else88010; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 168011; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB73_138012; RV64ZVE32F-ZVFH-NEXT: .LBB73_5: # %else118013; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 328014; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB73_148015; RV64ZVE32F-ZVFH-NEXT: .LBB73_6: # %else148016; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 648017; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB73_158018; RV64ZVE32F-ZVFH-NEXT: .LBB73_7: # %else178019; RV64ZVE32F-ZVFH-NEXT: andi a1, a1, -1288020; RV64ZVE32F-ZVFH-NEXT: bnez a1, .LBB73_168021; RV64ZVE32F-ZVFH-NEXT: .LBB73_8: # %else208022; RV64ZVE32F-ZVFH-NEXT: ret8023; RV64ZVE32F-ZVFH-NEXT: .LBB73_9: # %cond.load8024; RV64ZVE32F-ZVFH-NEXT: ld a2, 0(a0)8025; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)8026; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, m2, tu, ma8027; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v8, fa58028; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 28029; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB73_28030; RV64ZVE32F-ZVFH-NEXT: .LBB73_10: # %cond.load18031; RV64ZVE32F-ZVFH-NEXT: ld a2, 8(a0)8032; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)8033; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, ma8034; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v9, fa58035; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 2, e16, m1, tu, ma8036; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v8, v9, 18037; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 48038; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB73_38039; RV64ZVE32F-ZVFH-NEXT: .LBB73_11: # %cond.load48040; RV64ZVE32F-ZVFH-NEXT: ld a2, 16(a0)8041; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)8042; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 3, e16, m1, tu, ma8043; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v9, fa58044; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v8, v9, 28045; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 88046; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB73_48047; RV64ZVE32F-ZVFH-NEXT: .LBB73_12: # %cond.load78048; RV64ZVE32F-ZVFH-NEXT: ld a2, 24(a0)8049; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)8050; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 4, e16, m1, tu, ma8051; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v9, fa58052; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v8, v9, 38053; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 168054; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB73_58055; RV64ZVE32F-ZVFH-NEXT: .LBB73_13: # %cond.load108056; RV64ZVE32F-ZVFH-NEXT: ld a2, 32(a0)8057; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)8058; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 5, e16, m1, tu, ma8059; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v9, fa58060; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v8, v9, 48061; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 328062; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB73_68063; RV64ZVE32F-ZVFH-NEXT: .LBB73_14: # %cond.load138064; RV64ZVE32F-ZVFH-NEXT: ld a2, 40(a0)8065; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)8066; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 6, e16, m1, tu, ma8067; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v9, fa58068; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v8, v9, 58069; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 648070; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB73_78071; RV64ZVE32F-ZVFH-NEXT: .LBB73_15: # %cond.load168072; RV64ZVE32F-ZVFH-NEXT: ld a2, 48(a0)8073; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)8074; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 7, e16, m1, tu, ma8075; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v9, fa58076; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v8, v9, 68077; RV64ZVE32F-ZVFH-NEXT: andi a1, a1, -1288078; RV64ZVE32F-ZVFH-NEXT: beqz a1, .LBB73_88079; RV64ZVE32F-ZVFH-NEXT: .LBB73_16: # %cond.load198080; RV64ZVE32F-ZVFH-NEXT: ld a0, 56(a0)8081; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a0)8082; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma8083; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v9, fa58084; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v8, v9, 78085; RV64ZVE32F-ZVFH-NEXT: ret8086;8087; RV64ZVE32F-ZVFHMIN-LABEL: mgather_v8f16:8088; RV64ZVE32F-ZVFHMIN: # %bb.0:8089; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, m1, ta, ma8090; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a1, v08091; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 18092; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB73_98093; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.1: # %else8094; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 28095; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB73_108096; RV64ZVE32F-ZVFHMIN-NEXT: .LBB73_2: # %else28097; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 48098; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB73_118099; RV64ZVE32F-ZVFHMIN-NEXT: .LBB73_3: # %else58100; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 88101; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB73_128102; RV64ZVE32F-ZVFHMIN-NEXT: .LBB73_4: # %else88103; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 168104; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB73_138105; RV64ZVE32F-ZVFHMIN-NEXT: .LBB73_5: # %else118106; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 328107; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB73_148108; RV64ZVE32F-ZVFHMIN-NEXT: .LBB73_6: # %else148109; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 648110; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB73_158111; RV64ZVE32F-ZVFHMIN-NEXT: .LBB73_7: # %else178112; RV64ZVE32F-ZVFHMIN-NEXT: andi a1, a1, -1288113; RV64ZVE32F-ZVFHMIN-NEXT: bnez a1, .LBB73_168114; RV64ZVE32F-ZVFHMIN-NEXT: .LBB73_8: # %else208115; RV64ZVE32F-ZVFHMIN-NEXT: ret8116; RV64ZVE32F-ZVFHMIN-NEXT: .LBB73_9: # %cond.load8117; RV64ZVE32F-ZVFHMIN-NEXT: ld a2, 0(a0)8118; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)8119; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, tu, ma8120; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v8, a28121; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 28122; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB73_28123; RV64ZVE32F-ZVFHMIN-NEXT: .LBB73_10: # %cond.load18124; RV64ZVE32F-ZVFHMIN-NEXT: ld a2, 8(a0)8125; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)8126; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma8127; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v9, a28128; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e16, m1, tu, ma8129; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v8, v9, 18130; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 48131; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB73_38132; RV64ZVE32F-ZVFHMIN-NEXT: .LBB73_11: # %cond.load48133; RV64ZVE32F-ZVFHMIN-NEXT: ld a2, 16(a0)8134; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)8135; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 3, e16, m1, tu, ma8136; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v9, a28137; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v8, v9, 28138; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 88139; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB73_48140; RV64ZVE32F-ZVFHMIN-NEXT: .LBB73_12: # %cond.load78141; RV64ZVE32F-ZVFHMIN-NEXT: ld a2, 24(a0)8142; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)8143; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 4, e16, m1, tu, ma8144; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v9, a28145; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v8, v9, 38146; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 168147; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB73_58148; RV64ZVE32F-ZVFHMIN-NEXT: .LBB73_13: # %cond.load108149; RV64ZVE32F-ZVFHMIN-NEXT: ld a2, 32(a0)8150; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)8151; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 5, e16, m1, tu, ma8152; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v9, a28153; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v8, v9, 48154; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 328155; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB73_68156; RV64ZVE32F-ZVFHMIN-NEXT: .LBB73_14: # %cond.load138157; RV64ZVE32F-ZVFHMIN-NEXT: ld a2, 40(a0)8158; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)8159; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, tu, ma8160; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v9, a28161; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v8, v9, 58162; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 648163; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB73_78164; RV64ZVE32F-ZVFHMIN-NEXT: .LBB73_15: # %cond.load168165; RV64ZVE32F-ZVFHMIN-NEXT: ld a2, 48(a0)8166; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)8167; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 7, e16, m1, tu, ma8168; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v9, a28169; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v8, v9, 68170; RV64ZVE32F-ZVFHMIN-NEXT: andi a1, a1, -1288171; RV64ZVE32F-ZVFHMIN-NEXT: beqz a1, .LBB73_88172; RV64ZVE32F-ZVFHMIN-NEXT: .LBB73_16: # %cond.load198173; RV64ZVE32F-ZVFHMIN-NEXT: ld a0, 56(a0)8174; RV64ZVE32F-ZVFHMIN-NEXT: lh a0, 0(a0)8175; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma8176; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v9, a08177; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v8, v9, 78178; RV64ZVE32F-ZVFHMIN-NEXT: ret8179 %v = call <8 x half> @llvm.masked.gather.v8f16.v8p0(<8 x ptr> %ptrs, i32 2, <8 x i1> %m, <8 x half> %passthru)8180 ret <8 x half> %v8181}8182 8183define <8 x half> @mgather_baseidx_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8 x i1> %m, <8 x half> %passthru) {8184; RV32-LABEL: mgather_baseidx_v8i8_v8f16:8185; RV32: # %bb.0:8186; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma8187; RV32-NEXT: vsext.vf4 v10, v88188; RV32-NEXT: vadd.vv v10, v10, v108189; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu8190; RV32-NEXT: vluxei32.v v9, (a0), v10, v0.t8191; RV32-NEXT: vmv.v.v v8, v98192; RV32-NEXT: ret8193;8194; RV64V-LABEL: mgather_baseidx_v8i8_v8f16:8195; RV64V: # %bb.0:8196; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma8197; RV64V-NEXT: vsext.vf8 v12, v88198; RV64V-NEXT: vadd.vv v12, v12, v128199; RV64V-NEXT: vsetvli zero, zero, e16, m1, ta, mu8200; RV64V-NEXT: vluxei64.v v9, (a0), v12, v0.t8201; RV64V-NEXT: vmv.v.v v8, v98202; RV64V-NEXT: ret8203;8204; RV64ZVE32F-ZVFH-LABEL: mgather_baseidx_v8i8_v8f16:8205; RV64ZVE32F-ZVFH: # %bb.0:8206; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, m1, ta, ma8207; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a1, v08208; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 18209; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB74_28210; RV64ZVE32F-ZVFH-NEXT: # %bb.1: # %cond.load8211; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v88212; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 18213; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a28214; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)8215; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, m2, tu, ma8216; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v9, fa58217; RV64ZVE32F-ZVFH-NEXT: .LBB74_2: # %else8218; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 28219; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB74_48220; RV64ZVE32F-ZVFH-NEXT: # %bb.3: # %cond.load18221; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, mf4, ta, ma8222; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 18223; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v108224; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 18225; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a28226; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)8227; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma8228; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa58229; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 2, e16, m1, tu, ma8230; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 18231; RV64ZVE32F-ZVFH-NEXT: .LBB74_4: # %else28232; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 48233; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 2, e8, mf4, ta, ma8234; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 28235; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB74_68236; RV64ZVE32F-ZVFH-NEXT: # %bb.5: # %cond.load48237; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v108238; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 18239; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a28240; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)8241; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma8242; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v11, fa58243; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 3, e16, m1, tu, ma8244; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v11, 28245; RV64ZVE32F-ZVFH-NEXT: .LBB74_6: # %else58246; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 88247; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB74_88248; RV64ZVE32F-ZVFH-NEXT: # %bb.7: # %cond.load78249; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, mf4, ta, ma8250; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v10, 18251; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v108252; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 18253; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a28254; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)8255; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma8256; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa58257; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 4, e16, m1, tu, ma8258; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 38259; RV64ZVE32F-ZVFH-NEXT: .LBB74_8: # %else88260; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 168261; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 4, e8, mf2, ta, ma8262; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v8, v8, 48263; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB74_108264; RV64ZVE32F-ZVFH-NEXT: # %bb.9: # %cond.load108265; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v88266; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 18267; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a28268; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)8269; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, ma8270; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa58271; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 5, e16, m1, tu, ma8272; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 48273; RV64ZVE32F-ZVFH-NEXT: .LBB74_10: # %else118274; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 328275; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB74_128276; RV64ZVE32F-ZVFH-NEXT: # %bb.11: # %cond.load138277; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, mf4, ta, ma8278; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 18279; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v108280; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 18281; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a28282; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)8283; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma8284; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa58285; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 6, e16, m1, tu, ma8286; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 58287; RV64ZVE32F-ZVFH-NEXT: .LBB74_12: # %else148288; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 648289; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 2, e8, mf4, ta, ma8290; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v8, v8, 28291; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB74_148292; RV64ZVE32F-ZVFH-NEXT: # %bb.13: # %cond.load168293; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v88294; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 18295; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a28296; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)8297; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma8298; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa58299; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 7, e16, m1, tu, ma8300; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 68301; RV64ZVE32F-ZVFH-NEXT: .LBB74_14: # %else178302; RV64ZVE32F-ZVFH-NEXT: andi a1, a1, -1288303; RV64ZVE32F-ZVFH-NEXT: beqz a1, .LBB74_168304; RV64ZVE32F-ZVFH-NEXT: # %bb.15: # %cond.load198305; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, mf4, ta, ma8306; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v8, v8, 18307; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a1, v88308; RV64ZVE32F-ZVFH-NEXT: slli a1, a1, 18309; RV64ZVE32F-ZVFH-NEXT: add a0, a0, a18310; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a0)8311; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma8312; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v8, fa58313; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma8314; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v8, 78315; RV64ZVE32F-ZVFH-NEXT: .LBB74_16: # %else208316; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, m1, ta, ma8317; RV64ZVE32F-ZVFH-NEXT: vmv1r.v v8, v98318; RV64ZVE32F-ZVFH-NEXT: ret8319;8320; RV64ZVE32F-ZVFHMIN-LABEL: mgather_baseidx_v8i8_v8f16:8321; RV64ZVE32F-ZVFHMIN: # %bb.0:8322; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, m1, ta, ma8323; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a1, v08324; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 18325; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB74_28326; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.1: # %cond.load8327; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v88328; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 18329; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a28330; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)8331; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, tu, ma8332; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v9, a28333; RV64ZVE32F-ZVFHMIN-NEXT: .LBB74_2: # %else8334; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 28335; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB74_48336; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.3: # %cond.load18337; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, mf4, ta, ma8338; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 18339; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v108340; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 18341; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a28342; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)8343; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma8344; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a28345; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e16, m1, tu, ma8346; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 18347; RV64ZVE32F-ZVFHMIN-NEXT: .LBB74_4: # %else28348; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 48349; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e8, mf4, ta, ma8350; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 28351; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB74_68352; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.5: # %cond.load48353; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v108354; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 18355; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a28356; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)8357; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma8358; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v11, a28359; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 3, e16, m1, tu, ma8360; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v11, 28361; RV64ZVE32F-ZVFHMIN-NEXT: .LBB74_6: # %else58362; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 88363; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB74_88364; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.7: # %cond.load78365; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, mf4, ta, ma8366; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v10, 18367; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v108368; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 18369; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a28370; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)8371; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma8372; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a28373; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 4, e16, m1, tu, ma8374; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 38375; RV64ZVE32F-ZVFHMIN-NEXT: .LBB74_8: # %else88376; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 168377; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 4, e8, mf2, ta, ma8378; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v8, v8, 48379; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB74_108380; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.9: # %cond.load108381; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v88382; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 18383; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a28384; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)8385; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma8386; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a28387; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 5, e16, m1, tu, ma8388; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 48389; RV64ZVE32F-ZVFHMIN-NEXT: .LBB74_10: # %else118390; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 328391; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB74_128392; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.11: # %cond.load138393; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, mf4, ta, ma8394; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 18395; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v108396; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 18397; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a28398; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)8399; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma8400; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a28401; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, tu, ma8402; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 58403; RV64ZVE32F-ZVFHMIN-NEXT: .LBB74_12: # %else148404; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 648405; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e8, mf4, ta, ma8406; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v8, v8, 28407; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB74_148408; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.13: # %cond.load168409; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v88410; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 18411; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a28412; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)8413; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma8414; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a28415; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 7, e16, m1, tu, ma8416; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 68417; RV64ZVE32F-ZVFHMIN-NEXT: .LBB74_14: # %else178418; RV64ZVE32F-ZVFHMIN-NEXT: andi a1, a1, -1288419; RV64ZVE32F-ZVFHMIN-NEXT: beqz a1, .LBB74_168420; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.15: # %cond.load198421; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, mf4, ta, ma8422; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v8, v8, 18423; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a1, v88424; RV64ZVE32F-ZVFHMIN-NEXT: slli a1, a1, 18425; RV64ZVE32F-ZVFHMIN-NEXT: add a0, a0, a18426; RV64ZVE32F-ZVFHMIN-NEXT: lh a0, 0(a0)8427; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma8428; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v8, a08429; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma8430; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v8, 78431; RV64ZVE32F-ZVFHMIN-NEXT: .LBB74_16: # %else208432; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, m1, ta, ma8433; RV64ZVE32F-ZVFHMIN-NEXT: vmv1r.v v8, v98434; RV64ZVE32F-ZVFHMIN-NEXT: ret8435 %ptrs = getelementptr inbounds half, ptr %base, <8 x i8> %idxs8436 %v = call <8 x half> @llvm.masked.gather.v8f16.v8p0(<8 x ptr> %ptrs, i32 2, <8 x i1> %m, <8 x half> %passthru)8437 ret <8 x half> %v8438}8439 8440define <8 x half> @mgather_baseidx_sext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8 x i1> %m, <8 x half> %passthru) {8441; RV32-LABEL: mgather_baseidx_sext_v8i8_v8f16:8442; RV32: # %bb.0:8443; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma8444; RV32-NEXT: vsext.vf4 v10, v88445; RV32-NEXT: vadd.vv v10, v10, v108446; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu8447; RV32-NEXT: vluxei32.v v9, (a0), v10, v0.t8448; RV32-NEXT: vmv.v.v v8, v98449; RV32-NEXT: ret8450;8451; RV64V-LABEL: mgather_baseidx_sext_v8i8_v8f16:8452; RV64V: # %bb.0:8453; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma8454; RV64V-NEXT: vsext.vf8 v12, v88455; RV64V-NEXT: vadd.vv v12, v12, v128456; RV64V-NEXT: vsetvli zero, zero, e16, m1, ta, mu8457; RV64V-NEXT: vluxei64.v v9, (a0), v12, v0.t8458; RV64V-NEXT: vmv.v.v v8, v98459; RV64V-NEXT: ret8460;8461; RV64ZVE32F-ZVFH-LABEL: mgather_baseidx_sext_v8i8_v8f16:8462; RV64ZVE32F-ZVFH: # %bb.0:8463; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, m1, ta, ma8464; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a1, v08465; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 18466; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB75_28467; RV64ZVE32F-ZVFH-NEXT: # %bb.1: # %cond.load8468; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v88469; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 18470; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a28471; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)8472; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, m2, tu, ma8473; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v9, fa58474; RV64ZVE32F-ZVFH-NEXT: .LBB75_2: # %else8475; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 28476; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB75_48477; RV64ZVE32F-ZVFH-NEXT: # %bb.3: # %cond.load18478; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, mf4, ta, ma8479; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 18480; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v108481; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 18482; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a28483; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)8484; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma8485; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa58486; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 2, e16, m1, tu, ma8487; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 18488; RV64ZVE32F-ZVFH-NEXT: .LBB75_4: # %else28489; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 48490; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 2, e8, mf4, ta, ma8491; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 28492; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB75_68493; RV64ZVE32F-ZVFH-NEXT: # %bb.5: # %cond.load48494; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v108495; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 18496; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a28497; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)8498; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma8499; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v11, fa58500; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 3, e16, m1, tu, ma8501; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v11, 28502; RV64ZVE32F-ZVFH-NEXT: .LBB75_6: # %else58503; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 88504; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB75_88505; RV64ZVE32F-ZVFH-NEXT: # %bb.7: # %cond.load78506; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, mf4, ta, ma8507; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v10, 18508; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v108509; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 18510; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a28511; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)8512; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma8513; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa58514; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 4, e16, m1, tu, ma8515; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 38516; RV64ZVE32F-ZVFH-NEXT: .LBB75_8: # %else88517; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 168518; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 4, e8, mf2, ta, ma8519; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v8, v8, 48520; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB75_108521; RV64ZVE32F-ZVFH-NEXT: # %bb.9: # %cond.load108522; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v88523; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 18524; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a28525; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)8526; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, ma8527; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa58528; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 5, e16, m1, tu, ma8529; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 48530; RV64ZVE32F-ZVFH-NEXT: .LBB75_10: # %else118531; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 328532; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB75_128533; RV64ZVE32F-ZVFH-NEXT: # %bb.11: # %cond.load138534; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, mf4, ta, ma8535; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 18536; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v108537; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 18538; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a28539; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)8540; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma8541; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa58542; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 6, e16, m1, tu, ma8543; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 58544; RV64ZVE32F-ZVFH-NEXT: .LBB75_12: # %else148545; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 648546; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 2, e8, mf4, ta, ma8547; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v8, v8, 28548; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB75_148549; RV64ZVE32F-ZVFH-NEXT: # %bb.13: # %cond.load168550; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v88551; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 18552; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a28553; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)8554; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma8555; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa58556; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 7, e16, m1, tu, ma8557; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 68558; RV64ZVE32F-ZVFH-NEXT: .LBB75_14: # %else178559; RV64ZVE32F-ZVFH-NEXT: andi a1, a1, -1288560; RV64ZVE32F-ZVFH-NEXT: beqz a1, .LBB75_168561; RV64ZVE32F-ZVFH-NEXT: # %bb.15: # %cond.load198562; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, mf4, ta, ma8563; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v8, v8, 18564; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a1, v88565; RV64ZVE32F-ZVFH-NEXT: slli a1, a1, 18566; RV64ZVE32F-ZVFH-NEXT: add a0, a0, a18567; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a0)8568; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma8569; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v8, fa58570; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma8571; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v8, 78572; RV64ZVE32F-ZVFH-NEXT: .LBB75_16: # %else208573; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, m1, ta, ma8574; RV64ZVE32F-ZVFH-NEXT: vmv1r.v v8, v98575; RV64ZVE32F-ZVFH-NEXT: ret8576;8577; RV64ZVE32F-ZVFHMIN-LABEL: mgather_baseidx_sext_v8i8_v8f16:8578; RV64ZVE32F-ZVFHMIN: # %bb.0:8579; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, m1, ta, ma8580; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a1, v08581; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 18582; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB75_28583; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.1: # %cond.load8584; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v88585; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 18586; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a28587; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)8588; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, tu, ma8589; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v9, a28590; RV64ZVE32F-ZVFHMIN-NEXT: .LBB75_2: # %else8591; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 28592; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB75_48593; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.3: # %cond.load18594; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, mf4, ta, ma8595; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 18596; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v108597; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 18598; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a28599; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)8600; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma8601; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a28602; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e16, m1, tu, ma8603; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 18604; RV64ZVE32F-ZVFHMIN-NEXT: .LBB75_4: # %else28605; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 48606; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e8, mf4, ta, ma8607; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 28608; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB75_68609; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.5: # %cond.load48610; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v108611; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 18612; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a28613; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)8614; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma8615; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v11, a28616; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 3, e16, m1, tu, ma8617; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v11, 28618; RV64ZVE32F-ZVFHMIN-NEXT: .LBB75_6: # %else58619; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 88620; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB75_88621; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.7: # %cond.load78622; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, mf4, ta, ma8623; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v10, 18624; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v108625; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 18626; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a28627; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)8628; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma8629; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a28630; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 4, e16, m1, tu, ma8631; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 38632; RV64ZVE32F-ZVFHMIN-NEXT: .LBB75_8: # %else88633; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 168634; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 4, e8, mf2, ta, ma8635; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v8, v8, 48636; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB75_108637; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.9: # %cond.load108638; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v88639; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 18640; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a28641; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)8642; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma8643; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a28644; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 5, e16, m1, tu, ma8645; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 48646; RV64ZVE32F-ZVFHMIN-NEXT: .LBB75_10: # %else118647; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 328648; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB75_128649; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.11: # %cond.load138650; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, mf4, ta, ma8651; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 18652; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v108653; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 18654; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a28655; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)8656; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma8657; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a28658; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, tu, ma8659; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 58660; RV64ZVE32F-ZVFHMIN-NEXT: .LBB75_12: # %else148661; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 648662; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e8, mf4, ta, ma8663; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v8, v8, 28664; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB75_148665; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.13: # %cond.load168666; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v88667; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 18668; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a28669; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)8670; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma8671; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a28672; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 7, e16, m1, tu, ma8673; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 68674; RV64ZVE32F-ZVFHMIN-NEXT: .LBB75_14: # %else178675; RV64ZVE32F-ZVFHMIN-NEXT: andi a1, a1, -1288676; RV64ZVE32F-ZVFHMIN-NEXT: beqz a1, .LBB75_168677; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.15: # %cond.load198678; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, mf4, ta, ma8679; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v8, v8, 18680; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a1, v88681; RV64ZVE32F-ZVFHMIN-NEXT: slli a1, a1, 18682; RV64ZVE32F-ZVFHMIN-NEXT: add a0, a0, a18683; RV64ZVE32F-ZVFHMIN-NEXT: lh a0, 0(a0)8684; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma8685; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v8, a08686; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma8687; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v8, 78688; RV64ZVE32F-ZVFHMIN-NEXT: .LBB75_16: # %else208689; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, m1, ta, ma8690; RV64ZVE32F-ZVFHMIN-NEXT: vmv1r.v v8, v98691; RV64ZVE32F-ZVFHMIN-NEXT: ret8692 %eidxs = sext <8 x i8> %idxs to <8 x i16>8693 %ptrs = getelementptr inbounds half, ptr %base, <8 x i16> %eidxs8694 %v = call <8 x half> @llvm.masked.gather.v8f16.v8p0(<8 x ptr> %ptrs, i32 2, <8 x i1> %m, <8 x half> %passthru)8695 ret <8 x half> %v8696}8697 8698define <8 x half> @mgather_baseidx_zext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8 x i1> %m, <8 x half> %passthru) {8699; RV32-LABEL: mgather_baseidx_zext_v8i8_v8f16:8700; RV32: # %bb.0:8701; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma8702; RV32-NEXT: vwaddu.vv v10, v8, v88703; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu8704; RV32-NEXT: vluxei16.v v9, (a0), v10, v0.t8705; RV32-NEXT: vmv.v.v v8, v98706; RV32-NEXT: ret8707;8708; RV64V-LABEL: mgather_baseidx_zext_v8i8_v8f16:8709; RV64V: # %bb.0:8710; RV64V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma8711; RV64V-NEXT: vwaddu.vv v10, v8, v88712; RV64V-NEXT: vsetvli zero, zero, e16, m1, ta, mu8713; RV64V-NEXT: vluxei16.v v9, (a0), v10, v0.t8714; RV64V-NEXT: vmv.v.v v8, v98715; RV64V-NEXT: ret8716;8717; RV64ZVE32F-ZVFH-LABEL: mgather_baseidx_zext_v8i8_v8f16:8718; RV64ZVE32F-ZVFH: # %bb.0:8719; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, m1, ta, ma8720; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a1, v08721; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 18722; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB76_28723; RV64ZVE32F-ZVFH-NEXT: # %bb.1: # %cond.load8724; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v88725; RV64ZVE32F-ZVFH-NEXT: zext.b a2, a28726; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 18727; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a28728; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)8729; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, m2, tu, ma8730; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v9, fa58731; RV64ZVE32F-ZVFH-NEXT: .LBB76_2: # %else8732; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 28733; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB76_48734; RV64ZVE32F-ZVFH-NEXT: # %bb.3: # %cond.load18735; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, mf4, ta, ma8736; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 18737; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v108738; RV64ZVE32F-ZVFH-NEXT: zext.b a2, a28739; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 18740; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a28741; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)8742; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma8743; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa58744; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 2, e16, m1, tu, ma8745; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 18746; RV64ZVE32F-ZVFH-NEXT: .LBB76_4: # %else28747; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 48748; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 2, e8, mf4, ta, ma8749; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 28750; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB76_68751; RV64ZVE32F-ZVFH-NEXT: # %bb.5: # %cond.load48752; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v108753; RV64ZVE32F-ZVFH-NEXT: zext.b a2, a28754; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 18755; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a28756; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)8757; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma8758; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v11, fa58759; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 3, e16, m1, tu, ma8760; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v11, 28761; RV64ZVE32F-ZVFH-NEXT: .LBB76_6: # %else58762; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 88763; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB76_88764; RV64ZVE32F-ZVFH-NEXT: # %bb.7: # %cond.load78765; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, mf4, ta, ma8766; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v10, 18767; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v108768; RV64ZVE32F-ZVFH-NEXT: zext.b a2, a28769; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 18770; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a28771; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)8772; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma8773; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa58774; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 4, e16, m1, tu, ma8775; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 38776; RV64ZVE32F-ZVFH-NEXT: .LBB76_8: # %else88777; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 168778; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 4, e8, mf2, ta, ma8779; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v8, v8, 48780; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB76_108781; RV64ZVE32F-ZVFH-NEXT: # %bb.9: # %cond.load108782; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v88783; RV64ZVE32F-ZVFH-NEXT: zext.b a2, a28784; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 18785; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a28786; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)8787; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, ma8788; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa58789; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 5, e16, m1, tu, ma8790; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 48791; RV64ZVE32F-ZVFH-NEXT: .LBB76_10: # %else118792; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 328793; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB76_128794; RV64ZVE32F-ZVFH-NEXT: # %bb.11: # %cond.load138795; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, mf4, ta, ma8796; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 18797; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v108798; RV64ZVE32F-ZVFH-NEXT: zext.b a2, a28799; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 18800; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a28801; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)8802; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma8803; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa58804; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 6, e16, m1, tu, ma8805; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 58806; RV64ZVE32F-ZVFH-NEXT: .LBB76_12: # %else148807; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 648808; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 2, e8, mf4, ta, ma8809; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v8, v8, 28810; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB76_148811; RV64ZVE32F-ZVFH-NEXT: # %bb.13: # %cond.load168812; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v88813; RV64ZVE32F-ZVFH-NEXT: zext.b a2, a28814; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 18815; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a28816; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)8817; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma8818; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa58819; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 7, e16, m1, tu, ma8820; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 68821; RV64ZVE32F-ZVFH-NEXT: .LBB76_14: # %else178822; RV64ZVE32F-ZVFH-NEXT: andi a1, a1, -1288823; RV64ZVE32F-ZVFH-NEXT: beqz a1, .LBB76_168824; RV64ZVE32F-ZVFH-NEXT: # %bb.15: # %cond.load198825; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, mf4, ta, ma8826; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v8, v8, 18827; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a1, v88828; RV64ZVE32F-ZVFH-NEXT: zext.b a1, a18829; RV64ZVE32F-ZVFH-NEXT: slli a1, a1, 18830; RV64ZVE32F-ZVFH-NEXT: add a0, a0, a18831; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a0)8832; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma8833; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v8, fa58834; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma8835; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v8, 78836; RV64ZVE32F-ZVFH-NEXT: .LBB76_16: # %else208837; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, m1, ta, ma8838; RV64ZVE32F-ZVFH-NEXT: vmv1r.v v8, v98839; RV64ZVE32F-ZVFH-NEXT: ret8840;8841; RV64ZVE32F-ZVFHMIN-LABEL: mgather_baseidx_zext_v8i8_v8f16:8842; RV64ZVE32F-ZVFHMIN: # %bb.0:8843; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, m1, ta, ma8844; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a1, v08845; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 18846; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB76_28847; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.1: # %cond.load8848; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v88849; RV64ZVE32F-ZVFHMIN-NEXT: zext.b a2, a28850; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 18851; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a28852; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)8853; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, tu, ma8854; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v9, a28855; RV64ZVE32F-ZVFHMIN-NEXT: .LBB76_2: # %else8856; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 28857; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB76_48858; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.3: # %cond.load18859; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, mf4, ta, ma8860; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 18861; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v108862; RV64ZVE32F-ZVFHMIN-NEXT: zext.b a2, a28863; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 18864; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a28865; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)8866; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma8867; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a28868; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e16, m1, tu, ma8869; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 18870; RV64ZVE32F-ZVFHMIN-NEXT: .LBB76_4: # %else28871; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 48872; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e8, mf4, ta, ma8873; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 28874; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB76_68875; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.5: # %cond.load48876; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v108877; RV64ZVE32F-ZVFHMIN-NEXT: zext.b a2, a28878; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 18879; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a28880; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)8881; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma8882; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v11, a28883; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 3, e16, m1, tu, ma8884; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v11, 28885; RV64ZVE32F-ZVFHMIN-NEXT: .LBB76_6: # %else58886; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 88887; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB76_88888; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.7: # %cond.load78889; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, mf4, ta, ma8890; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v10, 18891; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v108892; RV64ZVE32F-ZVFHMIN-NEXT: zext.b a2, a28893; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 18894; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a28895; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)8896; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma8897; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a28898; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 4, e16, m1, tu, ma8899; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 38900; RV64ZVE32F-ZVFHMIN-NEXT: .LBB76_8: # %else88901; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 168902; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 4, e8, mf2, ta, ma8903; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v8, v8, 48904; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB76_108905; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.9: # %cond.load108906; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v88907; RV64ZVE32F-ZVFHMIN-NEXT: zext.b a2, a28908; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 18909; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a28910; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)8911; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma8912; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a28913; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 5, e16, m1, tu, ma8914; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 48915; RV64ZVE32F-ZVFHMIN-NEXT: .LBB76_10: # %else118916; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 328917; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB76_128918; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.11: # %cond.load138919; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, mf4, ta, ma8920; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 18921; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v108922; RV64ZVE32F-ZVFHMIN-NEXT: zext.b a2, a28923; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 18924; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a28925; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)8926; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma8927; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a28928; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, tu, ma8929; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 58930; RV64ZVE32F-ZVFHMIN-NEXT: .LBB76_12: # %else148931; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 648932; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e8, mf4, ta, ma8933; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v8, v8, 28934; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB76_148935; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.13: # %cond.load168936; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v88937; RV64ZVE32F-ZVFHMIN-NEXT: zext.b a2, a28938; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 18939; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a28940; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)8941; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma8942; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a28943; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 7, e16, m1, tu, ma8944; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 68945; RV64ZVE32F-ZVFHMIN-NEXT: .LBB76_14: # %else178946; RV64ZVE32F-ZVFHMIN-NEXT: andi a1, a1, -1288947; RV64ZVE32F-ZVFHMIN-NEXT: beqz a1, .LBB76_168948; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.15: # %cond.load198949; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, mf4, ta, ma8950; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v8, v8, 18951; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a1, v88952; RV64ZVE32F-ZVFHMIN-NEXT: zext.b a1, a18953; RV64ZVE32F-ZVFHMIN-NEXT: slli a1, a1, 18954; RV64ZVE32F-ZVFHMIN-NEXT: add a0, a0, a18955; RV64ZVE32F-ZVFHMIN-NEXT: lh a0, 0(a0)8956; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma8957; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v8, a08958; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma8959; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v8, 78960; RV64ZVE32F-ZVFHMIN-NEXT: .LBB76_16: # %else208961; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, m1, ta, ma8962; RV64ZVE32F-ZVFHMIN-NEXT: vmv1r.v v8, v98963; RV64ZVE32F-ZVFHMIN-NEXT: ret8964 %eidxs = zext <8 x i8> %idxs to <8 x i16>8965 %ptrs = getelementptr inbounds half, ptr %base, <8 x i16> %eidxs8966 %v = call <8 x half> @llvm.masked.gather.v8f16.v8p0(<8 x ptr> %ptrs, i32 2, <8 x i1> %m, <8 x half> %passthru)8967 ret <8 x half> %v8968}8969 8970define <8 x half> @mgather_baseidx_v8f16(ptr %base, <8 x i16> %idxs, <8 x i1> %m, <8 x half> %passthru) {8971; RV32-LABEL: mgather_baseidx_v8f16:8972; RV32: # %bb.0:8973; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu8974; RV32-NEXT: vwadd.vv v10, v8, v88975; RV32-NEXT: vluxei32.v v9, (a0), v10, v0.t8976; RV32-NEXT: vmv.v.v v8, v98977; RV32-NEXT: ret8978;8979; RV64V-LABEL: mgather_baseidx_v8f16:8980; RV64V: # %bb.0:8981; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma8982; RV64V-NEXT: vsext.vf4 v12, v88983; RV64V-NEXT: vadd.vv v12, v12, v128984; RV64V-NEXT: vsetvli zero, zero, e16, m1, ta, mu8985; RV64V-NEXT: vluxei64.v v9, (a0), v12, v0.t8986; RV64V-NEXT: vmv.v.v v8, v98987; RV64V-NEXT: ret8988;8989; RV64ZVE32F-ZVFH-LABEL: mgather_baseidx_v8f16:8990; RV64ZVE32F-ZVFH: # %bb.0:8991; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, m1, ta, ma8992; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a1, v08993; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 18994; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB77_28995; RV64ZVE32F-ZVFH-NEXT: # %bb.1: # %cond.load8996; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, m2, tu, ma8997; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v88998; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 18999; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a29000; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)9001; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v9, fa59002; RV64ZVE32F-ZVFH-NEXT: .LBB77_2: # %else9003; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 29004; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB77_49005; RV64ZVE32F-ZVFH-NEXT: # %bb.3: # %cond.load19006; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, mf2, ta, ma9007; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 19008; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v109009; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 19010; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a29011; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)9012; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa59013; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 2, e16, m1, tu, ma9014; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 19015; RV64ZVE32F-ZVFH-NEXT: .LBB77_4: # %else29016; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 49017; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 2, e16, mf2, ta, ma9018; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 29019; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB77_69020; RV64ZVE32F-ZVFH-NEXT: # %bb.5: # %cond.load49021; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v109022; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 19023; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a29024; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)9025; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v11, fa59026; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 3, e16, m1, tu, ma9027; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v11, 29028; RV64ZVE32F-ZVFH-NEXT: .LBB77_6: # %else59029; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 89030; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB77_89031; RV64ZVE32F-ZVFH-NEXT: # %bb.7: # %cond.load79032; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, mf2, ta, ma9033; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v10, 19034; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v109035; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 19036; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a29037; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)9038; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa59039; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 4, e16, m1, tu, ma9040; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 39041; RV64ZVE32F-ZVFH-NEXT: .LBB77_8: # %else89042; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 169043; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 4, e16, m1, ta, ma9044; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v8, v8, 49045; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB77_109046; RV64ZVE32F-ZVFH-NEXT: # %bb.9: # %cond.load109047; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v89048; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 19049; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a29050; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)9051; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa59052; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 5, e16, m1, tu, ma9053; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 49054; RV64ZVE32F-ZVFH-NEXT: .LBB77_10: # %else119055; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 329056; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB77_129057; RV64ZVE32F-ZVFH-NEXT: # %bb.11: # %cond.load139058; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, mf2, ta, ma9059; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 19060; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v109061; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 19062; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a29063; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)9064; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa59065; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 6, e16, m1, tu, ma9066; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 59067; RV64ZVE32F-ZVFH-NEXT: .LBB77_12: # %else149068; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 649069; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 2, e16, mf2, ta, ma9070; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v8, v8, 29071; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB77_149072; RV64ZVE32F-ZVFH-NEXT: # %bb.13: # %cond.load169073; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v89074; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 19075; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a29076; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)9077; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa59078; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 7, e16, m1, tu, ma9079; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 69080; RV64ZVE32F-ZVFH-NEXT: .LBB77_14: # %else179081; RV64ZVE32F-ZVFH-NEXT: andi a1, a1, -1289082; RV64ZVE32F-ZVFH-NEXT: beqz a1, .LBB77_169083; RV64ZVE32F-ZVFH-NEXT: # %bb.15: # %cond.load199084; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, mf2, ta, ma9085; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v8, v8, 19086; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a1, v89087; RV64ZVE32F-ZVFH-NEXT: slli a1, a1, 19088; RV64ZVE32F-ZVFH-NEXT: add a0, a0, a19089; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a0)9090; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v8, fa59091; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma9092; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v8, 79093; RV64ZVE32F-ZVFH-NEXT: .LBB77_16: # %else209094; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, m1, ta, ma9095; RV64ZVE32F-ZVFH-NEXT: vmv1r.v v8, v99096; RV64ZVE32F-ZVFH-NEXT: ret9097;9098; RV64ZVE32F-ZVFHMIN-LABEL: mgather_baseidx_v8f16:9099; RV64ZVE32F-ZVFHMIN: # %bb.0:9100; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, m1, ta, ma9101; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a1, v09102; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 19103; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB77_29104; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.1: # %cond.load9105; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, tu, ma9106; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v89107; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 19108; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a29109; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)9110; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v9, a29111; RV64ZVE32F-ZVFHMIN-NEXT: .LBB77_2: # %else9112; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 29113; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB77_49114; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.3: # %cond.load19115; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, mf2, ta, ma9116; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 19117; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v109118; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 19119; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a29120; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)9121; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a29122; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e16, m1, tu, ma9123; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 19124; RV64ZVE32F-ZVFHMIN-NEXT: .LBB77_4: # %else29125; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 49126; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf2, ta, ma9127; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 29128; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB77_69129; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.5: # %cond.load49130; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v109131; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 19132; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a29133; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)9134; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v11, a29135; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 3, e16, m1, tu, ma9136; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v11, 29137; RV64ZVE32F-ZVFHMIN-NEXT: .LBB77_6: # %else59138; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 89139; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB77_89140; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.7: # %cond.load79141; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, mf2, ta, ma9142; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v10, 19143; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v109144; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 19145; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a29146; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)9147; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a29148; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 4, e16, m1, tu, ma9149; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 39150; RV64ZVE32F-ZVFHMIN-NEXT: .LBB77_8: # %else89151; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 169152; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 4, e16, m1, ta, ma9153; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v8, v8, 49154; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB77_109155; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.9: # %cond.load109156; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v89157; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 19158; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a29159; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)9160; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a29161; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 5, e16, m1, tu, ma9162; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 49163; RV64ZVE32F-ZVFHMIN-NEXT: .LBB77_10: # %else119164; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 329165; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB77_129166; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.11: # %cond.load139167; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, mf2, ta, ma9168; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 19169; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v109170; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 19171; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a29172; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)9173; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a29174; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, tu, ma9175; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 59176; RV64ZVE32F-ZVFHMIN-NEXT: .LBB77_12: # %else149177; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 649178; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf2, ta, ma9179; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v8, v8, 29180; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB77_149181; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.13: # %cond.load169182; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v89183; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 19184; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a29185; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)9186; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a29187; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 7, e16, m1, tu, ma9188; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 69189; RV64ZVE32F-ZVFHMIN-NEXT: .LBB77_14: # %else179190; RV64ZVE32F-ZVFHMIN-NEXT: andi a1, a1, -1289191; RV64ZVE32F-ZVFHMIN-NEXT: beqz a1, .LBB77_169192; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.15: # %cond.load199193; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, mf2, ta, ma9194; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v8, v8, 19195; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a1, v89196; RV64ZVE32F-ZVFHMIN-NEXT: slli a1, a1, 19197; RV64ZVE32F-ZVFHMIN-NEXT: add a0, a0, a19198; RV64ZVE32F-ZVFHMIN-NEXT: lh a0, 0(a0)9199; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v8, a09200; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma9201; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v8, 79202; RV64ZVE32F-ZVFHMIN-NEXT: .LBB77_16: # %else209203; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, m1, ta, ma9204; RV64ZVE32F-ZVFHMIN-NEXT: vmv1r.v v8, v99205; RV64ZVE32F-ZVFHMIN-NEXT: ret9206 %ptrs = getelementptr inbounds half, ptr %base, <8 x i16> %idxs9207 %v = call <8 x half> @llvm.masked.gather.v8f16.v8p0(<8 x ptr> %ptrs, i32 2, <8 x i1> %m, <8 x half> %passthru)9208 ret <8 x half> %v9209}9210 9211define <1 x float> @mgather_v1f32(<1 x ptr> %ptrs, <1 x i1> %m, <1 x float> %passthru) {9212; RV32V-LABEL: mgather_v1f32:9213; RV32V: # %bb.0:9214; RV32V-NEXT: vsetivli zero, 1, e32, mf2, ta, mu9215; RV32V-NEXT: vluxei32.v v9, (zero), v8, v0.t9216; RV32V-NEXT: vmv1r.v v8, v99217; RV32V-NEXT: ret9218;9219; RV64V-LABEL: mgather_v1f32:9220; RV64V: # %bb.0:9221; RV64V-NEXT: vsetivli zero, 1, e32, mf2, ta, mu9222; RV64V-NEXT: vluxei64.v v9, (zero), v8, v0.t9223; RV64V-NEXT: vmv1r.v v8, v99224; RV64V-NEXT: ret9225;9226; RV32ZVE32F-LABEL: mgather_v1f32:9227; RV32ZVE32F: # %bb.0:9228; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, mu9229; RV32ZVE32F-NEXT: vluxei32.v v9, (zero), v8, v0.t9230; RV32ZVE32F-NEXT: vmv.v.v v8, v99231; RV32ZVE32F-NEXT: ret9232;9233; RV64ZVE32F-LABEL: mgather_v1f32:9234; RV64ZVE32F: # %bb.0:9235; RV64ZVE32F-NEXT: vsetvli a1, zero, e8, mf4, ta, ma9236; RV64ZVE32F-NEXT: vfirst.m a1, v09237; RV64ZVE32F-NEXT: bnez a1, .LBB78_29238; RV64ZVE32F-NEXT: # %bb.1: # %cond.load9239; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma9240; RV64ZVE32F-NEXT: vle32.v v8, (a0)9241; RV64ZVE32F-NEXT: .LBB78_2: # %else9242; RV64ZVE32F-NEXT: ret9243 %v = call <1 x float> @llvm.masked.gather.v1f32.v1p0(<1 x ptr> %ptrs, i32 4, <1 x i1> %m, <1 x float> %passthru)9244 ret <1 x float> %v9245}9246 9247define <2 x float> @mgather_v2f32(<2 x ptr> %ptrs, <2 x i1> %m, <2 x float> %passthru) {9248; RV32V-LABEL: mgather_v2f32:9249; RV32V: # %bb.0:9250; RV32V-NEXT: vsetivli zero, 2, e32, mf2, ta, mu9251; RV32V-NEXT: vluxei32.v v9, (zero), v8, v0.t9252; RV32V-NEXT: vmv1r.v v8, v99253; RV32V-NEXT: ret9254;9255; RV64V-LABEL: mgather_v2f32:9256; RV64V: # %bb.0:9257; RV64V-NEXT: vsetivli zero, 2, e32, mf2, ta, mu9258; RV64V-NEXT: vluxei64.v v9, (zero), v8, v0.t9259; RV64V-NEXT: vmv1r.v v8, v99260; RV64V-NEXT: ret9261;9262; RV32ZVE32F-LABEL: mgather_v2f32:9263; RV32ZVE32F: # %bb.0:9264; RV32ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, mu9265; RV32ZVE32F-NEXT: vluxei32.v v9, (zero), v8, v0.t9266; RV32ZVE32F-NEXT: vmv.v.v v8, v99267; RV32ZVE32F-NEXT: ret9268;9269; RV64ZVE32F-LABEL: mgather_v2f32:9270; RV64ZVE32F: # %bb.0:9271; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma9272; RV64ZVE32F-NEXT: vmv.x.s a2, v09273; RV64ZVE32F-NEXT: andi a3, a2, 19274; RV64ZVE32F-NEXT: bnez a3, .LBB79_39275; RV64ZVE32F-NEXT: # %bb.1: # %else9276; RV64ZVE32F-NEXT: andi a2, a2, 29277; RV64ZVE32F-NEXT: bnez a2, .LBB79_49278; RV64ZVE32F-NEXT: .LBB79_2: # %else29279; RV64ZVE32F-NEXT: ret9280; RV64ZVE32F-NEXT: .LBB79_3: # %cond.load9281; RV64ZVE32F-NEXT: flw fa5, 0(a0)9282; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma9283; RV64ZVE32F-NEXT: vfmv.s.f v8, fa59284; RV64ZVE32F-NEXT: andi a2, a2, 29285; RV64ZVE32F-NEXT: beqz a2, .LBB79_29286; RV64ZVE32F-NEXT: .LBB79_4: # %cond.load19287; RV64ZVE32F-NEXT: flw fa5, 0(a1)9288; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma9289; RV64ZVE32F-NEXT: vfmv.s.f v9, fa59290; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma9291; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 19292; RV64ZVE32F-NEXT: ret9293 %v = call <2 x float> @llvm.masked.gather.v2f32.v2p0(<2 x ptr> %ptrs, i32 4, <2 x i1> %m, <2 x float> %passthru)9294 ret <2 x float> %v9295}9296 9297define <4 x float> @mgather_v4f32(<4 x ptr> %ptrs, <4 x i1> %m, <4 x float> %passthru) {9298; RV32-LABEL: mgather_v4f32:9299; RV32: # %bb.0:9300; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu9301; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t9302; RV32-NEXT: vmv.v.v v8, v99303; RV32-NEXT: ret9304;9305; RV64V-LABEL: mgather_v4f32:9306; RV64V: # %bb.0:9307; RV64V-NEXT: vsetivli zero, 4, e32, m1, ta, mu9308; RV64V-NEXT: vluxei64.v v10, (zero), v8, v0.t9309; RV64V-NEXT: vmv.v.v v8, v109310; RV64V-NEXT: ret9311;9312; RV64ZVE32F-LABEL: mgather_v4f32:9313; RV64ZVE32F: # %bb.0:9314; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma9315; RV64ZVE32F-NEXT: vmv.x.s a1, v09316; RV64ZVE32F-NEXT: andi a2, a1, 19317; RV64ZVE32F-NEXT: bnez a2, .LBB80_59318; RV64ZVE32F-NEXT: # %bb.1: # %else9319; RV64ZVE32F-NEXT: andi a2, a1, 29320; RV64ZVE32F-NEXT: bnez a2, .LBB80_69321; RV64ZVE32F-NEXT: .LBB80_2: # %else29322; RV64ZVE32F-NEXT: andi a2, a1, 49323; RV64ZVE32F-NEXT: bnez a2, .LBB80_79324; RV64ZVE32F-NEXT: .LBB80_3: # %else59325; RV64ZVE32F-NEXT: andi a1, a1, 89326; RV64ZVE32F-NEXT: bnez a1, .LBB80_89327; RV64ZVE32F-NEXT: .LBB80_4: # %else89328; RV64ZVE32F-NEXT: ret9329; RV64ZVE32F-NEXT: .LBB80_5: # %cond.load9330; RV64ZVE32F-NEXT: ld a2, 0(a0)9331; RV64ZVE32F-NEXT: flw fa5, 0(a2)9332; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma9333; RV64ZVE32F-NEXT: vfmv.s.f v8, fa59334; RV64ZVE32F-NEXT: andi a2, a1, 29335; RV64ZVE32F-NEXT: beqz a2, .LBB80_29336; RV64ZVE32F-NEXT: .LBB80_6: # %cond.load19337; RV64ZVE32F-NEXT: ld a2, 8(a0)9338; RV64ZVE32F-NEXT: flw fa5, 0(a2)9339; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma9340; RV64ZVE32F-NEXT: vfmv.s.f v9, fa59341; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma9342; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 19343; RV64ZVE32F-NEXT: andi a2, a1, 49344; RV64ZVE32F-NEXT: beqz a2, .LBB80_39345; RV64ZVE32F-NEXT: .LBB80_7: # %cond.load49346; RV64ZVE32F-NEXT: ld a2, 16(a0)9347; RV64ZVE32F-NEXT: flw fa5, 0(a2)9348; RV64ZVE32F-NEXT: vsetivli zero, 3, e32, m1, tu, ma9349; RV64ZVE32F-NEXT: vfmv.s.f v9, fa59350; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 29351; RV64ZVE32F-NEXT: andi a1, a1, 89352; RV64ZVE32F-NEXT: beqz a1, .LBB80_49353; RV64ZVE32F-NEXT: .LBB80_8: # %cond.load79354; RV64ZVE32F-NEXT: ld a0, 24(a0)9355; RV64ZVE32F-NEXT: flw fa5, 0(a0)9356; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, ta, ma9357; RV64ZVE32F-NEXT: vfmv.s.f v9, fa59358; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 39359; RV64ZVE32F-NEXT: ret9360 %v = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %m, <4 x float> %passthru)9361 ret <4 x float> %v9362}9363 9364define <4 x float> @mgather_truemask_v4f32(<4 x ptr> %ptrs, <4 x float> %passthru) {9365; RV32-LABEL: mgather_truemask_v4f32:9366; RV32: # %bb.0:9367; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma9368; RV32-NEXT: vluxei32.v v8, (zero), v89369; RV32-NEXT: ret9370;9371; RV64V-LABEL: mgather_truemask_v4f32:9372; RV64V: # %bb.0:9373; RV64V-NEXT: vsetivli zero, 4, e32, m1, ta, ma9374; RV64V-NEXT: vluxei64.v v10, (zero), v89375; RV64V-NEXT: vmv.v.v v8, v109376; RV64V-NEXT: ret9377;9378; RV64ZVE32F-LABEL: mgather_truemask_v4f32:9379; RV64ZVE32F: # %bb.0:9380; RV64ZVE32F-NEXT: ld a1, 0(a0)9381; RV64ZVE32F-NEXT: ld a2, 8(a0)9382; RV64ZVE32F-NEXT: ld a3, 16(a0)9383; RV64ZVE32F-NEXT: ld a0, 24(a0)9384; RV64ZVE32F-NEXT: flw fa5, 0(a1)9385; RV64ZVE32F-NEXT: flw fa4, 0(a2)9386; RV64ZVE32F-NEXT: flw fa3, 0(a3)9387; RV64ZVE32F-NEXT: flw fa2, 0(a0)9388; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, ta, ma9389; RV64ZVE32F-NEXT: vfmv.v.f v8, fa59390; RV64ZVE32F-NEXT: vfslide1down.vf v8, v8, fa49391; RV64ZVE32F-NEXT: vfslide1down.vf v8, v8, fa39392; RV64ZVE32F-NEXT: vfslide1down.vf v8, v8, fa29393; RV64ZVE32F-NEXT: ret9394 %v = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> splat (i1 1), <4 x float> %passthru)9395 ret <4 x float> %v9396}9397 9398define <4 x float> @mgather_falsemask_v4f32(<4 x ptr> %ptrs, <4 x float> %passthru) {9399; RV32-LABEL: mgather_falsemask_v4f32:9400; RV32: # %bb.0:9401; RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma9402; RV32-NEXT: vmv1r.v v8, v99403; RV32-NEXT: ret9404;9405; RV64V-LABEL: mgather_falsemask_v4f32:9406; RV64V: # %bb.0:9407; RV64V-NEXT: vsetivli zero, 1, e8, m1, ta, ma9408; RV64V-NEXT: vmv1r.v v8, v109409; RV64V-NEXT: ret9410;9411; RV64ZVE32F-LABEL: mgather_falsemask_v4f32:9412; RV64ZVE32F: # %bb.0:9413; RV64ZVE32F-NEXT: ret9414 %v = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> zeroinitializer, <4 x float> %passthru)9415 ret <4 x float> %v9416}9417 9418define <8 x float> @mgather_v8f32(<8 x ptr> %ptrs, <8 x i1> %m, <8 x float> %passthru) {9419; RV32-LABEL: mgather_v8f32:9420; RV32: # %bb.0:9421; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu9422; RV32-NEXT: vluxei32.v v10, (zero), v8, v0.t9423; RV32-NEXT: vmv.v.v v8, v109424; RV32-NEXT: ret9425;9426; RV64V-LABEL: mgather_v8f32:9427; RV64V: # %bb.0:9428; RV64V-NEXT: vsetivli zero, 8, e32, m2, ta, mu9429; RV64V-NEXT: vluxei64.v v12, (zero), v8, v0.t9430; RV64V-NEXT: vmv.v.v v8, v129431; RV64V-NEXT: ret9432;9433; RV64ZVE32F-LABEL: mgather_v8f32:9434; RV64ZVE32F: # %bb.0:9435; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma9436; RV64ZVE32F-NEXT: vmv.x.s a1, v09437; RV64ZVE32F-NEXT: andi a2, a1, 19438; RV64ZVE32F-NEXT: bnez a2, .LBB83_99439; RV64ZVE32F-NEXT: # %bb.1: # %else9440; RV64ZVE32F-NEXT: andi a2, a1, 29441; RV64ZVE32F-NEXT: bnez a2, .LBB83_109442; RV64ZVE32F-NEXT: .LBB83_2: # %else29443; RV64ZVE32F-NEXT: andi a2, a1, 49444; RV64ZVE32F-NEXT: bnez a2, .LBB83_119445; RV64ZVE32F-NEXT: .LBB83_3: # %else59446; RV64ZVE32F-NEXT: andi a2, a1, 89447; RV64ZVE32F-NEXT: bnez a2, .LBB83_129448; RV64ZVE32F-NEXT: .LBB83_4: # %else89449; RV64ZVE32F-NEXT: andi a2, a1, 169450; RV64ZVE32F-NEXT: bnez a2, .LBB83_139451; RV64ZVE32F-NEXT: .LBB83_5: # %else119452; RV64ZVE32F-NEXT: andi a2, a1, 329453; RV64ZVE32F-NEXT: bnez a2, .LBB83_149454; RV64ZVE32F-NEXT: .LBB83_6: # %else149455; RV64ZVE32F-NEXT: andi a2, a1, 649456; RV64ZVE32F-NEXT: bnez a2, .LBB83_159457; RV64ZVE32F-NEXT: .LBB83_7: # %else179458; RV64ZVE32F-NEXT: andi a1, a1, -1289459; RV64ZVE32F-NEXT: bnez a1, .LBB83_169460; RV64ZVE32F-NEXT: .LBB83_8: # %else209461; RV64ZVE32F-NEXT: ret9462; RV64ZVE32F-NEXT: .LBB83_9: # %cond.load9463; RV64ZVE32F-NEXT: ld a2, 0(a0)9464; RV64ZVE32F-NEXT: flw fa5, 0(a2)9465; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma9466; RV64ZVE32F-NEXT: vfmv.s.f v8, fa59467; RV64ZVE32F-NEXT: andi a2, a1, 29468; RV64ZVE32F-NEXT: beqz a2, .LBB83_29469; RV64ZVE32F-NEXT: .LBB83_10: # %cond.load19470; RV64ZVE32F-NEXT: ld a2, 8(a0)9471; RV64ZVE32F-NEXT: flw fa5, 0(a2)9472; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma9473; RV64ZVE32F-NEXT: vfmv.s.f v10, fa59474; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma9475; RV64ZVE32F-NEXT: vslideup.vi v8, v10, 19476; RV64ZVE32F-NEXT: andi a2, a1, 49477; RV64ZVE32F-NEXT: beqz a2, .LBB83_39478; RV64ZVE32F-NEXT: .LBB83_11: # %cond.load49479; RV64ZVE32F-NEXT: ld a2, 16(a0)9480; RV64ZVE32F-NEXT: flw fa5, 0(a2)9481; RV64ZVE32F-NEXT: vsetivli zero, 3, e32, m1, tu, ma9482; RV64ZVE32F-NEXT: vfmv.s.f v10, fa59483; RV64ZVE32F-NEXT: vslideup.vi v8, v10, 29484; RV64ZVE32F-NEXT: andi a2, a1, 89485; RV64ZVE32F-NEXT: beqz a2, .LBB83_49486; RV64ZVE32F-NEXT: .LBB83_12: # %cond.load79487; RV64ZVE32F-NEXT: ld a2, 24(a0)9488; RV64ZVE32F-NEXT: flw fa5, 0(a2)9489; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma9490; RV64ZVE32F-NEXT: vfmv.s.f v10, fa59491; RV64ZVE32F-NEXT: vslideup.vi v8, v10, 39492; RV64ZVE32F-NEXT: andi a2, a1, 169493; RV64ZVE32F-NEXT: beqz a2, .LBB83_59494; RV64ZVE32F-NEXT: .LBB83_13: # %cond.load109495; RV64ZVE32F-NEXT: ld a2, 32(a0)9496; RV64ZVE32F-NEXT: flw fa5, 0(a2)9497; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma9498; RV64ZVE32F-NEXT: vfmv.s.f v10, fa59499; RV64ZVE32F-NEXT: vslideup.vi v8, v10, 49500; RV64ZVE32F-NEXT: andi a2, a1, 329501; RV64ZVE32F-NEXT: beqz a2, .LBB83_69502; RV64ZVE32F-NEXT: .LBB83_14: # %cond.load139503; RV64ZVE32F-NEXT: ld a2, 40(a0)9504; RV64ZVE32F-NEXT: flw fa5, 0(a2)9505; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma9506; RV64ZVE32F-NEXT: vfmv.s.f v10, fa59507; RV64ZVE32F-NEXT: vslideup.vi v8, v10, 59508; RV64ZVE32F-NEXT: andi a2, a1, 649509; RV64ZVE32F-NEXT: beqz a2, .LBB83_79510; RV64ZVE32F-NEXT: .LBB83_15: # %cond.load169511; RV64ZVE32F-NEXT: ld a2, 48(a0)9512; RV64ZVE32F-NEXT: flw fa5, 0(a2)9513; RV64ZVE32F-NEXT: vsetivli zero, 7, e32, m2, tu, ma9514; RV64ZVE32F-NEXT: vfmv.s.f v10, fa59515; RV64ZVE32F-NEXT: vslideup.vi v8, v10, 69516; RV64ZVE32F-NEXT: andi a1, a1, -1289517; RV64ZVE32F-NEXT: beqz a1, .LBB83_89518; RV64ZVE32F-NEXT: .LBB83_16: # %cond.load199519; RV64ZVE32F-NEXT: ld a0, 56(a0)9520; RV64ZVE32F-NEXT: flw fa5, 0(a0)9521; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma9522; RV64ZVE32F-NEXT: vfmv.s.f v10, fa59523; RV64ZVE32F-NEXT: vslideup.vi v8, v10, 79524; RV64ZVE32F-NEXT: ret9525 %v = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> %m, <8 x float> %passthru)9526 ret <8 x float> %v9527}9528 9529define <8 x float> @mgather_baseidx_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <8 x i1> %m, <8 x float> %passthru) {9530; RV32-LABEL: mgather_baseidx_v8i8_v8f32:9531; RV32: # %bb.0:9532; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu9533; RV32-NEXT: vsext.vf4 v12, v89534; RV32-NEXT: vsll.vi v8, v12, 29535; RV32-NEXT: vluxei32.v v10, (a0), v8, v0.t9536; RV32-NEXT: vmv.v.v v8, v109537; RV32-NEXT: ret9538;9539; RV64V-LABEL: mgather_baseidx_v8i8_v8f32:9540; RV64V: # %bb.0:9541; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma9542; RV64V-NEXT: vsext.vf8 v12, v89543; RV64V-NEXT: vsll.vi v12, v12, 29544; RV64V-NEXT: vsetvli zero, zero, e32, m2, ta, mu9545; RV64V-NEXT: vluxei64.v v10, (a0), v12, v0.t9546; RV64V-NEXT: vmv.v.v v8, v109547; RV64V-NEXT: ret9548;9549; RV64ZVE32F-LABEL: mgather_baseidx_v8i8_v8f32:9550; RV64ZVE32F: # %bb.0:9551; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma9552; RV64ZVE32F-NEXT: vmv.x.s a1, v09553; RV64ZVE32F-NEXT: andi a2, a1, 19554; RV64ZVE32F-NEXT: beqz a2, .LBB84_29555; RV64ZVE32F-NEXT: # %bb.1: # %cond.load9556; RV64ZVE32F-NEXT: vmv.x.s a2, v89557; RV64ZVE32F-NEXT: slli a2, a2, 29558; RV64ZVE32F-NEXT: add a2, a0, a29559; RV64ZVE32F-NEXT: flw fa5, 0(a2)9560; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma9561; RV64ZVE32F-NEXT: vfmv.s.f v10, fa59562; RV64ZVE32F-NEXT: .LBB84_2: # %else9563; RV64ZVE32F-NEXT: andi a2, a1, 29564; RV64ZVE32F-NEXT: beqz a2, .LBB84_49565; RV64ZVE32F-NEXT: # %bb.3: # %cond.load19566; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma9567; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 19568; RV64ZVE32F-NEXT: vmv.x.s a2, v99569; RV64ZVE32F-NEXT: slli a2, a2, 29570; RV64ZVE32F-NEXT: add a2, a0, a29571; RV64ZVE32F-NEXT: flw fa5, 0(a2)9572; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma9573; RV64ZVE32F-NEXT: vfmv.s.f v9, fa59574; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma9575; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 19576; RV64ZVE32F-NEXT: .LBB84_4: # %else29577; RV64ZVE32F-NEXT: andi a2, a1, 49578; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma9579; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 29580; RV64ZVE32F-NEXT: beqz a2, .LBB84_69581; RV64ZVE32F-NEXT: # %bb.5: # %cond.load49582; RV64ZVE32F-NEXT: vmv.x.s a2, v99583; RV64ZVE32F-NEXT: slli a2, a2, 29584; RV64ZVE32F-NEXT: add a2, a0, a29585; RV64ZVE32F-NEXT: flw fa5, 0(a2)9586; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma9587; RV64ZVE32F-NEXT: vfmv.s.f v12, fa59588; RV64ZVE32F-NEXT: vsetivli zero, 3, e32, m1, tu, ma9589; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 29590; RV64ZVE32F-NEXT: .LBB84_6: # %else59591; RV64ZVE32F-NEXT: andi a2, a1, 89592; RV64ZVE32F-NEXT: beqz a2, .LBB84_89593; RV64ZVE32F-NEXT: # %bb.7: # %cond.load79594; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma9595; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 19596; RV64ZVE32F-NEXT: vmv.x.s a2, v99597; RV64ZVE32F-NEXT: slli a2, a2, 29598; RV64ZVE32F-NEXT: add a2, a0, a29599; RV64ZVE32F-NEXT: flw fa5, 0(a2)9600; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma9601; RV64ZVE32F-NEXT: vfmv.s.f v9, fa59602; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma9603; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 39604; RV64ZVE32F-NEXT: .LBB84_8: # %else89605; RV64ZVE32F-NEXT: andi a2, a1, 169606; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma9607; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 49608; RV64ZVE32F-NEXT: beqz a2, .LBB84_109609; RV64ZVE32F-NEXT: # %bb.9: # %cond.load109610; RV64ZVE32F-NEXT: vmv.x.s a2, v89611; RV64ZVE32F-NEXT: slli a2, a2, 29612; RV64ZVE32F-NEXT: add a2, a0, a29613; RV64ZVE32F-NEXT: flw fa5, 0(a2)9614; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma9615; RV64ZVE32F-NEXT: vfmv.s.f v12, fa59616; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma9617; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 49618; RV64ZVE32F-NEXT: .LBB84_10: # %else119619; RV64ZVE32F-NEXT: andi a2, a1, 329620; RV64ZVE32F-NEXT: beqz a2, .LBB84_129621; RV64ZVE32F-NEXT: # %bb.11: # %cond.load139622; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma9623; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 19624; RV64ZVE32F-NEXT: vmv.x.s a2, v99625; RV64ZVE32F-NEXT: slli a2, a2, 29626; RV64ZVE32F-NEXT: add a2, a0, a29627; RV64ZVE32F-NEXT: flw fa5, 0(a2)9628; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma9629; RV64ZVE32F-NEXT: vfmv.s.f v12, fa59630; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma9631; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 59632; RV64ZVE32F-NEXT: .LBB84_12: # %else149633; RV64ZVE32F-NEXT: andi a2, a1, 649634; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma9635; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 29636; RV64ZVE32F-NEXT: beqz a2, .LBB84_149637; RV64ZVE32F-NEXT: # %bb.13: # %cond.load169638; RV64ZVE32F-NEXT: vmv.x.s a2, v89639; RV64ZVE32F-NEXT: slli a2, a2, 29640; RV64ZVE32F-NEXT: add a2, a0, a29641; RV64ZVE32F-NEXT: flw fa5, 0(a2)9642; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma9643; RV64ZVE32F-NEXT: vfmv.s.f v12, fa59644; RV64ZVE32F-NEXT: vsetivli zero, 7, e32, m2, tu, ma9645; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 69646; RV64ZVE32F-NEXT: .LBB84_14: # %else179647; RV64ZVE32F-NEXT: andi a1, a1, -1289648; RV64ZVE32F-NEXT: beqz a1, .LBB84_169649; RV64ZVE32F-NEXT: # %bb.15: # %cond.load199650; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma9651; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 19652; RV64ZVE32F-NEXT: vmv.x.s a1, v89653; RV64ZVE32F-NEXT: slli a1, a1, 29654; RV64ZVE32F-NEXT: add a0, a0, a19655; RV64ZVE32F-NEXT: flw fa5, 0(a0)9656; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma9657; RV64ZVE32F-NEXT: vfmv.s.f v8, fa59658; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma9659; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 79660; RV64ZVE32F-NEXT: .LBB84_16: # %else209661; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma9662; RV64ZVE32F-NEXT: vmv2r.v v8, v109663; RV64ZVE32F-NEXT: ret9664 %ptrs = getelementptr inbounds float, ptr %base, <8 x i8> %idxs9665 %v = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> %m, <8 x float> %passthru)9666 ret <8 x float> %v9667}9668 9669define <8 x float> @mgather_baseidx_sext_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <8 x i1> %m, <8 x float> %passthru) {9670; RV32-LABEL: mgather_baseidx_sext_v8i8_v8f32:9671; RV32: # %bb.0:9672; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu9673; RV32-NEXT: vsext.vf4 v12, v89674; RV32-NEXT: vsll.vi v8, v12, 29675; RV32-NEXT: vluxei32.v v10, (a0), v8, v0.t9676; RV32-NEXT: vmv.v.v v8, v109677; RV32-NEXT: ret9678;9679; RV64V-LABEL: mgather_baseidx_sext_v8i8_v8f32:9680; RV64V: # %bb.0:9681; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma9682; RV64V-NEXT: vsext.vf8 v12, v89683; RV64V-NEXT: vsll.vi v12, v12, 29684; RV64V-NEXT: vsetvli zero, zero, e32, m2, ta, mu9685; RV64V-NEXT: vluxei64.v v10, (a0), v12, v0.t9686; RV64V-NEXT: vmv.v.v v8, v109687; RV64V-NEXT: ret9688;9689; RV64ZVE32F-LABEL: mgather_baseidx_sext_v8i8_v8f32:9690; RV64ZVE32F: # %bb.0:9691; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma9692; RV64ZVE32F-NEXT: vmv.x.s a1, v09693; RV64ZVE32F-NEXT: andi a2, a1, 19694; RV64ZVE32F-NEXT: beqz a2, .LBB85_29695; RV64ZVE32F-NEXT: # %bb.1: # %cond.load9696; RV64ZVE32F-NEXT: vmv.x.s a2, v89697; RV64ZVE32F-NEXT: slli a2, a2, 29698; RV64ZVE32F-NEXT: add a2, a0, a29699; RV64ZVE32F-NEXT: flw fa5, 0(a2)9700; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma9701; RV64ZVE32F-NEXT: vfmv.s.f v10, fa59702; RV64ZVE32F-NEXT: .LBB85_2: # %else9703; RV64ZVE32F-NEXT: andi a2, a1, 29704; RV64ZVE32F-NEXT: beqz a2, .LBB85_49705; RV64ZVE32F-NEXT: # %bb.3: # %cond.load19706; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma9707; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 19708; RV64ZVE32F-NEXT: vmv.x.s a2, v99709; RV64ZVE32F-NEXT: slli a2, a2, 29710; RV64ZVE32F-NEXT: add a2, a0, a29711; RV64ZVE32F-NEXT: flw fa5, 0(a2)9712; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma9713; RV64ZVE32F-NEXT: vfmv.s.f v9, fa59714; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma9715; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 19716; RV64ZVE32F-NEXT: .LBB85_4: # %else29717; RV64ZVE32F-NEXT: andi a2, a1, 49718; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma9719; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 29720; RV64ZVE32F-NEXT: beqz a2, .LBB85_69721; RV64ZVE32F-NEXT: # %bb.5: # %cond.load49722; RV64ZVE32F-NEXT: vmv.x.s a2, v99723; RV64ZVE32F-NEXT: slli a2, a2, 29724; RV64ZVE32F-NEXT: add a2, a0, a29725; RV64ZVE32F-NEXT: flw fa5, 0(a2)9726; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma9727; RV64ZVE32F-NEXT: vfmv.s.f v12, fa59728; RV64ZVE32F-NEXT: vsetivli zero, 3, e32, m1, tu, ma9729; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 29730; RV64ZVE32F-NEXT: .LBB85_6: # %else59731; RV64ZVE32F-NEXT: andi a2, a1, 89732; RV64ZVE32F-NEXT: beqz a2, .LBB85_89733; RV64ZVE32F-NEXT: # %bb.7: # %cond.load79734; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma9735; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 19736; RV64ZVE32F-NEXT: vmv.x.s a2, v99737; RV64ZVE32F-NEXT: slli a2, a2, 29738; RV64ZVE32F-NEXT: add a2, a0, a29739; RV64ZVE32F-NEXT: flw fa5, 0(a2)9740; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma9741; RV64ZVE32F-NEXT: vfmv.s.f v9, fa59742; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma9743; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 39744; RV64ZVE32F-NEXT: .LBB85_8: # %else89745; RV64ZVE32F-NEXT: andi a2, a1, 169746; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma9747; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 49748; RV64ZVE32F-NEXT: beqz a2, .LBB85_109749; RV64ZVE32F-NEXT: # %bb.9: # %cond.load109750; RV64ZVE32F-NEXT: vmv.x.s a2, v89751; RV64ZVE32F-NEXT: slli a2, a2, 29752; RV64ZVE32F-NEXT: add a2, a0, a29753; RV64ZVE32F-NEXT: flw fa5, 0(a2)9754; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma9755; RV64ZVE32F-NEXT: vfmv.s.f v12, fa59756; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma9757; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 49758; RV64ZVE32F-NEXT: .LBB85_10: # %else119759; RV64ZVE32F-NEXT: andi a2, a1, 329760; RV64ZVE32F-NEXT: beqz a2, .LBB85_129761; RV64ZVE32F-NEXT: # %bb.11: # %cond.load139762; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma9763; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 19764; RV64ZVE32F-NEXT: vmv.x.s a2, v99765; RV64ZVE32F-NEXT: slli a2, a2, 29766; RV64ZVE32F-NEXT: add a2, a0, a29767; RV64ZVE32F-NEXT: flw fa5, 0(a2)9768; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma9769; RV64ZVE32F-NEXT: vfmv.s.f v12, fa59770; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma9771; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 59772; RV64ZVE32F-NEXT: .LBB85_12: # %else149773; RV64ZVE32F-NEXT: andi a2, a1, 649774; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma9775; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 29776; RV64ZVE32F-NEXT: beqz a2, .LBB85_149777; RV64ZVE32F-NEXT: # %bb.13: # %cond.load169778; RV64ZVE32F-NEXT: vmv.x.s a2, v89779; RV64ZVE32F-NEXT: slli a2, a2, 29780; RV64ZVE32F-NEXT: add a2, a0, a29781; RV64ZVE32F-NEXT: flw fa5, 0(a2)9782; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma9783; RV64ZVE32F-NEXT: vfmv.s.f v12, fa59784; RV64ZVE32F-NEXT: vsetivli zero, 7, e32, m2, tu, ma9785; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 69786; RV64ZVE32F-NEXT: .LBB85_14: # %else179787; RV64ZVE32F-NEXT: andi a1, a1, -1289788; RV64ZVE32F-NEXT: beqz a1, .LBB85_169789; RV64ZVE32F-NEXT: # %bb.15: # %cond.load199790; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma9791; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 19792; RV64ZVE32F-NEXT: vmv.x.s a1, v89793; RV64ZVE32F-NEXT: slli a1, a1, 29794; RV64ZVE32F-NEXT: add a0, a0, a19795; RV64ZVE32F-NEXT: flw fa5, 0(a0)9796; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma9797; RV64ZVE32F-NEXT: vfmv.s.f v8, fa59798; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma9799; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 79800; RV64ZVE32F-NEXT: .LBB85_16: # %else209801; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma9802; RV64ZVE32F-NEXT: vmv2r.v v8, v109803; RV64ZVE32F-NEXT: ret9804 %eidxs = sext <8 x i8> %idxs to <8 x i32>9805 %ptrs = getelementptr inbounds float, ptr %base, <8 x i32> %eidxs9806 %v = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> %m, <8 x float> %passthru)9807 ret <8 x float> %v9808}9809 9810define <8 x float> @mgather_baseidx_zext_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <8 x i1> %m, <8 x float> %passthru) {9811; RV32-LABEL: mgather_baseidx_zext_v8i8_v8f32:9812; RV32: # %bb.0:9813; RV32-NEXT: li a1, 49814; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma9815; RV32-NEXT: vwmulu.vx v9, v8, a19816; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, mu9817; RV32-NEXT: vluxei16.v v10, (a0), v9, v0.t9818; RV32-NEXT: vmv.v.v v8, v109819; RV32-NEXT: ret9820;9821; RV64V-LABEL: mgather_baseidx_zext_v8i8_v8f32:9822; RV64V: # %bb.0:9823; RV64V-NEXT: li a1, 49824; RV64V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma9825; RV64V-NEXT: vwmulu.vx v9, v8, a19826; RV64V-NEXT: vsetvli zero, zero, e32, m2, ta, mu9827; RV64V-NEXT: vluxei16.v v10, (a0), v9, v0.t9828; RV64V-NEXT: vmv.v.v v8, v109829; RV64V-NEXT: ret9830;9831; RV64ZVE32F-LABEL: mgather_baseidx_zext_v8i8_v8f32:9832; RV64ZVE32F: # %bb.0:9833; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma9834; RV64ZVE32F-NEXT: vmv.x.s a1, v09835; RV64ZVE32F-NEXT: andi a2, a1, 19836; RV64ZVE32F-NEXT: beqz a2, .LBB86_29837; RV64ZVE32F-NEXT: # %bb.1: # %cond.load9838; RV64ZVE32F-NEXT: vmv.x.s a2, v89839; RV64ZVE32F-NEXT: zext.b a2, a29840; RV64ZVE32F-NEXT: slli a2, a2, 29841; RV64ZVE32F-NEXT: add a2, a0, a29842; RV64ZVE32F-NEXT: flw fa5, 0(a2)9843; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma9844; RV64ZVE32F-NEXT: vfmv.s.f v10, fa59845; RV64ZVE32F-NEXT: .LBB86_2: # %else9846; RV64ZVE32F-NEXT: andi a2, a1, 29847; RV64ZVE32F-NEXT: beqz a2, .LBB86_49848; RV64ZVE32F-NEXT: # %bb.3: # %cond.load19849; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma9850; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 19851; RV64ZVE32F-NEXT: vmv.x.s a2, v99852; RV64ZVE32F-NEXT: zext.b a2, a29853; RV64ZVE32F-NEXT: slli a2, a2, 29854; RV64ZVE32F-NEXT: add a2, a0, a29855; RV64ZVE32F-NEXT: flw fa5, 0(a2)9856; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma9857; RV64ZVE32F-NEXT: vfmv.s.f v9, fa59858; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma9859; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 19860; RV64ZVE32F-NEXT: .LBB86_4: # %else29861; RV64ZVE32F-NEXT: andi a2, a1, 49862; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma9863; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 29864; RV64ZVE32F-NEXT: beqz a2, .LBB86_69865; RV64ZVE32F-NEXT: # %bb.5: # %cond.load49866; RV64ZVE32F-NEXT: vmv.x.s a2, v99867; RV64ZVE32F-NEXT: zext.b a2, a29868; RV64ZVE32F-NEXT: slli a2, a2, 29869; RV64ZVE32F-NEXT: add a2, a0, a29870; RV64ZVE32F-NEXT: flw fa5, 0(a2)9871; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma9872; RV64ZVE32F-NEXT: vfmv.s.f v12, fa59873; RV64ZVE32F-NEXT: vsetivli zero, 3, e32, m1, tu, ma9874; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 29875; RV64ZVE32F-NEXT: .LBB86_6: # %else59876; RV64ZVE32F-NEXT: andi a2, a1, 89877; RV64ZVE32F-NEXT: beqz a2, .LBB86_89878; RV64ZVE32F-NEXT: # %bb.7: # %cond.load79879; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma9880; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 19881; RV64ZVE32F-NEXT: vmv.x.s a2, v99882; RV64ZVE32F-NEXT: zext.b a2, a29883; RV64ZVE32F-NEXT: slli a2, a2, 29884; RV64ZVE32F-NEXT: add a2, a0, a29885; RV64ZVE32F-NEXT: flw fa5, 0(a2)9886; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma9887; RV64ZVE32F-NEXT: vfmv.s.f v9, fa59888; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma9889; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 39890; RV64ZVE32F-NEXT: .LBB86_8: # %else89891; RV64ZVE32F-NEXT: andi a2, a1, 169892; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma9893; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 49894; RV64ZVE32F-NEXT: beqz a2, .LBB86_109895; RV64ZVE32F-NEXT: # %bb.9: # %cond.load109896; RV64ZVE32F-NEXT: vmv.x.s a2, v89897; RV64ZVE32F-NEXT: zext.b a2, a29898; RV64ZVE32F-NEXT: slli a2, a2, 29899; RV64ZVE32F-NEXT: add a2, a0, a29900; RV64ZVE32F-NEXT: flw fa5, 0(a2)9901; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma9902; RV64ZVE32F-NEXT: vfmv.s.f v12, fa59903; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma9904; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 49905; RV64ZVE32F-NEXT: .LBB86_10: # %else119906; RV64ZVE32F-NEXT: andi a2, a1, 329907; RV64ZVE32F-NEXT: beqz a2, .LBB86_129908; RV64ZVE32F-NEXT: # %bb.11: # %cond.load139909; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma9910; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 19911; RV64ZVE32F-NEXT: vmv.x.s a2, v99912; RV64ZVE32F-NEXT: zext.b a2, a29913; RV64ZVE32F-NEXT: slli a2, a2, 29914; RV64ZVE32F-NEXT: add a2, a0, a29915; RV64ZVE32F-NEXT: flw fa5, 0(a2)9916; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma9917; RV64ZVE32F-NEXT: vfmv.s.f v12, fa59918; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma9919; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 59920; RV64ZVE32F-NEXT: .LBB86_12: # %else149921; RV64ZVE32F-NEXT: andi a2, a1, 649922; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma9923; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 29924; RV64ZVE32F-NEXT: beqz a2, .LBB86_149925; RV64ZVE32F-NEXT: # %bb.13: # %cond.load169926; RV64ZVE32F-NEXT: vmv.x.s a2, v89927; RV64ZVE32F-NEXT: zext.b a2, a29928; RV64ZVE32F-NEXT: slli a2, a2, 29929; RV64ZVE32F-NEXT: add a2, a0, a29930; RV64ZVE32F-NEXT: flw fa5, 0(a2)9931; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma9932; RV64ZVE32F-NEXT: vfmv.s.f v12, fa59933; RV64ZVE32F-NEXT: vsetivli zero, 7, e32, m2, tu, ma9934; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 69935; RV64ZVE32F-NEXT: .LBB86_14: # %else179936; RV64ZVE32F-NEXT: andi a1, a1, -1289937; RV64ZVE32F-NEXT: beqz a1, .LBB86_169938; RV64ZVE32F-NEXT: # %bb.15: # %cond.load199939; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma9940; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 19941; RV64ZVE32F-NEXT: vmv.x.s a1, v89942; RV64ZVE32F-NEXT: zext.b a1, a19943; RV64ZVE32F-NEXT: slli a1, a1, 29944; RV64ZVE32F-NEXT: add a0, a0, a19945; RV64ZVE32F-NEXT: flw fa5, 0(a0)9946; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma9947; RV64ZVE32F-NEXT: vfmv.s.f v8, fa59948; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma9949; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 79950; RV64ZVE32F-NEXT: .LBB86_16: # %else209951; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma9952; RV64ZVE32F-NEXT: vmv2r.v v8, v109953; RV64ZVE32F-NEXT: ret9954 %eidxs = zext <8 x i8> %idxs to <8 x i32>9955 %ptrs = getelementptr inbounds float, ptr %base, <8 x i32> %eidxs9956 %v = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> %m, <8 x float> %passthru)9957 ret <8 x float> %v9958}9959 9960define <8 x float> @mgather_baseidx_v8i16_v8f32(ptr %base, <8 x i16> %idxs, <8 x i1> %m, <8 x float> %passthru) {9961; RV32-LABEL: mgather_baseidx_v8i16_v8f32:9962; RV32: # %bb.0:9963; RV32-NEXT: li a1, 49964; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma9965; RV32-NEXT: vwmulsu.vx v12, v8, a19966; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, mu9967; RV32-NEXT: vluxei32.v v10, (a0), v12, v0.t9968; RV32-NEXT: vmv.v.v v8, v109969; RV32-NEXT: ret9970;9971; RV64V-LABEL: mgather_baseidx_v8i16_v8f32:9972; RV64V: # %bb.0:9973; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma9974; RV64V-NEXT: vsext.vf4 v12, v89975; RV64V-NEXT: vsll.vi v12, v12, 29976; RV64V-NEXT: vsetvli zero, zero, e32, m2, ta, mu9977; RV64V-NEXT: vluxei64.v v10, (a0), v12, v0.t9978; RV64V-NEXT: vmv.v.v v8, v109979; RV64V-NEXT: ret9980;9981; RV64ZVE32F-LABEL: mgather_baseidx_v8i16_v8f32:9982; RV64ZVE32F: # %bb.0:9983; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma9984; RV64ZVE32F-NEXT: vmv.x.s a1, v09985; RV64ZVE32F-NEXT: andi a2, a1, 19986; RV64ZVE32F-NEXT: beqz a2, .LBB87_29987; RV64ZVE32F-NEXT: # %bb.1: # %cond.load9988; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma9989; RV64ZVE32F-NEXT: vmv.x.s a2, v89990; RV64ZVE32F-NEXT: slli a2, a2, 29991; RV64ZVE32F-NEXT: add a2, a0, a29992; RV64ZVE32F-NEXT: flw fa5, 0(a2)9993; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma9994; RV64ZVE32F-NEXT: vfmv.s.f v10, fa59995; RV64ZVE32F-NEXT: .LBB87_2: # %else9996; RV64ZVE32F-NEXT: andi a2, a1, 29997; RV64ZVE32F-NEXT: beqz a2, .LBB87_49998; RV64ZVE32F-NEXT: # %bb.3: # %cond.load19999; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma10000; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 110001; RV64ZVE32F-NEXT: vmv.x.s a2, v910002; RV64ZVE32F-NEXT: slli a2, a2, 210003; RV64ZVE32F-NEXT: add a2, a0, a210004; RV64ZVE32F-NEXT: flw fa5, 0(a2)10005; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma10006; RV64ZVE32F-NEXT: vfmv.s.f v9, fa510007; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma10008; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 110009; RV64ZVE32F-NEXT: .LBB87_4: # %else210010; RV64ZVE32F-NEXT: andi a2, a1, 410011; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma10012; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 210013; RV64ZVE32F-NEXT: beqz a2, .LBB87_610014; RV64ZVE32F-NEXT: # %bb.5: # %cond.load410015; RV64ZVE32F-NEXT: vmv.x.s a2, v910016; RV64ZVE32F-NEXT: slli a2, a2, 210017; RV64ZVE32F-NEXT: add a2, a0, a210018; RV64ZVE32F-NEXT: flw fa5, 0(a2)10019; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma10020; RV64ZVE32F-NEXT: vfmv.s.f v12, fa510021; RV64ZVE32F-NEXT: vsetivli zero, 3, e32, m1, tu, ma10022; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 210023; RV64ZVE32F-NEXT: .LBB87_6: # %else510024; RV64ZVE32F-NEXT: andi a2, a1, 810025; RV64ZVE32F-NEXT: beqz a2, .LBB87_810026; RV64ZVE32F-NEXT: # %bb.7: # %cond.load710027; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma10028; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 110029; RV64ZVE32F-NEXT: vmv.x.s a2, v910030; RV64ZVE32F-NEXT: slli a2, a2, 210031; RV64ZVE32F-NEXT: add a2, a0, a210032; RV64ZVE32F-NEXT: flw fa5, 0(a2)10033; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma10034; RV64ZVE32F-NEXT: vfmv.s.f v9, fa510035; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma10036; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 310037; RV64ZVE32F-NEXT: .LBB87_8: # %else810038; RV64ZVE32F-NEXT: andi a2, a1, 1610039; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma10040; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 410041; RV64ZVE32F-NEXT: beqz a2, .LBB87_1010042; RV64ZVE32F-NEXT: # %bb.9: # %cond.load1010043; RV64ZVE32F-NEXT: vmv.x.s a2, v810044; RV64ZVE32F-NEXT: slli a2, a2, 210045; RV64ZVE32F-NEXT: add a2, a0, a210046; RV64ZVE32F-NEXT: flw fa5, 0(a2)10047; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma10048; RV64ZVE32F-NEXT: vfmv.s.f v12, fa510049; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma10050; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 410051; RV64ZVE32F-NEXT: .LBB87_10: # %else1110052; RV64ZVE32F-NEXT: andi a2, a1, 3210053; RV64ZVE32F-NEXT: beqz a2, .LBB87_1210054; RV64ZVE32F-NEXT: # %bb.11: # %cond.load1310055; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma10056; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 110057; RV64ZVE32F-NEXT: vmv.x.s a2, v910058; RV64ZVE32F-NEXT: slli a2, a2, 210059; RV64ZVE32F-NEXT: add a2, a0, a210060; RV64ZVE32F-NEXT: flw fa5, 0(a2)10061; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma10062; RV64ZVE32F-NEXT: vfmv.s.f v12, fa510063; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma10064; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 510065; RV64ZVE32F-NEXT: .LBB87_12: # %else1410066; RV64ZVE32F-NEXT: andi a2, a1, 6410067; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma10068; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 210069; RV64ZVE32F-NEXT: beqz a2, .LBB87_1410070; RV64ZVE32F-NEXT: # %bb.13: # %cond.load1610071; RV64ZVE32F-NEXT: vmv.x.s a2, v810072; RV64ZVE32F-NEXT: slli a2, a2, 210073; RV64ZVE32F-NEXT: add a2, a0, a210074; RV64ZVE32F-NEXT: flw fa5, 0(a2)10075; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma10076; RV64ZVE32F-NEXT: vfmv.s.f v12, fa510077; RV64ZVE32F-NEXT: vsetivli zero, 7, e32, m2, tu, ma10078; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 610079; RV64ZVE32F-NEXT: .LBB87_14: # %else1710080; RV64ZVE32F-NEXT: andi a1, a1, -12810081; RV64ZVE32F-NEXT: beqz a1, .LBB87_1610082; RV64ZVE32F-NEXT: # %bb.15: # %cond.load1910083; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma10084; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 110085; RV64ZVE32F-NEXT: vmv.x.s a1, v810086; RV64ZVE32F-NEXT: slli a1, a1, 210087; RV64ZVE32F-NEXT: add a0, a0, a110088; RV64ZVE32F-NEXT: flw fa5, 0(a0)10089; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma10090; RV64ZVE32F-NEXT: vfmv.s.f v8, fa510091; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma10092; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 710093; RV64ZVE32F-NEXT: .LBB87_16: # %else2010094; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma10095; RV64ZVE32F-NEXT: vmv2r.v v8, v1010096; RV64ZVE32F-NEXT: ret10097 %ptrs = getelementptr inbounds float, ptr %base, <8 x i16> %idxs10098 %v = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> %m, <8 x float> %passthru)10099 ret <8 x float> %v10100}10101 10102define <8 x float> @mgather_baseidx_sext_v8i16_v8f32(ptr %base, <8 x i16> %idxs, <8 x i1> %m, <8 x float> %passthru) {10103; RV32-LABEL: mgather_baseidx_sext_v8i16_v8f32:10104; RV32: # %bb.0:10105; RV32-NEXT: li a1, 410106; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma10107; RV32-NEXT: vwmulsu.vx v12, v8, a110108; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, mu10109; RV32-NEXT: vluxei32.v v10, (a0), v12, v0.t10110; RV32-NEXT: vmv.v.v v8, v1010111; RV32-NEXT: ret10112;10113; RV64V-LABEL: mgather_baseidx_sext_v8i16_v8f32:10114; RV64V: # %bb.0:10115; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma10116; RV64V-NEXT: vsext.vf4 v12, v810117; RV64V-NEXT: vsll.vi v12, v12, 210118; RV64V-NEXT: vsetvli zero, zero, e32, m2, ta, mu10119; RV64V-NEXT: vluxei64.v v10, (a0), v12, v0.t10120; RV64V-NEXT: vmv.v.v v8, v1010121; RV64V-NEXT: ret10122;10123; RV64ZVE32F-LABEL: mgather_baseidx_sext_v8i16_v8f32:10124; RV64ZVE32F: # %bb.0:10125; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma10126; RV64ZVE32F-NEXT: vmv.x.s a1, v010127; RV64ZVE32F-NEXT: andi a2, a1, 110128; RV64ZVE32F-NEXT: beqz a2, .LBB88_210129; RV64ZVE32F-NEXT: # %bb.1: # %cond.load10130; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma10131; RV64ZVE32F-NEXT: vmv.x.s a2, v810132; RV64ZVE32F-NEXT: slli a2, a2, 210133; RV64ZVE32F-NEXT: add a2, a0, a210134; RV64ZVE32F-NEXT: flw fa5, 0(a2)10135; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma10136; RV64ZVE32F-NEXT: vfmv.s.f v10, fa510137; RV64ZVE32F-NEXT: .LBB88_2: # %else10138; RV64ZVE32F-NEXT: andi a2, a1, 210139; RV64ZVE32F-NEXT: beqz a2, .LBB88_410140; RV64ZVE32F-NEXT: # %bb.3: # %cond.load110141; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma10142; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 110143; RV64ZVE32F-NEXT: vmv.x.s a2, v910144; RV64ZVE32F-NEXT: slli a2, a2, 210145; RV64ZVE32F-NEXT: add a2, a0, a210146; RV64ZVE32F-NEXT: flw fa5, 0(a2)10147; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma10148; RV64ZVE32F-NEXT: vfmv.s.f v9, fa510149; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma10150; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 110151; RV64ZVE32F-NEXT: .LBB88_4: # %else210152; RV64ZVE32F-NEXT: andi a2, a1, 410153; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma10154; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 210155; RV64ZVE32F-NEXT: beqz a2, .LBB88_610156; RV64ZVE32F-NEXT: # %bb.5: # %cond.load410157; RV64ZVE32F-NEXT: vmv.x.s a2, v910158; RV64ZVE32F-NEXT: slli a2, a2, 210159; RV64ZVE32F-NEXT: add a2, a0, a210160; RV64ZVE32F-NEXT: flw fa5, 0(a2)10161; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma10162; RV64ZVE32F-NEXT: vfmv.s.f v12, fa510163; RV64ZVE32F-NEXT: vsetivli zero, 3, e32, m1, tu, ma10164; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 210165; RV64ZVE32F-NEXT: .LBB88_6: # %else510166; RV64ZVE32F-NEXT: andi a2, a1, 810167; RV64ZVE32F-NEXT: beqz a2, .LBB88_810168; RV64ZVE32F-NEXT: # %bb.7: # %cond.load710169; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma10170; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 110171; RV64ZVE32F-NEXT: vmv.x.s a2, v910172; RV64ZVE32F-NEXT: slli a2, a2, 210173; RV64ZVE32F-NEXT: add a2, a0, a210174; RV64ZVE32F-NEXT: flw fa5, 0(a2)10175; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma10176; RV64ZVE32F-NEXT: vfmv.s.f v9, fa510177; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma10178; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 310179; RV64ZVE32F-NEXT: .LBB88_8: # %else810180; RV64ZVE32F-NEXT: andi a2, a1, 1610181; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma10182; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 410183; RV64ZVE32F-NEXT: beqz a2, .LBB88_1010184; RV64ZVE32F-NEXT: # %bb.9: # %cond.load1010185; RV64ZVE32F-NEXT: vmv.x.s a2, v810186; RV64ZVE32F-NEXT: slli a2, a2, 210187; RV64ZVE32F-NEXT: add a2, a0, a210188; RV64ZVE32F-NEXT: flw fa5, 0(a2)10189; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma10190; RV64ZVE32F-NEXT: vfmv.s.f v12, fa510191; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma10192; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 410193; RV64ZVE32F-NEXT: .LBB88_10: # %else1110194; RV64ZVE32F-NEXT: andi a2, a1, 3210195; RV64ZVE32F-NEXT: beqz a2, .LBB88_1210196; RV64ZVE32F-NEXT: # %bb.11: # %cond.load1310197; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma10198; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 110199; RV64ZVE32F-NEXT: vmv.x.s a2, v910200; RV64ZVE32F-NEXT: slli a2, a2, 210201; RV64ZVE32F-NEXT: add a2, a0, a210202; RV64ZVE32F-NEXT: flw fa5, 0(a2)10203; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma10204; RV64ZVE32F-NEXT: vfmv.s.f v12, fa510205; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma10206; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 510207; RV64ZVE32F-NEXT: .LBB88_12: # %else1410208; RV64ZVE32F-NEXT: andi a2, a1, 6410209; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma10210; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 210211; RV64ZVE32F-NEXT: beqz a2, .LBB88_1410212; RV64ZVE32F-NEXT: # %bb.13: # %cond.load1610213; RV64ZVE32F-NEXT: vmv.x.s a2, v810214; RV64ZVE32F-NEXT: slli a2, a2, 210215; RV64ZVE32F-NEXT: add a2, a0, a210216; RV64ZVE32F-NEXT: flw fa5, 0(a2)10217; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma10218; RV64ZVE32F-NEXT: vfmv.s.f v12, fa510219; RV64ZVE32F-NEXT: vsetivli zero, 7, e32, m2, tu, ma10220; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 610221; RV64ZVE32F-NEXT: .LBB88_14: # %else1710222; RV64ZVE32F-NEXT: andi a1, a1, -12810223; RV64ZVE32F-NEXT: beqz a1, .LBB88_1610224; RV64ZVE32F-NEXT: # %bb.15: # %cond.load1910225; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma10226; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 110227; RV64ZVE32F-NEXT: vmv.x.s a1, v810228; RV64ZVE32F-NEXT: slli a1, a1, 210229; RV64ZVE32F-NEXT: add a0, a0, a110230; RV64ZVE32F-NEXT: flw fa5, 0(a0)10231; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma10232; RV64ZVE32F-NEXT: vfmv.s.f v8, fa510233; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma10234; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 710235; RV64ZVE32F-NEXT: .LBB88_16: # %else2010236; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma10237; RV64ZVE32F-NEXT: vmv2r.v v8, v1010238; RV64ZVE32F-NEXT: ret10239 %eidxs = sext <8 x i16> %idxs to <8 x i32>10240 %ptrs = getelementptr inbounds float, ptr %base, <8 x i32> %eidxs10241 %v = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> %m, <8 x float> %passthru)10242 ret <8 x float> %v10243}10244 10245define <8 x float> @mgather_baseidx_zext_v8i16_v8f32(ptr %base, <8 x i16> %idxs, <8 x i1> %m, <8 x float> %passthru) {10246; RV32-LABEL: mgather_baseidx_zext_v8i16_v8f32:10247; RV32: # %bb.0:10248; RV32-NEXT: li a1, 410249; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma10250; RV32-NEXT: vwmulu.vx v12, v8, a110251; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, mu10252; RV32-NEXT: vluxei32.v v10, (a0), v12, v0.t10253; RV32-NEXT: vmv.v.v v8, v1010254; RV32-NEXT: ret10255;10256; RV64V-LABEL: mgather_baseidx_zext_v8i16_v8f32:10257; RV64V: # %bb.0:10258; RV64V-NEXT: li a1, 410259; RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, ma10260; RV64V-NEXT: vwmulu.vx v12, v8, a110261; RV64V-NEXT: vsetvli zero, zero, e32, m2, ta, mu10262; RV64V-NEXT: vluxei32.v v10, (a0), v12, v0.t10263; RV64V-NEXT: vmv.v.v v8, v1010264; RV64V-NEXT: ret10265;10266; RV64ZVE32F-LABEL: mgather_baseidx_zext_v8i16_v8f32:10267; RV64ZVE32F: # %bb.0:10268; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma10269; RV64ZVE32F-NEXT: vmv.x.s a1, v010270; RV64ZVE32F-NEXT: andi a2, a1, 110271; RV64ZVE32F-NEXT: beqz a2, .LBB89_210272; RV64ZVE32F-NEXT: # %bb.1: # %cond.load10273; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma10274; RV64ZVE32F-NEXT: vmv.x.s a2, v810275; RV64ZVE32F-NEXT: slli a2, a2, 4810276; RV64ZVE32F-NEXT: srli a2, a2, 4610277; RV64ZVE32F-NEXT: add a2, a0, a210278; RV64ZVE32F-NEXT: flw fa5, 0(a2)10279; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma10280; RV64ZVE32F-NEXT: vfmv.s.f v10, fa510281; RV64ZVE32F-NEXT: .LBB89_2: # %else10282; RV64ZVE32F-NEXT: andi a2, a1, 210283; RV64ZVE32F-NEXT: beqz a2, .LBB89_410284; RV64ZVE32F-NEXT: # %bb.3: # %cond.load110285; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma10286; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 110287; RV64ZVE32F-NEXT: vmv.x.s a2, v910288; RV64ZVE32F-NEXT: slli a2, a2, 4810289; RV64ZVE32F-NEXT: srli a2, a2, 4610290; RV64ZVE32F-NEXT: add a2, a0, a210291; RV64ZVE32F-NEXT: flw fa5, 0(a2)10292; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma10293; RV64ZVE32F-NEXT: vfmv.s.f v9, fa510294; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma10295; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 110296; RV64ZVE32F-NEXT: .LBB89_4: # %else210297; RV64ZVE32F-NEXT: andi a2, a1, 410298; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma10299; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 210300; RV64ZVE32F-NEXT: beqz a2, .LBB89_610301; RV64ZVE32F-NEXT: # %bb.5: # %cond.load410302; RV64ZVE32F-NEXT: vmv.x.s a2, v910303; RV64ZVE32F-NEXT: slli a2, a2, 4810304; RV64ZVE32F-NEXT: srli a2, a2, 4610305; RV64ZVE32F-NEXT: add a2, a0, a210306; RV64ZVE32F-NEXT: flw fa5, 0(a2)10307; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma10308; RV64ZVE32F-NEXT: vfmv.s.f v12, fa510309; RV64ZVE32F-NEXT: vsetivli zero, 3, e32, m1, tu, ma10310; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 210311; RV64ZVE32F-NEXT: .LBB89_6: # %else510312; RV64ZVE32F-NEXT: andi a2, a1, 810313; RV64ZVE32F-NEXT: beqz a2, .LBB89_810314; RV64ZVE32F-NEXT: # %bb.7: # %cond.load710315; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma10316; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 110317; RV64ZVE32F-NEXT: vmv.x.s a2, v910318; RV64ZVE32F-NEXT: slli a2, a2, 4810319; RV64ZVE32F-NEXT: srli a2, a2, 4610320; RV64ZVE32F-NEXT: add a2, a0, a210321; RV64ZVE32F-NEXT: flw fa5, 0(a2)10322; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma10323; RV64ZVE32F-NEXT: vfmv.s.f v9, fa510324; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma10325; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 310326; RV64ZVE32F-NEXT: .LBB89_8: # %else810327; RV64ZVE32F-NEXT: andi a2, a1, 1610328; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma10329; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 410330; RV64ZVE32F-NEXT: beqz a2, .LBB89_1010331; RV64ZVE32F-NEXT: # %bb.9: # %cond.load1010332; RV64ZVE32F-NEXT: vmv.x.s a2, v810333; RV64ZVE32F-NEXT: slli a2, a2, 4810334; RV64ZVE32F-NEXT: srli a2, a2, 4610335; RV64ZVE32F-NEXT: add a2, a0, a210336; RV64ZVE32F-NEXT: flw fa5, 0(a2)10337; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma10338; RV64ZVE32F-NEXT: vfmv.s.f v12, fa510339; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma10340; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 410341; RV64ZVE32F-NEXT: .LBB89_10: # %else1110342; RV64ZVE32F-NEXT: andi a2, a1, 3210343; RV64ZVE32F-NEXT: beqz a2, .LBB89_1210344; RV64ZVE32F-NEXT: # %bb.11: # %cond.load1310345; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma10346; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 110347; RV64ZVE32F-NEXT: vmv.x.s a2, v910348; RV64ZVE32F-NEXT: slli a2, a2, 4810349; RV64ZVE32F-NEXT: srli a2, a2, 4610350; RV64ZVE32F-NEXT: add a2, a0, a210351; RV64ZVE32F-NEXT: flw fa5, 0(a2)10352; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma10353; RV64ZVE32F-NEXT: vfmv.s.f v12, fa510354; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma10355; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 510356; RV64ZVE32F-NEXT: .LBB89_12: # %else1410357; RV64ZVE32F-NEXT: andi a2, a1, 6410358; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma10359; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 210360; RV64ZVE32F-NEXT: beqz a2, .LBB89_1410361; RV64ZVE32F-NEXT: # %bb.13: # %cond.load1610362; RV64ZVE32F-NEXT: vmv.x.s a2, v810363; RV64ZVE32F-NEXT: slli a2, a2, 4810364; RV64ZVE32F-NEXT: srli a2, a2, 4610365; RV64ZVE32F-NEXT: add a2, a0, a210366; RV64ZVE32F-NEXT: flw fa5, 0(a2)10367; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma10368; RV64ZVE32F-NEXT: vfmv.s.f v12, fa510369; RV64ZVE32F-NEXT: vsetivli zero, 7, e32, m2, tu, ma10370; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 610371; RV64ZVE32F-NEXT: .LBB89_14: # %else1710372; RV64ZVE32F-NEXT: andi a1, a1, -12810373; RV64ZVE32F-NEXT: beqz a1, .LBB89_1610374; RV64ZVE32F-NEXT: # %bb.15: # %cond.load1910375; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma10376; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 110377; RV64ZVE32F-NEXT: vmv.x.s a1, v810378; RV64ZVE32F-NEXT: slli a1, a1, 4810379; RV64ZVE32F-NEXT: srli a1, a1, 4610380; RV64ZVE32F-NEXT: add a0, a0, a110381; RV64ZVE32F-NEXT: flw fa5, 0(a0)10382; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma10383; RV64ZVE32F-NEXT: vfmv.s.f v8, fa510384; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma10385; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 710386; RV64ZVE32F-NEXT: .LBB89_16: # %else2010387; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma10388; RV64ZVE32F-NEXT: vmv2r.v v8, v1010389; RV64ZVE32F-NEXT: ret10390 %eidxs = zext <8 x i16> %idxs to <8 x i32>10391 %ptrs = getelementptr inbounds float, ptr %base, <8 x i32> %eidxs10392 %v = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> %m, <8 x float> %passthru)10393 ret <8 x float> %v10394}10395 10396define <8 x float> @mgather_baseidx_v8f32(ptr %base, <8 x i32> %idxs, <8 x i1> %m, <8 x float> %passthru) {10397; RV32-LABEL: mgather_baseidx_v8f32:10398; RV32: # %bb.0:10399; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu10400; RV32-NEXT: vsll.vi v8, v8, 210401; RV32-NEXT: vluxei32.v v10, (a0), v8, v0.t10402; RV32-NEXT: vmv.v.v v8, v1010403; RV32-NEXT: ret10404;10405; RV64V-LABEL: mgather_baseidx_v8f32:10406; RV64V: # %bb.0:10407; RV64V-NEXT: li a1, 410408; RV64V-NEXT: vsetivli zero, 8, e32, m2, ta, mu10409; RV64V-NEXT: vwmulsu.vx v12, v8, a110410; RV64V-NEXT: vluxei64.v v10, (a0), v12, v0.t10411; RV64V-NEXT: vmv.v.v v8, v1010412; RV64V-NEXT: ret10413;10414; RV64ZVE32F-LABEL: mgather_baseidx_v8f32:10415; RV64ZVE32F: # %bb.0:10416; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma10417; RV64ZVE32F-NEXT: vmv.x.s a1, v010418; RV64ZVE32F-NEXT: andi a2, a1, 110419; RV64ZVE32F-NEXT: beqz a2, .LBB90_210420; RV64ZVE32F-NEXT: # %bb.1: # %cond.load10421; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma10422; RV64ZVE32F-NEXT: vmv.x.s a2, v810423; RV64ZVE32F-NEXT: slli a2, a2, 210424; RV64ZVE32F-NEXT: add a2, a0, a210425; RV64ZVE32F-NEXT: flw fa5, 0(a2)10426; RV64ZVE32F-NEXT: vfmv.s.f v10, fa510427; RV64ZVE32F-NEXT: .LBB90_2: # %else10428; RV64ZVE32F-NEXT: andi a2, a1, 210429; RV64ZVE32F-NEXT: beqz a2, .LBB90_410430; RV64ZVE32F-NEXT: # %bb.3: # %cond.load110431; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma10432; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 110433; RV64ZVE32F-NEXT: vmv.x.s a2, v1210434; RV64ZVE32F-NEXT: slli a2, a2, 210435; RV64ZVE32F-NEXT: add a2, a0, a210436; RV64ZVE32F-NEXT: flw fa5, 0(a2)10437; RV64ZVE32F-NEXT: vfmv.s.f v12, fa510438; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 110439; RV64ZVE32F-NEXT: .LBB90_4: # %else210440; RV64ZVE32F-NEXT: andi a2, a1, 410441; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma10442; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 210443; RV64ZVE32F-NEXT: beqz a2, .LBB90_610444; RV64ZVE32F-NEXT: # %bb.5: # %cond.load410445; RV64ZVE32F-NEXT: vmv.x.s a2, v1210446; RV64ZVE32F-NEXT: slli a2, a2, 210447; RV64ZVE32F-NEXT: add a2, a0, a210448; RV64ZVE32F-NEXT: flw fa5, 0(a2)10449; RV64ZVE32F-NEXT: vfmv.s.f v13, fa510450; RV64ZVE32F-NEXT: vsetivli zero, 3, e32, m1, tu, ma10451; RV64ZVE32F-NEXT: vslideup.vi v10, v13, 210452; RV64ZVE32F-NEXT: .LBB90_6: # %else510453; RV64ZVE32F-NEXT: andi a2, a1, 810454; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, ta, ma10455; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 410456; RV64ZVE32F-NEXT: bnez a2, .LBB90_1510457; RV64ZVE32F-NEXT: # %bb.7: # %else810458; RV64ZVE32F-NEXT: andi a2, a1, 1610459; RV64ZVE32F-NEXT: bnez a2, .LBB90_1610460; RV64ZVE32F-NEXT: .LBB90_8: # %else1110461; RV64ZVE32F-NEXT: andi a2, a1, 3210462; RV64ZVE32F-NEXT: beqz a2, .LBB90_1010463; RV64ZVE32F-NEXT: .LBB90_9: # %cond.load1310464; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma10465; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 110466; RV64ZVE32F-NEXT: vmv.x.s a2, v910467; RV64ZVE32F-NEXT: slli a2, a2, 210468; RV64ZVE32F-NEXT: add a2, a0, a210469; RV64ZVE32F-NEXT: flw fa5, 0(a2)10470; RV64ZVE32F-NEXT: vfmv.s.f v12, fa510471; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma10472; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 510473; RV64ZVE32F-NEXT: .LBB90_10: # %else1410474; RV64ZVE32F-NEXT: andi a2, a1, 6410475; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma10476; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 210477; RV64ZVE32F-NEXT: beqz a2, .LBB90_1210478; RV64ZVE32F-NEXT: # %bb.11: # %cond.load1610479; RV64ZVE32F-NEXT: vmv.x.s a2, v810480; RV64ZVE32F-NEXT: slli a2, a2, 210481; RV64ZVE32F-NEXT: add a2, a0, a210482; RV64ZVE32F-NEXT: flw fa5, 0(a2)10483; RV64ZVE32F-NEXT: vfmv.s.f v12, fa510484; RV64ZVE32F-NEXT: vsetivli zero, 7, e32, m2, tu, ma10485; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 610486; RV64ZVE32F-NEXT: .LBB90_12: # %else1710487; RV64ZVE32F-NEXT: andi a1, a1, -12810488; RV64ZVE32F-NEXT: beqz a1, .LBB90_1410489; RV64ZVE32F-NEXT: # %bb.13: # %cond.load1910490; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma10491; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 110492; RV64ZVE32F-NEXT: vmv.x.s a1, v810493; RV64ZVE32F-NEXT: slli a1, a1, 210494; RV64ZVE32F-NEXT: add a0, a0, a110495; RV64ZVE32F-NEXT: flw fa5, 0(a0)10496; RV64ZVE32F-NEXT: vfmv.s.f v8, fa510497; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma10498; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 710499; RV64ZVE32F-NEXT: .LBB90_14: # %else2010500; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma10501; RV64ZVE32F-NEXT: vmv2r.v v8, v1010502; RV64ZVE32F-NEXT: ret10503; RV64ZVE32F-NEXT: .LBB90_15: # %cond.load710504; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma10505; RV64ZVE32F-NEXT: vslidedown.vi v9, v12, 110506; RV64ZVE32F-NEXT: vmv.x.s a2, v910507; RV64ZVE32F-NEXT: slli a2, a2, 210508; RV64ZVE32F-NEXT: add a2, a0, a210509; RV64ZVE32F-NEXT: flw fa5, 0(a2)10510; RV64ZVE32F-NEXT: vfmv.s.f v9, fa510511; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 310512; RV64ZVE32F-NEXT: andi a2, a1, 1610513; RV64ZVE32F-NEXT: beqz a2, .LBB90_810514; RV64ZVE32F-NEXT: .LBB90_16: # %cond.load1010515; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma10516; RV64ZVE32F-NEXT: vmv.x.s a2, v810517; RV64ZVE32F-NEXT: slli a2, a2, 210518; RV64ZVE32F-NEXT: add a2, a0, a210519; RV64ZVE32F-NEXT: flw fa5, 0(a2)10520; RV64ZVE32F-NEXT: vfmv.s.f v12, fa510521; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 410522; RV64ZVE32F-NEXT: andi a2, a1, 3210523; RV64ZVE32F-NEXT: bnez a2, .LBB90_910524; RV64ZVE32F-NEXT: j .LBB90_1010525 %ptrs = getelementptr inbounds float, ptr %base, <8 x i32> %idxs10526 %v = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> %m, <8 x float> %passthru)10527 ret <8 x float> %v10528}10529 10530define <1 x double> @mgather_v1f64(<1 x ptr> %ptrs, <1 x i1> %m, <1 x double> %passthru) {10531; RV32V-LABEL: mgather_v1f64:10532; RV32V: # %bb.0:10533; RV32V-NEXT: vsetivli zero, 1, e64, m1, ta, mu10534; RV32V-NEXT: vluxei32.v v9, (zero), v8, v0.t10535; RV32V-NEXT: vmv.v.v v8, v910536; RV32V-NEXT: ret10537;10538; RV64V-LABEL: mgather_v1f64:10539; RV64V: # %bb.0:10540; RV64V-NEXT: vsetivli zero, 1, e64, m1, ta, mu10541; RV64V-NEXT: vluxei64.v v9, (zero), v8, v0.t10542; RV64V-NEXT: vmv.v.v v8, v910543; RV64V-NEXT: ret10544;10545; RV32ZVE32F-LABEL: mgather_v1f64:10546; RV32ZVE32F: # %bb.0:10547; RV32ZVE32F-NEXT: vsetvli a0, zero, e8, mf4, ta, ma10548; RV32ZVE32F-NEXT: vfirst.m a0, v010549; RV32ZVE32F-NEXT: bnez a0, .LBB91_210550; RV32ZVE32F-NEXT: # %bb.1: # %cond.load10551; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma10552; RV32ZVE32F-NEXT: vmv.x.s a0, v810553; RV32ZVE32F-NEXT: fld fa0, 0(a0)10554; RV32ZVE32F-NEXT: .LBB91_2: # %else10555; RV32ZVE32F-NEXT: ret10556;10557; RV64ZVE32F-LABEL: mgather_v1f64:10558; RV64ZVE32F: # %bb.0:10559; RV64ZVE32F-NEXT: vsetvli a1, zero, e8, mf4, ta, ma10560; RV64ZVE32F-NEXT: vfirst.m a1, v010561; RV64ZVE32F-NEXT: bnez a1, .LBB91_210562; RV64ZVE32F-NEXT: # %bb.1: # %cond.load10563; RV64ZVE32F-NEXT: fld fa0, 0(a0)10564; RV64ZVE32F-NEXT: .LBB91_2: # %else10565; RV64ZVE32F-NEXT: ret10566 %v = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> %ptrs, i32 8, <1 x i1> %m, <1 x double> %passthru)10567 ret <1 x double> %v10568}10569 10570define <2 x double> @mgather_v2f64(<2 x ptr> %ptrs, <2 x i1> %m, <2 x double> %passthru) {10571; RV32V-LABEL: mgather_v2f64:10572; RV32V: # %bb.0:10573; RV32V-NEXT: vsetivli zero, 2, e64, m1, ta, mu10574; RV32V-NEXT: vluxei32.v v9, (zero), v8, v0.t10575; RV32V-NEXT: vmv.v.v v8, v910576; RV32V-NEXT: ret10577;10578; RV64V-LABEL: mgather_v2f64:10579; RV64V: # %bb.0:10580; RV64V-NEXT: vsetivli zero, 2, e64, m1, ta, mu10581; RV64V-NEXT: vluxei64.v v9, (zero), v8, v0.t10582; RV64V-NEXT: vmv.v.v v8, v910583; RV64V-NEXT: ret10584;10585; RV32ZVE32F-LABEL: mgather_v2f64:10586; RV32ZVE32F: # %bb.0:10587; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma10588; RV32ZVE32F-NEXT: vmv.x.s a0, v010589; RV32ZVE32F-NEXT: andi a1, a0, 110590; RV32ZVE32F-NEXT: bnez a1, .LBB92_310591; RV32ZVE32F-NEXT: # %bb.1: # %else10592; RV32ZVE32F-NEXT: andi a0, a0, 210593; RV32ZVE32F-NEXT: bnez a0, .LBB92_410594; RV32ZVE32F-NEXT: .LBB92_2: # %else210595; RV32ZVE32F-NEXT: ret10596; RV32ZVE32F-NEXT: .LBB92_3: # %cond.load10597; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma10598; RV32ZVE32F-NEXT: vmv.x.s a1, v810599; RV32ZVE32F-NEXT: fld fa0, 0(a1)10600; RV32ZVE32F-NEXT: andi a0, a0, 210601; RV32ZVE32F-NEXT: beqz a0, .LBB92_210602; RV32ZVE32F-NEXT: .LBB92_4: # %cond.load110603; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma10604; RV32ZVE32F-NEXT: vslidedown.vi v8, v8, 110605; RV32ZVE32F-NEXT: vmv.x.s a0, v810606; RV32ZVE32F-NEXT: fld fa1, 0(a0)10607; RV32ZVE32F-NEXT: ret10608;10609; RV64ZVE32F-LABEL: mgather_v2f64:10610; RV64ZVE32F: # %bb.0:10611; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma10612; RV64ZVE32F-NEXT: vmv.x.s a2, v010613; RV64ZVE32F-NEXT: andi a3, a2, 110614; RV64ZVE32F-NEXT: bnez a3, .LBB92_310615; RV64ZVE32F-NEXT: # %bb.1: # %else10616; RV64ZVE32F-NEXT: andi a2, a2, 210617; RV64ZVE32F-NEXT: bnez a2, .LBB92_410618; RV64ZVE32F-NEXT: .LBB92_2: # %else210619; RV64ZVE32F-NEXT: ret10620; RV64ZVE32F-NEXT: .LBB92_3: # %cond.load10621; RV64ZVE32F-NEXT: fld fa0, 0(a0)10622; RV64ZVE32F-NEXT: andi a2, a2, 210623; RV64ZVE32F-NEXT: beqz a2, .LBB92_210624; RV64ZVE32F-NEXT: .LBB92_4: # %cond.load110625; RV64ZVE32F-NEXT: fld fa1, 0(a1)10626; RV64ZVE32F-NEXT: ret10627 %v = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> %ptrs, i32 8, <2 x i1> %m, <2 x double> %passthru)10628 ret <2 x double> %v10629}10630 10631define <4 x double> @mgather_v4f64(<4 x ptr> %ptrs, <4 x i1> %m, <4 x double> %passthru) {10632; RV32V-LABEL: mgather_v4f64:10633; RV32V: # %bb.0:10634; RV32V-NEXT: vsetivli zero, 4, e64, m2, ta, mu10635; RV32V-NEXT: vluxei32.v v10, (zero), v8, v0.t10636; RV32V-NEXT: vmv.v.v v8, v1010637; RV32V-NEXT: ret10638;10639; RV64V-LABEL: mgather_v4f64:10640; RV64V: # %bb.0:10641; RV64V-NEXT: vsetivli zero, 4, e64, m2, ta, mu10642; RV64V-NEXT: vluxei64.v v10, (zero), v8, v0.t10643; RV64V-NEXT: vmv.v.v v8, v1010644; RV64V-NEXT: ret10645;10646; RV32ZVE32F-LABEL: mgather_v4f64:10647; RV32ZVE32F: # %bb.0:10648; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma10649; RV32ZVE32F-NEXT: vmv.x.s a1, v010650; RV32ZVE32F-NEXT: andi a2, a1, 110651; RV32ZVE32F-NEXT: bnez a2, .LBB93_610652; RV32ZVE32F-NEXT: # %bb.1: # %else10653; RV32ZVE32F-NEXT: andi a2, a1, 210654; RV32ZVE32F-NEXT: bnez a2, .LBB93_710655; RV32ZVE32F-NEXT: .LBB93_2: # %else210656; RV32ZVE32F-NEXT: andi a2, a1, 410657; RV32ZVE32F-NEXT: bnez a2, .LBB93_810658; RV32ZVE32F-NEXT: .LBB93_3: # %else510659; RV32ZVE32F-NEXT: andi a1, a1, 810660; RV32ZVE32F-NEXT: beqz a1, .LBB93_510661; RV32ZVE32F-NEXT: .LBB93_4: # %cond.load710662; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma10663; RV32ZVE32F-NEXT: vslidedown.vi v8, v8, 310664; RV32ZVE32F-NEXT: vmv.x.s a1, v810665; RV32ZVE32F-NEXT: fld fa3, 0(a1)10666; RV32ZVE32F-NEXT: .LBB93_5: # %else810667; RV32ZVE32F-NEXT: fsd fa0, 0(a0)10668; RV32ZVE32F-NEXT: fsd fa1, 8(a0)10669; RV32ZVE32F-NEXT: fsd fa2, 16(a0)10670; RV32ZVE32F-NEXT: fsd fa3, 24(a0)10671; RV32ZVE32F-NEXT: ret10672; RV32ZVE32F-NEXT: .LBB93_6: # %cond.load10673; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma10674; RV32ZVE32F-NEXT: vmv.x.s a2, v810675; RV32ZVE32F-NEXT: fld fa0, 0(a2)10676; RV32ZVE32F-NEXT: andi a2, a1, 210677; RV32ZVE32F-NEXT: beqz a2, .LBB93_210678; RV32ZVE32F-NEXT: .LBB93_7: # %cond.load110679; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma10680; RV32ZVE32F-NEXT: vslidedown.vi v9, v8, 110681; RV32ZVE32F-NEXT: vmv.x.s a2, v910682; RV32ZVE32F-NEXT: fld fa1, 0(a2)10683; RV32ZVE32F-NEXT: andi a2, a1, 410684; RV32ZVE32F-NEXT: beqz a2, .LBB93_310685; RV32ZVE32F-NEXT: .LBB93_8: # %cond.load410686; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma10687; RV32ZVE32F-NEXT: vslidedown.vi v9, v8, 210688; RV32ZVE32F-NEXT: vmv.x.s a2, v910689; RV32ZVE32F-NEXT: fld fa2, 0(a2)10690; RV32ZVE32F-NEXT: andi a1, a1, 810691; RV32ZVE32F-NEXT: bnez a1, .LBB93_410692; RV32ZVE32F-NEXT: j .LBB93_510693;10694; RV64ZVE32F-LABEL: mgather_v4f64:10695; RV64ZVE32F: # %bb.0:10696; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma10697; RV64ZVE32F-NEXT: vmv.x.s a2, v010698; RV64ZVE32F-NEXT: andi a3, a2, 110699; RV64ZVE32F-NEXT: bnez a3, .LBB93_610700; RV64ZVE32F-NEXT: # %bb.1: # %else10701; RV64ZVE32F-NEXT: andi a3, a2, 210702; RV64ZVE32F-NEXT: bnez a3, .LBB93_710703; RV64ZVE32F-NEXT: .LBB93_2: # %else210704; RV64ZVE32F-NEXT: andi a3, a2, 410705; RV64ZVE32F-NEXT: bnez a3, .LBB93_810706; RV64ZVE32F-NEXT: .LBB93_3: # %else510707; RV64ZVE32F-NEXT: andi a2, a2, 810708; RV64ZVE32F-NEXT: beqz a2, .LBB93_510709; RV64ZVE32F-NEXT: .LBB93_4: # %cond.load710710; RV64ZVE32F-NEXT: ld a1, 24(a1)10711; RV64ZVE32F-NEXT: fld fa3, 0(a1)10712; RV64ZVE32F-NEXT: .LBB93_5: # %else810713; RV64ZVE32F-NEXT: fsd fa0, 0(a0)10714; RV64ZVE32F-NEXT: fsd fa1, 8(a0)10715; RV64ZVE32F-NEXT: fsd fa2, 16(a0)10716; RV64ZVE32F-NEXT: fsd fa3, 24(a0)10717; RV64ZVE32F-NEXT: ret10718; RV64ZVE32F-NEXT: .LBB93_6: # %cond.load10719; RV64ZVE32F-NEXT: ld a3, 0(a1)10720; RV64ZVE32F-NEXT: fld fa0, 0(a3)10721; RV64ZVE32F-NEXT: andi a3, a2, 210722; RV64ZVE32F-NEXT: beqz a3, .LBB93_210723; RV64ZVE32F-NEXT: .LBB93_7: # %cond.load110724; RV64ZVE32F-NEXT: ld a3, 8(a1)10725; RV64ZVE32F-NEXT: fld fa1, 0(a3)10726; RV64ZVE32F-NEXT: andi a3, a2, 410727; RV64ZVE32F-NEXT: beqz a3, .LBB93_310728; RV64ZVE32F-NEXT: .LBB93_8: # %cond.load410729; RV64ZVE32F-NEXT: ld a3, 16(a1)10730; RV64ZVE32F-NEXT: fld fa2, 0(a3)10731; RV64ZVE32F-NEXT: andi a2, a2, 810732; RV64ZVE32F-NEXT: bnez a2, .LBB93_410733; RV64ZVE32F-NEXT: j .LBB93_510734 %v = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> %ptrs, i32 8, <4 x i1> %m, <4 x double> %passthru)10735 ret <4 x double> %v10736}10737 10738define <4 x double> @mgather_truemask_v4f64(<4 x ptr> %ptrs, <4 x double> %passthru) {10739; RV32V-LABEL: mgather_truemask_v4f64:10740; RV32V: # %bb.0:10741; RV32V-NEXT: vsetivli zero, 4, e64, m2, ta, ma10742; RV32V-NEXT: vmv1r.v v10, v810743; RV32V-NEXT: vluxei32.v v8, (zero), v1010744; RV32V-NEXT: ret10745;10746; RV64V-LABEL: mgather_truemask_v4f64:10747; RV64V: # %bb.0:10748; RV64V-NEXT: vsetivli zero, 4, e64, m2, ta, ma10749; RV64V-NEXT: vluxei64.v v8, (zero), v810750; RV64V-NEXT: ret10751;10752; RV32ZVE32F-LABEL: mgather_truemask_v4f64:10753; RV32ZVE32F: # %bb.0:10754; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma10755; RV32ZVE32F-NEXT: vmv.x.s a1, v810756; RV32ZVE32F-NEXT: vslidedown.vi v9, v8, 110757; RV32ZVE32F-NEXT: fld fa5, 0(a1)10758; RV32ZVE32F-NEXT: vmv.x.s a1, v910759; RV32ZVE32F-NEXT: vslidedown.vi v9, v8, 210760; RV32ZVE32F-NEXT: vslidedown.vi v8, v8, 310761; RV32ZVE32F-NEXT: fld fa4, 0(a1)10762; RV32ZVE32F-NEXT: vmv.x.s a1, v910763; RV32ZVE32F-NEXT: fld fa3, 0(a1)10764; RV32ZVE32F-NEXT: vmv.x.s a1, v810765; RV32ZVE32F-NEXT: fld fa2, 0(a1)10766; RV32ZVE32F-NEXT: fsd fa5, 0(a0)10767; RV32ZVE32F-NEXT: fsd fa4, 8(a0)10768; RV32ZVE32F-NEXT: fsd fa3, 16(a0)10769; RV32ZVE32F-NEXT: fsd fa2, 24(a0)10770; RV32ZVE32F-NEXT: ret10771;10772; RV64ZVE32F-LABEL: mgather_truemask_v4f64:10773; RV64ZVE32F: # %bb.0:10774; RV64ZVE32F-NEXT: ld a2, 0(a1)10775; RV64ZVE32F-NEXT: ld a3, 8(a1)10776; RV64ZVE32F-NEXT: ld a4, 16(a1)10777; RV64ZVE32F-NEXT: ld a1, 24(a1)10778; RV64ZVE32F-NEXT: fld fa5, 0(a2)10779; RV64ZVE32F-NEXT: fld fa4, 0(a3)10780; RV64ZVE32F-NEXT: fld fa3, 0(a4)10781; RV64ZVE32F-NEXT: fld fa2, 0(a1)10782; RV64ZVE32F-NEXT: fsd fa5, 0(a0)10783; RV64ZVE32F-NEXT: fsd fa4, 8(a0)10784; RV64ZVE32F-NEXT: fsd fa3, 16(a0)10785; RV64ZVE32F-NEXT: fsd fa2, 24(a0)10786; RV64ZVE32F-NEXT: ret10787 %v = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> %ptrs, i32 8, <4 x i1> splat (i1 1), <4 x double> %passthru)10788 ret <4 x double> %v10789}10790 10791define <4 x double> @mgather_falsemask_v4f64(<4 x ptr> %ptrs, <4 x double> %passthru) {10792; RV32V-LABEL: mgather_falsemask_v4f64:10793; RV32V: # %bb.0:10794; RV32V-NEXT: vsetivli zero, 1, e8, m1, ta, ma10795; RV32V-NEXT: vmv2r.v v8, v1010796; RV32V-NEXT: ret10797;10798; RV64V-LABEL: mgather_falsemask_v4f64:10799; RV64V: # %bb.0:10800; RV64V-NEXT: vsetivli zero, 1, e8, m1, ta, ma10801; RV64V-NEXT: vmv2r.v v8, v1010802; RV64V-NEXT: ret10803;10804; RV32ZVE32F-LABEL: mgather_falsemask_v4f64:10805; RV32ZVE32F: # %bb.0:10806; RV32ZVE32F-NEXT: fsd fa0, 0(a0)10807; RV32ZVE32F-NEXT: fsd fa1, 8(a0)10808; RV32ZVE32F-NEXT: fsd fa2, 16(a0)10809; RV32ZVE32F-NEXT: fsd fa3, 24(a0)10810; RV32ZVE32F-NEXT: ret10811;10812; RV64ZVE32F-LABEL: mgather_falsemask_v4f64:10813; RV64ZVE32F: # %bb.0:10814; RV64ZVE32F-NEXT: fsd fa0, 0(a0)10815; RV64ZVE32F-NEXT: fsd fa1, 8(a0)10816; RV64ZVE32F-NEXT: fsd fa2, 16(a0)10817; RV64ZVE32F-NEXT: fsd fa3, 24(a0)10818; RV64ZVE32F-NEXT: ret10819 %v = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> %ptrs, i32 8, <4 x i1> zeroinitializer, <4 x double> %passthru)10820 ret <4 x double> %v10821}10822 10823define <8 x double> @mgather_v8f64(<8 x ptr> %ptrs, <8 x i1> %m, <8 x double> %passthru) {10824; RV32V-LABEL: mgather_v8f64:10825; RV32V: # %bb.0:10826; RV32V-NEXT: vsetivli zero, 8, e64, m4, ta, mu10827; RV32V-NEXT: vluxei32.v v12, (zero), v8, v0.t10828; RV32V-NEXT: vmv.v.v v8, v1210829; RV32V-NEXT: ret10830;10831; RV64V-LABEL: mgather_v8f64:10832; RV64V: # %bb.0:10833; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, mu10834; RV64V-NEXT: vluxei64.v v12, (zero), v8, v0.t10835; RV64V-NEXT: vmv.v.v v8, v1210836; RV64V-NEXT: ret10837;10838; RV32ZVE32F-LABEL: mgather_v8f64:10839; RV32ZVE32F: # %bb.0:10840; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma10841; RV32ZVE32F-NEXT: vmv.x.s a1, v010842; RV32ZVE32F-NEXT: andi a2, a1, 110843; RV32ZVE32F-NEXT: bnez a2, .LBB96_1010844; RV32ZVE32F-NEXT: # %bb.1: # %else10845; RV32ZVE32F-NEXT: andi a2, a1, 210846; RV32ZVE32F-NEXT: bnez a2, .LBB96_1110847; RV32ZVE32F-NEXT: .LBB96_2: # %else210848; RV32ZVE32F-NEXT: andi a2, a1, 410849; RV32ZVE32F-NEXT: bnez a2, .LBB96_1210850; RV32ZVE32F-NEXT: .LBB96_3: # %else510851; RV32ZVE32F-NEXT: andi a2, a1, 810852; RV32ZVE32F-NEXT: bnez a2, .LBB96_1310853; RV32ZVE32F-NEXT: .LBB96_4: # %else810854; RV32ZVE32F-NEXT: andi a2, a1, 1610855; RV32ZVE32F-NEXT: bnez a2, .LBB96_1410856; RV32ZVE32F-NEXT: .LBB96_5: # %else1110857; RV32ZVE32F-NEXT: andi a2, a1, 3210858; RV32ZVE32F-NEXT: bnez a2, .LBB96_1510859; RV32ZVE32F-NEXT: .LBB96_6: # %else1410860; RV32ZVE32F-NEXT: andi a2, a1, 6410861; RV32ZVE32F-NEXT: bnez a2, .LBB96_1610862; RV32ZVE32F-NEXT: .LBB96_7: # %else1710863; RV32ZVE32F-NEXT: andi a1, a1, -12810864; RV32ZVE32F-NEXT: beqz a1, .LBB96_910865; RV32ZVE32F-NEXT: .LBB96_8: # %cond.load1910866; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma10867; RV32ZVE32F-NEXT: vslidedown.vi v8, v8, 710868; RV32ZVE32F-NEXT: vmv.x.s a1, v810869; RV32ZVE32F-NEXT: fld fa7, 0(a1)10870; RV32ZVE32F-NEXT: .LBB96_9: # %else2010871; RV32ZVE32F-NEXT: fsd fa0, 0(a0)10872; RV32ZVE32F-NEXT: fsd fa1, 8(a0)10873; RV32ZVE32F-NEXT: fsd fa2, 16(a0)10874; RV32ZVE32F-NEXT: fsd fa3, 24(a0)10875; RV32ZVE32F-NEXT: fsd fa4, 32(a0)10876; RV32ZVE32F-NEXT: fsd fa5, 40(a0)10877; RV32ZVE32F-NEXT: fsd fa6, 48(a0)10878; RV32ZVE32F-NEXT: fsd fa7, 56(a0)10879; RV32ZVE32F-NEXT: ret10880; RV32ZVE32F-NEXT: .LBB96_10: # %cond.load10881; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma10882; RV32ZVE32F-NEXT: vmv.x.s a2, v810883; RV32ZVE32F-NEXT: fld fa0, 0(a2)10884; RV32ZVE32F-NEXT: andi a2, a1, 210885; RV32ZVE32F-NEXT: beqz a2, .LBB96_210886; RV32ZVE32F-NEXT: .LBB96_11: # %cond.load110887; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma10888; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 110889; RV32ZVE32F-NEXT: vmv.x.s a2, v1010890; RV32ZVE32F-NEXT: fld fa1, 0(a2)10891; RV32ZVE32F-NEXT: andi a2, a1, 410892; RV32ZVE32F-NEXT: beqz a2, .LBB96_310893; RV32ZVE32F-NEXT: .LBB96_12: # %cond.load410894; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma10895; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 210896; RV32ZVE32F-NEXT: vmv.x.s a2, v1010897; RV32ZVE32F-NEXT: fld fa2, 0(a2)10898; RV32ZVE32F-NEXT: andi a2, a1, 810899; RV32ZVE32F-NEXT: beqz a2, .LBB96_410900; RV32ZVE32F-NEXT: .LBB96_13: # %cond.load710901; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma10902; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 310903; RV32ZVE32F-NEXT: vmv.x.s a2, v1010904; RV32ZVE32F-NEXT: fld fa3, 0(a2)10905; RV32ZVE32F-NEXT: andi a2, a1, 1610906; RV32ZVE32F-NEXT: beqz a2, .LBB96_510907; RV32ZVE32F-NEXT: .LBB96_14: # %cond.load1010908; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma10909; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 410910; RV32ZVE32F-NEXT: vmv.x.s a2, v1010911; RV32ZVE32F-NEXT: fld fa4, 0(a2)10912; RV32ZVE32F-NEXT: andi a2, a1, 3210913; RV32ZVE32F-NEXT: beqz a2, .LBB96_610914; RV32ZVE32F-NEXT: .LBB96_15: # %cond.load1310915; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma10916; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 510917; RV32ZVE32F-NEXT: vmv.x.s a2, v1010918; RV32ZVE32F-NEXT: fld fa5, 0(a2)10919; RV32ZVE32F-NEXT: andi a2, a1, 6410920; RV32ZVE32F-NEXT: beqz a2, .LBB96_710921; RV32ZVE32F-NEXT: .LBB96_16: # %cond.load1610922; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma10923; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 610924; RV32ZVE32F-NEXT: vmv.x.s a2, v1010925; RV32ZVE32F-NEXT: fld fa6, 0(a2)10926; RV32ZVE32F-NEXT: andi a1, a1, -12810927; RV32ZVE32F-NEXT: bnez a1, .LBB96_810928; RV32ZVE32F-NEXT: j .LBB96_910929;10930; RV64ZVE32F-LABEL: mgather_v8f64:10931; RV64ZVE32F: # %bb.0:10932; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma10933; RV64ZVE32F-NEXT: vmv.x.s a2, v010934; RV64ZVE32F-NEXT: andi a3, a2, 110935; RV64ZVE32F-NEXT: bnez a3, .LBB96_1010936; RV64ZVE32F-NEXT: # %bb.1: # %else10937; RV64ZVE32F-NEXT: andi a3, a2, 210938; RV64ZVE32F-NEXT: bnez a3, .LBB96_1110939; RV64ZVE32F-NEXT: .LBB96_2: # %else210940; RV64ZVE32F-NEXT: andi a3, a2, 410941; RV64ZVE32F-NEXT: bnez a3, .LBB96_1210942; RV64ZVE32F-NEXT: .LBB96_3: # %else510943; RV64ZVE32F-NEXT: andi a3, a2, 810944; RV64ZVE32F-NEXT: bnez a3, .LBB96_1310945; RV64ZVE32F-NEXT: .LBB96_4: # %else810946; RV64ZVE32F-NEXT: andi a3, a2, 1610947; RV64ZVE32F-NEXT: bnez a3, .LBB96_1410948; RV64ZVE32F-NEXT: .LBB96_5: # %else1110949; RV64ZVE32F-NEXT: andi a3, a2, 3210950; RV64ZVE32F-NEXT: bnez a3, .LBB96_1510951; RV64ZVE32F-NEXT: .LBB96_6: # %else1410952; RV64ZVE32F-NEXT: andi a3, a2, 6410953; RV64ZVE32F-NEXT: bnez a3, .LBB96_1610954; RV64ZVE32F-NEXT: .LBB96_7: # %else1710955; RV64ZVE32F-NEXT: andi a2, a2, -12810956; RV64ZVE32F-NEXT: beqz a2, .LBB96_910957; RV64ZVE32F-NEXT: .LBB96_8: # %cond.load1910958; RV64ZVE32F-NEXT: ld a1, 56(a1)10959; RV64ZVE32F-NEXT: fld fa7, 0(a1)10960; RV64ZVE32F-NEXT: .LBB96_9: # %else2010961; RV64ZVE32F-NEXT: fsd fa0, 0(a0)10962; RV64ZVE32F-NEXT: fsd fa1, 8(a0)10963; RV64ZVE32F-NEXT: fsd fa2, 16(a0)10964; RV64ZVE32F-NEXT: fsd fa3, 24(a0)10965; RV64ZVE32F-NEXT: fsd fa4, 32(a0)10966; RV64ZVE32F-NEXT: fsd fa5, 40(a0)10967; RV64ZVE32F-NEXT: fsd fa6, 48(a0)10968; RV64ZVE32F-NEXT: fsd fa7, 56(a0)10969; RV64ZVE32F-NEXT: ret10970; RV64ZVE32F-NEXT: .LBB96_10: # %cond.load10971; RV64ZVE32F-NEXT: ld a3, 0(a1)10972; RV64ZVE32F-NEXT: fld fa0, 0(a3)10973; RV64ZVE32F-NEXT: andi a3, a2, 210974; RV64ZVE32F-NEXT: beqz a3, .LBB96_210975; RV64ZVE32F-NEXT: .LBB96_11: # %cond.load110976; RV64ZVE32F-NEXT: ld a3, 8(a1)10977; RV64ZVE32F-NEXT: fld fa1, 0(a3)10978; RV64ZVE32F-NEXT: andi a3, a2, 410979; RV64ZVE32F-NEXT: beqz a3, .LBB96_310980; RV64ZVE32F-NEXT: .LBB96_12: # %cond.load410981; RV64ZVE32F-NEXT: ld a3, 16(a1)10982; RV64ZVE32F-NEXT: fld fa2, 0(a3)10983; RV64ZVE32F-NEXT: andi a3, a2, 810984; RV64ZVE32F-NEXT: beqz a3, .LBB96_410985; RV64ZVE32F-NEXT: .LBB96_13: # %cond.load710986; RV64ZVE32F-NEXT: ld a3, 24(a1)10987; RV64ZVE32F-NEXT: fld fa3, 0(a3)10988; RV64ZVE32F-NEXT: andi a3, a2, 1610989; RV64ZVE32F-NEXT: beqz a3, .LBB96_510990; RV64ZVE32F-NEXT: .LBB96_14: # %cond.load1010991; RV64ZVE32F-NEXT: ld a3, 32(a1)10992; RV64ZVE32F-NEXT: fld fa4, 0(a3)10993; RV64ZVE32F-NEXT: andi a3, a2, 3210994; RV64ZVE32F-NEXT: beqz a3, .LBB96_610995; RV64ZVE32F-NEXT: .LBB96_15: # %cond.load1310996; RV64ZVE32F-NEXT: ld a3, 40(a1)10997; RV64ZVE32F-NEXT: fld fa5, 0(a3)10998; RV64ZVE32F-NEXT: andi a3, a2, 6410999; RV64ZVE32F-NEXT: beqz a3, .LBB96_711000; RV64ZVE32F-NEXT: .LBB96_16: # %cond.load1611001; RV64ZVE32F-NEXT: ld a3, 48(a1)11002; RV64ZVE32F-NEXT: fld fa6, 0(a3)11003; RV64ZVE32F-NEXT: andi a2, a2, -12811004; RV64ZVE32F-NEXT: bnez a2, .LBB96_811005; RV64ZVE32F-NEXT: j .LBB96_911006 %v = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> %ptrs, i32 8, <8 x i1> %m, <8 x double> %passthru)11007 ret <8 x double> %v11008}11009 11010define <8 x double> @mgather_baseidx_v8i8_v8f64(ptr %base, <8 x i8> %idxs, <8 x i1> %m, <8 x double> %passthru) {11011; RV32V-LABEL: mgather_baseidx_v8i8_v8f64:11012; RV32V: # %bb.0:11013; RV32V-NEXT: vsetivli zero, 8, e32, m2, ta, ma11014; RV32V-NEXT: vsext.vf4 v10, v811015; RV32V-NEXT: vsll.vi v8, v10, 311016; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, mu11017; RV32V-NEXT: vluxei32.v v12, (a0), v8, v0.t11018; RV32V-NEXT: vmv.v.v v8, v1211019; RV32V-NEXT: ret11020;11021; RV64V-LABEL: mgather_baseidx_v8i8_v8f64:11022; RV64V: # %bb.0:11023; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, mu11024; RV64V-NEXT: vsext.vf8 v16, v811025; RV64V-NEXT: vsll.vi v8, v16, 311026; RV64V-NEXT: vluxei64.v v12, (a0), v8, v0.t11027; RV64V-NEXT: vmv.v.v v8, v1211028; RV64V-NEXT: ret11029;11030; RV32ZVE32F-LABEL: mgather_baseidx_v8i8_v8f64:11031; RV32ZVE32F: # %bb.0:11032; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma11033; RV32ZVE32F-NEXT: vsext.vf4 v10, v811034; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma11035; RV32ZVE32F-NEXT: vmv.x.s a2, v011036; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma11037; RV32ZVE32F-NEXT: vsll.vi v8, v10, 311038; RV32ZVE32F-NEXT: andi a3, a2, 111039; RV32ZVE32F-NEXT: vadd.vx v8, v8, a111040; RV32ZVE32F-NEXT: bnez a3, .LBB97_1011041; RV32ZVE32F-NEXT: # %bb.1: # %else11042; RV32ZVE32F-NEXT: andi a1, a2, 211043; RV32ZVE32F-NEXT: bnez a1, .LBB97_1111044; RV32ZVE32F-NEXT: .LBB97_2: # %else211045; RV32ZVE32F-NEXT: andi a1, a2, 411046; RV32ZVE32F-NEXT: bnez a1, .LBB97_1211047; RV32ZVE32F-NEXT: .LBB97_3: # %else511048; RV32ZVE32F-NEXT: andi a1, a2, 811049; RV32ZVE32F-NEXT: bnez a1, .LBB97_1311050; RV32ZVE32F-NEXT: .LBB97_4: # %else811051; RV32ZVE32F-NEXT: andi a1, a2, 1611052; RV32ZVE32F-NEXT: bnez a1, .LBB97_1411053; RV32ZVE32F-NEXT: .LBB97_5: # %else1111054; RV32ZVE32F-NEXT: andi a1, a2, 3211055; RV32ZVE32F-NEXT: bnez a1, .LBB97_1511056; RV32ZVE32F-NEXT: .LBB97_6: # %else1411057; RV32ZVE32F-NEXT: andi a1, a2, 6411058; RV32ZVE32F-NEXT: bnez a1, .LBB97_1611059; RV32ZVE32F-NEXT: .LBB97_7: # %else1711060; RV32ZVE32F-NEXT: andi a1, a2, -12811061; RV32ZVE32F-NEXT: beqz a1, .LBB97_911062; RV32ZVE32F-NEXT: .LBB97_8: # %cond.load1911063; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma11064; RV32ZVE32F-NEXT: vslidedown.vi v8, v8, 711065; RV32ZVE32F-NEXT: vmv.x.s a1, v811066; RV32ZVE32F-NEXT: fld fa7, 0(a1)11067; RV32ZVE32F-NEXT: .LBB97_9: # %else2011068; RV32ZVE32F-NEXT: fsd fa0, 0(a0)11069; RV32ZVE32F-NEXT: fsd fa1, 8(a0)11070; RV32ZVE32F-NEXT: fsd fa2, 16(a0)11071; RV32ZVE32F-NEXT: fsd fa3, 24(a0)11072; RV32ZVE32F-NEXT: fsd fa4, 32(a0)11073; RV32ZVE32F-NEXT: fsd fa5, 40(a0)11074; RV32ZVE32F-NEXT: fsd fa6, 48(a0)11075; RV32ZVE32F-NEXT: fsd fa7, 56(a0)11076; RV32ZVE32F-NEXT: ret11077; RV32ZVE32F-NEXT: .LBB97_10: # %cond.load11078; RV32ZVE32F-NEXT: vmv.x.s a1, v811079; RV32ZVE32F-NEXT: fld fa0, 0(a1)11080; RV32ZVE32F-NEXT: andi a1, a2, 211081; RV32ZVE32F-NEXT: beqz a1, .LBB97_211082; RV32ZVE32F-NEXT: .LBB97_11: # %cond.load111083; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma11084; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 111085; RV32ZVE32F-NEXT: vmv.x.s a1, v1011086; RV32ZVE32F-NEXT: fld fa1, 0(a1)11087; RV32ZVE32F-NEXT: andi a1, a2, 411088; RV32ZVE32F-NEXT: beqz a1, .LBB97_311089; RV32ZVE32F-NEXT: .LBB97_12: # %cond.load411090; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma11091; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 211092; RV32ZVE32F-NEXT: vmv.x.s a1, v1011093; RV32ZVE32F-NEXT: fld fa2, 0(a1)11094; RV32ZVE32F-NEXT: andi a1, a2, 811095; RV32ZVE32F-NEXT: beqz a1, .LBB97_411096; RV32ZVE32F-NEXT: .LBB97_13: # %cond.load711097; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma11098; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 311099; RV32ZVE32F-NEXT: vmv.x.s a1, v1011100; RV32ZVE32F-NEXT: fld fa3, 0(a1)11101; RV32ZVE32F-NEXT: andi a1, a2, 1611102; RV32ZVE32F-NEXT: beqz a1, .LBB97_511103; RV32ZVE32F-NEXT: .LBB97_14: # %cond.load1011104; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma11105; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 411106; RV32ZVE32F-NEXT: vmv.x.s a1, v1011107; RV32ZVE32F-NEXT: fld fa4, 0(a1)11108; RV32ZVE32F-NEXT: andi a1, a2, 3211109; RV32ZVE32F-NEXT: beqz a1, .LBB97_611110; RV32ZVE32F-NEXT: .LBB97_15: # %cond.load1311111; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma11112; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 511113; RV32ZVE32F-NEXT: vmv.x.s a1, v1011114; RV32ZVE32F-NEXT: fld fa5, 0(a1)11115; RV32ZVE32F-NEXT: andi a1, a2, 6411116; RV32ZVE32F-NEXT: beqz a1, .LBB97_711117; RV32ZVE32F-NEXT: .LBB97_16: # %cond.load1611118; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma11119; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 611120; RV32ZVE32F-NEXT: vmv.x.s a1, v1011121; RV32ZVE32F-NEXT: fld fa6, 0(a1)11122; RV32ZVE32F-NEXT: andi a1, a2, -12811123; RV32ZVE32F-NEXT: bnez a1, .LBB97_811124; RV32ZVE32F-NEXT: j .LBB97_911125;11126; RV64ZVE32F-LABEL: mgather_baseidx_v8i8_v8f64:11127; RV64ZVE32F: # %bb.0:11128; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma11129; RV64ZVE32F-NEXT: vmv.x.s a2, v011130; RV64ZVE32F-NEXT: andi a3, a2, 111131; RV64ZVE32F-NEXT: beqz a3, .LBB97_211132; RV64ZVE32F-NEXT: # %bb.1: # %cond.load11133; RV64ZVE32F-NEXT: vmv.x.s a3, v811134; RV64ZVE32F-NEXT: slli a3, a3, 311135; RV64ZVE32F-NEXT: add a3, a1, a311136; RV64ZVE32F-NEXT: fld fa0, 0(a3)11137; RV64ZVE32F-NEXT: .LBB97_2: # %else11138; RV64ZVE32F-NEXT: andi a3, a2, 211139; RV64ZVE32F-NEXT: beqz a3, .LBB97_411140; RV64ZVE32F-NEXT: # %bb.3: # %cond.load111141; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma11142; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 111143; RV64ZVE32F-NEXT: vmv.x.s a3, v911144; RV64ZVE32F-NEXT: slli a3, a3, 311145; RV64ZVE32F-NEXT: add a3, a1, a311146; RV64ZVE32F-NEXT: fld fa1, 0(a3)11147; RV64ZVE32F-NEXT: .LBB97_4: # %else211148; RV64ZVE32F-NEXT: andi a3, a2, 411149; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma11150; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 211151; RV64ZVE32F-NEXT: beqz a3, .LBB97_611152; RV64ZVE32F-NEXT: # %bb.5: # %cond.load411153; RV64ZVE32F-NEXT: vmv.x.s a3, v911154; RV64ZVE32F-NEXT: slli a3, a3, 311155; RV64ZVE32F-NEXT: add a3, a1, a311156; RV64ZVE32F-NEXT: fld fa2, 0(a3)11157; RV64ZVE32F-NEXT: .LBB97_6: # %else511158; RV64ZVE32F-NEXT: andi a3, a2, 811159; RV64ZVE32F-NEXT: beqz a3, .LBB97_811160; RV64ZVE32F-NEXT: # %bb.7: # %cond.load711161; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 111162; RV64ZVE32F-NEXT: vmv.x.s a3, v911163; RV64ZVE32F-NEXT: slli a3, a3, 311164; RV64ZVE32F-NEXT: add a3, a1, a311165; RV64ZVE32F-NEXT: fld fa3, 0(a3)11166; RV64ZVE32F-NEXT: .LBB97_8: # %else811167; RV64ZVE32F-NEXT: andi a3, a2, 1611168; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma11169; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 411170; RV64ZVE32F-NEXT: beqz a3, .LBB97_1011171; RV64ZVE32F-NEXT: # %bb.9: # %cond.load1011172; RV64ZVE32F-NEXT: vmv.x.s a3, v811173; RV64ZVE32F-NEXT: slli a3, a3, 311174; RV64ZVE32F-NEXT: add a3, a1, a311175; RV64ZVE32F-NEXT: fld fa4, 0(a3)11176; RV64ZVE32F-NEXT: .LBB97_10: # %else1111177; RV64ZVE32F-NEXT: andi a3, a2, 3211178; RV64ZVE32F-NEXT: beqz a3, .LBB97_1211179; RV64ZVE32F-NEXT: # %bb.11: # %cond.load1311180; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma11181; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 111182; RV64ZVE32F-NEXT: vmv.x.s a3, v911183; RV64ZVE32F-NEXT: slli a3, a3, 311184; RV64ZVE32F-NEXT: add a3, a1, a311185; RV64ZVE32F-NEXT: fld fa5, 0(a3)11186; RV64ZVE32F-NEXT: .LBB97_12: # %else1411187; RV64ZVE32F-NEXT: andi a3, a2, 6411188; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma11189; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 211190; RV64ZVE32F-NEXT: beqz a3, .LBB97_1411191; RV64ZVE32F-NEXT: # %bb.13: # %cond.load1611192; RV64ZVE32F-NEXT: vmv.x.s a3, v811193; RV64ZVE32F-NEXT: slli a3, a3, 311194; RV64ZVE32F-NEXT: add a3, a1, a311195; RV64ZVE32F-NEXT: fld fa6, 0(a3)11196; RV64ZVE32F-NEXT: .LBB97_14: # %else1711197; RV64ZVE32F-NEXT: andi a2, a2, -12811198; RV64ZVE32F-NEXT: beqz a2, .LBB97_1611199; RV64ZVE32F-NEXT: # %bb.15: # %cond.load1911200; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 111201; RV64ZVE32F-NEXT: vmv.x.s a2, v811202; RV64ZVE32F-NEXT: slli a2, a2, 311203; RV64ZVE32F-NEXT: add a1, a1, a211204; RV64ZVE32F-NEXT: fld fa7, 0(a1)11205; RV64ZVE32F-NEXT: .LBB97_16: # %else2011206; RV64ZVE32F-NEXT: fsd fa0, 0(a0)11207; RV64ZVE32F-NEXT: fsd fa1, 8(a0)11208; RV64ZVE32F-NEXT: fsd fa2, 16(a0)11209; RV64ZVE32F-NEXT: fsd fa3, 24(a0)11210; RV64ZVE32F-NEXT: fsd fa4, 32(a0)11211; RV64ZVE32F-NEXT: fsd fa5, 40(a0)11212; RV64ZVE32F-NEXT: fsd fa6, 48(a0)11213; RV64ZVE32F-NEXT: fsd fa7, 56(a0)11214; RV64ZVE32F-NEXT: ret11215 %ptrs = getelementptr inbounds double, ptr %base, <8 x i8> %idxs11216 %v = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> %ptrs, i32 8, <8 x i1> %m, <8 x double> %passthru)11217 ret <8 x double> %v11218}11219 11220define <8 x double> @mgather_baseidx_sext_v8i8_v8f64(ptr %base, <8 x i8> %idxs, <8 x i1> %m, <8 x double> %passthru) {11221; RV32V-LABEL: mgather_baseidx_sext_v8i8_v8f64:11222; RV32V: # %bb.0:11223; RV32V-NEXT: vsetivli zero, 8, e32, m2, ta, ma11224; RV32V-NEXT: vsext.vf4 v10, v811225; RV32V-NEXT: vsll.vi v8, v10, 311226; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, mu11227; RV32V-NEXT: vluxei32.v v12, (a0), v8, v0.t11228; RV32V-NEXT: vmv.v.v v8, v1211229; RV32V-NEXT: ret11230;11231; RV64V-LABEL: mgather_baseidx_sext_v8i8_v8f64:11232; RV64V: # %bb.0:11233; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, mu11234; RV64V-NEXT: vsext.vf8 v16, v811235; RV64V-NEXT: vsll.vi v8, v16, 311236; RV64V-NEXT: vluxei64.v v12, (a0), v8, v0.t11237; RV64V-NEXT: vmv.v.v v8, v1211238; RV64V-NEXT: ret11239;11240; RV32ZVE32F-LABEL: mgather_baseidx_sext_v8i8_v8f64:11241; RV32ZVE32F: # %bb.0:11242; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma11243; RV32ZVE32F-NEXT: vsext.vf4 v10, v811244; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma11245; RV32ZVE32F-NEXT: vmv.x.s a2, v011246; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma11247; RV32ZVE32F-NEXT: vsll.vi v8, v10, 311248; RV32ZVE32F-NEXT: andi a3, a2, 111249; RV32ZVE32F-NEXT: vadd.vx v8, v8, a111250; RV32ZVE32F-NEXT: bnez a3, .LBB98_1011251; RV32ZVE32F-NEXT: # %bb.1: # %else11252; RV32ZVE32F-NEXT: andi a1, a2, 211253; RV32ZVE32F-NEXT: bnez a1, .LBB98_1111254; RV32ZVE32F-NEXT: .LBB98_2: # %else211255; RV32ZVE32F-NEXT: andi a1, a2, 411256; RV32ZVE32F-NEXT: bnez a1, .LBB98_1211257; RV32ZVE32F-NEXT: .LBB98_3: # %else511258; RV32ZVE32F-NEXT: andi a1, a2, 811259; RV32ZVE32F-NEXT: bnez a1, .LBB98_1311260; RV32ZVE32F-NEXT: .LBB98_4: # %else811261; RV32ZVE32F-NEXT: andi a1, a2, 1611262; RV32ZVE32F-NEXT: bnez a1, .LBB98_1411263; RV32ZVE32F-NEXT: .LBB98_5: # %else1111264; RV32ZVE32F-NEXT: andi a1, a2, 3211265; RV32ZVE32F-NEXT: bnez a1, .LBB98_1511266; RV32ZVE32F-NEXT: .LBB98_6: # %else1411267; RV32ZVE32F-NEXT: andi a1, a2, 6411268; RV32ZVE32F-NEXT: bnez a1, .LBB98_1611269; RV32ZVE32F-NEXT: .LBB98_7: # %else1711270; RV32ZVE32F-NEXT: andi a1, a2, -12811271; RV32ZVE32F-NEXT: beqz a1, .LBB98_911272; RV32ZVE32F-NEXT: .LBB98_8: # %cond.load1911273; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma11274; RV32ZVE32F-NEXT: vslidedown.vi v8, v8, 711275; RV32ZVE32F-NEXT: vmv.x.s a1, v811276; RV32ZVE32F-NEXT: fld fa7, 0(a1)11277; RV32ZVE32F-NEXT: .LBB98_9: # %else2011278; RV32ZVE32F-NEXT: fsd fa0, 0(a0)11279; RV32ZVE32F-NEXT: fsd fa1, 8(a0)11280; RV32ZVE32F-NEXT: fsd fa2, 16(a0)11281; RV32ZVE32F-NEXT: fsd fa3, 24(a0)11282; RV32ZVE32F-NEXT: fsd fa4, 32(a0)11283; RV32ZVE32F-NEXT: fsd fa5, 40(a0)11284; RV32ZVE32F-NEXT: fsd fa6, 48(a0)11285; RV32ZVE32F-NEXT: fsd fa7, 56(a0)11286; RV32ZVE32F-NEXT: ret11287; RV32ZVE32F-NEXT: .LBB98_10: # %cond.load11288; RV32ZVE32F-NEXT: vmv.x.s a1, v811289; RV32ZVE32F-NEXT: fld fa0, 0(a1)11290; RV32ZVE32F-NEXT: andi a1, a2, 211291; RV32ZVE32F-NEXT: beqz a1, .LBB98_211292; RV32ZVE32F-NEXT: .LBB98_11: # %cond.load111293; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma11294; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 111295; RV32ZVE32F-NEXT: vmv.x.s a1, v1011296; RV32ZVE32F-NEXT: fld fa1, 0(a1)11297; RV32ZVE32F-NEXT: andi a1, a2, 411298; RV32ZVE32F-NEXT: beqz a1, .LBB98_311299; RV32ZVE32F-NEXT: .LBB98_12: # %cond.load411300; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma11301; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 211302; RV32ZVE32F-NEXT: vmv.x.s a1, v1011303; RV32ZVE32F-NEXT: fld fa2, 0(a1)11304; RV32ZVE32F-NEXT: andi a1, a2, 811305; RV32ZVE32F-NEXT: beqz a1, .LBB98_411306; RV32ZVE32F-NEXT: .LBB98_13: # %cond.load711307; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma11308; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 311309; RV32ZVE32F-NEXT: vmv.x.s a1, v1011310; RV32ZVE32F-NEXT: fld fa3, 0(a1)11311; RV32ZVE32F-NEXT: andi a1, a2, 1611312; RV32ZVE32F-NEXT: beqz a1, .LBB98_511313; RV32ZVE32F-NEXT: .LBB98_14: # %cond.load1011314; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma11315; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 411316; RV32ZVE32F-NEXT: vmv.x.s a1, v1011317; RV32ZVE32F-NEXT: fld fa4, 0(a1)11318; RV32ZVE32F-NEXT: andi a1, a2, 3211319; RV32ZVE32F-NEXT: beqz a1, .LBB98_611320; RV32ZVE32F-NEXT: .LBB98_15: # %cond.load1311321; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma11322; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 511323; RV32ZVE32F-NEXT: vmv.x.s a1, v1011324; RV32ZVE32F-NEXT: fld fa5, 0(a1)11325; RV32ZVE32F-NEXT: andi a1, a2, 6411326; RV32ZVE32F-NEXT: beqz a1, .LBB98_711327; RV32ZVE32F-NEXT: .LBB98_16: # %cond.load1611328; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma11329; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 611330; RV32ZVE32F-NEXT: vmv.x.s a1, v1011331; RV32ZVE32F-NEXT: fld fa6, 0(a1)11332; RV32ZVE32F-NEXT: andi a1, a2, -12811333; RV32ZVE32F-NEXT: bnez a1, .LBB98_811334; RV32ZVE32F-NEXT: j .LBB98_911335;11336; RV64ZVE32F-LABEL: mgather_baseidx_sext_v8i8_v8f64:11337; RV64ZVE32F: # %bb.0:11338; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma11339; RV64ZVE32F-NEXT: vmv.x.s a2, v011340; RV64ZVE32F-NEXT: andi a3, a2, 111341; RV64ZVE32F-NEXT: beqz a3, .LBB98_211342; RV64ZVE32F-NEXT: # %bb.1: # %cond.load11343; RV64ZVE32F-NEXT: vmv.x.s a3, v811344; RV64ZVE32F-NEXT: slli a3, a3, 311345; RV64ZVE32F-NEXT: add a3, a1, a311346; RV64ZVE32F-NEXT: fld fa0, 0(a3)11347; RV64ZVE32F-NEXT: .LBB98_2: # %else11348; RV64ZVE32F-NEXT: andi a3, a2, 211349; RV64ZVE32F-NEXT: beqz a3, .LBB98_411350; RV64ZVE32F-NEXT: # %bb.3: # %cond.load111351; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma11352; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 111353; RV64ZVE32F-NEXT: vmv.x.s a3, v911354; RV64ZVE32F-NEXT: slli a3, a3, 311355; RV64ZVE32F-NEXT: add a3, a1, a311356; RV64ZVE32F-NEXT: fld fa1, 0(a3)11357; RV64ZVE32F-NEXT: .LBB98_4: # %else211358; RV64ZVE32F-NEXT: andi a3, a2, 411359; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma11360; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 211361; RV64ZVE32F-NEXT: beqz a3, .LBB98_611362; RV64ZVE32F-NEXT: # %bb.5: # %cond.load411363; RV64ZVE32F-NEXT: vmv.x.s a3, v911364; RV64ZVE32F-NEXT: slli a3, a3, 311365; RV64ZVE32F-NEXT: add a3, a1, a311366; RV64ZVE32F-NEXT: fld fa2, 0(a3)11367; RV64ZVE32F-NEXT: .LBB98_6: # %else511368; RV64ZVE32F-NEXT: andi a3, a2, 811369; RV64ZVE32F-NEXT: beqz a3, .LBB98_811370; RV64ZVE32F-NEXT: # %bb.7: # %cond.load711371; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 111372; RV64ZVE32F-NEXT: vmv.x.s a3, v911373; RV64ZVE32F-NEXT: slli a3, a3, 311374; RV64ZVE32F-NEXT: add a3, a1, a311375; RV64ZVE32F-NEXT: fld fa3, 0(a3)11376; RV64ZVE32F-NEXT: .LBB98_8: # %else811377; RV64ZVE32F-NEXT: andi a3, a2, 1611378; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma11379; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 411380; RV64ZVE32F-NEXT: beqz a3, .LBB98_1011381; RV64ZVE32F-NEXT: # %bb.9: # %cond.load1011382; RV64ZVE32F-NEXT: vmv.x.s a3, v811383; RV64ZVE32F-NEXT: slli a3, a3, 311384; RV64ZVE32F-NEXT: add a3, a1, a311385; RV64ZVE32F-NEXT: fld fa4, 0(a3)11386; RV64ZVE32F-NEXT: .LBB98_10: # %else1111387; RV64ZVE32F-NEXT: andi a3, a2, 3211388; RV64ZVE32F-NEXT: beqz a3, .LBB98_1211389; RV64ZVE32F-NEXT: # %bb.11: # %cond.load1311390; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma11391; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 111392; RV64ZVE32F-NEXT: vmv.x.s a3, v911393; RV64ZVE32F-NEXT: slli a3, a3, 311394; RV64ZVE32F-NEXT: add a3, a1, a311395; RV64ZVE32F-NEXT: fld fa5, 0(a3)11396; RV64ZVE32F-NEXT: .LBB98_12: # %else1411397; RV64ZVE32F-NEXT: andi a3, a2, 6411398; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma11399; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 211400; RV64ZVE32F-NEXT: beqz a3, .LBB98_1411401; RV64ZVE32F-NEXT: # %bb.13: # %cond.load1611402; RV64ZVE32F-NEXT: vmv.x.s a3, v811403; RV64ZVE32F-NEXT: slli a3, a3, 311404; RV64ZVE32F-NEXT: add a3, a1, a311405; RV64ZVE32F-NEXT: fld fa6, 0(a3)11406; RV64ZVE32F-NEXT: .LBB98_14: # %else1711407; RV64ZVE32F-NEXT: andi a2, a2, -12811408; RV64ZVE32F-NEXT: beqz a2, .LBB98_1611409; RV64ZVE32F-NEXT: # %bb.15: # %cond.load1911410; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 111411; RV64ZVE32F-NEXT: vmv.x.s a2, v811412; RV64ZVE32F-NEXT: slli a2, a2, 311413; RV64ZVE32F-NEXT: add a1, a1, a211414; RV64ZVE32F-NEXT: fld fa7, 0(a1)11415; RV64ZVE32F-NEXT: .LBB98_16: # %else2011416; RV64ZVE32F-NEXT: fsd fa0, 0(a0)11417; RV64ZVE32F-NEXT: fsd fa1, 8(a0)11418; RV64ZVE32F-NEXT: fsd fa2, 16(a0)11419; RV64ZVE32F-NEXT: fsd fa3, 24(a0)11420; RV64ZVE32F-NEXT: fsd fa4, 32(a0)11421; RV64ZVE32F-NEXT: fsd fa5, 40(a0)11422; RV64ZVE32F-NEXT: fsd fa6, 48(a0)11423; RV64ZVE32F-NEXT: fsd fa7, 56(a0)11424; RV64ZVE32F-NEXT: ret11425 %eidxs = sext <8 x i8> %idxs to <8 x i64>11426 %ptrs = getelementptr inbounds double, ptr %base, <8 x i64> %eidxs11427 %v = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> %ptrs, i32 8, <8 x i1> %m, <8 x double> %passthru)11428 ret <8 x double> %v11429}11430 11431define <8 x double> @mgather_baseidx_zext_v8i8_v8f64(ptr %base, <8 x i8> %idxs, <8 x i1> %m, <8 x double> %passthru) {11432; RV32V-LABEL: mgather_baseidx_zext_v8i8_v8f64:11433; RV32V: # %bb.0:11434; RV32V-NEXT: li a1, 811435; RV32V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma11436; RV32V-NEXT: vwmulu.vx v9, v8, a111437; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, mu11438; RV32V-NEXT: vluxei16.v v12, (a0), v9, v0.t11439; RV32V-NEXT: vmv.v.v v8, v1211440; RV32V-NEXT: ret11441;11442; RV64V-LABEL: mgather_baseidx_zext_v8i8_v8f64:11443; RV64V: # %bb.0:11444; RV64V-NEXT: li a1, 811445; RV64V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma11446; RV64V-NEXT: vwmulu.vx v9, v8, a111447; RV64V-NEXT: vsetvli zero, zero, e64, m4, ta, mu11448; RV64V-NEXT: vluxei16.v v12, (a0), v9, v0.t11449; RV64V-NEXT: vmv.v.v v8, v1211450; RV64V-NEXT: ret11451;11452; RV32ZVE32F-LABEL: mgather_baseidx_zext_v8i8_v8f64:11453; RV32ZVE32F: # %bb.0:11454; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma11455; RV32ZVE32F-NEXT: vzext.vf4 v10, v811456; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma11457; RV32ZVE32F-NEXT: vmv.x.s a2, v011458; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma11459; RV32ZVE32F-NEXT: vsll.vi v8, v10, 311460; RV32ZVE32F-NEXT: andi a3, a2, 111461; RV32ZVE32F-NEXT: vadd.vx v8, v8, a111462; RV32ZVE32F-NEXT: bnez a3, .LBB99_1011463; RV32ZVE32F-NEXT: # %bb.1: # %else11464; RV32ZVE32F-NEXT: andi a1, a2, 211465; RV32ZVE32F-NEXT: bnez a1, .LBB99_1111466; RV32ZVE32F-NEXT: .LBB99_2: # %else211467; RV32ZVE32F-NEXT: andi a1, a2, 411468; RV32ZVE32F-NEXT: bnez a1, .LBB99_1211469; RV32ZVE32F-NEXT: .LBB99_3: # %else511470; RV32ZVE32F-NEXT: andi a1, a2, 811471; RV32ZVE32F-NEXT: bnez a1, .LBB99_1311472; RV32ZVE32F-NEXT: .LBB99_4: # %else811473; RV32ZVE32F-NEXT: andi a1, a2, 1611474; RV32ZVE32F-NEXT: bnez a1, .LBB99_1411475; RV32ZVE32F-NEXT: .LBB99_5: # %else1111476; RV32ZVE32F-NEXT: andi a1, a2, 3211477; RV32ZVE32F-NEXT: bnez a1, .LBB99_1511478; RV32ZVE32F-NEXT: .LBB99_6: # %else1411479; RV32ZVE32F-NEXT: andi a1, a2, 6411480; RV32ZVE32F-NEXT: bnez a1, .LBB99_1611481; RV32ZVE32F-NEXT: .LBB99_7: # %else1711482; RV32ZVE32F-NEXT: andi a1, a2, -12811483; RV32ZVE32F-NEXT: beqz a1, .LBB99_911484; RV32ZVE32F-NEXT: .LBB99_8: # %cond.load1911485; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma11486; RV32ZVE32F-NEXT: vslidedown.vi v8, v8, 711487; RV32ZVE32F-NEXT: vmv.x.s a1, v811488; RV32ZVE32F-NEXT: fld fa7, 0(a1)11489; RV32ZVE32F-NEXT: .LBB99_9: # %else2011490; RV32ZVE32F-NEXT: fsd fa0, 0(a0)11491; RV32ZVE32F-NEXT: fsd fa1, 8(a0)11492; RV32ZVE32F-NEXT: fsd fa2, 16(a0)11493; RV32ZVE32F-NEXT: fsd fa3, 24(a0)11494; RV32ZVE32F-NEXT: fsd fa4, 32(a0)11495; RV32ZVE32F-NEXT: fsd fa5, 40(a0)11496; RV32ZVE32F-NEXT: fsd fa6, 48(a0)11497; RV32ZVE32F-NEXT: fsd fa7, 56(a0)11498; RV32ZVE32F-NEXT: ret11499; RV32ZVE32F-NEXT: .LBB99_10: # %cond.load11500; RV32ZVE32F-NEXT: vmv.x.s a1, v811501; RV32ZVE32F-NEXT: fld fa0, 0(a1)11502; RV32ZVE32F-NEXT: andi a1, a2, 211503; RV32ZVE32F-NEXT: beqz a1, .LBB99_211504; RV32ZVE32F-NEXT: .LBB99_11: # %cond.load111505; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma11506; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 111507; RV32ZVE32F-NEXT: vmv.x.s a1, v1011508; RV32ZVE32F-NEXT: fld fa1, 0(a1)11509; RV32ZVE32F-NEXT: andi a1, a2, 411510; RV32ZVE32F-NEXT: beqz a1, .LBB99_311511; RV32ZVE32F-NEXT: .LBB99_12: # %cond.load411512; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma11513; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 211514; RV32ZVE32F-NEXT: vmv.x.s a1, v1011515; RV32ZVE32F-NEXT: fld fa2, 0(a1)11516; RV32ZVE32F-NEXT: andi a1, a2, 811517; RV32ZVE32F-NEXT: beqz a1, .LBB99_411518; RV32ZVE32F-NEXT: .LBB99_13: # %cond.load711519; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma11520; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 311521; RV32ZVE32F-NEXT: vmv.x.s a1, v1011522; RV32ZVE32F-NEXT: fld fa3, 0(a1)11523; RV32ZVE32F-NEXT: andi a1, a2, 1611524; RV32ZVE32F-NEXT: beqz a1, .LBB99_511525; RV32ZVE32F-NEXT: .LBB99_14: # %cond.load1011526; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma11527; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 411528; RV32ZVE32F-NEXT: vmv.x.s a1, v1011529; RV32ZVE32F-NEXT: fld fa4, 0(a1)11530; RV32ZVE32F-NEXT: andi a1, a2, 3211531; RV32ZVE32F-NEXT: beqz a1, .LBB99_611532; RV32ZVE32F-NEXT: .LBB99_15: # %cond.load1311533; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma11534; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 511535; RV32ZVE32F-NEXT: vmv.x.s a1, v1011536; RV32ZVE32F-NEXT: fld fa5, 0(a1)11537; RV32ZVE32F-NEXT: andi a1, a2, 6411538; RV32ZVE32F-NEXT: beqz a1, .LBB99_711539; RV32ZVE32F-NEXT: .LBB99_16: # %cond.load1611540; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma11541; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 611542; RV32ZVE32F-NEXT: vmv.x.s a1, v1011543; RV32ZVE32F-NEXT: fld fa6, 0(a1)11544; RV32ZVE32F-NEXT: andi a1, a2, -12811545; RV32ZVE32F-NEXT: bnez a1, .LBB99_811546; RV32ZVE32F-NEXT: j .LBB99_911547;11548; RV64ZVE32F-LABEL: mgather_baseidx_zext_v8i8_v8f64:11549; RV64ZVE32F: # %bb.0:11550; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma11551; RV64ZVE32F-NEXT: vmv.x.s a2, v011552; RV64ZVE32F-NEXT: andi a3, a2, 111553; RV64ZVE32F-NEXT: beqz a3, .LBB99_211554; RV64ZVE32F-NEXT: # %bb.1: # %cond.load11555; RV64ZVE32F-NEXT: vmv.x.s a3, v811556; RV64ZVE32F-NEXT: zext.b a3, a311557; RV64ZVE32F-NEXT: slli a3, a3, 311558; RV64ZVE32F-NEXT: add a3, a1, a311559; RV64ZVE32F-NEXT: fld fa0, 0(a3)11560; RV64ZVE32F-NEXT: .LBB99_2: # %else11561; RV64ZVE32F-NEXT: andi a3, a2, 211562; RV64ZVE32F-NEXT: beqz a3, .LBB99_411563; RV64ZVE32F-NEXT: # %bb.3: # %cond.load111564; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma11565; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 111566; RV64ZVE32F-NEXT: vmv.x.s a3, v911567; RV64ZVE32F-NEXT: zext.b a3, a311568; RV64ZVE32F-NEXT: slli a3, a3, 311569; RV64ZVE32F-NEXT: add a3, a1, a311570; RV64ZVE32F-NEXT: fld fa1, 0(a3)11571; RV64ZVE32F-NEXT: .LBB99_4: # %else211572; RV64ZVE32F-NEXT: andi a3, a2, 411573; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma11574; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 211575; RV64ZVE32F-NEXT: beqz a3, .LBB99_611576; RV64ZVE32F-NEXT: # %bb.5: # %cond.load411577; RV64ZVE32F-NEXT: vmv.x.s a3, v911578; RV64ZVE32F-NEXT: zext.b a3, a311579; RV64ZVE32F-NEXT: slli a3, a3, 311580; RV64ZVE32F-NEXT: add a3, a1, a311581; RV64ZVE32F-NEXT: fld fa2, 0(a3)11582; RV64ZVE32F-NEXT: .LBB99_6: # %else511583; RV64ZVE32F-NEXT: andi a3, a2, 811584; RV64ZVE32F-NEXT: beqz a3, .LBB99_811585; RV64ZVE32F-NEXT: # %bb.7: # %cond.load711586; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 111587; RV64ZVE32F-NEXT: vmv.x.s a3, v911588; RV64ZVE32F-NEXT: zext.b a3, a311589; RV64ZVE32F-NEXT: slli a3, a3, 311590; RV64ZVE32F-NEXT: add a3, a1, a311591; RV64ZVE32F-NEXT: fld fa3, 0(a3)11592; RV64ZVE32F-NEXT: .LBB99_8: # %else811593; RV64ZVE32F-NEXT: andi a3, a2, 1611594; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma11595; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 411596; RV64ZVE32F-NEXT: beqz a3, .LBB99_1011597; RV64ZVE32F-NEXT: # %bb.9: # %cond.load1011598; RV64ZVE32F-NEXT: vmv.x.s a3, v811599; RV64ZVE32F-NEXT: zext.b a3, a311600; RV64ZVE32F-NEXT: slli a3, a3, 311601; RV64ZVE32F-NEXT: add a3, a1, a311602; RV64ZVE32F-NEXT: fld fa4, 0(a3)11603; RV64ZVE32F-NEXT: .LBB99_10: # %else1111604; RV64ZVE32F-NEXT: andi a3, a2, 3211605; RV64ZVE32F-NEXT: beqz a3, .LBB99_1211606; RV64ZVE32F-NEXT: # %bb.11: # %cond.load1311607; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma11608; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 111609; RV64ZVE32F-NEXT: vmv.x.s a3, v911610; RV64ZVE32F-NEXT: zext.b a3, a311611; RV64ZVE32F-NEXT: slli a3, a3, 311612; RV64ZVE32F-NEXT: add a3, a1, a311613; RV64ZVE32F-NEXT: fld fa5, 0(a3)11614; RV64ZVE32F-NEXT: .LBB99_12: # %else1411615; RV64ZVE32F-NEXT: andi a3, a2, 6411616; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma11617; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 211618; RV64ZVE32F-NEXT: beqz a3, .LBB99_1411619; RV64ZVE32F-NEXT: # %bb.13: # %cond.load1611620; RV64ZVE32F-NEXT: vmv.x.s a3, v811621; RV64ZVE32F-NEXT: zext.b a3, a311622; RV64ZVE32F-NEXT: slli a3, a3, 311623; RV64ZVE32F-NEXT: add a3, a1, a311624; RV64ZVE32F-NEXT: fld fa6, 0(a3)11625; RV64ZVE32F-NEXT: .LBB99_14: # %else1711626; RV64ZVE32F-NEXT: andi a2, a2, -12811627; RV64ZVE32F-NEXT: beqz a2, .LBB99_1611628; RV64ZVE32F-NEXT: # %bb.15: # %cond.load1911629; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 111630; RV64ZVE32F-NEXT: vmv.x.s a2, v811631; RV64ZVE32F-NEXT: zext.b a2, a211632; RV64ZVE32F-NEXT: slli a2, a2, 311633; RV64ZVE32F-NEXT: add a1, a1, a211634; RV64ZVE32F-NEXT: fld fa7, 0(a1)11635; RV64ZVE32F-NEXT: .LBB99_16: # %else2011636; RV64ZVE32F-NEXT: fsd fa0, 0(a0)11637; RV64ZVE32F-NEXT: fsd fa1, 8(a0)11638; RV64ZVE32F-NEXT: fsd fa2, 16(a0)11639; RV64ZVE32F-NEXT: fsd fa3, 24(a0)11640; RV64ZVE32F-NEXT: fsd fa4, 32(a0)11641; RV64ZVE32F-NEXT: fsd fa5, 40(a0)11642; RV64ZVE32F-NEXT: fsd fa6, 48(a0)11643; RV64ZVE32F-NEXT: fsd fa7, 56(a0)11644; RV64ZVE32F-NEXT: ret11645 %eidxs = zext <8 x i8> %idxs to <8 x i64>11646 %ptrs = getelementptr inbounds double, ptr %base, <8 x i64> %eidxs11647 %v = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> %ptrs, i32 8, <8 x i1> %m, <8 x double> %passthru)11648 ret <8 x double> %v11649}11650 11651define <8 x double> @mgather_baseidx_v8i16_v8f64(ptr %base, <8 x i16> %idxs, <8 x i1> %m, <8 x double> %passthru) {11652; RV32V-LABEL: mgather_baseidx_v8i16_v8f64:11653; RV32V: # %bb.0:11654; RV32V-NEXT: li a1, 811655; RV32V-NEXT: vsetivli zero, 8, e16, m1, ta, ma11656; RV32V-NEXT: vwmulsu.vx v10, v8, a111657; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, mu11658; RV32V-NEXT: vluxei32.v v12, (a0), v10, v0.t11659; RV32V-NEXT: vmv.v.v v8, v1211660; RV32V-NEXT: ret11661;11662; RV64V-LABEL: mgather_baseidx_v8i16_v8f64:11663; RV64V: # %bb.0:11664; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, mu11665; RV64V-NEXT: vsext.vf4 v16, v811666; RV64V-NEXT: vsll.vi v8, v16, 311667; RV64V-NEXT: vluxei64.v v12, (a0), v8, v0.t11668; RV64V-NEXT: vmv.v.v v8, v1211669; RV64V-NEXT: ret11670;11671; RV32ZVE32F-LABEL: mgather_baseidx_v8i16_v8f64:11672; RV32ZVE32F: # %bb.0:11673; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma11674; RV32ZVE32F-NEXT: vmv.v.x v10, a111675; RV32ZVE32F-NEXT: li a2, 811676; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma11677; RV32ZVE32F-NEXT: vmv.x.s a1, v011678; RV32ZVE32F-NEXT: andi a3, a1, 111679; RV32ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma11680; RV32ZVE32F-NEXT: vwmaccus.vx v10, a2, v811681; RV32ZVE32F-NEXT: bnez a3, .LBB100_1011682; RV32ZVE32F-NEXT: # %bb.1: # %else11683; RV32ZVE32F-NEXT: andi a2, a1, 211684; RV32ZVE32F-NEXT: bnez a2, .LBB100_1111685; RV32ZVE32F-NEXT: .LBB100_2: # %else211686; RV32ZVE32F-NEXT: andi a2, a1, 411687; RV32ZVE32F-NEXT: bnez a2, .LBB100_1211688; RV32ZVE32F-NEXT: .LBB100_3: # %else511689; RV32ZVE32F-NEXT: andi a2, a1, 811690; RV32ZVE32F-NEXT: bnez a2, .LBB100_1311691; RV32ZVE32F-NEXT: .LBB100_4: # %else811692; RV32ZVE32F-NEXT: andi a2, a1, 1611693; RV32ZVE32F-NEXT: bnez a2, .LBB100_1411694; RV32ZVE32F-NEXT: .LBB100_5: # %else1111695; RV32ZVE32F-NEXT: andi a2, a1, 3211696; RV32ZVE32F-NEXT: bnez a2, .LBB100_1511697; RV32ZVE32F-NEXT: .LBB100_6: # %else1411698; RV32ZVE32F-NEXT: andi a2, a1, 6411699; RV32ZVE32F-NEXT: bnez a2, .LBB100_1611700; RV32ZVE32F-NEXT: .LBB100_7: # %else1711701; RV32ZVE32F-NEXT: andi a1, a1, -12811702; RV32ZVE32F-NEXT: beqz a1, .LBB100_911703; RV32ZVE32F-NEXT: .LBB100_8: # %cond.load1911704; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma11705; RV32ZVE32F-NEXT: vslidedown.vi v8, v10, 711706; RV32ZVE32F-NEXT: vmv.x.s a1, v811707; RV32ZVE32F-NEXT: fld fa7, 0(a1)11708; RV32ZVE32F-NEXT: .LBB100_9: # %else2011709; RV32ZVE32F-NEXT: fsd fa0, 0(a0)11710; RV32ZVE32F-NEXT: fsd fa1, 8(a0)11711; RV32ZVE32F-NEXT: fsd fa2, 16(a0)11712; RV32ZVE32F-NEXT: fsd fa3, 24(a0)11713; RV32ZVE32F-NEXT: fsd fa4, 32(a0)11714; RV32ZVE32F-NEXT: fsd fa5, 40(a0)11715; RV32ZVE32F-NEXT: fsd fa6, 48(a0)11716; RV32ZVE32F-NEXT: fsd fa7, 56(a0)11717; RV32ZVE32F-NEXT: ret11718; RV32ZVE32F-NEXT: .LBB100_10: # %cond.load11719; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma11720; RV32ZVE32F-NEXT: vmv.x.s a2, v1011721; RV32ZVE32F-NEXT: fld fa0, 0(a2)11722; RV32ZVE32F-NEXT: andi a2, a1, 211723; RV32ZVE32F-NEXT: beqz a2, .LBB100_211724; RV32ZVE32F-NEXT: .LBB100_11: # %cond.load111725; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma11726; RV32ZVE32F-NEXT: vslidedown.vi v8, v10, 111727; RV32ZVE32F-NEXT: vmv.x.s a2, v811728; RV32ZVE32F-NEXT: fld fa1, 0(a2)11729; RV32ZVE32F-NEXT: andi a2, a1, 411730; RV32ZVE32F-NEXT: beqz a2, .LBB100_311731; RV32ZVE32F-NEXT: .LBB100_12: # %cond.load411732; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma11733; RV32ZVE32F-NEXT: vslidedown.vi v8, v10, 211734; RV32ZVE32F-NEXT: vmv.x.s a2, v811735; RV32ZVE32F-NEXT: fld fa2, 0(a2)11736; RV32ZVE32F-NEXT: andi a2, a1, 811737; RV32ZVE32F-NEXT: beqz a2, .LBB100_411738; RV32ZVE32F-NEXT: .LBB100_13: # %cond.load711739; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma11740; RV32ZVE32F-NEXT: vslidedown.vi v8, v10, 311741; RV32ZVE32F-NEXT: vmv.x.s a2, v811742; RV32ZVE32F-NEXT: fld fa3, 0(a2)11743; RV32ZVE32F-NEXT: andi a2, a1, 1611744; RV32ZVE32F-NEXT: beqz a2, .LBB100_511745; RV32ZVE32F-NEXT: .LBB100_14: # %cond.load1011746; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma11747; RV32ZVE32F-NEXT: vslidedown.vi v8, v10, 411748; RV32ZVE32F-NEXT: vmv.x.s a2, v811749; RV32ZVE32F-NEXT: fld fa4, 0(a2)11750; RV32ZVE32F-NEXT: andi a2, a1, 3211751; RV32ZVE32F-NEXT: beqz a2, .LBB100_611752; RV32ZVE32F-NEXT: .LBB100_15: # %cond.load1311753; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma11754; RV32ZVE32F-NEXT: vslidedown.vi v8, v10, 511755; RV32ZVE32F-NEXT: vmv.x.s a2, v811756; RV32ZVE32F-NEXT: fld fa5, 0(a2)11757; RV32ZVE32F-NEXT: andi a2, a1, 6411758; RV32ZVE32F-NEXT: beqz a2, .LBB100_711759; RV32ZVE32F-NEXT: .LBB100_16: # %cond.load1611760; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma11761; RV32ZVE32F-NEXT: vslidedown.vi v8, v10, 611762; RV32ZVE32F-NEXT: vmv.x.s a2, v811763; RV32ZVE32F-NEXT: fld fa6, 0(a2)11764; RV32ZVE32F-NEXT: andi a1, a1, -12811765; RV32ZVE32F-NEXT: bnez a1, .LBB100_811766; RV32ZVE32F-NEXT: j .LBB100_911767;11768; RV64ZVE32F-LABEL: mgather_baseidx_v8i16_v8f64:11769; RV64ZVE32F: # %bb.0:11770; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma11771; RV64ZVE32F-NEXT: vmv.x.s a2, v011772; RV64ZVE32F-NEXT: andi a3, a2, 111773; RV64ZVE32F-NEXT: beqz a3, .LBB100_211774; RV64ZVE32F-NEXT: # %bb.1: # %cond.load11775; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma11776; RV64ZVE32F-NEXT: vmv.x.s a3, v811777; RV64ZVE32F-NEXT: slli a3, a3, 311778; RV64ZVE32F-NEXT: add a3, a1, a311779; RV64ZVE32F-NEXT: fld fa0, 0(a3)11780; RV64ZVE32F-NEXT: .LBB100_2: # %else11781; RV64ZVE32F-NEXT: andi a3, a2, 211782; RV64ZVE32F-NEXT: beqz a3, .LBB100_411783; RV64ZVE32F-NEXT: # %bb.3: # %cond.load111784; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma11785; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 111786; RV64ZVE32F-NEXT: vmv.x.s a3, v911787; RV64ZVE32F-NEXT: slli a3, a3, 311788; RV64ZVE32F-NEXT: add a3, a1, a311789; RV64ZVE32F-NEXT: fld fa1, 0(a3)11790; RV64ZVE32F-NEXT: .LBB100_4: # %else211791; RV64ZVE32F-NEXT: andi a3, a2, 411792; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma11793; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 211794; RV64ZVE32F-NEXT: beqz a3, .LBB100_611795; RV64ZVE32F-NEXT: # %bb.5: # %cond.load411796; RV64ZVE32F-NEXT: vmv.x.s a3, v911797; RV64ZVE32F-NEXT: slli a3, a3, 311798; RV64ZVE32F-NEXT: add a3, a1, a311799; RV64ZVE32F-NEXT: fld fa2, 0(a3)11800; RV64ZVE32F-NEXT: .LBB100_6: # %else511801; RV64ZVE32F-NEXT: andi a3, a2, 811802; RV64ZVE32F-NEXT: beqz a3, .LBB100_811803; RV64ZVE32F-NEXT: # %bb.7: # %cond.load711804; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 111805; RV64ZVE32F-NEXT: vmv.x.s a3, v911806; RV64ZVE32F-NEXT: slli a3, a3, 311807; RV64ZVE32F-NEXT: add a3, a1, a311808; RV64ZVE32F-NEXT: fld fa3, 0(a3)11809; RV64ZVE32F-NEXT: .LBB100_8: # %else811810; RV64ZVE32F-NEXT: andi a3, a2, 1611811; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma11812; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 411813; RV64ZVE32F-NEXT: beqz a3, .LBB100_1011814; RV64ZVE32F-NEXT: # %bb.9: # %cond.load1011815; RV64ZVE32F-NEXT: vmv.x.s a3, v811816; RV64ZVE32F-NEXT: slli a3, a3, 311817; RV64ZVE32F-NEXT: add a3, a1, a311818; RV64ZVE32F-NEXT: fld fa4, 0(a3)11819; RV64ZVE32F-NEXT: .LBB100_10: # %else1111820; RV64ZVE32F-NEXT: andi a3, a2, 3211821; RV64ZVE32F-NEXT: beqz a3, .LBB100_1211822; RV64ZVE32F-NEXT: # %bb.11: # %cond.load1311823; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma11824; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 111825; RV64ZVE32F-NEXT: vmv.x.s a3, v911826; RV64ZVE32F-NEXT: slli a3, a3, 311827; RV64ZVE32F-NEXT: add a3, a1, a311828; RV64ZVE32F-NEXT: fld fa5, 0(a3)11829; RV64ZVE32F-NEXT: .LBB100_12: # %else1411830; RV64ZVE32F-NEXT: andi a3, a2, 6411831; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma11832; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 211833; RV64ZVE32F-NEXT: beqz a3, .LBB100_1411834; RV64ZVE32F-NEXT: # %bb.13: # %cond.load1611835; RV64ZVE32F-NEXT: vmv.x.s a3, v811836; RV64ZVE32F-NEXT: slli a3, a3, 311837; RV64ZVE32F-NEXT: add a3, a1, a311838; RV64ZVE32F-NEXT: fld fa6, 0(a3)11839; RV64ZVE32F-NEXT: .LBB100_14: # %else1711840; RV64ZVE32F-NEXT: andi a2, a2, -12811841; RV64ZVE32F-NEXT: beqz a2, .LBB100_1611842; RV64ZVE32F-NEXT: # %bb.15: # %cond.load1911843; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 111844; RV64ZVE32F-NEXT: vmv.x.s a2, v811845; RV64ZVE32F-NEXT: slli a2, a2, 311846; RV64ZVE32F-NEXT: add a1, a1, a211847; RV64ZVE32F-NEXT: fld fa7, 0(a1)11848; RV64ZVE32F-NEXT: .LBB100_16: # %else2011849; RV64ZVE32F-NEXT: fsd fa0, 0(a0)11850; RV64ZVE32F-NEXT: fsd fa1, 8(a0)11851; RV64ZVE32F-NEXT: fsd fa2, 16(a0)11852; RV64ZVE32F-NEXT: fsd fa3, 24(a0)11853; RV64ZVE32F-NEXT: fsd fa4, 32(a0)11854; RV64ZVE32F-NEXT: fsd fa5, 40(a0)11855; RV64ZVE32F-NEXT: fsd fa6, 48(a0)11856; RV64ZVE32F-NEXT: fsd fa7, 56(a0)11857; RV64ZVE32F-NEXT: ret11858 %ptrs = getelementptr inbounds double, ptr %base, <8 x i16> %idxs11859 %v = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> %ptrs, i32 8, <8 x i1> %m, <8 x double> %passthru)11860 ret <8 x double> %v11861}11862 11863define <8 x double> @mgather_baseidx_sext_v8i16_v8f64(ptr %base, <8 x i16> %idxs, <8 x i1> %m, <8 x double> %passthru) {11864; RV32V-LABEL: mgather_baseidx_sext_v8i16_v8f64:11865; RV32V: # %bb.0:11866; RV32V-NEXT: li a1, 811867; RV32V-NEXT: vsetivli zero, 8, e16, m1, ta, ma11868; RV32V-NEXT: vwmulsu.vx v10, v8, a111869; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, mu11870; RV32V-NEXT: vluxei32.v v12, (a0), v10, v0.t11871; RV32V-NEXT: vmv.v.v v8, v1211872; RV32V-NEXT: ret11873;11874; RV64V-LABEL: mgather_baseidx_sext_v8i16_v8f64:11875; RV64V: # %bb.0:11876; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, mu11877; RV64V-NEXT: vsext.vf4 v16, v811878; RV64V-NEXT: vsll.vi v8, v16, 311879; RV64V-NEXT: vluxei64.v v12, (a0), v8, v0.t11880; RV64V-NEXT: vmv.v.v v8, v1211881; RV64V-NEXT: ret11882;11883; RV32ZVE32F-LABEL: mgather_baseidx_sext_v8i16_v8f64:11884; RV32ZVE32F: # %bb.0:11885; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma11886; RV32ZVE32F-NEXT: vmv.v.x v10, a111887; RV32ZVE32F-NEXT: li a2, 811888; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma11889; RV32ZVE32F-NEXT: vmv.x.s a1, v011890; RV32ZVE32F-NEXT: andi a3, a1, 111891; RV32ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma11892; RV32ZVE32F-NEXT: vwmaccus.vx v10, a2, v811893; RV32ZVE32F-NEXT: bnez a3, .LBB101_1011894; RV32ZVE32F-NEXT: # %bb.1: # %else11895; RV32ZVE32F-NEXT: andi a2, a1, 211896; RV32ZVE32F-NEXT: bnez a2, .LBB101_1111897; RV32ZVE32F-NEXT: .LBB101_2: # %else211898; RV32ZVE32F-NEXT: andi a2, a1, 411899; RV32ZVE32F-NEXT: bnez a2, .LBB101_1211900; RV32ZVE32F-NEXT: .LBB101_3: # %else511901; RV32ZVE32F-NEXT: andi a2, a1, 811902; RV32ZVE32F-NEXT: bnez a2, .LBB101_1311903; RV32ZVE32F-NEXT: .LBB101_4: # %else811904; RV32ZVE32F-NEXT: andi a2, a1, 1611905; RV32ZVE32F-NEXT: bnez a2, .LBB101_1411906; RV32ZVE32F-NEXT: .LBB101_5: # %else1111907; RV32ZVE32F-NEXT: andi a2, a1, 3211908; RV32ZVE32F-NEXT: bnez a2, .LBB101_1511909; RV32ZVE32F-NEXT: .LBB101_6: # %else1411910; RV32ZVE32F-NEXT: andi a2, a1, 6411911; RV32ZVE32F-NEXT: bnez a2, .LBB101_1611912; RV32ZVE32F-NEXT: .LBB101_7: # %else1711913; RV32ZVE32F-NEXT: andi a1, a1, -12811914; RV32ZVE32F-NEXT: beqz a1, .LBB101_911915; RV32ZVE32F-NEXT: .LBB101_8: # %cond.load1911916; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma11917; RV32ZVE32F-NEXT: vslidedown.vi v8, v10, 711918; RV32ZVE32F-NEXT: vmv.x.s a1, v811919; RV32ZVE32F-NEXT: fld fa7, 0(a1)11920; RV32ZVE32F-NEXT: .LBB101_9: # %else2011921; RV32ZVE32F-NEXT: fsd fa0, 0(a0)11922; RV32ZVE32F-NEXT: fsd fa1, 8(a0)11923; RV32ZVE32F-NEXT: fsd fa2, 16(a0)11924; RV32ZVE32F-NEXT: fsd fa3, 24(a0)11925; RV32ZVE32F-NEXT: fsd fa4, 32(a0)11926; RV32ZVE32F-NEXT: fsd fa5, 40(a0)11927; RV32ZVE32F-NEXT: fsd fa6, 48(a0)11928; RV32ZVE32F-NEXT: fsd fa7, 56(a0)11929; RV32ZVE32F-NEXT: ret11930; RV32ZVE32F-NEXT: .LBB101_10: # %cond.load11931; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma11932; RV32ZVE32F-NEXT: vmv.x.s a2, v1011933; RV32ZVE32F-NEXT: fld fa0, 0(a2)11934; RV32ZVE32F-NEXT: andi a2, a1, 211935; RV32ZVE32F-NEXT: beqz a2, .LBB101_211936; RV32ZVE32F-NEXT: .LBB101_11: # %cond.load111937; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma11938; RV32ZVE32F-NEXT: vslidedown.vi v8, v10, 111939; RV32ZVE32F-NEXT: vmv.x.s a2, v811940; RV32ZVE32F-NEXT: fld fa1, 0(a2)11941; RV32ZVE32F-NEXT: andi a2, a1, 411942; RV32ZVE32F-NEXT: beqz a2, .LBB101_311943; RV32ZVE32F-NEXT: .LBB101_12: # %cond.load411944; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma11945; RV32ZVE32F-NEXT: vslidedown.vi v8, v10, 211946; RV32ZVE32F-NEXT: vmv.x.s a2, v811947; RV32ZVE32F-NEXT: fld fa2, 0(a2)11948; RV32ZVE32F-NEXT: andi a2, a1, 811949; RV32ZVE32F-NEXT: beqz a2, .LBB101_411950; RV32ZVE32F-NEXT: .LBB101_13: # %cond.load711951; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma11952; RV32ZVE32F-NEXT: vslidedown.vi v8, v10, 311953; RV32ZVE32F-NEXT: vmv.x.s a2, v811954; RV32ZVE32F-NEXT: fld fa3, 0(a2)11955; RV32ZVE32F-NEXT: andi a2, a1, 1611956; RV32ZVE32F-NEXT: beqz a2, .LBB101_511957; RV32ZVE32F-NEXT: .LBB101_14: # %cond.load1011958; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma11959; RV32ZVE32F-NEXT: vslidedown.vi v8, v10, 411960; RV32ZVE32F-NEXT: vmv.x.s a2, v811961; RV32ZVE32F-NEXT: fld fa4, 0(a2)11962; RV32ZVE32F-NEXT: andi a2, a1, 3211963; RV32ZVE32F-NEXT: beqz a2, .LBB101_611964; RV32ZVE32F-NEXT: .LBB101_15: # %cond.load1311965; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma11966; RV32ZVE32F-NEXT: vslidedown.vi v8, v10, 511967; RV32ZVE32F-NEXT: vmv.x.s a2, v811968; RV32ZVE32F-NEXT: fld fa5, 0(a2)11969; RV32ZVE32F-NEXT: andi a2, a1, 6411970; RV32ZVE32F-NEXT: beqz a2, .LBB101_711971; RV32ZVE32F-NEXT: .LBB101_16: # %cond.load1611972; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma11973; RV32ZVE32F-NEXT: vslidedown.vi v8, v10, 611974; RV32ZVE32F-NEXT: vmv.x.s a2, v811975; RV32ZVE32F-NEXT: fld fa6, 0(a2)11976; RV32ZVE32F-NEXT: andi a1, a1, -12811977; RV32ZVE32F-NEXT: bnez a1, .LBB101_811978; RV32ZVE32F-NEXT: j .LBB101_911979;11980; RV64ZVE32F-LABEL: mgather_baseidx_sext_v8i16_v8f64:11981; RV64ZVE32F: # %bb.0:11982; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma11983; RV64ZVE32F-NEXT: vmv.x.s a2, v011984; RV64ZVE32F-NEXT: andi a3, a2, 111985; RV64ZVE32F-NEXT: beqz a3, .LBB101_211986; RV64ZVE32F-NEXT: # %bb.1: # %cond.load11987; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma11988; RV64ZVE32F-NEXT: vmv.x.s a3, v811989; RV64ZVE32F-NEXT: slli a3, a3, 311990; RV64ZVE32F-NEXT: add a3, a1, a311991; RV64ZVE32F-NEXT: fld fa0, 0(a3)11992; RV64ZVE32F-NEXT: .LBB101_2: # %else11993; RV64ZVE32F-NEXT: andi a3, a2, 211994; RV64ZVE32F-NEXT: beqz a3, .LBB101_411995; RV64ZVE32F-NEXT: # %bb.3: # %cond.load111996; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma11997; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 111998; RV64ZVE32F-NEXT: vmv.x.s a3, v911999; RV64ZVE32F-NEXT: slli a3, a3, 312000; RV64ZVE32F-NEXT: add a3, a1, a312001; RV64ZVE32F-NEXT: fld fa1, 0(a3)12002; RV64ZVE32F-NEXT: .LBB101_4: # %else212003; RV64ZVE32F-NEXT: andi a3, a2, 412004; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma12005; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 212006; RV64ZVE32F-NEXT: beqz a3, .LBB101_612007; RV64ZVE32F-NEXT: # %bb.5: # %cond.load412008; RV64ZVE32F-NEXT: vmv.x.s a3, v912009; RV64ZVE32F-NEXT: slli a3, a3, 312010; RV64ZVE32F-NEXT: add a3, a1, a312011; RV64ZVE32F-NEXT: fld fa2, 0(a3)12012; RV64ZVE32F-NEXT: .LBB101_6: # %else512013; RV64ZVE32F-NEXT: andi a3, a2, 812014; RV64ZVE32F-NEXT: beqz a3, .LBB101_812015; RV64ZVE32F-NEXT: # %bb.7: # %cond.load712016; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 112017; RV64ZVE32F-NEXT: vmv.x.s a3, v912018; RV64ZVE32F-NEXT: slli a3, a3, 312019; RV64ZVE32F-NEXT: add a3, a1, a312020; RV64ZVE32F-NEXT: fld fa3, 0(a3)12021; RV64ZVE32F-NEXT: .LBB101_8: # %else812022; RV64ZVE32F-NEXT: andi a3, a2, 1612023; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma12024; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 412025; RV64ZVE32F-NEXT: beqz a3, .LBB101_1012026; RV64ZVE32F-NEXT: # %bb.9: # %cond.load1012027; RV64ZVE32F-NEXT: vmv.x.s a3, v812028; RV64ZVE32F-NEXT: slli a3, a3, 312029; RV64ZVE32F-NEXT: add a3, a1, a312030; RV64ZVE32F-NEXT: fld fa4, 0(a3)12031; RV64ZVE32F-NEXT: .LBB101_10: # %else1112032; RV64ZVE32F-NEXT: andi a3, a2, 3212033; RV64ZVE32F-NEXT: beqz a3, .LBB101_1212034; RV64ZVE32F-NEXT: # %bb.11: # %cond.load1312035; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma12036; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 112037; RV64ZVE32F-NEXT: vmv.x.s a3, v912038; RV64ZVE32F-NEXT: slli a3, a3, 312039; RV64ZVE32F-NEXT: add a3, a1, a312040; RV64ZVE32F-NEXT: fld fa5, 0(a3)12041; RV64ZVE32F-NEXT: .LBB101_12: # %else1412042; RV64ZVE32F-NEXT: andi a3, a2, 6412043; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma12044; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 212045; RV64ZVE32F-NEXT: beqz a3, .LBB101_1412046; RV64ZVE32F-NEXT: # %bb.13: # %cond.load1612047; RV64ZVE32F-NEXT: vmv.x.s a3, v812048; RV64ZVE32F-NEXT: slli a3, a3, 312049; RV64ZVE32F-NEXT: add a3, a1, a312050; RV64ZVE32F-NEXT: fld fa6, 0(a3)12051; RV64ZVE32F-NEXT: .LBB101_14: # %else1712052; RV64ZVE32F-NEXT: andi a2, a2, -12812053; RV64ZVE32F-NEXT: beqz a2, .LBB101_1612054; RV64ZVE32F-NEXT: # %bb.15: # %cond.load1912055; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 112056; RV64ZVE32F-NEXT: vmv.x.s a2, v812057; RV64ZVE32F-NEXT: slli a2, a2, 312058; RV64ZVE32F-NEXT: add a1, a1, a212059; RV64ZVE32F-NEXT: fld fa7, 0(a1)12060; RV64ZVE32F-NEXT: .LBB101_16: # %else2012061; RV64ZVE32F-NEXT: fsd fa0, 0(a0)12062; RV64ZVE32F-NEXT: fsd fa1, 8(a0)12063; RV64ZVE32F-NEXT: fsd fa2, 16(a0)12064; RV64ZVE32F-NEXT: fsd fa3, 24(a0)12065; RV64ZVE32F-NEXT: fsd fa4, 32(a0)12066; RV64ZVE32F-NEXT: fsd fa5, 40(a0)12067; RV64ZVE32F-NEXT: fsd fa6, 48(a0)12068; RV64ZVE32F-NEXT: fsd fa7, 56(a0)12069; RV64ZVE32F-NEXT: ret12070 %eidxs = sext <8 x i16> %idxs to <8 x i64>12071 %ptrs = getelementptr inbounds double, ptr %base, <8 x i64> %eidxs12072 %v = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> %ptrs, i32 8, <8 x i1> %m, <8 x double> %passthru)12073 ret <8 x double> %v12074}12075 12076define <8 x double> @mgather_baseidx_zext_v8i16_v8f64(ptr %base, <8 x i16> %idxs, <8 x i1> %m, <8 x double> %passthru) {12077; RV32V-LABEL: mgather_baseidx_zext_v8i16_v8f64:12078; RV32V: # %bb.0:12079; RV32V-NEXT: li a1, 812080; RV32V-NEXT: vsetivli zero, 8, e16, m1, ta, ma12081; RV32V-NEXT: vwmulu.vx v10, v8, a112082; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, mu12083; RV32V-NEXT: vluxei32.v v12, (a0), v10, v0.t12084; RV32V-NEXT: vmv.v.v v8, v1212085; RV32V-NEXT: ret12086;12087; RV64V-LABEL: mgather_baseidx_zext_v8i16_v8f64:12088; RV64V: # %bb.0:12089; RV64V-NEXT: li a1, 812090; RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, ma12091; RV64V-NEXT: vwmulu.vx v10, v8, a112092; RV64V-NEXT: vsetvli zero, zero, e64, m4, ta, mu12093; RV64V-NEXT: vluxei32.v v12, (a0), v10, v0.t12094; RV64V-NEXT: vmv.v.v v8, v1212095; RV64V-NEXT: ret12096;12097; RV32ZVE32F-LABEL: mgather_baseidx_zext_v8i16_v8f64:12098; RV32ZVE32F: # %bb.0:12099; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma12100; RV32ZVE32F-NEXT: vmv.v.x v10, a112101; RV32ZVE32F-NEXT: li a2, 812102; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma12103; RV32ZVE32F-NEXT: vmv.x.s a1, v012104; RV32ZVE32F-NEXT: andi a3, a1, 112105; RV32ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma12106; RV32ZVE32F-NEXT: vwmaccu.vx v10, a2, v812107; RV32ZVE32F-NEXT: bnez a3, .LBB102_1012108; RV32ZVE32F-NEXT: # %bb.1: # %else12109; RV32ZVE32F-NEXT: andi a2, a1, 212110; RV32ZVE32F-NEXT: bnez a2, .LBB102_1112111; RV32ZVE32F-NEXT: .LBB102_2: # %else212112; RV32ZVE32F-NEXT: andi a2, a1, 412113; RV32ZVE32F-NEXT: bnez a2, .LBB102_1212114; RV32ZVE32F-NEXT: .LBB102_3: # %else512115; RV32ZVE32F-NEXT: andi a2, a1, 812116; RV32ZVE32F-NEXT: bnez a2, .LBB102_1312117; RV32ZVE32F-NEXT: .LBB102_4: # %else812118; RV32ZVE32F-NEXT: andi a2, a1, 1612119; RV32ZVE32F-NEXT: bnez a2, .LBB102_1412120; RV32ZVE32F-NEXT: .LBB102_5: # %else1112121; RV32ZVE32F-NEXT: andi a2, a1, 3212122; RV32ZVE32F-NEXT: bnez a2, .LBB102_1512123; RV32ZVE32F-NEXT: .LBB102_6: # %else1412124; RV32ZVE32F-NEXT: andi a2, a1, 6412125; RV32ZVE32F-NEXT: bnez a2, .LBB102_1612126; RV32ZVE32F-NEXT: .LBB102_7: # %else1712127; RV32ZVE32F-NEXT: andi a1, a1, -12812128; RV32ZVE32F-NEXT: beqz a1, .LBB102_912129; RV32ZVE32F-NEXT: .LBB102_8: # %cond.load1912130; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma12131; RV32ZVE32F-NEXT: vslidedown.vi v8, v10, 712132; RV32ZVE32F-NEXT: vmv.x.s a1, v812133; RV32ZVE32F-NEXT: fld fa7, 0(a1)12134; RV32ZVE32F-NEXT: .LBB102_9: # %else2012135; RV32ZVE32F-NEXT: fsd fa0, 0(a0)12136; RV32ZVE32F-NEXT: fsd fa1, 8(a0)12137; RV32ZVE32F-NEXT: fsd fa2, 16(a0)12138; RV32ZVE32F-NEXT: fsd fa3, 24(a0)12139; RV32ZVE32F-NEXT: fsd fa4, 32(a0)12140; RV32ZVE32F-NEXT: fsd fa5, 40(a0)12141; RV32ZVE32F-NEXT: fsd fa6, 48(a0)12142; RV32ZVE32F-NEXT: fsd fa7, 56(a0)12143; RV32ZVE32F-NEXT: ret12144; RV32ZVE32F-NEXT: .LBB102_10: # %cond.load12145; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma12146; RV32ZVE32F-NEXT: vmv.x.s a2, v1012147; RV32ZVE32F-NEXT: fld fa0, 0(a2)12148; RV32ZVE32F-NEXT: andi a2, a1, 212149; RV32ZVE32F-NEXT: beqz a2, .LBB102_212150; RV32ZVE32F-NEXT: .LBB102_11: # %cond.load112151; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma12152; RV32ZVE32F-NEXT: vslidedown.vi v8, v10, 112153; RV32ZVE32F-NEXT: vmv.x.s a2, v812154; RV32ZVE32F-NEXT: fld fa1, 0(a2)12155; RV32ZVE32F-NEXT: andi a2, a1, 412156; RV32ZVE32F-NEXT: beqz a2, .LBB102_312157; RV32ZVE32F-NEXT: .LBB102_12: # %cond.load412158; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma12159; RV32ZVE32F-NEXT: vslidedown.vi v8, v10, 212160; RV32ZVE32F-NEXT: vmv.x.s a2, v812161; RV32ZVE32F-NEXT: fld fa2, 0(a2)12162; RV32ZVE32F-NEXT: andi a2, a1, 812163; RV32ZVE32F-NEXT: beqz a2, .LBB102_412164; RV32ZVE32F-NEXT: .LBB102_13: # %cond.load712165; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma12166; RV32ZVE32F-NEXT: vslidedown.vi v8, v10, 312167; RV32ZVE32F-NEXT: vmv.x.s a2, v812168; RV32ZVE32F-NEXT: fld fa3, 0(a2)12169; RV32ZVE32F-NEXT: andi a2, a1, 1612170; RV32ZVE32F-NEXT: beqz a2, .LBB102_512171; RV32ZVE32F-NEXT: .LBB102_14: # %cond.load1012172; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma12173; RV32ZVE32F-NEXT: vslidedown.vi v8, v10, 412174; RV32ZVE32F-NEXT: vmv.x.s a2, v812175; RV32ZVE32F-NEXT: fld fa4, 0(a2)12176; RV32ZVE32F-NEXT: andi a2, a1, 3212177; RV32ZVE32F-NEXT: beqz a2, .LBB102_612178; RV32ZVE32F-NEXT: .LBB102_15: # %cond.load1312179; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma12180; RV32ZVE32F-NEXT: vslidedown.vi v8, v10, 512181; RV32ZVE32F-NEXT: vmv.x.s a2, v812182; RV32ZVE32F-NEXT: fld fa5, 0(a2)12183; RV32ZVE32F-NEXT: andi a2, a1, 6412184; RV32ZVE32F-NEXT: beqz a2, .LBB102_712185; RV32ZVE32F-NEXT: .LBB102_16: # %cond.load1612186; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma12187; RV32ZVE32F-NEXT: vslidedown.vi v8, v10, 612188; RV32ZVE32F-NEXT: vmv.x.s a2, v812189; RV32ZVE32F-NEXT: fld fa6, 0(a2)12190; RV32ZVE32F-NEXT: andi a1, a1, -12812191; RV32ZVE32F-NEXT: bnez a1, .LBB102_812192; RV32ZVE32F-NEXT: j .LBB102_912193;12194; RV64ZVE32F-LABEL: mgather_baseidx_zext_v8i16_v8f64:12195; RV64ZVE32F: # %bb.0:12196; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma12197; RV64ZVE32F-NEXT: vmv.x.s a2, v012198; RV64ZVE32F-NEXT: andi a3, a2, 112199; RV64ZVE32F-NEXT: beqz a3, .LBB102_212200; RV64ZVE32F-NEXT: # %bb.1: # %cond.load12201; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma12202; RV64ZVE32F-NEXT: vmv.x.s a3, v812203; RV64ZVE32F-NEXT: slli a3, a3, 4812204; RV64ZVE32F-NEXT: srli a3, a3, 4512205; RV64ZVE32F-NEXT: add a3, a1, a312206; RV64ZVE32F-NEXT: fld fa0, 0(a3)12207; RV64ZVE32F-NEXT: .LBB102_2: # %else12208; RV64ZVE32F-NEXT: andi a3, a2, 212209; RV64ZVE32F-NEXT: beqz a3, .LBB102_412210; RV64ZVE32F-NEXT: # %bb.3: # %cond.load112211; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma12212; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 112213; RV64ZVE32F-NEXT: vmv.x.s a3, v912214; RV64ZVE32F-NEXT: slli a3, a3, 4812215; RV64ZVE32F-NEXT: srli a3, a3, 4512216; RV64ZVE32F-NEXT: add a3, a1, a312217; RV64ZVE32F-NEXT: fld fa1, 0(a3)12218; RV64ZVE32F-NEXT: .LBB102_4: # %else212219; RV64ZVE32F-NEXT: andi a3, a2, 412220; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma12221; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 212222; RV64ZVE32F-NEXT: beqz a3, .LBB102_612223; RV64ZVE32F-NEXT: # %bb.5: # %cond.load412224; RV64ZVE32F-NEXT: vmv.x.s a3, v912225; RV64ZVE32F-NEXT: slli a3, a3, 4812226; RV64ZVE32F-NEXT: srli a3, a3, 4512227; RV64ZVE32F-NEXT: add a3, a1, a312228; RV64ZVE32F-NEXT: fld fa2, 0(a3)12229; RV64ZVE32F-NEXT: .LBB102_6: # %else512230; RV64ZVE32F-NEXT: andi a3, a2, 812231; RV64ZVE32F-NEXT: beqz a3, .LBB102_812232; RV64ZVE32F-NEXT: # %bb.7: # %cond.load712233; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 112234; RV64ZVE32F-NEXT: vmv.x.s a3, v912235; RV64ZVE32F-NEXT: slli a3, a3, 4812236; RV64ZVE32F-NEXT: srli a3, a3, 4512237; RV64ZVE32F-NEXT: add a3, a1, a312238; RV64ZVE32F-NEXT: fld fa3, 0(a3)12239; RV64ZVE32F-NEXT: .LBB102_8: # %else812240; RV64ZVE32F-NEXT: andi a3, a2, 1612241; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma12242; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 412243; RV64ZVE32F-NEXT: beqz a3, .LBB102_1012244; RV64ZVE32F-NEXT: # %bb.9: # %cond.load1012245; RV64ZVE32F-NEXT: vmv.x.s a3, v812246; RV64ZVE32F-NEXT: slli a3, a3, 4812247; RV64ZVE32F-NEXT: srli a3, a3, 4512248; RV64ZVE32F-NEXT: add a3, a1, a312249; RV64ZVE32F-NEXT: fld fa4, 0(a3)12250; RV64ZVE32F-NEXT: .LBB102_10: # %else1112251; RV64ZVE32F-NEXT: andi a3, a2, 3212252; RV64ZVE32F-NEXT: beqz a3, .LBB102_1212253; RV64ZVE32F-NEXT: # %bb.11: # %cond.load1312254; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma12255; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 112256; RV64ZVE32F-NEXT: vmv.x.s a3, v912257; RV64ZVE32F-NEXT: slli a3, a3, 4812258; RV64ZVE32F-NEXT: srli a3, a3, 4512259; RV64ZVE32F-NEXT: add a3, a1, a312260; RV64ZVE32F-NEXT: fld fa5, 0(a3)12261; RV64ZVE32F-NEXT: .LBB102_12: # %else1412262; RV64ZVE32F-NEXT: andi a3, a2, 6412263; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma12264; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 212265; RV64ZVE32F-NEXT: beqz a3, .LBB102_1412266; RV64ZVE32F-NEXT: # %bb.13: # %cond.load1612267; RV64ZVE32F-NEXT: vmv.x.s a3, v812268; RV64ZVE32F-NEXT: slli a3, a3, 4812269; RV64ZVE32F-NEXT: srli a3, a3, 4512270; RV64ZVE32F-NEXT: add a3, a1, a312271; RV64ZVE32F-NEXT: fld fa6, 0(a3)12272; RV64ZVE32F-NEXT: .LBB102_14: # %else1712273; RV64ZVE32F-NEXT: andi a2, a2, -12812274; RV64ZVE32F-NEXT: beqz a2, .LBB102_1612275; RV64ZVE32F-NEXT: # %bb.15: # %cond.load1912276; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 112277; RV64ZVE32F-NEXT: vmv.x.s a2, v812278; RV64ZVE32F-NEXT: slli a2, a2, 4812279; RV64ZVE32F-NEXT: srli a2, a2, 4512280; RV64ZVE32F-NEXT: add a1, a1, a212281; RV64ZVE32F-NEXT: fld fa7, 0(a1)12282; RV64ZVE32F-NEXT: .LBB102_16: # %else2012283; RV64ZVE32F-NEXT: fsd fa0, 0(a0)12284; RV64ZVE32F-NEXT: fsd fa1, 8(a0)12285; RV64ZVE32F-NEXT: fsd fa2, 16(a0)12286; RV64ZVE32F-NEXT: fsd fa3, 24(a0)12287; RV64ZVE32F-NEXT: fsd fa4, 32(a0)12288; RV64ZVE32F-NEXT: fsd fa5, 40(a0)12289; RV64ZVE32F-NEXT: fsd fa6, 48(a0)12290; RV64ZVE32F-NEXT: fsd fa7, 56(a0)12291; RV64ZVE32F-NEXT: ret12292 %eidxs = zext <8 x i16> %idxs to <8 x i64>12293 %ptrs = getelementptr inbounds double, ptr %base, <8 x i64> %eidxs12294 %v = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> %ptrs, i32 8, <8 x i1> %m, <8 x double> %passthru)12295 ret <8 x double> %v12296}12297 12298define <8 x double> @mgather_baseidx_v8i32_v8f64(ptr %base, <8 x i32> %idxs, <8 x i1> %m, <8 x double> %passthru) {12299; RV32V-LABEL: mgather_baseidx_v8i32_v8f64:12300; RV32V: # %bb.0:12301; RV32V-NEXT: vsetivli zero, 8, e32, m2, ta, ma12302; RV32V-NEXT: vsll.vi v8, v8, 312303; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, mu12304; RV32V-NEXT: vluxei32.v v12, (a0), v8, v0.t12305; RV32V-NEXT: vmv.v.v v8, v1212306; RV32V-NEXT: ret12307;12308; RV64V-LABEL: mgather_baseidx_v8i32_v8f64:12309; RV64V: # %bb.0:12310; RV64V-NEXT: li a1, 812311; RV64V-NEXT: vsetivli zero, 8, e32, m2, ta, ma12312; RV64V-NEXT: vwmulsu.vx v16, v8, a112313; RV64V-NEXT: vsetvli zero, zero, e64, m4, ta, mu12314; RV64V-NEXT: vluxei64.v v12, (a0), v16, v0.t12315; RV64V-NEXT: vmv.v.v v8, v1212316; RV64V-NEXT: ret12317;12318; RV32ZVE32F-LABEL: mgather_baseidx_v8i32_v8f64:12319; RV32ZVE32F: # %bb.0:12320; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma12321; RV32ZVE32F-NEXT: vsll.vi v8, v8, 312322; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma12323; RV32ZVE32F-NEXT: vmv.x.s a2, v012324; RV32ZVE32F-NEXT: andi a3, a2, 112325; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma12326; RV32ZVE32F-NEXT: vadd.vx v8, v8, a112327; RV32ZVE32F-NEXT: bnez a3, .LBB103_1012328; RV32ZVE32F-NEXT: # %bb.1: # %else12329; RV32ZVE32F-NEXT: andi a1, a2, 212330; RV32ZVE32F-NEXT: bnez a1, .LBB103_1112331; RV32ZVE32F-NEXT: .LBB103_2: # %else212332; RV32ZVE32F-NEXT: andi a1, a2, 412333; RV32ZVE32F-NEXT: bnez a1, .LBB103_1212334; RV32ZVE32F-NEXT: .LBB103_3: # %else512335; RV32ZVE32F-NEXT: andi a1, a2, 812336; RV32ZVE32F-NEXT: bnez a1, .LBB103_1312337; RV32ZVE32F-NEXT: .LBB103_4: # %else812338; RV32ZVE32F-NEXT: andi a1, a2, 1612339; RV32ZVE32F-NEXT: bnez a1, .LBB103_1412340; RV32ZVE32F-NEXT: .LBB103_5: # %else1112341; RV32ZVE32F-NEXT: andi a1, a2, 3212342; RV32ZVE32F-NEXT: bnez a1, .LBB103_1512343; RV32ZVE32F-NEXT: .LBB103_6: # %else1412344; RV32ZVE32F-NEXT: andi a1, a2, 6412345; RV32ZVE32F-NEXT: bnez a1, .LBB103_1612346; RV32ZVE32F-NEXT: .LBB103_7: # %else1712347; RV32ZVE32F-NEXT: andi a1, a2, -12812348; RV32ZVE32F-NEXT: beqz a1, .LBB103_912349; RV32ZVE32F-NEXT: .LBB103_8: # %cond.load1912350; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma12351; RV32ZVE32F-NEXT: vslidedown.vi v8, v8, 712352; RV32ZVE32F-NEXT: vmv.x.s a1, v812353; RV32ZVE32F-NEXT: fld fa7, 0(a1)12354; RV32ZVE32F-NEXT: .LBB103_9: # %else2012355; RV32ZVE32F-NEXT: fsd fa0, 0(a0)12356; RV32ZVE32F-NEXT: fsd fa1, 8(a0)12357; RV32ZVE32F-NEXT: fsd fa2, 16(a0)12358; RV32ZVE32F-NEXT: fsd fa3, 24(a0)12359; RV32ZVE32F-NEXT: fsd fa4, 32(a0)12360; RV32ZVE32F-NEXT: fsd fa5, 40(a0)12361; RV32ZVE32F-NEXT: fsd fa6, 48(a0)12362; RV32ZVE32F-NEXT: fsd fa7, 56(a0)12363; RV32ZVE32F-NEXT: ret12364; RV32ZVE32F-NEXT: .LBB103_10: # %cond.load12365; RV32ZVE32F-NEXT: vmv.x.s a1, v812366; RV32ZVE32F-NEXT: fld fa0, 0(a1)12367; RV32ZVE32F-NEXT: andi a1, a2, 212368; RV32ZVE32F-NEXT: beqz a1, .LBB103_212369; RV32ZVE32F-NEXT: .LBB103_11: # %cond.load112370; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma12371; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 112372; RV32ZVE32F-NEXT: vmv.x.s a1, v1012373; RV32ZVE32F-NEXT: fld fa1, 0(a1)12374; RV32ZVE32F-NEXT: andi a1, a2, 412375; RV32ZVE32F-NEXT: beqz a1, .LBB103_312376; RV32ZVE32F-NEXT: .LBB103_12: # %cond.load412377; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma12378; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 212379; RV32ZVE32F-NEXT: vmv.x.s a1, v1012380; RV32ZVE32F-NEXT: fld fa2, 0(a1)12381; RV32ZVE32F-NEXT: andi a1, a2, 812382; RV32ZVE32F-NEXT: beqz a1, .LBB103_412383; RV32ZVE32F-NEXT: .LBB103_13: # %cond.load712384; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma12385; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 312386; RV32ZVE32F-NEXT: vmv.x.s a1, v1012387; RV32ZVE32F-NEXT: fld fa3, 0(a1)12388; RV32ZVE32F-NEXT: andi a1, a2, 1612389; RV32ZVE32F-NEXT: beqz a1, .LBB103_512390; RV32ZVE32F-NEXT: .LBB103_14: # %cond.load1012391; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma12392; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 412393; RV32ZVE32F-NEXT: vmv.x.s a1, v1012394; RV32ZVE32F-NEXT: fld fa4, 0(a1)12395; RV32ZVE32F-NEXT: andi a1, a2, 3212396; RV32ZVE32F-NEXT: beqz a1, .LBB103_612397; RV32ZVE32F-NEXT: .LBB103_15: # %cond.load1312398; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma12399; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 512400; RV32ZVE32F-NEXT: vmv.x.s a1, v1012401; RV32ZVE32F-NEXT: fld fa5, 0(a1)12402; RV32ZVE32F-NEXT: andi a1, a2, 6412403; RV32ZVE32F-NEXT: beqz a1, .LBB103_712404; RV32ZVE32F-NEXT: .LBB103_16: # %cond.load1612405; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma12406; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 612407; RV32ZVE32F-NEXT: vmv.x.s a1, v1012408; RV32ZVE32F-NEXT: fld fa6, 0(a1)12409; RV32ZVE32F-NEXT: andi a1, a2, -12812410; RV32ZVE32F-NEXT: bnez a1, .LBB103_812411; RV32ZVE32F-NEXT: j .LBB103_912412;12413; RV64ZVE32F-LABEL: mgather_baseidx_v8i32_v8f64:12414; RV64ZVE32F: # %bb.0:12415; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma12416; RV64ZVE32F-NEXT: vmv.x.s a2, v012417; RV64ZVE32F-NEXT: andi a3, a2, 112418; RV64ZVE32F-NEXT: beqz a3, .LBB103_212419; RV64ZVE32F-NEXT: # %bb.1: # %cond.load12420; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma12421; RV64ZVE32F-NEXT: vmv.x.s a3, v812422; RV64ZVE32F-NEXT: slli a3, a3, 312423; RV64ZVE32F-NEXT: add a3, a1, a312424; RV64ZVE32F-NEXT: fld fa0, 0(a3)12425; RV64ZVE32F-NEXT: .LBB103_2: # %else12426; RV64ZVE32F-NEXT: andi a3, a2, 212427; RV64ZVE32F-NEXT: beqz a3, .LBB103_412428; RV64ZVE32F-NEXT: # %bb.3: # %cond.load112429; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma12430; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 112431; RV64ZVE32F-NEXT: vmv.x.s a3, v1012432; RV64ZVE32F-NEXT: slli a3, a3, 312433; RV64ZVE32F-NEXT: add a3, a1, a312434; RV64ZVE32F-NEXT: fld fa1, 0(a3)12435; RV64ZVE32F-NEXT: .LBB103_4: # %else212436; RV64ZVE32F-NEXT: andi a3, a2, 412437; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma12438; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 212439; RV64ZVE32F-NEXT: beqz a3, .LBB103_612440; RV64ZVE32F-NEXT: # %bb.5: # %cond.load412441; RV64ZVE32F-NEXT: vmv.x.s a3, v1012442; RV64ZVE32F-NEXT: slli a3, a3, 312443; RV64ZVE32F-NEXT: add a3, a1, a312444; RV64ZVE32F-NEXT: fld fa2, 0(a3)12445; RV64ZVE32F-NEXT: .LBB103_6: # %else512446; RV64ZVE32F-NEXT: andi a3, a2, 812447; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, ta, ma12448; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 412449; RV64ZVE32F-NEXT: bnez a3, .LBB103_1512450; RV64ZVE32F-NEXT: # %bb.7: # %else812451; RV64ZVE32F-NEXT: andi a3, a2, 1612452; RV64ZVE32F-NEXT: bnez a3, .LBB103_1612453; RV64ZVE32F-NEXT: .LBB103_8: # %else1112454; RV64ZVE32F-NEXT: andi a3, a2, 3212455; RV64ZVE32F-NEXT: beqz a3, .LBB103_1012456; RV64ZVE32F-NEXT: .LBB103_9: # %cond.load1312457; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma12458; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 112459; RV64ZVE32F-NEXT: vmv.x.s a3, v912460; RV64ZVE32F-NEXT: slli a3, a3, 312461; RV64ZVE32F-NEXT: add a3, a1, a312462; RV64ZVE32F-NEXT: fld fa5, 0(a3)12463; RV64ZVE32F-NEXT: .LBB103_10: # %else1412464; RV64ZVE32F-NEXT: andi a3, a2, 6412465; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma12466; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 212467; RV64ZVE32F-NEXT: beqz a3, .LBB103_1212468; RV64ZVE32F-NEXT: # %bb.11: # %cond.load1612469; RV64ZVE32F-NEXT: vmv.x.s a3, v812470; RV64ZVE32F-NEXT: slli a3, a3, 312471; RV64ZVE32F-NEXT: add a3, a1, a312472; RV64ZVE32F-NEXT: fld fa6, 0(a3)12473; RV64ZVE32F-NEXT: .LBB103_12: # %else1712474; RV64ZVE32F-NEXT: andi a2, a2, -12812475; RV64ZVE32F-NEXT: beqz a2, .LBB103_1412476; RV64ZVE32F-NEXT: # %bb.13: # %cond.load1912477; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 112478; RV64ZVE32F-NEXT: vmv.x.s a2, v812479; RV64ZVE32F-NEXT: slli a2, a2, 312480; RV64ZVE32F-NEXT: add a1, a1, a212481; RV64ZVE32F-NEXT: fld fa7, 0(a1)12482; RV64ZVE32F-NEXT: .LBB103_14: # %else2012483; RV64ZVE32F-NEXT: fsd fa0, 0(a0)12484; RV64ZVE32F-NEXT: fsd fa1, 8(a0)12485; RV64ZVE32F-NEXT: fsd fa2, 16(a0)12486; RV64ZVE32F-NEXT: fsd fa3, 24(a0)12487; RV64ZVE32F-NEXT: fsd fa4, 32(a0)12488; RV64ZVE32F-NEXT: fsd fa5, 40(a0)12489; RV64ZVE32F-NEXT: fsd fa6, 48(a0)12490; RV64ZVE32F-NEXT: fsd fa7, 56(a0)12491; RV64ZVE32F-NEXT: ret12492; RV64ZVE32F-NEXT: .LBB103_15: # %cond.load712493; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma12494; RV64ZVE32F-NEXT: vslidedown.vi v9, v10, 112495; RV64ZVE32F-NEXT: vmv.x.s a3, v912496; RV64ZVE32F-NEXT: slli a3, a3, 312497; RV64ZVE32F-NEXT: add a3, a1, a312498; RV64ZVE32F-NEXT: fld fa3, 0(a3)12499; RV64ZVE32F-NEXT: andi a3, a2, 1612500; RV64ZVE32F-NEXT: beqz a3, .LBB103_812501; RV64ZVE32F-NEXT: .LBB103_16: # %cond.load1012502; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma12503; RV64ZVE32F-NEXT: vmv.x.s a3, v812504; RV64ZVE32F-NEXT: slli a3, a3, 312505; RV64ZVE32F-NEXT: add a3, a1, a312506; RV64ZVE32F-NEXT: fld fa4, 0(a3)12507; RV64ZVE32F-NEXT: andi a3, a2, 3212508; RV64ZVE32F-NEXT: bnez a3, .LBB103_912509; RV64ZVE32F-NEXT: j .LBB103_1012510 %ptrs = getelementptr inbounds double, ptr %base, <8 x i32> %idxs12511 %v = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> %ptrs, i32 8, <8 x i1> %m, <8 x double> %passthru)12512 ret <8 x double> %v12513}12514 12515define <8 x double> @mgather_baseidx_sext_v8i32_v8f64(ptr %base, <8 x i32> %idxs, <8 x i1> %m, <8 x double> %passthru) {12516; RV32V-LABEL: mgather_baseidx_sext_v8i32_v8f64:12517; RV32V: # %bb.0:12518; RV32V-NEXT: vsetivli zero, 8, e32, m2, ta, ma12519; RV32V-NEXT: vsll.vi v8, v8, 312520; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, mu12521; RV32V-NEXT: vluxei32.v v12, (a0), v8, v0.t12522; RV32V-NEXT: vmv.v.v v8, v1212523; RV32V-NEXT: ret12524;12525; RV64V-LABEL: mgather_baseidx_sext_v8i32_v8f64:12526; RV64V: # %bb.0:12527; RV64V-NEXT: li a1, 812528; RV64V-NEXT: vsetivli zero, 8, e32, m2, ta, ma12529; RV64V-NEXT: vwmulsu.vx v16, v8, a112530; RV64V-NEXT: vsetvli zero, zero, e64, m4, ta, mu12531; RV64V-NEXT: vluxei64.v v12, (a0), v16, v0.t12532; RV64V-NEXT: vmv.v.v v8, v1212533; RV64V-NEXT: ret12534;12535; RV32ZVE32F-LABEL: mgather_baseidx_sext_v8i32_v8f64:12536; RV32ZVE32F: # %bb.0:12537; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma12538; RV32ZVE32F-NEXT: vsll.vi v8, v8, 312539; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma12540; RV32ZVE32F-NEXT: vmv.x.s a2, v012541; RV32ZVE32F-NEXT: andi a3, a2, 112542; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma12543; RV32ZVE32F-NEXT: vadd.vx v8, v8, a112544; RV32ZVE32F-NEXT: bnez a3, .LBB104_1012545; RV32ZVE32F-NEXT: # %bb.1: # %else12546; RV32ZVE32F-NEXT: andi a1, a2, 212547; RV32ZVE32F-NEXT: bnez a1, .LBB104_1112548; RV32ZVE32F-NEXT: .LBB104_2: # %else212549; RV32ZVE32F-NEXT: andi a1, a2, 412550; RV32ZVE32F-NEXT: bnez a1, .LBB104_1212551; RV32ZVE32F-NEXT: .LBB104_3: # %else512552; RV32ZVE32F-NEXT: andi a1, a2, 812553; RV32ZVE32F-NEXT: bnez a1, .LBB104_1312554; RV32ZVE32F-NEXT: .LBB104_4: # %else812555; RV32ZVE32F-NEXT: andi a1, a2, 1612556; RV32ZVE32F-NEXT: bnez a1, .LBB104_1412557; RV32ZVE32F-NEXT: .LBB104_5: # %else1112558; RV32ZVE32F-NEXT: andi a1, a2, 3212559; RV32ZVE32F-NEXT: bnez a1, .LBB104_1512560; RV32ZVE32F-NEXT: .LBB104_6: # %else1412561; RV32ZVE32F-NEXT: andi a1, a2, 6412562; RV32ZVE32F-NEXT: bnez a1, .LBB104_1612563; RV32ZVE32F-NEXT: .LBB104_7: # %else1712564; RV32ZVE32F-NEXT: andi a1, a2, -12812565; RV32ZVE32F-NEXT: beqz a1, .LBB104_912566; RV32ZVE32F-NEXT: .LBB104_8: # %cond.load1912567; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma12568; RV32ZVE32F-NEXT: vslidedown.vi v8, v8, 712569; RV32ZVE32F-NEXT: vmv.x.s a1, v812570; RV32ZVE32F-NEXT: fld fa7, 0(a1)12571; RV32ZVE32F-NEXT: .LBB104_9: # %else2012572; RV32ZVE32F-NEXT: fsd fa0, 0(a0)12573; RV32ZVE32F-NEXT: fsd fa1, 8(a0)12574; RV32ZVE32F-NEXT: fsd fa2, 16(a0)12575; RV32ZVE32F-NEXT: fsd fa3, 24(a0)12576; RV32ZVE32F-NEXT: fsd fa4, 32(a0)12577; RV32ZVE32F-NEXT: fsd fa5, 40(a0)12578; RV32ZVE32F-NEXT: fsd fa6, 48(a0)12579; RV32ZVE32F-NEXT: fsd fa7, 56(a0)12580; RV32ZVE32F-NEXT: ret12581; RV32ZVE32F-NEXT: .LBB104_10: # %cond.load12582; RV32ZVE32F-NEXT: vmv.x.s a1, v812583; RV32ZVE32F-NEXT: fld fa0, 0(a1)12584; RV32ZVE32F-NEXT: andi a1, a2, 212585; RV32ZVE32F-NEXT: beqz a1, .LBB104_212586; RV32ZVE32F-NEXT: .LBB104_11: # %cond.load112587; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma12588; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 112589; RV32ZVE32F-NEXT: vmv.x.s a1, v1012590; RV32ZVE32F-NEXT: fld fa1, 0(a1)12591; RV32ZVE32F-NEXT: andi a1, a2, 412592; RV32ZVE32F-NEXT: beqz a1, .LBB104_312593; RV32ZVE32F-NEXT: .LBB104_12: # %cond.load412594; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma12595; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 212596; RV32ZVE32F-NEXT: vmv.x.s a1, v1012597; RV32ZVE32F-NEXT: fld fa2, 0(a1)12598; RV32ZVE32F-NEXT: andi a1, a2, 812599; RV32ZVE32F-NEXT: beqz a1, .LBB104_412600; RV32ZVE32F-NEXT: .LBB104_13: # %cond.load712601; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma12602; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 312603; RV32ZVE32F-NEXT: vmv.x.s a1, v1012604; RV32ZVE32F-NEXT: fld fa3, 0(a1)12605; RV32ZVE32F-NEXT: andi a1, a2, 1612606; RV32ZVE32F-NEXT: beqz a1, .LBB104_512607; RV32ZVE32F-NEXT: .LBB104_14: # %cond.load1012608; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma12609; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 412610; RV32ZVE32F-NEXT: vmv.x.s a1, v1012611; RV32ZVE32F-NEXT: fld fa4, 0(a1)12612; RV32ZVE32F-NEXT: andi a1, a2, 3212613; RV32ZVE32F-NEXT: beqz a1, .LBB104_612614; RV32ZVE32F-NEXT: .LBB104_15: # %cond.load1312615; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma12616; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 512617; RV32ZVE32F-NEXT: vmv.x.s a1, v1012618; RV32ZVE32F-NEXT: fld fa5, 0(a1)12619; RV32ZVE32F-NEXT: andi a1, a2, 6412620; RV32ZVE32F-NEXT: beqz a1, .LBB104_712621; RV32ZVE32F-NEXT: .LBB104_16: # %cond.load1612622; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma12623; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 612624; RV32ZVE32F-NEXT: vmv.x.s a1, v1012625; RV32ZVE32F-NEXT: fld fa6, 0(a1)12626; RV32ZVE32F-NEXT: andi a1, a2, -12812627; RV32ZVE32F-NEXT: bnez a1, .LBB104_812628; RV32ZVE32F-NEXT: j .LBB104_912629;12630; RV64ZVE32F-LABEL: mgather_baseidx_sext_v8i32_v8f64:12631; RV64ZVE32F: # %bb.0:12632; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma12633; RV64ZVE32F-NEXT: vmv.x.s a2, v012634; RV64ZVE32F-NEXT: andi a3, a2, 112635; RV64ZVE32F-NEXT: beqz a3, .LBB104_212636; RV64ZVE32F-NEXT: # %bb.1: # %cond.load12637; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma12638; RV64ZVE32F-NEXT: vmv.x.s a3, v812639; RV64ZVE32F-NEXT: slli a3, a3, 312640; RV64ZVE32F-NEXT: add a3, a1, a312641; RV64ZVE32F-NEXT: fld fa0, 0(a3)12642; RV64ZVE32F-NEXT: .LBB104_2: # %else12643; RV64ZVE32F-NEXT: andi a3, a2, 212644; RV64ZVE32F-NEXT: beqz a3, .LBB104_412645; RV64ZVE32F-NEXT: # %bb.3: # %cond.load112646; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma12647; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 112648; RV64ZVE32F-NEXT: vmv.x.s a3, v1012649; RV64ZVE32F-NEXT: slli a3, a3, 312650; RV64ZVE32F-NEXT: add a3, a1, a312651; RV64ZVE32F-NEXT: fld fa1, 0(a3)12652; RV64ZVE32F-NEXT: .LBB104_4: # %else212653; RV64ZVE32F-NEXT: andi a3, a2, 412654; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma12655; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 212656; RV64ZVE32F-NEXT: beqz a3, .LBB104_612657; RV64ZVE32F-NEXT: # %bb.5: # %cond.load412658; RV64ZVE32F-NEXT: vmv.x.s a3, v1012659; RV64ZVE32F-NEXT: slli a3, a3, 312660; RV64ZVE32F-NEXT: add a3, a1, a312661; RV64ZVE32F-NEXT: fld fa2, 0(a3)12662; RV64ZVE32F-NEXT: .LBB104_6: # %else512663; RV64ZVE32F-NEXT: andi a3, a2, 812664; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, ta, ma12665; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 412666; RV64ZVE32F-NEXT: bnez a3, .LBB104_1512667; RV64ZVE32F-NEXT: # %bb.7: # %else812668; RV64ZVE32F-NEXT: andi a3, a2, 1612669; RV64ZVE32F-NEXT: bnez a3, .LBB104_1612670; RV64ZVE32F-NEXT: .LBB104_8: # %else1112671; RV64ZVE32F-NEXT: andi a3, a2, 3212672; RV64ZVE32F-NEXT: beqz a3, .LBB104_1012673; RV64ZVE32F-NEXT: .LBB104_9: # %cond.load1312674; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma12675; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 112676; RV64ZVE32F-NEXT: vmv.x.s a3, v912677; RV64ZVE32F-NEXT: slli a3, a3, 312678; RV64ZVE32F-NEXT: add a3, a1, a312679; RV64ZVE32F-NEXT: fld fa5, 0(a3)12680; RV64ZVE32F-NEXT: .LBB104_10: # %else1412681; RV64ZVE32F-NEXT: andi a3, a2, 6412682; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma12683; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 212684; RV64ZVE32F-NEXT: beqz a3, .LBB104_1212685; RV64ZVE32F-NEXT: # %bb.11: # %cond.load1612686; RV64ZVE32F-NEXT: vmv.x.s a3, v812687; RV64ZVE32F-NEXT: slli a3, a3, 312688; RV64ZVE32F-NEXT: add a3, a1, a312689; RV64ZVE32F-NEXT: fld fa6, 0(a3)12690; RV64ZVE32F-NEXT: .LBB104_12: # %else1712691; RV64ZVE32F-NEXT: andi a2, a2, -12812692; RV64ZVE32F-NEXT: beqz a2, .LBB104_1412693; RV64ZVE32F-NEXT: # %bb.13: # %cond.load1912694; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 112695; RV64ZVE32F-NEXT: vmv.x.s a2, v812696; RV64ZVE32F-NEXT: slli a2, a2, 312697; RV64ZVE32F-NEXT: add a1, a1, a212698; RV64ZVE32F-NEXT: fld fa7, 0(a1)12699; RV64ZVE32F-NEXT: .LBB104_14: # %else2012700; RV64ZVE32F-NEXT: fsd fa0, 0(a0)12701; RV64ZVE32F-NEXT: fsd fa1, 8(a0)12702; RV64ZVE32F-NEXT: fsd fa2, 16(a0)12703; RV64ZVE32F-NEXT: fsd fa3, 24(a0)12704; RV64ZVE32F-NEXT: fsd fa4, 32(a0)12705; RV64ZVE32F-NEXT: fsd fa5, 40(a0)12706; RV64ZVE32F-NEXT: fsd fa6, 48(a0)12707; RV64ZVE32F-NEXT: fsd fa7, 56(a0)12708; RV64ZVE32F-NEXT: ret12709; RV64ZVE32F-NEXT: .LBB104_15: # %cond.load712710; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma12711; RV64ZVE32F-NEXT: vslidedown.vi v9, v10, 112712; RV64ZVE32F-NEXT: vmv.x.s a3, v912713; RV64ZVE32F-NEXT: slli a3, a3, 312714; RV64ZVE32F-NEXT: add a3, a1, a312715; RV64ZVE32F-NEXT: fld fa3, 0(a3)12716; RV64ZVE32F-NEXT: andi a3, a2, 1612717; RV64ZVE32F-NEXT: beqz a3, .LBB104_812718; RV64ZVE32F-NEXT: .LBB104_16: # %cond.load1012719; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma12720; RV64ZVE32F-NEXT: vmv.x.s a3, v812721; RV64ZVE32F-NEXT: slli a3, a3, 312722; RV64ZVE32F-NEXT: add a3, a1, a312723; RV64ZVE32F-NEXT: fld fa4, 0(a3)12724; RV64ZVE32F-NEXT: andi a3, a2, 3212725; RV64ZVE32F-NEXT: bnez a3, .LBB104_912726; RV64ZVE32F-NEXT: j .LBB104_1012727 %eidxs = sext <8 x i32> %idxs to <8 x i64>12728 %ptrs = getelementptr inbounds double, ptr %base, <8 x i64> %eidxs12729 %v = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> %ptrs, i32 8, <8 x i1> %m, <8 x double> %passthru)12730 ret <8 x double> %v12731}12732 12733define <8 x double> @mgather_baseidx_zext_v8i32_v8f64(ptr %base, <8 x i32> %idxs, <8 x i1> %m, <8 x double> %passthru) {12734; RV32V-LABEL: mgather_baseidx_zext_v8i32_v8f64:12735; RV32V: # %bb.0:12736; RV32V-NEXT: vsetivli zero, 8, e32, m2, ta, ma12737; RV32V-NEXT: vsll.vi v8, v8, 312738; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, mu12739; RV32V-NEXT: vluxei32.v v12, (a0), v8, v0.t12740; RV32V-NEXT: vmv.v.v v8, v1212741; RV32V-NEXT: ret12742;12743; RV64V-LABEL: mgather_baseidx_zext_v8i32_v8f64:12744; RV64V: # %bb.0:12745; RV64V-NEXT: li a1, 812746; RV64V-NEXT: vsetivli zero, 8, e32, m2, ta, ma12747; RV64V-NEXT: vwmulu.vx v16, v8, a112748; RV64V-NEXT: vsetvli zero, zero, e64, m4, ta, mu12749; RV64V-NEXT: vluxei64.v v12, (a0), v16, v0.t12750; RV64V-NEXT: vmv.v.v v8, v1212751; RV64V-NEXT: ret12752;12753; RV32ZVE32F-LABEL: mgather_baseidx_zext_v8i32_v8f64:12754; RV32ZVE32F: # %bb.0:12755; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma12756; RV32ZVE32F-NEXT: vsll.vi v8, v8, 312757; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma12758; RV32ZVE32F-NEXT: vmv.x.s a2, v012759; RV32ZVE32F-NEXT: andi a3, a2, 112760; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma12761; RV32ZVE32F-NEXT: vadd.vx v8, v8, a112762; RV32ZVE32F-NEXT: bnez a3, .LBB105_1012763; RV32ZVE32F-NEXT: # %bb.1: # %else12764; RV32ZVE32F-NEXT: andi a1, a2, 212765; RV32ZVE32F-NEXT: bnez a1, .LBB105_1112766; RV32ZVE32F-NEXT: .LBB105_2: # %else212767; RV32ZVE32F-NEXT: andi a1, a2, 412768; RV32ZVE32F-NEXT: bnez a1, .LBB105_1212769; RV32ZVE32F-NEXT: .LBB105_3: # %else512770; RV32ZVE32F-NEXT: andi a1, a2, 812771; RV32ZVE32F-NEXT: bnez a1, .LBB105_1312772; RV32ZVE32F-NEXT: .LBB105_4: # %else812773; RV32ZVE32F-NEXT: andi a1, a2, 1612774; RV32ZVE32F-NEXT: bnez a1, .LBB105_1412775; RV32ZVE32F-NEXT: .LBB105_5: # %else1112776; RV32ZVE32F-NEXT: andi a1, a2, 3212777; RV32ZVE32F-NEXT: bnez a1, .LBB105_1512778; RV32ZVE32F-NEXT: .LBB105_6: # %else1412779; RV32ZVE32F-NEXT: andi a1, a2, 6412780; RV32ZVE32F-NEXT: bnez a1, .LBB105_1612781; RV32ZVE32F-NEXT: .LBB105_7: # %else1712782; RV32ZVE32F-NEXT: andi a1, a2, -12812783; RV32ZVE32F-NEXT: beqz a1, .LBB105_912784; RV32ZVE32F-NEXT: .LBB105_8: # %cond.load1912785; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma12786; RV32ZVE32F-NEXT: vslidedown.vi v8, v8, 712787; RV32ZVE32F-NEXT: vmv.x.s a1, v812788; RV32ZVE32F-NEXT: fld fa7, 0(a1)12789; RV32ZVE32F-NEXT: .LBB105_9: # %else2012790; RV32ZVE32F-NEXT: fsd fa0, 0(a0)12791; RV32ZVE32F-NEXT: fsd fa1, 8(a0)12792; RV32ZVE32F-NEXT: fsd fa2, 16(a0)12793; RV32ZVE32F-NEXT: fsd fa3, 24(a0)12794; RV32ZVE32F-NEXT: fsd fa4, 32(a0)12795; RV32ZVE32F-NEXT: fsd fa5, 40(a0)12796; RV32ZVE32F-NEXT: fsd fa6, 48(a0)12797; RV32ZVE32F-NEXT: fsd fa7, 56(a0)12798; RV32ZVE32F-NEXT: ret12799; RV32ZVE32F-NEXT: .LBB105_10: # %cond.load12800; RV32ZVE32F-NEXT: vmv.x.s a1, v812801; RV32ZVE32F-NEXT: fld fa0, 0(a1)12802; RV32ZVE32F-NEXT: andi a1, a2, 212803; RV32ZVE32F-NEXT: beqz a1, .LBB105_212804; RV32ZVE32F-NEXT: .LBB105_11: # %cond.load112805; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma12806; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 112807; RV32ZVE32F-NEXT: vmv.x.s a1, v1012808; RV32ZVE32F-NEXT: fld fa1, 0(a1)12809; RV32ZVE32F-NEXT: andi a1, a2, 412810; RV32ZVE32F-NEXT: beqz a1, .LBB105_312811; RV32ZVE32F-NEXT: .LBB105_12: # %cond.load412812; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma12813; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 212814; RV32ZVE32F-NEXT: vmv.x.s a1, v1012815; RV32ZVE32F-NEXT: fld fa2, 0(a1)12816; RV32ZVE32F-NEXT: andi a1, a2, 812817; RV32ZVE32F-NEXT: beqz a1, .LBB105_412818; RV32ZVE32F-NEXT: .LBB105_13: # %cond.load712819; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma12820; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 312821; RV32ZVE32F-NEXT: vmv.x.s a1, v1012822; RV32ZVE32F-NEXT: fld fa3, 0(a1)12823; RV32ZVE32F-NEXT: andi a1, a2, 1612824; RV32ZVE32F-NEXT: beqz a1, .LBB105_512825; RV32ZVE32F-NEXT: .LBB105_14: # %cond.load1012826; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma12827; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 412828; RV32ZVE32F-NEXT: vmv.x.s a1, v1012829; RV32ZVE32F-NEXT: fld fa4, 0(a1)12830; RV32ZVE32F-NEXT: andi a1, a2, 3212831; RV32ZVE32F-NEXT: beqz a1, .LBB105_612832; RV32ZVE32F-NEXT: .LBB105_15: # %cond.load1312833; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma12834; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 512835; RV32ZVE32F-NEXT: vmv.x.s a1, v1012836; RV32ZVE32F-NEXT: fld fa5, 0(a1)12837; RV32ZVE32F-NEXT: andi a1, a2, 6412838; RV32ZVE32F-NEXT: beqz a1, .LBB105_712839; RV32ZVE32F-NEXT: .LBB105_16: # %cond.load1612840; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma12841; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 612842; RV32ZVE32F-NEXT: vmv.x.s a1, v1012843; RV32ZVE32F-NEXT: fld fa6, 0(a1)12844; RV32ZVE32F-NEXT: andi a1, a2, -12812845; RV32ZVE32F-NEXT: bnez a1, .LBB105_812846; RV32ZVE32F-NEXT: j .LBB105_912847;12848; RV64ZVE32F-LABEL: mgather_baseidx_zext_v8i32_v8f64:12849; RV64ZVE32F: # %bb.0:12850; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma12851; RV64ZVE32F-NEXT: vmv.x.s a2, v012852; RV64ZVE32F-NEXT: andi a3, a2, 112853; RV64ZVE32F-NEXT: beqz a3, .LBB105_212854; RV64ZVE32F-NEXT: # %bb.1: # %cond.load12855; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma12856; RV64ZVE32F-NEXT: vmv.x.s a3, v812857; RV64ZVE32F-NEXT: slli a3, a3, 3212858; RV64ZVE32F-NEXT: srli a3, a3, 2912859; RV64ZVE32F-NEXT: add a3, a1, a312860; RV64ZVE32F-NEXT: fld fa0, 0(a3)12861; RV64ZVE32F-NEXT: .LBB105_2: # %else12862; RV64ZVE32F-NEXT: andi a3, a2, 212863; RV64ZVE32F-NEXT: beqz a3, .LBB105_412864; RV64ZVE32F-NEXT: # %bb.3: # %cond.load112865; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma12866; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 112867; RV64ZVE32F-NEXT: vmv.x.s a3, v1012868; RV64ZVE32F-NEXT: slli a3, a3, 3212869; RV64ZVE32F-NEXT: srli a3, a3, 2912870; RV64ZVE32F-NEXT: add a3, a1, a312871; RV64ZVE32F-NEXT: fld fa1, 0(a3)12872; RV64ZVE32F-NEXT: .LBB105_4: # %else212873; RV64ZVE32F-NEXT: andi a3, a2, 412874; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma12875; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 212876; RV64ZVE32F-NEXT: beqz a3, .LBB105_612877; RV64ZVE32F-NEXT: # %bb.5: # %cond.load412878; RV64ZVE32F-NEXT: vmv.x.s a3, v1012879; RV64ZVE32F-NEXT: slli a3, a3, 3212880; RV64ZVE32F-NEXT: srli a3, a3, 2912881; RV64ZVE32F-NEXT: add a3, a1, a312882; RV64ZVE32F-NEXT: fld fa2, 0(a3)12883; RV64ZVE32F-NEXT: .LBB105_6: # %else512884; RV64ZVE32F-NEXT: andi a3, a2, 812885; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, ta, ma12886; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 412887; RV64ZVE32F-NEXT: bnez a3, .LBB105_1512888; RV64ZVE32F-NEXT: # %bb.7: # %else812889; RV64ZVE32F-NEXT: andi a3, a2, 1612890; RV64ZVE32F-NEXT: bnez a3, .LBB105_1612891; RV64ZVE32F-NEXT: .LBB105_8: # %else1112892; RV64ZVE32F-NEXT: andi a3, a2, 3212893; RV64ZVE32F-NEXT: beqz a3, .LBB105_1012894; RV64ZVE32F-NEXT: .LBB105_9: # %cond.load1312895; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma12896; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 112897; RV64ZVE32F-NEXT: vmv.x.s a3, v912898; RV64ZVE32F-NEXT: slli a3, a3, 3212899; RV64ZVE32F-NEXT: srli a3, a3, 2912900; RV64ZVE32F-NEXT: add a3, a1, a312901; RV64ZVE32F-NEXT: fld fa5, 0(a3)12902; RV64ZVE32F-NEXT: .LBB105_10: # %else1412903; RV64ZVE32F-NEXT: andi a3, a2, 6412904; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma12905; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 212906; RV64ZVE32F-NEXT: beqz a3, .LBB105_1212907; RV64ZVE32F-NEXT: # %bb.11: # %cond.load1612908; RV64ZVE32F-NEXT: vmv.x.s a3, v812909; RV64ZVE32F-NEXT: slli a3, a3, 3212910; RV64ZVE32F-NEXT: srli a3, a3, 2912911; RV64ZVE32F-NEXT: add a3, a1, a312912; RV64ZVE32F-NEXT: fld fa6, 0(a3)12913; RV64ZVE32F-NEXT: .LBB105_12: # %else1712914; RV64ZVE32F-NEXT: andi a2, a2, -12812915; RV64ZVE32F-NEXT: beqz a2, .LBB105_1412916; RV64ZVE32F-NEXT: # %bb.13: # %cond.load1912917; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 112918; RV64ZVE32F-NEXT: vmv.x.s a2, v812919; RV64ZVE32F-NEXT: slli a2, a2, 3212920; RV64ZVE32F-NEXT: srli a2, a2, 2912921; RV64ZVE32F-NEXT: add a1, a1, a212922; RV64ZVE32F-NEXT: fld fa7, 0(a1)12923; RV64ZVE32F-NEXT: .LBB105_14: # %else2012924; RV64ZVE32F-NEXT: fsd fa0, 0(a0)12925; RV64ZVE32F-NEXT: fsd fa1, 8(a0)12926; RV64ZVE32F-NEXT: fsd fa2, 16(a0)12927; RV64ZVE32F-NEXT: fsd fa3, 24(a0)12928; RV64ZVE32F-NEXT: fsd fa4, 32(a0)12929; RV64ZVE32F-NEXT: fsd fa5, 40(a0)12930; RV64ZVE32F-NEXT: fsd fa6, 48(a0)12931; RV64ZVE32F-NEXT: fsd fa7, 56(a0)12932; RV64ZVE32F-NEXT: ret12933; RV64ZVE32F-NEXT: .LBB105_15: # %cond.load712934; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma12935; RV64ZVE32F-NEXT: vslidedown.vi v9, v10, 112936; RV64ZVE32F-NEXT: vmv.x.s a3, v912937; RV64ZVE32F-NEXT: slli a3, a3, 3212938; RV64ZVE32F-NEXT: srli a3, a3, 2912939; RV64ZVE32F-NEXT: add a3, a1, a312940; RV64ZVE32F-NEXT: fld fa3, 0(a3)12941; RV64ZVE32F-NEXT: andi a3, a2, 1612942; RV64ZVE32F-NEXT: beqz a3, .LBB105_812943; RV64ZVE32F-NEXT: .LBB105_16: # %cond.load1012944; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma12945; RV64ZVE32F-NEXT: vmv.x.s a3, v812946; RV64ZVE32F-NEXT: slli a3, a3, 3212947; RV64ZVE32F-NEXT: srli a3, a3, 2912948; RV64ZVE32F-NEXT: add a3, a1, a312949; RV64ZVE32F-NEXT: fld fa4, 0(a3)12950; RV64ZVE32F-NEXT: andi a3, a2, 3212951; RV64ZVE32F-NEXT: bnez a3, .LBB105_912952; RV64ZVE32F-NEXT: j .LBB105_1012953 %eidxs = zext <8 x i32> %idxs to <8 x i64>12954 %ptrs = getelementptr inbounds double, ptr %base, <8 x i64> %eidxs12955 %v = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> %ptrs, i32 8, <8 x i1> %m, <8 x double> %passthru)12956 ret <8 x double> %v12957}12958 12959define <8 x double> @mgather_baseidx_v8f64(ptr %base, <8 x i64> %idxs, <8 x i1> %m, <8 x double> %passthru) {12960; RV32V-LABEL: mgather_baseidx_v8f64:12961; RV32V: # %bb.0:12962; RV32V-NEXT: vsetivli zero, 8, e32, m2, ta, ma12963; RV32V-NEXT: vnsrl.wi v16, v8, 012964; RV32V-NEXT: vsll.vi v8, v16, 312965; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, mu12966; RV32V-NEXT: vluxei32.v v12, (a0), v8, v0.t12967; RV32V-NEXT: vmv.v.v v8, v1212968; RV32V-NEXT: ret12969;12970; RV64V-LABEL: mgather_baseidx_v8f64:12971; RV64V: # %bb.0:12972; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, mu12973; RV64V-NEXT: vsll.vi v8, v8, 312974; RV64V-NEXT: vluxei64.v v12, (a0), v8, v0.t12975; RV64V-NEXT: vmv.v.v v8, v1212976; RV64V-NEXT: ret12977;12978; RV32ZVE32F-LABEL: mgather_baseidx_v8f64:12979; RV32ZVE32F: # %bb.0:12980; RV32ZVE32F-NEXT: lw a3, 32(a2)12981; RV32ZVE32F-NEXT: lw a4, 40(a2)12982; RV32ZVE32F-NEXT: lw a5, 48(a2)12983; RV32ZVE32F-NEXT: lw a6, 56(a2)12984; RV32ZVE32F-NEXT: lw a7, 0(a2)12985; RV32ZVE32F-NEXT: lw t0, 8(a2)12986; RV32ZVE32F-NEXT: lw t1, 16(a2)12987; RV32ZVE32F-NEXT: lw t2, 24(a2)12988; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma12989; RV32ZVE32F-NEXT: vmv.v.x v8, a712990; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma12991; RV32ZVE32F-NEXT: vmv.x.s a2, v012992; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma12993; RV32ZVE32F-NEXT: vslide1down.vx v8, v8, t012994; RV32ZVE32F-NEXT: vslide1down.vx v8, v8, t112995; RV32ZVE32F-NEXT: vslide1down.vx v8, v8, t212996; RV32ZVE32F-NEXT: vslide1down.vx v8, v8, a312997; RV32ZVE32F-NEXT: vslide1down.vx v8, v8, a412998; RV32ZVE32F-NEXT: vslide1down.vx v8, v8, a512999; RV32ZVE32F-NEXT: vslide1down.vx v8, v8, a613000; RV32ZVE32F-NEXT: vsll.vi v8, v8, 313001; RV32ZVE32F-NEXT: andi a3, a2, 113002; RV32ZVE32F-NEXT: vadd.vx v8, v8, a113003; RV32ZVE32F-NEXT: bnez a3, .LBB106_1013004; RV32ZVE32F-NEXT: # %bb.1: # %else13005; RV32ZVE32F-NEXT: andi a1, a2, 213006; RV32ZVE32F-NEXT: bnez a1, .LBB106_1113007; RV32ZVE32F-NEXT: .LBB106_2: # %else213008; RV32ZVE32F-NEXT: andi a1, a2, 413009; RV32ZVE32F-NEXT: bnez a1, .LBB106_1213010; RV32ZVE32F-NEXT: .LBB106_3: # %else513011; RV32ZVE32F-NEXT: andi a1, a2, 813012; RV32ZVE32F-NEXT: bnez a1, .LBB106_1313013; RV32ZVE32F-NEXT: .LBB106_4: # %else813014; RV32ZVE32F-NEXT: andi a1, a2, 1613015; RV32ZVE32F-NEXT: bnez a1, .LBB106_1413016; RV32ZVE32F-NEXT: .LBB106_5: # %else1113017; RV32ZVE32F-NEXT: andi a1, a2, 3213018; RV32ZVE32F-NEXT: bnez a1, .LBB106_1513019; RV32ZVE32F-NEXT: .LBB106_6: # %else1413020; RV32ZVE32F-NEXT: andi a1, a2, 6413021; RV32ZVE32F-NEXT: bnez a1, .LBB106_1613022; RV32ZVE32F-NEXT: .LBB106_7: # %else1713023; RV32ZVE32F-NEXT: andi a1, a2, -12813024; RV32ZVE32F-NEXT: beqz a1, .LBB106_913025; RV32ZVE32F-NEXT: .LBB106_8: # %cond.load1913026; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma13027; RV32ZVE32F-NEXT: vslidedown.vi v8, v8, 713028; RV32ZVE32F-NEXT: vmv.x.s a1, v813029; RV32ZVE32F-NEXT: fld fa7, 0(a1)13030; RV32ZVE32F-NEXT: .LBB106_9: # %else2013031; RV32ZVE32F-NEXT: fsd fa0, 0(a0)13032; RV32ZVE32F-NEXT: fsd fa1, 8(a0)13033; RV32ZVE32F-NEXT: fsd fa2, 16(a0)13034; RV32ZVE32F-NEXT: fsd fa3, 24(a0)13035; RV32ZVE32F-NEXT: fsd fa4, 32(a0)13036; RV32ZVE32F-NEXT: fsd fa5, 40(a0)13037; RV32ZVE32F-NEXT: fsd fa6, 48(a0)13038; RV32ZVE32F-NEXT: fsd fa7, 56(a0)13039; RV32ZVE32F-NEXT: ret13040; RV32ZVE32F-NEXT: .LBB106_10: # %cond.load13041; RV32ZVE32F-NEXT: vmv.x.s a1, v813042; RV32ZVE32F-NEXT: fld fa0, 0(a1)13043; RV32ZVE32F-NEXT: andi a1, a2, 213044; RV32ZVE32F-NEXT: beqz a1, .LBB106_213045; RV32ZVE32F-NEXT: .LBB106_11: # %cond.load113046; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma13047; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 113048; RV32ZVE32F-NEXT: vmv.x.s a1, v1013049; RV32ZVE32F-NEXT: fld fa1, 0(a1)13050; RV32ZVE32F-NEXT: andi a1, a2, 413051; RV32ZVE32F-NEXT: beqz a1, .LBB106_313052; RV32ZVE32F-NEXT: .LBB106_12: # %cond.load413053; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma13054; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 213055; RV32ZVE32F-NEXT: vmv.x.s a1, v1013056; RV32ZVE32F-NEXT: fld fa2, 0(a1)13057; RV32ZVE32F-NEXT: andi a1, a2, 813058; RV32ZVE32F-NEXT: beqz a1, .LBB106_413059; RV32ZVE32F-NEXT: .LBB106_13: # %cond.load713060; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma13061; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 313062; RV32ZVE32F-NEXT: vmv.x.s a1, v1013063; RV32ZVE32F-NEXT: fld fa3, 0(a1)13064; RV32ZVE32F-NEXT: andi a1, a2, 1613065; RV32ZVE32F-NEXT: beqz a1, .LBB106_513066; RV32ZVE32F-NEXT: .LBB106_14: # %cond.load1013067; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma13068; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 413069; RV32ZVE32F-NEXT: vmv.x.s a1, v1013070; RV32ZVE32F-NEXT: fld fa4, 0(a1)13071; RV32ZVE32F-NEXT: andi a1, a2, 3213072; RV32ZVE32F-NEXT: beqz a1, .LBB106_613073; RV32ZVE32F-NEXT: .LBB106_15: # %cond.load1313074; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma13075; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 513076; RV32ZVE32F-NEXT: vmv.x.s a1, v1013077; RV32ZVE32F-NEXT: fld fa5, 0(a1)13078; RV32ZVE32F-NEXT: andi a1, a2, 6413079; RV32ZVE32F-NEXT: beqz a1, .LBB106_713080; RV32ZVE32F-NEXT: .LBB106_16: # %cond.load1613081; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma13082; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 613083; RV32ZVE32F-NEXT: vmv.x.s a1, v1013084; RV32ZVE32F-NEXT: fld fa6, 0(a1)13085; RV32ZVE32F-NEXT: andi a1, a2, -12813086; RV32ZVE32F-NEXT: bnez a1, .LBB106_813087; RV32ZVE32F-NEXT: j .LBB106_913088;13089; RV64ZVE32F-LABEL: mgather_baseidx_v8f64:13090; RV64ZVE32F: # %bb.0:13091; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma13092; RV64ZVE32F-NEXT: vmv.x.s a3, v013093; RV64ZVE32F-NEXT: andi a4, a3, 113094; RV64ZVE32F-NEXT: bnez a4, .LBB106_1013095; RV64ZVE32F-NEXT: # %bb.1: # %else13096; RV64ZVE32F-NEXT: andi a4, a3, 213097; RV64ZVE32F-NEXT: bnez a4, .LBB106_1113098; RV64ZVE32F-NEXT: .LBB106_2: # %else213099; RV64ZVE32F-NEXT: andi a4, a3, 413100; RV64ZVE32F-NEXT: bnez a4, .LBB106_1213101; RV64ZVE32F-NEXT: .LBB106_3: # %else513102; RV64ZVE32F-NEXT: andi a4, a3, 813103; RV64ZVE32F-NEXT: bnez a4, .LBB106_1313104; RV64ZVE32F-NEXT: .LBB106_4: # %else813105; RV64ZVE32F-NEXT: andi a4, a3, 1613106; RV64ZVE32F-NEXT: bnez a4, .LBB106_1413107; RV64ZVE32F-NEXT: .LBB106_5: # %else1113108; RV64ZVE32F-NEXT: andi a4, a3, 3213109; RV64ZVE32F-NEXT: bnez a4, .LBB106_1513110; RV64ZVE32F-NEXT: .LBB106_6: # %else1413111; RV64ZVE32F-NEXT: andi a4, a3, 6413112; RV64ZVE32F-NEXT: bnez a4, .LBB106_1613113; RV64ZVE32F-NEXT: .LBB106_7: # %else1713114; RV64ZVE32F-NEXT: andi a3, a3, -12813115; RV64ZVE32F-NEXT: beqz a3, .LBB106_913116; RV64ZVE32F-NEXT: .LBB106_8: # %cond.load1913117; RV64ZVE32F-NEXT: ld a2, 56(a2)13118; RV64ZVE32F-NEXT: slli a2, a2, 313119; RV64ZVE32F-NEXT: add a1, a1, a213120; RV64ZVE32F-NEXT: fld fa7, 0(a1)13121; RV64ZVE32F-NEXT: .LBB106_9: # %else2013122; RV64ZVE32F-NEXT: fsd fa0, 0(a0)13123; RV64ZVE32F-NEXT: fsd fa1, 8(a0)13124; RV64ZVE32F-NEXT: fsd fa2, 16(a0)13125; RV64ZVE32F-NEXT: fsd fa3, 24(a0)13126; RV64ZVE32F-NEXT: fsd fa4, 32(a0)13127; RV64ZVE32F-NEXT: fsd fa5, 40(a0)13128; RV64ZVE32F-NEXT: fsd fa6, 48(a0)13129; RV64ZVE32F-NEXT: fsd fa7, 56(a0)13130; RV64ZVE32F-NEXT: ret13131; RV64ZVE32F-NEXT: .LBB106_10: # %cond.load13132; RV64ZVE32F-NEXT: ld a4, 0(a2)13133; RV64ZVE32F-NEXT: slli a4, a4, 313134; RV64ZVE32F-NEXT: add a4, a1, a413135; RV64ZVE32F-NEXT: fld fa0, 0(a4)13136; RV64ZVE32F-NEXT: andi a4, a3, 213137; RV64ZVE32F-NEXT: beqz a4, .LBB106_213138; RV64ZVE32F-NEXT: .LBB106_11: # %cond.load113139; RV64ZVE32F-NEXT: ld a4, 8(a2)13140; RV64ZVE32F-NEXT: slli a4, a4, 313141; RV64ZVE32F-NEXT: add a4, a1, a413142; RV64ZVE32F-NEXT: fld fa1, 0(a4)13143; RV64ZVE32F-NEXT: andi a4, a3, 413144; RV64ZVE32F-NEXT: beqz a4, .LBB106_313145; RV64ZVE32F-NEXT: .LBB106_12: # %cond.load413146; RV64ZVE32F-NEXT: ld a4, 16(a2)13147; RV64ZVE32F-NEXT: slli a4, a4, 313148; RV64ZVE32F-NEXT: add a4, a1, a413149; RV64ZVE32F-NEXT: fld fa2, 0(a4)13150; RV64ZVE32F-NEXT: andi a4, a3, 813151; RV64ZVE32F-NEXT: beqz a4, .LBB106_413152; RV64ZVE32F-NEXT: .LBB106_13: # %cond.load713153; RV64ZVE32F-NEXT: ld a4, 24(a2)13154; RV64ZVE32F-NEXT: slli a4, a4, 313155; RV64ZVE32F-NEXT: add a4, a1, a413156; RV64ZVE32F-NEXT: fld fa3, 0(a4)13157; RV64ZVE32F-NEXT: andi a4, a3, 1613158; RV64ZVE32F-NEXT: beqz a4, .LBB106_513159; RV64ZVE32F-NEXT: .LBB106_14: # %cond.load1013160; RV64ZVE32F-NEXT: ld a4, 32(a2)13161; RV64ZVE32F-NEXT: slli a4, a4, 313162; RV64ZVE32F-NEXT: add a4, a1, a413163; RV64ZVE32F-NEXT: fld fa4, 0(a4)13164; RV64ZVE32F-NEXT: andi a4, a3, 3213165; RV64ZVE32F-NEXT: beqz a4, .LBB106_613166; RV64ZVE32F-NEXT: .LBB106_15: # %cond.load1313167; RV64ZVE32F-NEXT: ld a4, 40(a2)13168; RV64ZVE32F-NEXT: slli a4, a4, 313169; RV64ZVE32F-NEXT: add a4, a1, a413170; RV64ZVE32F-NEXT: fld fa5, 0(a4)13171; RV64ZVE32F-NEXT: andi a4, a3, 6413172; RV64ZVE32F-NEXT: beqz a4, .LBB106_713173; RV64ZVE32F-NEXT: .LBB106_16: # %cond.load1613174; RV64ZVE32F-NEXT: ld a4, 48(a2)13175; RV64ZVE32F-NEXT: slli a4, a4, 313176; RV64ZVE32F-NEXT: add a4, a1, a413177; RV64ZVE32F-NEXT: fld fa6, 0(a4)13178; RV64ZVE32F-NEXT: andi a3, a3, -12813179; RV64ZVE32F-NEXT: bnez a3, .LBB106_813180; RV64ZVE32F-NEXT: j .LBB106_913181 %ptrs = getelementptr inbounds double, ptr %base, <8 x i64> %idxs13182 %v = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> %ptrs, i32 8, <8 x i1> %m, <8 x double> %passthru)13183 ret <8 x double> %v13184}13185 13186define <16 x i8> @mgather_baseidx_v16i8(ptr %base, <16 x i8> %idxs, <16 x i1> %m, <16 x i8> %passthru) {13187; RV32-LABEL: mgather_baseidx_v16i8:13188; RV32: # %bb.0:13189; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma13190; RV32-NEXT: vsext.vf4 v12, v813191; RV32-NEXT: vsetvli zero, zero, e8, m1, ta, mu13192; RV32-NEXT: vluxei32.v v9, (a0), v12, v0.t13193; RV32-NEXT: vmv.v.v v8, v913194; RV32-NEXT: ret13195;13196; RV64V-LABEL: mgather_baseidx_v16i8:13197; RV64V: # %bb.0:13198; RV64V-NEXT: vsetivli zero, 16, e64, m8, ta, ma13199; RV64V-NEXT: vsext.vf8 v16, v813200; RV64V-NEXT: vsetvli zero, zero, e8, m1, ta, mu13201; RV64V-NEXT: vluxei64.v v9, (a0), v16, v0.t13202; RV64V-NEXT: vmv.v.v v8, v913203; RV64V-NEXT: ret13204;13205; RV64ZVE32F-LABEL: mgather_baseidx_v16i8:13206; RV64ZVE32F: # %bb.0:13207; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma13208; RV64ZVE32F-NEXT: vmv.x.s a1, v013209; RV64ZVE32F-NEXT: andi a2, a1, 113210; RV64ZVE32F-NEXT: beqz a2, .LBB107_213211; RV64ZVE32F-NEXT: # %bb.1: # %cond.load13212; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, tu, ma13213; RV64ZVE32F-NEXT: vmv.x.s a2, v813214; RV64ZVE32F-NEXT: add a2, a0, a213215; RV64ZVE32F-NEXT: lbu a2, 0(a2)13216; RV64ZVE32F-NEXT: vmv.s.x v9, a213217; RV64ZVE32F-NEXT: .LBB107_2: # %else13218; RV64ZVE32F-NEXT: andi a2, a1, 213219; RV64ZVE32F-NEXT: beqz a2, .LBB107_413220; RV64ZVE32F-NEXT: # %bb.3: # %cond.load113221; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma13222; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 113223; RV64ZVE32F-NEXT: vmv.x.s a2, v1013224; RV64ZVE32F-NEXT: add a2, a0, a213225; RV64ZVE32F-NEXT: lbu a2, 0(a2)13226; RV64ZVE32F-NEXT: vmv.s.x v10, a213227; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, m1, tu, ma13228; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 113229; RV64ZVE32F-NEXT: .LBB107_4: # %else213230; RV64ZVE32F-NEXT: andi a2, a1, 413231; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma13232; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 213233; RV64ZVE32F-NEXT: beqz a2, .LBB107_613234; RV64ZVE32F-NEXT: # %bb.5: # %cond.load413235; RV64ZVE32F-NEXT: vmv.x.s a2, v1013236; RV64ZVE32F-NEXT: add a2, a0, a213237; RV64ZVE32F-NEXT: lbu a2, 0(a2)13238; RV64ZVE32F-NEXT: vmv.s.x v11, a213239; RV64ZVE32F-NEXT: vsetivli zero, 3, e8, m1, tu, ma13240; RV64ZVE32F-NEXT: vslideup.vi v9, v11, 213241; RV64ZVE32F-NEXT: .LBB107_6: # %else513242; RV64ZVE32F-NEXT: andi a2, a1, 813243; RV64ZVE32F-NEXT: beqz a2, .LBB107_813244; RV64ZVE32F-NEXT: # %bb.7: # %cond.load713245; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma13246; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 113247; RV64ZVE32F-NEXT: vmv.x.s a2, v1013248; RV64ZVE32F-NEXT: add a2, a0, a213249; RV64ZVE32F-NEXT: lbu a2, 0(a2)13250; RV64ZVE32F-NEXT: vmv.s.x v10, a213251; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, m1, tu, ma13252; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 313253; RV64ZVE32F-NEXT: .LBB107_8: # %else813254; RV64ZVE32F-NEXT: andi a2, a1, 1613255; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma13256; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 413257; RV64ZVE32F-NEXT: beqz a2, .LBB107_1013258; RV64ZVE32F-NEXT: # %bb.9: # %cond.load1013259; RV64ZVE32F-NEXT: vmv.x.s a2, v1013260; RV64ZVE32F-NEXT: add a2, a0, a213261; RV64ZVE32F-NEXT: lbu a2, 0(a2)13262; RV64ZVE32F-NEXT: vmv.s.x v11, a213263; RV64ZVE32F-NEXT: vsetivli zero, 5, e8, m1, tu, ma13264; RV64ZVE32F-NEXT: vslideup.vi v9, v11, 413265; RV64ZVE32F-NEXT: .LBB107_10: # %else1113266; RV64ZVE32F-NEXT: andi a2, a1, 3213267; RV64ZVE32F-NEXT: beqz a2, .LBB107_1213268; RV64ZVE32F-NEXT: # %bb.11: # %cond.load1313269; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma13270; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 113271; RV64ZVE32F-NEXT: vmv.x.s a2, v1113272; RV64ZVE32F-NEXT: add a2, a0, a213273; RV64ZVE32F-NEXT: lbu a2, 0(a2)13274; RV64ZVE32F-NEXT: vmv.s.x v11, a213275; RV64ZVE32F-NEXT: vsetivli zero, 6, e8, m1, tu, ma13276; RV64ZVE32F-NEXT: vslideup.vi v9, v11, 513277; RV64ZVE32F-NEXT: .LBB107_12: # %else1413278; RV64ZVE32F-NEXT: andi a2, a1, 6413279; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma13280; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 213281; RV64ZVE32F-NEXT: beqz a2, .LBB107_1413282; RV64ZVE32F-NEXT: # %bb.13: # %cond.load1613283; RV64ZVE32F-NEXT: vmv.x.s a2, v1013284; RV64ZVE32F-NEXT: add a2, a0, a213285; RV64ZVE32F-NEXT: lbu a2, 0(a2)13286; RV64ZVE32F-NEXT: vmv.s.x v11, a213287; RV64ZVE32F-NEXT: vsetivli zero, 7, e8, m1, tu, ma13288; RV64ZVE32F-NEXT: vslideup.vi v9, v11, 613289; RV64ZVE32F-NEXT: .LBB107_14: # %else1713290; RV64ZVE32F-NEXT: andi a2, a1, 12813291; RV64ZVE32F-NEXT: beqz a2, .LBB107_1613292; RV64ZVE32F-NEXT: # %bb.15: # %cond.load1913293; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma13294; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 113295; RV64ZVE32F-NEXT: vmv.x.s a2, v1013296; RV64ZVE32F-NEXT: add a2, a0, a213297; RV64ZVE32F-NEXT: lbu a2, 0(a2)13298; RV64ZVE32F-NEXT: vmv.s.x v10, a213299; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, m1, tu, ma13300; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 713301; RV64ZVE32F-NEXT: .LBB107_16: # %else2013302; RV64ZVE32F-NEXT: andi a2, a1, 25613303; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, m1, ta, ma13304; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 813305; RV64ZVE32F-NEXT: beqz a2, .LBB107_1813306; RV64ZVE32F-NEXT: # %bb.17: # %cond.load2213307; RV64ZVE32F-NEXT: vmv.x.s a2, v813308; RV64ZVE32F-NEXT: add a2, a0, a213309; RV64ZVE32F-NEXT: lbu a2, 0(a2)13310; RV64ZVE32F-NEXT: vmv.s.x v10, a213311; RV64ZVE32F-NEXT: vsetivli zero, 9, e8, m1, tu, ma13312; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 813313; RV64ZVE32F-NEXT: .LBB107_18: # %else2313314; RV64ZVE32F-NEXT: andi a2, a1, 51213315; RV64ZVE32F-NEXT: beqz a2, .LBB107_2013316; RV64ZVE32F-NEXT: # %bb.19: # %cond.load2513317; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma13318; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 113319; RV64ZVE32F-NEXT: vmv.x.s a2, v1013320; RV64ZVE32F-NEXT: add a2, a0, a213321; RV64ZVE32F-NEXT: lbu a2, 0(a2)13322; RV64ZVE32F-NEXT: vmv.s.x v10, a213323; RV64ZVE32F-NEXT: vsetivli zero, 10, e8, m1, tu, ma13324; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 913325; RV64ZVE32F-NEXT: .LBB107_20: # %else2613326; RV64ZVE32F-NEXT: andi a2, a1, 102413327; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma13328; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 213329; RV64ZVE32F-NEXT: beqz a2, .LBB107_2213330; RV64ZVE32F-NEXT: # %bb.21: # %cond.load2813331; RV64ZVE32F-NEXT: vmv.x.s a2, v1013332; RV64ZVE32F-NEXT: add a2, a0, a213333; RV64ZVE32F-NEXT: lbu a2, 0(a2)13334; RV64ZVE32F-NEXT: vmv.s.x v11, a213335; RV64ZVE32F-NEXT: vsetivli zero, 11, e8, m1, tu, ma13336; RV64ZVE32F-NEXT: vslideup.vi v9, v11, 1013337; RV64ZVE32F-NEXT: .LBB107_22: # %else2913338; RV64ZVE32F-NEXT: slli a2, a1, 5213339; RV64ZVE32F-NEXT: bgez a2, .LBB107_2413340; RV64ZVE32F-NEXT: # %bb.23: # %cond.load3113341; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma13342; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 113343; RV64ZVE32F-NEXT: vmv.x.s a2, v1013344; RV64ZVE32F-NEXT: add a2, a0, a213345; RV64ZVE32F-NEXT: lbu a2, 0(a2)13346; RV64ZVE32F-NEXT: vmv.s.x v10, a213347; RV64ZVE32F-NEXT: vsetivli zero, 12, e8, m1, tu, ma13348; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 1113349; RV64ZVE32F-NEXT: .LBB107_24: # %else3213350; RV64ZVE32F-NEXT: slli a2, a1, 5113351; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma13352; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 413353; RV64ZVE32F-NEXT: bgez a2, .LBB107_2613354; RV64ZVE32F-NEXT: # %bb.25: # %cond.load3413355; RV64ZVE32F-NEXT: vmv.x.s a2, v813356; RV64ZVE32F-NEXT: add a2, a0, a213357; RV64ZVE32F-NEXT: lbu a2, 0(a2)13358; RV64ZVE32F-NEXT: vmv.s.x v10, a213359; RV64ZVE32F-NEXT: vsetivli zero, 13, e8, m1, tu, ma13360; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 1213361; RV64ZVE32F-NEXT: .LBB107_26: # %else3513362; RV64ZVE32F-NEXT: slli a2, a1, 5013363; RV64ZVE32F-NEXT: bgez a2, .LBB107_2813364; RV64ZVE32F-NEXT: # %bb.27: # %cond.load3713365; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma13366; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 113367; RV64ZVE32F-NEXT: vmv.x.s a2, v1013368; RV64ZVE32F-NEXT: add a2, a0, a213369; RV64ZVE32F-NEXT: lbu a2, 0(a2)13370; RV64ZVE32F-NEXT: vmv.s.x v10, a213371; RV64ZVE32F-NEXT: vsetivli zero, 14, e8, m1, tu, ma13372; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 1313373; RV64ZVE32F-NEXT: .LBB107_28: # %else3813374; RV64ZVE32F-NEXT: slli a2, a1, 4913375; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma13376; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 213377; RV64ZVE32F-NEXT: bgez a2, .LBB107_3013378; RV64ZVE32F-NEXT: # %bb.29: # %cond.load4013379; RV64ZVE32F-NEXT: vmv.x.s a2, v813380; RV64ZVE32F-NEXT: add a2, a0, a213381; RV64ZVE32F-NEXT: lbu a2, 0(a2)13382; RV64ZVE32F-NEXT: vmv.s.x v10, a213383; RV64ZVE32F-NEXT: vsetivli zero, 15, e8, m1, tu, ma13384; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 1413385; RV64ZVE32F-NEXT: .LBB107_30: # %else4113386; RV64ZVE32F-NEXT: lui a2, 104856813387; RV64ZVE32F-NEXT: and a1, a1, a213388; RV64ZVE32F-NEXT: beqz a1, .LBB107_3213389; RV64ZVE32F-NEXT: # %bb.31: # %cond.load4313390; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma13391; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 113392; RV64ZVE32F-NEXT: vmv.x.s a1, v813393; RV64ZVE32F-NEXT: add a0, a0, a113394; RV64ZVE32F-NEXT: lbu a0, 0(a0)13395; RV64ZVE32F-NEXT: vmv.s.x v8, a013396; RV64ZVE32F-NEXT: vsetivli zero, 16, e8, m1, ta, ma13397; RV64ZVE32F-NEXT: vslideup.vi v9, v8, 1513398; RV64ZVE32F-NEXT: .LBB107_32: # %else4413399; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma13400; RV64ZVE32F-NEXT: vmv1r.v v8, v913401; RV64ZVE32F-NEXT: ret13402 %ptrs = getelementptr inbounds i8, ptr %base, <16 x i8> %idxs13403 %v = call <16 x i8> @llvm.masked.gather.v16i8.v16p0(<16 x ptr> %ptrs, i32 2, <16 x i1> %m, <16 x i8> %passthru)13404 ret <16 x i8> %v13405}13406 13407define <32 x i8> @mgather_baseidx_v32i8(ptr %base, <32 x i8> %idxs, <32 x i1> %m, <32 x i8> %passthru) {13408; RV32-LABEL: mgather_baseidx_v32i8:13409; RV32: # %bb.0:13410; RV32-NEXT: li a1, 3213411; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma13412; RV32-NEXT: vsext.vf4 v16, v813413; RV32-NEXT: vsetvli zero, zero, e8, m2, ta, mu13414; RV32-NEXT: vluxei32.v v10, (a0), v16, v0.t13415; RV32-NEXT: vmv.v.v v8, v1013416; RV32-NEXT: ret13417;13418; RV64V-LABEL: mgather_baseidx_v32i8:13419; RV64V: # %bb.0:13420; RV64V-NEXT: vsetivli zero, 16, e64, m8, ta, ma13421; RV64V-NEXT: vsext.vf8 v16, v813422; RV64V-NEXT: vsetivli zero, 16, e8, m2, ta, ma13423; RV64V-NEXT: vslidedown.vi v12, v10, 1613424; RV64V-NEXT: vslidedown.vi v8, v8, 1613425; RV64V-NEXT: vsetivli zero, 16, e8, m1, ta, mu13426; RV64V-NEXT: vluxei64.v v10, (a0), v16, v0.t13427; RV64V-NEXT: vsetivli zero, 2, e8, mf4, ta, ma13428; RV64V-NEXT: vslidedown.vi v0, v0, 213429; RV64V-NEXT: vsetivli zero, 16, e64, m8, ta, ma13430; RV64V-NEXT: vsext.vf8 v16, v813431; RV64V-NEXT: vsetvli zero, zero, e8, m1, ta, mu13432; RV64V-NEXT: vluxei64.v v12, (a0), v16, v0.t13433; RV64V-NEXT: li a0, 3213434; RV64V-NEXT: vsetvli zero, a0, e8, m2, ta, ma13435; RV64V-NEXT: vslideup.vi v10, v12, 1613436; RV64V-NEXT: vmv.v.v v8, v1013437; RV64V-NEXT: ret13438;13439; RV64ZVE32F-LABEL: mgather_baseidx_v32i8:13440; RV64ZVE32F: # %bb.0:13441; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma13442; RV64ZVE32F-NEXT: vmv.x.s a1, v013443; RV64ZVE32F-NEXT: andi a2, a1, 113444; RV64ZVE32F-NEXT: beqz a2, .LBB108_213445; RV64ZVE32F-NEXT: # %bb.1: # %cond.load13446; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, mf4, tu, ma13447; RV64ZVE32F-NEXT: vmv.x.s a2, v813448; RV64ZVE32F-NEXT: add a2, a0, a213449; RV64ZVE32F-NEXT: lbu a2, 0(a2)13450; RV64ZVE32F-NEXT: vmv.s.x v10, a213451; RV64ZVE32F-NEXT: .LBB108_2: # %else13452; RV64ZVE32F-NEXT: andi a2, a1, 213453; RV64ZVE32F-NEXT: beqz a2, .LBB108_413454; RV64ZVE32F-NEXT: # %bb.3: # %cond.load113455; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, mf4, ta, ma13456; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 113457; RV64ZVE32F-NEXT: vmv.x.s a2, v1213458; RV64ZVE32F-NEXT: add a2, a0, a213459; RV64ZVE32F-NEXT: lbu a2, 0(a2)13460; RV64ZVE32F-NEXT: vmv.s.x v12, a213461; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, m1, tu, ma13462; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 113463; RV64ZVE32F-NEXT: .LBB108_4: # %else213464; RV64ZVE32F-NEXT: andi a2, a1, 413465; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma13466; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 213467; RV64ZVE32F-NEXT: beqz a2, .LBB108_613468; RV64ZVE32F-NEXT: # %bb.5: # %cond.load413469; RV64ZVE32F-NEXT: vmv.x.s a2, v1213470; RV64ZVE32F-NEXT: add a2, a0, a213471; RV64ZVE32F-NEXT: lbu a2, 0(a2)13472; RV64ZVE32F-NEXT: vmv.s.x v13, a213473; RV64ZVE32F-NEXT: vsetivli zero, 3, e8, m1, tu, ma13474; RV64ZVE32F-NEXT: vslideup.vi v10, v13, 213475; RV64ZVE32F-NEXT: .LBB108_6: # %else513476; RV64ZVE32F-NEXT: andi a2, a1, 813477; RV64ZVE32F-NEXT: beqz a2, .LBB108_813478; RV64ZVE32F-NEXT: # %bb.7: # %cond.load713479; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma13480; RV64ZVE32F-NEXT: vslidedown.vi v12, v12, 113481; RV64ZVE32F-NEXT: vmv.x.s a2, v1213482; RV64ZVE32F-NEXT: add a2, a0, a213483; RV64ZVE32F-NEXT: lbu a2, 0(a2)13484; RV64ZVE32F-NEXT: vmv.s.x v12, a213485; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, m1, tu, ma13486; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 313487; RV64ZVE32F-NEXT: .LBB108_8: # %else813488; RV64ZVE32F-NEXT: andi a2, a1, 1613489; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma13490; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 413491; RV64ZVE32F-NEXT: beqz a2, .LBB108_1013492; RV64ZVE32F-NEXT: # %bb.9: # %cond.load1013493; RV64ZVE32F-NEXT: vmv.x.s a2, v1213494; RV64ZVE32F-NEXT: add a2, a0, a213495; RV64ZVE32F-NEXT: lbu a2, 0(a2)13496; RV64ZVE32F-NEXT: vmv.s.x v13, a213497; RV64ZVE32F-NEXT: vsetivli zero, 5, e8, m1, tu, ma13498; RV64ZVE32F-NEXT: vslideup.vi v10, v13, 413499; RV64ZVE32F-NEXT: .LBB108_10: # %else1113500; RV64ZVE32F-NEXT: andi a2, a1, 3213501; RV64ZVE32F-NEXT: beqz a2, .LBB108_1213502; RV64ZVE32F-NEXT: # %bb.11: # %cond.load1313503; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma13504; RV64ZVE32F-NEXT: vslidedown.vi v13, v12, 113505; RV64ZVE32F-NEXT: vmv.x.s a2, v1313506; RV64ZVE32F-NEXT: add a2, a0, a213507; RV64ZVE32F-NEXT: lbu a2, 0(a2)13508; RV64ZVE32F-NEXT: vmv.s.x v13, a213509; RV64ZVE32F-NEXT: vsetivli zero, 6, e8, m1, tu, ma13510; RV64ZVE32F-NEXT: vslideup.vi v10, v13, 513511; RV64ZVE32F-NEXT: .LBB108_12: # %else1413512; RV64ZVE32F-NEXT: andi a2, a1, 6413513; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma13514; RV64ZVE32F-NEXT: vslidedown.vi v12, v12, 213515; RV64ZVE32F-NEXT: beqz a2, .LBB108_1413516; RV64ZVE32F-NEXT: # %bb.13: # %cond.load1613517; RV64ZVE32F-NEXT: vmv.x.s a2, v1213518; RV64ZVE32F-NEXT: add a2, a0, a213519; RV64ZVE32F-NEXT: lbu a2, 0(a2)13520; RV64ZVE32F-NEXT: vmv.s.x v13, a213521; RV64ZVE32F-NEXT: vsetivli zero, 7, e8, m1, tu, ma13522; RV64ZVE32F-NEXT: vslideup.vi v10, v13, 613523; RV64ZVE32F-NEXT: .LBB108_14: # %else1713524; RV64ZVE32F-NEXT: andi a2, a1, 12813525; RV64ZVE32F-NEXT: beqz a2, .LBB108_1613526; RV64ZVE32F-NEXT: # %bb.15: # %cond.load1913527; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma13528; RV64ZVE32F-NEXT: vslidedown.vi v12, v12, 113529; RV64ZVE32F-NEXT: vmv.x.s a2, v1213530; RV64ZVE32F-NEXT: add a2, a0, a213531; RV64ZVE32F-NEXT: lbu a2, 0(a2)13532; RV64ZVE32F-NEXT: vmv.s.x v12, a213533; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, m1, tu, ma13534; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 713535; RV64ZVE32F-NEXT: .LBB108_16: # %else2013536; RV64ZVE32F-NEXT: andi a2, a1, 25613537; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, m1, ta, ma13538; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 813539; RV64ZVE32F-NEXT: beqz a2, .LBB108_1813540; RV64ZVE32F-NEXT: # %bb.17: # %cond.load2213541; RV64ZVE32F-NEXT: vmv.x.s a2, v1213542; RV64ZVE32F-NEXT: add a2, a0, a213543; RV64ZVE32F-NEXT: lbu a2, 0(a2)13544; RV64ZVE32F-NEXT: vmv.s.x v13, a213545; RV64ZVE32F-NEXT: vsetivli zero, 9, e8, m1, tu, ma13546; RV64ZVE32F-NEXT: vslideup.vi v10, v13, 813547; RV64ZVE32F-NEXT: .LBB108_18: # %else2313548; RV64ZVE32F-NEXT: andi a2, a1, 51213549; RV64ZVE32F-NEXT: beqz a2, .LBB108_2013550; RV64ZVE32F-NEXT: # %bb.19: # %cond.load2513551; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma13552; RV64ZVE32F-NEXT: vslidedown.vi v13, v12, 113553; RV64ZVE32F-NEXT: vmv.x.s a2, v1313554; RV64ZVE32F-NEXT: add a2, a0, a213555; RV64ZVE32F-NEXT: lbu a2, 0(a2)13556; RV64ZVE32F-NEXT: vmv.s.x v13, a213557; RV64ZVE32F-NEXT: vsetivli zero, 10, e8, m1, tu, ma13558; RV64ZVE32F-NEXT: vslideup.vi v10, v13, 913559; RV64ZVE32F-NEXT: .LBB108_20: # %else2613560; RV64ZVE32F-NEXT: andi a2, a1, 102413561; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma13562; RV64ZVE32F-NEXT: vslidedown.vi v13, v12, 213563; RV64ZVE32F-NEXT: beqz a2, .LBB108_2213564; RV64ZVE32F-NEXT: # %bb.21: # %cond.load2813565; RV64ZVE32F-NEXT: vmv.x.s a2, v1313566; RV64ZVE32F-NEXT: add a2, a0, a213567; RV64ZVE32F-NEXT: lbu a2, 0(a2)13568; RV64ZVE32F-NEXT: vmv.s.x v14, a213569; RV64ZVE32F-NEXT: vsetivli zero, 11, e8, m1, tu, ma13570; RV64ZVE32F-NEXT: vslideup.vi v10, v14, 1013571; RV64ZVE32F-NEXT: .LBB108_22: # %else2913572; RV64ZVE32F-NEXT: slli a2, a1, 5213573; RV64ZVE32F-NEXT: bgez a2, .LBB108_2413574; RV64ZVE32F-NEXT: # %bb.23: # %cond.load3113575; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma13576; RV64ZVE32F-NEXT: vslidedown.vi v13, v13, 113577; RV64ZVE32F-NEXT: vmv.x.s a2, v1313578; RV64ZVE32F-NEXT: add a2, a0, a213579; RV64ZVE32F-NEXT: lbu a2, 0(a2)13580; RV64ZVE32F-NEXT: vmv.s.x v13, a213581; RV64ZVE32F-NEXT: vsetivli zero, 12, e8, m1, tu, ma13582; RV64ZVE32F-NEXT: vslideup.vi v10, v13, 1113583; RV64ZVE32F-NEXT: .LBB108_24: # %else3213584; RV64ZVE32F-NEXT: slli a2, a1, 5113585; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma13586; RV64ZVE32F-NEXT: vslidedown.vi v12, v12, 413587; RV64ZVE32F-NEXT: bgez a2, .LBB108_2613588; RV64ZVE32F-NEXT: # %bb.25: # %cond.load3413589; RV64ZVE32F-NEXT: vmv.x.s a2, v1213590; RV64ZVE32F-NEXT: add a2, a0, a213591; RV64ZVE32F-NEXT: lbu a2, 0(a2)13592; RV64ZVE32F-NEXT: vmv.s.x v13, a213593; RV64ZVE32F-NEXT: vsetivli zero, 13, e8, m1, tu, ma13594; RV64ZVE32F-NEXT: vslideup.vi v10, v13, 1213595; RV64ZVE32F-NEXT: .LBB108_26: # %else3513596; RV64ZVE32F-NEXT: slli a2, a1, 5013597; RV64ZVE32F-NEXT: bgez a2, .LBB108_2813598; RV64ZVE32F-NEXT: # %bb.27: # %cond.load3713599; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma13600; RV64ZVE32F-NEXT: vslidedown.vi v13, v12, 113601; RV64ZVE32F-NEXT: vmv.x.s a2, v1313602; RV64ZVE32F-NEXT: add a2, a0, a213603; RV64ZVE32F-NEXT: lbu a2, 0(a2)13604; RV64ZVE32F-NEXT: vmv.s.x v13, a213605; RV64ZVE32F-NEXT: vsetivli zero, 14, e8, m1, tu, ma13606; RV64ZVE32F-NEXT: vslideup.vi v10, v13, 1313607; RV64ZVE32F-NEXT: .LBB108_28: # %else3813608; RV64ZVE32F-NEXT: slli a2, a1, 4913609; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma13610; RV64ZVE32F-NEXT: vslidedown.vi v12, v12, 213611; RV64ZVE32F-NEXT: bgez a2, .LBB108_3013612; RV64ZVE32F-NEXT: # %bb.29: # %cond.load4013613; RV64ZVE32F-NEXT: vmv.x.s a2, v1213614; RV64ZVE32F-NEXT: add a2, a0, a213615; RV64ZVE32F-NEXT: lbu a2, 0(a2)13616; RV64ZVE32F-NEXT: vmv.s.x v13, a213617; RV64ZVE32F-NEXT: vsetivli zero, 15, e8, m1, tu, ma13618; RV64ZVE32F-NEXT: vslideup.vi v10, v13, 1413619; RV64ZVE32F-NEXT: .LBB108_30: # %else4113620; RV64ZVE32F-NEXT: slli a2, a1, 4813621; RV64ZVE32F-NEXT: vsetivli zero, 16, e8, m2, ta, ma13622; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1613623; RV64ZVE32F-NEXT: bltz a2, .LBB108_6313624; RV64ZVE32F-NEXT: # %bb.31: # %else4413625; RV64ZVE32F-NEXT: slli a2, a1, 4713626; RV64ZVE32F-NEXT: bltz a2, .LBB108_6413627; RV64ZVE32F-NEXT: .LBB108_32: # %else4713628; RV64ZVE32F-NEXT: slli a2, a1, 4613629; RV64ZVE32F-NEXT: bgez a2, .LBB108_3413630; RV64ZVE32F-NEXT: .LBB108_33: # %cond.load4913631; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma13632; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 113633; RV64ZVE32F-NEXT: vmv.x.s a2, v913634; RV64ZVE32F-NEXT: add a2, a0, a213635; RV64ZVE32F-NEXT: lbu a2, 0(a2)13636; RV64ZVE32F-NEXT: vmv.s.x v12, a213637; RV64ZVE32F-NEXT: vsetivli zero, 18, e8, m2, tu, ma13638; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 1713639; RV64ZVE32F-NEXT: .LBB108_34: # %else5013640; RV64ZVE32F-NEXT: slli a2, a1, 4513641; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma13642; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 213643; RV64ZVE32F-NEXT: bgez a2, .LBB108_3613644; RV64ZVE32F-NEXT: # %bb.35: # %cond.load5213645; RV64ZVE32F-NEXT: vmv.x.s a2, v913646; RV64ZVE32F-NEXT: add a2, a0, a213647; RV64ZVE32F-NEXT: lbu a2, 0(a2)13648; RV64ZVE32F-NEXT: vmv.s.x v12, a213649; RV64ZVE32F-NEXT: vsetivli zero, 19, e8, m2, tu, ma13650; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 1813651; RV64ZVE32F-NEXT: .LBB108_36: # %else5313652; RV64ZVE32F-NEXT: slli a2, a1, 4413653; RV64ZVE32F-NEXT: bgez a2, .LBB108_3813654; RV64ZVE32F-NEXT: # %bb.37: # %cond.load5513655; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma13656; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 113657; RV64ZVE32F-NEXT: vmv.x.s a2, v913658; RV64ZVE32F-NEXT: add a2, a0, a213659; RV64ZVE32F-NEXT: lbu a2, 0(a2)13660; RV64ZVE32F-NEXT: vmv.s.x v12, a213661; RV64ZVE32F-NEXT: vsetivli zero, 20, e8, m2, tu, ma13662; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 1913663; RV64ZVE32F-NEXT: .LBB108_38: # %else5613664; RV64ZVE32F-NEXT: slli a2, a1, 4313665; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma13666; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 413667; RV64ZVE32F-NEXT: bgez a2, .LBB108_4013668; RV64ZVE32F-NEXT: # %bb.39: # %cond.load5813669; RV64ZVE32F-NEXT: vmv.x.s a2, v913670; RV64ZVE32F-NEXT: add a2, a0, a213671; RV64ZVE32F-NEXT: lbu a2, 0(a2)13672; RV64ZVE32F-NEXT: vmv.s.x v12, a213673; RV64ZVE32F-NEXT: vsetivli zero, 21, e8, m2, tu, ma13674; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 2013675; RV64ZVE32F-NEXT: .LBB108_40: # %else5913676; RV64ZVE32F-NEXT: slli a2, a1, 4213677; RV64ZVE32F-NEXT: bgez a2, .LBB108_4213678; RV64ZVE32F-NEXT: # %bb.41: # %cond.load6113679; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma13680; RV64ZVE32F-NEXT: vslidedown.vi v12, v9, 113681; RV64ZVE32F-NEXT: vmv.x.s a2, v1213682; RV64ZVE32F-NEXT: add a2, a0, a213683; RV64ZVE32F-NEXT: lbu a2, 0(a2)13684; RV64ZVE32F-NEXT: vmv.s.x v12, a213685; RV64ZVE32F-NEXT: vsetivli zero, 22, e8, m2, tu, ma13686; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 2113687; RV64ZVE32F-NEXT: .LBB108_42: # %else6213688; RV64ZVE32F-NEXT: slli a2, a1, 4113689; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma13690; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 213691; RV64ZVE32F-NEXT: bgez a2, .LBB108_4413692; RV64ZVE32F-NEXT: # %bb.43: # %cond.load6413693; RV64ZVE32F-NEXT: vmv.x.s a2, v913694; RV64ZVE32F-NEXT: add a2, a0, a213695; RV64ZVE32F-NEXT: lbu a2, 0(a2)13696; RV64ZVE32F-NEXT: vmv.s.x v12, a213697; RV64ZVE32F-NEXT: vsetivli zero, 23, e8, m2, tu, ma13698; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 2213699; RV64ZVE32F-NEXT: .LBB108_44: # %else6513700; RV64ZVE32F-NEXT: slli a2, a1, 4013701; RV64ZVE32F-NEXT: bgez a2, .LBB108_4613702; RV64ZVE32F-NEXT: # %bb.45: # %cond.load6713703; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma13704; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 113705; RV64ZVE32F-NEXT: vmv.x.s a2, v913706; RV64ZVE32F-NEXT: add a2, a0, a213707; RV64ZVE32F-NEXT: lbu a2, 0(a2)13708; RV64ZVE32F-NEXT: vmv.s.x v12, a213709; RV64ZVE32F-NEXT: vsetivli zero, 24, e8, m2, tu, ma13710; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 2313711; RV64ZVE32F-NEXT: .LBB108_46: # %else6813712; RV64ZVE32F-NEXT: slli a2, a1, 3913713; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, m1, ta, ma13714; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 813715; RV64ZVE32F-NEXT: bgez a2, .LBB108_4813716; RV64ZVE32F-NEXT: # %bb.47: # %cond.load7013717; RV64ZVE32F-NEXT: vmv.x.s a2, v813718; RV64ZVE32F-NEXT: add a2, a0, a213719; RV64ZVE32F-NEXT: lbu a2, 0(a2)13720; RV64ZVE32F-NEXT: vmv.s.x v12, a213721; RV64ZVE32F-NEXT: vsetivli zero, 25, e8, m2, tu, ma13722; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 2413723; RV64ZVE32F-NEXT: .LBB108_48: # %else7113724; RV64ZVE32F-NEXT: slli a2, a1, 3813725; RV64ZVE32F-NEXT: bgez a2, .LBB108_5013726; RV64ZVE32F-NEXT: # %bb.49: # %cond.load7313727; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma13728; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 113729; RV64ZVE32F-NEXT: vmv.x.s a2, v913730; RV64ZVE32F-NEXT: add a2, a0, a213731; RV64ZVE32F-NEXT: lbu a2, 0(a2)13732; RV64ZVE32F-NEXT: vmv.s.x v12, a213733; RV64ZVE32F-NEXT: vsetivli zero, 26, e8, m2, tu, ma13734; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 2513735; RV64ZVE32F-NEXT: .LBB108_50: # %else7413736; RV64ZVE32F-NEXT: slli a2, a1, 3713737; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma13738; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 213739; RV64ZVE32F-NEXT: bgez a2, .LBB108_5213740; RV64ZVE32F-NEXT: # %bb.51: # %cond.load7613741; RV64ZVE32F-NEXT: vmv.x.s a2, v913742; RV64ZVE32F-NEXT: add a2, a0, a213743; RV64ZVE32F-NEXT: lbu a2, 0(a2)13744; RV64ZVE32F-NEXT: vmv.s.x v12, a213745; RV64ZVE32F-NEXT: vsetivli zero, 27, e8, m2, tu, ma13746; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 2613747; RV64ZVE32F-NEXT: .LBB108_52: # %else7713748; RV64ZVE32F-NEXT: slli a2, a1, 3613749; RV64ZVE32F-NEXT: bgez a2, .LBB108_5413750; RV64ZVE32F-NEXT: # %bb.53: # %cond.load7913751; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma13752; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 113753; RV64ZVE32F-NEXT: vmv.x.s a2, v913754; RV64ZVE32F-NEXT: add a2, a0, a213755; RV64ZVE32F-NEXT: lbu a2, 0(a2)13756; RV64ZVE32F-NEXT: vmv.s.x v12, a213757; RV64ZVE32F-NEXT: vsetivli zero, 28, e8, m2, tu, ma13758; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 2713759; RV64ZVE32F-NEXT: .LBB108_54: # %else8013760; RV64ZVE32F-NEXT: slli a2, a1, 3513761; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma13762; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 413763; RV64ZVE32F-NEXT: bgez a2, .LBB108_5613764; RV64ZVE32F-NEXT: # %bb.55: # %cond.load8213765; RV64ZVE32F-NEXT: vmv.x.s a2, v813766; RV64ZVE32F-NEXT: add a2, a0, a213767; RV64ZVE32F-NEXT: lbu a2, 0(a2)13768; RV64ZVE32F-NEXT: vmv.s.x v12, a213769; RV64ZVE32F-NEXT: vsetivli zero, 29, e8, m2, tu, ma13770; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 2813771; RV64ZVE32F-NEXT: .LBB108_56: # %else8313772; RV64ZVE32F-NEXT: slli a2, a1, 3413773; RV64ZVE32F-NEXT: bgez a2, .LBB108_5813774; RV64ZVE32F-NEXT: # %bb.57: # %cond.load8513775; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma13776; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 113777; RV64ZVE32F-NEXT: vmv.x.s a2, v913778; RV64ZVE32F-NEXT: add a2, a0, a213779; RV64ZVE32F-NEXT: lbu a2, 0(a2)13780; RV64ZVE32F-NEXT: vmv.s.x v12, a213781; RV64ZVE32F-NEXT: vsetivli zero, 30, e8, m2, tu, ma13782; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 2913783; RV64ZVE32F-NEXT: .LBB108_58: # %else8613784; RV64ZVE32F-NEXT: slli a2, a1, 3313785; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma13786; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 213787; RV64ZVE32F-NEXT: bgez a2, .LBB108_6013788; RV64ZVE32F-NEXT: # %bb.59: # %cond.load8813789; RV64ZVE32F-NEXT: vmv.x.s a2, v813790; RV64ZVE32F-NEXT: add a2, a0, a213791; RV64ZVE32F-NEXT: lbu a2, 0(a2)13792; RV64ZVE32F-NEXT: vmv.s.x v12, a213793; RV64ZVE32F-NEXT: vsetivli zero, 31, e8, m2, tu, ma13794; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 3013795; RV64ZVE32F-NEXT: .LBB108_60: # %else8913796; RV64ZVE32F-NEXT: lui a2, 52428813797; RV64ZVE32F-NEXT: and a1, a1, a213798; RV64ZVE32F-NEXT: beqz a1, .LBB108_6213799; RV64ZVE32F-NEXT: # %bb.61: # %cond.load9113800; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma13801; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 113802; RV64ZVE32F-NEXT: vmv.x.s a1, v813803; RV64ZVE32F-NEXT: add a0, a0, a113804; RV64ZVE32F-NEXT: lbu a0, 0(a0)13805; RV64ZVE32F-NEXT: li a1, 3213806; RV64ZVE32F-NEXT: vmv.s.x v8, a013807; RV64ZVE32F-NEXT: vsetvli zero, a1, e8, m2, ta, ma13808; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 3113809; RV64ZVE32F-NEXT: .LBB108_62: # %else9213810; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma13811; RV64ZVE32F-NEXT: vmv2r.v v8, v1013812; RV64ZVE32F-NEXT: ret13813; RV64ZVE32F-NEXT: .LBB108_63: # %cond.load4313814; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma13815; RV64ZVE32F-NEXT: vslidedown.vi v9, v12, 113816; RV64ZVE32F-NEXT: vmv.x.s a2, v913817; RV64ZVE32F-NEXT: add a2, a0, a213818; RV64ZVE32F-NEXT: lbu a2, 0(a2)13819; RV64ZVE32F-NEXT: vmv.s.x v9, a213820; RV64ZVE32F-NEXT: vsetivli zero, 16, e8, m1, tu, ma13821; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 1513822; RV64ZVE32F-NEXT: slli a2, a1, 4713823; RV64ZVE32F-NEXT: bgez a2, .LBB108_3213824; RV64ZVE32F-NEXT: .LBB108_64: # %cond.load4613825; RV64ZVE32F-NEXT: vsetivli zero, 17, e8, m2, tu, ma13826; RV64ZVE32F-NEXT: vmv.x.s a2, v813827; RV64ZVE32F-NEXT: add a2, a0, a213828; RV64ZVE32F-NEXT: lbu a2, 0(a2)13829; RV64ZVE32F-NEXT: vmv.s.x v12, a213830; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 1613831; RV64ZVE32F-NEXT: slli a2, a1, 4613832; RV64ZVE32F-NEXT: bltz a2, .LBB108_3313833; RV64ZVE32F-NEXT: j .LBB108_3413834 %ptrs = getelementptr inbounds i8, ptr %base, <32 x i8> %idxs13835 %v = call <32 x i8> @llvm.masked.gather.v32i8.v32p0(<32 x ptr> %ptrs, i32 2, <32 x i1> %m, <32 x i8> %passthru)13836 ret <32 x i8> %v13837}13838 13839define <4 x i32> @mgather_broadcast_load_unmasked(ptr %base) {13840; CHECK-LABEL: mgather_broadcast_load_unmasked:13841; CHECK: # %bb.0:13842; CHECK-NEXT: lw a0, 0(a0)13843; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma13844; CHECK-NEXT: vmv.v.x v8, a013845; CHECK-NEXT: ret13846 %ptrs = getelementptr inbounds i8, ptr %base, <4 x i32> zeroinitializer13847 %v = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> splat (i1 true), <4 x i32> poison)13848 ret <4 x i32> %v13849}13850 13851; Same as previous, but use an explicit splat instead of splat-via-gep13852define <4 x i32> @mgather_broadcast_load_unmasked2(ptr %base) {13853; CHECK-LABEL: mgather_broadcast_load_unmasked2:13854; CHECK: # %bb.0:13855; CHECK-NEXT: lw a0, 0(a0)13856; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma13857; CHECK-NEXT: vmv.v.x v8, a013858; CHECK-NEXT: ret13859 %ptrhead = insertelement <4 x ptr> poison, ptr %base, i32 013860 %ptrs = shufflevector <4 x ptr> %ptrhead, <4 x ptr> poison, <4 x i32> zeroinitializer13861 %v = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> splat (i1 true), <4 x i32> poison)13862 ret <4 x i32> %v13863}13864 13865define <4 x i32> @mgather_broadcast_load_masked(ptr %base, <4 x i1> %m) {13866; CHECK-LABEL: mgather_broadcast_load_masked:13867; CHECK: # %bb.0:13868; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma13869; CHECK-NEXT: vlse32.v v8, (a0), zero, v0.t13870; CHECK-NEXT: ret13871 %ptrs = getelementptr inbounds i8, ptr %base, <4 x i32> zeroinitializer13872 %v = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %m, <4 x i32> poison)13873 ret <4 x i32> %v13874}13875 13876define <4 x i32> @mgather_unit_stride_load(ptr %base) {13877; CHECK-LABEL: mgather_unit_stride_load:13878; CHECK: # %bb.0:13879; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma13880; CHECK-NEXT: vle32.v v8, (a0)13881; CHECK-NEXT: ret13882 %ptrs = getelementptr inbounds i32, ptr %base, <4 x i32> <i32 0, i32 1, i32 2, i32 3>13883 %v = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> splat (i1 true), <4 x i32> poison)13884 ret <4 x i32> %v13885}13886 13887define <4 x i32> @mgather_unit_stride_load_with_offset(ptr %base) {13888; CHECK-LABEL: mgather_unit_stride_load_with_offset:13889; CHECK: # %bb.0:13890; CHECK-NEXT: addi a0, a0, 1613891; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma13892; CHECK-NEXT: vle32.v v8, (a0)13893; CHECK-NEXT: ret13894 %ptrs = getelementptr inbounds i32, ptr %base, <4 x i32> <i32 4, i32 5, i32 6, i32 7>13895 %v = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> splat (i1 true), <4 x i32> poison)13896 ret <4 x i32> %v13897}13898 13899define <4 x i32> @mgather_unit_stride_load_narrow_idx(ptr %base) {13900; CHECK-LABEL: mgather_unit_stride_load_narrow_idx:13901; CHECK: # %bb.0:13902; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma13903; CHECK-NEXT: vle32.v v8, (a0)13904; CHECK-NEXT: ret13905 %ptrs = getelementptr inbounds i32, ptr %base, <4 x i8> <i8 0, i8 1, i8 2, i8 3>13906 %v = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> splat (i1 true), <4 x i32> poison)13907 ret <4 x i32> %v13908}13909 13910define <4 x i32> @mgather_unit_stride_load_wide_idx(ptr %base) {13911; CHECK-LABEL: mgather_unit_stride_load_wide_idx:13912; CHECK: # %bb.0:13913; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma13914; CHECK-NEXT: vle32.v v8, (a0)13915; CHECK-NEXT: ret13916 %ptrs = getelementptr inbounds i32, ptr %base, <4 x i128> <i128 0, i128 1, i128 2, i128 3>13917 %v = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> splat (i1 true), <4 x i32> poison)13918 ret <4 x i32> %v13919}13920 13921; This looks like a strided load (at i8), but isn't at index type.13922define <4 x i32> @mgather_narrow_edge_case(ptr %base) {13923; RV32-LABEL: mgather_narrow_edge_case:13924; RV32: # %bb.0:13925; RV32-NEXT: li a1, -51213926; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma13927; RV32-NEXT: vmv.v.i v0, 513928; RV32-NEXT: vmv.v.x v8, a113929; RV32-NEXT: vmerge.vim v8, v8, 0, v013930; RV32-NEXT: vluxei32.v v8, (a0), v813931; RV32-NEXT: ret13932;13933; RV64V-LABEL: mgather_narrow_edge_case:13934; RV64V: # %bb.0:13935; RV64V-NEXT: li a1, -51213936; RV64V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma13937; RV64V-NEXT: vmv.v.i v0, 513938; RV64V-NEXT: vsetivli zero, 4, e64, m2, ta, ma13939; RV64V-NEXT: vmv.v.x v8, a113940; RV64V-NEXT: vmerge.vim v10, v8, 0, v013941; RV64V-NEXT: vsetvli zero, zero, e32, m1, ta, ma13942; RV64V-NEXT: vluxei64.v v8, (a0), v1013943; RV64V-NEXT: ret13944;13945; RV64ZVE32F-LABEL: mgather_narrow_edge_case:13946; RV64ZVE32F: # %bb.0:13947; RV64ZVE32F-NEXT: lw a1, -512(a0)13948; RV64ZVE32F-NEXT: lw a0, 0(a0)13949; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, ta, ma13950; RV64ZVE32F-NEXT: vmv.v.i v0, 513951; RV64ZVE32F-NEXT: vmv.v.x v8, a113952; RV64ZVE32F-NEXT: vmerge.vxm v8, v8, a0, v013953; RV64ZVE32F-NEXT: ret13954 %ptrs = getelementptr inbounds i32, ptr %base, <4 x i8> <i8 0, i8 128, i8 0, i8 128>13955 %v = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> splat (i1 true), <4 x i32> poison)13956 ret <4 x i32> %v13957}13958 13959define <8 x i16> @mgather_strided_unaligned(ptr %base) {13960; RV32-LABEL: mgather_strided_unaligned:13961; RV32: # %bb.0:13962; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma13963; RV32-NEXT: vid.v v813964; RV32-NEXT: vsll.vi v8, v8, 213965; RV32-NEXT: vadd.vx v8, v8, a013966; RV32-NEXT: vmv.x.s a0, v813967; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma13968; RV32-NEXT: vslidedown.vi v10, v8, 113969; RV32-NEXT: vslidedown.vi v11, v8, 213970; RV32-NEXT: vmv.x.s a1, v1013971; RV32-NEXT: vslidedown.vi v10, v8, 313972; RV32-NEXT: vmv.x.s a2, v1113973; RV32-NEXT: vmv.x.s a3, v1013974; RV32-NEXT: vsetivli zero, 1, e32, m2, ta, ma13975; RV32-NEXT: vslidedown.vi v10, v8, 413976; RV32-NEXT: vmv.x.s a4, v1013977; RV32-NEXT: vslidedown.vi v10, v8, 513978; RV32-NEXT: vmv.x.s a5, v1013979; RV32-NEXT: vslidedown.vi v10, v8, 613980; RV32-NEXT: vslidedown.vi v8, v8, 713981; RV32-NEXT: lbu a6, 0(a0)13982; RV32-NEXT: lbu a0, 1(a0)13983; RV32-NEXT: vmv.x.s a7, v1013984; RV32-NEXT: vmv.x.s t0, v813985; RV32-NEXT: lbu t1, 0(a1)13986; RV32-NEXT: lbu a1, 1(a1)13987; RV32-NEXT: slli a0, a0, 813988; RV32-NEXT: or a0, a0, a613989; RV32-NEXT: lbu a6, 0(a2)13990; RV32-NEXT: lbu a2, 1(a2)13991; RV32-NEXT: slli a1, a1, 813992; RV32-NEXT: or a1, a1, t113993; RV32-NEXT: lbu t1, 0(a3)13994; RV32-NEXT: lbu a3, 1(a3)13995; RV32-NEXT: slli a2, a2, 813996; RV32-NEXT: or a2, a2, a613997; RV32-NEXT: lbu a6, 0(a4)13998; RV32-NEXT: lbu a4, 1(a4)13999; RV32-NEXT: slli a3, a3, 814000; RV32-NEXT: or a3, a3, t114001; RV32-NEXT: lbu t1, 0(a5)14002; RV32-NEXT: lbu a5, 1(a5)14003; RV32-NEXT: slli a4, a4, 814004; RV32-NEXT: or a4, a4, a614005; RV32-NEXT: lbu a6, 0(a7)14006; RV32-NEXT: lbu a7, 1(a7)14007; RV32-NEXT: slli a5, a5, 814008; RV32-NEXT: or a5, a5, t114009; RV32-NEXT: lbu t1, 0(t0)14010; RV32-NEXT: lbu t0, 1(t0)14011; RV32-NEXT: slli a7, a7, 814012; RV32-NEXT: or a6, a7, a614013; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu14014; RV32-NEXT: vmv.v.i v0, 1514015; RV32-NEXT: slli t0, t0, 814016; RV32-NEXT: or a7, t0, t114017; RV32-NEXT: vmv.v.x v8, a014018; RV32-NEXT: vmv.v.x v9, a414019; RV32-NEXT: vslide1down.vx v8, v8, a114020; RV32-NEXT: vslide1down.vx v9, v9, a514021; RV32-NEXT: vslide1down.vx v10, v8, a214022; RV32-NEXT: vslide1down.vx v8, v9, a614023; RV32-NEXT: vslide1down.vx v8, v8, a714024; RV32-NEXT: vslide1down.vx v9, v10, a314025; RV32-NEXT: vslidedown.vi v8, v9, 4, v0.t14026; RV32-NEXT: ret14027;14028; RV64V-LABEL: mgather_strided_unaligned:14029; RV64V: # %bb.0:14030; RV64V-NEXT: addi sp, sp, -12814031; RV64V-NEXT: .cfi_def_cfa_offset 12814032; RV64V-NEXT: sd ra, 120(sp) # 8-byte Folded Spill14033; RV64V-NEXT: sd s0, 112(sp) # 8-byte Folded Spill14034; RV64V-NEXT: .cfi_offset ra, -814035; RV64V-NEXT: .cfi_offset s0, -1614036; RV64V-NEXT: addi s0, sp, 12814037; RV64V-NEXT: .cfi_def_cfa s0, 014038; RV64V-NEXT: andi sp, sp, -6414039; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma14040; RV64V-NEXT: vid.v v814041; RV64V-NEXT: mv a1, sp14042; RV64V-NEXT: vsll.vi v8, v8, 214043; RV64V-NEXT: vadd.vx v8, v8, a014044; RV64V-NEXT: vmv.x.s a0, v814045; RV64V-NEXT: vsetivli zero, 1, e64, m1, ta, ma14046; RV64V-NEXT: vslidedown.vi v12, v8, 114047; RV64V-NEXT: vmv.x.s a2, v1214048; RV64V-NEXT: vsetivli zero, 1, e64, m2, ta, ma14049; RV64V-NEXT: vslidedown.vi v12, v8, 214050; RV64V-NEXT: vmv.x.s a3, v1214051; RV64V-NEXT: vslidedown.vi v12, v8, 314052; RV64V-NEXT: lbu a4, 0(a0)14053; RV64V-NEXT: lbu a0, 1(a0)14054; RV64V-NEXT: vmv.x.s a5, v1214055; RV64V-NEXT: lbu a6, 0(a2)14056; RV64V-NEXT: lbu a2, 1(a2)14057; RV64V-NEXT: lbu a7, 0(a3)14058; RV64V-NEXT: lbu a3, 1(a3)14059; RV64V-NEXT: lbu t0, 0(a5)14060; RV64V-NEXT: lbu a5, 1(a5)14061; RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, mu14062; RV64V-NEXT: vse64.v v8, (a1)14063; RV64V-NEXT: slli a0, a0, 814064; RV64V-NEXT: or a0, a0, a414065; RV64V-NEXT: slli a2, a2, 814066; RV64V-NEXT: slli a3, a3, 814067; RV64V-NEXT: or a1, a2, a614068; RV64V-NEXT: or a2, a3, a714069; RV64V-NEXT: ld a3, 32(sp)14070; RV64V-NEXT: ld a4, 40(sp)14071; RV64V-NEXT: ld a6, 48(sp)14072; RV64V-NEXT: ld a7, 56(sp)14073; RV64V-NEXT: slli a5, a5, 814074; RV64V-NEXT: or a5, a5, t014075; RV64V-NEXT: lbu t0, 0(a3)14076; RV64V-NEXT: lbu a3, 1(a3)14077; RV64V-NEXT: vmv.v.x v8, a014078; RV64V-NEXT: lbu a0, 0(a4)14079; RV64V-NEXT: lbu a4, 1(a4)14080; RV64V-NEXT: vslide1down.vx v8, v8, a114081; RV64V-NEXT: lbu a1, 0(a6)14082; RV64V-NEXT: lbu a6, 1(a6)14083; RV64V-NEXT: vslide1down.vx v8, v8, a214084; RV64V-NEXT: lbu a2, 0(a7)14085; RV64V-NEXT: lbu a7, 1(a7)14086; RV64V-NEXT: vslide1down.vx v9, v8, a514087; RV64V-NEXT: slli a3, a3, 814088; RV64V-NEXT: slli a4, a4, 814089; RV64V-NEXT: slli a6, a6, 814090; RV64V-NEXT: slli a7, a7, 814091; RV64V-NEXT: or a3, a3, t014092; RV64V-NEXT: or a0, a4, a014093; RV64V-NEXT: or a1, a6, a114094; RV64V-NEXT: or a2, a7, a214095; RV64V-NEXT: vmv.v.x v8, a314096; RV64V-NEXT: vslide1down.vx v8, v8, a014097; RV64V-NEXT: vslide1down.vx v8, v8, a114098; RV64V-NEXT: vmv.v.i v0, 1514099; RV64V-NEXT: vslide1down.vx v8, v8, a214100; RV64V-NEXT: vslidedown.vi v8, v9, 4, v0.t14101; RV64V-NEXT: addi sp, s0, -12814102; RV64V-NEXT: .cfi_def_cfa sp, 12814103; RV64V-NEXT: ld ra, 120(sp) # 8-byte Folded Reload14104; RV64V-NEXT: ld s0, 112(sp) # 8-byte Folded Reload14105; RV64V-NEXT: .cfi_restore ra14106; RV64V-NEXT: .cfi_restore s014107; RV64V-NEXT: addi sp, sp, 12814108; RV64V-NEXT: .cfi_def_cfa_offset 014109; RV64V-NEXT: ret14110;14111; RV64ZVE32F-LABEL: mgather_strided_unaligned:14112; RV64ZVE32F: # %bb.0:14113; RV64ZVE32F-NEXT: lbu a1, 0(a0)14114; RV64ZVE32F-NEXT: lbu a2, 1(a0)14115; RV64ZVE32F-NEXT: lbu a3, 4(a0)14116; RV64ZVE32F-NEXT: lbu a4, 5(a0)14117; RV64ZVE32F-NEXT: lbu a5, 8(a0)14118; RV64ZVE32F-NEXT: lbu a6, 9(a0)14119; RV64ZVE32F-NEXT: lbu a7, 12(a0)14120; RV64ZVE32F-NEXT: lbu t0, 13(a0)14121; RV64ZVE32F-NEXT: slli a2, a2, 814122; RV64ZVE32F-NEXT: slli a4, a4, 814123; RV64ZVE32F-NEXT: or a1, a2, a114124; RV64ZVE32F-NEXT: or a3, a4, a314125; RV64ZVE32F-NEXT: lbu a2, 16(a0)14126; RV64ZVE32F-NEXT: lbu a4, 17(a0)14127; RV64ZVE32F-NEXT: lbu t1, 20(a0)14128; RV64ZVE32F-NEXT: lbu t2, 21(a0)14129; RV64ZVE32F-NEXT: slli a6, a6, 814130; RV64ZVE32F-NEXT: or a5, a6, a514131; RV64ZVE32F-NEXT: slli t0, t0, 814132; RV64ZVE32F-NEXT: slli a4, a4, 814133; RV64ZVE32F-NEXT: slli t2, t2, 814134; RV64ZVE32F-NEXT: or a6, t0, a714135; RV64ZVE32F-NEXT: or a2, a4, a214136; RV64ZVE32F-NEXT: or a4, t2, t114137; RV64ZVE32F-NEXT: lbu a7, 25(a0)14138; RV64ZVE32F-NEXT: lbu t0, 24(a0)14139; RV64ZVE32F-NEXT: lbu t1, 28(a0)14140; RV64ZVE32F-NEXT: lbu a0, 29(a0)14141; RV64ZVE32F-NEXT: slli a7, a7, 814142; RV64ZVE32F-NEXT: or a7, a7, t014143; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, mu14144; RV64ZVE32F-NEXT: vmv.v.i v0, 1514145; RV64ZVE32F-NEXT: slli a0, a0, 814146; RV64ZVE32F-NEXT: or a0, a0, t114147; RV64ZVE32F-NEXT: vmv.v.x v8, a214148; RV64ZVE32F-NEXT: vmv.v.x v9, a114149; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a414150; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a314151; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a714152; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a514153; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a014154; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a614155; RV64ZVE32F-NEXT: vslidedown.vi v8, v9, 4, v0.t14156; RV64ZVE32F-NEXT: ret14157 %ptrs = getelementptr inbounds i16, ptr %base, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>14158 %v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 1, <8 x i1> splat (i1 true), <8 x i16> poison)14159 ret <8 x i16> %v14160}14161 14162; TODO: Recognize as strided load with SEW=3214163define <8 x i16> @mgather_strided_2xSEW(ptr %base) {14164; RV32-LABEL: mgather_strided_2xSEW:14165; RV32: # %bb.0:14166; RV32-NEXT: li a1, 814167; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma14168; RV32-NEXT: vlse32.v v8, (a0), a114169; RV32-NEXT: ret14170;14171; RV64V-LABEL: mgather_strided_2xSEW:14172; RV64V: # %bb.0:14173; RV64V-NEXT: li a1, 814174; RV64V-NEXT: vsetivli zero, 4, e32, m1, ta, ma14175; RV64V-NEXT: vlse32.v v8, (a0), a114176; RV64V-NEXT: ret14177;14178; RV64ZVE32F-LABEL: mgather_strided_2xSEW:14179; RV64ZVE32F: # %bb.0:14180; RV64ZVE32F-NEXT: lh a1, 0(a0)14181; RV64ZVE32F-NEXT: lh a2, 2(a0)14182; RV64ZVE32F-NEXT: lh a3, 8(a0)14183; RV64ZVE32F-NEXT: lh a4, 10(a0)14184; RV64ZVE32F-NEXT: lh a5, 16(a0)14185; RV64ZVE32F-NEXT: lh a6, 18(a0)14186; RV64ZVE32F-NEXT: lh a7, 24(a0)14187; RV64ZVE32F-NEXT: lh a0, 26(a0)14188; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, mu14189; RV64ZVE32F-NEXT: vmv.v.i v0, 1514190; RV64ZVE32F-NEXT: vmv.v.x v8, a514191; RV64ZVE32F-NEXT: vmv.v.x v9, a114192; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a614193; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a214194; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a714195; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a314196; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a014197; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a414198; RV64ZVE32F-NEXT: vslidedown.vi v8, v9, 4, v0.t14199; RV64ZVE32F-NEXT: ret14200 %ptrs = getelementptr inbounds i16, ptr %base, <8 x i32> <i32 0, i32 1, i32 4, i32 5, i32 8, i32 9, i32 12, i32 13>14201 %v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> splat (i1 true), <8 x i16> poison)14202 ret <8 x i16> %v14203}14204 14205; TODO: Recognize as strided load with SEW=3214206define <8 x i16> @mgather_strided_2xSEW_with_offset(ptr %base) {14207; RV32-LABEL: mgather_strided_2xSEW_with_offset:14208; RV32: # %bb.0:14209; RV32-NEXT: addi a0, a0, 414210; RV32-NEXT: li a1, 814211; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma14212; RV32-NEXT: vlse32.v v8, (a0), a114213; RV32-NEXT: ret14214;14215; RV64V-LABEL: mgather_strided_2xSEW_with_offset:14216; RV64V: # %bb.0:14217; RV64V-NEXT: addi a0, a0, 414218; RV64V-NEXT: li a1, 814219; RV64V-NEXT: vsetivli zero, 4, e32, m1, ta, ma14220; RV64V-NEXT: vlse32.v v8, (a0), a114221; RV64V-NEXT: ret14222;14223; RV64ZVE32F-LABEL: mgather_strided_2xSEW_with_offset:14224; RV64ZVE32F: # %bb.0:14225; RV64ZVE32F-NEXT: lh a1, 4(a0)14226; RV64ZVE32F-NEXT: lh a2, 6(a0)14227; RV64ZVE32F-NEXT: lh a3, 12(a0)14228; RV64ZVE32F-NEXT: lh a4, 14(a0)14229; RV64ZVE32F-NEXT: lh a5, 20(a0)14230; RV64ZVE32F-NEXT: lh a6, 22(a0)14231; RV64ZVE32F-NEXT: lh a7, 28(a0)14232; RV64ZVE32F-NEXT: lh a0, 30(a0)14233; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, mu14234; RV64ZVE32F-NEXT: vmv.v.i v0, 1514235; RV64ZVE32F-NEXT: vmv.v.x v8, a514236; RV64ZVE32F-NEXT: vmv.v.x v9, a114237; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a614238; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a214239; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a714240; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a314241; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a014242; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a414243; RV64ZVE32F-NEXT: vslidedown.vi v8, v9, 4, v0.t14244; RV64ZVE32F-NEXT: ret14245 %ptrs = getelementptr inbounds i16, ptr %base, <8 x i64> <i64 2, i64 3, i64 6, i64 7, i64 10, i64 11, i64 14, i64 15>14246 %v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> splat (i1 true), <8 x i16> poison)14247 ret <8 x i16> %v14248}14249 14250; TODO: Recognize as strided load with SEW=3214251define <8 x i16> @mgather_reverse_unit_strided_2xSEW(ptr %base) {14252; RV32-LABEL: mgather_reverse_unit_strided_2xSEW:14253; RV32: # %bb.0:14254; RV32-NEXT: addi a0, a0, 2814255; RV32-NEXT: li a1, -414256; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma14257; RV32-NEXT: vlse32.v v8, (a0), a114258; RV32-NEXT: ret14259;14260; RV64V-LABEL: mgather_reverse_unit_strided_2xSEW:14261; RV64V: # %bb.0:14262; RV64V-NEXT: addi a0, a0, 2814263; RV64V-NEXT: li a1, -414264; RV64V-NEXT: vsetivli zero, 4, e32, m1, ta, ma14265; RV64V-NEXT: vlse32.v v8, (a0), a114266; RV64V-NEXT: ret14267;14268; RV64ZVE32F-LABEL: mgather_reverse_unit_strided_2xSEW:14269; RV64ZVE32F: # %bb.0:14270; RV64ZVE32F-NEXT: lh a1, 24(a0)14271; RV64ZVE32F-NEXT: lh a2, 26(a0)14272; RV64ZVE32F-NEXT: lh a3, 28(a0)14273; RV64ZVE32F-NEXT: lh a4, 30(a0)14274; RV64ZVE32F-NEXT: lh a5, 20(a0)14275; RV64ZVE32F-NEXT: lh a6, 16(a0)14276; RV64ZVE32F-NEXT: lh a7, 18(a0)14277; RV64ZVE32F-NEXT: lh a0, 22(a0)14278; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, mu14279; RV64ZVE32F-NEXT: vmv.v.i v0, 1514280; RV64ZVE32F-NEXT: vmv.v.x v8, a514281; RV64ZVE32F-NEXT: vmv.v.x v9, a314282; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a014283; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a414284; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a614285; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a114286; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a714287; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a214288; RV64ZVE32F-NEXT: vslidedown.vi v8, v9, 4, v0.t14289; RV64ZVE32F-NEXT: ret14290 %ptrs = getelementptr inbounds i16, ptr %base, <8 x i64> <i64 14, i64 15, i64 12, i64 13, i64 10, i64 11, i64 8, i64 9>14291 %v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> splat (i1 true), <8 x i16> poison)14292 ret <8 x i16> %v14293}14294 14295; TODO: Recognize as strided load with SEW=3214296define <8 x i16> @mgather_reverse_strided_2xSEW(ptr %base) {14297; RV32-LABEL: mgather_reverse_strided_2xSEW:14298; RV32: # %bb.0:14299; RV32-NEXT: addi a0, a0, 2814300; RV32-NEXT: li a1, -814301; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma14302; RV32-NEXT: vlse32.v v8, (a0), a114303; RV32-NEXT: ret14304;14305; RV64V-LABEL: mgather_reverse_strided_2xSEW:14306; RV64V: # %bb.0:14307; RV64V-NEXT: addi a0, a0, 2814308; RV64V-NEXT: li a1, -814309; RV64V-NEXT: vsetivli zero, 4, e32, m1, ta, ma14310; RV64V-NEXT: vlse32.v v8, (a0), a114311; RV64V-NEXT: ret14312;14313; RV64ZVE32F-LABEL: mgather_reverse_strided_2xSEW:14314; RV64ZVE32F: # %bb.0:14315; RV64ZVE32F-NEXT: lh a1, 20(a0)14316; RV64ZVE32F-NEXT: lh a2, 22(a0)14317; RV64ZVE32F-NEXT: lh a3, 28(a0)14318; RV64ZVE32F-NEXT: lh a4, 30(a0)14319; RV64ZVE32F-NEXT: lh a5, 12(a0)14320; RV64ZVE32F-NEXT: lh a6, 4(a0)14321; RV64ZVE32F-NEXT: lh a7, 6(a0)14322; RV64ZVE32F-NEXT: lh a0, 14(a0)14323; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, mu14324; RV64ZVE32F-NEXT: vmv.v.i v0, 1514325; RV64ZVE32F-NEXT: vmv.v.x v8, a514326; RV64ZVE32F-NEXT: vmv.v.x v9, a314327; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a014328; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a414329; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a614330; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a114331; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a714332; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a214333; RV64ZVE32F-NEXT: vslidedown.vi v8, v9, 4, v0.t14334; RV64ZVE32F-NEXT: ret14335 %ptrs = getelementptr inbounds i16, ptr %base, <8 x i64> <i64 14, i64 15, i64 10, i64 11, i64 6, i64 7, i64 2, i64 3>14336 %v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> splat (i1 true), <8 x i16> poison)14337 ret <8 x i16> %v14338}14339 14340define <8 x i16> @mgather_gather_2xSEW(ptr %base) {14341; RV32-LABEL: mgather_gather_2xSEW:14342; RV32: # %bb.0:14343; RV32-NEXT: lui a1, 1651314344; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma14345; RV32-NEXT: vmv.s.x v9, a114346; RV32-NEXT: vluxei8.v v8, (a0), v914347; RV32-NEXT: ret14348;14349; RV64V-LABEL: mgather_gather_2xSEW:14350; RV64V: # %bb.0:14351; RV64V-NEXT: lui a1, 1651314352; RV64V-NEXT: vsetivli zero, 4, e32, m1, ta, ma14353; RV64V-NEXT: vmv.s.x v9, a114354; RV64V-NEXT: vluxei8.v v8, (a0), v914355; RV64V-NEXT: ret14356;14357; RV64ZVE32F-LABEL: mgather_gather_2xSEW:14358; RV64ZVE32F: # %bb.0:14359; RV64ZVE32F-NEXT: lh a1, 8(a0)14360; RV64ZVE32F-NEXT: lh a2, 10(a0)14361; RV64ZVE32F-NEXT: lh a3, 16(a0)14362; RV64ZVE32F-NEXT: lh a4, 18(a0)14363; RV64ZVE32F-NEXT: lh a5, 0(a0)14364; RV64ZVE32F-NEXT: lh a6, 2(a0)14365; RV64ZVE32F-NEXT: lh a7, 4(a0)14366; RV64ZVE32F-NEXT: lh a0, 6(a0)14367; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, mu14368; RV64ZVE32F-NEXT: vmv.v.i v0, 1514369; RV64ZVE32F-NEXT: vmv.v.x v8, a114370; RV64ZVE32F-NEXT: vmv.v.x v9, a514371; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a214372; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a614373; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a714374; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a314375; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a014376; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a414377; RV64ZVE32F-NEXT: vslidedown.vi v8, v9, 4, v0.t14378; RV64ZVE32F-NEXT: ret14379 %ptrs = getelementptr inbounds i16, ptr %base, <8 x i32> <i32 0, i32 1, i32 8, i32 9, i32 4, i32 5, i32 2, i32 3>14380 %v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> splat (i1 true), <8 x i16> poison)14381 ret <8 x i16> %v14382}14383 14384; Base pointer isn't sufficiently aligned to form gather with e3214385define <8 x i16> @mgather_gather_2xSEW_unaligned(ptr %base) {14386; RV32-LABEL: mgather_gather_2xSEW_unaligned:14387; RV32: # %bb.0:14388; RV32-NEXT: lui a1, %hi(.LCPI123_0)14389; RV32-NEXT: addi a1, a1, %lo(.LCPI123_0)14390; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma14391; RV32-NEXT: vle8.v v9, (a1)14392; RV32-NEXT: vluxei8.v v8, (a0), v914393; RV32-NEXT: ret14394;14395; RV64V-LABEL: mgather_gather_2xSEW_unaligned:14396; RV64V: # %bb.0:14397; RV64V-NEXT: lui a1, %hi(.LCPI123_0)14398; RV64V-NEXT: addi a1, a1, %lo(.LCPI123_0)14399; RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, ma14400; RV64V-NEXT: vle8.v v9, (a1)14401; RV64V-NEXT: vluxei8.v v8, (a0), v914402; RV64V-NEXT: ret14403;14404; RV64ZVE32F-LABEL: mgather_gather_2xSEW_unaligned:14405; RV64ZVE32F: # %bb.0:14406; RV64ZVE32F-NEXT: lh a1, 8(a0)14407; RV64ZVE32F-NEXT: lh a2, 10(a0)14408; RV64ZVE32F-NEXT: lh a3, 18(a0)14409; RV64ZVE32F-NEXT: lh a4, 20(a0)14410; RV64ZVE32F-NEXT: lh a5, 0(a0)14411; RV64ZVE32F-NEXT: lh a6, 2(a0)14412; RV64ZVE32F-NEXT: lh a7, 4(a0)14413; RV64ZVE32F-NEXT: lh a0, 6(a0)14414; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, mu14415; RV64ZVE32F-NEXT: vmv.v.i v0, 1514416; RV64ZVE32F-NEXT: vmv.v.x v8, a114417; RV64ZVE32F-NEXT: vmv.v.x v9, a514418; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a214419; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a614420; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a714421; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a314422; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a014423; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a414424; RV64ZVE32F-NEXT: vslidedown.vi v8, v9, 4, v0.t14425; RV64ZVE32F-NEXT: ret14426 %ptrs = getelementptr inbounds i16, ptr %base, <8 x i32> <i32 0, i32 1, i32 9, i32 10, i32 4, i32 5, i32 2, i32 3>14427 %v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 2, <8 x i1> splat (i1 true), <8 x i16> poison)14428 ret <8 x i16> %v14429}14430 14431; Despite sufficient starting alignment, the index values aren't properly14432; aligned for e32.14433define <8 x i16> @mgather_gather_2xSEW_unaligned2(ptr %base) {14434; RV32-LABEL: mgather_gather_2xSEW_unaligned2:14435; RV32: # %bb.0:14436; RV32-NEXT: lui a1, %hi(.LCPI124_0)14437; RV32-NEXT: addi a1, a1, %lo(.LCPI124_0)14438; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma14439; RV32-NEXT: vle8.v v9, (a1)14440; RV32-NEXT: vluxei8.v v8, (a0), v914441; RV32-NEXT: ret14442;14443; RV64V-LABEL: mgather_gather_2xSEW_unaligned2:14444; RV64V: # %bb.0:14445; RV64V-NEXT: lui a1, %hi(.LCPI124_0)14446; RV64V-NEXT: addi a1, a1, %lo(.LCPI124_0)14447; RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, ma14448; RV64V-NEXT: vle8.v v9, (a1)14449; RV64V-NEXT: vluxei8.v v8, (a0), v914450; RV64V-NEXT: ret14451;14452; RV64ZVE32F-LABEL: mgather_gather_2xSEW_unaligned2:14453; RV64ZVE32F: # %bb.0:14454; RV64ZVE32F-NEXT: lh a1, 2(a0)14455; RV64ZVE32F-NEXT: lh a2, 4(a0)14456; RV64ZVE32F-NEXT: lh a3, 6(a0)14457; RV64ZVE32F-NEXT: lh a4, 8(a0)14458; RV64ZVE32F-NEXT: lh a5, 10(a0)14459; RV64ZVE32F-NEXT: lh a6, 18(a0)14460; RV64ZVE32F-NEXT: lh a0, 20(a0)14461; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, mu14462; RV64ZVE32F-NEXT: vmv.v.i v0, 1514463; RV64ZVE32F-NEXT: vmv.v.x v8, a414464; RV64ZVE32F-NEXT: vmv.v.x v9, a114465; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a514466; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a214467; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a214468; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a614469; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a314470; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a014471; RV64ZVE32F-NEXT: vslidedown.vi v8, v9, 4, v0.t14472; RV64ZVE32F-NEXT: ret14473 %ptrs = getelementptr inbounds i16, ptr %base, <8 x i32> <i32 1, i32 2, i32 9, i32 10, i32 4, i32 5, i32 2, i32 3>14474 %v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> splat (i1 true), <8 x i16> poison)14475 ret <8 x i16> %v14476}14477 14478define <8 x i16> @mgather_gather_4xSEW(ptr %base) {14479; RV32V-LABEL: mgather_gather_4xSEW:14480; RV32V: # %bb.0:14481; RV32V-NEXT: li a1, 1614482; RV32V-NEXT: vsetivli zero, 2, e64, m1, ta, ma14483; RV32V-NEXT: vlse64.v v8, (a0), a114484; RV32V-NEXT: ret14485;14486; RV64V-LABEL: mgather_gather_4xSEW:14487; RV64V: # %bb.0:14488; RV64V-NEXT: li a1, 1614489; RV64V-NEXT: vsetivli zero, 2, e64, m1, ta, ma14490; RV64V-NEXT: vlse64.v v8, (a0), a114491; RV64V-NEXT: ret14492;14493; RV32ZVE32F-LABEL: mgather_gather_4xSEW:14494; RV32ZVE32F: # %bb.0:14495; RV32ZVE32F-NEXT: lui a1, 8217614496; RV32ZVE32F-NEXT: addi a1, a1, 102414497; RV32ZVE32F-NEXT: vsetivli zero, 4, e32, m1, ta, ma14498; RV32ZVE32F-NEXT: vmv.s.x v9, a114499; RV32ZVE32F-NEXT: vluxei8.v v8, (a0), v914500; RV32ZVE32F-NEXT: ret14501;14502; RV64ZVE32F-LABEL: mgather_gather_4xSEW:14503; RV64ZVE32F: # %bb.0:14504; RV64ZVE32F-NEXT: lh a1, 0(a0)14505; RV64ZVE32F-NEXT: lh a2, 2(a0)14506; RV64ZVE32F-NEXT: lh a3, 4(a0)14507; RV64ZVE32F-NEXT: lh a4, 6(a0)14508; RV64ZVE32F-NEXT: lh a5, 16(a0)14509; RV64ZVE32F-NEXT: lh a6, 18(a0)14510; RV64ZVE32F-NEXT: lh a7, 20(a0)14511; RV64ZVE32F-NEXT: lh a0, 22(a0)14512; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, mu14513; RV64ZVE32F-NEXT: vmv.v.i v0, 1514514; RV64ZVE32F-NEXT: vmv.v.x v8, a514515; RV64ZVE32F-NEXT: vmv.v.x v9, a114516; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a614517; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a214518; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a714519; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a314520; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a014521; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a414522; RV64ZVE32F-NEXT: vslidedown.vi v8, v9, 4, v0.t14523; RV64ZVE32F-NEXT: ret14524 %ptrs = getelementptr inbounds i16, ptr %base, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>14525 %v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 8, <8 x i1> splat (i1 true), <8 x i16> poison)14526 ret <8 x i16> %v14527}14528 14529; This is a case where we'd be able to do 4xSEW if we had proper alignment14530; but we only have sufficient alignment for 2xSEW.14531define <8 x i16> @mgather_gather_4xSEW_partial_align(ptr %base) {14532; RV32-LABEL: mgather_gather_4xSEW_partial_align:14533; RV32: # %bb.0:14534; RV32-NEXT: lui a1, 8217614535; RV32-NEXT: addi a1, a1, 102414536; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma14537; RV32-NEXT: vmv.s.x v9, a114538; RV32-NEXT: vluxei8.v v8, (a0), v914539; RV32-NEXT: ret14540;14541; RV64V-LABEL: mgather_gather_4xSEW_partial_align:14542; RV64V: # %bb.0:14543; RV64V-NEXT: lui a1, 8217614544; RV64V-NEXT: addi a1, a1, 102414545; RV64V-NEXT: vsetivli zero, 4, e32, m1, ta, ma14546; RV64V-NEXT: vmv.s.x v9, a114547; RV64V-NEXT: vluxei8.v v8, (a0), v914548; RV64V-NEXT: ret14549;14550; RV64ZVE32F-LABEL: mgather_gather_4xSEW_partial_align:14551; RV64ZVE32F: # %bb.0:14552; RV64ZVE32F-NEXT: lh a1, 0(a0)14553; RV64ZVE32F-NEXT: lh a2, 2(a0)14554; RV64ZVE32F-NEXT: lh a3, 4(a0)14555; RV64ZVE32F-NEXT: lh a4, 6(a0)14556; RV64ZVE32F-NEXT: lh a5, 16(a0)14557; RV64ZVE32F-NEXT: lh a6, 18(a0)14558; RV64ZVE32F-NEXT: lh a7, 20(a0)14559; RV64ZVE32F-NEXT: lh a0, 22(a0)14560; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, mu14561; RV64ZVE32F-NEXT: vmv.v.i v0, 1514562; RV64ZVE32F-NEXT: vmv.v.x v8, a514563; RV64ZVE32F-NEXT: vmv.v.x v9, a114564; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a614565; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a214566; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a714567; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a314568; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a014569; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a414570; RV64ZVE32F-NEXT: vslidedown.vi v8, v9, 4, v0.t14571; RV64ZVE32F-NEXT: ret14572 %ptrs = getelementptr inbounds i16, ptr %base, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>14573 %v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> splat (i1 true), <8 x i16> poison)14574 ret <8 x i16> %v14575}14576 14577define <8 x i16> @mgather_shuffle_reverse(ptr %base) {14578; CHECK-LABEL: mgather_shuffle_reverse:14579; CHECK: # %bb.0:14580; CHECK-NEXT: addi a0, a0, 1414581; CHECK-NEXT: li a1, -214582; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma14583; CHECK-NEXT: vlse16.v v8, (a0), a114584; CHECK-NEXT: ret14585 %ptrs = getelementptr inbounds i16, ptr %base, <8 x i64> <i64 7, i64 6, i64 5, i64 4, i64 3, i64 2, i64 1, i64 0>14586 %v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> splat (i1 true), <8 x i16> poison)14587 ret <8 x i16> %v14588}14589 14590define <8 x i16> @mgather_shuffle_rotate(ptr %base) {14591; RV32-LABEL: mgather_shuffle_rotate:14592; RV32: # %bb.0:14593; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma14594; RV32-NEXT: vle16.v v9, (a0)14595; RV32-NEXT: vslidedown.vi v8, v9, 414596; RV32-NEXT: vslideup.vi v8, v9, 414597; RV32-NEXT: ret14598;14599; RV64V-LABEL: mgather_shuffle_rotate:14600; RV64V: # %bb.0:14601; RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, ma14602; RV64V-NEXT: vle16.v v9, (a0)14603; RV64V-NEXT: vslidedown.vi v8, v9, 414604; RV64V-NEXT: vslideup.vi v8, v9, 414605; RV64V-NEXT: ret14606;14607; RV64ZVE32F-LABEL: mgather_shuffle_rotate:14608; RV64ZVE32F: # %bb.0:14609; RV64ZVE32F-NEXT: lh a1, 8(a0)14610; RV64ZVE32F-NEXT: lh a2, 10(a0)14611; RV64ZVE32F-NEXT: lh a3, 12(a0)14612; RV64ZVE32F-NEXT: lh a4, 14(a0)14613; RV64ZVE32F-NEXT: lh a5, 0(a0)14614; RV64ZVE32F-NEXT: lh a6, 2(a0)14615; RV64ZVE32F-NEXT: lh a7, 4(a0)14616; RV64ZVE32F-NEXT: lh a0, 6(a0)14617; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, mu14618; RV64ZVE32F-NEXT: vmv.v.i v0, 1514619; RV64ZVE32F-NEXT: vmv.v.x v8, a514620; RV64ZVE32F-NEXT: vmv.v.x v9, a114621; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a614622; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a214623; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a714624; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a314625; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a014626; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a414627; RV64ZVE32F-NEXT: vslidedown.vi v8, v9, 4, v0.t14628; RV64ZVE32F-NEXT: ret14629 %ptrs = getelementptr inbounds i16, ptr %base, <8 x i64> <i64 4, i64 5, i64 6, i64 7, i64 0, i64 1, i64 2, i64 3>14630 %v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> splat (i1 true), <8 x i16> poison)14631 ret <8 x i16> %v14632}14633 14634define <8 x i16> @mgather_shuffle_vrgather(ptr %base) {14635; RV32-LABEL: mgather_shuffle_vrgather:14636; RV32: # %bb.0:14637; RV32-NEXT: lui a1, %hi(.LCPI129_0)14638; RV32-NEXT: addi a1, a1, %lo(.LCPI129_0)14639; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma14640; RV32-NEXT: vle16.v v9, (a1)14641; RV32-NEXT: vle16.v v10, (a0)14642; RV32-NEXT: vrgather.vv v8, v10, v914643; RV32-NEXT: ret14644;14645; RV64V-LABEL: mgather_shuffle_vrgather:14646; RV64V: # %bb.0:14647; RV64V-NEXT: lui a1, %hi(.LCPI129_0)14648; RV64V-NEXT: addi a1, a1, %lo(.LCPI129_0)14649; RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, ma14650; RV64V-NEXT: vle16.v v9, (a1)14651; RV64V-NEXT: vle16.v v10, (a0)14652; RV64V-NEXT: vrgather.vv v8, v10, v914653; RV64V-NEXT: ret14654;14655; RV64ZVE32F-LABEL: mgather_shuffle_vrgather:14656; RV64ZVE32F: # %bb.0:14657; RV64ZVE32F-NEXT: lh a1, 0(a0)14658; RV64ZVE32F-NEXT: lh a2, 2(a0)14659; RV64ZVE32F-NEXT: lh a3, 4(a0)14660; RV64ZVE32F-NEXT: lh a4, 6(a0)14661; RV64ZVE32F-NEXT: lh a5, 8(a0)14662; RV64ZVE32F-NEXT: lh a6, 10(a0)14663; RV64ZVE32F-NEXT: lh a7, 12(a0)14664; RV64ZVE32F-NEXT: lh a0, 14(a0)14665; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, mu14666; RV64ZVE32F-NEXT: vmv.v.i v0, 1514667; RV64ZVE32F-NEXT: vmv.v.x v8, a514668; RV64ZVE32F-NEXT: vmv.v.x v9, a114669; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a614670; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a314671; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a714672; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a414673; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a014674; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a214675; RV64ZVE32F-NEXT: vslidedown.vi v8, v9, 4, v0.t14676; RV64ZVE32F-NEXT: ret14677 %ptrs = getelementptr inbounds i16, ptr %base, <8 x i64> <i64 0, i64 2, i64 3, i64 1, i64 4, i64 5, i64 6, i64 7>14678 %v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> splat (i1 true), <8 x i16> poison)14679 ret <8 x i16> %v14680}14681 14682; v32i64 is not a legal type, so make sure we don't try to combine the mgather14683; to a vlse intrinsic until it is legalized and split.14684define <32 x i64> @mgather_strided_split(ptr %base) {14685; RV32V-LABEL: mgather_strided_split:14686; RV32V: # %bb.0:14687; RV32V-NEXT: li a1, 1614688; RV32V-NEXT: vsetivli zero, 16, e64, m8, ta, ma14689; RV32V-NEXT: vlse64.v v8, (a0), a114690; RV32V-NEXT: addi a0, a0, 25614691; RV32V-NEXT: vlse64.v v16, (a0), a114692; RV32V-NEXT: ret14693;14694; RV64V-LABEL: mgather_strided_split:14695; RV64V: # %bb.0:14696; RV64V-NEXT: li a1, 1614697; RV64V-NEXT: vsetivli zero, 16, e64, m8, ta, ma14698; RV64V-NEXT: vlse64.v v8, (a0), a114699; RV64V-NEXT: addi a0, a0, 25614700; RV64V-NEXT: vlse64.v v16, (a0), a114701; RV64V-NEXT: ret14702;14703; RV32ZVE32F-LABEL: mgather_strided_split:14704; RV32ZVE32F: # %bb.0:14705; RV32ZVE32F-NEXT: addi sp, sp, -51214706; RV32ZVE32F-NEXT: .cfi_def_cfa_offset 51214707; RV32ZVE32F-NEXT: sw ra, 508(sp) # 4-byte Folded Spill14708; RV32ZVE32F-NEXT: sw s0, 504(sp) # 4-byte Folded Spill14709; RV32ZVE32F-NEXT: sw s2, 500(sp) # 4-byte Folded Spill14710; RV32ZVE32F-NEXT: sw s3, 496(sp) # 4-byte Folded Spill14711; RV32ZVE32F-NEXT: sw s4, 492(sp) # 4-byte Folded Spill14712; RV32ZVE32F-NEXT: sw s5, 488(sp) # 4-byte Folded Spill14713; RV32ZVE32F-NEXT: sw s6, 484(sp) # 4-byte Folded Spill14714; RV32ZVE32F-NEXT: sw s7, 480(sp) # 4-byte Folded Spill14715; RV32ZVE32F-NEXT: sw s8, 476(sp) # 4-byte Folded Spill14716; RV32ZVE32F-NEXT: sw s9, 472(sp) # 4-byte Folded Spill14717; RV32ZVE32F-NEXT: sw s10, 468(sp) # 4-byte Folded Spill14718; RV32ZVE32F-NEXT: sw s11, 464(sp) # 4-byte Folded Spill14719; RV32ZVE32F-NEXT: .cfi_offset ra, -414720; RV32ZVE32F-NEXT: .cfi_offset s0, -814721; RV32ZVE32F-NEXT: .cfi_offset s2, -1214722; RV32ZVE32F-NEXT: .cfi_offset s3, -1614723; RV32ZVE32F-NEXT: .cfi_offset s4, -2014724; RV32ZVE32F-NEXT: .cfi_offset s5, -2414725; RV32ZVE32F-NEXT: .cfi_offset s6, -2814726; RV32ZVE32F-NEXT: .cfi_offset s7, -3214727; RV32ZVE32F-NEXT: .cfi_offset s8, -3614728; RV32ZVE32F-NEXT: .cfi_offset s9, -4014729; RV32ZVE32F-NEXT: .cfi_offset s10, -4414730; RV32ZVE32F-NEXT: .cfi_offset s11, -4814731; RV32ZVE32F-NEXT: addi s0, sp, 51214732; RV32ZVE32F-NEXT: .cfi_def_cfa s0, 014733; RV32ZVE32F-NEXT: andi sp, sp, -12814734; RV32ZVE32F-NEXT: li a2, 3214735; RV32ZVE32F-NEXT: lw a3, 0(a1)14736; RV32ZVE32F-NEXT: sw a3, 236(sp) # 4-byte Folded Spill14737; RV32ZVE32F-NEXT: lw a3, 4(a1)14738; RV32ZVE32F-NEXT: sw a3, 232(sp) # 4-byte Folded Spill14739; RV32ZVE32F-NEXT: addi a3, sp, 25614740; RV32ZVE32F-NEXT: vsetvli zero, a2, e32, m8, ta, ma14741; RV32ZVE32F-NEXT: vid.v v814742; RV32ZVE32F-NEXT: vsll.vi v8, v8, 414743; RV32ZVE32F-NEXT: vadd.vx v8, v8, a114744; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma14745; RV32ZVE32F-NEXT: vslidedown.vi v16, v8, 114746; RV32ZVE32F-NEXT: vslidedown.vi v17, v8, 214747; RV32ZVE32F-NEXT: vmv.x.s a1, v1614748; RV32ZVE32F-NEXT: vslidedown.vi v16, v8, 314749; RV32ZVE32F-NEXT: vmv.x.s a4, v1714750; RV32ZVE32F-NEXT: vmv.x.s a5, v1614751; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma14752; RV32ZVE32F-NEXT: vslidedown.vi v16, v8, 414753; RV32ZVE32F-NEXT: vmv.x.s a6, v1614754; RV32ZVE32F-NEXT: vslidedown.vi v16, v8, 514755; RV32ZVE32F-NEXT: vmv.x.s a7, v1614756; RV32ZVE32F-NEXT: vslidedown.vi v16, v8, 614757; RV32ZVE32F-NEXT: vmv.x.s t0, v1614758; RV32ZVE32F-NEXT: vslidedown.vi v16, v8, 714759; RV32ZVE32F-NEXT: vmv.x.s t1, v1614760; RV32ZVE32F-NEXT: lw t2, 0(a1)14761; RV32ZVE32F-NEXT: sw t2, 196(sp) # 4-byte Folded Spill14762; RV32ZVE32F-NEXT: lw a1, 4(a1)14763; RV32ZVE32F-NEXT: sw a1, 192(sp) # 4-byte Folded Spill14764; RV32ZVE32F-NEXT: lw ra, 0(a4)14765; RV32ZVE32F-NEXT: lw a1, 4(a4)14766; RV32ZVE32F-NEXT: sw a1, 172(sp) # 4-byte Folded Spill14767; RV32ZVE32F-NEXT: lw a1, 0(a5)14768; RV32ZVE32F-NEXT: sw a1, 168(sp) # 4-byte Folded Spill14769; RV32ZVE32F-NEXT: lw a1, 4(a5)14770; RV32ZVE32F-NEXT: sw a1, 164(sp) # 4-byte Folded Spill14771; RV32ZVE32F-NEXT: lw a1, 0(a6)14772; RV32ZVE32F-NEXT: sw a1, 252(sp) # 4-byte Folded Spill14773; RV32ZVE32F-NEXT: lw a1, 4(a6)14774; RV32ZVE32F-NEXT: sw a1, 248(sp) # 4-byte Folded Spill14775; RV32ZVE32F-NEXT: lw a1, 0(a7)14776; RV32ZVE32F-NEXT: sw a1, 244(sp) # 4-byte Folded Spill14777; RV32ZVE32F-NEXT: lw a1, 4(a7)14778; RV32ZVE32F-NEXT: sw a1, 240(sp) # 4-byte Folded Spill14779; RV32ZVE32F-NEXT: lw a1, 0(t0)14780; RV32ZVE32F-NEXT: sw a1, 188(sp) # 4-byte Folded Spill14781; RV32ZVE32F-NEXT: lw a1, 4(t0)14782; RV32ZVE32F-NEXT: sw a1, 184(sp) # 4-byte Folded Spill14783; RV32ZVE32F-NEXT: lw a1, 0(t1)14784; RV32ZVE32F-NEXT: sw a1, 180(sp) # 4-byte Folded Spill14785; RV32ZVE32F-NEXT: lw a1, 4(t1)14786; RV32ZVE32F-NEXT: sw a1, 176(sp) # 4-byte Folded Spill14787; RV32ZVE32F-NEXT: vsetvli zero, a2, e32, m8, ta, ma14788; RV32ZVE32F-NEXT: vse32.v v8, (a3)14789; RV32ZVE32F-NEXT: lw a1, 288(sp)14790; RV32ZVE32F-NEXT: lw a2, 292(sp)14791; RV32ZVE32F-NEXT: lw a3, 296(sp)14792; RV32ZVE32F-NEXT: lw a4, 300(sp)14793; RV32ZVE32F-NEXT: lw a5, 0(a1)14794; RV32ZVE32F-NEXT: sw a5, 228(sp) # 4-byte Folded Spill14795; RV32ZVE32F-NEXT: lw a1, 4(a1)14796; RV32ZVE32F-NEXT: sw a1, 224(sp) # 4-byte Folded Spill14797; RV32ZVE32F-NEXT: lw a1, 0(a2)14798; RV32ZVE32F-NEXT: sw a1, 220(sp) # 4-byte Folded Spill14799; RV32ZVE32F-NEXT: lw a1, 4(a2)14800; RV32ZVE32F-NEXT: sw a1, 216(sp) # 4-byte Folded Spill14801; RV32ZVE32F-NEXT: lw a1, 0(a3)14802; RV32ZVE32F-NEXT: sw a1, 212(sp) # 4-byte Folded Spill14803; RV32ZVE32F-NEXT: lw a1, 4(a3)14804; RV32ZVE32F-NEXT: sw a1, 208(sp) # 4-byte Folded Spill14805; RV32ZVE32F-NEXT: lw a1, 0(a4)14806; RV32ZVE32F-NEXT: sw a1, 204(sp) # 4-byte Folded Spill14807; RV32ZVE32F-NEXT: lw a1, 4(a4)14808; RV32ZVE32F-NEXT: sw a1, 200(sp) # 4-byte Folded Spill14809; RV32ZVE32F-NEXT: lw a1, 304(sp)14810; RV32ZVE32F-NEXT: lw a2, 308(sp)14811; RV32ZVE32F-NEXT: lw a3, 312(sp)14812; RV32ZVE32F-NEXT: lw a4, 316(sp)14813; RV32ZVE32F-NEXT: lw a5, 0(a1)14814; RV32ZVE32F-NEXT: sw a5, 160(sp) # 4-byte Folded Spill14815; RV32ZVE32F-NEXT: lw a1, 4(a1)14816; RV32ZVE32F-NEXT: sw a1, 156(sp) # 4-byte Folded Spill14817; RV32ZVE32F-NEXT: lw a1, 0(a2)14818; RV32ZVE32F-NEXT: sw a1, 152(sp) # 4-byte Folded Spill14819; RV32ZVE32F-NEXT: lw a1, 4(a2)14820; RV32ZVE32F-NEXT: sw a1, 148(sp) # 4-byte Folded Spill14821; RV32ZVE32F-NEXT: lw a1, 0(a3)14822; RV32ZVE32F-NEXT: sw a1, 144(sp) # 4-byte Folded Spill14823; RV32ZVE32F-NEXT: lw a1, 4(a3)14824; RV32ZVE32F-NEXT: sw a1, 140(sp) # 4-byte Folded Spill14825; RV32ZVE32F-NEXT: lw a1, 0(a4)14826; RV32ZVE32F-NEXT: sw a1, 136(sp) # 4-byte Folded Spill14827; RV32ZVE32F-NEXT: lw a1, 4(a4)14828; RV32ZVE32F-NEXT: sw a1, 132(sp) # 4-byte Folded Spill14829; RV32ZVE32F-NEXT: lw a1, 320(sp)14830; RV32ZVE32F-NEXT: lw a2, 324(sp)14831; RV32ZVE32F-NEXT: lw a3, 328(sp)14832; RV32ZVE32F-NEXT: lw a4, 332(sp)14833; RV32ZVE32F-NEXT: lw a5, 0(a1)14834; RV32ZVE32F-NEXT: sw a5, 128(sp) # 4-byte Folded Spill14835; RV32ZVE32F-NEXT: lw a1, 4(a1)14836; RV32ZVE32F-NEXT: sw a1, 124(sp) # 4-byte Folded Spill14837; RV32ZVE32F-NEXT: lw a1, 0(a2)14838; RV32ZVE32F-NEXT: sw a1, 120(sp) # 4-byte Folded Spill14839; RV32ZVE32F-NEXT: lw a1, 4(a2)14840; RV32ZVE32F-NEXT: sw a1, 116(sp) # 4-byte Folded Spill14841; RV32ZVE32F-NEXT: lw s8, 0(a3)14842; RV32ZVE32F-NEXT: lw s9, 4(a3)14843; RV32ZVE32F-NEXT: lw s10, 0(a4)14844; RV32ZVE32F-NEXT: lw s11, 4(a4)14845; RV32ZVE32F-NEXT: lw a1, 336(sp)14846; RV32ZVE32F-NEXT: lw a2, 340(sp)14847; RV32ZVE32F-NEXT: lw a3, 344(sp)14848; RV32ZVE32F-NEXT: lw a4, 348(sp)14849; RV32ZVE32F-NEXT: lw t5, 0(a1)14850; RV32ZVE32F-NEXT: lw t6, 4(a1)14851; RV32ZVE32F-NEXT: lw s2, 0(a2)14852; RV32ZVE32F-NEXT: lw s3, 4(a2)14853; RV32ZVE32F-NEXT: lw a5, 0(a3)14854; RV32ZVE32F-NEXT: lw a6, 4(a3)14855; RV32ZVE32F-NEXT: lw a7, 0(a4)14856; RV32ZVE32F-NEXT: lw t0, 4(a4)14857; RV32ZVE32F-NEXT: lw a1, 352(sp)14858; RV32ZVE32F-NEXT: lw a2, 356(sp)14859; RV32ZVE32F-NEXT: lw a3, 360(sp)14860; RV32ZVE32F-NEXT: lw a4, 364(sp)14861; RV32ZVE32F-NEXT: lw t1, 0(a1)14862; RV32ZVE32F-NEXT: sw t1, 112(sp) # 4-byte Folded Spill14863; RV32ZVE32F-NEXT: lw a1, 4(a1)14864; RV32ZVE32F-NEXT: sw a1, 108(sp) # 4-byte Folded Spill14865; RV32ZVE32F-NEXT: lw a1, 0(a2)14866; RV32ZVE32F-NEXT: sw a1, 104(sp) # 4-byte Folded Spill14867; RV32ZVE32F-NEXT: lw a1, 4(a2)14868; RV32ZVE32F-NEXT: sw a1, 100(sp) # 4-byte Folded Spill14869; RV32ZVE32F-NEXT: lw s4, 0(a3)14870; RV32ZVE32F-NEXT: lw s5, 4(a3)14871; RV32ZVE32F-NEXT: lw s6, 0(a4)14872; RV32ZVE32F-NEXT: lw s7, 4(a4)14873; RV32ZVE32F-NEXT: lw a1, 368(sp)14874; RV32ZVE32F-NEXT: lw a2, 372(sp)14875; RV32ZVE32F-NEXT: lw a3, 376(sp)14876; RV32ZVE32F-NEXT: lw a4, 380(sp)14877; RV32ZVE32F-NEXT: lw t1, 0(a1)14878; RV32ZVE32F-NEXT: lw t2, 4(a1)14879; RV32ZVE32F-NEXT: lw t3, 0(a2)14880; RV32ZVE32F-NEXT: lw t4, 4(a2)14881; RV32ZVE32F-NEXT: lw a1, 0(a3)14882; RV32ZVE32F-NEXT: lw a2, 4(a3)14883; RV32ZVE32F-NEXT: lw a3, 0(a4)14884; RV32ZVE32F-NEXT: lw a4, 4(a4)14885; RV32ZVE32F-NEXT: sw ra, 16(a0)14886; RV32ZVE32F-NEXT: lw ra, 172(sp) # 4-byte Folded Reload14887; RV32ZVE32F-NEXT: sw ra, 20(a0)14888; RV32ZVE32F-NEXT: lw ra, 168(sp) # 4-byte Folded Reload14889; RV32ZVE32F-NEXT: sw ra, 24(a0)14890; RV32ZVE32F-NEXT: lw ra, 164(sp) # 4-byte Folded Reload14891; RV32ZVE32F-NEXT: sw ra, 28(a0)14892; RV32ZVE32F-NEXT: lw ra, 236(sp) # 4-byte Folded Reload14893; RV32ZVE32F-NEXT: sw ra, 0(a0)14894; RV32ZVE32F-NEXT: lw ra, 232(sp) # 4-byte Folded Reload14895; RV32ZVE32F-NEXT: sw ra, 4(a0)14896; RV32ZVE32F-NEXT: lw ra, 196(sp) # 4-byte Folded Reload14897; RV32ZVE32F-NEXT: sw ra, 8(a0)14898; RV32ZVE32F-NEXT: lw ra, 192(sp) # 4-byte Folded Reload14899; RV32ZVE32F-NEXT: sw ra, 12(a0)14900; RV32ZVE32F-NEXT: lw ra, 188(sp) # 4-byte Folded Reload14901; RV32ZVE32F-NEXT: sw ra, 48(a0)14902; RV32ZVE32F-NEXT: lw ra, 184(sp) # 4-byte Folded Reload14903; RV32ZVE32F-NEXT: sw ra, 52(a0)14904; RV32ZVE32F-NEXT: lw ra, 180(sp) # 4-byte Folded Reload14905; RV32ZVE32F-NEXT: sw ra, 56(a0)14906; RV32ZVE32F-NEXT: lw ra, 176(sp) # 4-byte Folded Reload14907; RV32ZVE32F-NEXT: sw ra, 60(a0)14908; RV32ZVE32F-NEXT: sw a5, 176(a0)14909; RV32ZVE32F-NEXT: sw a6, 180(a0)14910; RV32ZVE32F-NEXT: sw a7, 184(a0)14911; RV32ZVE32F-NEXT: sw t0, 188(a0)14912; RV32ZVE32F-NEXT: sw t5, 160(a0)14913; RV32ZVE32F-NEXT: sw t6, 164(a0)14914; RV32ZVE32F-NEXT: sw s2, 168(a0)14915; RV32ZVE32F-NEXT: sw s3, 172(a0)14916; RV32ZVE32F-NEXT: sw s8, 144(a0)14917; RV32ZVE32F-NEXT: sw s9, 148(a0)14918; RV32ZVE32F-NEXT: sw s10, 152(a0)14919; RV32ZVE32F-NEXT: sw s11, 156(a0)14920; RV32ZVE32F-NEXT: lw a5, 128(sp) # 4-byte Folded Reload14921; RV32ZVE32F-NEXT: sw a5, 128(a0)14922; RV32ZVE32F-NEXT: lw a5, 124(sp) # 4-byte Folded Reload14923; RV32ZVE32F-NEXT: sw a5, 132(a0)14924; RV32ZVE32F-NEXT: lw a5, 120(sp) # 4-byte Folded Reload14925; RV32ZVE32F-NEXT: sw a5, 136(a0)14926; RV32ZVE32F-NEXT: lw a5, 116(sp) # 4-byte Folded Reload14927; RV32ZVE32F-NEXT: sw a5, 140(a0)14928; RV32ZVE32F-NEXT: lw a5, 144(sp) # 4-byte Folded Reload14929; RV32ZVE32F-NEXT: sw a5, 112(a0)14930; RV32ZVE32F-NEXT: lw a5, 140(sp) # 4-byte Folded Reload14931; RV32ZVE32F-NEXT: sw a5, 116(a0)14932; RV32ZVE32F-NEXT: lw a5, 136(sp) # 4-byte Folded Reload14933; RV32ZVE32F-NEXT: sw a5, 120(a0)14934; RV32ZVE32F-NEXT: lw a5, 132(sp) # 4-byte Folded Reload14935; RV32ZVE32F-NEXT: sw a5, 124(a0)14936; RV32ZVE32F-NEXT: lw a5, 160(sp) # 4-byte Folded Reload14937; RV32ZVE32F-NEXT: sw a5, 96(a0)14938; RV32ZVE32F-NEXT: lw a5, 156(sp) # 4-byte Folded Reload14939; RV32ZVE32F-NEXT: sw a5, 100(a0)14940; RV32ZVE32F-NEXT: lw a5, 152(sp) # 4-byte Folded Reload14941; RV32ZVE32F-NEXT: sw a5, 104(a0)14942; RV32ZVE32F-NEXT: lw a5, 148(sp) # 4-byte Folded Reload14943; RV32ZVE32F-NEXT: sw a5, 108(a0)14944; RV32ZVE32F-NEXT: lw a5, 212(sp) # 4-byte Folded Reload14945; RV32ZVE32F-NEXT: sw a5, 80(a0)14946; RV32ZVE32F-NEXT: lw a5, 208(sp) # 4-byte Folded Reload14947; RV32ZVE32F-NEXT: sw a5, 84(a0)14948; RV32ZVE32F-NEXT: lw a5, 204(sp) # 4-byte Folded Reload14949; RV32ZVE32F-NEXT: sw a5, 88(a0)14950; RV32ZVE32F-NEXT: lw a5, 200(sp) # 4-byte Folded Reload14951; RV32ZVE32F-NEXT: sw a5, 92(a0)14952; RV32ZVE32F-NEXT: lw a5, 228(sp) # 4-byte Folded Reload14953; RV32ZVE32F-NEXT: sw a5, 64(a0)14954; RV32ZVE32F-NEXT: lw a5, 224(sp) # 4-byte Folded Reload14955; RV32ZVE32F-NEXT: sw a5, 68(a0)14956; RV32ZVE32F-NEXT: lw a5, 220(sp) # 4-byte Folded Reload14957; RV32ZVE32F-NEXT: sw a5, 72(a0)14958; RV32ZVE32F-NEXT: lw a5, 216(sp) # 4-byte Folded Reload14959; RV32ZVE32F-NEXT: sw a5, 76(a0)14960; RV32ZVE32F-NEXT: sw a1, 240(a0)14961; RV32ZVE32F-NEXT: sw a2, 244(a0)14962; RV32ZVE32F-NEXT: sw a3, 248(a0)14963; RV32ZVE32F-NEXT: sw a4, 252(a0)14964; RV32ZVE32F-NEXT: sw t1, 224(a0)14965; RV32ZVE32F-NEXT: sw t2, 228(a0)14966; RV32ZVE32F-NEXT: sw t3, 232(a0)14967; RV32ZVE32F-NEXT: sw t4, 236(a0)14968; RV32ZVE32F-NEXT: sw s4, 208(a0)14969; RV32ZVE32F-NEXT: sw s5, 212(a0)14970; RV32ZVE32F-NEXT: sw s6, 216(a0)14971; RV32ZVE32F-NEXT: sw s7, 220(a0)14972; RV32ZVE32F-NEXT: lw a1, 112(sp) # 4-byte Folded Reload14973; RV32ZVE32F-NEXT: sw a1, 192(a0)14974; RV32ZVE32F-NEXT: lw a1, 108(sp) # 4-byte Folded Reload14975; RV32ZVE32F-NEXT: sw a1, 196(a0)14976; RV32ZVE32F-NEXT: lw a1, 104(sp) # 4-byte Folded Reload14977; RV32ZVE32F-NEXT: sw a1, 200(a0)14978; RV32ZVE32F-NEXT: lw a1, 100(sp) # 4-byte Folded Reload14979; RV32ZVE32F-NEXT: sw a1, 204(a0)14980; RV32ZVE32F-NEXT: lw a1, 252(sp) # 4-byte Folded Reload14981; RV32ZVE32F-NEXT: sw a1, 32(a0)14982; RV32ZVE32F-NEXT: lw a1, 248(sp) # 4-byte Folded Reload14983; RV32ZVE32F-NEXT: sw a1, 36(a0)14984; RV32ZVE32F-NEXT: lw a1, 244(sp) # 4-byte Folded Reload14985; RV32ZVE32F-NEXT: sw a1, 40(a0)14986; RV32ZVE32F-NEXT: lw a1, 240(sp) # 4-byte Folded Reload14987; RV32ZVE32F-NEXT: sw a1, 44(a0)14988; RV32ZVE32F-NEXT: addi sp, s0, -51214989; RV32ZVE32F-NEXT: .cfi_def_cfa sp, 51214990; RV32ZVE32F-NEXT: lw ra, 508(sp) # 4-byte Folded Reload14991; RV32ZVE32F-NEXT: lw s0, 504(sp) # 4-byte Folded Reload14992; RV32ZVE32F-NEXT: lw s2, 500(sp) # 4-byte Folded Reload14993; RV32ZVE32F-NEXT: lw s3, 496(sp) # 4-byte Folded Reload14994; RV32ZVE32F-NEXT: lw s4, 492(sp) # 4-byte Folded Reload14995; RV32ZVE32F-NEXT: lw s5, 488(sp) # 4-byte Folded Reload14996; RV32ZVE32F-NEXT: lw s6, 484(sp) # 4-byte Folded Reload14997; RV32ZVE32F-NEXT: lw s7, 480(sp) # 4-byte Folded Reload14998; RV32ZVE32F-NEXT: lw s8, 476(sp) # 4-byte Folded Reload14999; RV32ZVE32F-NEXT: lw s9, 472(sp) # 4-byte Folded Reload15000; RV32ZVE32F-NEXT: lw s10, 468(sp) # 4-byte Folded Reload15001; RV32ZVE32F-NEXT: lw s11, 464(sp) # 4-byte Folded Reload15002; RV32ZVE32F-NEXT: .cfi_restore ra15003; RV32ZVE32F-NEXT: .cfi_restore s015004; RV32ZVE32F-NEXT: .cfi_restore s215005; RV32ZVE32F-NEXT: .cfi_restore s315006; RV32ZVE32F-NEXT: .cfi_restore s415007; RV32ZVE32F-NEXT: .cfi_restore s515008; RV32ZVE32F-NEXT: .cfi_restore s615009; RV32ZVE32F-NEXT: .cfi_restore s715010; RV32ZVE32F-NEXT: .cfi_restore s815011; RV32ZVE32F-NEXT: .cfi_restore s915012; RV32ZVE32F-NEXT: .cfi_restore s1015013; RV32ZVE32F-NEXT: .cfi_restore s1115014; RV32ZVE32F-NEXT: addi sp, sp, 51215015; RV32ZVE32F-NEXT: .cfi_def_cfa_offset 015016; RV32ZVE32F-NEXT: ret15017;15018; RV64ZVE32F-LABEL: mgather_strided_split:15019; RV64ZVE32F: # %bb.0:15020; RV64ZVE32F-NEXT: addi sp, sp, -14415021; RV64ZVE32F-NEXT: .cfi_def_cfa_offset 14415022; RV64ZVE32F-NEXT: sd ra, 136(sp) # 8-byte Folded Spill15023; RV64ZVE32F-NEXT: sd s0, 128(sp) # 8-byte Folded Spill15024; RV64ZVE32F-NEXT: sd s1, 120(sp) # 8-byte Folded Spill15025; RV64ZVE32F-NEXT: sd s2, 112(sp) # 8-byte Folded Spill15026; RV64ZVE32F-NEXT: sd s3, 104(sp) # 8-byte Folded Spill15027; RV64ZVE32F-NEXT: sd s4, 96(sp) # 8-byte Folded Spill15028; RV64ZVE32F-NEXT: sd s5, 88(sp) # 8-byte Folded Spill15029; RV64ZVE32F-NEXT: sd s6, 80(sp) # 8-byte Folded Spill15030; RV64ZVE32F-NEXT: sd s7, 72(sp) # 8-byte Folded Spill15031; RV64ZVE32F-NEXT: sd s8, 64(sp) # 8-byte Folded Spill15032; RV64ZVE32F-NEXT: sd s9, 56(sp) # 8-byte Folded Spill15033; RV64ZVE32F-NEXT: sd s10, 48(sp) # 8-byte Folded Spill15034; RV64ZVE32F-NEXT: sd s11, 40(sp) # 8-byte Folded Spill15035; RV64ZVE32F-NEXT: .cfi_offset ra, -815036; RV64ZVE32F-NEXT: .cfi_offset s0, -1615037; RV64ZVE32F-NEXT: .cfi_offset s1, -2415038; RV64ZVE32F-NEXT: .cfi_offset s2, -3215039; RV64ZVE32F-NEXT: .cfi_offset s3, -4015040; RV64ZVE32F-NEXT: .cfi_offset s4, -4815041; RV64ZVE32F-NEXT: .cfi_offset s5, -5615042; RV64ZVE32F-NEXT: .cfi_offset s6, -6415043; RV64ZVE32F-NEXT: .cfi_offset s7, -7215044; RV64ZVE32F-NEXT: .cfi_offset s8, -8015045; RV64ZVE32F-NEXT: .cfi_offset s9, -8815046; RV64ZVE32F-NEXT: .cfi_offset s10, -9615047; RV64ZVE32F-NEXT: .cfi_offset s11, -10415048; RV64ZVE32F-NEXT: ld a2, 0(a1)15049; RV64ZVE32F-NEXT: sd a2, 32(sp) # 8-byte Folded Spill15050; RV64ZVE32F-NEXT: ld a2, 16(a1)15051; RV64ZVE32F-NEXT: sd a2, 24(sp) # 8-byte Folded Spill15052; RV64ZVE32F-NEXT: ld a2, 32(a1)15053; RV64ZVE32F-NEXT: sd a2, 16(sp) # 8-byte Folded Spill15054; RV64ZVE32F-NEXT: ld a2, 48(a1)15055; RV64ZVE32F-NEXT: sd a2, 8(sp) # 8-byte Folded Spill15056; RV64ZVE32F-NEXT: ld a2, 64(a1)15057; RV64ZVE32F-NEXT: sd a2, 0(sp) # 8-byte Folded Spill15058; RV64ZVE32F-NEXT: ld a7, 80(a1)15059; RV64ZVE32F-NEXT: ld t0, 96(a1)15060; RV64ZVE32F-NEXT: ld t1, 112(a1)15061; RV64ZVE32F-NEXT: ld t2, 128(a1)15062; RV64ZVE32F-NEXT: ld t3, 144(a1)15063; RV64ZVE32F-NEXT: ld t4, 160(a1)15064; RV64ZVE32F-NEXT: ld t5, 176(a1)15065; RV64ZVE32F-NEXT: ld t6, 192(a1)15066; RV64ZVE32F-NEXT: ld s0, 208(a1)15067; RV64ZVE32F-NEXT: ld s1, 224(a1)15068; RV64ZVE32F-NEXT: ld s2, 240(a1)15069; RV64ZVE32F-NEXT: ld s3, 256(a1)15070; RV64ZVE32F-NEXT: ld s4, 272(a1)15071; RV64ZVE32F-NEXT: ld s5, 288(a1)15072; RV64ZVE32F-NEXT: ld s6, 304(a1)15073; RV64ZVE32F-NEXT: ld s7, 320(a1)15074; RV64ZVE32F-NEXT: ld s8, 336(a1)15075; RV64ZVE32F-NEXT: ld s9, 352(a1)15076; RV64ZVE32F-NEXT: ld s10, 368(a1)15077; RV64ZVE32F-NEXT: ld s11, 384(a1)15078; RV64ZVE32F-NEXT: ld ra, 400(a1)15079; RV64ZVE32F-NEXT: ld a6, 416(a1)15080; RV64ZVE32F-NEXT: ld a5, 432(a1)15081; RV64ZVE32F-NEXT: ld a2, 448(a1)15082; RV64ZVE32F-NEXT: ld a3, 464(a1)15083; RV64ZVE32F-NEXT: ld a4, 480(a1)15084; RV64ZVE32F-NEXT: ld a1, 496(a1)15085; RV64ZVE32F-NEXT: sd a2, 224(a0)15086; RV64ZVE32F-NEXT: sd a3, 232(a0)15087; RV64ZVE32F-NEXT: sd a4, 240(a0)15088; RV64ZVE32F-NEXT: sd a1, 248(a0)15089; RV64ZVE32F-NEXT: sd s11, 192(a0)15090; RV64ZVE32F-NEXT: sd ra, 200(a0)15091; RV64ZVE32F-NEXT: sd a6, 208(a0)15092; RV64ZVE32F-NEXT: sd a5, 216(a0)15093; RV64ZVE32F-NEXT: sd s7, 160(a0)15094; RV64ZVE32F-NEXT: sd s8, 168(a0)15095; RV64ZVE32F-NEXT: sd s9, 176(a0)15096; RV64ZVE32F-NEXT: sd s10, 184(a0)15097; RV64ZVE32F-NEXT: sd s3, 128(a0)15098; RV64ZVE32F-NEXT: sd s4, 136(a0)15099; RV64ZVE32F-NEXT: sd s5, 144(a0)15100; RV64ZVE32F-NEXT: sd s6, 152(a0)15101; RV64ZVE32F-NEXT: sd t6, 96(a0)15102; RV64ZVE32F-NEXT: sd s0, 104(a0)15103; RV64ZVE32F-NEXT: sd s1, 112(a0)15104; RV64ZVE32F-NEXT: sd s2, 120(a0)15105; RV64ZVE32F-NEXT: sd t2, 64(a0)15106; RV64ZVE32F-NEXT: sd t3, 72(a0)15107; RV64ZVE32F-NEXT: sd t4, 80(a0)15108; RV64ZVE32F-NEXT: sd t5, 88(a0)15109; RV64ZVE32F-NEXT: ld a1, 0(sp) # 8-byte Folded Reload15110; RV64ZVE32F-NEXT: sd a1, 32(a0)15111; RV64ZVE32F-NEXT: sd a7, 40(a0)15112; RV64ZVE32F-NEXT: sd t0, 48(a0)15113; RV64ZVE32F-NEXT: sd t1, 56(a0)15114; RV64ZVE32F-NEXT: ld a1, 32(sp) # 8-byte Folded Reload15115; RV64ZVE32F-NEXT: sd a1, 0(a0)15116; RV64ZVE32F-NEXT: ld a1, 24(sp) # 8-byte Folded Reload15117; RV64ZVE32F-NEXT: sd a1, 8(a0)15118; RV64ZVE32F-NEXT: ld a1, 16(sp) # 8-byte Folded Reload15119; RV64ZVE32F-NEXT: sd a1, 16(a0)15120; RV64ZVE32F-NEXT: ld a1, 8(sp) # 8-byte Folded Reload15121; RV64ZVE32F-NEXT: sd a1, 24(a0)15122; RV64ZVE32F-NEXT: ld ra, 136(sp) # 8-byte Folded Reload15123; RV64ZVE32F-NEXT: ld s0, 128(sp) # 8-byte Folded Reload15124; RV64ZVE32F-NEXT: ld s1, 120(sp) # 8-byte Folded Reload15125; RV64ZVE32F-NEXT: ld s2, 112(sp) # 8-byte Folded Reload15126; RV64ZVE32F-NEXT: ld s3, 104(sp) # 8-byte Folded Reload15127; RV64ZVE32F-NEXT: ld s4, 96(sp) # 8-byte Folded Reload15128; RV64ZVE32F-NEXT: ld s5, 88(sp) # 8-byte Folded Reload15129; RV64ZVE32F-NEXT: ld s6, 80(sp) # 8-byte Folded Reload15130; RV64ZVE32F-NEXT: ld s7, 72(sp) # 8-byte Folded Reload15131; RV64ZVE32F-NEXT: ld s8, 64(sp) # 8-byte Folded Reload15132; RV64ZVE32F-NEXT: ld s9, 56(sp) # 8-byte Folded Reload15133; RV64ZVE32F-NEXT: ld s10, 48(sp) # 8-byte Folded Reload15134; RV64ZVE32F-NEXT: ld s11, 40(sp) # 8-byte Folded Reload15135; RV64ZVE32F-NEXT: .cfi_restore ra15136; RV64ZVE32F-NEXT: .cfi_restore s015137; RV64ZVE32F-NEXT: .cfi_restore s115138; RV64ZVE32F-NEXT: .cfi_restore s215139; RV64ZVE32F-NEXT: .cfi_restore s315140; RV64ZVE32F-NEXT: .cfi_restore s415141; RV64ZVE32F-NEXT: .cfi_restore s515142; RV64ZVE32F-NEXT: .cfi_restore s615143; RV64ZVE32F-NEXT: .cfi_restore s715144; RV64ZVE32F-NEXT: .cfi_restore s815145; RV64ZVE32F-NEXT: .cfi_restore s915146; RV64ZVE32F-NEXT: .cfi_restore s1015147; RV64ZVE32F-NEXT: .cfi_restore s1115148; RV64ZVE32F-NEXT: addi sp, sp, 14415149; RV64ZVE32F-NEXT: .cfi_def_cfa_offset 015150; RV64ZVE32F-NEXT: ret15151 %ptrs = getelementptr inbounds i64, ptr %base, <32 x i64> <i64 0, i64 2, i64 4, i64 6, i64 8, i64 10, i64 12, i64 14, i64 16, i64 18, i64 20, i64 22, i64 24, i64 26, i64 28, i64 30, i64 32, i64 34, i64 36, i64 38, i64 40, i64 42, i64 44, i64 46, i64 48, i64 50, i64 52, i64 54, i64 56, i64 58, i64 60, i64 62>15152 %x = call <32 x i64> @llvm.masked.gather.v32i64.v32p0(<32 x ptr> %ptrs, i32 8, <32 x i1> splat (i1 true), <32 x i64> poison)15153 ret <32 x i64> %x15154}15155 15156define <4 x i32> @masked_gather_widen_sew_negative_stride(ptr %base) {15157; RV32V-LABEL: masked_gather_widen_sew_negative_stride:15158; RV32V: # %bb.0:15159; RV32V-NEXT: addi a0, a0, 13615160; RV32V-NEXT: li a1, -13615161; RV32V-NEXT: vsetivli zero, 2, e64, m1, ta, ma15162; RV32V-NEXT: vlse64.v v8, (a0), a115163; RV32V-NEXT: ret15164;15165; RV64V-LABEL: masked_gather_widen_sew_negative_stride:15166; RV64V: # %bb.0:15167; RV64V-NEXT: addi a0, a0, 13615168; RV64V-NEXT: li a1, -13615169; RV64V-NEXT: vsetivli zero, 2, e64, m1, ta, ma15170; RV64V-NEXT: vlse64.v v8, (a0), a115171; RV64V-NEXT: ret15172;15173; RV32ZVE32F-LABEL: masked_gather_widen_sew_negative_stride:15174; RV32ZVE32F: # %bb.0:15175; RV32ZVE32F-NEXT: lui a1, 1639315176; RV32ZVE32F-NEXT: addi a1, a1, -88815177; RV32ZVE32F-NEXT: vsetivli zero, 4, e32, m1, ta, ma15178; RV32ZVE32F-NEXT: vmv.s.x v9, a115179; RV32ZVE32F-NEXT: vluxei8.v v8, (a0), v915180; RV32ZVE32F-NEXT: ret15181;15182; RV64ZVE32F-LABEL: masked_gather_widen_sew_negative_stride:15183; RV64ZVE32F: # %bb.0:15184; RV64ZVE32F-NEXT: lw a1, 136(a0)15185; RV64ZVE32F-NEXT: lw a2, 140(a0)15186; RV64ZVE32F-NEXT: lw a3, 0(a0)15187; RV64ZVE32F-NEXT: lw a0, 4(a0)15188; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, ta, ma15189; RV64ZVE32F-NEXT: vmv.v.x v8, a115190; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a215191; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a315192; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a015193; RV64ZVE32F-NEXT: ret15194 %ptrs = getelementptr i32, ptr %base, <4 x i64> <i64 34, i64 35, i64 0, i64 1>15195 %x = call <4 x i32> @llvm.masked.gather.v4i32.v32p0(<4 x ptr> %ptrs, i32 8, <4 x i1> splat (i1 true), <4 x i32> poison)15196 ret <4 x i32> %x15197}15198 15199define <7 x i8> @mgather_baseidx_v7i8(ptr %base, <7 x i8> %idxs, <7 x i1> %m, <7 x i8> %passthru) {15200; RV32-LABEL: mgather_baseidx_v7i8:15201; RV32: # %bb.0:15202; RV32-NEXT: li a1, 12715203; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma15204; RV32-NEXT: vmv.s.x v10, a115205; RV32-NEXT: vmand.mm v0, v0, v1015206; RV32-NEXT: vsext.vf4 v10, v815207; RV32-NEXT: vsetvli zero, zero, e8, mf2, ta, mu15208; RV32-NEXT: vluxei32.v v9, (a0), v10, v0.t15209; RV32-NEXT: vmv1r.v v8, v915210; RV32-NEXT: ret15211;15212; RV64V-LABEL: mgather_baseidx_v7i8:15213; RV64V: # %bb.0:15214; RV64V-NEXT: li a1, 12715215; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma15216; RV64V-NEXT: vmv.s.x v10, a115217; RV64V-NEXT: vmand.mm v0, v0, v1015218; RV64V-NEXT: vsext.vf8 v12, v815219; RV64V-NEXT: vsetvli zero, zero, e8, mf2, ta, mu15220; RV64V-NEXT: vluxei64.v v9, (a0), v12, v0.t15221; RV64V-NEXT: vmv1r.v v8, v915222; RV64V-NEXT: ret15223;15224; RV64ZVE32F-LABEL: mgather_baseidx_v7i8:15225; RV64ZVE32F: # %bb.0:15226; RV64ZVE32F-NEXT: addi sp, sp, -1615227; RV64ZVE32F-NEXT: .cfi_def_cfa_offset 1615228; RV64ZVE32F-NEXT: .cfi_remember_state15229; RV64ZVE32F-NEXT: li a1, 6415230; RV64ZVE32F-NEXT: addi a2, sp, 815231; RV64ZVE32F-NEXT: vsetvli zero, a1, e8, m4, ta, ma15232; RV64ZVE32F-NEXT: vsm.v v0, (a2)15233; RV64ZVE32F-NEXT: ld a1, 8(sp)15234; RV64ZVE32F-NEXT: andi a2, a1, 115235; RV64ZVE32F-NEXT: beqz a2, .LBB132_215236; RV64ZVE32F-NEXT: # %bb.1: # %cond.load15237; RV64ZVE32F-NEXT: vmv.x.s a2, v815238; RV64ZVE32F-NEXT: add a2, a0, a215239; RV64ZVE32F-NEXT: lbu a2, 0(a2)15240; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma15241; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 115242; RV64ZVE32F-NEXT: vmv.v.x v11, a215243; RV64ZVE32F-NEXT: vmv.x.s a2, v1015244; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 215245; RV64ZVE32F-NEXT: vslide1down.vx v11, v11, a215246; RV64ZVE32F-NEXT: vmv.x.s a2, v1015247; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 315248; RV64ZVE32F-NEXT: vslide1down.vx v11, v11, a215249; RV64ZVE32F-NEXT: vmv.x.s a2, v1015250; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 415251; RV64ZVE32F-NEXT: vslide1down.vx v11, v11, a215252; RV64ZVE32F-NEXT: vmv.x.s a2, v1015253; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 515254; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 615255; RV64ZVE32F-NEXT: vslide1down.vx v11, v11, a215256; RV64ZVE32F-NEXT: vmv.x.s a2, v1015257; RV64ZVE32F-NEXT: vslide1down.vx v10, v11, a215258; RV64ZVE32F-NEXT: vmv.x.s a2, v915259; RV64ZVE32F-NEXT: vslide1down.vx v9, v10, a215260; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 115261; RV64ZVE32F-NEXT: .LBB132_2: # %else15262; RV64ZVE32F-NEXT: andi a2, a1, 215263; RV64ZVE32F-NEXT: beqz a2, .LBB132_415264; RV64ZVE32F-NEXT: # %bb.3: # %cond.load115265; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma15266; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 115267; RV64ZVE32F-NEXT: vmv.x.s a2, v915268; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma15269; RV64ZVE32F-NEXT: vslidedown.vi v11, v9, 215270; RV64ZVE32F-NEXT: vmv.x.s a3, v1015271; RV64ZVE32F-NEXT: add a3, a0, a315272; RV64ZVE32F-NEXT: lbu a3, 0(a3)15273; RV64ZVE32F-NEXT: vmv.v.x v10, a215274; RV64ZVE32F-NEXT: vmv.x.s a2, v1115275; RV64ZVE32F-NEXT: vslidedown.vi v11, v9, 315276; RV64ZVE32F-NEXT: vslide1down.vx v10, v10, a315277; RV64ZVE32F-NEXT: vmv.x.s a3, v1115278; RV64ZVE32F-NEXT: vslidedown.vi v11, v9, 415279; RV64ZVE32F-NEXT: vslide1down.vx v10, v10, a215280; RV64ZVE32F-NEXT: vmv.x.s a2, v1115281; RV64ZVE32F-NEXT: vslidedown.vi v11, v9, 515282; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 615283; RV64ZVE32F-NEXT: vslide1down.vx v10, v10, a315284; RV64ZVE32F-NEXT: vmv.x.s a3, v1115285; RV64ZVE32F-NEXT: vslide1down.vx v10, v10, a215286; RV64ZVE32F-NEXT: vslide1down.vx v10, v10, a315287; RV64ZVE32F-NEXT: vmv.x.s a2, v915288; RV64ZVE32F-NEXT: vslide1down.vx v9, v10, a215289; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 115290; RV64ZVE32F-NEXT: .LBB132_4: # %else215291; RV64ZVE32F-NEXT: andi a2, a1, 415292; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma15293; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 215294; RV64ZVE32F-NEXT: beqz a2, .LBB132_615295; RV64ZVE32F-NEXT: # %bb.5: # %cond.load415296; RV64ZVE32F-NEXT: vmv.x.s a2, v1015297; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma15298; RV64ZVE32F-NEXT: vslidedown.vi v11, v9, 115299; RV64ZVE32F-NEXT: vmv.x.s a3, v915300; RV64ZVE32F-NEXT: vslidedown.vi v12, v9, 315301; RV64ZVE32F-NEXT: vmv.x.s a4, v1115302; RV64ZVE32F-NEXT: vmv.v.x v11, a315303; RV64ZVE32F-NEXT: vmv.x.s a3, v1215304; RV64ZVE32F-NEXT: vslidedown.vi v12, v9, 415305; RV64ZVE32F-NEXT: add a2, a0, a215306; RV64ZVE32F-NEXT: lbu a2, 0(a2)15307; RV64ZVE32F-NEXT: vslide1down.vx v11, v11, a415308; RV64ZVE32F-NEXT: vmv.x.s a4, v1215309; RV64ZVE32F-NEXT: vslidedown.vi v12, v9, 515310; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 615311; RV64ZVE32F-NEXT: vslide1down.vx v11, v11, a215312; RV64ZVE32F-NEXT: vmv.x.s a2, v1215313; RV64ZVE32F-NEXT: vslide1down.vx v11, v11, a315314; RV64ZVE32F-NEXT: vslide1down.vx v11, v11, a415315; RV64ZVE32F-NEXT: vslide1down.vx v11, v11, a215316; RV64ZVE32F-NEXT: vmv.x.s a2, v915317; RV64ZVE32F-NEXT: vslide1down.vx v9, v11, a215318; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 115319; RV64ZVE32F-NEXT: .LBB132_6: # %else515320; RV64ZVE32F-NEXT: andi a2, a1, 815321; RV64ZVE32F-NEXT: beqz a2, .LBB132_815322; RV64ZVE32F-NEXT: # %bb.7: # %cond.load715323; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma15324; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 115325; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma15326; RV64ZVE32F-NEXT: vslidedown.vi v11, v9, 115327; RV64ZVE32F-NEXT: vmv.x.s a2, v915328; RV64ZVE32F-NEXT: vmv.x.s a3, v1015329; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 215330; RV64ZVE32F-NEXT: vmv.x.s a4, v1115331; RV64ZVE32F-NEXT: vmv.v.x v11, a215332; RV64ZVE32F-NEXT: vmv.x.s a2, v1015333; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 415334; RV64ZVE32F-NEXT: vslide1down.vx v11, v11, a415335; RV64ZVE32F-NEXT: vmv.x.s a4, v1015336; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 515337; RV64ZVE32F-NEXT: add a3, a0, a315338; RV64ZVE32F-NEXT: lbu a3, 0(a3)15339; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 615340; RV64ZVE32F-NEXT: vslide1down.vx v11, v11, a215341; RV64ZVE32F-NEXT: vmv.x.s a2, v1015342; RV64ZVE32F-NEXT: vslide1down.vx v10, v11, a315343; RV64ZVE32F-NEXT: vslide1down.vx v10, v10, a415344; RV64ZVE32F-NEXT: vslide1down.vx v10, v10, a215345; RV64ZVE32F-NEXT: vmv.x.s a2, v915346; RV64ZVE32F-NEXT: vslide1down.vx v9, v10, a215347; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 115348; RV64ZVE32F-NEXT: .LBB132_8: # %else815349; RV64ZVE32F-NEXT: andi a2, a1, 1615350; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma15351; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 415352; RV64ZVE32F-NEXT: bnez a2, .LBB132_1315353; RV64ZVE32F-NEXT: # %bb.9: # %else1115354; RV64ZVE32F-NEXT: andi a2, a1, 3215355; RV64ZVE32F-NEXT: bnez a2, .LBB132_1415356; RV64ZVE32F-NEXT: .LBB132_10: # %else1415357; RV64ZVE32F-NEXT: andi a1, a1, 6415358; RV64ZVE32F-NEXT: beqz a1, .LBB132_1215359; RV64ZVE32F-NEXT: .LBB132_11: # %cond.load1615360; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma15361; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 215362; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma15363; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 115364; RV64ZVE32F-NEXT: vmv.x.s a1, v915365; RV64ZVE32F-NEXT: vmv.x.s a2, v815366; RV64ZVE32F-NEXT: vmv.v.x v8, a115367; RV64ZVE32F-NEXT: vmv.x.s a1, v1015368; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 215369; RV64ZVE32F-NEXT: add a0, a0, a215370; RV64ZVE32F-NEXT: vmv.x.s a2, v1015371; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 315372; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a115373; RV64ZVE32F-NEXT: vmv.x.s a1, v1015374; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 415375; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 515376; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a215377; RV64ZVE32F-NEXT: vmv.x.s a2, v1015378; RV64ZVE32F-NEXT: lbu a0, 0(a0)15379; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a115380; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a215381; RV64ZVE32F-NEXT: vmv.x.s a1, v915382; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a115383; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a015384; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 115385; RV64ZVE32F-NEXT: .LBB132_12: # %else1715386; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma15387; RV64ZVE32F-NEXT: vmv1r.v v8, v915388; RV64ZVE32F-NEXT: addi sp, sp, 1615389; RV64ZVE32F-NEXT: .cfi_def_cfa_offset 015390; RV64ZVE32F-NEXT: ret15391; RV64ZVE32F-NEXT: .LBB132_13: # %cond.load1015392; RV64ZVE32F-NEXT: .cfi_restore_state15393; RV64ZVE32F-NEXT: vmv.x.s a2, v815394; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 115395; RV64ZVE32F-NEXT: vmv.x.s a3, v915396; RV64ZVE32F-NEXT: vslidedown.vi v11, v9, 215397; RV64ZVE32F-NEXT: vmv.x.s a4, v1015398; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma15399; RV64ZVE32F-NEXT: vmv.v.x v10, a315400; RV64ZVE32F-NEXT: vmv.x.s a3, v1115401; RV64ZVE32F-NEXT: vslidedown.vi v11, v9, 315402; RV64ZVE32F-NEXT: vslide1down.vx v10, v10, a415403; RV64ZVE32F-NEXT: vmv.x.s a4, v1115404; RV64ZVE32F-NEXT: vslidedown.vi v11, v9, 515405; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 615406; RV64ZVE32F-NEXT: add a2, a0, a215407; RV64ZVE32F-NEXT: lbu a2, 0(a2)15408; RV64ZVE32F-NEXT: vslide1down.vx v10, v10, a315409; RV64ZVE32F-NEXT: vmv.x.s a3, v1115410; RV64ZVE32F-NEXT: vslide1down.vx v10, v10, a415411; RV64ZVE32F-NEXT: vslide1down.vx v10, v10, a215412; RV64ZVE32F-NEXT: vslide1down.vx v10, v10, a315413; RV64ZVE32F-NEXT: vmv.x.s a2, v915414; RV64ZVE32F-NEXT: vslide1down.vx v9, v10, a215415; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 115416; RV64ZVE32F-NEXT: andi a2, a1, 3215417; RV64ZVE32F-NEXT: beqz a2, .LBB132_1015418; RV64ZVE32F-NEXT: .LBB132_14: # %cond.load1315419; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma15420; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 115421; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma15422; RV64ZVE32F-NEXT: vslidedown.vi v11, v9, 115423; RV64ZVE32F-NEXT: vmv.x.s a2, v915424; RV64ZVE32F-NEXT: vmv.x.s a3, v1015425; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 215426; RV64ZVE32F-NEXT: vmv.x.s a4, v1115427; RV64ZVE32F-NEXT: vmv.v.x v11, a215428; RV64ZVE32F-NEXT: vmv.x.s a2, v1015429; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 315430; RV64ZVE32F-NEXT: vslide1down.vx v11, v11, a415431; RV64ZVE32F-NEXT: vmv.x.s a4, v1015432; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 415433; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 615434; RV64ZVE32F-NEXT: add a3, a0, a315435; RV64ZVE32F-NEXT: lbu a3, 0(a3)15436; RV64ZVE32F-NEXT: vslide1down.vx v11, v11, a215437; RV64ZVE32F-NEXT: vmv.x.s a2, v1015438; RV64ZVE32F-NEXT: vslide1down.vx v10, v11, a415439; RV64ZVE32F-NEXT: vslide1down.vx v10, v10, a215440; RV64ZVE32F-NEXT: vslide1down.vx v10, v10, a315441; RV64ZVE32F-NEXT: vmv.x.s a2, v915442; RV64ZVE32F-NEXT: vslide1down.vx v9, v10, a215443; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 115444; RV64ZVE32F-NEXT: andi a1, a1, 6415445; RV64ZVE32F-NEXT: bnez a1, .LBB132_1115446; RV64ZVE32F-NEXT: j .LBB132_1215447 %ptrs = getelementptr inbounds i8, ptr %base, <7 x i8> %idxs15448 %v = call <7 x i8> @llvm.masked.gather.v7i8.v7p0(<7 x ptr> %ptrs, i32 1, <7 x i1> %m, <7 x i8> %passthru)15449 ret <7 x i8> %v15450}15451 15452;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:15453; RV32V-ZVFH: {{.*}}15454; RV32V-ZVFHMIN: {{.*}}15455; RV32ZVE32F-ZVFH: {{.*}}15456; RV32ZVE32F-ZVFHMIN: {{.*}}15457; RV64: {{.*}}15458; RV64V-ZVFH: {{.*}}15459; RV64V-ZVFHMIN: {{.*}}15460