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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zvfh,+zfbfmin,+zvfbfmin,+v -target-abi=ilp32d \3; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32V,RV32V-ZVFH4; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zvfh,+zfbfmin,+zvfbfmin,+v -target-abi=lp64d \5; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64V,RV64V-ZVFH6; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v -target-abi=ilp32d \7; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32V,RV32V-ZVFHMIN8; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v -target-abi=lp64d \9; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64V,RV64V-ZVFHMIN10 11; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zvfh,+zfbfmin,+zvfbfmin,+zve32f,+zvl128b -target-abi=ilp32d \12; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32ZVE32F,RV32ZVE32F-ZVFH13; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zvfh,+zfbfmin,+zvfbfmin,+zve32f,+zvl128b -target-abi=lp64d \14; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64ZVE32F,RV64ZVE32F-ZVFH15; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+zve32f,+zvl128b -target-abi=ilp32d \16; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32ZVE32F,RV32ZVE32F-ZVFHMIN17; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+zve32f,+zvl128b -target-abi=lp64d \18; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64ZVE32F,RV64ZVE32F-ZVFHMIN19 20define void @mscatter_v1i8(<1 x i8> %val, <1 x ptr> %ptrs, <1 x i1> %m) {21; RV32V-LABEL: mscatter_v1i8:22; RV32V:       # %bb.0:23; RV32V-NEXT:    vsetivli zero, 1, e8, mf8, ta, ma24; RV32V-NEXT:    vsoxei32.v v8, (zero), v9, v0.t25; RV32V-NEXT:    ret26;27; RV64V-LABEL: mscatter_v1i8:28; RV64V:       # %bb.0:29; RV64V-NEXT:    vsetivli zero, 1, e8, mf8, ta, ma30; RV64V-NEXT:    vsoxei64.v v8, (zero), v9, v0.t31; RV64V-NEXT:    ret32;33; RV32ZVE32F-LABEL: mscatter_v1i8:34; RV32ZVE32F:       # %bb.0:35; RV32ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma36; RV32ZVE32F-NEXT:    vsoxei32.v v8, (zero), v9, v0.t37; RV32ZVE32F-NEXT:    ret38;39; RV64ZVE32F-LABEL: mscatter_v1i8:40; RV64ZVE32F:       # %bb.0:41; RV64ZVE32F-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma42; RV64ZVE32F-NEXT:    vfirst.m a1, v043; RV64ZVE32F-NEXT:    bnez a1, .LBB0_244; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store45; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma46; RV64ZVE32F-NEXT:    vse8.v v8, (a0)47; RV64ZVE32F-NEXT:  .LBB0_2: # %else48; RV64ZVE32F-NEXT:    ret49  call void @llvm.masked.scatter.v1i8.v1p0(<1 x i8> %val, <1 x ptr> %ptrs, i32 1, <1 x i1> %m)50  ret void51}52 53define void @mscatter_v2i8(<2 x i8> %val, <2 x ptr> %ptrs, <2 x i1> %m) {54; RV32V-LABEL: mscatter_v2i8:55; RV32V:       # %bb.0:56; RV32V-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma57; RV32V-NEXT:    vsoxei32.v v8, (zero), v9, v0.t58; RV32V-NEXT:    ret59;60; RV64V-LABEL: mscatter_v2i8:61; RV64V:       # %bb.0:62; RV64V-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma63; RV64V-NEXT:    vsoxei64.v v8, (zero), v9, v0.t64; RV64V-NEXT:    ret65;66; RV32ZVE32F-LABEL: mscatter_v2i8:67; RV32ZVE32F:       # %bb.0:68; RV32ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma69; RV32ZVE32F-NEXT:    vsoxei32.v v8, (zero), v9, v0.t70; RV32ZVE32F-NEXT:    ret71;72; RV64ZVE32F-LABEL: mscatter_v2i8:73; RV64ZVE32F:       # %bb.0:74; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma75; RV64ZVE32F-NEXT:    vmv.x.s a2, v076; RV64ZVE32F-NEXT:    andi a3, a2, 177; RV64ZVE32F-NEXT:    bnez a3, .LBB1_378; RV64ZVE32F-NEXT:  # %bb.1: # %else79; RV64ZVE32F-NEXT:    andi a2, a2, 280; RV64ZVE32F-NEXT:    bnez a2, .LBB1_481; RV64ZVE32F-NEXT:  .LBB1_2: # %else282; RV64ZVE32F-NEXT:    ret83; RV64ZVE32F-NEXT:  .LBB1_3: # %cond.store84; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma85; RV64ZVE32F-NEXT:    vse8.v v8, (a0)86; RV64ZVE32F-NEXT:    andi a2, a2, 287; RV64ZVE32F-NEXT:    beqz a2, .LBB1_288; RV64ZVE32F-NEXT:  .LBB1_4: # %cond.store189; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma90; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 191; RV64ZVE32F-NEXT:    vse8.v v8, (a1)92; RV64ZVE32F-NEXT:    ret93  call void @llvm.masked.scatter.v2i8.v2p0(<2 x i8> %val, <2 x ptr> %ptrs, i32 1, <2 x i1> %m)94  ret void95}96 97define void @mscatter_v2i16_truncstore_v2i8(<2 x i16> %val, <2 x ptr> %ptrs, <2 x i1> %m) {98; RV32V-LABEL: mscatter_v2i16_truncstore_v2i8:99; RV32V:       # %bb.0:100; RV32V-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma101; RV32V-NEXT:    vnsrl.wi v8, v8, 0102; RV32V-NEXT:    vsoxei32.v v8, (zero), v9, v0.t103; RV32V-NEXT:    ret104;105; RV64V-LABEL: mscatter_v2i16_truncstore_v2i8:106; RV64V:       # %bb.0:107; RV64V-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma108; RV64V-NEXT:    vnsrl.wi v8, v8, 0109; RV64V-NEXT:    vsoxei64.v v8, (zero), v9, v0.t110; RV64V-NEXT:    ret111;112; RV32ZVE32F-LABEL: mscatter_v2i16_truncstore_v2i8:113; RV32ZVE32F:       # %bb.0:114; RV32ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma115; RV32ZVE32F-NEXT:    vnsrl.wi v8, v8, 0116; RV32ZVE32F-NEXT:    vsoxei32.v v8, (zero), v9, v0.t117; RV32ZVE32F-NEXT:    ret118;119; RV64ZVE32F-LABEL: mscatter_v2i16_truncstore_v2i8:120; RV64ZVE32F:       # %bb.0:121; RV64ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma122; RV64ZVE32F-NEXT:    vmv.x.s a2, v0123; RV64ZVE32F-NEXT:    andi a3, a2, 1124; RV64ZVE32F-NEXT:    vnsrl.wi v8, v8, 0125; RV64ZVE32F-NEXT:    bnez a3, .LBB2_3126; RV64ZVE32F-NEXT:  # %bb.1: # %else127; RV64ZVE32F-NEXT:    andi a2, a2, 2128; RV64ZVE32F-NEXT:    bnez a2, .LBB2_4129; RV64ZVE32F-NEXT:  .LBB2_2: # %else2130; RV64ZVE32F-NEXT:    ret131; RV64ZVE32F-NEXT:  .LBB2_3: # %cond.store132; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma133; RV64ZVE32F-NEXT:    vse8.v v8, (a0)134; RV64ZVE32F-NEXT:    andi a2, a2, 2135; RV64ZVE32F-NEXT:    beqz a2, .LBB2_2136; RV64ZVE32F-NEXT:  .LBB2_4: # %cond.store1137; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma138; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 1139; RV64ZVE32F-NEXT:    vse8.v v8, (a1)140; RV64ZVE32F-NEXT:    ret141  %tval = trunc <2 x i16> %val to <2 x i8>142  call void @llvm.masked.scatter.v2i8.v2p0(<2 x i8> %tval, <2 x ptr> %ptrs, i32 1, <2 x i1> %m)143  ret void144}145 146define void @mscatter_v2i32_truncstore_v2i8(<2 x i32> %val, <2 x ptr> %ptrs, <2 x i1> %m) {147; RV32V-LABEL: mscatter_v2i32_truncstore_v2i8:148; RV32V:       # %bb.0:149; RV32V-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma150; RV32V-NEXT:    vnsrl.wi v8, v8, 0151; RV32V-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma152; RV32V-NEXT:    vnsrl.wi v8, v8, 0153; RV32V-NEXT:    vsoxei32.v v8, (zero), v9, v0.t154; RV32V-NEXT:    ret155;156; RV64V-LABEL: mscatter_v2i32_truncstore_v2i8:157; RV64V:       # %bb.0:158; RV64V-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma159; RV64V-NEXT:    vnsrl.wi v8, v8, 0160; RV64V-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma161; RV64V-NEXT:    vnsrl.wi v8, v8, 0162; RV64V-NEXT:    vsoxei64.v v8, (zero), v9, v0.t163; RV64V-NEXT:    ret164;165; RV32ZVE32F-LABEL: mscatter_v2i32_truncstore_v2i8:166; RV32ZVE32F:       # %bb.0:167; RV32ZVE32F-NEXT:    vsetivli zero, 2, e16, mf2, ta, ma168; RV32ZVE32F-NEXT:    vnsrl.wi v8, v8, 0169; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma170; RV32ZVE32F-NEXT:    vnsrl.wi v8, v8, 0171; RV32ZVE32F-NEXT:    vsoxei32.v v8, (zero), v9, v0.t172; RV32ZVE32F-NEXT:    ret173;174; RV64ZVE32F-LABEL: mscatter_v2i32_truncstore_v2i8:175; RV64ZVE32F:       # %bb.0:176; RV64ZVE32F-NEXT:    vsetivli zero, 2, e16, mf2, ta, ma177; RV64ZVE32F-NEXT:    vnsrl.wi v8, v8, 0178; RV64ZVE32F-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma179; RV64ZVE32F-NEXT:    vmv.x.s a2, v0180; RV64ZVE32F-NEXT:    andi a3, a2, 1181; RV64ZVE32F-NEXT:    vnsrl.wi v8, v8, 0182; RV64ZVE32F-NEXT:    bnez a3, .LBB3_3183; RV64ZVE32F-NEXT:  # %bb.1: # %else184; RV64ZVE32F-NEXT:    andi a2, a2, 2185; RV64ZVE32F-NEXT:    bnez a2, .LBB3_4186; RV64ZVE32F-NEXT:  .LBB3_2: # %else2187; RV64ZVE32F-NEXT:    ret188; RV64ZVE32F-NEXT:  .LBB3_3: # %cond.store189; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma190; RV64ZVE32F-NEXT:    vse8.v v8, (a0)191; RV64ZVE32F-NEXT:    andi a2, a2, 2192; RV64ZVE32F-NEXT:    beqz a2, .LBB3_2193; RV64ZVE32F-NEXT:  .LBB3_4: # %cond.store1194; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma195; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 1196; RV64ZVE32F-NEXT:    vse8.v v8, (a1)197; RV64ZVE32F-NEXT:    ret198  %tval = trunc <2 x i32> %val to <2 x i8>199  call void @llvm.masked.scatter.v2i8.v2p0(<2 x i8> %tval, <2 x ptr> %ptrs, i32 1, <2 x i1> %m)200  ret void201}202 203define void @mscatter_v2i64_truncstore_v2i8(<2 x i64> %val, <2 x ptr> %ptrs, <2 x i1> %m) {204; RV32V-LABEL: mscatter_v2i64_truncstore_v2i8:205; RV32V:       # %bb.0:206; RV32V-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma207; RV32V-NEXT:    vnsrl.wi v8, v8, 0208; RV32V-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma209; RV32V-NEXT:    vnsrl.wi v8, v8, 0210; RV32V-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma211; RV32V-NEXT:    vnsrl.wi v8, v8, 0212; RV32V-NEXT:    vsoxei32.v v8, (zero), v9, v0.t213; RV32V-NEXT:    ret214;215; RV64V-LABEL: mscatter_v2i64_truncstore_v2i8:216; RV64V:       # %bb.0:217; RV64V-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma218; RV64V-NEXT:    vnsrl.wi v8, v8, 0219; RV64V-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma220; RV64V-NEXT:    vnsrl.wi v8, v8, 0221; RV64V-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma222; RV64V-NEXT:    vnsrl.wi v8, v8, 0223; RV64V-NEXT:    vsoxei64.v v8, (zero), v9, v0.t224; RV64V-NEXT:    ret225;226; RV32ZVE32F-LABEL: mscatter_v2i64_truncstore_v2i8:227; RV32ZVE32F:       # %bb.0:228; RV32ZVE32F-NEXT:    lw a1, 8(a0)229; RV32ZVE32F-NEXT:    lw a0, 0(a0)230; RV32ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma231; RV32ZVE32F-NEXT:    vmv.s.x v9, a1232; RV32ZVE32F-NEXT:    vmv.s.x v10, a0233; RV32ZVE32F-NEXT:    vslideup.vi v10, v9, 1234; RV32ZVE32F-NEXT:    vsoxei32.v v10, (zero), v8, v0.t235; RV32ZVE32F-NEXT:    ret236;237; RV64ZVE32F-LABEL: mscatter_v2i64_truncstore_v2i8:238; RV64ZVE32F:       # %bb.0:239; RV64ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma240; RV64ZVE32F-NEXT:    vmv.s.x v9, a1241; RV64ZVE32F-NEXT:    vmv.s.x v8, a0242; RV64ZVE32F-NEXT:    vmv.x.s a0, v0243; RV64ZVE32F-NEXT:    andi a1, a0, 1244; RV64ZVE32F-NEXT:    vslideup.vi v8, v9, 1245; RV64ZVE32F-NEXT:    bnez a1, .LBB4_3246; RV64ZVE32F-NEXT:  # %bb.1: # %else247; RV64ZVE32F-NEXT:    andi a0, a0, 2248; RV64ZVE32F-NEXT:    bnez a0, .LBB4_4249; RV64ZVE32F-NEXT:  .LBB4_2: # %else2250; RV64ZVE32F-NEXT:    ret251; RV64ZVE32F-NEXT:  .LBB4_3: # %cond.store252; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma253; RV64ZVE32F-NEXT:    vse8.v v8, (a2)254; RV64ZVE32F-NEXT:    andi a0, a0, 2255; RV64ZVE32F-NEXT:    beqz a0, .LBB4_2256; RV64ZVE32F-NEXT:  .LBB4_4: # %cond.store1257; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma258; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 1259; RV64ZVE32F-NEXT:    vse8.v v8, (a3)260; RV64ZVE32F-NEXT:    ret261  %tval = trunc <2 x i64> %val to <2 x i8>262  call void @llvm.masked.scatter.v2i8.v2p0(<2 x i8> %tval, <2 x ptr> %ptrs, i32 1, <2 x i1> %m)263  ret void264}265 266define void @mscatter_v4i8(<4 x i8> %val, <4 x ptr> %ptrs, <4 x i1> %m) {267; RV32-LABEL: mscatter_v4i8:268; RV32:       # %bb.0:269; RV32-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma270; RV32-NEXT:    vsoxei32.v v8, (zero), v9, v0.t271; RV32-NEXT:    ret272;273; RV64V-LABEL: mscatter_v4i8:274; RV64V:       # %bb.0:275; RV64V-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma276; RV64V-NEXT:    vsoxei64.v v8, (zero), v10, v0.t277; RV64V-NEXT:    ret278;279; RV64ZVE32F-LABEL: mscatter_v4i8:280; RV64ZVE32F:       # %bb.0:281; RV64ZVE32F-NEXT:    ld a4, 8(a0)282; RV64ZVE32F-NEXT:    ld a2, 16(a0)283; RV64ZVE32F-NEXT:    ld a1, 24(a0)284; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma285; RV64ZVE32F-NEXT:    vmv.x.s a3, v0286; RV64ZVE32F-NEXT:    andi a5, a3, 1287; RV64ZVE32F-NEXT:    bnez a5, .LBB5_5288; RV64ZVE32F-NEXT:  # %bb.1: # %else289; RV64ZVE32F-NEXT:    andi a0, a3, 2290; RV64ZVE32F-NEXT:    bnez a0, .LBB5_6291; RV64ZVE32F-NEXT:  .LBB5_2: # %else2292; RV64ZVE32F-NEXT:    andi a0, a3, 4293; RV64ZVE32F-NEXT:    bnez a0, .LBB5_7294; RV64ZVE32F-NEXT:  .LBB5_3: # %else4295; RV64ZVE32F-NEXT:    andi a3, a3, 8296; RV64ZVE32F-NEXT:    bnez a3, .LBB5_8297; RV64ZVE32F-NEXT:  .LBB5_4: # %else6298; RV64ZVE32F-NEXT:    ret299; RV64ZVE32F-NEXT:  .LBB5_5: # %cond.store300; RV64ZVE32F-NEXT:    ld a0, 0(a0)301; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma302; RV64ZVE32F-NEXT:    vse8.v v8, (a0)303; RV64ZVE32F-NEXT:    andi a0, a3, 2304; RV64ZVE32F-NEXT:    beqz a0, .LBB5_2305; RV64ZVE32F-NEXT:  .LBB5_6: # %cond.store1306; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma307; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 1308; RV64ZVE32F-NEXT:    vse8.v v9, (a4)309; RV64ZVE32F-NEXT:    andi a0, a3, 4310; RV64ZVE32F-NEXT:    beqz a0, .LBB5_3311; RV64ZVE32F-NEXT:  .LBB5_7: # %cond.store3312; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma313; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 2314; RV64ZVE32F-NEXT:    vse8.v v9, (a2)315; RV64ZVE32F-NEXT:    andi a3, a3, 8316; RV64ZVE32F-NEXT:    beqz a3, .LBB5_4317; RV64ZVE32F-NEXT:  .LBB5_8: # %cond.store5318; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma319; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 3320; RV64ZVE32F-NEXT:    vse8.v v8, (a1)321; RV64ZVE32F-NEXT:    ret322  call void @llvm.masked.scatter.v4i8.v4p0(<4 x i8> %val, <4 x ptr> %ptrs, i32 1, <4 x i1> %m)323  ret void324}325 326define void @mscatter_truemask_v4i8(<4 x i8> %val, <4 x ptr> %ptrs) {327; RV32-LABEL: mscatter_truemask_v4i8:328; RV32:       # %bb.0:329; RV32-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma330; RV32-NEXT:    vsoxei32.v v8, (zero), v9331; RV32-NEXT:    ret332;333; RV64V-LABEL: mscatter_truemask_v4i8:334; RV64V:       # %bb.0:335; RV64V-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma336; RV64V-NEXT:    vsoxei64.v v8, (zero), v10337; RV64V-NEXT:    ret338;339; RV64ZVE32F-LABEL: mscatter_truemask_v4i8:340; RV64ZVE32F:       # %bb.0:341; RV64ZVE32F-NEXT:    ld a1, 0(a0)342; RV64ZVE32F-NEXT:    ld a2, 8(a0)343; RV64ZVE32F-NEXT:    ld a3, 16(a0)344; RV64ZVE32F-NEXT:    ld a0, 24(a0)345; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma346; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 1347; RV64ZVE32F-NEXT:    vse8.v v8, (a1)348; RV64ZVE32F-NEXT:    vse8.v v9, (a2)349; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 2350; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 3351; RV64ZVE32F-NEXT:    vse8.v v9, (a3)352; RV64ZVE32F-NEXT:    vse8.v v8, (a0)353; RV64ZVE32F-NEXT:    ret354  call void @llvm.masked.scatter.v4i8.v4p0(<4 x i8> %val, <4 x ptr> %ptrs, i32 1, <4 x i1> splat (i1 1))355  ret void356}357 358define void @mscatter_falsemask_v4i8(<4 x i8> %val, <4 x ptr> %ptrs) {359; CHECK-LABEL: mscatter_falsemask_v4i8:360; CHECK:       # %bb.0:361; CHECK-NEXT:    ret362  call void @llvm.masked.scatter.v4i8.v4p0(<4 x i8> %val, <4 x ptr> %ptrs, i32 1, <4 x i1> zeroinitializer)363  ret void364}365 366define void @mscatter_v8i8(<8 x i8> %val, <8 x ptr> %ptrs, <8 x i1> %m) {367; RV32-LABEL: mscatter_v8i8:368; RV32:       # %bb.0:369; RV32-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma370; RV32-NEXT:    vsoxei32.v v8, (zero), v10, v0.t371; RV32-NEXT:    ret372;373; RV64V-LABEL: mscatter_v8i8:374; RV64V:       # %bb.0:375; RV64V-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma376; RV64V-NEXT:    vsoxei64.v v8, (zero), v12, v0.t377; RV64V-NEXT:    ret378;379; RV64ZVE32F-LABEL: mscatter_v8i8:380; RV64ZVE32F:       # %bb.0:381; RV64ZVE32F-NEXT:    ld a3, 40(a0)382; RV64ZVE32F-NEXT:    ld a2, 48(a0)383; RV64ZVE32F-NEXT:    ld a1, 56(a0)384; RV64ZVE32F-NEXT:    ld t0, 8(a0)385; RV64ZVE32F-NEXT:    ld a7, 16(a0)386; RV64ZVE32F-NEXT:    ld a6, 24(a0)387; RV64ZVE32F-NEXT:    ld a5, 32(a0)388; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma389; RV64ZVE32F-NEXT:    vmv.x.s a4, v0390; RV64ZVE32F-NEXT:    andi t1, a4, 1391; RV64ZVE32F-NEXT:    bnez t1, .LBB8_9392; RV64ZVE32F-NEXT:  # %bb.1: # %else393; RV64ZVE32F-NEXT:    andi a0, a4, 2394; RV64ZVE32F-NEXT:    bnez a0, .LBB8_10395; RV64ZVE32F-NEXT:  .LBB8_2: # %else2396; RV64ZVE32F-NEXT:    andi a0, a4, 4397; RV64ZVE32F-NEXT:    bnez a0, .LBB8_11398; RV64ZVE32F-NEXT:  .LBB8_3: # %else4399; RV64ZVE32F-NEXT:    andi a0, a4, 8400; RV64ZVE32F-NEXT:    bnez a0, .LBB8_12401; RV64ZVE32F-NEXT:  .LBB8_4: # %else6402; RV64ZVE32F-NEXT:    andi a0, a4, 16403; RV64ZVE32F-NEXT:    bnez a0, .LBB8_13404; RV64ZVE32F-NEXT:  .LBB8_5: # %else8405; RV64ZVE32F-NEXT:    andi a0, a4, 32406; RV64ZVE32F-NEXT:    bnez a0, .LBB8_14407; RV64ZVE32F-NEXT:  .LBB8_6: # %else10408; RV64ZVE32F-NEXT:    andi a0, a4, 64409; RV64ZVE32F-NEXT:    bnez a0, .LBB8_15410; RV64ZVE32F-NEXT:  .LBB8_7: # %else12411; RV64ZVE32F-NEXT:    andi a0, a4, -128412; RV64ZVE32F-NEXT:    bnez a0, .LBB8_16413; RV64ZVE32F-NEXT:  .LBB8_8: # %else14414; RV64ZVE32F-NEXT:    ret415; RV64ZVE32F-NEXT:  .LBB8_9: # %cond.store416; RV64ZVE32F-NEXT:    ld a0, 0(a0)417; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf2, ta, ma418; RV64ZVE32F-NEXT:    vse8.v v8, (a0)419; RV64ZVE32F-NEXT:    andi a0, a4, 2420; RV64ZVE32F-NEXT:    beqz a0, .LBB8_2421; RV64ZVE32F-NEXT:  .LBB8_10: # %cond.store1422; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf2, ta, ma423; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 1424; RV64ZVE32F-NEXT:    vse8.v v9, (t0)425; RV64ZVE32F-NEXT:    andi a0, a4, 4426; RV64ZVE32F-NEXT:    beqz a0, .LBB8_3427; RV64ZVE32F-NEXT:  .LBB8_11: # %cond.store3428; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf2, ta, ma429; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 2430; RV64ZVE32F-NEXT:    vse8.v v9, (a7)431; RV64ZVE32F-NEXT:    andi a0, a4, 8432; RV64ZVE32F-NEXT:    beqz a0, .LBB8_4433; RV64ZVE32F-NEXT:  .LBB8_12: # %cond.store5434; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf2, ta, ma435; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 3436; RV64ZVE32F-NEXT:    vse8.v v9, (a6)437; RV64ZVE32F-NEXT:    andi a0, a4, 16438; RV64ZVE32F-NEXT:    beqz a0, .LBB8_5439; RV64ZVE32F-NEXT:  .LBB8_13: # %cond.store7440; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf2, ta, ma441; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 4442; RV64ZVE32F-NEXT:    vse8.v v9, (a5)443; RV64ZVE32F-NEXT:    andi a0, a4, 32444; RV64ZVE32F-NEXT:    beqz a0, .LBB8_6445; RV64ZVE32F-NEXT:  .LBB8_14: # %cond.store9446; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf2, ta, ma447; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 5448; RV64ZVE32F-NEXT:    vse8.v v9, (a3)449; RV64ZVE32F-NEXT:    andi a0, a4, 64450; RV64ZVE32F-NEXT:    beqz a0, .LBB8_7451; RV64ZVE32F-NEXT:  .LBB8_15: # %cond.store11452; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf2, ta, ma453; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 6454; RV64ZVE32F-NEXT:    vse8.v v9, (a2)455; RV64ZVE32F-NEXT:    andi a0, a4, -128456; RV64ZVE32F-NEXT:    beqz a0, .LBB8_8457; RV64ZVE32F-NEXT:  .LBB8_16: # %cond.store13458; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf2, ta, ma459; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 7460; RV64ZVE32F-NEXT:    vse8.v v8, (a1)461; RV64ZVE32F-NEXT:    ret462  call void @llvm.masked.scatter.v8i8.v8p0(<8 x i8> %val, <8 x ptr> %ptrs, i32 1, <8 x i1> %m)463  ret void464}465 466define void @mscatter_baseidx_v8i8(<8 x i8> %val, ptr %base, <8 x i8> %idxs, <8 x i1> %m) {467; RV32-LABEL: mscatter_baseidx_v8i8:468; RV32:       # %bb.0:469; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma470; RV32-NEXT:    vsext.vf4 v10, v9471; RV32-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma472; RV32-NEXT:    vsoxei32.v v8, (a0), v10, v0.t473; RV32-NEXT:    ret474;475; RV64V-LABEL: mscatter_baseidx_v8i8:476; RV64V:       # %bb.0:477; RV64V-NEXT:    vsetivli zero, 8, e64, m4, ta, ma478; RV64V-NEXT:    vsext.vf8 v12, v9479; RV64V-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma480; RV64V-NEXT:    vsoxei64.v v8, (a0), v12, v0.t481; RV64V-NEXT:    ret482;483; RV64ZVE32F-LABEL: mscatter_baseidx_v8i8:484; RV64ZVE32F:       # %bb.0:485; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma486; RV64ZVE32F-NEXT:    vmv.x.s a1, v0487; RV64ZVE32F-NEXT:    andi a2, a1, 1488; RV64ZVE32F-NEXT:    beqz a2, .LBB9_2489; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store490; RV64ZVE32F-NEXT:    vmv.x.s a2, v9491; RV64ZVE32F-NEXT:    add a2, a0, a2492; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf2, ta, ma493; RV64ZVE32F-NEXT:    vse8.v v8, (a2)494; RV64ZVE32F-NEXT:  .LBB9_2: # %else495; RV64ZVE32F-NEXT:    andi a2, a1, 2496; RV64ZVE32F-NEXT:    beqz a2, .LBB9_4497; RV64ZVE32F-NEXT:  # %bb.3: # %cond.store1498; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma499; RV64ZVE32F-NEXT:    vslidedown.vi v10, v9, 1500; RV64ZVE32F-NEXT:    vmv.x.s a2, v10501; RV64ZVE32F-NEXT:    add a2, a0, a2502; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf2, ta, ma503; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 1504; RV64ZVE32F-NEXT:    vse8.v v10, (a2)505; RV64ZVE32F-NEXT:  .LBB9_4: # %else2506; RV64ZVE32F-NEXT:    andi a2, a1, 4507; RV64ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma508; RV64ZVE32F-NEXT:    vslidedown.vi v10, v9, 2509; RV64ZVE32F-NEXT:    beqz a2, .LBB9_6510; RV64ZVE32F-NEXT:  # %bb.5: # %cond.store3511; RV64ZVE32F-NEXT:    vmv.x.s a2, v10512; RV64ZVE32F-NEXT:    add a2, a0, a2513; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf2, ta, ma514; RV64ZVE32F-NEXT:    vslidedown.vi v11, v8, 2515; RV64ZVE32F-NEXT:    vse8.v v11, (a2)516; RV64ZVE32F-NEXT:  .LBB9_6: # %else4517; RV64ZVE32F-NEXT:    andi a2, a1, 8518; RV64ZVE32F-NEXT:    beqz a2, .LBB9_8519; RV64ZVE32F-NEXT:  # %bb.7: # %cond.store5520; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma521; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 1522; RV64ZVE32F-NEXT:    vmv.x.s a2, v10523; RV64ZVE32F-NEXT:    add a2, a0, a2524; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf2, ta, ma525; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 3526; RV64ZVE32F-NEXT:    vse8.v v10, (a2)527; RV64ZVE32F-NEXT:  .LBB9_8: # %else6528; RV64ZVE32F-NEXT:    andi a2, a1, 16529; RV64ZVE32F-NEXT:    vsetivli zero, 4, e8, mf2, ta, ma530; RV64ZVE32F-NEXT:    vslidedown.vi v9, v9, 4531; RV64ZVE32F-NEXT:    beqz a2, .LBB9_10532; RV64ZVE32F-NEXT:  # %bb.9: # %cond.store7533; RV64ZVE32F-NEXT:    vmv.x.s a2, v9534; RV64ZVE32F-NEXT:    add a2, a0, a2535; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 4536; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf2, ta, ma537; RV64ZVE32F-NEXT:    vse8.v v10, (a2)538; RV64ZVE32F-NEXT:  .LBB9_10: # %else8539; RV64ZVE32F-NEXT:    andi a2, a1, 32540; RV64ZVE32F-NEXT:    beqz a2, .LBB9_12541; RV64ZVE32F-NEXT:  # %bb.11: # %cond.store9542; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma543; RV64ZVE32F-NEXT:    vslidedown.vi v10, v9, 1544; RV64ZVE32F-NEXT:    vmv.x.s a2, v10545; RV64ZVE32F-NEXT:    add a2, a0, a2546; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf2, ta, ma547; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 5548; RV64ZVE32F-NEXT:    vse8.v v10, (a2)549; RV64ZVE32F-NEXT:  .LBB9_12: # %else10550; RV64ZVE32F-NEXT:    andi a2, a1, 64551; RV64ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma552; RV64ZVE32F-NEXT:    vslidedown.vi v9, v9, 2553; RV64ZVE32F-NEXT:    bnez a2, .LBB9_15554; RV64ZVE32F-NEXT:  # %bb.13: # %else12555; RV64ZVE32F-NEXT:    andi a1, a1, -128556; RV64ZVE32F-NEXT:    bnez a1, .LBB9_16557; RV64ZVE32F-NEXT:  .LBB9_14: # %else14558; RV64ZVE32F-NEXT:    ret559; RV64ZVE32F-NEXT:  .LBB9_15: # %cond.store11560; RV64ZVE32F-NEXT:    vmv.x.s a2, v9561; RV64ZVE32F-NEXT:    add a2, a0, a2562; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf2, ta, ma563; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 6564; RV64ZVE32F-NEXT:    vse8.v v10, (a2)565; RV64ZVE32F-NEXT:    andi a1, a1, -128566; RV64ZVE32F-NEXT:    beqz a1, .LBB9_14567; RV64ZVE32F-NEXT:  .LBB9_16: # %cond.store13568; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma569; RV64ZVE32F-NEXT:    vslidedown.vi v9, v9, 1570; RV64ZVE32F-NEXT:    vmv.x.s a1, v9571; RV64ZVE32F-NEXT:    add a0, a0, a1572; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf2, ta, ma573; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 7574; RV64ZVE32F-NEXT:    vse8.v v8, (a0)575; RV64ZVE32F-NEXT:    ret576  %ptrs = getelementptr inbounds i8, ptr %base, <8 x i8> %idxs577  call void @llvm.masked.scatter.v8i8.v8p0(<8 x i8> %val, <8 x ptr> %ptrs, i32 1, <8 x i1> %m)578  ret void579}580 581define void @mscatter_v1i16(<1 x i16> %val, <1 x ptr> %ptrs, <1 x i1> %m) {582; RV32V-LABEL: mscatter_v1i16:583; RV32V:       # %bb.0:584; RV32V-NEXT:    vsetivli zero, 1, e16, mf4, ta, ma585; RV32V-NEXT:    vsoxei32.v v8, (zero), v9, v0.t586; RV32V-NEXT:    ret587;588; RV64V-LABEL: mscatter_v1i16:589; RV64V:       # %bb.0:590; RV64V-NEXT:    vsetivli zero, 1, e16, mf4, ta, ma591; RV64V-NEXT:    vsoxei64.v v8, (zero), v9, v0.t592; RV64V-NEXT:    ret593;594; RV32ZVE32F-LABEL: mscatter_v1i16:595; RV32ZVE32F:       # %bb.0:596; RV32ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma597; RV32ZVE32F-NEXT:    vsoxei32.v v8, (zero), v9, v0.t598; RV32ZVE32F-NEXT:    ret599;600; RV64ZVE32F-LABEL: mscatter_v1i16:601; RV64ZVE32F:       # %bb.0:602; RV64ZVE32F-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma603; RV64ZVE32F-NEXT:    vfirst.m a1, v0604; RV64ZVE32F-NEXT:    bnez a1, .LBB10_2605; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store606; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma607; RV64ZVE32F-NEXT:    vse16.v v8, (a0)608; RV64ZVE32F-NEXT:  .LBB10_2: # %else609; RV64ZVE32F-NEXT:    ret610  call void @llvm.masked.scatter.v1i16.v1p0(<1 x i16> %val, <1 x ptr> %ptrs, i32 2, <1 x i1> %m)611  ret void612}613 614define void @mscatter_v2i16(<2 x i16> %val, <2 x ptr> %ptrs, <2 x i1> %m) {615; RV32V-LABEL: mscatter_v2i16:616; RV32V:       # %bb.0:617; RV32V-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma618; RV32V-NEXT:    vsoxei32.v v8, (zero), v9, v0.t619; RV32V-NEXT:    ret620;621; RV64V-LABEL: mscatter_v2i16:622; RV64V:       # %bb.0:623; RV64V-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma624; RV64V-NEXT:    vsoxei64.v v8, (zero), v9, v0.t625; RV64V-NEXT:    ret626;627; RV32ZVE32F-LABEL: mscatter_v2i16:628; RV32ZVE32F:       # %bb.0:629; RV32ZVE32F-NEXT:    vsetivli zero, 2, e16, mf2, ta, ma630; RV32ZVE32F-NEXT:    vsoxei32.v v8, (zero), v9, v0.t631; RV32ZVE32F-NEXT:    ret632;633; RV64ZVE32F-LABEL: mscatter_v2i16:634; RV64ZVE32F:       # %bb.0:635; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma636; RV64ZVE32F-NEXT:    vmv.x.s a2, v0637; RV64ZVE32F-NEXT:    andi a3, a2, 1638; RV64ZVE32F-NEXT:    bnez a3, .LBB11_3639; RV64ZVE32F-NEXT:  # %bb.1: # %else640; RV64ZVE32F-NEXT:    andi a2, a2, 2641; RV64ZVE32F-NEXT:    bnez a2, .LBB11_4642; RV64ZVE32F-NEXT:  .LBB11_2: # %else2643; RV64ZVE32F-NEXT:    ret644; RV64ZVE32F-NEXT:  .LBB11_3: # %cond.store645; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma646; RV64ZVE32F-NEXT:    vse16.v v8, (a0)647; RV64ZVE32F-NEXT:    andi a2, a2, 2648; RV64ZVE32F-NEXT:    beqz a2, .LBB11_2649; RV64ZVE32F-NEXT:  .LBB11_4: # %cond.store1650; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma651; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 1652; RV64ZVE32F-NEXT:    vse16.v v8, (a1)653; RV64ZVE32F-NEXT:    ret654  call void @llvm.masked.scatter.v2i16.v2p0(<2 x i16> %val, <2 x ptr> %ptrs, i32 2, <2 x i1> %m)655  ret void656}657 658define void @mscatter_v2i32_truncstore_v2i16(<2 x i32> %val, <2 x ptr> %ptrs, <2 x i1> %m) {659; RV32V-LABEL: mscatter_v2i32_truncstore_v2i16:660; RV32V:       # %bb.0:661; RV32V-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma662; RV32V-NEXT:    vnsrl.wi v8, v8, 0663; RV32V-NEXT:    vsoxei32.v v8, (zero), v9, v0.t664; RV32V-NEXT:    ret665;666; RV64V-LABEL: mscatter_v2i32_truncstore_v2i16:667; RV64V:       # %bb.0:668; RV64V-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma669; RV64V-NEXT:    vnsrl.wi v8, v8, 0670; RV64V-NEXT:    vsoxei64.v v8, (zero), v9, v0.t671; RV64V-NEXT:    ret672;673; RV32ZVE32F-LABEL: mscatter_v2i32_truncstore_v2i16:674; RV32ZVE32F:       # %bb.0:675; RV32ZVE32F-NEXT:    vsetivli zero, 2, e16, mf2, ta, ma676; RV32ZVE32F-NEXT:    vnsrl.wi v8, v8, 0677; RV32ZVE32F-NEXT:    vsoxei32.v v8, (zero), v9, v0.t678; RV32ZVE32F-NEXT:    ret679;680; RV64ZVE32F-LABEL: mscatter_v2i32_truncstore_v2i16:681; RV64ZVE32F:       # %bb.0:682; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma683; RV64ZVE32F-NEXT:    vmv.x.s a2, v0684; RV64ZVE32F-NEXT:    andi a3, a2, 1685; RV64ZVE32F-NEXT:    vsetivli zero, 2, e16, mf2, ta, ma686; RV64ZVE32F-NEXT:    vnsrl.wi v8, v8, 0687; RV64ZVE32F-NEXT:    bnez a3, .LBB12_3688; RV64ZVE32F-NEXT:  # %bb.1: # %else689; RV64ZVE32F-NEXT:    andi a2, a2, 2690; RV64ZVE32F-NEXT:    bnez a2, .LBB12_4691; RV64ZVE32F-NEXT:  .LBB12_2: # %else2692; RV64ZVE32F-NEXT:    ret693; RV64ZVE32F-NEXT:  .LBB12_3: # %cond.store694; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma695; RV64ZVE32F-NEXT:    vse16.v v8, (a0)696; RV64ZVE32F-NEXT:    andi a2, a2, 2697; RV64ZVE32F-NEXT:    beqz a2, .LBB12_2698; RV64ZVE32F-NEXT:  .LBB12_4: # %cond.store1699; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma700; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 1701; RV64ZVE32F-NEXT:    vse16.v v8, (a1)702; RV64ZVE32F-NEXT:    ret703  %tval = trunc <2 x i32> %val to <2 x i16>704  call void @llvm.masked.scatter.v2i16.v2p0(<2 x i16> %tval, <2 x ptr> %ptrs, i32 2, <2 x i1> %m)705  ret void706}707 708define void @mscatter_v2i64_truncstore_v2i16(<2 x i64> %val, <2 x ptr> %ptrs, <2 x i1> %m) {709; RV32V-LABEL: mscatter_v2i64_truncstore_v2i16:710; RV32V:       # %bb.0:711; RV32V-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma712; RV32V-NEXT:    vnsrl.wi v8, v8, 0713; RV32V-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma714; RV32V-NEXT:    vnsrl.wi v8, v8, 0715; RV32V-NEXT:    vsoxei32.v v8, (zero), v9, v0.t716; RV32V-NEXT:    ret717;718; RV64V-LABEL: mscatter_v2i64_truncstore_v2i16:719; RV64V:       # %bb.0:720; RV64V-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma721; RV64V-NEXT:    vnsrl.wi v8, v8, 0722; RV64V-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma723; RV64V-NEXT:    vnsrl.wi v8, v8, 0724; RV64V-NEXT:    vsoxei64.v v8, (zero), v9, v0.t725; RV64V-NEXT:    ret726;727; RV32ZVE32F-LABEL: mscatter_v2i64_truncstore_v2i16:728; RV32ZVE32F:       # %bb.0:729; RV32ZVE32F-NEXT:    lw a1, 8(a0)730; RV32ZVE32F-NEXT:    lw a0, 0(a0)731; RV32ZVE32F-NEXT:    vsetivli zero, 2, e16, mf2, ta, ma732; RV32ZVE32F-NEXT:    vmv.s.x v9, a1733; RV32ZVE32F-NEXT:    vmv.s.x v10, a0734; RV32ZVE32F-NEXT:    vslideup.vi v10, v9, 1735; RV32ZVE32F-NEXT:    vsoxei32.v v10, (zero), v8, v0.t736; RV32ZVE32F-NEXT:    ret737;738; RV64ZVE32F-LABEL: mscatter_v2i64_truncstore_v2i16:739; RV64ZVE32F:       # %bb.0:740; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma741; RV64ZVE32F-NEXT:    vmv.s.x v9, a1742; RV64ZVE32F-NEXT:    vmv.s.x v8, a0743; RV64ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma744; RV64ZVE32F-NEXT:    vmv.x.s a0, v0745; RV64ZVE32F-NEXT:    andi a1, a0, 1746; RV64ZVE32F-NEXT:    vsetivli zero, 2, e16, mf2, ta, ma747; RV64ZVE32F-NEXT:    vslideup.vi v8, v9, 1748; RV64ZVE32F-NEXT:    bnez a1, .LBB13_3749; RV64ZVE32F-NEXT:  # %bb.1: # %else750; RV64ZVE32F-NEXT:    andi a0, a0, 2751; RV64ZVE32F-NEXT:    bnez a0, .LBB13_4752; RV64ZVE32F-NEXT:  .LBB13_2: # %else2753; RV64ZVE32F-NEXT:    ret754; RV64ZVE32F-NEXT:  .LBB13_3: # %cond.store755; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma756; RV64ZVE32F-NEXT:    vse16.v v8, (a2)757; RV64ZVE32F-NEXT:    andi a0, a0, 2758; RV64ZVE32F-NEXT:    beqz a0, .LBB13_2759; RV64ZVE32F-NEXT:  .LBB13_4: # %cond.store1760; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma761; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 1762; RV64ZVE32F-NEXT:    vse16.v v8, (a3)763; RV64ZVE32F-NEXT:    ret764  %tval = trunc <2 x i64> %val to <2 x i16>765  call void @llvm.masked.scatter.v2i16.v2p0(<2 x i16> %tval, <2 x ptr> %ptrs, i32 2, <2 x i1> %m)766  ret void767}768 769define void @mscatter_v4i16(<4 x i16> %val, <4 x ptr> %ptrs, <4 x i1> %m) {770; RV32-LABEL: mscatter_v4i16:771; RV32:       # %bb.0:772; RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma773; RV32-NEXT:    vsoxei32.v v8, (zero), v9, v0.t774; RV32-NEXT:    ret775;776; RV64V-LABEL: mscatter_v4i16:777; RV64V:       # %bb.0:778; RV64V-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma779; RV64V-NEXT:    vsoxei64.v v8, (zero), v10, v0.t780; RV64V-NEXT:    ret781;782; RV64ZVE32F-LABEL: mscatter_v4i16:783; RV64ZVE32F:       # %bb.0:784; RV64ZVE32F-NEXT:    ld a4, 8(a0)785; RV64ZVE32F-NEXT:    ld a2, 16(a0)786; RV64ZVE32F-NEXT:    ld a1, 24(a0)787; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma788; RV64ZVE32F-NEXT:    vmv.x.s a3, v0789; RV64ZVE32F-NEXT:    andi a5, a3, 1790; RV64ZVE32F-NEXT:    bnez a5, .LBB14_5791; RV64ZVE32F-NEXT:  # %bb.1: # %else792; RV64ZVE32F-NEXT:    andi a0, a3, 2793; RV64ZVE32F-NEXT:    bnez a0, .LBB14_6794; RV64ZVE32F-NEXT:  .LBB14_2: # %else2795; RV64ZVE32F-NEXT:    andi a0, a3, 4796; RV64ZVE32F-NEXT:    bnez a0, .LBB14_7797; RV64ZVE32F-NEXT:  .LBB14_3: # %else4798; RV64ZVE32F-NEXT:    andi a3, a3, 8799; RV64ZVE32F-NEXT:    bnez a3, .LBB14_8800; RV64ZVE32F-NEXT:  .LBB14_4: # %else6801; RV64ZVE32F-NEXT:    ret802; RV64ZVE32F-NEXT:  .LBB14_5: # %cond.store803; RV64ZVE32F-NEXT:    ld a0, 0(a0)804; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma805; RV64ZVE32F-NEXT:    vse16.v v8, (a0)806; RV64ZVE32F-NEXT:    andi a0, a3, 2807; RV64ZVE32F-NEXT:    beqz a0, .LBB14_2808; RV64ZVE32F-NEXT:  .LBB14_6: # %cond.store1809; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma810; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 1811; RV64ZVE32F-NEXT:    vse16.v v9, (a4)812; RV64ZVE32F-NEXT:    andi a0, a3, 4813; RV64ZVE32F-NEXT:    beqz a0, .LBB14_3814; RV64ZVE32F-NEXT:  .LBB14_7: # %cond.store3815; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma816; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 2817; RV64ZVE32F-NEXT:    vse16.v v9, (a2)818; RV64ZVE32F-NEXT:    andi a3, a3, 8819; RV64ZVE32F-NEXT:    beqz a3, .LBB14_4820; RV64ZVE32F-NEXT:  .LBB14_8: # %cond.store5821; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma822; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 3823; RV64ZVE32F-NEXT:    vse16.v v8, (a1)824; RV64ZVE32F-NEXT:    ret825  call void @llvm.masked.scatter.v4i16.v4p0(<4 x i16> %val, <4 x ptr> %ptrs, i32 2, <4 x i1> %m)826  ret void827}828 829define void @mscatter_truemask_v4i16(<4 x i16> %val, <4 x ptr> %ptrs) {830; RV32-LABEL: mscatter_truemask_v4i16:831; RV32:       # %bb.0:832; RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma833; RV32-NEXT:    vsoxei32.v v8, (zero), v9834; RV32-NEXT:    ret835;836; RV64V-LABEL: mscatter_truemask_v4i16:837; RV64V:       # %bb.0:838; RV64V-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma839; RV64V-NEXT:    vsoxei64.v v8, (zero), v10840; RV64V-NEXT:    ret841;842; RV64ZVE32F-LABEL: mscatter_truemask_v4i16:843; RV64ZVE32F:       # %bb.0:844; RV64ZVE32F-NEXT:    ld a1, 0(a0)845; RV64ZVE32F-NEXT:    ld a2, 8(a0)846; RV64ZVE32F-NEXT:    ld a3, 16(a0)847; RV64ZVE32F-NEXT:    ld a0, 24(a0)848; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma849; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 1850; RV64ZVE32F-NEXT:    vse16.v v8, (a1)851; RV64ZVE32F-NEXT:    vse16.v v9, (a2)852; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 2853; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 3854; RV64ZVE32F-NEXT:    vse16.v v9, (a3)855; RV64ZVE32F-NEXT:    vse16.v v8, (a0)856; RV64ZVE32F-NEXT:    ret857  call void @llvm.masked.scatter.v4i16.v4p0(<4 x i16> %val, <4 x ptr> %ptrs, i32 2, <4 x i1> splat (i1 1))858  ret void859}860 861define void @mscatter_falsemask_v4i16(<4 x i16> %val, <4 x ptr> %ptrs) {862; CHECK-LABEL: mscatter_falsemask_v4i16:863; CHECK:       # %bb.0:864; CHECK-NEXT:    ret865  call void @llvm.masked.scatter.v4i16.v4p0(<4 x i16> %val, <4 x ptr> %ptrs, i32 2, <4 x i1> zeroinitializer)866  ret void867}868 869define void @mscatter_v8i16(<8 x i16> %val, <8 x ptr> %ptrs, <8 x i1> %m) {870; RV32-LABEL: mscatter_v8i16:871; RV32:       # %bb.0:872; RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma873; RV32-NEXT:    vsoxei32.v v8, (zero), v10, v0.t874; RV32-NEXT:    ret875;876; RV64V-LABEL: mscatter_v8i16:877; RV64V:       # %bb.0:878; RV64V-NEXT:    vsetivli zero, 8, e16, m1, ta, ma879; RV64V-NEXT:    vsoxei64.v v8, (zero), v12, v0.t880; RV64V-NEXT:    ret881;882; RV64ZVE32F-LABEL: mscatter_v8i16:883; RV64ZVE32F:       # %bb.0:884; RV64ZVE32F-NEXT:    ld a3, 40(a0)885; RV64ZVE32F-NEXT:    ld a2, 48(a0)886; RV64ZVE32F-NEXT:    ld a1, 56(a0)887; RV64ZVE32F-NEXT:    ld t0, 8(a0)888; RV64ZVE32F-NEXT:    ld a7, 16(a0)889; RV64ZVE32F-NEXT:    ld a6, 24(a0)890; RV64ZVE32F-NEXT:    ld a5, 32(a0)891; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma892; RV64ZVE32F-NEXT:    vmv.x.s a4, v0893; RV64ZVE32F-NEXT:    andi t1, a4, 1894; RV64ZVE32F-NEXT:    bnez t1, .LBB17_9895; RV64ZVE32F-NEXT:  # %bb.1: # %else896; RV64ZVE32F-NEXT:    andi a0, a4, 2897; RV64ZVE32F-NEXT:    bnez a0, .LBB17_10898; RV64ZVE32F-NEXT:  .LBB17_2: # %else2899; RV64ZVE32F-NEXT:    andi a0, a4, 4900; RV64ZVE32F-NEXT:    bnez a0, .LBB17_11901; RV64ZVE32F-NEXT:  .LBB17_3: # %else4902; RV64ZVE32F-NEXT:    andi a0, a4, 8903; RV64ZVE32F-NEXT:    bnez a0, .LBB17_12904; RV64ZVE32F-NEXT:  .LBB17_4: # %else6905; RV64ZVE32F-NEXT:    andi a0, a4, 16906; RV64ZVE32F-NEXT:    bnez a0, .LBB17_13907; RV64ZVE32F-NEXT:  .LBB17_5: # %else8908; RV64ZVE32F-NEXT:    andi a0, a4, 32909; RV64ZVE32F-NEXT:    bnez a0, .LBB17_14910; RV64ZVE32F-NEXT:  .LBB17_6: # %else10911; RV64ZVE32F-NEXT:    andi a0, a4, 64912; RV64ZVE32F-NEXT:    bnez a0, .LBB17_15913; RV64ZVE32F-NEXT:  .LBB17_7: # %else12914; RV64ZVE32F-NEXT:    andi a0, a4, -128915; RV64ZVE32F-NEXT:    bnez a0, .LBB17_16916; RV64ZVE32F-NEXT:  .LBB17_8: # %else14917; RV64ZVE32F-NEXT:    ret918; RV64ZVE32F-NEXT:  .LBB17_9: # %cond.store919; RV64ZVE32F-NEXT:    ld a0, 0(a0)920; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma921; RV64ZVE32F-NEXT:    vse16.v v8, (a0)922; RV64ZVE32F-NEXT:    andi a0, a4, 2923; RV64ZVE32F-NEXT:    beqz a0, .LBB17_2924; RV64ZVE32F-NEXT:  .LBB17_10: # %cond.store1925; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma926; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 1927; RV64ZVE32F-NEXT:    vse16.v v9, (t0)928; RV64ZVE32F-NEXT:    andi a0, a4, 4929; RV64ZVE32F-NEXT:    beqz a0, .LBB17_3930; RV64ZVE32F-NEXT:  .LBB17_11: # %cond.store3931; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma932; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 2933; RV64ZVE32F-NEXT:    vse16.v v9, (a7)934; RV64ZVE32F-NEXT:    andi a0, a4, 8935; RV64ZVE32F-NEXT:    beqz a0, .LBB17_4936; RV64ZVE32F-NEXT:  .LBB17_12: # %cond.store5937; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma938; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 3939; RV64ZVE32F-NEXT:    vse16.v v9, (a6)940; RV64ZVE32F-NEXT:    andi a0, a4, 16941; RV64ZVE32F-NEXT:    beqz a0, .LBB17_5942; RV64ZVE32F-NEXT:  .LBB17_13: # %cond.store7943; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma944; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 4945; RV64ZVE32F-NEXT:    vse16.v v9, (a5)946; RV64ZVE32F-NEXT:    andi a0, a4, 32947; RV64ZVE32F-NEXT:    beqz a0, .LBB17_6948; RV64ZVE32F-NEXT:  .LBB17_14: # %cond.store9949; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma950; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 5951; RV64ZVE32F-NEXT:    vse16.v v9, (a3)952; RV64ZVE32F-NEXT:    andi a0, a4, 64953; RV64ZVE32F-NEXT:    beqz a0, .LBB17_7954; RV64ZVE32F-NEXT:  .LBB17_15: # %cond.store11955; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma956; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 6957; RV64ZVE32F-NEXT:    vse16.v v9, (a2)958; RV64ZVE32F-NEXT:    andi a0, a4, -128959; RV64ZVE32F-NEXT:    beqz a0, .LBB17_8960; RV64ZVE32F-NEXT:  .LBB17_16: # %cond.store13961; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma962; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 7963; RV64ZVE32F-NEXT:    vse16.v v8, (a1)964; RV64ZVE32F-NEXT:    ret965  call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> %val, <8 x ptr> %ptrs, i32 2, <8 x i1> %m)966  ret void967}968 969define void @mscatter_baseidx_v8i8_v8i16(<8 x i16> %val, ptr %base, <8 x i8> %idxs, <8 x i1> %m) {970; RV32-LABEL: mscatter_baseidx_v8i8_v8i16:971; RV32:       # %bb.0:972; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma973; RV32-NEXT:    vsext.vf4 v10, v9974; RV32-NEXT:    vadd.vv v10, v10, v10975; RV32-NEXT:    vsetvli zero, zero, e16, m1, ta, ma976; RV32-NEXT:    vsoxei32.v v8, (a0), v10, v0.t977; RV32-NEXT:    ret978;979; RV64V-LABEL: mscatter_baseidx_v8i8_v8i16:980; RV64V:       # %bb.0:981; RV64V-NEXT:    vsetivli zero, 8, e64, m4, ta, ma982; RV64V-NEXT:    vsext.vf8 v12, v9983; RV64V-NEXT:    vadd.vv v12, v12, v12984; RV64V-NEXT:    vsetvli zero, zero, e16, m1, ta, ma985; RV64V-NEXT:    vsoxei64.v v8, (a0), v12, v0.t986; RV64V-NEXT:    ret987;988; RV64ZVE32F-LABEL: mscatter_baseidx_v8i8_v8i16:989; RV64ZVE32F:       # %bb.0:990; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma991; RV64ZVE32F-NEXT:    vmv.x.s a1, v0992; RV64ZVE32F-NEXT:    andi a2, a1, 1993; RV64ZVE32F-NEXT:    beqz a2, .LBB18_2994; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store995; RV64ZVE32F-NEXT:    vmv.x.s a2, v9996; RV64ZVE32F-NEXT:    slli a2, a2, 1997; RV64ZVE32F-NEXT:    add a2, a0, a2998; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma999; RV64ZVE32F-NEXT:    vse16.v v8, (a2)1000; RV64ZVE32F-NEXT:  .LBB18_2: # %else1001; RV64ZVE32F-NEXT:    andi a2, a1, 21002; RV64ZVE32F-NEXT:    beqz a2, .LBB18_41003; RV64ZVE32F-NEXT:  # %bb.3: # %cond.store11004; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma1005; RV64ZVE32F-NEXT:    vslidedown.vi v10, v9, 11006; RV64ZVE32F-NEXT:    vmv.x.s a2, v101007; RV64ZVE32F-NEXT:    slli a2, a2, 11008; RV64ZVE32F-NEXT:    add a2, a0, a21009; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma1010; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 11011; RV64ZVE32F-NEXT:    vse16.v v10, (a2)1012; RV64ZVE32F-NEXT:  .LBB18_4: # %else21013; RV64ZVE32F-NEXT:    andi a2, a1, 41014; RV64ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma1015; RV64ZVE32F-NEXT:    vslidedown.vi v10, v9, 21016; RV64ZVE32F-NEXT:    beqz a2, .LBB18_61017; RV64ZVE32F-NEXT:  # %bb.5: # %cond.store31018; RV64ZVE32F-NEXT:    vmv.x.s a2, v101019; RV64ZVE32F-NEXT:    slli a2, a2, 11020; RV64ZVE32F-NEXT:    add a2, a0, a21021; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma1022; RV64ZVE32F-NEXT:    vslidedown.vi v11, v8, 21023; RV64ZVE32F-NEXT:    vse16.v v11, (a2)1024; RV64ZVE32F-NEXT:  .LBB18_6: # %else41025; RV64ZVE32F-NEXT:    andi a2, a1, 81026; RV64ZVE32F-NEXT:    beqz a2, .LBB18_81027; RV64ZVE32F-NEXT:  # %bb.7: # %cond.store51028; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma1029; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 11030; RV64ZVE32F-NEXT:    vmv.x.s a2, v101031; RV64ZVE32F-NEXT:    slli a2, a2, 11032; RV64ZVE32F-NEXT:    add a2, a0, a21033; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma1034; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 31035; RV64ZVE32F-NEXT:    vse16.v v10, (a2)1036; RV64ZVE32F-NEXT:  .LBB18_8: # %else61037; RV64ZVE32F-NEXT:    andi a2, a1, 161038; RV64ZVE32F-NEXT:    vsetivli zero, 4, e8, mf2, ta, ma1039; RV64ZVE32F-NEXT:    vslidedown.vi v9, v9, 41040; RV64ZVE32F-NEXT:    beqz a2, .LBB18_101041; RV64ZVE32F-NEXT:  # %bb.9: # %cond.store71042; RV64ZVE32F-NEXT:    vmv.x.s a2, v91043; RV64ZVE32F-NEXT:    slli a2, a2, 11044; RV64ZVE32F-NEXT:    add a2, a0, a21045; RV64ZVE32F-NEXT:    vsetvli zero, zero, e16, m1, ta, ma1046; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 41047; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma1048; RV64ZVE32F-NEXT:    vse16.v v10, (a2)1049; RV64ZVE32F-NEXT:  .LBB18_10: # %else81050; RV64ZVE32F-NEXT:    andi a2, a1, 321051; RV64ZVE32F-NEXT:    beqz a2, .LBB18_121052; RV64ZVE32F-NEXT:  # %bb.11: # %cond.store91053; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma1054; RV64ZVE32F-NEXT:    vslidedown.vi v10, v9, 11055; RV64ZVE32F-NEXT:    vmv.x.s a2, v101056; RV64ZVE32F-NEXT:    slli a2, a2, 11057; RV64ZVE32F-NEXT:    add a2, a0, a21058; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma1059; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 51060; RV64ZVE32F-NEXT:    vse16.v v10, (a2)1061; RV64ZVE32F-NEXT:  .LBB18_12: # %else101062; RV64ZVE32F-NEXT:    andi a2, a1, 641063; RV64ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma1064; RV64ZVE32F-NEXT:    vslidedown.vi v9, v9, 21065; RV64ZVE32F-NEXT:    bnez a2, .LBB18_151066; RV64ZVE32F-NEXT:  # %bb.13: # %else121067; RV64ZVE32F-NEXT:    andi a1, a1, -1281068; RV64ZVE32F-NEXT:    bnez a1, .LBB18_161069; RV64ZVE32F-NEXT:  .LBB18_14: # %else141070; RV64ZVE32F-NEXT:    ret1071; RV64ZVE32F-NEXT:  .LBB18_15: # %cond.store111072; RV64ZVE32F-NEXT:    vmv.x.s a2, v91073; RV64ZVE32F-NEXT:    slli a2, a2, 11074; RV64ZVE32F-NEXT:    add a2, a0, a21075; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma1076; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 61077; RV64ZVE32F-NEXT:    vse16.v v10, (a2)1078; RV64ZVE32F-NEXT:    andi a1, a1, -1281079; RV64ZVE32F-NEXT:    beqz a1, .LBB18_141080; RV64ZVE32F-NEXT:  .LBB18_16: # %cond.store131081; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma1082; RV64ZVE32F-NEXT:    vslidedown.vi v9, v9, 11083; RV64ZVE32F-NEXT:    vmv.x.s a1, v91084; RV64ZVE32F-NEXT:    slli a1, a1, 11085; RV64ZVE32F-NEXT:    add a0, a0, a11086; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma1087; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 71088; RV64ZVE32F-NEXT:    vse16.v v8, (a0)1089; RV64ZVE32F-NEXT:    ret1090  %ptrs = getelementptr inbounds i16, ptr %base, <8 x i8> %idxs1091  call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> %val, <8 x ptr> %ptrs, i32 2, <8 x i1> %m)1092  ret void1093}1094 1095define void @mscatter_baseidx_sext_v8i8_v8i16(<8 x i16> %val, ptr %base, <8 x i8> %idxs, <8 x i1> %m) {1096; RV32-LABEL: mscatter_baseidx_sext_v8i8_v8i16:1097; RV32:       # %bb.0:1098; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma1099; RV32-NEXT:    vsext.vf4 v10, v91100; RV32-NEXT:    vadd.vv v10, v10, v101101; RV32-NEXT:    vsetvli zero, zero, e16, m1, ta, ma1102; RV32-NEXT:    vsoxei32.v v8, (a0), v10, v0.t1103; RV32-NEXT:    ret1104;1105; RV64V-LABEL: mscatter_baseidx_sext_v8i8_v8i16:1106; RV64V:       # %bb.0:1107; RV64V-NEXT:    vsetivli zero, 8, e64, m4, ta, ma1108; RV64V-NEXT:    vsext.vf8 v12, v91109; RV64V-NEXT:    vadd.vv v12, v12, v121110; RV64V-NEXT:    vsetvli zero, zero, e16, m1, ta, ma1111; RV64V-NEXT:    vsoxei64.v v8, (a0), v12, v0.t1112; RV64V-NEXT:    ret1113;1114; RV64ZVE32F-LABEL: mscatter_baseidx_sext_v8i8_v8i16:1115; RV64ZVE32F:       # %bb.0:1116; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma1117; RV64ZVE32F-NEXT:    vmv.x.s a1, v01118; RV64ZVE32F-NEXT:    andi a2, a1, 11119; RV64ZVE32F-NEXT:    beqz a2, .LBB19_21120; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store1121; RV64ZVE32F-NEXT:    vmv.x.s a2, v91122; RV64ZVE32F-NEXT:    slli a2, a2, 11123; RV64ZVE32F-NEXT:    add a2, a0, a21124; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma1125; RV64ZVE32F-NEXT:    vse16.v v8, (a2)1126; RV64ZVE32F-NEXT:  .LBB19_2: # %else1127; RV64ZVE32F-NEXT:    andi a2, a1, 21128; RV64ZVE32F-NEXT:    beqz a2, .LBB19_41129; RV64ZVE32F-NEXT:  # %bb.3: # %cond.store11130; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma1131; RV64ZVE32F-NEXT:    vslidedown.vi v10, v9, 11132; RV64ZVE32F-NEXT:    vmv.x.s a2, v101133; RV64ZVE32F-NEXT:    slli a2, a2, 11134; RV64ZVE32F-NEXT:    add a2, a0, a21135; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma1136; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 11137; RV64ZVE32F-NEXT:    vse16.v v10, (a2)1138; RV64ZVE32F-NEXT:  .LBB19_4: # %else21139; RV64ZVE32F-NEXT:    andi a2, a1, 41140; RV64ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma1141; RV64ZVE32F-NEXT:    vslidedown.vi v10, v9, 21142; RV64ZVE32F-NEXT:    beqz a2, .LBB19_61143; RV64ZVE32F-NEXT:  # %bb.5: # %cond.store31144; RV64ZVE32F-NEXT:    vmv.x.s a2, v101145; RV64ZVE32F-NEXT:    slli a2, a2, 11146; RV64ZVE32F-NEXT:    add a2, a0, a21147; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma1148; RV64ZVE32F-NEXT:    vslidedown.vi v11, v8, 21149; RV64ZVE32F-NEXT:    vse16.v v11, (a2)1150; RV64ZVE32F-NEXT:  .LBB19_6: # %else41151; RV64ZVE32F-NEXT:    andi a2, a1, 81152; RV64ZVE32F-NEXT:    beqz a2, .LBB19_81153; RV64ZVE32F-NEXT:  # %bb.7: # %cond.store51154; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma1155; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 11156; RV64ZVE32F-NEXT:    vmv.x.s a2, v101157; RV64ZVE32F-NEXT:    slli a2, a2, 11158; RV64ZVE32F-NEXT:    add a2, a0, a21159; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma1160; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 31161; RV64ZVE32F-NEXT:    vse16.v v10, (a2)1162; RV64ZVE32F-NEXT:  .LBB19_8: # %else61163; RV64ZVE32F-NEXT:    andi a2, a1, 161164; RV64ZVE32F-NEXT:    vsetivli zero, 4, e8, mf2, ta, ma1165; RV64ZVE32F-NEXT:    vslidedown.vi v9, v9, 41166; RV64ZVE32F-NEXT:    beqz a2, .LBB19_101167; RV64ZVE32F-NEXT:  # %bb.9: # %cond.store71168; RV64ZVE32F-NEXT:    vmv.x.s a2, v91169; RV64ZVE32F-NEXT:    slli a2, a2, 11170; RV64ZVE32F-NEXT:    add a2, a0, a21171; RV64ZVE32F-NEXT:    vsetvli zero, zero, e16, m1, ta, ma1172; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 41173; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma1174; RV64ZVE32F-NEXT:    vse16.v v10, (a2)1175; RV64ZVE32F-NEXT:  .LBB19_10: # %else81176; RV64ZVE32F-NEXT:    andi a2, a1, 321177; RV64ZVE32F-NEXT:    beqz a2, .LBB19_121178; RV64ZVE32F-NEXT:  # %bb.11: # %cond.store91179; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma1180; RV64ZVE32F-NEXT:    vslidedown.vi v10, v9, 11181; RV64ZVE32F-NEXT:    vmv.x.s a2, v101182; RV64ZVE32F-NEXT:    slli a2, a2, 11183; RV64ZVE32F-NEXT:    add a2, a0, a21184; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma1185; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 51186; RV64ZVE32F-NEXT:    vse16.v v10, (a2)1187; RV64ZVE32F-NEXT:  .LBB19_12: # %else101188; RV64ZVE32F-NEXT:    andi a2, a1, 641189; RV64ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma1190; RV64ZVE32F-NEXT:    vslidedown.vi v9, v9, 21191; RV64ZVE32F-NEXT:    bnez a2, .LBB19_151192; RV64ZVE32F-NEXT:  # %bb.13: # %else121193; RV64ZVE32F-NEXT:    andi a1, a1, -1281194; RV64ZVE32F-NEXT:    bnez a1, .LBB19_161195; RV64ZVE32F-NEXT:  .LBB19_14: # %else141196; RV64ZVE32F-NEXT:    ret1197; RV64ZVE32F-NEXT:  .LBB19_15: # %cond.store111198; RV64ZVE32F-NEXT:    vmv.x.s a2, v91199; RV64ZVE32F-NEXT:    slli a2, a2, 11200; RV64ZVE32F-NEXT:    add a2, a0, a21201; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma1202; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 61203; RV64ZVE32F-NEXT:    vse16.v v10, (a2)1204; RV64ZVE32F-NEXT:    andi a1, a1, -1281205; RV64ZVE32F-NEXT:    beqz a1, .LBB19_141206; RV64ZVE32F-NEXT:  .LBB19_16: # %cond.store131207; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma1208; RV64ZVE32F-NEXT:    vslidedown.vi v9, v9, 11209; RV64ZVE32F-NEXT:    vmv.x.s a1, v91210; RV64ZVE32F-NEXT:    slli a1, a1, 11211; RV64ZVE32F-NEXT:    add a0, a0, a11212; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma1213; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 71214; RV64ZVE32F-NEXT:    vse16.v v8, (a0)1215; RV64ZVE32F-NEXT:    ret1216  %eidxs = sext <8 x i8> %idxs to <8 x i16>1217  %ptrs = getelementptr inbounds i16, ptr %base, <8 x i16> %eidxs1218  call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> %val, <8 x ptr> %ptrs, i32 2, <8 x i1> %m)1219  ret void1220}1221 1222define void @mscatter_baseidx_zext_v8i8_v8i16(<8 x i16> %val, ptr %base, <8 x i8> %idxs, <8 x i1> %m) {1223; RV32-LABEL: mscatter_baseidx_zext_v8i8_v8i16:1224; RV32:       # %bb.0:1225; RV32-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma1226; RV32-NEXT:    vwaddu.vv v10, v9, v91227; RV32-NEXT:    vsetvli zero, zero, e16, m1, ta, ma1228; RV32-NEXT:    vsoxei16.v v8, (a0), v10, v0.t1229; RV32-NEXT:    ret1230;1231; RV64V-LABEL: mscatter_baseidx_zext_v8i8_v8i16:1232; RV64V:       # %bb.0:1233; RV64V-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma1234; RV64V-NEXT:    vwaddu.vv v10, v9, v91235; RV64V-NEXT:    vsetvli zero, zero, e16, m1, ta, ma1236; RV64V-NEXT:    vsoxei16.v v8, (a0), v10, v0.t1237; RV64V-NEXT:    ret1238;1239; RV64ZVE32F-LABEL: mscatter_baseidx_zext_v8i8_v8i16:1240; RV64ZVE32F:       # %bb.0:1241; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma1242; RV64ZVE32F-NEXT:    vmv.x.s a1, v01243; RV64ZVE32F-NEXT:    andi a2, a1, 11244; RV64ZVE32F-NEXT:    beqz a2, .LBB20_21245; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store1246; RV64ZVE32F-NEXT:    vmv.x.s a2, v91247; RV64ZVE32F-NEXT:    zext.b a2, a21248; RV64ZVE32F-NEXT:    slli a2, a2, 11249; RV64ZVE32F-NEXT:    add a2, a0, a21250; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma1251; RV64ZVE32F-NEXT:    vse16.v v8, (a2)1252; RV64ZVE32F-NEXT:  .LBB20_2: # %else1253; RV64ZVE32F-NEXT:    andi a2, a1, 21254; RV64ZVE32F-NEXT:    beqz a2, .LBB20_41255; RV64ZVE32F-NEXT:  # %bb.3: # %cond.store11256; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma1257; RV64ZVE32F-NEXT:    vslidedown.vi v10, v9, 11258; RV64ZVE32F-NEXT:    vmv.x.s a2, v101259; RV64ZVE32F-NEXT:    zext.b a2, a21260; RV64ZVE32F-NEXT:    slli a2, a2, 11261; RV64ZVE32F-NEXT:    add a2, a0, a21262; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma1263; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 11264; RV64ZVE32F-NEXT:    vse16.v v10, (a2)1265; RV64ZVE32F-NEXT:  .LBB20_4: # %else21266; RV64ZVE32F-NEXT:    andi a2, a1, 41267; RV64ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma1268; RV64ZVE32F-NEXT:    vslidedown.vi v10, v9, 21269; RV64ZVE32F-NEXT:    beqz a2, .LBB20_61270; RV64ZVE32F-NEXT:  # %bb.5: # %cond.store31271; RV64ZVE32F-NEXT:    vmv.x.s a2, v101272; RV64ZVE32F-NEXT:    zext.b a2, a21273; RV64ZVE32F-NEXT:    slli a2, a2, 11274; RV64ZVE32F-NEXT:    add a2, a0, a21275; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma1276; RV64ZVE32F-NEXT:    vslidedown.vi v11, v8, 21277; RV64ZVE32F-NEXT:    vse16.v v11, (a2)1278; RV64ZVE32F-NEXT:  .LBB20_6: # %else41279; RV64ZVE32F-NEXT:    andi a2, a1, 81280; RV64ZVE32F-NEXT:    beqz a2, .LBB20_81281; RV64ZVE32F-NEXT:  # %bb.7: # %cond.store51282; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma1283; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 11284; RV64ZVE32F-NEXT:    vmv.x.s a2, v101285; RV64ZVE32F-NEXT:    zext.b a2, a21286; RV64ZVE32F-NEXT:    slli a2, a2, 11287; RV64ZVE32F-NEXT:    add a2, a0, a21288; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma1289; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 31290; RV64ZVE32F-NEXT:    vse16.v v10, (a2)1291; RV64ZVE32F-NEXT:  .LBB20_8: # %else61292; RV64ZVE32F-NEXT:    andi a2, a1, 161293; RV64ZVE32F-NEXT:    vsetivli zero, 4, e8, mf2, ta, ma1294; RV64ZVE32F-NEXT:    vslidedown.vi v9, v9, 41295; RV64ZVE32F-NEXT:    beqz a2, .LBB20_101296; RV64ZVE32F-NEXT:  # %bb.9: # %cond.store71297; RV64ZVE32F-NEXT:    vmv.x.s a2, v91298; RV64ZVE32F-NEXT:    zext.b a2, a21299; RV64ZVE32F-NEXT:    slli a2, a2, 11300; RV64ZVE32F-NEXT:    add a2, a0, a21301; RV64ZVE32F-NEXT:    vsetvli zero, zero, e16, m1, ta, ma1302; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 41303; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma1304; RV64ZVE32F-NEXT:    vse16.v v10, (a2)1305; RV64ZVE32F-NEXT:  .LBB20_10: # %else81306; RV64ZVE32F-NEXT:    andi a2, a1, 321307; RV64ZVE32F-NEXT:    beqz a2, .LBB20_121308; RV64ZVE32F-NEXT:  # %bb.11: # %cond.store91309; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma1310; RV64ZVE32F-NEXT:    vslidedown.vi v10, v9, 11311; RV64ZVE32F-NEXT:    vmv.x.s a2, v101312; RV64ZVE32F-NEXT:    zext.b a2, a21313; RV64ZVE32F-NEXT:    slli a2, a2, 11314; RV64ZVE32F-NEXT:    add a2, a0, a21315; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma1316; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 51317; RV64ZVE32F-NEXT:    vse16.v v10, (a2)1318; RV64ZVE32F-NEXT:  .LBB20_12: # %else101319; RV64ZVE32F-NEXT:    andi a2, a1, 641320; RV64ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma1321; RV64ZVE32F-NEXT:    vslidedown.vi v9, v9, 21322; RV64ZVE32F-NEXT:    bnez a2, .LBB20_151323; RV64ZVE32F-NEXT:  # %bb.13: # %else121324; RV64ZVE32F-NEXT:    andi a1, a1, -1281325; RV64ZVE32F-NEXT:    bnez a1, .LBB20_161326; RV64ZVE32F-NEXT:  .LBB20_14: # %else141327; RV64ZVE32F-NEXT:    ret1328; RV64ZVE32F-NEXT:  .LBB20_15: # %cond.store111329; RV64ZVE32F-NEXT:    vmv.x.s a2, v91330; RV64ZVE32F-NEXT:    zext.b a2, a21331; RV64ZVE32F-NEXT:    slli a2, a2, 11332; RV64ZVE32F-NEXT:    add a2, a0, a21333; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma1334; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 61335; RV64ZVE32F-NEXT:    vse16.v v10, (a2)1336; RV64ZVE32F-NEXT:    andi a1, a1, -1281337; RV64ZVE32F-NEXT:    beqz a1, .LBB20_141338; RV64ZVE32F-NEXT:  .LBB20_16: # %cond.store131339; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma1340; RV64ZVE32F-NEXT:    vslidedown.vi v9, v9, 11341; RV64ZVE32F-NEXT:    vmv.x.s a1, v91342; RV64ZVE32F-NEXT:    zext.b a1, a11343; RV64ZVE32F-NEXT:    slli a1, a1, 11344; RV64ZVE32F-NEXT:    add a0, a0, a11345; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma1346; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 71347; RV64ZVE32F-NEXT:    vse16.v v8, (a0)1348; RV64ZVE32F-NEXT:    ret1349  %eidxs = zext <8 x i8> %idxs to <8 x i16>1350  %ptrs = getelementptr inbounds i16, ptr %base, <8 x i16> %eidxs1351  call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> %val, <8 x ptr> %ptrs, i32 2, <8 x i1> %m)1352  ret void1353}1354 1355define void @mscatter_baseidx_v8i16(<8 x i16> %val, ptr %base, <8 x i16> %idxs, <8 x i1> %m) {1356; RV32-LABEL: mscatter_baseidx_v8i16:1357; RV32:       # %bb.0:1358; RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma1359; RV32-NEXT:    vwadd.vv v10, v9, v91360; RV32-NEXT:    vsoxei32.v v8, (a0), v10, v0.t1361; RV32-NEXT:    ret1362;1363; RV64V-LABEL: mscatter_baseidx_v8i16:1364; RV64V:       # %bb.0:1365; RV64V-NEXT:    vsetivli zero, 8, e64, m4, ta, ma1366; RV64V-NEXT:    vsext.vf4 v12, v91367; RV64V-NEXT:    vadd.vv v12, v12, v121368; RV64V-NEXT:    vsetvli zero, zero, e16, m1, ta, ma1369; RV64V-NEXT:    vsoxei64.v v8, (a0), v12, v0.t1370; RV64V-NEXT:    ret1371;1372; RV64ZVE32F-LABEL: mscatter_baseidx_v8i16:1373; RV64ZVE32F:       # %bb.0:1374; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma1375; RV64ZVE32F-NEXT:    vmv.x.s a1, v01376; RV64ZVE32F-NEXT:    andi a2, a1, 11377; RV64ZVE32F-NEXT:    beqz a2, .LBB21_21378; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store1379; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma1380; RV64ZVE32F-NEXT:    vmv.x.s a2, v91381; RV64ZVE32F-NEXT:    slli a2, a2, 11382; RV64ZVE32F-NEXT:    add a2, a0, a21383; RV64ZVE32F-NEXT:    vse16.v v8, (a2)1384; RV64ZVE32F-NEXT:  .LBB21_2: # %else1385; RV64ZVE32F-NEXT:    andi a2, a1, 21386; RV64ZVE32F-NEXT:    beqz a2, .LBB21_41387; RV64ZVE32F-NEXT:  # %bb.3: # %cond.store11388; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma1389; RV64ZVE32F-NEXT:    vslidedown.vi v10, v9, 11390; RV64ZVE32F-NEXT:    vmv.x.s a2, v101391; RV64ZVE32F-NEXT:    slli a2, a2, 11392; RV64ZVE32F-NEXT:    add a2, a0, a21393; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma1394; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 11395; RV64ZVE32F-NEXT:    vse16.v v10, (a2)1396; RV64ZVE32F-NEXT:  .LBB21_4: # %else21397; RV64ZVE32F-NEXT:    andi a2, a1, 41398; RV64ZVE32F-NEXT:    vsetivli zero, 2, e16, mf2, ta, ma1399; RV64ZVE32F-NEXT:    vslidedown.vi v10, v9, 21400; RV64ZVE32F-NEXT:    beqz a2, .LBB21_61401; RV64ZVE32F-NEXT:  # %bb.5: # %cond.store31402; RV64ZVE32F-NEXT:    vmv.x.s a2, v101403; RV64ZVE32F-NEXT:    slli a2, a2, 11404; RV64ZVE32F-NEXT:    add a2, a0, a21405; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma1406; RV64ZVE32F-NEXT:    vslidedown.vi v11, v8, 21407; RV64ZVE32F-NEXT:    vse16.v v11, (a2)1408; RV64ZVE32F-NEXT:  .LBB21_6: # %else41409; RV64ZVE32F-NEXT:    andi a2, a1, 81410; RV64ZVE32F-NEXT:    beqz a2, .LBB21_81411; RV64ZVE32F-NEXT:  # %bb.7: # %cond.store51412; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma1413; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 11414; RV64ZVE32F-NEXT:    vmv.x.s a2, v101415; RV64ZVE32F-NEXT:    slli a2, a2, 11416; RV64ZVE32F-NEXT:    add a2, a0, a21417; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma1418; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 31419; RV64ZVE32F-NEXT:    vse16.v v10, (a2)1420; RV64ZVE32F-NEXT:  .LBB21_8: # %else61421; RV64ZVE32F-NEXT:    andi a2, a1, 161422; RV64ZVE32F-NEXT:    vsetivli zero, 4, e16, m1, ta, ma1423; RV64ZVE32F-NEXT:    vslidedown.vi v9, v9, 41424; RV64ZVE32F-NEXT:    beqz a2, .LBB21_101425; RV64ZVE32F-NEXT:  # %bb.9: # %cond.store71426; RV64ZVE32F-NEXT:    vmv.x.s a2, v91427; RV64ZVE32F-NEXT:    slli a2, a2, 11428; RV64ZVE32F-NEXT:    add a2, a0, a21429; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 41430; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma1431; RV64ZVE32F-NEXT:    vse16.v v10, (a2)1432; RV64ZVE32F-NEXT:  .LBB21_10: # %else81433; RV64ZVE32F-NEXT:    andi a2, a1, 321434; RV64ZVE32F-NEXT:    beqz a2, .LBB21_121435; RV64ZVE32F-NEXT:  # %bb.11: # %cond.store91436; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma1437; RV64ZVE32F-NEXT:    vslidedown.vi v10, v9, 11438; RV64ZVE32F-NEXT:    vmv.x.s a2, v101439; RV64ZVE32F-NEXT:    slli a2, a2, 11440; RV64ZVE32F-NEXT:    add a2, a0, a21441; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma1442; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 51443; RV64ZVE32F-NEXT:    vse16.v v10, (a2)1444; RV64ZVE32F-NEXT:  .LBB21_12: # %else101445; RV64ZVE32F-NEXT:    andi a2, a1, 641446; RV64ZVE32F-NEXT:    vsetivli zero, 2, e16, mf2, ta, ma1447; RV64ZVE32F-NEXT:    vslidedown.vi v9, v9, 21448; RV64ZVE32F-NEXT:    bnez a2, .LBB21_151449; RV64ZVE32F-NEXT:  # %bb.13: # %else121450; RV64ZVE32F-NEXT:    andi a1, a1, -1281451; RV64ZVE32F-NEXT:    bnez a1, .LBB21_161452; RV64ZVE32F-NEXT:  .LBB21_14: # %else141453; RV64ZVE32F-NEXT:    ret1454; RV64ZVE32F-NEXT:  .LBB21_15: # %cond.store111455; RV64ZVE32F-NEXT:    vmv.x.s a2, v91456; RV64ZVE32F-NEXT:    slli a2, a2, 11457; RV64ZVE32F-NEXT:    add a2, a0, a21458; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma1459; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 61460; RV64ZVE32F-NEXT:    vse16.v v10, (a2)1461; RV64ZVE32F-NEXT:    andi a1, a1, -1281462; RV64ZVE32F-NEXT:    beqz a1, .LBB21_141463; RV64ZVE32F-NEXT:  .LBB21_16: # %cond.store131464; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma1465; RV64ZVE32F-NEXT:    vslidedown.vi v9, v9, 11466; RV64ZVE32F-NEXT:    vmv.x.s a1, v91467; RV64ZVE32F-NEXT:    slli a1, a1, 11468; RV64ZVE32F-NEXT:    add a0, a0, a11469; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma1470; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 71471; RV64ZVE32F-NEXT:    vse16.v v8, (a0)1472; RV64ZVE32F-NEXT:    ret1473  %ptrs = getelementptr inbounds i16, ptr %base, <8 x i16> %idxs1474  call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> %val, <8 x ptr> %ptrs, i32 2, <8 x i1> %m)1475  ret void1476}1477 1478define void @mscatter_v1i32(<1 x i32> %val, <1 x ptr> %ptrs, <1 x i1> %m) {1479; RV32V-LABEL: mscatter_v1i32:1480; RV32V:       # %bb.0:1481; RV32V-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma1482; RV32V-NEXT:    vsoxei32.v v8, (zero), v9, v0.t1483; RV32V-NEXT:    ret1484;1485; RV64V-LABEL: mscatter_v1i32:1486; RV64V:       # %bb.0:1487; RV64V-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma1488; RV64V-NEXT:    vsoxei64.v v8, (zero), v9, v0.t1489; RV64V-NEXT:    ret1490;1491; RV32ZVE32F-LABEL: mscatter_v1i32:1492; RV32ZVE32F:       # %bb.0:1493; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma1494; RV32ZVE32F-NEXT:    vsoxei32.v v8, (zero), v9, v0.t1495; RV32ZVE32F-NEXT:    ret1496;1497; RV64ZVE32F-LABEL: mscatter_v1i32:1498; RV64ZVE32F:       # %bb.0:1499; RV64ZVE32F-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma1500; RV64ZVE32F-NEXT:    vfirst.m a1, v01501; RV64ZVE32F-NEXT:    bnez a1, .LBB22_21502; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store1503; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma1504; RV64ZVE32F-NEXT:    vse32.v v8, (a0)1505; RV64ZVE32F-NEXT:  .LBB22_2: # %else1506; RV64ZVE32F-NEXT:    ret1507  call void @llvm.masked.scatter.v1i32.v1p0(<1 x i32> %val, <1 x ptr> %ptrs, i32 4, <1 x i1> %m)1508  ret void1509}1510 1511define void @mscatter_v2i32(<2 x i32> %val, <2 x ptr> %ptrs, <2 x i1> %m) {1512; RV32V-LABEL: mscatter_v2i32:1513; RV32V:       # %bb.0:1514; RV32V-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma1515; RV32V-NEXT:    vsoxei32.v v8, (zero), v9, v0.t1516; RV32V-NEXT:    ret1517;1518; RV64V-LABEL: mscatter_v2i32:1519; RV64V:       # %bb.0:1520; RV64V-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma1521; RV64V-NEXT:    vsoxei64.v v8, (zero), v9, v0.t1522; RV64V-NEXT:    ret1523;1524; RV32ZVE32F-LABEL: mscatter_v2i32:1525; RV32ZVE32F:       # %bb.0:1526; RV32ZVE32F-NEXT:    vsetivli zero, 2, e32, m1, ta, ma1527; RV32ZVE32F-NEXT:    vsoxei32.v v8, (zero), v9, v0.t1528; RV32ZVE32F-NEXT:    ret1529;1530; RV64ZVE32F-LABEL: mscatter_v2i32:1531; RV64ZVE32F:       # %bb.0:1532; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma1533; RV64ZVE32F-NEXT:    vmv.x.s a2, v01534; RV64ZVE32F-NEXT:    andi a3, a2, 11535; RV64ZVE32F-NEXT:    bnez a3, .LBB23_31536; RV64ZVE32F-NEXT:  # %bb.1: # %else1537; RV64ZVE32F-NEXT:    andi a2, a2, 21538; RV64ZVE32F-NEXT:    bnez a2, .LBB23_41539; RV64ZVE32F-NEXT:  .LBB23_2: # %else21540; RV64ZVE32F-NEXT:    ret1541; RV64ZVE32F-NEXT:  .LBB23_3: # %cond.store1542; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma1543; RV64ZVE32F-NEXT:    vse32.v v8, (a0)1544; RV64ZVE32F-NEXT:    andi a2, a2, 21545; RV64ZVE32F-NEXT:    beqz a2, .LBB23_21546; RV64ZVE32F-NEXT:  .LBB23_4: # %cond.store11547; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma1548; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 11549; RV64ZVE32F-NEXT:    vse32.v v8, (a1)1550; RV64ZVE32F-NEXT:    ret1551  call void @llvm.masked.scatter.v2i32.v2p0(<2 x i32> %val, <2 x ptr> %ptrs, i32 4, <2 x i1> %m)1552  ret void1553}1554 1555define void @mscatter_v2i64_truncstore_v2i32(<2 x i64> %val, <2 x ptr> %ptrs, <2 x i1> %m) {1556; RV32V-LABEL: mscatter_v2i64_truncstore_v2i32:1557; RV32V:       # %bb.0:1558; RV32V-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma1559; RV32V-NEXT:    vnsrl.wi v8, v8, 01560; RV32V-NEXT:    vsoxei32.v v8, (zero), v9, v0.t1561; RV32V-NEXT:    ret1562;1563; RV64V-LABEL: mscatter_v2i64_truncstore_v2i32:1564; RV64V:       # %bb.0:1565; RV64V-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma1566; RV64V-NEXT:    vnsrl.wi v8, v8, 01567; RV64V-NEXT:    vsoxei64.v v8, (zero), v9, v0.t1568; RV64V-NEXT:    ret1569;1570; RV32ZVE32F-LABEL: mscatter_v2i64_truncstore_v2i32:1571; RV32ZVE32F:       # %bb.0:1572; RV32ZVE32F-NEXT:    lw a1, 0(a0)1573; RV32ZVE32F-NEXT:    lw a0, 8(a0)1574; RV32ZVE32F-NEXT:    vsetivli zero, 2, e32, m1, ta, ma1575; RV32ZVE32F-NEXT:    vmv.v.x v9, a11576; RV32ZVE32F-NEXT:    vslide1down.vx v9, v9, a01577; RV32ZVE32F-NEXT:    vsoxei32.v v9, (zero), v8, v0.t1578; RV32ZVE32F-NEXT:    ret1579;1580; RV64ZVE32F-LABEL: mscatter_v2i64_truncstore_v2i32:1581; RV64ZVE32F:       # %bb.0:1582; RV64ZVE32F-NEXT:    vsetivli zero, 2, e32, m1, ta, ma1583; RV64ZVE32F-NEXT:    vmv.v.x v8, a01584; RV64ZVE32F-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma1585; RV64ZVE32F-NEXT:    vmv.x.s a0, v01586; RV64ZVE32F-NEXT:    andi a4, a0, 11587; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma1588; RV64ZVE32F-NEXT:    vslide1down.vx v8, v8, a11589; RV64ZVE32F-NEXT:    bnez a4, .LBB24_31590; RV64ZVE32F-NEXT:  # %bb.1: # %else1591; RV64ZVE32F-NEXT:    andi a0, a0, 21592; RV64ZVE32F-NEXT:    bnez a0, .LBB24_41593; RV64ZVE32F-NEXT:  .LBB24_2: # %else21594; RV64ZVE32F-NEXT:    ret1595; RV64ZVE32F-NEXT:  .LBB24_3: # %cond.store1596; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma1597; RV64ZVE32F-NEXT:    vse32.v v8, (a2)1598; RV64ZVE32F-NEXT:    andi a0, a0, 21599; RV64ZVE32F-NEXT:    beqz a0, .LBB24_21600; RV64ZVE32F-NEXT:  .LBB24_4: # %cond.store11601; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma1602; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 11603; RV64ZVE32F-NEXT:    vse32.v v8, (a3)1604; RV64ZVE32F-NEXT:    ret1605  %tval = trunc <2 x i64> %val to <2 x i32>1606  call void @llvm.masked.scatter.v2i32.v2p0(<2 x i32> %tval, <2 x ptr> %ptrs, i32 4, <2 x i1> %m)1607  ret void1608}1609 1610define void @mscatter_v4i32(<4 x i32> %val, <4 x ptr> %ptrs, <4 x i1> %m) {1611; RV32-LABEL: mscatter_v4i32:1612; RV32:       # %bb.0:1613; RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, ma1614; RV32-NEXT:    vsoxei32.v v8, (zero), v9, v0.t1615; RV32-NEXT:    ret1616;1617; RV64V-LABEL: mscatter_v4i32:1618; RV64V:       # %bb.0:1619; RV64V-NEXT:    vsetivli zero, 4, e32, m1, ta, ma1620; RV64V-NEXT:    vsoxei64.v v8, (zero), v10, v0.t1621; RV64V-NEXT:    ret1622;1623; RV64ZVE32F-LABEL: mscatter_v4i32:1624; RV64ZVE32F:       # %bb.0:1625; RV64ZVE32F-NEXT:    ld a4, 8(a0)1626; RV64ZVE32F-NEXT:    ld a2, 16(a0)1627; RV64ZVE32F-NEXT:    ld a1, 24(a0)1628; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma1629; RV64ZVE32F-NEXT:    vmv.x.s a3, v01630; RV64ZVE32F-NEXT:    andi a5, a3, 11631; RV64ZVE32F-NEXT:    bnez a5, .LBB25_51632; RV64ZVE32F-NEXT:  # %bb.1: # %else1633; RV64ZVE32F-NEXT:    andi a0, a3, 21634; RV64ZVE32F-NEXT:    bnez a0, .LBB25_61635; RV64ZVE32F-NEXT:  .LBB25_2: # %else21636; RV64ZVE32F-NEXT:    andi a0, a3, 41637; RV64ZVE32F-NEXT:    bnez a0, .LBB25_71638; RV64ZVE32F-NEXT:  .LBB25_3: # %else41639; RV64ZVE32F-NEXT:    andi a3, a3, 81640; RV64ZVE32F-NEXT:    bnez a3, .LBB25_81641; RV64ZVE32F-NEXT:  .LBB25_4: # %else61642; RV64ZVE32F-NEXT:    ret1643; RV64ZVE32F-NEXT:  .LBB25_5: # %cond.store1644; RV64ZVE32F-NEXT:    ld a0, 0(a0)1645; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma1646; RV64ZVE32F-NEXT:    vse32.v v8, (a0)1647; RV64ZVE32F-NEXT:    andi a0, a3, 21648; RV64ZVE32F-NEXT:    beqz a0, .LBB25_21649; RV64ZVE32F-NEXT:  .LBB25_6: # %cond.store11650; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma1651; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 11652; RV64ZVE32F-NEXT:    vse32.v v9, (a4)1653; RV64ZVE32F-NEXT:    andi a0, a3, 41654; RV64ZVE32F-NEXT:    beqz a0, .LBB25_31655; RV64ZVE32F-NEXT:  .LBB25_7: # %cond.store31656; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma1657; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 21658; RV64ZVE32F-NEXT:    vse32.v v9, (a2)1659; RV64ZVE32F-NEXT:    andi a3, a3, 81660; RV64ZVE32F-NEXT:    beqz a3, .LBB25_41661; RV64ZVE32F-NEXT:  .LBB25_8: # %cond.store51662; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma1663; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 31664; RV64ZVE32F-NEXT:    vse32.v v8, (a1)1665; RV64ZVE32F-NEXT:    ret1666  call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %val, <4 x ptr> %ptrs, i32 4, <4 x i1> %m)1667  ret void1668}1669 1670define void @mscatter_truemask_v4i32(<4 x i32> %val, <4 x ptr> %ptrs) {1671; RV32-LABEL: mscatter_truemask_v4i32:1672; RV32:       # %bb.0:1673; RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, ma1674; RV32-NEXT:    vsoxei32.v v8, (zero), v91675; RV32-NEXT:    ret1676;1677; RV64V-LABEL: mscatter_truemask_v4i32:1678; RV64V:       # %bb.0:1679; RV64V-NEXT:    vsetivli zero, 4, e32, m1, ta, ma1680; RV64V-NEXT:    vsoxei64.v v8, (zero), v101681; RV64V-NEXT:    ret1682;1683; RV64ZVE32F-LABEL: mscatter_truemask_v4i32:1684; RV64ZVE32F:       # %bb.0:1685; RV64ZVE32F-NEXT:    ld a1, 0(a0)1686; RV64ZVE32F-NEXT:    ld a2, 8(a0)1687; RV64ZVE32F-NEXT:    ld a3, 16(a0)1688; RV64ZVE32F-NEXT:    ld a0, 24(a0)1689; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma1690; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 11691; RV64ZVE32F-NEXT:    vse32.v v8, (a1)1692; RV64ZVE32F-NEXT:    vse32.v v9, (a2)1693; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 21694; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 31695; RV64ZVE32F-NEXT:    vse32.v v9, (a3)1696; RV64ZVE32F-NEXT:    vse32.v v8, (a0)1697; RV64ZVE32F-NEXT:    ret1698  call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %val, <4 x ptr> %ptrs, i32 4, <4 x i1> splat (i1 1))1699  ret void1700}1701 1702define void @mscatter_falsemask_v4i32(<4 x i32> %val, <4 x ptr> %ptrs) {1703; CHECK-LABEL: mscatter_falsemask_v4i32:1704; CHECK:       # %bb.0:1705; CHECK-NEXT:    ret1706  call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %val, <4 x ptr> %ptrs, i32 4, <4 x i1> zeroinitializer)1707  ret void1708}1709 1710define void @mscatter_v8i32(<8 x i32> %val, <8 x ptr> %ptrs, <8 x i1> %m) {1711; RV32-LABEL: mscatter_v8i32:1712; RV32:       # %bb.0:1713; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma1714; RV32-NEXT:    vsoxei32.v v8, (zero), v10, v0.t1715; RV32-NEXT:    ret1716;1717; RV64V-LABEL: mscatter_v8i32:1718; RV64V:       # %bb.0:1719; RV64V-NEXT:    vsetivli zero, 8, e32, m2, ta, ma1720; RV64V-NEXT:    vsoxei64.v v8, (zero), v12, v0.t1721; RV64V-NEXT:    ret1722;1723; RV64ZVE32F-LABEL: mscatter_v8i32:1724; RV64ZVE32F:       # %bb.0:1725; RV64ZVE32F-NEXT:    ld a3, 40(a0)1726; RV64ZVE32F-NEXT:    ld a2, 48(a0)1727; RV64ZVE32F-NEXT:    ld a1, 56(a0)1728; RV64ZVE32F-NEXT:    ld t0, 8(a0)1729; RV64ZVE32F-NEXT:    ld a7, 16(a0)1730; RV64ZVE32F-NEXT:    ld a6, 24(a0)1731; RV64ZVE32F-NEXT:    ld a5, 32(a0)1732; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma1733; RV64ZVE32F-NEXT:    vmv.x.s a4, v01734; RV64ZVE32F-NEXT:    andi t1, a4, 11735; RV64ZVE32F-NEXT:    bnez t1, .LBB28_91736; RV64ZVE32F-NEXT:  # %bb.1: # %else1737; RV64ZVE32F-NEXT:    andi a0, a4, 21738; RV64ZVE32F-NEXT:    bnez a0, .LBB28_101739; RV64ZVE32F-NEXT:  .LBB28_2: # %else21740; RV64ZVE32F-NEXT:    andi a0, a4, 41741; RV64ZVE32F-NEXT:    bnez a0, .LBB28_111742; RV64ZVE32F-NEXT:  .LBB28_3: # %else41743; RV64ZVE32F-NEXT:    andi a0, a4, 81744; RV64ZVE32F-NEXT:    bnez a0, .LBB28_121745; RV64ZVE32F-NEXT:  .LBB28_4: # %else61746; RV64ZVE32F-NEXT:    andi a0, a4, 161747; RV64ZVE32F-NEXT:    bnez a0, .LBB28_131748; RV64ZVE32F-NEXT:  .LBB28_5: # %else81749; RV64ZVE32F-NEXT:    andi a0, a4, 321750; RV64ZVE32F-NEXT:    bnez a0, .LBB28_141751; RV64ZVE32F-NEXT:  .LBB28_6: # %else101752; RV64ZVE32F-NEXT:    andi a0, a4, 641753; RV64ZVE32F-NEXT:    bnez a0, .LBB28_151754; RV64ZVE32F-NEXT:  .LBB28_7: # %else121755; RV64ZVE32F-NEXT:    andi a0, a4, -1281756; RV64ZVE32F-NEXT:    bnez a0, .LBB28_161757; RV64ZVE32F-NEXT:  .LBB28_8: # %else141758; RV64ZVE32F-NEXT:    ret1759; RV64ZVE32F-NEXT:  .LBB28_9: # %cond.store1760; RV64ZVE32F-NEXT:    ld a0, 0(a0)1761; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma1762; RV64ZVE32F-NEXT:    vse32.v v8, (a0)1763; RV64ZVE32F-NEXT:    andi a0, a4, 21764; RV64ZVE32F-NEXT:    beqz a0, .LBB28_21765; RV64ZVE32F-NEXT:  .LBB28_10: # %cond.store11766; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma1767; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 11768; RV64ZVE32F-NEXT:    vse32.v v10, (t0)1769; RV64ZVE32F-NEXT:    andi a0, a4, 41770; RV64ZVE32F-NEXT:    beqz a0, .LBB28_31771; RV64ZVE32F-NEXT:  .LBB28_11: # %cond.store31772; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma1773; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 21774; RV64ZVE32F-NEXT:    vse32.v v10, (a7)1775; RV64ZVE32F-NEXT:    andi a0, a4, 81776; RV64ZVE32F-NEXT:    beqz a0, .LBB28_41777; RV64ZVE32F-NEXT:  .LBB28_12: # %cond.store51778; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma1779; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 31780; RV64ZVE32F-NEXT:    vse32.v v10, (a6)1781; RV64ZVE32F-NEXT:    andi a0, a4, 161782; RV64ZVE32F-NEXT:    beqz a0, .LBB28_51783; RV64ZVE32F-NEXT:  .LBB28_13: # %cond.store71784; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma1785; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 41786; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma1787; RV64ZVE32F-NEXT:    vse32.v v10, (a5)1788; RV64ZVE32F-NEXT:    andi a0, a4, 321789; RV64ZVE32F-NEXT:    beqz a0, .LBB28_61790; RV64ZVE32F-NEXT:  .LBB28_14: # %cond.store91791; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma1792; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 51793; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma1794; RV64ZVE32F-NEXT:    vse32.v v10, (a3)1795; RV64ZVE32F-NEXT:    andi a0, a4, 641796; RV64ZVE32F-NEXT:    beqz a0, .LBB28_71797; RV64ZVE32F-NEXT:  .LBB28_15: # %cond.store111798; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma1799; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 61800; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma1801; RV64ZVE32F-NEXT:    vse32.v v10, (a2)1802; RV64ZVE32F-NEXT:    andi a0, a4, -1281803; RV64ZVE32F-NEXT:    beqz a0, .LBB28_81804; RV64ZVE32F-NEXT:  .LBB28_16: # %cond.store131805; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma1806; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 71807; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma1808; RV64ZVE32F-NEXT:    vse32.v v8, (a1)1809; RV64ZVE32F-NEXT:    ret1810  call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> %val, <8 x ptr> %ptrs, i32 4, <8 x i1> %m)1811  ret void1812}1813 1814define void @mscatter_baseidx_v8i8_v8i32(<8 x i32> %val, ptr %base, <8 x i8> %idxs, <8 x i1> %m) {1815; RV32-LABEL: mscatter_baseidx_v8i8_v8i32:1816; RV32:       # %bb.0:1817; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma1818; RV32-NEXT:    vsext.vf4 v12, v101819; RV32-NEXT:    vsll.vi v10, v12, 21820; RV32-NEXT:    vsoxei32.v v8, (a0), v10, v0.t1821; RV32-NEXT:    ret1822;1823; RV64V-LABEL: mscatter_baseidx_v8i8_v8i32:1824; RV64V:       # %bb.0:1825; RV64V-NEXT:    vsetivli zero, 8, e64, m4, ta, ma1826; RV64V-NEXT:    vsext.vf8 v12, v101827; RV64V-NEXT:    vsll.vi v12, v12, 21828; RV64V-NEXT:    vsetvli zero, zero, e32, m2, ta, ma1829; RV64V-NEXT:    vsoxei64.v v8, (a0), v12, v0.t1830; RV64V-NEXT:    ret1831;1832; RV64ZVE32F-LABEL: mscatter_baseidx_v8i8_v8i32:1833; RV64ZVE32F:       # %bb.0:1834; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma1835; RV64ZVE32F-NEXT:    vmv.x.s a1, v01836; RV64ZVE32F-NEXT:    andi a2, a1, 11837; RV64ZVE32F-NEXT:    beqz a2, .LBB29_21838; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store1839; RV64ZVE32F-NEXT:    vmv.x.s a2, v101840; RV64ZVE32F-NEXT:    slli a2, a2, 21841; RV64ZVE32F-NEXT:    add a2, a0, a21842; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma1843; RV64ZVE32F-NEXT:    vse32.v v8, (a2)1844; RV64ZVE32F-NEXT:  .LBB29_2: # %else1845; RV64ZVE32F-NEXT:    andi a2, a1, 21846; RV64ZVE32F-NEXT:    beqz a2, .LBB29_41847; RV64ZVE32F-NEXT:  # %bb.3: # %cond.store11848; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma1849; RV64ZVE32F-NEXT:    vslidedown.vi v11, v10, 11850; RV64ZVE32F-NEXT:    vmv.x.s a2, v111851; RV64ZVE32F-NEXT:    slli a2, a2, 21852; RV64ZVE32F-NEXT:    add a2, a0, a21853; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma1854; RV64ZVE32F-NEXT:    vslidedown.vi v11, v8, 11855; RV64ZVE32F-NEXT:    vse32.v v11, (a2)1856; RV64ZVE32F-NEXT:  .LBB29_4: # %else21857; RV64ZVE32F-NEXT:    andi a2, a1, 41858; RV64ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma1859; RV64ZVE32F-NEXT:    vslidedown.vi v11, v10, 21860; RV64ZVE32F-NEXT:    beqz a2, .LBB29_61861; RV64ZVE32F-NEXT:  # %bb.5: # %cond.store31862; RV64ZVE32F-NEXT:    vmv.x.s a2, v111863; RV64ZVE32F-NEXT:    slli a2, a2, 21864; RV64ZVE32F-NEXT:    add a2, a0, a21865; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma1866; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 21867; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma1868; RV64ZVE32F-NEXT:    vse32.v v12, (a2)1869; RV64ZVE32F-NEXT:  .LBB29_6: # %else41870; RV64ZVE32F-NEXT:    andi a2, a1, 81871; RV64ZVE32F-NEXT:    beqz a2, .LBB29_81872; RV64ZVE32F-NEXT:  # %bb.7: # %cond.store51873; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma1874; RV64ZVE32F-NEXT:    vslidedown.vi v11, v11, 11875; RV64ZVE32F-NEXT:    vmv.x.s a2, v111876; RV64ZVE32F-NEXT:    slli a2, a2, 21877; RV64ZVE32F-NEXT:    add a2, a0, a21878; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma1879; RV64ZVE32F-NEXT:    vslidedown.vi v11, v8, 31880; RV64ZVE32F-NEXT:    vse32.v v11, (a2)1881; RV64ZVE32F-NEXT:  .LBB29_8: # %else61882; RV64ZVE32F-NEXT:    andi a2, a1, 161883; RV64ZVE32F-NEXT:    vsetivli zero, 4, e8, mf2, ta, ma1884; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 41885; RV64ZVE32F-NEXT:    beqz a2, .LBB29_101886; RV64ZVE32F-NEXT:  # %bb.9: # %cond.store71887; RV64ZVE32F-NEXT:    vmv.x.s a2, v101888; RV64ZVE32F-NEXT:    slli a2, a2, 21889; RV64ZVE32F-NEXT:    add a2, a0, a21890; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma1891; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 41892; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma1893; RV64ZVE32F-NEXT:    vse32.v v12, (a2)1894; RV64ZVE32F-NEXT:  .LBB29_10: # %else81895; RV64ZVE32F-NEXT:    andi a2, a1, 321896; RV64ZVE32F-NEXT:    beqz a2, .LBB29_121897; RV64ZVE32F-NEXT:  # %bb.11: # %cond.store91898; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma1899; RV64ZVE32F-NEXT:    vslidedown.vi v11, v10, 11900; RV64ZVE32F-NEXT:    vmv.x.s a2, v111901; RV64ZVE32F-NEXT:    slli a2, a2, 21902; RV64ZVE32F-NEXT:    add a2, a0, a21903; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma1904; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 51905; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma1906; RV64ZVE32F-NEXT:    vse32.v v12, (a2)1907; RV64ZVE32F-NEXT:  .LBB29_12: # %else101908; RV64ZVE32F-NEXT:    andi a2, a1, 641909; RV64ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma1910; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 21911; RV64ZVE32F-NEXT:    bnez a2, .LBB29_151912; RV64ZVE32F-NEXT:  # %bb.13: # %else121913; RV64ZVE32F-NEXT:    andi a1, a1, -1281914; RV64ZVE32F-NEXT:    bnez a1, .LBB29_161915; RV64ZVE32F-NEXT:  .LBB29_14: # %else141916; RV64ZVE32F-NEXT:    ret1917; RV64ZVE32F-NEXT:  .LBB29_15: # %cond.store111918; RV64ZVE32F-NEXT:    vmv.x.s a2, v101919; RV64ZVE32F-NEXT:    slli a2, a2, 21920; RV64ZVE32F-NEXT:    add a2, a0, a21921; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma1922; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 61923; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma1924; RV64ZVE32F-NEXT:    vse32.v v12, (a2)1925; RV64ZVE32F-NEXT:    andi a1, a1, -1281926; RV64ZVE32F-NEXT:    beqz a1, .LBB29_141927; RV64ZVE32F-NEXT:  .LBB29_16: # %cond.store131928; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma1929; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 11930; RV64ZVE32F-NEXT:    vmv.x.s a1, v101931; RV64ZVE32F-NEXT:    slli a1, a1, 21932; RV64ZVE32F-NEXT:    add a0, a0, a11933; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma1934; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 71935; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma1936; RV64ZVE32F-NEXT:    vse32.v v8, (a0)1937; RV64ZVE32F-NEXT:    ret1938  %ptrs = getelementptr inbounds i32, ptr %base, <8 x i8> %idxs1939  call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> %val, <8 x ptr> %ptrs, i32 4, <8 x i1> %m)1940  ret void1941}1942 1943define void @mscatter_baseidx_sext_v8i8_v8i32(<8 x i32> %val, ptr %base, <8 x i8> %idxs, <8 x i1> %m) {1944; RV32-LABEL: mscatter_baseidx_sext_v8i8_v8i32:1945; RV32:       # %bb.0:1946; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma1947; RV32-NEXT:    vsext.vf4 v12, v101948; RV32-NEXT:    vsll.vi v10, v12, 21949; RV32-NEXT:    vsoxei32.v v8, (a0), v10, v0.t1950; RV32-NEXT:    ret1951;1952; RV64V-LABEL: mscatter_baseidx_sext_v8i8_v8i32:1953; RV64V:       # %bb.0:1954; RV64V-NEXT:    vsetivli zero, 8, e64, m4, ta, ma1955; RV64V-NEXT:    vsext.vf8 v12, v101956; RV64V-NEXT:    vsll.vi v12, v12, 21957; RV64V-NEXT:    vsetvli zero, zero, e32, m2, ta, ma1958; RV64V-NEXT:    vsoxei64.v v8, (a0), v12, v0.t1959; RV64V-NEXT:    ret1960;1961; RV64ZVE32F-LABEL: mscatter_baseidx_sext_v8i8_v8i32:1962; RV64ZVE32F:       # %bb.0:1963; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma1964; RV64ZVE32F-NEXT:    vmv.x.s a1, v01965; RV64ZVE32F-NEXT:    andi a2, a1, 11966; RV64ZVE32F-NEXT:    beqz a2, .LBB30_21967; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store1968; RV64ZVE32F-NEXT:    vmv.x.s a2, v101969; RV64ZVE32F-NEXT:    slli a2, a2, 21970; RV64ZVE32F-NEXT:    add a2, a0, a21971; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma1972; RV64ZVE32F-NEXT:    vse32.v v8, (a2)1973; RV64ZVE32F-NEXT:  .LBB30_2: # %else1974; RV64ZVE32F-NEXT:    andi a2, a1, 21975; RV64ZVE32F-NEXT:    beqz a2, .LBB30_41976; RV64ZVE32F-NEXT:  # %bb.3: # %cond.store11977; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma1978; RV64ZVE32F-NEXT:    vslidedown.vi v11, v10, 11979; RV64ZVE32F-NEXT:    vmv.x.s a2, v111980; RV64ZVE32F-NEXT:    slli a2, a2, 21981; RV64ZVE32F-NEXT:    add a2, a0, a21982; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma1983; RV64ZVE32F-NEXT:    vslidedown.vi v11, v8, 11984; RV64ZVE32F-NEXT:    vse32.v v11, (a2)1985; RV64ZVE32F-NEXT:  .LBB30_4: # %else21986; RV64ZVE32F-NEXT:    andi a2, a1, 41987; RV64ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma1988; RV64ZVE32F-NEXT:    vslidedown.vi v11, v10, 21989; RV64ZVE32F-NEXT:    beqz a2, .LBB30_61990; RV64ZVE32F-NEXT:  # %bb.5: # %cond.store31991; RV64ZVE32F-NEXT:    vmv.x.s a2, v111992; RV64ZVE32F-NEXT:    slli a2, a2, 21993; RV64ZVE32F-NEXT:    add a2, a0, a21994; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma1995; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 21996; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma1997; RV64ZVE32F-NEXT:    vse32.v v12, (a2)1998; RV64ZVE32F-NEXT:  .LBB30_6: # %else41999; RV64ZVE32F-NEXT:    andi a2, a1, 82000; RV64ZVE32F-NEXT:    beqz a2, .LBB30_82001; RV64ZVE32F-NEXT:  # %bb.7: # %cond.store52002; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma2003; RV64ZVE32F-NEXT:    vslidedown.vi v11, v11, 12004; RV64ZVE32F-NEXT:    vmv.x.s a2, v112005; RV64ZVE32F-NEXT:    slli a2, a2, 22006; RV64ZVE32F-NEXT:    add a2, a0, a22007; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma2008; RV64ZVE32F-NEXT:    vslidedown.vi v11, v8, 32009; RV64ZVE32F-NEXT:    vse32.v v11, (a2)2010; RV64ZVE32F-NEXT:  .LBB30_8: # %else62011; RV64ZVE32F-NEXT:    andi a2, a1, 162012; RV64ZVE32F-NEXT:    vsetivli zero, 4, e8, mf2, ta, ma2013; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 42014; RV64ZVE32F-NEXT:    beqz a2, .LBB30_102015; RV64ZVE32F-NEXT:  # %bb.9: # %cond.store72016; RV64ZVE32F-NEXT:    vmv.x.s a2, v102017; RV64ZVE32F-NEXT:    slli a2, a2, 22018; RV64ZVE32F-NEXT:    add a2, a0, a22019; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma2020; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 42021; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma2022; RV64ZVE32F-NEXT:    vse32.v v12, (a2)2023; RV64ZVE32F-NEXT:  .LBB30_10: # %else82024; RV64ZVE32F-NEXT:    andi a2, a1, 322025; RV64ZVE32F-NEXT:    beqz a2, .LBB30_122026; RV64ZVE32F-NEXT:  # %bb.11: # %cond.store92027; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma2028; RV64ZVE32F-NEXT:    vslidedown.vi v11, v10, 12029; RV64ZVE32F-NEXT:    vmv.x.s a2, v112030; RV64ZVE32F-NEXT:    slli a2, a2, 22031; RV64ZVE32F-NEXT:    add a2, a0, a22032; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma2033; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 52034; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma2035; RV64ZVE32F-NEXT:    vse32.v v12, (a2)2036; RV64ZVE32F-NEXT:  .LBB30_12: # %else102037; RV64ZVE32F-NEXT:    andi a2, a1, 642038; RV64ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma2039; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 22040; RV64ZVE32F-NEXT:    bnez a2, .LBB30_152041; RV64ZVE32F-NEXT:  # %bb.13: # %else122042; RV64ZVE32F-NEXT:    andi a1, a1, -1282043; RV64ZVE32F-NEXT:    bnez a1, .LBB30_162044; RV64ZVE32F-NEXT:  .LBB30_14: # %else142045; RV64ZVE32F-NEXT:    ret2046; RV64ZVE32F-NEXT:  .LBB30_15: # %cond.store112047; RV64ZVE32F-NEXT:    vmv.x.s a2, v102048; RV64ZVE32F-NEXT:    slli a2, a2, 22049; RV64ZVE32F-NEXT:    add a2, a0, a22050; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma2051; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 62052; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma2053; RV64ZVE32F-NEXT:    vse32.v v12, (a2)2054; RV64ZVE32F-NEXT:    andi a1, a1, -1282055; RV64ZVE32F-NEXT:    beqz a1, .LBB30_142056; RV64ZVE32F-NEXT:  .LBB30_16: # %cond.store132057; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma2058; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 12059; RV64ZVE32F-NEXT:    vmv.x.s a1, v102060; RV64ZVE32F-NEXT:    slli a1, a1, 22061; RV64ZVE32F-NEXT:    add a0, a0, a12062; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma2063; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 72064; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma2065; RV64ZVE32F-NEXT:    vse32.v v8, (a0)2066; RV64ZVE32F-NEXT:    ret2067  %eidxs = sext <8 x i8> %idxs to <8 x i32>2068  %ptrs = getelementptr inbounds i32, ptr %base, <8 x i32> %eidxs2069  call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> %val, <8 x ptr> %ptrs, i32 4, <8 x i1> %m)2070  ret void2071}2072 2073define void @mscatter_baseidx_zext_v8i8_v8i32(<8 x i32> %val, ptr %base, <8 x i8> %idxs, <8 x i1> %m) {2074; RV32-LABEL: mscatter_baseidx_zext_v8i8_v8i32:2075; RV32:       # %bb.0:2076; RV32-NEXT:    li a1, 42077; RV32-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma2078; RV32-NEXT:    vwmulu.vx v11, v10, a12079; RV32-NEXT:    vsetvli zero, zero, e32, m2, ta, ma2080; RV32-NEXT:    vsoxei16.v v8, (a0), v11, v0.t2081; RV32-NEXT:    ret2082;2083; RV64V-LABEL: mscatter_baseidx_zext_v8i8_v8i32:2084; RV64V:       # %bb.0:2085; RV64V-NEXT:    li a1, 42086; RV64V-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma2087; RV64V-NEXT:    vwmulu.vx v11, v10, a12088; RV64V-NEXT:    vsetvli zero, zero, e32, m2, ta, ma2089; RV64V-NEXT:    vsoxei16.v v8, (a0), v11, v0.t2090; RV64V-NEXT:    ret2091;2092; RV64ZVE32F-LABEL: mscatter_baseidx_zext_v8i8_v8i32:2093; RV64ZVE32F:       # %bb.0:2094; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma2095; RV64ZVE32F-NEXT:    vmv.x.s a1, v02096; RV64ZVE32F-NEXT:    andi a2, a1, 12097; RV64ZVE32F-NEXT:    beqz a2, .LBB31_22098; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store2099; RV64ZVE32F-NEXT:    vmv.x.s a2, v102100; RV64ZVE32F-NEXT:    zext.b a2, a22101; RV64ZVE32F-NEXT:    slli a2, a2, 22102; RV64ZVE32F-NEXT:    add a2, a0, a22103; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma2104; RV64ZVE32F-NEXT:    vse32.v v8, (a2)2105; RV64ZVE32F-NEXT:  .LBB31_2: # %else2106; RV64ZVE32F-NEXT:    andi a2, a1, 22107; RV64ZVE32F-NEXT:    beqz a2, .LBB31_42108; RV64ZVE32F-NEXT:  # %bb.3: # %cond.store12109; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma2110; RV64ZVE32F-NEXT:    vslidedown.vi v11, v10, 12111; RV64ZVE32F-NEXT:    vmv.x.s a2, v112112; RV64ZVE32F-NEXT:    zext.b a2, a22113; RV64ZVE32F-NEXT:    slli a2, a2, 22114; RV64ZVE32F-NEXT:    add a2, a0, a22115; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma2116; RV64ZVE32F-NEXT:    vslidedown.vi v11, v8, 12117; RV64ZVE32F-NEXT:    vse32.v v11, (a2)2118; RV64ZVE32F-NEXT:  .LBB31_4: # %else22119; RV64ZVE32F-NEXT:    andi a2, a1, 42120; RV64ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma2121; RV64ZVE32F-NEXT:    vslidedown.vi v11, v10, 22122; RV64ZVE32F-NEXT:    beqz a2, .LBB31_62123; RV64ZVE32F-NEXT:  # %bb.5: # %cond.store32124; RV64ZVE32F-NEXT:    vmv.x.s a2, v112125; RV64ZVE32F-NEXT:    zext.b a2, a22126; RV64ZVE32F-NEXT:    slli a2, a2, 22127; RV64ZVE32F-NEXT:    add a2, a0, a22128; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma2129; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 22130; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma2131; RV64ZVE32F-NEXT:    vse32.v v12, (a2)2132; RV64ZVE32F-NEXT:  .LBB31_6: # %else42133; RV64ZVE32F-NEXT:    andi a2, a1, 82134; RV64ZVE32F-NEXT:    beqz a2, .LBB31_82135; RV64ZVE32F-NEXT:  # %bb.7: # %cond.store52136; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma2137; RV64ZVE32F-NEXT:    vslidedown.vi v11, v11, 12138; RV64ZVE32F-NEXT:    vmv.x.s a2, v112139; RV64ZVE32F-NEXT:    zext.b a2, a22140; RV64ZVE32F-NEXT:    slli a2, a2, 22141; RV64ZVE32F-NEXT:    add a2, a0, a22142; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma2143; RV64ZVE32F-NEXT:    vslidedown.vi v11, v8, 32144; RV64ZVE32F-NEXT:    vse32.v v11, (a2)2145; RV64ZVE32F-NEXT:  .LBB31_8: # %else62146; RV64ZVE32F-NEXT:    andi a2, a1, 162147; RV64ZVE32F-NEXT:    vsetivli zero, 4, e8, mf2, ta, ma2148; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 42149; RV64ZVE32F-NEXT:    beqz a2, .LBB31_102150; RV64ZVE32F-NEXT:  # %bb.9: # %cond.store72151; RV64ZVE32F-NEXT:    vmv.x.s a2, v102152; RV64ZVE32F-NEXT:    zext.b a2, a22153; RV64ZVE32F-NEXT:    slli a2, a2, 22154; RV64ZVE32F-NEXT:    add a2, a0, a22155; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma2156; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 42157; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma2158; RV64ZVE32F-NEXT:    vse32.v v12, (a2)2159; RV64ZVE32F-NEXT:  .LBB31_10: # %else82160; RV64ZVE32F-NEXT:    andi a2, a1, 322161; RV64ZVE32F-NEXT:    beqz a2, .LBB31_122162; RV64ZVE32F-NEXT:  # %bb.11: # %cond.store92163; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma2164; RV64ZVE32F-NEXT:    vslidedown.vi v11, v10, 12165; RV64ZVE32F-NEXT:    vmv.x.s a2, v112166; RV64ZVE32F-NEXT:    zext.b a2, a22167; RV64ZVE32F-NEXT:    slli a2, a2, 22168; RV64ZVE32F-NEXT:    add a2, a0, a22169; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma2170; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 52171; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma2172; RV64ZVE32F-NEXT:    vse32.v v12, (a2)2173; RV64ZVE32F-NEXT:  .LBB31_12: # %else102174; RV64ZVE32F-NEXT:    andi a2, a1, 642175; RV64ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma2176; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 22177; RV64ZVE32F-NEXT:    bnez a2, .LBB31_152178; RV64ZVE32F-NEXT:  # %bb.13: # %else122179; RV64ZVE32F-NEXT:    andi a1, a1, -1282180; RV64ZVE32F-NEXT:    bnez a1, .LBB31_162181; RV64ZVE32F-NEXT:  .LBB31_14: # %else142182; RV64ZVE32F-NEXT:    ret2183; RV64ZVE32F-NEXT:  .LBB31_15: # %cond.store112184; RV64ZVE32F-NEXT:    vmv.x.s a2, v102185; RV64ZVE32F-NEXT:    zext.b a2, a22186; RV64ZVE32F-NEXT:    slli a2, a2, 22187; RV64ZVE32F-NEXT:    add a2, a0, a22188; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma2189; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 62190; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma2191; RV64ZVE32F-NEXT:    vse32.v v12, (a2)2192; RV64ZVE32F-NEXT:    andi a1, a1, -1282193; RV64ZVE32F-NEXT:    beqz a1, .LBB31_142194; RV64ZVE32F-NEXT:  .LBB31_16: # %cond.store132195; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma2196; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 12197; RV64ZVE32F-NEXT:    vmv.x.s a1, v102198; RV64ZVE32F-NEXT:    zext.b a1, a12199; RV64ZVE32F-NEXT:    slli a1, a1, 22200; RV64ZVE32F-NEXT:    add a0, a0, a12201; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma2202; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 72203; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma2204; RV64ZVE32F-NEXT:    vse32.v v8, (a0)2205; RV64ZVE32F-NEXT:    ret2206  %eidxs = zext <8 x i8> %idxs to <8 x i32>2207  %ptrs = getelementptr inbounds i32, ptr %base, <8 x i32> %eidxs2208  call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> %val, <8 x ptr> %ptrs, i32 4, <8 x i1> %m)2209  ret void2210}2211 2212define void @mscatter_baseidx_v8i16_v8i32(<8 x i32> %val, ptr %base, <8 x i16> %idxs, <8 x i1> %m) {2213; RV32-LABEL: mscatter_baseidx_v8i16_v8i32:2214; RV32:       # %bb.0:2215; RV32-NEXT:    li a1, 42216; RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma2217; RV32-NEXT:    vwmulsu.vx v12, v10, a12218; RV32-NEXT:    vsetvli zero, zero, e32, m2, ta, ma2219; RV32-NEXT:    vsoxei32.v v8, (a0), v12, v0.t2220; RV32-NEXT:    ret2221;2222; RV64V-LABEL: mscatter_baseidx_v8i16_v8i32:2223; RV64V:       # %bb.0:2224; RV64V-NEXT:    vsetivli zero, 8, e64, m4, ta, ma2225; RV64V-NEXT:    vsext.vf4 v12, v102226; RV64V-NEXT:    vsll.vi v12, v12, 22227; RV64V-NEXT:    vsetvli zero, zero, e32, m2, ta, ma2228; RV64V-NEXT:    vsoxei64.v v8, (a0), v12, v0.t2229; RV64V-NEXT:    ret2230;2231; RV64ZVE32F-LABEL: mscatter_baseidx_v8i16_v8i32:2232; RV64ZVE32F:       # %bb.0:2233; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma2234; RV64ZVE32F-NEXT:    vmv.x.s a1, v02235; RV64ZVE32F-NEXT:    andi a2, a1, 12236; RV64ZVE32F-NEXT:    beqz a2, .LBB32_22237; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store2238; RV64ZVE32F-NEXT:    vsetvli zero, zero, e16, m2, ta, ma2239; RV64ZVE32F-NEXT:    vmv.x.s a2, v102240; RV64ZVE32F-NEXT:    slli a2, a2, 22241; RV64ZVE32F-NEXT:    add a2, a0, a22242; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma2243; RV64ZVE32F-NEXT:    vse32.v v8, (a2)2244; RV64ZVE32F-NEXT:  .LBB32_2: # %else2245; RV64ZVE32F-NEXT:    andi a2, a1, 22246; RV64ZVE32F-NEXT:    beqz a2, .LBB32_42247; RV64ZVE32F-NEXT:  # %bb.3: # %cond.store12248; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma2249; RV64ZVE32F-NEXT:    vslidedown.vi v11, v10, 12250; RV64ZVE32F-NEXT:    vmv.x.s a2, v112251; RV64ZVE32F-NEXT:    slli a2, a2, 22252; RV64ZVE32F-NEXT:    add a2, a0, a22253; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma2254; RV64ZVE32F-NEXT:    vslidedown.vi v11, v8, 12255; RV64ZVE32F-NEXT:    vse32.v v11, (a2)2256; RV64ZVE32F-NEXT:  .LBB32_4: # %else22257; RV64ZVE32F-NEXT:    andi a2, a1, 42258; RV64ZVE32F-NEXT:    vsetivli zero, 2, e16, mf2, ta, ma2259; RV64ZVE32F-NEXT:    vslidedown.vi v11, v10, 22260; RV64ZVE32F-NEXT:    beqz a2, .LBB32_62261; RV64ZVE32F-NEXT:  # %bb.5: # %cond.store32262; RV64ZVE32F-NEXT:    vmv.x.s a2, v112263; RV64ZVE32F-NEXT:    slli a2, a2, 22264; RV64ZVE32F-NEXT:    add a2, a0, a22265; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma2266; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 22267; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma2268; RV64ZVE32F-NEXT:    vse32.v v12, (a2)2269; RV64ZVE32F-NEXT:  .LBB32_6: # %else42270; RV64ZVE32F-NEXT:    andi a2, a1, 82271; RV64ZVE32F-NEXT:    beqz a2, .LBB32_82272; RV64ZVE32F-NEXT:  # %bb.7: # %cond.store52273; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma2274; RV64ZVE32F-NEXT:    vslidedown.vi v11, v11, 12275; RV64ZVE32F-NEXT:    vmv.x.s a2, v112276; RV64ZVE32F-NEXT:    slli a2, a2, 22277; RV64ZVE32F-NEXT:    add a2, a0, a22278; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma2279; RV64ZVE32F-NEXT:    vslidedown.vi v11, v8, 32280; RV64ZVE32F-NEXT:    vse32.v v11, (a2)2281; RV64ZVE32F-NEXT:  .LBB32_8: # %else62282; RV64ZVE32F-NEXT:    andi a2, a1, 162283; RV64ZVE32F-NEXT:    vsetivli zero, 4, e16, m1, ta, ma2284; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 42285; RV64ZVE32F-NEXT:    beqz a2, .LBB32_102286; RV64ZVE32F-NEXT:  # %bb.9: # %cond.store72287; RV64ZVE32F-NEXT:    vmv.x.s a2, v102288; RV64ZVE32F-NEXT:    slli a2, a2, 22289; RV64ZVE32F-NEXT:    add a2, a0, a22290; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma2291; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 42292; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma2293; RV64ZVE32F-NEXT:    vse32.v v12, (a2)2294; RV64ZVE32F-NEXT:  .LBB32_10: # %else82295; RV64ZVE32F-NEXT:    andi a2, a1, 322296; RV64ZVE32F-NEXT:    beqz a2, .LBB32_122297; RV64ZVE32F-NEXT:  # %bb.11: # %cond.store92298; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma2299; RV64ZVE32F-NEXT:    vslidedown.vi v11, v10, 12300; RV64ZVE32F-NEXT:    vmv.x.s a2, v112301; RV64ZVE32F-NEXT:    slli a2, a2, 22302; RV64ZVE32F-NEXT:    add a2, a0, a22303; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma2304; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 52305; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma2306; RV64ZVE32F-NEXT:    vse32.v v12, (a2)2307; RV64ZVE32F-NEXT:  .LBB32_12: # %else102308; RV64ZVE32F-NEXT:    andi a2, a1, 642309; RV64ZVE32F-NEXT:    vsetivli zero, 2, e16, mf2, ta, ma2310; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 22311; RV64ZVE32F-NEXT:    bnez a2, .LBB32_152312; RV64ZVE32F-NEXT:  # %bb.13: # %else122313; RV64ZVE32F-NEXT:    andi a1, a1, -1282314; RV64ZVE32F-NEXT:    bnez a1, .LBB32_162315; RV64ZVE32F-NEXT:  .LBB32_14: # %else142316; RV64ZVE32F-NEXT:    ret2317; RV64ZVE32F-NEXT:  .LBB32_15: # %cond.store112318; RV64ZVE32F-NEXT:    vmv.x.s a2, v102319; RV64ZVE32F-NEXT:    slli a2, a2, 22320; RV64ZVE32F-NEXT:    add a2, a0, a22321; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma2322; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 62323; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma2324; RV64ZVE32F-NEXT:    vse32.v v12, (a2)2325; RV64ZVE32F-NEXT:    andi a1, a1, -1282326; RV64ZVE32F-NEXT:    beqz a1, .LBB32_142327; RV64ZVE32F-NEXT:  .LBB32_16: # %cond.store132328; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma2329; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 12330; RV64ZVE32F-NEXT:    vmv.x.s a1, v102331; RV64ZVE32F-NEXT:    slli a1, a1, 22332; RV64ZVE32F-NEXT:    add a0, a0, a12333; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma2334; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 72335; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma2336; RV64ZVE32F-NEXT:    vse32.v v8, (a0)2337; RV64ZVE32F-NEXT:    ret2338  %ptrs = getelementptr inbounds i32, ptr %base, <8 x i16> %idxs2339  call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> %val, <8 x ptr> %ptrs, i32 4, <8 x i1> %m)2340  ret void2341}2342 2343define void @mscatter_baseidx_sext_v8i16_v8i32(<8 x i32> %val, ptr %base, <8 x i16> %idxs, <8 x i1> %m) {2344; RV32-LABEL: mscatter_baseidx_sext_v8i16_v8i32:2345; RV32:       # %bb.0:2346; RV32-NEXT:    li a1, 42347; RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma2348; RV32-NEXT:    vwmulsu.vx v12, v10, a12349; RV32-NEXT:    vsetvli zero, zero, e32, m2, ta, ma2350; RV32-NEXT:    vsoxei32.v v8, (a0), v12, v0.t2351; RV32-NEXT:    ret2352;2353; RV64V-LABEL: mscatter_baseidx_sext_v8i16_v8i32:2354; RV64V:       # %bb.0:2355; RV64V-NEXT:    vsetivli zero, 8, e64, m4, ta, ma2356; RV64V-NEXT:    vsext.vf4 v12, v102357; RV64V-NEXT:    vsll.vi v12, v12, 22358; RV64V-NEXT:    vsetvli zero, zero, e32, m2, ta, ma2359; RV64V-NEXT:    vsoxei64.v v8, (a0), v12, v0.t2360; RV64V-NEXT:    ret2361;2362; RV64ZVE32F-LABEL: mscatter_baseidx_sext_v8i16_v8i32:2363; RV64ZVE32F:       # %bb.0:2364; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma2365; RV64ZVE32F-NEXT:    vmv.x.s a1, v02366; RV64ZVE32F-NEXT:    andi a2, a1, 12367; RV64ZVE32F-NEXT:    beqz a2, .LBB33_22368; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store2369; RV64ZVE32F-NEXT:    vsetvli zero, zero, e16, m2, ta, ma2370; RV64ZVE32F-NEXT:    vmv.x.s a2, v102371; RV64ZVE32F-NEXT:    slli a2, a2, 22372; RV64ZVE32F-NEXT:    add a2, a0, a22373; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma2374; RV64ZVE32F-NEXT:    vse32.v v8, (a2)2375; RV64ZVE32F-NEXT:  .LBB33_2: # %else2376; RV64ZVE32F-NEXT:    andi a2, a1, 22377; RV64ZVE32F-NEXT:    beqz a2, .LBB33_42378; RV64ZVE32F-NEXT:  # %bb.3: # %cond.store12379; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma2380; RV64ZVE32F-NEXT:    vslidedown.vi v11, v10, 12381; RV64ZVE32F-NEXT:    vmv.x.s a2, v112382; RV64ZVE32F-NEXT:    slli a2, a2, 22383; RV64ZVE32F-NEXT:    add a2, a0, a22384; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma2385; RV64ZVE32F-NEXT:    vslidedown.vi v11, v8, 12386; RV64ZVE32F-NEXT:    vse32.v v11, (a2)2387; RV64ZVE32F-NEXT:  .LBB33_4: # %else22388; RV64ZVE32F-NEXT:    andi a2, a1, 42389; RV64ZVE32F-NEXT:    vsetivli zero, 2, e16, mf2, ta, ma2390; RV64ZVE32F-NEXT:    vslidedown.vi v11, v10, 22391; RV64ZVE32F-NEXT:    beqz a2, .LBB33_62392; RV64ZVE32F-NEXT:  # %bb.5: # %cond.store32393; RV64ZVE32F-NEXT:    vmv.x.s a2, v112394; RV64ZVE32F-NEXT:    slli a2, a2, 22395; RV64ZVE32F-NEXT:    add a2, a0, a22396; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma2397; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 22398; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma2399; RV64ZVE32F-NEXT:    vse32.v v12, (a2)2400; RV64ZVE32F-NEXT:  .LBB33_6: # %else42401; RV64ZVE32F-NEXT:    andi a2, a1, 82402; RV64ZVE32F-NEXT:    beqz a2, .LBB33_82403; RV64ZVE32F-NEXT:  # %bb.7: # %cond.store52404; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma2405; RV64ZVE32F-NEXT:    vslidedown.vi v11, v11, 12406; RV64ZVE32F-NEXT:    vmv.x.s a2, v112407; RV64ZVE32F-NEXT:    slli a2, a2, 22408; RV64ZVE32F-NEXT:    add a2, a0, a22409; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma2410; RV64ZVE32F-NEXT:    vslidedown.vi v11, v8, 32411; RV64ZVE32F-NEXT:    vse32.v v11, (a2)2412; RV64ZVE32F-NEXT:  .LBB33_8: # %else62413; RV64ZVE32F-NEXT:    andi a2, a1, 162414; RV64ZVE32F-NEXT:    vsetivli zero, 4, e16, m1, ta, ma2415; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 42416; RV64ZVE32F-NEXT:    beqz a2, .LBB33_102417; RV64ZVE32F-NEXT:  # %bb.9: # %cond.store72418; RV64ZVE32F-NEXT:    vmv.x.s a2, v102419; RV64ZVE32F-NEXT:    slli a2, a2, 22420; RV64ZVE32F-NEXT:    add a2, a0, a22421; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma2422; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 42423; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma2424; RV64ZVE32F-NEXT:    vse32.v v12, (a2)2425; RV64ZVE32F-NEXT:  .LBB33_10: # %else82426; RV64ZVE32F-NEXT:    andi a2, a1, 322427; RV64ZVE32F-NEXT:    beqz a2, .LBB33_122428; RV64ZVE32F-NEXT:  # %bb.11: # %cond.store92429; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma2430; RV64ZVE32F-NEXT:    vslidedown.vi v11, v10, 12431; RV64ZVE32F-NEXT:    vmv.x.s a2, v112432; RV64ZVE32F-NEXT:    slli a2, a2, 22433; RV64ZVE32F-NEXT:    add a2, a0, a22434; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma2435; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 52436; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma2437; RV64ZVE32F-NEXT:    vse32.v v12, (a2)2438; RV64ZVE32F-NEXT:  .LBB33_12: # %else102439; RV64ZVE32F-NEXT:    andi a2, a1, 642440; RV64ZVE32F-NEXT:    vsetivli zero, 2, e16, mf2, ta, ma2441; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 22442; RV64ZVE32F-NEXT:    bnez a2, .LBB33_152443; RV64ZVE32F-NEXT:  # %bb.13: # %else122444; RV64ZVE32F-NEXT:    andi a1, a1, -1282445; RV64ZVE32F-NEXT:    bnez a1, .LBB33_162446; RV64ZVE32F-NEXT:  .LBB33_14: # %else142447; RV64ZVE32F-NEXT:    ret2448; RV64ZVE32F-NEXT:  .LBB33_15: # %cond.store112449; RV64ZVE32F-NEXT:    vmv.x.s a2, v102450; RV64ZVE32F-NEXT:    slli a2, a2, 22451; RV64ZVE32F-NEXT:    add a2, a0, a22452; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma2453; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 62454; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma2455; RV64ZVE32F-NEXT:    vse32.v v12, (a2)2456; RV64ZVE32F-NEXT:    andi a1, a1, -1282457; RV64ZVE32F-NEXT:    beqz a1, .LBB33_142458; RV64ZVE32F-NEXT:  .LBB33_16: # %cond.store132459; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma2460; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 12461; RV64ZVE32F-NEXT:    vmv.x.s a1, v102462; RV64ZVE32F-NEXT:    slli a1, a1, 22463; RV64ZVE32F-NEXT:    add a0, a0, a12464; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma2465; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 72466; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma2467; RV64ZVE32F-NEXT:    vse32.v v8, (a0)2468; RV64ZVE32F-NEXT:    ret2469  %eidxs = sext <8 x i16> %idxs to <8 x i32>2470  %ptrs = getelementptr inbounds i32, ptr %base, <8 x i32> %eidxs2471  call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> %val, <8 x ptr> %ptrs, i32 4, <8 x i1> %m)2472  ret void2473}2474 2475define void @mscatter_baseidx_zext_v8i16_v8i32(<8 x i32> %val, ptr %base, <8 x i16> %idxs, <8 x i1> %m) {2476; RV32-LABEL: mscatter_baseidx_zext_v8i16_v8i32:2477; RV32:       # %bb.0:2478; RV32-NEXT:    li a1, 42479; RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma2480; RV32-NEXT:    vwmulu.vx v12, v10, a12481; RV32-NEXT:    vsetvli zero, zero, e32, m2, ta, ma2482; RV32-NEXT:    vsoxei32.v v8, (a0), v12, v0.t2483; RV32-NEXT:    ret2484;2485; RV64V-LABEL: mscatter_baseidx_zext_v8i16_v8i32:2486; RV64V:       # %bb.0:2487; RV64V-NEXT:    li a1, 42488; RV64V-NEXT:    vsetivli zero, 8, e16, m1, ta, ma2489; RV64V-NEXT:    vwmulu.vx v12, v10, a12490; RV64V-NEXT:    vsetvli zero, zero, e32, m2, ta, ma2491; RV64V-NEXT:    vsoxei32.v v8, (a0), v12, v0.t2492; RV64V-NEXT:    ret2493;2494; RV64ZVE32F-LABEL: mscatter_baseidx_zext_v8i16_v8i32:2495; RV64ZVE32F:       # %bb.0:2496; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma2497; RV64ZVE32F-NEXT:    vmv.x.s a1, v02498; RV64ZVE32F-NEXT:    andi a2, a1, 12499; RV64ZVE32F-NEXT:    beqz a2, .LBB34_22500; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store2501; RV64ZVE32F-NEXT:    vsetvli zero, zero, e16, m2, ta, ma2502; RV64ZVE32F-NEXT:    vmv.x.s a2, v102503; RV64ZVE32F-NEXT:    slli a2, a2, 482504; RV64ZVE32F-NEXT:    srli a2, a2, 462505; RV64ZVE32F-NEXT:    add a2, a0, a22506; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma2507; RV64ZVE32F-NEXT:    vse32.v v8, (a2)2508; RV64ZVE32F-NEXT:  .LBB34_2: # %else2509; RV64ZVE32F-NEXT:    andi a2, a1, 22510; RV64ZVE32F-NEXT:    beqz a2, .LBB34_42511; RV64ZVE32F-NEXT:  # %bb.3: # %cond.store12512; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma2513; RV64ZVE32F-NEXT:    vslidedown.vi v11, v10, 12514; RV64ZVE32F-NEXT:    vmv.x.s a2, v112515; RV64ZVE32F-NEXT:    slli a2, a2, 482516; RV64ZVE32F-NEXT:    srli a2, a2, 462517; RV64ZVE32F-NEXT:    add a2, a0, a22518; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma2519; RV64ZVE32F-NEXT:    vslidedown.vi v11, v8, 12520; RV64ZVE32F-NEXT:    vse32.v v11, (a2)2521; RV64ZVE32F-NEXT:  .LBB34_4: # %else22522; RV64ZVE32F-NEXT:    andi a2, a1, 42523; RV64ZVE32F-NEXT:    vsetivli zero, 2, e16, mf2, ta, ma2524; RV64ZVE32F-NEXT:    vslidedown.vi v11, v10, 22525; RV64ZVE32F-NEXT:    beqz a2, .LBB34_62526; RV64ZVE32F-NEXT:  # %bb.5: # %cond.store32527; RV64ZVE32F-NEXT:    vmv.x.s a2, v112528; RV64ZVE32F-NEXT:    slli a2, a2, 482529; RV64ZVE32F-NEXT:    srli a2, a2, 462530; RV64ZVE32F-NEXT:    add a2, a0, a22531; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma2532; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 22533; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma2534; RV64ZVE32F-NEXT:    vse32.v v12, (a2)2535; RV64ZVE32F-NEXT:  .LBB34_6: # %else42536; RV64ZVE32F-NEXT:    andi a2, a1, 82537; RV64ZVE32F-NEXT:    beqz a2, .LBB34_82538; RV64ZVE32F-NEXT:  # %bb.7: # %cond.store52539; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma2540; RV64ZVE32F-NEXT:    vslidedown.vi v11, v11, 12541; RV64ZVE32F-NEXT:    vmv.x.s a2, v112542; RV64ZVE32F-NEXT:    slli a2, a2, 482543; RV64ZVE32F-NEXT:    srli a2, a2, 462544; RV64ZVE32F-NEXT:    add a2, a0, a22545; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma2546; RV64ZVE32F-NEXT:    vslidedown.vi v11, v8, 32547; RV64ZVE32F-NEXT:    vse32.v v11, (a2)2548; RV64ZVE32F-NEXT:  .LBB34_8: # %else62549; RV64ZVE32F-NEXT:    andi a2, a1, 162550; RV64ZVE32F-NEXT:    vsetivli zero, 4, e16, m1, ta, ma2551; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 42552; RV64ZVE32F-NEXT:    beqz a2, .LBB34_102553; RV64ZVE32F-NEXT:  # %bb.9: # %cond.store72554; RV64ZVE32F-NEXT:    vmv.x.s a2, v102555; RV64ZVE32F-NEXT:    slli a2, a2, 482556; RV64ZVE32F-NEXT:    srli a2, a2, 462557; RV64ZVE32F-NEXT:    add a2, a0, a22558; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma2559; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 42560; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma2561; RV64ZVE32F-NEXT:    vse32.v v12, (a2)2562; RV64ZVE32F-NEXT:  .LBB34_10: # %else82563; RV64ZVE32F-NEXT:    andi a2, a1, 322564; RV64ZVE32F-NEXT:    beqz a2, .LBB34_122565; RV64ZVE32F-NEXT:  # %bb.11: # %cond.store92566; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma2567; RV64ZVE32F-NEXT:    vslidedown.vi v11, v10, 12568; RV64ZVE32F-NEXT:    vmv.x.s a2, v112569; RV64ZVE32F-NEXT:    slli a2, a2, 482570; RV64ZVE32F-NEXT:    srli a2, a2, 462571; RV64ZVE32F-NEXT:    add a2, a0, a22572; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma2573; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 52574; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma2575; RV64ZVE32F-NEXT:    vse32.v v12, (a2)2576; RV64ZVE32F-NEXT:  .LBB34_12: # %else102577; RV64ZVE32F-NEXT:    andi a2, a1, 642578; RV64ZVE32F-NEXT:    vsetivli zero, 2, e16, mf2, ta, ma2579; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 22580; RV64ZVE32F-NEXT:    bnez a2, .LBB34_152581; RV64ZVE32F-NEXT:  # %bb.13: # %else122582; RV64ZVE32F-NEXT:    andi a1, a1, -1282583; RV64ZVE32F-NEXT:    bnez a1, .LBB34_162584; RV64ZVE32F-NEXT:  .LBB34_14: # %else142585; RV64ZVE32F-NEXT:    ret2586; RV64ZVE32F-NEXT:  .LBB34_15: # %cond.store112587; RV64ZVE32F-NEXT:    vmv.x.s a2, v102588; RV64ZVE32F-NEXT:    slli a2, a2, 482589; RV64ZVE32F-NEXT:    srli a2, a2, 462590; RV64ZVE32F-NEXT:    add a2, a0, a22591; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma2592; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 62593; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma2594; RV64ZVE32F-NEXT:    vse32.v v12, (a2)2595; RV64ZVE32F-NEXT:    andi a1, a1, -1282596; RV64ZVE32F-NEXT:    beqz a1, .LBB34_142597; RV64ZVE32F-NEXT:  .LBB34_16: # %cond.store132598; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma2599; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 12600; RV64ZVE32F-NEXT:    vmv.x.s a1, v102601; RV64ZVE32F-NEXT:    slli a1, a1, 482602; RV64ZVE32F-NEXT:    srli a1, a1, 462603; RV64ZVE32F-NEXT:    add a0, a0, a12604; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma2605; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 72606; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma2607; RV64ZVE32F-NEXT:    vse32.v v8, (a0)2608; RV64ZVE32F-NEXT:    ret2609  %eidxs = zext <8 x i16> %idxs to <8 x i32>2610  %ptrs = getelementptr inbounds i32, ptr %base, <8 x i32> %eidxs2611  call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> %val, <8 x ptr> %ptrs, i32 4, <8 x i1> %m)2612  ret void2613}2614 2615define void @mscatter_baseidx_v8i32(<8 x i32> %val, ptr %base, <8 x i32> %idxs, <8 x i1> %m) {2616; RV32-LABEL: mscatter_baseidx_v8i32:2617; RV32:       # %bb.0:2618; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma2619; RV32-NEXT:    vsll.vi v10, v10, 22620; RV32-NEXT:    vsoxei32.v v8, (a0), v10, v0.t2621; RV32-NEXT:    ret2622;2623; RV64V-LABEL: mscatter_baseidx_v8i32:2624; RV64V:       # %bb.0:2625; RV64V-NEXT:    li a1, 42626; RV64V-NEXT:    vsetivli zero, 8, e32, m2, ta, ma2627; RV64V-NEXT:    vwmulsu.vx v12, v10, a12628; RV64V-NEXT:    vsoxei64.v v8, (a0), v12, v0.t2629; RV64V-NEXT:    ret2630;2631; RV64ZVE32F-LABEL: mscatter_baseidx_v8i32:2632; RV64ZVE32F:       # %bb.0:2633; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma2634; RV64ZVE32F-NEXT:    vmv.x.s a1, v02635; RV64ZVE32F-NEXT:    andi a2, a1, 12636; RV64ZVE32F-NEXT:    beqz a2, .LBB35_22637; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store2638; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma2639; RV64ZVE32F-NEXT:    vmv.x.s a2, v102640; RV64ZVE32F-NEXT:    slli a2, a2, 22641; RV64ZVE32F-NEXT:    add a2, a0, a22642; RV64ZVE32F-NEXT:    vse32.v v8, (a2)2643; RV64ZVE32F-NEXT:  .LBB35_2: # %else2644; RV64ZVE32F-NEXT:    andi a2, a1, 22645; RV64ZVE32F-NEXT:    beqz a2, .LBB35_42646; RV64ZVE32F-NEXT:  # %bb.3: # %cond.store12647; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma2648; RV64ZVE32F-NEXT:    vslidedown.vi v12, v10, 12649; RV64ZVE32F-NEXT:    vmv.x.s a2, v122650; RV64ZVE32F-NEXT:    slli a2, a2, 22651; RV64ZVE32F-NEXT:    add a2, a0, a22652; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 12653; RV64ZVE32F-NEXT:    vse32.v v12, (a2)2654; RV64ZVE32F-NEXT:  .LBB35_4: # %else22655; RV64ZVE32F-NEXT:    andi a2, a1, 42656; RV64ZVE32F-NEXT:    vsetivli zero, 2, e32, m1, ta, ma2657; RV64ZVE32F-NEXT:    vslidedown.vi v12, v10, 22658; RV64ZVE32F-NEXT:    beqz a2, .LBB35_62659; RV64ZVE32F-NEXT:  # %bb.5: # %cond.store32660; RV64ZVE32F-NEXT:    vmv.x.s a2, v122661; RV64ZVE32F-NEXT:    slli a2, a2, 22662; RV64ZVE32F-NEXT:    add a2, a0, a22663; RV64ZVE32F-NEXT:    vslidedown.vi v13, v8, 22664; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma2665; RV64ZVE32F-NEXT:    vse32.v v13, (a2)2666; RV64ZVE32F-NEXT:  .LBB35_6: # %else42667; RV64ZVE32F-NEXT:    andi a2, a1, 82668; RV64ZVE32F-NEXT:    vsetivli zero, 4, e32, m2, ta, ma2669; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 42670; RV64ZVE32F-NEXT:    bnez a2, .LBB35_132671; RV64ZVE32F-NEXT:  # %bb.7: # %else62672; RV64ZVE32F-NEXT:    andi a2, a1, 162673; RV64ZVE32F-NEXT:    bnez a2, .LBB35_142674; RV64ZVE32F-NEXT:  .LBB35_8: # %else82675; RV64ZVE32F-NEXT:    andi a2, a1, 322676; RV64ZVE32F-NEXT:    beqz a2, .LBB35_102677; RV64ZVE32F-NEXT:  .LBB35_9: # %cond.store92678; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma2679; RV64ZVE32F-NEXT:    vslidedown.vi v11, v10, 12680; RV64ZVE32F-NEXT:    vmv.x.s a2, v112681; RV64ZVE32F-NEXT:    slli a2, a2, 22682; RV64ZVE32F-NEXT:    add a2, a0, a22683; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma2684; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 52685; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma2686; RV64ZVE32F-NEXT:    vse32.v v12, (a2)2687; RV64ZVE32F-NEXT:  .LBB35_10: # %else102688; RV64ZVE32F-NEXT:    andi a2, a1, 642689; RV64ZVE32F-NEXT:    vsetivli zero, 2, e32, m1, ta, ma2690; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 22691; RV64ZVE32F-NEXT:    bnez a2, .LBB35_152692; RV64ZVE32F-NEXT:  # %bb.11: # %else122693; RV64ZVE32F-NEXT:    andi a1, a1, -1282694; RV64ZVE32F-NEXT:    bnez a1, .LBB35_162695; RV64ZVE32F-NEXT:  .LBB35_12: # %else142696; RV64ZVE32F-NEXT:    ret2697; RV64ZVE32F-NEXT:  .LBB35_13: # %cond.store52698; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma2699; RV64ZVE32F-NEXT:    vslidedown.vi v11, v12, 12700; RV64ZVE32F-NEXT:    vmv.x.s a2, v112701; RV64ZVE32F-NEXT:    slli a2, a2, 22702; RV64ZVE32F-NEXT:    add a2, a0, a22703; RV64ZVE32F-NEXT:    vslidedown.vi v11, v8, 32704; RV64ZVE32F-NEXT:    vse32.v v11, (a2)2705; RV64ZVE32F-NEXT:    andi a2, a1, 162706; RV64ZVE32F-NEXT:    beqz a2, .LBB35_82707; RV64ZVE32F-NEXT:  .LBB35_14: # %cond.store72708; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma2709; RV64ZVE32F-NEXT:    vmv.x.s a2, v102710; RV64ZVE32F-NEXT:    slli a2, a2, 22711; RV64ZVE32F-NEXT:    add a2, a0, a22712; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 42713; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma2714; RV64ZVE32F-NEXT:    vse32.v v12, (a2)2715; RV64ZVE32F-NEXT:    andi a2, a1, 322716; RV64ZVE32F-NEXT:    bnez a2, .LBB35_92717; RV64ZVE32F-NEXT:    j .LBB35_102718; RV64ZVE32F-NEXT:  .LBB35_15: # %cond.store112719; RV64ZVE32F-NEXT:    vmv.x.s a2, v102720; RV64ZVE32F-NEXT:    slli a2, a2, 22721; RV64ZVE32F-NEXT:    add a2, a0, a22722; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma2723; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 62724; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma2725; RV64ZVE32F-NEXT:    vse32.v v12, (a2)2726; RV64ZVE32F-NEXT:    andi a1, a1, -1282727; RV64ZVE32F-NEXT:    beqz a1, .LBB35_122728; RV64ZVE32F-NEXT:  .LBB35_16: # %cond.store132729; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma2730; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 12731; RV64ZVE32F-NEXT:    vmv.x.s a1, v102732; RV64ZVE32F-NEXT:    slli a1, a1, 22733; RV64ZVE32F-NEXT:    add a0, a0, a12734; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma2735; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 72736; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma2737; RV64ZVE32F-NEXT:    vse32.v v8, (a0)2738; RV64ZVE32F-NEXT:    ret2739  %ptrs = getelementptr inbounds i32, ptr %base, <8 x i32> %idxs2740  call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> %val, <8 x ptr> %ptrs, i32 4, <8 x i1> %m)2741  ret void2742}2743 2744define void @mscatter_v1i64(<1 x i64> %val, <1 x ptr> %ptrs, <1 x i1> %m) {2745; RV32V-LABEL: mscatter_v1i64:2746; RV32V:       # %bb.0:2747; RV32V-NEXT:    vsetivli zero, 1, e64, m1, ta, ma2748; RV32V-NEXT:    vsoxei32.v v8, (zero), v9, v0.t2749; RV32V-NEXT:    ret2750;2751; RV64V-LABEL: mscatter_v1i64:2752; RV64V:       # %bb.0:2753; RV64V-NEXT:    vsetivli zero, 1, e64, m1, ta, ma2754; RV64V-NEXT:    vsoxei64.v v8, (zero), v9, v0.t2755; RV64V-NEXT:    ret2756;2757; RV32ZVE32F-LABEL: mscatter_v1i64:2758; RV32ZVE32F:       # %bb.0:2759; RV32ZVE32F-NEXT:    vsetvli a2, zero, e8, mf4, ta, ma2760; RV32ZVE32F-NEXT:    vfirst.m a2, v02761; RV32ZVE32F-NEXT:    bnez a2, .LBB36_22762; RV32ZVE32F-NEXT:  # %bb.1: # %cond.store2763; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma2764; RV32ZVE32F-NEXT:    vmv.x.s a2, v82765; RV32ZVE32F-NEXT:    sw a0, 0(a2)2766; RV32ZVE32F-NEXT:    sw a1, 4(a2)2767; RV32ZVE32F-NEXT:  .LBB36_2: # %else2768; RV32ZVE32F-NEXT:    ret2769;2770; RV64ZVE32F-LABEL: mscatter_v1i64:2771; RV64ZVE32F:       # %bb.0:2772; RV64ZVE32F-NEXT:    vsetvli a2, zero, e8, mf4, ta, ma2773; RV64ZVE32F-NEXT:    vfirst.m a2, v02774; RV64ZVE32F-NEXT:    bnez a2, .LBB36_22775; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store2776; RV64ZVE32F-NEXT:    sd a0, 0(a1)2777; RV64ZVE32F-NEXT:  .LBB36_2: # %else2778; RV64ZVE32F-NEXT:    ret2779  call void @llvm.masked.scatter.v1i64.v1p0(<1 x i64> %val, <1 x ptr> %ptrs, i32 8, <1 x i1> %m)2780  ret void2781}2782 2783define void @mscatter_v2i64(<2 x i64> %val, <2 x ptr> %ptrs, <2 x i1> %m) {2784; RV32V-LABEL: mscatter_v2i64:2785; RV32V:       # %bb.0:2786; RV32V-NEXT:    vsetivli zero, 2, e64, m1, ta, ma2787; RV32V-NEXT:    vsoxei32.v v8, (zero), v9, v0.t2788; RV32V-NEXT:    ret2789;2790; RV64V-LABEL: mscatter_v2i64:2791; RV64V:       # %bb.0:2792; RV64V-NEXT:    vsetivli zero, 2, e64, m1, ta, ma2793; RV64V-NEXT:    vsoxei64.v v8, (zero), v9, v0.t2794; RV64V-NEXT:    ret2795;2796; RV32ZVE32F-LABEL: mscatter_v2i64:2797; RV32ZVE32F:       # %bb.0:2798; RV32ZVE32F-NEXT:    lw a1, 8(a0)2799; RV32ZVE32F-NEXT:    lw a2, 12(a0)2800; RV32ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma2801; RV32ZVE32F-NEXT:    vmv.x.s a3, v02802; RV32ZVE32F-NEXT:    andi a4, a3, 12803; RV32ZVE32F-NEXT:    bnez a4, .LBB37_32804; RV32ZVE32F-NEXT:  # %bb.1: # %else2805; RV32ZVE32F-NEXT:    andi a3, a3, 22806; RV32ZVE32F-NEXT:    bnez a3, .LBB37_42807; RV32ZVE32F-NEXT:  .LBB37_2: # %else22808; RV32ZVE32F-NEXT:    ret2809; RV32ZVE32F-NEXT:  .LBB37_3: # %cond.store2810; RV32ZVE32F-NEXT:    lw a4, 0(a0)2811; RV32ZVE32F-NEXT:    lw a0, 4(a0)2812; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m4, ta, ma2813; RV32ZVE32F-NEXT:    vmv.x.s a5, v82814; RV32ZVE32F-NEXT:    sw a4, 0(a5)2815; RV32ZVE32F-NEXT:    sw a0, 4(a5)2816; RV32ZVE32F-NEXT:    andi a3, a3, 22817; RV32ZVE32F-NEXT:    beqz a3, .LBB37_22818; RV32ZVE32F-NEXT:  .LBB37_4: # %cond.store12819; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma2820; RV32ZVE32F-NEXT:    vslidedown.vi v8, v8, 12821; RV32ZVE32F-NEXT:    vmv.x.s a0, v82822; RV32ZVE32F-NEXT:    sw a1, 0(a0)2823; RV32ZVE32F-NEXT:    sw a2, 4(a0)2824; RV32ZVE32F-NEXT:    ret2825;2826; RV64ZVE32F-LABEL: mscatter_v2i64:2827; RV64ZVE32F:       # %bb.0:2828; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma2829; RV64ZVE32F-NEXT:    vmv.x.s a4, v02830; RV64ZVE32F-NEXT:    andi a5, a4, 12831; RV64ZVE32F-NEXT:    bnez a5, .LBB37_32832; RV64ZVE32F-NEXT:  # %bb.1: # %else2833; RV64ZVE32F-NEXT:    andi a4, a4, 22834; RV64ZVE32F-NEXT:    bnez a4, .LBB37_42835; RV64ZVE32F-NEXT:  .LBB37_2: # %else22836; RV64ZVE32F-NEXT:    ret2837; RV64ZVE32F-NEXT:  .LBB37_3: # %cond.store2838; RV64ZVE32F-NEXT:    sd a0, 0(a2)2839; RV64ZVE32F-NEXT:    andi a4, a4, 22840; RV64ZVE32F-NEXT:    beqz a4, .LBB37_22841; RV64ZVE32F-NEXT:  .LBB37_4: # %cond.store12842; RV64ZVE32F-NEXT:    sd a1, 0(a3)2843; RV64ZVE32F-NEXT:    ret2844  call void @llvm.masked.scatter.v2i64.v2p0(<2 x i64> %val, <2 x ptr> %ptrs, i32 8, <2 x i1> %m)2845  ret void2846}2847 2848define void @mscatter_v4i64(<4 x i64> %val, <4 x ptr> %ptrs, <4 x i1> %m) {2849; RV32V-LABEL: mscatter_v4i64:2850; RV32V:       # %bb.0:2851; RV32V-NEXT:    vsetivli zero, 4, e64, m2, ta, ma2852; RV32V-NEXT:    vsoxei32.v v8, (zero), v10, v0.t2853; RV32V-NEXT:    ret2854;2855; RV64V-LABEL: mscatter_v4i64:2856; RV64V:       # %bb.0:2857; RV64V-NEXT:    vsetivli zero, 4, e64, m2, ta, ma2858; RV64V-NEXT:    vsoxei64.v v8, (zero), v10, v0.t2859; RV64V-NEXT:    ret2860;2861; RV32ZVE32F-LABEL: mscatter_v4i64:2862; RV32ZVE32F:       # %bb.0:2863; RV32ZVE32F-NEXT:    lw a1, 24(a0)2864; RV32ZVE32F-NEXT:    lw a2, 28(a0)2865; RV32ZVE32F-NEXT:    lw a6, 8(a0)2866; RV32ZVE32F-NEXT:    lw a7, 12(a0)2867; RV32ZVE32F-NEXT:    lw a3, 16(a0)2868; RV32ZVE32F-NEXT:    lw a4, 20(a0)2869; RV32ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma2870; RV32ZVE32F-NEXT:    vmv.x.s a5, v02871; RV32ZVE32F-NEXT:    andi t0, a5, 12872; RV32ZVE32F-NEXT:    bnez t0, .LBB38_52873; RV32ZVE32F-NEXT:  # %bb.1: # %else2874; RV32ZVE32F-NEXT:    andi a0, a5, 22875; RV32ZVE32F-NEXT:    bnez a0, .LBB38_62876; RV32ZVE32F-NEXT:  .LBB38_2: # %else22877; RV32ZVE32F-NEXT:    andi a0, a5, 42878; RV32ZVE32F-NEXT:    bnez a0, .LBB38_72879; RV32ZVE32F-NEXT:  .LBB38_3: # %else42880; RV32ZVE32F-NEXT:    andi a5, a5, 82881; RV32ZVE32F-NEXT:    bnez a5, .LBB38_82882; RV32ZVE32F-NEXT:  .LBB38_4: # %else62883; RV32ZVE32F-NEXT:    ret2884; RV32ZVE32F-NEXT:  .LBB38_5: # %cond.store2885; RV32ZVE32F-NEXT:    lw t0, 0(a0)2886; RV32ZVE32F-NEXT:    lw a0, 4(a0)2887; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m4, ta, ma2888; RV32ZVE32F-NEXT:    vmv.x.s t1, v82889; RV32ZVE32F-NEXT:    sw t0, 0(t1)2890; RV32ZVE32F-NEXT:    sw a0, 4(t1)2891; RV32ZVE32F-NEXT:    andi a0, a5, 22892; RV32ZVE32F-NEXT:    beqz a0, .LBB38_22893; RV32ZVE32F-NEXT:  .LBB38_6: # %cond.store12894; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma2895; RV32ZVE32F-NEXT:    vslidedown.vi v9, v8, 12896; RV32ZVE32F-NEXT:    vmv.x.s a0, v92897; RV32ZVE32F-NEXT:    sw a6, 0(a0)2898; RV32ZVE32F-NEXT:    sw a7, 4(a0)2899; RV32ZVE32F-NEXT:    andi a0, a5, 42900; RV32ZVE32F-NEXT:    beqz a0, .LBB38_32901; RV32ZVE32F-NEXT:  .LBB38_7: # %cond.store32902; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma2903; RV32ZVE32F-NEXT:    vslidedown.vi v9, v8, 22904; RV32ZVE32F-NEXT:    vmv.x.s a0, v92905; RV32ZVE32F-NEXT:    sw a3, 0(a0)2906; RV32ZVE32F-NEXT:    sw a4, 4(a0)2907; RV32ZVE32F-NEXT:    andi a5, a5, 82908; RV32ZVE32F-NEXT:    beqz a5, .LBB38_42909; RV32ZVE32F-NEXT:  .LBB38_8: # %cond.store52910; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma2911; RV32ZVE32F-NEXT:    vslidedown.vi v8, v8, 32912; RV32ZVE32F-NEXT:    vmv.x.s a0, v82913; RV32ZVE32F-NEXT:    sw a1, 0(a0)2914; RV32ZVE32F-NEXT:    sw a2, 4(a0)2915; RV32ZVE32F-NEXT:    ret2916;2917; RV64ZVE32F-LABEL: mscatter_v4i64:2918; RV64ZVE32F:       # %bb.0:2919; RV64ZVE32F-NEXT:    ld a6, 8(a1)2920; RV64ZVE32F-NEXT:    ld a4, 16(a1)2921; RV64ZVE32F-NEXT:    ld a2, 24(a1)2922; RV64ZVE32F-NEXT:    ld t0, 8(a0)2923; RV64ZVE32F-NEXT:    ld a5, 16(a0)2924; RV64ZVE32F-NEXT:    ld a3, 24(a0)2925; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma2926; RV64ZVE32F-NEXT:    vmv.x.s a7, v02927; RV64ZVE32F-NEXT:    andi t1, a7, 12928; RV64ZVE32F-NEXT:    bnez t1, .LBB38_52929; RV64ZVE32F-NEXT:  # %bb.1: # %else2930; RV64ZVE32F-NEXT:    andi a0, a7, 22931; RV64ZVE32F-NEXT:    bnez a0, .LBB38_62932; RV64ZVE32F-NEXT:  .LBB38_2: # %else22933; RV64ZVE32F-NEXT:    andi a0, a7, 42934; RV64ZVE32F-NEXT:    bnez a0, .LBB38_72935; RV64ZVE32F-NEXT:  .LBB38_3: # %else42936; RV64ZVE32F-NEXT:    andi a0, a7, 82937; RV64ZVE32F-NEXT:    bnez a0, .LBB38_82938; RV64ZVE32F-NEXT:  .LBB38_4: # %else62939; RV64ZVE32F-NEXT:    ret2940; RV64ZVE32F-NEXT:  .LBB38_5: # %cond.store2941; RV64ZVE32F-NEXT:    ld a1, 0(a1)2942; RV64ZVE32F-NEXT:    ld a0, 0(a0)2943; RV64ZVE32F-NEXT:    sd a0, 0(a1)2944; RV64ZVE32F-NEXT:    andi a0, a7, 22945; RV64ZVE32F-NEXT:    beqz a0, .LBB38_22946; RV64ZVE32F-NEXT:  .LBB38_6: # %cond.store12947; RV64ZVE32F-NEXT:    sd t0, 0(a6)2948; RV64ZVE32F-NEXT:    andi a0, a7, 42949; RV64ZVE32F-NEXT:    beqz a0, .LBB38_32950; RV64ZVE32F-NEXT:  .LBB38_7: # %cond.store32951; RV64ZVE32F-NEXT:    sd a5, 0(a4)2952; RV64ZVE32F-NEXT:    andi a0, a7, 82953; RV64ZVE32F-NEXT:    beqz a0, .LBB38_42954; RV64ZVE32F-NEXT:  .LBB38_8: # %cond.store52955; RV64ZVE32F-NEXT:    sd a3, 0(a2)2956; RV64ZVE32F-NEXT:    ret2957  call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> %val, <4 x ptr> %ptrs, i32 8, <4 x i1> %m)2958  ret void2959}2960 2961define void @mscatter_truemask_v4i64(<4 x i64> %val, <4 x ptr> %ptrs) {2962; RV32V-LABEL: mscatter_truemask_v4i64:2963; RV32V:       # %bb.0:2964; RV32V-NEXT:    vsetivli zero, 4, e64, m2, ta, ma2965; RV32V-NEXT:    vsoxei32.v v8, (zero), v102966; RV32V-NEXT:    ret2967;2968; RV64V-LABEL: mscatter_truemask_v4i64:2969; RV64V:       # %bb.0:2970; RV64V-NEXT:    vsetivli zero, 4, e64, m2, ta, ma2971; RV64V-NEXT:    vsoxei64.v v8, (zero), v102972; RV64V-NEXT:    ret2973;2974; RV32ZVE32F-LABEL: mscatter_truemask_v4i64:2975; RV32ZVE32F:       # %bb.0:2976; RV32ZVE32F-NEXT:    lw a1, 16(a0)2977; RV32ZVE32F-NEXT:    lw a2, 20(a0)2978; RV32ZVE32F-NEXT:    lw a3, 24(a0)2979; RV32ZVE32F-NEXT:    lw a4, 28(a0)2980; RV32ZVE32F-NEXT:    lw a5, 0(a0)2981; RV32ZVE32F-NEXT:    lw a6, 4(a0)2982; RV32ZVE32F-NEXT:    lw a7, 8(a0)2983; RV32ZVE32F-NEXT:    lw a0, 12(a0)2984; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma2985; RV32ZVE32F-NEXT:    vmv.x.s t0, v82986; RV32ZVE32F-NEXT:    vslidedown.vi v9, v8, 12987; RV32ZVE32F-NEXT:    vmv.x.s t1, v92988; RV32ZVE32F-NEXT:    vslidedown.vi v9, v8, 22989; RV32ZVE32F-NEXT:    vslidedown.vi v8, v8, 32990; RV32ZVE32F-NEXT:    sw a5, 0(t0)2991; RV32ZVE32F-NEXT:    sw a6, 4(t0)2992; RV32ZVE32F-NEXT:    vmv.x.s a5, v92993; RV32ZVE32F-NEXT:    vmv.x.s a6, v82994; RV32ZVE32F-NEXT:    sw a7, 0(t1)2995; RV32ZVE32F-NEXT:    sw a0, 4(t1)2996; RV32ZVE32F-NEXT:    sw a1, 0(a5)2997; RV32ZVE32F-NEXT:    sw a2, 4(a5)2998; RV32ZVE32F-NEXT:    sw a3, 0(a6)2999; RV32ZVE32F-NEXT:    sw a4, 4(a6)3000; RV32ZVE32F-NEXT:    ret3001;3002; RV64ZVE32F-LABEL: mscatter_truemask_v4i64:3003; RV64ZVE32F:       # %bb.0:3004; RV64ZVE32F-NEXT:    ld a2, 0(a1)3005; RV64ZVE32F-NEXT:    ld a3, 8(a1)3006; RV64ZVE32F-NEXT:    ld a4, 16(a1)3007; RV64ZVE32F-NEXT:    ld a1, 24(a1)3008; RV64ZVE32F-NEXT:    ld a5, 0(a0)3009; RV64ZVE32F-NEXT:    ld a6, 8(a0)3010; RV64ZVE32F-NEXT:    ld a7, 16(a0)3011; RV64ZVE32F-NEXT:    ld a0, 24(a0)3012; RV64ZVE32F-NEXT:    sd a5, 0(a2)3013; RV64ZVE32F-NEXT:    sd a6, 0(a3)3014; RV64ZVE32F-NEXT:    sd a7, 0(a4)3015; RV64ZVE32F-NEXT:    sd a0, 0(a1)3016; RV64ZVE32F-NEXT:    ret3017  call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> %val, <4 x ptr> %ptrs, i32 8, <4 x i1> splat (i1 1))3018  ret void3019}3020 3021define void @mscatter_falsemask_v4i64(<4 x i64> %val, <4 x ptr> %ptrs) {3022; CHECK-LABEL: mscatter_falsemask_v4i64:3023; CHECK:       # %bb.0:3024; CHECK-NEXT:    ret3025  call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> %val, <4 x ptr> %ptrs, i32 8, <4 x i1> zeroinitializer)3026  ret void3027}3028 3029define void @mscatter_v8i64(<8 x i64> %val, <8 x ptr> %ptrs, <8 x i1> %m) {3030; RV32V-LABEL: mscatter_v8i64:3031; RV32V:       # %bb.0:3032; RV32V-NEXT:    vsetivli zero, 8, e64, m4, ta, ma3033; RV32V-NEXT:    vsoxei32.v v8, (zero), v12, v0.t3034; RV32V-NEXT:    ret3035;3036; RV64V-LABEL: mscatter_v8i64:3037; RV64V:       # %bb.0:3038; RV64V-NEXT:    vsetivli zero, 8, e64, m4, ta, ma3039; RV64V-NEXT:    vsoxei64.v v8, (zero), v12, v0.t3040; RV64V-NEXT:    ret3041;3042; RV32ZVE32F-LABEL: mscatter_v8i64:3043; RV32ZVE32F:       # %bb.0:3044; RV32ZVE32F-NEXT:    addi sp, sp, -163045; RV32ZVE32F-NEXT:    .cfi_def_cfa_offset 163046; RV32ZVE32F-NEXT:    sw s0, 12(sp) # 4-byte Folded Spill3047; RV32ZVE32F-NEXT:    sw s1, 8(sp) # 4-byte Folded Spill3048; RV32ZVE32F-NEXT:    sw s2, 4(sp) # 4-byte Folded Spill3049; RV32ZVE32F-NEXT:    .cfi_offset s0, -43050; RV32ZVE32F-NEXT:    .cfi_offset s1, -83051; RV32ZVE32F-NEXT:    .cfi_offset s2, -123052; RV32ZVE32F-NEXT:    .cfi_remember_state3053; RV32ZVE32F-NEXT:    lw a1, 56(a0)3054; RV32ZVE32F-NEXT:    lw a2, 60(a0)3055; RV32ZVE32F-NEXT:    lw a5, 40(a0)3056; RV32ZVE32F-NEXT:    lw a6, 44(a0)3057; RV32ZVE32F-NEXT:    lw a3, 48(a0)3058; RV32ZVE32F-NEXT:    lw a4, 52(a0)3059; RV32ZVE32F-NEXT:    lw t2, 24(a0)3060; RV32ZVE32F-NEXT:    lw t3, 28(a0)3061; RV32ZVE32F-NEXT:    lw t0, 32(a0)3062; RV32ZVE32F-NEXT:    lw t1, 36(a0)3063; RV32ZVE32F-NEXT:    lw t6, 8(a0)3064; RV32ZVE32F-NEXT:    lw s0, 12(a0)3065; RV32ZVE32F-NEXT:    lw t4, 16(a0)3066; RV32ZVE32F-NEXT:    lw t5, 20(a0)3067; RV32ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma3068; RV32ZVE32F-NEXT:    vmv.x.s a7, v03069; RV32ZVE32F-NEXT:    andi s1, a7, 13070; RV32ZVE32F-NEXT:    bnez s1, .LBB41_103071; RV32ZVE32F-NEXT:  # %bb.1: # %else3072; RV32ZVE32F-NEXT:    andi a0, a7, 23073; RV32ZVE32F-NEXT:    bnez a0, .LBB41_113074; RV32ZVE32F-NEXT:  .LBB41_2: # %else23075; RV32ZVE32F-NEXT:    andi a0, a7, 43076; RV32ZVE32F-NEXT:    bnez a0, .LBB41_123077; RV32ZVE32F-NEXT:  .LBB41_3: # %else43078; RV32ZVE32F-NEXT:    andi a0, a7, 83079; RV32ZVE32F-NEXT:    bnez a0, .LBB41_133080; RV32ZVE32F-NEXT:  .LBB41_4: # %else63081; RV32ZVE32F-NEXT:    andi a0, a7, 163082; RV32ZVE32F-NEXT:    bnez a0, .LBB41_143083; RV32ZVE32F-NEXT:  .LBB41_5: # %else83084; RV32ZVE32F-NEXT:    andi a0, a7, 323085; RV32ZVE32F-NEXT:    bnez a0, .LBB41_153086; RV32ZVE32F-NEXT:  .LBB41_6: # %else103087; RV32ZVE32F-NEXT:    andi a0, a7, 643088; RV32ZVE32F-NEXT:    bnez a0, .LBB41_163089; RV32ZVE32F-NEXT:  .LBB41_7: # %else123090; RV32ZVE32F-NEXT:    andi a0, a7, -1283091; RV32ZVE32F-NEXT:    beqz a0, .LBB41_93092; RV32ZVE32F-NEXT:  .LBB41_8: # %cond.store133093; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma3094; RV32ZVE32F-NEXT:    vslidedown.vi v8, v8, 73095; RV32ZVE32F-NEXT:    vmv.x.s a0, v83096; RV32ZVE32F-NEXT:    sw a1, 0(a0)3097; RV32ZVE32F-NEXT:    sw a2, 4(a0)3098; RV32ZVE32F-NEXT:  .LBB41_9: # %else143099; RV32ZVE32F-NEXT:    lw s0, 12(sp) # 4-byte Folded Reload3100; RV32ZVE32F-NEXT:    lw s1, 8(sp) # 4-byte Folded Reload3101; RV32ZVE32F-NEXT:    lw s2, 4(sp) # 4-byte Folded Reload3102; RV32ZVE32F-NEXT:    .cfi_restore s03103; RV32ZVE32F-NEXT:    .cfi_restore s13104; RV32ZVE32F-NEXT:    .cfi_restore s23105; RV32ZVE32F-NEXT:    addi sp, sp, 163106; RV32ZVE32F-NEXT:    .cfi_def_cfa_offset 03107; RV32ZVE32F-NEXT:    ret3108; RV32ZVE32F-NEXT:  .LBB41_10: # %cond.store3109; RV32ZVE32F-NEXT:    .cfi_restore_state3110; RV32ZVE32F-NEXT:    lw s1, 0(a0)3111; RV32ZVE32F-NEXT:    lw a0, 4(a0)3112; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m4, ta, ma3113; RV32ZVE32F-NEXT:    vmv.x.s s2, v83114; RV32ZVE32F-NEXT:    sw s1, 0(s2)3115; RV32ZVE32F-NEXT:    sw a0, 4(s2)3116; RV32ZVE32F-NEXT:    andi a0, a7, 23117; RV32ZVE32F-NEXT:    beqz a0, .LBB41_23118; RV32ZVE32F-NEXT:  .LBB41_11: # %cond.store13119; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma3120; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 13121; RV32ZVE32F-NEXT:    vmv.x.s a0, v103122; RV32ZVE32F-NEXT:    sw t6, 0(a0)3123; RV32ZVE32F-NEXT:    sw s0, 4(a0)3124; RV32ZVE32F-NEXT:    andi a0, a7, 43125; RV32ZVE32F-NEXT:    beqz a0, .LBB41_33126; RV32ZVE32F-NEXT:  .LBB41_12: # %cond.store33127; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma3128; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 23129; RV32ZVE32F-NEXT:    vmv.x.s a0, v103130; RV32ZVE32F-NEXT:    sw t4, 0(a0)3131; RV32ZVE32F-NEXT:    sw t5, 4(a0)3132; RV32ZVE32F-NEXT:    andi a0, a7, 83133; RV32ZVE32F-NEXT:    beqz a0, .LBB41_43134; RV32ZVE32F-NEXT:  .LBB41_13: # %cond.store53135; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma3136; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 33137; RV32ZVE32F-NEXT:    vmv.x.s a0, v103138; RV32ZVE32F-NEXT:    sw t2, 0(a0)3139; RV32ZVE32F-NEXT:    sw t3, 4(a0)3140; RV32ZVE32F-NEXT:    andi a0, a7, 163141; RV32ZVE32F-NEXT:    beqz a0, .LBB41_53142; RV32ZVE32F-NEXT:  .LBB41_14: # %cond.store73143; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma3144; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 43145; RV32ZVE32F-NEXT:    vmv.x.s a0, v103146; RV32ZVE32F-NEXT:    sw t0, 0(a0)3147; RV32ZVE32F-NEXT:    sw t1, 4(a0)3148; RV32ZVE32F-NEXT:    andi a0, a7, 323149; RV32ZVE32F-NEXT:    beqz a0, .LBB41_63150; RV32ZVE32F-NEXT:  .LBB41_15: # %cond.store93151; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma3152; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 53153; RV32ZVE32F-NEXT:    vmv.x.s a0, v103154; RV32ZVE32F-NEXT:    sw a5, 0(a0)3155; RV32ZVE32F-NEXT:    sw a6, 4(a0)3156; RV32ZVE32F-NEXT:    andi a0, a7, 643157; RV32ZVE32F-NEXT:    beqz a0, .LBB41_73158; RV32ZVE32F-NEXT:  .LBB41_16: # %cond.store113159; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma3160; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 63161; RV32ZVE32F-NEXT:    vmv.x.s a0, v103162; RV32ZVE32F-NEXT:    sw a3, 0(a0)3163; RV32ZVE32F-NEXT:    sw a4, 4(a0)3164; RV32ZVE32F-NEXT:    andi a0, a7, -1283165; RV32ZVE32F-NEXT:    bnez a0, .LBB41_83166; RV32ZVE32F-NEXT:    j .LBB41_93167;3168; RV64ZVE32F-LABEL: mscatter_v8i64:3169; RV64ZVE32F:       # %bb.0:3170; RV64ZVE32F-NEXT:    addi sp, sp, -323171; RV64ZVE32F-NEXT:    .cfi_def_cfa_offset 323172; RV64ZVE32F-NEXT:    sd s0, 24(sp) # 8-byte Folded Spill3173; RV64ZVE32F-NEXT:    sd s1, 16(sp) # 8-byte Folded Spill3174; RV64ZVE32F-NEXT:    sd s2, 8(sp) # 8-byte Folded Spill3175; RV64ZVE32F-NEXT:    .cfi_offset s0, -83176; RV64ZVE32F-NEXT:    .cfi_offset s1, -163177; RV64ZVE32F-NEXT:    .cfi_offset s2, -243178; RV64ZVE32F-NEXT:    .cfi_remember_state3179; RV64ZVE32F-NEXT:    ld a4, 40(a1)3180; RV64ZVE32F-NEXT:    ld a3, 48(a1)3181; RV64ZVE32F-NEXT:    ld a2, 56(a1)3182; RV64ZVE32F-NEXT:    ld t5, 8(a1)3183; RV64ZVE32F-NEXT:    ld t3, 16(a1)3184; RV64ZVE32F-NEXT:    ld t2, 24(a1)3185; RV64ZVE32F-NEXT:    ld t0, 32(a1)3186; RV64ZVE32F-NEXT:    ld a7, 40(a0)3187; RV64ZVE32F-NEXT:    ld a6, 48(a0)3188; RV64ZVE32F-NEXT:    ld a5, 56(a0)3189; RV64ZVE32F-NEXT:    ld s1, 8(a0)3190; RV64ZVE32F-NEXT:    ld s0, 16(a0)3191; RV64ZVE32F-NEXT:    ld t6, 24(a0)3192; RV64ZVE32F-NEXT:    ld t4, 32(a0)3193; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma3194; RV64ZVE32F-NEXT:    vmv.x.s t1, v03195; RV64ZVE32F-NEXT:    andi s2, t1, 13196; RV64ZVE32F-NEXT:    bnez s2, .LBB41_103197; RV64ZVE32F-NEXT:  # %bb.1: # %else3198; RV64ZVE32F-NEXT:    andi a0, t1, 23199; RV64ZVE32F-NEXT:    bnez a0, .LBB41_113200; RV64ZVE32F-NEXT:  .LBB41_2: # %else23201; RV64ZVE32F-NEXT:    andi a0, t1, 43202; RV64ZVE32F-NEXT:    bnez a0, .LBB41_123203; RV64ZVE32F-NEXT:  .LBB41_3: # %else43204; RV64ZVE32F-NEXT:    andi a0, t1, 83205; RV64ZVE32F-NEXT:    bnez a0, .LBB41_133206; RV64ZVE32F-NEXT:  .LBB41_4: # %else63207; RV64ZVE32F-NEXT:    andi a0, t1, 163208; RV64ZVE32F-NEXT:    bnez a0, .LBB41_143209; RV64ZVE32F-NEXT:  .LBB41_5: # %else83210; RV64ZVE32F-NEXT:    andi a0, t1, 323211; RV64ZVE32F-NEXT:    bnez a0, .LBB41_153212; RV64ZVE32F-NEXT:  .LBB41_6: # %else103213; RV64ZVE32F-NEXT:    andi a0, t1, 643214; RV64ZVE32F-NEXT:    bnez a0, .LBB41_163215; RV64ZVE32F-NEXT:  .LBB41_7: # %else123216; RV64ZVE32F-NEXT:    andi a0, t1, -1283217; RV64ZVE32F-NEXT:    beqz a0, .LBB41_93218; RV64ZVE32F-NEXT:  .LBB41_8: # %cond.store133219; RV64ZVE32F-NEXT:    sd a5, 0(a2)3220; RV64ZVE32F-NEXT:  .LBB41_9: # %else143221; RV64ZVE32F-NEXT:    ld s0, 24(sp) # 8-byte Folded Reload3222; RV64ZVE32F-NEXT:    ld s1, 16(sp) # 8-byte Folded Reload3223; RV64ZVE32F-NEXT:    ld s2, 8(sp) # 8-byte Folded Reload3224; RV64ZVE32F-NEXT:    .cfi_restore s03225; RV64ZVE32F-NEXT:    .cfi_restore s13226; RV64ZVE32F-NEXT:    .cfi_restore s23227; RV64ZVE32F-NEXT:    addi sp, sp, 323228; RV64ZVE32F-NEXT:    .cfi_def_cfa_offset 03229; RV64ZVE32F-NEXT:    ret3230; RV64ZVE32F-NEXT:  .LBB41_10: # %cond.store3231; RV64ZVE32F-NEXT:    .cfi_restore_state3232; RV64ZVE32F-NEXT:    ld a1, 0(a1)3233; RV64ZVE32F-NEXT:    ld a0, 0(a0)3234; RV64ZVE32F-NEXT:    sd a0, 0(a1)3235; RV64ZVE32F-NEXT:    andi a0, t1, 23236; RV64ZVE32F-NEXT:    beqz a0, .LBB41_23237; RV64ZVE32F-NEXT:  .LBB41_11: # %cond.store13238; RV64ZVE32F-NEXT:    sd s1, 0(t5)3239; RV64ZVE32F-NEXT:    andi a0, t1, 43240; RV64ZVE32F-NEXT:    beqz a0, .LBB41_33241; RV64ZVE32F-NEXT:  .LBB41_12: # %cond.store33242; RV64ZVE32F-NEXT:    sd s0, 0(t3)3243; RV64ZVE32F-NEXT:    andi a0, t1, 83244; RV64ZVE32F-NEXT:    beqz a0, .LBB41_43245; RV64ZVE32F-NEXT:  .LBB41_13: # %cond.store53246; RV64ZVE32F-NEXT:    sd t6, 0(t2)3247; RV64ZVE32F-NEXT:    andi a0, t1, 163248; RV64ZVE32F-NEXT:    beqz a0, .LBB41_53249; RV64ZVE32F-NEXT:  .LBB41_14: # %cond.store73250; RV64ZVE32F-NEXT:    sd t4, 0(t0)3251; RV64ZVE32F-NEXT:    andi a0, t1, 323252; RV64ZVE32F-NEXT:    beqz a0, .LBB41_63253; RV64ZVE32F-NEXT:  .LBB41_15: # %cond.store93254; RV64ZVE32F-NEXT:    sd a7, 0(a4)3255; RV64ZVE32F-NEXT:    andi a0, t1, 643256; RV64ZVE32F-NEXT:    beqz a0, .LBB41_73257; RV64ZVE32F-NEXT:  .LBB41_16: # %cond.store113258; RV64ZVE32F-NEXT:    sd a6, 0(a3)3259; RV64ZVE32F-NEXT:    andi a0, t1, -1283260; RV64ZVE32F-NEXT:    bnez a0, .LBB41_83261; RV64ZVE32F-NEXT:    j .LBB41_93262  call void @llvm.masked.scatter.v8i64.v8p0(<8 x i64> %val, <8 x ptr> %ptrs, i32 8, <8 x i1> %m)3263  ret void3264}3265 3266define void @mscatter_baseidx_v8i8_v8i64(<8 x i64> %val, ptr %base, <8 x i8> %idxs, <8 x i1> %m) {3267; RV32V-LABEL: mscatter_baseidx_v8i8_v8i64:3268; RV32V:       # %bb.0:3269; RV32V-NEXT:    vsetivli zero, 8, e32, m2, ta, ma3270; RV32V-NEXT:    vsext.vf4 v14, v123271; RV32V-NEXT:    vsll.vi v12, v14, 33272; RV32V-NEXT:    vsetvli zero, zero, e64, m4, ta, ma3273; RV32V-NEXT:    vsoxei32.v v8, (a0), v12, v0.t3274; RV32V-NEXT:    ret3275;3276; RV64V-LABEL: mscatter_baseidx_v8i8_v8i64:3277; RV64V:       # %bb.0:3278; RV64V-NEXT:    vsetivli zero, 8, e64, m4, ta, ma3279; RV64V-NEXT:    vsext.vf8 v16, v123280; RV64V-NEXT:    vsll.vi v12, v16, 33281; RV64V-NEXT:    vsoxei64.v v8, (a0), v12, v0.t3282; RV64V-NEXT:    ret3283;3284; RV32ZVE32F-LABEL: mscatter_baseidx_v8i8_v8i64:3285; RV32ZVE32F:       # %bb.0:3286; RV32ZVE32F-NEXT:    addi sp, sp, -163287; RV32ZVE32F-NEXT:    .cfi_def_cfa_offset 163288; RV32ZVE32F-NEXT:    sw s0, 12(sp) # 4-byte Folded Spill3289; RV32ZVE32F-NEXT:    sw s1, 8(sp) # 4-byte Folded Spill3290; RV32ZVE32F-NEXT:    sw s2, 4(sp) # 4-byte Folded Spill3291; RV32ZVE32F-NEXT:    .cfi_offset s0, -43292; RV32ZVE32F-NEXT:    .cfi_offset s1, -83293; RV32ZVE32F-NEXT:    .cfi_offset s2, -123294; RV32ZVE32F-NEXT:    .cfi_remember_state3295; RV32ZVE32F-NEXT:    lw a2, 56(a0)3296; RV32ZVE32F-NEXT:    lw a3, 60(a0)3297; RV32ZVE32F-NEXT:    lw a6, 40(a0)3298; RV32ZVE32F-NEXT:    lw a7, 44(a0)3299; RV32ZVE32F-NEXT:    lw a4, 48(a0)3300; RV32ZVE32F-NEXT:    lw a5, 52(a0)3301; RV32ZVE32F-NEXT:    lw t3, 24(a0)3302; RV32ZVE32F-NEXT:    lw t4, 28(a0)3303; RV32ZVE32F-NEXT:    lw t1, 32(a0)3304; RV32ZVE32F-NEXT:    lw t2, 36(a0)3305; RV32ZVE32F-NEXT:    lw s0, 8(a0)3306; RV32ZVE32F-NEXT:    lw s1, 12(a0)3307; RV32ZVE32F-NEXT:    lw t5, 16(a0)3308; RV32ZVE32F-NEXT:    lw t6, 20(a0)3309; RV32ZVE32F-NEXT:    vsetivli zero, 8, e32, m2, ta, ma3310; RV32ZVE32F-NEXT:    vsext.vf4 v10, v83311; RV32ZVE32F-NEXT:    vsll.vi v8, v10, 33312; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma3313; RV32ZVE32F-NEXT:    vmv.x.s t0, v03314; RV32ZVE32F-NEXT:    andi s2, t0, 13315; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma3316; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a13317; RV32ZVE32F-NEXT:    bnez s2, .LBB42_103318; RV32ZVE32F-NEXT:  # %bb.1: # %else3319; RV32ZVE32F-NEXT:    andi a0, t0, 23320; RV32ZVE32F-NEXT:    bnez a0, .LBB42_113321; RV32ZVE32F-NEXT:  .LBB42_2: # %else23322; RV32ZVE32F-NEXT:    andi a0, t0, 43323; RV32ZVE32F-NEXT:    bnez a0, .LBB42_123324; RV32ZVE32F-NEXT:  .LBB42_3: # %else43325; RV32ZVE32F-NEXT:    andi a0, t0, 83326; RV32ZVE32F-NEXT:    bnez a0, .LBB42_133327; RV32ZVE32F-NEXT:  .LBB42_4: # %else63328; RV32ZVE32F-NEXT:    andi a0, t0, 163329; RV32ZVE32F-NEXT:    bnez a0, .LBB42_143330; RV32ZVE32F-NEXT:  .LBB42_5: # %else83331; RV32ZVE32F-NEXT:    andi a0, t0, 323332; RV32ZVE32F-NEXT:    bnez a0, .LBB42_153333; RV32ZVE32F-NEXT:  .LBB42_6: # %else103334; RV32ZVE32F-NEXT:    andi a0, t0, 643335; RV32ZVE32F-NEXT:    bnez a0, .LBB42_163336; RV32ZVE32F-NEXT:  .LBB42_7: # %else123337; RV32ZVE32F-NEXT:    andi a0, t0, -1283338; RV32ZVE32F-NEXT:    beqz a0, .LBB42_93339; RV32ZVE32F-NEXT:  .LBB42_8: # %cond.store133340; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma3341; RV32ZVE32F-NEXT:    vslidedown.vi v8, v8, 73342; RV32ZVE32F-NEXT:    vmv.x.s a0, v83343; RV32ZVE32F-NEXT:    sw a2, 0(a0)3344; RV32ZVE32F-NEXT:    sw a3, 4(a0)3345; RV32ZVE32F-NEXT:  .LBB42_9: # %else143346; RV32ZVE32F-NEXT:    lw s0, 12(sp) # 4-byte Folded Reload3347; RV32ZVE32F-NEXT:    lw s1, 8(sp) # 4-byte Folded Reload3348; RV32ZVE32F-NEXT:    lw s2, 4(sp) # 4-byte Folded Reload3349; RV32ZVE32F-NEXT:    .cfi_restore s03350; RV32ZVE32F-NEXT:    .cfi_restore s13351; RV32ZVE32F-NEXT:    .cfi_restore s23352; RV32ZVE32F-NEXT:    addi sp, sp, 163353; RV32ZVE32F-NEXT:    .cfi_def_cfa_offset 03354; RV32ZVE32F-NEXT:    ret3355; RV32ZVE32F-NEXT:  .LBB42_10: # %cond.store3356; RV32ZVE32F-NEXT:    .cfi_restore_state3357; RV32ZVE32F-NEXT:    lw a1, 0(a0)3358; RV32ZVE32F-NEXT:    lw a0, 4(a0)3359; RV32ZVE32F-NEXT:    vmv.x.s s2, v83360; RV32ZVE32F-NEXT:    sw a1, 0(s2)3361; RV32ZVE32F-NEXT:    sw a0, 4(s2)3362; RV32ZVE32F-NEXT:    andi a0, t0, 23363; RV32ZVE32F-NEXT:    beqz a0, .LBB42_23364; RV32ZVE32F-NEXT:  .LBB42_11: # %cond.store13365; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma3366; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 13367; RV32ZVE32F-NEXT:    vmv.x.s a0, v103368; RV32ZVE32F-NEXT:    sw s0, 0(a0)3369; RV32ZVE32F-NEXT:    sw s1, 4(a0)3370; RV32ZVE32F-NEXT:    andi a0, t0, 43371; RV32ZVE32F-NEXT:    beqz a0, .LBB42_33372; RV32ZVE32F-NEXT:  .LBB42_12: # %cond.store33373; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma3374; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 23375; RV32ZVE32F-NEXT:    vmv.x.s a0, v103376; RV32ZVE32F-NEXT:    sw t5, 0(a0)3377; RV32ZVE32F-NEXT:    sw t6, 4(a0)3378; RV32ZVE32F-NEXT:    andi a0, t0, 83379; RV32ZVE32F-NEXT:    beqz a0, .LBB42_43380; RV32ZVE32F-NEXT:  .LBB42_13: # %cond.store53381; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma3382; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 33383; RV32ZVE32F-NEXT:    vmv.x.s a0, v103384; RV32ZVE32F-NEXT:    sw t3, 0(a0)3385; RV32ZVE32F-NEXT:    sw t4, 4(a0)3386; RV32ZVE32F-NEXT:    andi a0, t0, 163387; RV32ZVE32F-NEXT:    beqz a0, .LBB42_53388; RV32ZVE32F-NEXT:  .LBB42_14: # %cond.store73389; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma3390; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 43391; RV32ZVE32F-NEXT:    vmv.x.s a0, v103392; RV32ZVE32F-NEXT:    sw t1, 0(a0)3393; RV32ZVE32F-NEXT:    sw t2, 4(a0)3394; RV32ZVE32F-NEXT:    andi a0, t0, 323395; RV32ZVE32F-NEXT:    beqz a0, .LBB42_63396; RV32ZVE32F-NEXT:  .LBB42_15: # %cond.store93397; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma3398; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 53399; RV32ZVE32F-NEXT:    vmv.x.s a0, v103400; RV32ZVE32F-NEXT:    sw a6, 0(a0)3401; RV32ZVE32F-NEXT:    sw a7, 4(a0)3402; RV32ZVE32F-NEXT:    andi a0, t0, 643403; RV32ZVE32F-NEXT:    beqz a0, .LBB42_73404; RV32ZVE32F-NEXT:  .LBB42_16: # %cond.store113405; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma3406; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 63407; RV32ZVE32F-NEXT:    vmv.x.s a0, v103408; RV32ZVE32F-NEXT:    sw a4, 0(a0)3409; RV32ZVE32F-NEXT:    sw a5, 4(a0)3410; RV32ZVE32F-NEXT:    andi a0, t0, -1283411; RV32ZVE32F-NEXT:    bnez a0, .LBB42_83412; RV32ZVE32F-NEXT:    j .LBB42_93413;3414; RV64ZVE32F-LABEL: mscatter_baseidx_v8i8_v8i64:3415; RV64ZVE32F:       # %bb.0:3416; RV64ZVE32F-NEXT:    ld a5, 40(a0)3417; RV64ZVE32F-NEXT:    ld a3, 48(a0)3418; RV64ZVE32F-NEXT:    ld a2, 56(a0)3419; RV64ZVE32F-NEXT:    ld t1, 8(a0)3420; RV64ZVE32F-NEXT:    ld t0, 16(a0)3421; RV64ZVE32F-NEXT:    ld a7, 24(a0)3422; RV64ZVE32F-NEXT:    ld a6, 32(a0)3423; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma3424; RV64ZVE32F-NEXT:    vmv.x.s a4, v03425; RV64ZVE32F-NEXT:    andi t2, a4, 13426; RV64ZVE32F-NEXT:    beqz t2, .LBB42_23427; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store3428; RV64ZVE32F-NEXT:    ld a0, 0(a0)3429; RV64ZVE32F-NEXT:    vmv.x.s t2, v83430; RV64ZVE32F-NEXT:    slli t2, t2, 33431; RV64ZVE32F-NEXT:    add t2, a1, t23432; RV64ZVE32F-NEXT:    sd a0, 0(t2)3433; RV64ZVE32F-NEXT:  .LBB42_2: # %else3434; RV64ZVE32F-NEXT:    andi a0, a4, 23435; RV64ZVE32F-NEXT:    beqz a0, .LBB42_43436; RV64ZVE32F-NEXT:  # %bb.3: # %cond.store13437; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma3438; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 13439; RV64ZVE32F-NEXT:    vmv.x.s a0, v93440; RV64ZVE32F-NEXT:    slli a0, a0, 33441; RV64ZVE32F-NEXT:    add a0, a1, a03442; RV64ZVE32F-NEXT:    sd t1, 0(a0)3443; RV64ZVE32F-NEXT:  .LBB42_4: # %else23444; RV64ZVE32F-NEXT:    andi a0, a4, 43445; RV64ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma3446; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 23447; RV64ZVE32F-NEXT:    beqz a0, .LBB42_63448; RV64ZVE32F-NEXT:  # %bb.5: # %cond.store33449; RV64ZVE32F-NEXT:    vmv.x.s a0, v93450; RV64ZVE32F-NEXT:    slli a0, a0, 33451; RV64ZVE32F-NEXT:    add a0, a1, a03452; RV64ZVE32F-NEXT:    sd t0, 0(a0)3453; RV64ZVE32F-NEXT:  .LBB42_6: # %else43454; RV64ZVE32F-NEXT:    andi a0, a4, 83455; RV64ZVE32F-NEXT:    beqz a0, .LBB42_83456; RV64ZVE32F-NEXT:  # %bb.7: # %cond.store53457; RV64ZVE32F-NEXT:    vslidedown.vi v9, v9, 13458; RV64ZVE32F-NEXT:    vmv.x.s a0, v93459; RV64ZVE32F-NEXT:    slli a0, a0, 33460; RV64ZVE32F-NEXT:    add a0, a1, a03461; RV64ZVE32F-NEXT:    sd a7, 0(a0)3462; RV64ZVE32F-NEXT:  .LBB42_8: # %else63463; RV64ZVE32F-NEXT:    andi a0, a4, 163464; RV64ZVE32F-NEXT:    vsetivli zero, 4, e8, mf2, ta, ma3465; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 43466; RV64ZVE32F-NEXT:    beqz a0, .LBB42_103467; RV64ZVE32F-NEXT:  # %bb.9: # %cond.store73468; RV64ZVE32F-NEXT:    vmv.x.s a0, v83469; RV64ZVE32F-NEXT:    slli a0, a0, 33470; RV64ZVE32F-NEXT:    add a0, a1, a03471; RV64ZVE32F-NEXT:    sd a6, 0(a0)3472; RV64ZVE32F-NEXT:  .LBB42_10: # %else83473; RV64ZVE32F-NEXT:    andi a0, a4, 323474; RV64ZVE32F-NEXT:    beqz a0, .LBB42_123475; RV64ZVE32F-NEXT:  # %bb.11: # %cond.store93476; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma3477; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 13478; RV64ZVE32F-NEXT:    vmv.x.s a0, v93479; RV64ZVE32F-NEXT:    slli a0, a0, 33480; RV64ZVE32F-NEXT:    add a0, a1, a03481; RV64ZVE32F-NEXT:    sd a5, 0(a0)3482; RV64ZVE32F-NEXT:  .LBB42_12: # %else103483; RV64ZVE32F-NEXT:    andi a0, a4, 643484; RV64ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma3485; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 23486; RV64ZVE32F-NEXT:    bnez a0, .LBB42_153487; RV64ZVE32F-NEXT:  # %bb.13: # %else123488; RV64ZVE32F-NEXT:    andi a0, a4, -1283489; RV64ZVE32F-NEXT:    bnez a0, .LBB42_163490; RV64ZVE32F-NEXT:  .LBB42_14: # %else143491; RV64ZVE32F-NEXT:    ret3492; RV64ZVE32F-NEXT:  .LBB42_15: # %cond.store113493; RV64ZVE32F-NEXT:    vmv.x.s a0, v83494; RV64ZVE32F-NEXT:    slli a0, a0, 33495; RV64ZVE32F-NEXT:    add a0, a1, a03496; RV64ZVE32F-NEXT:    sd a3, 0(a0)3497; RV64ZVE32F-NEXT:    andi a0, a4, -1283498; RV64ZVE32F-NEXT:    beqz a0, .LBB42_143499; RV64ZVE32F-NEXT:  .LBB42_16: # %cond.store133500; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 13501; RV64ZVE32F-NEXT:    vmv.x.s a0, v83502; RV64ZVE32F-NEXT:    slli a0, a0, 33503; RV64ZVE32F-NEXT:    add a0, a1, a03504; RV64ZVE32F-NEXT:    sd a2, 0(a0)3505; RV64ZVE32F-NEXT:    ret3506  %ptrs = getelementptr inbounds i64, ptr %base, <8 x i8> %idxs3507  call void @llvm.masked.scatter.v8i64.v8p0(<8 x i64> %val, <8 x ptr> %ptrs, i32 8, <8 x i1> %m)3508  ret void3509}3510 3511define void @mscatter_baseidx_sext_v8i8_v8i64(<8 x i64> %val, ptr %base, <8 x i8> %idxs, <8 x i1> %m) {3512; RV32V-LABEL: mscatter_baseidx_sext_v8i8_v8i64:3513; RV32V:       # %bb.0:3514; RV32V-NEXT:    vsetivli zero, 8, e32, m2, ta, ma3515; RV32V-NEXT:    vsext.vf4 v14, v123516; RV32V-NEXT:    vsll.vi v12, v14, 33517; RV32V-NEXT:    vsetvli zero, zero, e64, m4, ta, ma3518; RV32V-NEXT:    vsoxei32.v v8, (a0), v12, v0.t3519; RV32V-NEXT:    ret3520;3521; RV64V-LABEL: mscatter_baseidx_sext_v8i8_v8i64:3522; RV64V:       # %bb.0:3523; RV64V-NEXT:    vsetivli zero, 8, e64, m4, ta, ma3524; RV64V-NEXT:    vsext.vf8 v16, v123525; RV64V-NEXT:    vsll.vi v12, v16, 33526; RV64V-NEXT:    vsoxei64.v v8, (a0), v12, v0.t3527; RV64V-NEXT:    ret3528;3529; RV32ZVE32F-LABEL: mscatter_baseidx_sext_v8i8_v8i64:3530; RV32ZVE32F:       # %bb.0:3531; RV32ZVE32F-NEXT:    addi sp, sp, -163532; RV32ZVE32F-NEXT:    .cfi_def_cfa_offset 163533; RV32ZVE32F-NEXT:    sw s0, 12(sp) # 4-byte Folded Spill3534; RV32ZVE32F-NEXT:    sw s1, 8(sp) # 4-byte Folded Spill3535; RV32ZVE32F-NEXT:    sw s2, 4(sp) # 4-byte Folded Spill3536; RV32ZVE32F-NEXT:    .cfi_offset s0, -43537; RV32ZVE32F-NEXT:    .cfi_offset s1, -83538; RV32ZVE32F-NEXT:    .cfi_offset s2, -123539; RV32ZVE32F-NEXT:    .cfi_remember_state3540; RV32ZVE32F-NEXT:    lw a2, 56(a0)3541; RV32ZVE32F-NEXT:    lw a3, 60(a0)3542; RV32ZVE32F-NEXT:    lw a6, 40(a0)3543; RV32ZVE32F-NEXT:    lw a7, 44(a0)3544; RV32ZVE32F-NEXT:    lw a4, 48(a0)3545; RV32ZVE32F-NEXT:    lw a5, 52(a0)3546; RV32ZVE32F-NEXT:    lw t3, 24(a0)3547; RV32ZVE32F-NEXT:    lw t4, 28(a0)3548; RV32ZVE32F-NEXT:    lw t1, 32(a0)3549; RV32ZVE32F-NEXT:    lw t2, 36(a0)3550; RV32ZVE32F-NEXT:    lw s0, 8(a0)3551; RV32ZVE32F-NEXT:    lw s1, 12(a0)3552; RV32ZVE32F-NEXT:    lw t5, 16(a0)3553; RV32ZVE32F-NEXT:    lw t6, 20(a0)3554; RV32ZVE32F-NEXT:    vsetivli zero, 8, e32, m2, ta, ma3555; RV32ZVE32F-NEXT:    vsext.vf4 v10, v83556; RV32ZVE32F-NEXT:    vsll.vi v8, v10, 33557; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma3558; RV32ZVE32F-NEXT:    vmv.x.s t0, v03559; RV32ZVE32F-NEXT:    andi s2, t0, 13560; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma3561; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a13562; RV32ZVE32F-NEXT:    bnez s2, .LBB43_103563; RV32ZVE32F-NEXT:  # %bb.1: # %else3564; RV32ZVE32F-NEXT:    andi a0, t0, 23565; RV32ZVE32F-NEXT:    bnez a0, .LBB43_113566; RV32ZVE32F-NEXT:  .LBB43_2: # %else23567; RV32ZVE32F-NEXT:    andi a0, t0, 43568; RV32ZVE32F-NEXT:    bnez a0, .LBB43_123569; RV32ZVE32F-NEXT:  .LBB43_3: # %else43570; RV32ZVE32F-NEXT:    andi a0, t0, 83571; RV32ZVE32F-NEXT:    bnez a0, .LBB43_133572; RV32ZVE32F-NEXT:  .LBB43_4: # %else63573; RV32ZVE32F-NEXT:    andi a0, t0, 163574; RV32ZVE32F-NEXT:    bnez a0, .LBB43_143575; RV32ZVE32F-NEXT:  .LBB43_5: # %else83576; RV32ZVE32F-NEXT:    andi a0, t0, 323577; RV32ZVE32F-NEXT:    bnez a0, .LBB43_153578; RV32ZVE32F-NEXT:  .LBB43_6: # %else103579; RV32ZVE32F-NEXT:    andi a0, t0, 643580; RV32ZVE32F-NEXT:    bnez a0, .LBB43_163581; RV32ZVE32F-NEXT:  .LBB43_7: # %else123582; RV32ZVE32F-NEXT:    andi a0, t0, -1283583; RV32ZVE32F-NEXT:    beqz a0, .LBB43_93584; RV32ZVE32F-NEXT:  .LBB43_8: # %cond.store133585; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma3586; RV32ZVE32F-NEXT:    vslidedown.vi v8, v8, 73587; RV32ZVE32F-NEXT:    vmv.x.s a0, v83588; RV32ZVE32F-NEXT:    sw a2, 0(a0)3589; RV32ZVE32F-NEXT:    sw a3, 4(a0)3590; RV32ZVE32F-NEXT:  .LBB43_9: # %else143591; RV32ZVE32F-NEXT:    lw s0, 12(sp) # 4-byte Folded Reload3592; RV32ZVE32F-NEXT:    lw s1, 8(sp) # 4-byte Folded Reload3593; RV32ZVE32F-NEXT:    lw s2, 4(sp) # 4-byte Folded Reload3594; RV32ZVE32F-NEXT:    .cfi_restore s03595; RV32ZVE32F-NEXT:    .cfi_restore s13596; RV32ZVE32F-NEXT:    .cfi_restore s23597; RV32ZVE32F-NEXT:    addi sp, sp, 163598; RV32ZVE32F-NEXT:    .cfi_def_cfa_offset 03599; RV32ZVE32F-NEXT:    ret3600; RV32ZVE32F-NEXT:  .LBB43_10: # %cond.store3601; RV32ZVE32F-NEXT:    .cfi_restore_state3602; RV32ZVE32F-NEXT:    lw a1, 0(a0)3603; RV32ZVE32F-NEXT:    lw a0, 4(a0)3604; RV32ZVE32F-NEXT:    vmv.x.s s2, v83605; RV32ZVE32F-NEXT:    sw a1, 0(s2)3606; RV32ZVE32F-NEXT:    sw a0, 4(s2)3607; RV32ZVE32F-NEXT:    andi a0, t0, 23608; RV32ZVE32F-NEXT:    beqz a0, .LBB43_23609; RV32ZVE32F-NEXT:  .LBB43_11: # %cond.store13610; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma3611; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 13612; RV32ZVE32F-NEXT:    vmv.x.s a0, v103613; RV32ZVE32F-NEXT:    sw s0, 0(a0)3614; RV32ZVE32F-NEXT:    sw s1, 4(a0)3615; RV32ZVE32F-NEXT:    andi a0, t0, 43616; RV32ZVE32F-NEXT:    beqz a0, .LBB43_33617; RV32ZVE32F-NEXT:  .LBB43_12: # %cond.store33618; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma3619; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 23620; RV32ZVE32F-NEXT:    vmv.x.s a0, v103621; RV32ZVE32F-NEXT:    sw t5, 0(a0)3622; RV32ZVE32F-NEXT:    sw t6, 4(a0)3623; RV32ZVE32F-NEXT:    andi a0, t0, 83624; RV32ZVE32F-NEXT:    beqz a0, .LBB43_43625; RV32ZVE32F-NEXT:  .LBB43_13: # %cond.store53626; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma3627; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 33628; RV32ZVE32F-NEXT:    vmv.x.s a0, v103629; RV32ZVE32F-NEXT:    sw t3, 0(a0)3630; RV32ZVE32F-NEXT:    sw t4, 4(a0)3631; RV32ZVE32F-NEXT:    andi a0, t0, 163632; RV32ZVE32F-NEXT:    beqz a0, .LBB43_53633; RV32ZVE32F-NEXT:  .LBB43_14: # %cond.store73634; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma3635; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 43636; RV32ZVE32F-NEXT:    vmv.x.s a0, v103637; RV32ZVE32F-NEXT:    sw t1, 0(a0)3638; RV32ZVE32F-NEXT:    sw t2, 4(a0)3639; RV32ZVE32F-NEXT:    andi a0, t0, 323640; RV32ZVE32F-NEXT:    beqz a0, .LBB43_63641; RV32ZVE32F-NEXT:  .LBB43_15: # %cond.store93642; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma3643; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 53644; RV32ZVE32F-NEXT:    vmv.x.s a0, v103645; RV32ZVE32F-NEXT:    sw a6, 0(a0)3646; RV32ZVE32F-NEXT:    sw a7, 4(a0)3647; RV32ZVE32F-NEXT:    andi a0, t0, 643648; RV32ZVE32F-NEXT:    beqz a0, .LBB43_73649; RV32ZVE32F-NEXT:  .LBB43_16: # %cond.store113650; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma3651; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 63652; RV32ZVE32F-NEXT:    vmv.x.s a0, v103653; RV32ZVE32F-NEXT:    sw a4, 0(a0)3654; RV32ZVE32F-NEXT:    sw a5, 4(a0)3655; RV32ZVE32F-NEXT:    andi a0, t0, -1283656; RV32ZVE32F-NEXT:    bnez a0, .LBB43_83657; RV32ZVE32F-NEXT:    j .LBB43_93658;3659; RV64ZVE32F-LABEL: mscatter_baseidx_sext_v8i8_v8i64:3660; RV64ZVE32F:       # %bb.0:3661; RV64ZVE32F-NEXT:    ld a5, 40(a0)3662; RV64ZVE32F-NEXT:    ld a3, 48(a0)3663; RV64ZVE32F-NEXT:    ld a2, 56(a0)3664; RV64ZVE32F-NEXT:    ld t1, 8(a0)3665; RV64ZVE32F-NEXT:    ld t0, 16(a0)3666; RV64ZVE32F-NEXT:    ld a7, 24(a0)3667; RV64ZVE32F-NEXT:    ld a6, 32(a0)3668; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma3669; RV64ZVE32F-NEXT:    vmv.x.s a4, v03670; RV64ZVE32F-NEXT:    andi t2, a4, 13671; RV64ZVE32F-NEXT:    beqz t2, .LBB43_23672; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store3673; RV64ZVE32F-NEXT:    ld a0, 0(a0)3674; RV64ZVE32F-NEXT:    vmv.x.s t2, v83675; RV64ZVE32F-NEXT:    slli t2, t2, 33676; RV64ZVE32F-NEXT:    add t2, a1, t23677; RV64ZVE32F-NEXT:    sd a0, 0(t2)3678; RV64ZVE32F-NEXT:  .LBB43_2: # %else3679; RV64ZVE32F-NEXT:    andi a0, a4, 23680; RV64ZVE32F-NEXT:    beqz a0, .LBB43_43681; RV64ZVE32F-NEXT:  # %bb.3: # %cond.store13682; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma3683; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 13684; RV64ZVE32F-NEXT:    vmv.x.s a0, v93685; RV64ZVE32F-NEXT:    slli a0, a0, 33686; RV64ZVE32F-NEXT:    add a0, a1, a03687; RV64ZVE32F-NEXT:    sd t1, 0(a0)3688; RV64ZVE32F-NEXT:  .LBB43_4: # %else23689; RV64ZVE32F-NEXT:    andi a0, a4, 43690; RV64ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma3691; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 23692; RV64ZVE32F-NEXT:    beqz a0, .LBB43_63693; RV64ZVE32F-NEXT:  # %bb.5: # %cond.store33694; RV64ZVE32F-NEXT:    vmv.x.s a0, v93695; RV64ZVE32F-NEXT:    slli a0, a0, 33696; RV64ZVE32F-NEXT:    add a0, a1, a03697; RV64ZVE32F-NEXT:    sd t0, 0(a0)3698; RV64ZVE32F-NEXT:  .LBB43_6: # %else43699; RV64ZVE32F-NEXT:    andi a0, a4, 83700; RV64ZVE32F-NEXT:    beqz a0, .LBB43_83701; RV64ZVE32F-NEXT:  # %bb.7: # %cond.store53702; RV64ZVE32F-NEXT:    vslidedown.vi v9, v9, 13703; RV64ZVE32F-NEXT:    vmv.x.s a0, v93704; RV64ZVE32F-NEXT:    slli a0, a0, 33705; RV64ZVE32F-NEXT:    add a0, a1, a03706; RV64ZVE32F-NEXT:    sd a7, 0(a0)3707; RV64ZVE32F-NEXT:  .LBB43_8: # %else63708; RV64ZVE32F-NEXT:    andi a0, a4, 163709; RV64ZVE32F-NEXT:    vsetivli zero, 4, e8, mf2, ta, ma3710; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 43711; RV64ZVE32F-NEXT:    beqz a0, .LBB43_103712; RV64ZVE32F-NEXT:  # %bb.9: # %cond.store73713; RV64ZVE32F-NEXT:    vmv.x.s a0, v83714; RV64ZVE32F-NEXT:    slli a0, a0, 33715; RV64ZVE32F-NEXT:    add a0, a1, a03716; RV64ZVE32F-NEXT:    sd a6, 0(a0)3717; RV64ZVE32F-NEXT:  .LBB43_10: # %else83718; RV64ZVE32F-NEXT:    andi a0, a4, 323719; RV64ZVE32F-NEXT:    beqz a0, .LBB43_123720; RV64ZVE32F-NEXT:  # %bb.11: # %cond.store93721; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma3722; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 13723; RV64ZVE32F-NEXT:    vmv.x.s a0, v93724; RV64ZVE32F-NEXT:    slli a0, a0, 33725; RV64ZVE32F-NEXT:    add a0, a1, a03726; RV64ZVE32F-NEXT:    sd a5, 0(a0)3727; RV64ZVE32F-NEXT:  .LBB43_12: # %else103728; RV64ZVE32F-NEXT:    andi a0, a4, 643729; RV64ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma3730; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 23731; RV64ZVE32F-NEXT:    bnez a0, .LBB43_153732; RV64ZVE32F-NEXT:  # %bb.13: # %else123733; RV64ZVE32F-NEXT:    andi a0, a4, -1283734; RV64ZVE32F-NEXT:    bnez a0, .LBB43_163735; RV64ZVE32F-NEXT:  .LBB43_14: # %else143736; RV64ZVE32F-NEXT:    ret3737; RV64ZVE32F-NEXT:  .LBB43_15: # %cond.store113738; RV64ZVE32F-NEXT:    vmv.x.s a0, v83739; RV64ZVE32F-NEXT:    slli a0, a0, 33740; RV64ZVE32F-NEXT:    add a0, a1, a03741; RV64ZVE32F-NEXT:    sd a3, 0(a0)3742; RV64ZVE32F-NEXT:    andi a0, a4, -1283743; RV64ZVE32F-NEXT:    beqz a0, .LBB43_143744; RV64ZVE32F-NEXT:  .LBB43_16: # %cond.store133745; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 13746; RV64ZVE32F-NEXT:    vmv.x.s a0, v83747; RV64ZVE32F-NEXT:    slli a0, a0, 33748; RV64ZVE32F-NEXT:    add a0, a1, a03749; RV64ZVE32F-NEXT:    sd a2, 0(a0)3750; RV64ZVE32F-NEXT:    ret3751  %eidxs = sext <8 x i8> %idxs to <8 x i64>3752  %ptrs = getelementptr inbounds i64, ptr %base, <8 x i64> %eidxs3753  call void @llvm.masked.scatter.v8i64.v8p0(<8 x i64> %val, <8 x ptr> %ptrs, i32 8, <8 x i1> %m)3754  ret void3755}3756 3757define void @mscatter_baseidx_zext_v8i8_v8i64(<8 x i64> %val, ptr %base, <8 x i8> %idxs, <8 x i1> %m) {3758; RV32V-LABEL: mscatter_baseidx_zext_v8i8_v8i64:3759; RV32V:       # %bb.0:3760; RV32V-NEXT:    li a1, 83761; RV32V-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma3762; RV32V-NEXT:    vwmulu.vx v13, v12, a13763; RV32V-NEXT:    vsetvli zero, zero, e64, m4, ta, ma3764; RV32V-NEXT:    vsoxei16.v v8, (a0), v13, v0.t3765; RV32V-NEXT:    ret3766;3767; RV64V-LABEL: mscatter_baseidx_zext_v8i8_v8i64:3768; RV64V:       # %bb.0:3769; RV64V-NEXT:    li a1, 83770; RV64V-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma3771; RV64V-NEXT:    vwmulu.vx v13, v12, a13772; RV64V-NEXT:    vsetvli zero, zero, e64, m4, ta, ma3773; RV64V-NEXT:    vsoxei16.v v8, (a0), v13, v0.t3774; RV64V-NEXT:    ret3775;3776; RV32ZVE32F-LABEL: mscatter_baseidx_zext_v8i8_v8i64:3777; RV32ZVE32F:       # %bb.0:3778; RV32ZVE32F-NEXT:    addi sp, sp, -163779; RV32ZVE32F-NEXT:    .cfi_def_cfa_offset 163780; RV32ZVE32F-NEXT:    sw s0, 12(sp) # 4-byte Folded Spill3781; RV32ZVE32F-NEXT:    sw s1, 8(sp) # 4-byte Folded Spill3782; RV32ZVE32F-NEXT:    sw s2, 4(sp) # 4-byte Folded Spill3783; RV32ZVE32F-NEXT:    .cfi_offset s0, -43784; RV32ZVE32F-NEXT:    .cfi_offset s1, -83785; RV32ZVE32F-NEXT:    .cfi_offset s2, -123786; RV32ZVE32F-NEXT:    .cfi_remember_state3787; RV32ZVE32F-NEXT:    lw a2, 56(a0)3788; RV32ZVE32F-NEXT:    lw a3, 60(a0)3789; RV32ZVE32F-NEXT:    lw a6, 40(a0)3790; RV32ZVE32F-NEXT:    lw a7, 44(a0)3791; RV32ZVE32F-NEXT:    lw a4, 48(a0)3792; RV32ZVE32F-NEXT:    lw a5, 52(a0)3793; RV32ZVE32F-NEXT:    lw t3, 24(a0)3794; RV32ZVE32F-NEXT:    lw t4, 28(a0)3795; RV32ZVE32F-NEXT:    lw t1, 32(a0)3796; RV32ZVE32F-NEXT:    lw t2, 36(a0)3797; RV32ZVE32F-NEXT:    lw s0, 8(a0)3798; RV32ZVE32F-NEXT:    lw s1, 12(a0)3799; RV32ZVE32F-NEXT:    lw t5, 16(a0)3800; RV32ZVE32F-NEXT:    lw t6, 20(a0)3801; RV32ZVE32F-NEXT:    vsetivli zero, 8, e32, m2, ta, ma3802; RV32ZVE32F-NEXT:    vzext.vf4 v10, v83803; RV32ZVE32F-NEXT:    vsll.vi v8, v10, 33804; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma3805; RV32ZVE32F-NEXT:    vmv.x.s t0, v03806; RV32ZVE32F-NEXT:    andi s2, t0, 13807; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma3808; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a13809; RV32ZVE32F-NEXT:    bnez s2, .LBB44_103810; RV32ZVE32F-NEXT:  # %bb.1: # %else3811; RV32ZVE32F-NEXT:    andi a0, t0, 23812; RV32ZVE32F-NEXT:    bnez a0, .LBB44_113813; RV32ZVE32F-NEXT:  .LBB44_2: # %else23814; RV32ZVE32F-NEXT:    andi a0, t0, 43815; RV32ZVE32F-NEXT:    bnez a0, .LBB44_123816; RV32ZVE32F-NEXT:  .LBB44_3: # %else43817; RV32ZVE32F-NEXT:    andi a0, t0, 83818; RV32ZVE32F-NEXT:    bnez a0, .LBB44_133819; RV32ZVE32F-NEXT:  .LBB44_4: # %else63820; RV32ZVE32F-NEXT:    andi a0, t0, 163821; RV32ZVE32F-NEXT:    bnez a0, .LBB44_143822; RV32ZVE32F-NEXT:  .LBB44_5: # %else83823; RV32ZVE32F-NEXT:    andi a0, t0, 323824; RV32ZVE32F-NEXT:    bnez a0, .LBB44_153825; RV32ZVE32F-NEXT:  .LBB44_6: # %else103826; RV32ZVE32F-NEXT:    andi a0, t0, 643827; RV32ZVE32F-NEXT:    bnez a0, .LBB44_163828; RV32ZVE32F-NEXT:  .LBB44_7: # %else123829; RV32ZVE32F-NEXT:    andi a0, t0, -1283830; RV32ZVE32F-NEXT:    beqz a0, .LBB44_93831; RV32ZVE32F-NEXT:  .LBB44_8: # %cond.store133832; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma3833; RV32ZVE32F-NEXT:    vslidedown.vi v8, v8, 73834; RV32ZVE32F-NEXT:    vmv.x.s a0, v83835; RV32ZVE32F-NEXT:    sw a2, 0(a0)3836; RV32ZVE32F-NEXT:    sw a3, 4(a0)3837; RV32ZVE32F-NEXT:  .LBB44_9: # %else143838; RV32ZVE32F-NEXT:    lw s0, 12(sp) # 4-byte Folded Reload3839; RV32ZVE32F-NEXT:    lw s1, 8(sp) # 4-byte Folded Reload3840; RV32ZVE32F-NEXT:    lw s2, 4(sp) # 4-byte Folded Reload3841; RV32ZVE32F-NEXT:    .cfi_restore s03842; RV32ZVE32F-NEXT:    .cfi_restore s13843; RV32ZVE32F-NEXT:    .cfi_restore s23844; RV32ZVE32F-NEXT:    addi sp, sp, 163845; RV32ZVE32F-NEXT:    .cfi_def_cfa_offset 03846; RV32ZVE32F-NEXT:    ret3847; RV32ZVE32F-NEXT:  .LBB44_10: # %cond.store3848; RV32ZVE32F-NEXT:    .cfi_restore_state3849; RV32ZVE32F-NEXT:    lw a1, 0(a0)3850; RV32ZVE32F-NEXT:    lw a0, 4(a0)3851; RV32ZVE32F-NEXT:    vmv.x.s s2, v83852; RV32ZVE32F-NEXT:    sw a1, 0(s2)3853; RV32ZVE32F-NEXT:    sw a0, 4(s2)3854; RV32ZVE32F-NEXT:    andi a0, t0, 23855; RV32ZVE32F-NEXT:    beqz a0, .LBB44_23856; RV32ZVE32F-NEXT:  .LBB44_11: # %cond.store13857; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma3858; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 13859; RV32ZVE32F-NEXT:    vmv.x.s a0, v103860; RV32ZVE32F-NEXT:    sw s0, 0(a0)3861; RV32ZVE32F-NEXT:    sw s1, 4(a0)3862; RV32ZVE32F-NEXT:    andi a0, t0, 43863; RV32ZVE32F-NEXT:    beqz a0, .LBB44_33864; RV32ZVE32F-NEXT:  .LBB44_12: # %cond.store33865; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma3866; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 23867; RV32ZVE32F-NEXT:    vmv.x.s a0, v103868; RV32ZVE32F-NEXT:    sw t5, 0(a0)3869; RV32ZVE32F-NEXT:    sw t6, 4(a0)3870; RV32ZVE32F-NEXT:    andi a0, t0, 83871; RV32ZVE32F-NEXT:    beqz a0, .LBB44_43872; RV32ZVE32F-NEXT:  .LBB44_13: # %cond.store53873; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma3874; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 33875; RV32ZVE32F-NEXT:    vmv.x.s a0, v103876; RV32ZVE32F-NEXT:    sw t3, 0(a0)3877; RV32ZVE32F-NEXT:    sw t4, 4(a0)3878; RV32ZVE32F-NEXT:    andi a0, t0, 163879; RV32ZVE32F-NEXT:    beqz a0, .LBB44_53880; RV32ZVE32F-NEXT:  .LBB44_14: # %cond.store73881; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma3882; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 43883; RV32ZVE32F-NEXT:    vmv.x.s a0, v103884; RV32ZVE32F-NEXT:    sw t1, 0(a0)3885; RV32ZVE32F-NEXT:    sw t2, 4(a0)3886; RV32ZVE32F-NEXT:    andi a0, t0, 323887; RV32ZVE32F-NEXT:    beqz a0, .LBB44_63888; RV32ZVE32F-NEXT:  .LBB44_15: # %cond.store93889; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma3890; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 53891; RV32ZVE32F-NEXT:    vmv.x.s a0, v103892; RV32ZVE32F-NEXT:    sw a6, 0(a0)3893; RV32ZVE32F-NEXT:    sw a7, 4(a0)3894; RV32ZVE32F-NEXT:    andi a0, t0, 643895; RV32ZVE32F-NEXT:    beqz a0, .LBB44_73896; RV32ZVE32F-NEXT:  .LBB44_16: # %cond.store113897; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma3898; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 63899; RV32ZVE32F-NEXT:    vmv.x.s a0, v103900; RV32ZVE32F-NEXT:    sw a4, 0(a0)3901; RV32ZVE32F-NEXT:    sw a5, 4(a0)3902; RV32ZVE32F-NEXT:    andi a0, t0, -1283903; RV32ZVE32F-NEXT:    bnez a0, .LBB44_83904; RV32ZVE32F-NEXT:    j .LBB44_93905;3906; RV64ZVE32F-LABEL: mscatter_baseidx_zext_v8i8_v8i64:3907; RV64ZVE32F:       # %bb.0:3908; RV64ZVE32F-NEXT:    ld a5, 40(a0)3909; RV64ZVE32F-NEXT:    ld a3, 48(a0)3910; RV64ZVE32F-NEXT:    ld a2, 56(a0)3911; RV64ZVE32F-NEXT:    ld t1, 8(a0)3912; RV64ZVE32F-NEXT:    ld t0, 16(a0)3913; RV64ZVE32F-NEXT:    ld a7, 24(a0)3914; RV64ZVE32F-NEXT:    ld a6, 32(a0)3915; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma3916; RV64ZVE32F-NEXT:    vmv.x.s a4, v03917; RV64ZVE32F-NEXT:    andi t2, a4, 13918; RV64ZVE32F-NEXT:    beqz t2, .LBB44_23919; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store3920; RV64ZVE32F-NEXT:    ld a0, 0(a0)3921; RV64ZVE32F-NEXT:    vmv.x.s t2, v83922; RV64ZVE32F-NEXT:    zext.b t2, t23923; RV64ZVE32F-NEXT:    slli t2, t2, 33924; RV64ZVE32F-NEXT:    add t2, a1, t23925; RV64ZVE32F-NEXT:    sd a0, 0(t2)3926; RV64ZVE32F-NEXT:  .LBB44_2: # %else3927; RV64ZVE32F-NEXT:    andi a0, a4, 23928; RV64ZVE32F-NEXT:    beqz a0, .LBB44_43929; RV64ZVE32F-NEXT:  # %bb.3: # %cond.store13930; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma3931; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 13932; RV64ZVE32F-NEXT:    vmv.x.s a0, v93933; RV64ZVE32F-NEXT:    zext.b a0, a03934; RV64ZVE32F-NEXT:    slli a0, a0, 33935; RV64ZVE32F-NEXT:    add a0, a1, a03936; RV64ZVE32F-NEXT:    sd t1, 0(a0)3937; RV64ZVE32F-NEXT:  .LBB44_4: # %else23938; RV64ZVE32F-NEXT:    andi a0, a4, 43939; RV64ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma3940; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 23941; RV64ZVE32F-NEXT:    beqz a0, .LBB44_63942; RV64ZVE32F-NEXT:  # %bb.5: # %cond.store33943; RV64ZVE32F-NEXT:    vmv.x.s a0, v93944; RV64ZVE32F-NEXT:    zext.b a0, a03945; RV64ZVE32F-NEXT:    slli a0, a0, 33946; RV64ZVE32F-NEXT:    add a0, a1, a03947; RV64ZVE32F-NEXT:    sd t0, 0(a0)3948; RV64ZVE32F-NEXT:  .LBB44_6: # %else43949; RV64ZVE32F-NEXT:    andi a0, a4, 83950; RV64ZVE32F-NEXT:    beqz a0, .LBB44_83951; RV64ZVE32F-NEXT:  # %bb.7: # %cond.store53952; RV64ZVE32F-NEXT:    vslidedown.vi v9, v9, 13953; RV64ZVE32F-NEXT:    vmv.x.s a0, v93954; RV64ZVE32F-NEXT:    zext.b a0, a03955; RV64ZVE32F-NEXT:    slli a0, a0, 33956; RV64ZVE32F-NEXT:    add a0, a1, a03957; RV64ZVE32F-NEXT:    sd a7, 0(a0)3958; RV64ZVE32F-NEXT:  .LBB44_8: # %else63959; RV64ZVE32F-NEXT:    andi a0, a4, 163960; RV64ZVE32F-NEXT:    vsetivli zero, 4, e8, mf2, ta, ma3961; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 43962; RV64ZVE32F-NEXT:    beqz a0, .LBB44_103963; RV64ZVE32F-NEXT:  # %bb.9: # %cond.store73964; RV64ZVE32F-NEXT:    vmv.x.s a0, v83965; RV64ZVE32F-NEXT:    zext.b a0, a03966; RV64ZVE32F-NEXT:    slli a0, a0, 33967; RV64ZVE32F-NEXT:    add a0, a1, a03968; RV64ZVE32F-NEXT:    sd a6, 0(a0)3969; RV64ZVE32F-NEXT:  .LBB44_10: # %else83970; RV64ZVE32F-NEXT:    andi a0, a4, 323971; RV64ZVE32F-NEXT:    beqz a0, .LBB44_123972; RV64ZVE32F-NEXT:  # %bb.11: # %cond.store93973; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma3974; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 13975; RV64ZVE32F-NEXT:    vmv.x.s a0, v93976; RV64ZVE32F-NEXT:    zext.b a0, a03977; RV64ZVE32F-NEXT:    slli a0, a0, 33978; RV64ZVE32F-NEXT:    add a0, a1, a03979; RV64ZVE32F-NEXT:    sd a5, 0(a0)3980; RV64ZVE32F-NEXT:  .LBB44_12: # %else103981; RV64ZVE32F-NEXT:    andi a0, a4, 643982; RV64ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma3983; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 23984; RV64ZVE32F-NEXT:    bnez a0, .LBB44_153985; RV64ZVE32F-NEXT:  # %bb.13: # %else123986; RV64ZVE32F-NEXT:    andi a0, a4, -1283987; RV64ZVE32F-NEXT:    bnez a0, .LBB44_163988; RV64ZVE32F-NEXT:  .LBB44_14: # %else143989; RV64ZVE32F-NEXT:    ret3990; RV64ZVE32F-NEXT:  .LBB44_15: # %cond.store113991; RV64ZVE32F-NEXT:    vmv.x.s a0, v83992; RV64ZVE32F-NEXT:    zext.b a0, a03993; RV64ZVE32F-NEXT:    slli a0, a0, 33994; RV64ZVE32F-NEXT:    add a0, a1, a03995; RV64ZVE32F-NEXT:    sd a3, 0(a0)3996; RV64ZVE32F-NEXT:    andi a0, a4, -1283997; RV64ZVE32F-NEXT:    beqz a0, .LBB44_143998; RV64ZVE32F-NEXT:  .LBB44_16: # %cond.store133999; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 14000; RV64ZVE32F-NEXT:    vmv.x.s a0, v84001; RV64ZVE32F-NEXT:    zext.b a0, a04002; RV64ZVE32F-NEXT:    slli a0, a0, 34003; RV64ZVE32F-NEXT:    add a0, a1, a04004; RV64ZVE32F-NEXT:    sd a2, 0(a0)4005; RV64ZVE32F-NEXT:    ret4006  %eidxs = zext <8 x i8> %idxs to <8 x i64>4007  %ptrs = getelementptr inbounds i64, ptr %base, <8 x i64> %eidxs4008  call void @llvm.masked.scatter.v8i64.v8p0(<8 x i64> %val, <8 x ptr> %ptrs, i32 8, <8 x i1> %m)4009  ret void4010}4011 4012define void @mscatter_baseidx_v8i16_v8i64(<8 x i64> %val, ptr %base, <8 x i16> %idxs, <8 x i1> %m) {4013; RV32V-LABEL: mscatter_baseidx_v8i16_v8i64:4014; RV32V:       # %bb.0:4015; RV32V-NEXT:    li a1, 84016; RV32V-NEXT:    vsetivli zero, 8, e16, m1, ta, ma4017; RV32V-NEXT:    vwmulsu.vx v14, v12, a14018; RV32V-NEXT:    vsetvli zero, zero, e64, m4, ta, ma4019; RV32V-NEXT:    vsoxei32.v v8, (a0), v14, v0.t4020; RV32V-NEXT:    ret4021;4022; RV64V-LABEL: mscatter_baseidx_v8i16_v8i64:4023; RV64V:       # %bb.0:4024; RV64V-NEXT:    vsetivli zero, 8, e64, m4, ta, ma4025; RV64V-NEXT:    vsext.vf4 v16, v124026; RV64V-NEXT:    vsll.vi v12, v16, 34027; RV64V-NEXT:    vsoxei64.v v8, (a0), v12, v0.t4028; RV64V-NEXT:    ret4029;4030; RV32ZVE32F-LABEL: mscatter_baseidx_v8i16_v8i64:4031; RV32ZVE32F:       # %bb.0:4032; RV32ZVE32F-NEXT:    addi sp, sp, -164033; RV32ZVE32F-NEXT:    .cfi_def_cfa_offset 164034; RV32ZVE32F-NEXT:    sw s0, 12(sp) # 4-byte Folded Spill4035; RV32ZVE32F-NEXT:    sw s1, 8(sp) # 4-byte Folded Spill4036; RV32ZVE32F-NEXT:    sw s2, 4(sp) # 4-byte Folded Spill4037; RV32ZVE32F-NEXT:    .cfi_offset s0, -44038; RV32ZVE32F-NEXT:    .cfi_offset s1, -84039; RV32ZVE32F-NEXT:    .cfi_offset s2, -124040; RV32ZVE32F-NEXT:    .cfi_remember_state4041; RV32ZVE32F-NEXT:    lw a2, 56(a0)4042; RV32ZVE32F-NEXT:    lw a3, 60(a0)4043; RV32ZVE32F-NEXT:    lw a6, 40(a0)4044; RV32ZVE32F-NEXT:    lw a7, 44(a0)4045; RV32ZVE32F-NEXT:    lw a4, 48(a0)4046; RV32ZVE32F-NEXT:    lw a5, 52(a0)4047; RV32ZVE32F-NEXT:    lw t2, 24(a0)4048; RV32ZVE32F-NEXT:    lw t3, 28(a0)4049; RV32ZVE32F-NEXT:    lw t0, 32(a0)4050; RV32ZVE32F-NEXT:    lw t1, 36(a0)4051; RV32ZVE32F-NEXT:    lw t6, 8(a0)4052; RV32ZVE32F-NEXT:    lw s0, 12(a0)4053; RV32ZVE32F-NEXT:    lw t4, 16(a0)4054; RV32ZVE32F-NEXT:    lw t5, 20(a0)4055; RV32ZVE32F-NEXT:    vsetivli zero, 8, e32, m2, ta, ma4056; RV32ZVE32F-NEXT:    vmv.v.x v10, a14057; RV32ZVE32F-NEXT:    li s1, 84058; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma4059; RV32ZVE32F-NEXT:    vmv.x.s a1, v04060; RV32ZVE32F-NEXT:    andi s2, a1, 14061; RV32ZVE32F-NEXT:    vsetvli zero, zero, e16, m1, ta, ma4062; RV32ZVE32F-NEXT:    vwmaccus.vx v10, s1, v84063; RV32ZVE32F-NEXT:    bnez s2, .LBB45_104064; RV32ZVE32F-NEXT:  # %bb.1: # %else4065; RV32ZVE32F-NEXT:    andi a0, a1, 24066; RV32ZVE32F-NEXT:    bnez a0, .LBB45_114067; RV32ZVE32F-NEXT:  .LBB45_2: # %else24068; RV32ZVE32F-NEXT:    andi a0, a1, 44069; RV32ZVE32F-NEXT:    bnez a0, .LBB45_124070; RV32ZVE32F-NEXT:  .LBB45_3: # %else44071; RV32ZVE32F-NEXT:    andi a0, a1, 84072; RV32ZVE32F-NEXT:    bnez a0, .LBB45_134073; RV32ZVE32F-NEXT:  .LBB45_4: # %else64074; RV32ZVE32F-NEXT:    andi a0, a1, 164075; RV32ZVE32F-NEXT:    bnez a0, .LBB45_144076; RV32ZVE32F-NEXT:  .LBB45_5: # %else84077; RV32ZVE32F-NEXT:    andi a0, a1, 324078; RV32ZVE32F-NEXT:    bnez a0, .LBB45_154079; RV32ZVE32F-NEXT:  .LBB45_6: # %else104080; RV32ZVE32F-NEXT:    andi a0, a1, 644081; RV32ZVE32F-NEXT:    bnez a0, .LBB45_164082; RV32ZVE32F-NEXT:  .LBB45_7: # %else124083; RV32ZVE32F-NEXT:    andi a0, a1, -1284084; RV32ZVE32F-NEXT:    beqz a0, .LBB45_94085; RV32ZVE32F-NEXT:  .LBB45_8: # %cond.store134086; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma4087; RV32ZVE32F-NEXT:    vslidedown.vi v8, v10, 74088; RV32ZVE32F-NEXT:    vmv.x.s a0, v84089; RV32ZVE32F-NEXT:    sw a2, 0(a0)4090; RV32ZVE32F-NEXT:    sw a3, 4(a0)4091; RV32ZVE32F-NEXT:  .LBB45_9: # %else144092; RV32ZVE32F-NEXT:    lw s0, 12(sp) # 4-byte Folded Reload4093; RV32ZVE32F-NEXT:    lw s1, 8(sp) # 4-byte Folded Reload4094; RV32ZVE32F-NEXT:    lw s2, 4(sp) # 4-byte Folded Reload4095; RV32ZVE32F-NEXT:    .cfi_restore s04096; RV32ZVE32F-NEXT:    .cfi_restore s14097; RV32ZVE32F-NEXT:    .cfi_restore s24098; RV32ZVE32F-NEXT:    addi sp, sp, 164099; RV32ZVE32F-NEXT:    .cfi_def_cfa_offset 04100; RV32ZVE32F-NEXT:    ret4101; RV32ZVE32F-NEXT:  .LBB45_10: # %cond.store4102; RV32ZVE32F-NEXT:    .cfi_restore_state4103; RV32ZVE32F-NEXT:    lw s1, 0(a0)4104; RV32ZVE32F-NEXT:    lw a0, 4(a0)4105; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma4106; RV32ZVE32F-NEXT:    vmv.x.s s2, v104107; RV32ZVE32F-NEXT:    sw s1, 0(s2)4108; RV32ZVE32F-NEXT:    sw a0, 4(s2)4109; RV32ZVE32F-NEXT:    andi a0, a1, 24110; RV32ZVE32F-NEXT:    beqz a0, .LBB45_24111; RV32ZVE32F-NEXT:  .LBB45_11: # %cond.store14112; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma4113; RV32ZVE32F-NEXT:    vslidedown.vi v8, v10, 14114; RV32ZVE32F-NEXT:    vmv.x.s a0, v84115; RV32ZVE32F-NEXT:    sw t6, 0(a0)4116; RV32ZVE32F-NEXT:    sw s0, 4(a0)4117; RV32ZVE32F-NEXT:    andi a0, a1, 44118; RV32ZVE32F-NEXT:    beqz a0, .LBB45_34119; RV32ZVE32F-NEXT:  .LBB45_12: # %cond.store34120; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma4121; RV32ZVE32F-NEXT:    vslidedown.vi v8, v10, 24122; RV32ZVE32F-NEXT:    vmv.x.s a0, v84123; RV32ZVE32F-NEXT:    sw t4, 0(a0)4124; RV32ZVE32F-NEXT:    sw t5, 4(a0)4125; RV32ZVE32F-NEXT:    andi a0, a1, 84126; RV32ZVE32F-NEXT:    beqz a0, .LBB45_44127; RV32ZVE32F-NEXT:  .LBB45_13: # %cond.store54128; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma4129; RV32ZVE32F-NEXT:    vslidedown.vi v8, v10, 34130; RV32ZVE32F-NEXT:    vmv.x.s a0, v84131; RV32ZVE32F-NEXT:    sw t2, 0(a0)4132; RV32ZVE32F-NEXT:    sw t3, 4(a0)4133; RV32ZVE32F-NEXT:    andi a0, a1, 164134; RV32ZVE32F-NEXT:    beqz a0, .LBB45_54135; RV32ZVE32F-NEXT:  .LBB45_14: # %cond.store74136; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma4137; RV32ZVE32F-NEXT:    vslidedown.vi v8, v10, 44138; RV32ZVE32F-NEXT:    vmv.x.s a0, v84139; RV32ZVE32F-NEXT:    sw t0, 0(a0)4140; RV32ZVE32F-NEXT:    sw t1, 4(a0)4141; RV32ZVE32F-NEXT:    andi a0, a1, 324142; RV32ZVE32F-NEXT:    beqz a0, .LBB45_64143; RV32ZVE32F-NEXT:  .LBB45_15: # %cond.store94144; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma4145; RV32ZVE32F-NEXT:    vslidedown.vi v8, v10, 54146; RV32ZVE32F-NEXT:    vmv.x.s a0, v84147; RV32ZVE32F-NEXT:    sw a6, 0(a0)4148; RV32ZVE32F-NEXT:    sw a7, 4(a0)4149; RV32ZVE32F-NEXT:    andi a0, a1, 644150; RV32ZVE32F-NEXT:    beqz a0, .LBB45_74151; RV32ZVE32F-NEXT:  .LBB45_16: # %cond.store114152; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma4153; RV32ZVE32F-NEXT:    vslidedown.vi v8, v10, 64154; RV32ZVE32F-NEXT:    vmv.x.s a0, v84155; RV32ZVE32F-NEXT:    sw a4, 0(a0)4156; RV32ZVE32F-NEXT:    sw a5, 4(a0)4157; RV32ZVE32F-NEXT:    andi a0, a1, -1284158; RV32ZVE32F-NEXT:    bnez a0, .LBB45_84159; RV32ZVE32F-NEXT:    j .LBB45_94160;4161; RV64ZVE32F-LABEL: mscatter_baseidx_v8i16_v8i64:4162; RV64ZVE32F:       # %bb.0:4163; RV64ZVE32F-NEXT:    ld a5, 40(a0)4164; RV64ZVE32F-NEXT:    ld a3, 48(a0)4165; RV64ZVE32F-NEXT:    ld a2, 56(a0)4166; RV64ZVE32F-NEXT:    ld t1, 8(a0)4167; RV64ZVE32F-NEXT:    ld t0, 16(a0)4168; RV64ZVE32F-NEXT:    ld a7, 24(a0)4169; RV64ZVE32F-NEXT:    ld a6, 32(a0)4170; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma4171; RV64ZVE32F-NEXT:    vmv.x.s a4, v04172; RV64ZVE32F-NEXT:    andi t2, a4, 14173; RV64ZVE32F-NEXT:    beqz t2, .LBB45_24174; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store4175; RV64ZVE32F-NEXT:    ld a0, 0(a0)4176; RV64ZVE32F-NEXT:    vsetvli zero, zero, e16, m2, ta, ma4177; RV64ZVE32F-NEXT:    vmv.x.s t2, v84178; RV64ZVE32F-NEXT:    slli t2, t2, 34179; RV64ZVE32F-NEXT:    add t2, a1, t24180; RV64ZVE32F-NEXT:    sd a0, 0(t2)4181; RV64ZVE32F-NEXT:  .LBB45_2: # %else4182; RV64ZVE32F-NEXT:    andi a0, a4, 24183; RV64ZVE32F-NEXT:    beqz a0, .LBB45_44184; RV64ZVE32F-NEXT:  # %bb.3: # %cond.store14185; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma4186; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 14187; RV64ZVE32F-NEXT:    vmv.x.s a0, v94188; RV64ZVE32F-NEXT:    slli a0, a0, 34189; RV64ZVE32F-NEXT:    add a0, a1, a04190; RV64ZVE32F-NEXT:    sd t1, 0(a0)4191; RV64ZVE32F-NEXT:  .LBB45_4: # %else24192; RV64ZVE32F-NEXT:    andi a0, a4, 44193; RV64ZVE32F-NEXT:    vsetivli zero, 2, e16, mf2, ta, ma4194; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 24195; RV64ZVE32F-NEXT:    beqz a0, .LBB45_64196; RV64ZVE32F-NEXT:  # %bb.5: # %cond.store34197; RV64ZVE32F-NEXT:    vmv.x.s a0, v94198; RV64ZVE32F-NEXT:    slli a0, a0, 34199; RV64ZVE32F-NEXT:    add a0, a1, a04200; RV64ZVE32F-NEXT:    sd t0, 0(a0)4201; RV64ZVE32F-NEXT:  .LBB45_6: # %else44202; RV64ZVE32F-NEXT:    andi a0, a4, 84203; RV64ZVE32F-NEXT:    beqz a0, .LBB45_84204; RV64ZVE32F-NEXT:  # %bb.7: # %cond.store54205; RV64ZVE32F-NEXT:    vslidedown.vi v9, v9, 14206; RV64ZVE32F-NEXT:    vmv.x.s a0, v94207; RV64ZVE32F-NEXT:    slli a0, a0, 34208; RV64ZVE32F-NEXT:    add a0, a1, a04209; RV64ZVE32F-NEXT:    sd a7, 0(a0)4210; RV64ZVE32F-NEXT:  .LBB45_8: # %else64211; RV64ZVE32F-NEXT:    andi a0, a4, 164212; RV64ZVE32F-NEXT:    vsetivli zero, 4, e16, m1, ta, ma4213; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 44214; RV64ZVE32F-NEXT:    beqz a0, .LBB45_104215; RV64ZVE32F-NEXT:  # %bb.9: # %cond.store74216; RV64ZVE32F-NEXT:    vmv.x.s a0, v84217; RV64ZVE32F-NEXT:    slli a0, a0, 34218; RV64ZVE32F-NEXT:    add a0, a1, a04219; RV64ZVE32F-NEXT:    sd a6, 0(a0)4220; RV64ZVE32F-NEXT:  .LBB45_10: # %else84221; RV64ZVE32F-NEXT:    andi a0, a4, 324222; RV64ZVE32F-NEXT:    beqz a0, .LBB45_124223; RV64ZVE32F-NEXT:  # %bb.11: # %cond.store94224; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma4225; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 14226; RV64ZVE32F-NEXT:    vmv.x.s a0, v94227; RV64ZVE32F-NEXT:    slli a0, a0, 34228; RV64ZVE32F-NEXT:    add a0, a1, a04229; RV64ZVE32F-NEXT:    sd a5, 0(a0)4230; RV64ZVE32F-NEXT:  .LBB45_12: # %else104231; RV64ZVE32F-NEXT:    andi a0, a4, 644232; RV64ZVE32F-NEXT:    vsetivli zero, 2, e16, mf2, ta, ma4233; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 24234; RV64ZVE32F-NEXT:    bnez a0, .LBB45_154235; RV64ZVE32F-NEXT:  # %bb.13: # %else124236; RV64ZVE32F-NEXT:    andi a0, a4, -1284237; RV64ZVE32F-NEXT:    bnez a0, .LBB45_164238; RV64ZVE32F-NEXT:  .LBB45_14: # %else144239; RV64ZVE32F-NEXT:    ret4240; RV64ZVE32F-NEXT:  .LBB45_15: # %cond.store114241; RV64ZVE32F-NEXT:    vmv.x.s a0, v84242; RV64ZVE32F-NEXT:    slli a0, a0, 34243; RV64ZVE32F-NEXT:    add a0, a1, a04244; RV64ZVE32F-NEXT:    sd a3, 0(a0)4245; RV64ZVE32F-NEXT:    andi a0, a4, -1284246; RV64ZVE32F-NEXT:    beqz a0, .LBB45_144247; RV64ZVE32F-NEXT:  .LBB45_16: # %cond.store134248; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 14249; RV64ZVE32F-NEXT:    vmv.x.s a0, v84250; RV64ZVE32F-NEXT:    slli a0, a0, 34251; RV64ZVE32F-NEXT:    add a0, a1, a04252; RV64ZVE32F-NEXT:    sd a2, 0(a0)4253; RV64ZVE32F-NEXT:    ret4254  %ptrs = getelementptr inbounds i64, ptr %base, <8 x i16> %idxs4255  call void @llvm.masked.scatter.v8i64.v8p0(<8 x i64> %val, <8 x ptr> %ptrs, i32 8, <8 x i1> %m)4256  ret void4257}4258 4259define void @mscatter_baseidx_sext_v8i16_v8i64(<8 x i64> %val, ptr %base, <8 x i16> %idxs, <8 x i1> %m) {4260; RV32V-LABEL: mscatter_baseidx_sext_v8i16_v8i64:4261; RV32V:       # %bb.0:4262; RV32V-NEXT:    li a1, 84263; RV32V-NEXT:    vsetivli zero, 8, e16, m1, ta, ma4264; RV32V-NEXT:    vwmulsu.vx v14, v12, a14265; RV32V-NEXT:    vsetvli zero, zero, e64, m4, ta, ma4266; RV32V-NEXT:    vsoxei32.v v8, (a0), v14, v0.t4267; RV32V-NEXT:    ret4268;4269; RV64V-LABEL: mscatter_baseidx_sext_v8i16_v8i64:4270; RV64V:       # %bb.0:4271; RV64V-NEXT:    vsetivli zero, 8, e64, m4, ta, ma4272; RV64V-NEXT:    vsext.vf4 v16, v124273; RV64V-NEXT:    vsll.vi v12, v16, 34274; RV64V-NEXT:    vsoxei64.v v8, (a0), v12, v0.t4275; RV64V-NEXT:    ret4276;4277; RV32ZVE32F-LABEL: mscatter_baseidx_sext_v8i16_v8i64:4278; RV32ZVE32F:       # %bb.0:4279; RV32ZVE32F-NEXT:    addi sp, sp, -164280; RV32ZVE32F-NEXT:    .cfi_def_cfa_offset 164281; RV32ZVE32F-NEXT:    sw s0, 12(sp) # 4-byte Folded Spill4282; RV32ZVE32F-NEXT:    sw s1, 8(sp) # 4-byte Folded Spill4283; RV32ZVE32F-NEXT:    sw s2, 4(sp) # 4-byte Folded Spill4284; RV32ZVE32F-NEXT:    .cfi_offset s0, -44285; RV32ZVE32F-NEXT:    .cfi_offset s1, -84286; RV32ZVE32F-NEXT:    .cfi_offset s2, -124287; RV32ZVE32F-NEXT:    .cfi_remember_state4288; RV32ZVE32F-NEXT:    lw a2, 56(a0)4289; RV32ZVE32F-NEXT:    lw a3, 60(a0)4290; RV32ZVE32F-NEXT:    lw a6, 40(a0)4291; RV32ZVE32F-NEXT:    lw a7, 44(a0)4292; RV32ZVE32F-NEXT:    lw a4, 48(a0)4293; RV32ZVE32F-NEXT:    lw a5, 52(a0)4294; RV32ZVE32F-NEXT:    lw t2, 24(a0)4295; RV32ZVE32F-NEXT:    lw t3, 28(a0)4296; RV32ZVE32F-NEXT:    lw t0, 32(a0)4297; RV32ZVE32F-NEXT:    lw t1, 36(a0)4298; RV32ZVE32F-NEXT:    lw t6, 8(a0)4299; RV32ZVE32F-NEXT:    lw s0, 12(a0)4300; RV32ZVE32F-NEXT:    lw t4, 16(a0)4301; RV32ZVE32F-NEXT:    lw t5, 20(a0)4302; RV32ZVE32F-NEXT:    vsetivli zero, 8, e32, m2, ta, ma4303; RV32ZVE32F-NEXT:    vmv.v.x v10, a14304; RV32ZVE32F-NEXT:    li s1, 84305; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma4306; RV32ZVE32F-NEXT:    vmv.x.s a1, v04307; RV32ZVE32F-NEXT:    andi s2, a1, 14308; RV32ZVE32F-NEXT:    vsetvli zero, zero, e16, m1, ta, ma4309; RV32ZVE32F-NEXT:    vwmaccus.vx v10, s1, v84310; RV32ZVE32F-NEXT:    bnez s2, .LBB46_104311; RV32ZVE32F-NEXT:  # %bb.1: # %else4312; RV32ZVE32F-NEXT:    andi a0, a1, 24313; RV32ZVE32F-NEXT:    bnez a0, .LBB46_114314; RV32ZVE32F-NEXT:  .LBB46_2: # %else24315; RV32ZVE32F-NEXT:    andi a0, a1, 44316; RV32ZVE32F-NEXT:    bnez a0, .LBB46_124317; RV32ZVE32F-NEXT:  .LBB46_3: # %else44318; RV32ZVE32F-NEXT:    andi a0, a1, 84319; RV32ZVE32F-NEXT:    bnez a0, .LBB46_134320; RV32ZVE32F-NEXT:  .LBB46_4: # %else64321; RV32ZVE32F-NEXT:    andi a0, a1, 164322; RV32ZVE32F-NEXT:    bnez a0, .LBB46_144323; RV32ZVE32F-NEXT:  .LBB46_5: # %else84324; RV32ZVE32F-NEXT:    andi a0, a1, 324325; RV32ZVE32F-NEXT:    bnez a0, .LBB46_154326; RV32ZVE32F-NEXT:  .LBB46_6: # %else104327; RV32ZVE32F-NEXT:    andi a0, a1, 644328; RV32ZVE32F-NEXT:    bnez a0, .LBB46_164329; RV32ZVE32F-NEXT:  .LBB46_7: # %else124330; RV32ZVE32F-NEXT:    andi a0, a1, -1284331; RV32ZVE32F-NEXT:    beqz a0, .LBB46_94332; RV32ZVE32F-NEXT:  .LBB46_8: # %cond.store134333; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma4334; RV32ZVE32F-NEXT:    vslidedown.vi v8, v10, 74335; RV32ZVE32F-NEXT:    vmv.x.s a0, v84336; RV32ZVE32F-NEXT:    sw a2, 0(a0)4337; RV32ZVE32F-NEXT:    sw a3, 4(a0)4338; RV32ZVE32F-NEXT:  .LBB46_9: # %else144339; RV32ZVE32F-NEXT:    lw s0, 12(sp) # 4-byte Folded Reload4340; RV32ZVE32F-NEXT:    lw s1, 8(sp) # 4-byte Folded Reload4341; RV32ZVE32F-NEXT:    lw s2, 4(sp) # 4-byte Folded Reload4342; RV32ZVE32F-NEXT:    .cfi_restore s04343; RV32ZVE32F-NEXT:    .cfi_restore s14344; RV32ZVE32F-NEXT:    .cfi_restore s24345; RV32ZVE32F-NEXT:    addi sp, sp, 164346; RV32ZVE32F-NEXT:    .cfi_def_cfa_offset 04347; RV32ZVE32F-NEXT:    ret4348; RV32ZVE32F-NEXT:  .LBB46_10: # %cond.store4349; RV32ZVE32F-NEXT:    .cfi_restore_state4350; RV32ZVE32F-NEXT:    lw s1, 0(a0)4351; RV32ZVE32F-NEXT:    lw a0, 4(a0)4352; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma4353; RV32ZVE32F-NEXT:    vmv.x.s s2, v104354; RV32ZVE32F-NEXT:    sw s1, 0(s2)4355; RV32ZVE32F-NEXT:    sw a0, 4(s2)4356; RV32ZVE32F-NEXT:    andi a0, a1, 24357; RV32ZVE32F-NEXT:    beqz a0, .LBB46_24358; RV32ZVE32F-NEXT:  .LBB46_11: # %cond.store14359; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma4360; RV32ZVE32F-NEXT:    vslidedown.vi v8, v10, 14361; RV32ZVE32F-NEXT:    vmv.x.s a0, v84362; RV32ZVE32F-NEXT:    sw t6, 0(a0)4363; RV32ZVE32F-NEXT:    sw s0, 4(a0)4364; RV32ZVE32F-NEXT:    andi a0, a1, 44365; RV32ZVE32F-NEXT:    beqz a0, .LBB46_34366; RV32ZVE32F-NEXT:  .LBB46_12: # %cond.store34367; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma4368; RV32ZVE32F-NEXT:    vslidedown.vi v8, v10, 24369; RV32ZVE32F-NEXT:    vmv.x.s a0, v84370; RV32ZVE32F-NEXT:    sw t4, 0(a0)4371; RV32ZVE32F-NEXT:    sw t5, 4(a0)4372; RV32ZVE32F-NEXT:    andi a0, a1, 84373; RV32ZVE32F-NEXT:    beqz a0, .LBB46_44374; RV32ZVE32F-NEXT:  .LBB46_13: # %cond.store54375; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma4376; RV32ZVE32F-NEXT:    vslidedown.vi v8, v10, 34377; RV32ZVE32F-NEXT:    vmv.x.s a0, v84378; RV32ZVE32F-NEXT:    sw t2, 0(a0)4379; RV32ZVE32F-NEXT:    sw t3, 4(a0)4380; RV32ZVE32F-NEXT:    andi a0, a1, 164381; RV32ZVE32F-NEXT:    beqz a0, .LBB46_54382; RV32ZVE32F-NEXT:  .LBB46_14: # %cond.store74383; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma4384; RV32ZVE32F-NEXT:    vslidedown.vi v8, v10, 44385; RV32ZVE32F-NEXT:    vmv.x.s a0, v84386; RV32ZVE32F-NEXT:    sw t0, 0(a0)4387; RV32ZVE32F-NEXT:    sw t1, 4(a0)4388; RV32ZVE32F-NEXT:    andi a0, a1, 324389; RV32ZVE32F-NEXT:    beqz a0, .LBB46_64390; RV32ZVE32F-NEXT:  .LBB46_15: # %cond.store94391; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma4392; RV32ZVE32F-NEXT:    vslidedown.vi v8, v10, 54393; RV32ZVE32F-NEXT:    vmv.x.s a0, v84394; RV32ZVE32F-NEXT:    sw a6, 0(a0)4395; RV32ZVE32F-NEXT:    sw a7, 4(a0)4396; RV32ZVE32F-NEXT:    andi a0, a1, 644397; RV32ZVE32F-NEXT:    beqz a0, .LBB46_74398; RV32ZVE32F-NEXT:  .LBB46_16: # %cond.store114399; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma4400; RV32ZVE32F-NEXT:    vslidedown.vi v8, v10, 64401; RV32ZVE32F-NEXT:    vmv.x.s a0, v84402; RV32ZVE32F-NEXT:    sw a4, 0(a0)4403; RV32ZVE32F-NEXT:    sw a5, 4(a0)4404; RV32ZVE32F-NEXT:    andi a0, a1, -1284405; RV32ZVE32F-NEXT:    bnez a0, .LBB46_84406; RV32ZVE32F-NEXT:    j .LBB46_94407;4408; RV64ZVE32F-LABEL: mscatter_baseidx_sext_v8i16_v8i64:4409; RV64ZVE32F:       # %bb.0:4410; RV64ZVE32F-NEXT:    ld a5, 40(a0)4411; RV64ZVE32F-NEXT:    ld a3, 48(a0)4412; RV64ZVE32F-NEXT:    ld a2, 56(a0)4413; RV64ZVE32F-NEXT:    ld t1, 8(a0)4414; RV64ZVE32F-NEXT:    ld t0, 16(a0)4415; RV64ZVE32F-NEXT:    ld a7, 24(a0)4416; RV64ZVE32F-NEXT:    ld a6, 32(a0)4417; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma4418; RV64ZVE32F-NEXT:    vmv.x.s a4, v04419; RV64ZVE32F-NEXT:    andi t2, a4, 14420; RV64ZVE32F-NEXT:    beqz t2, .LBB46_24421; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store4422; RV64ZVE32F-NEXT:    ld a0, 0(a0)4423; RV64ZVE32F-NEXT:    vsetvli zero, zero, e16, m2, ta, ma4424; RV64ZVE32F-NEXT:    vmv.x.s t2, v84425; RV64ZVE32F-NEXT:    slli t2, t2, 34426; RV64ZVE32F-NEXT:    add t2, a1, t24427; RV64ZVE32F-NEXT:    sd a0, 0(t2)4428; RV64ZVE32F-NEXT:  .LBB46_2: # %else4429; RV64ZVE32F-NEXT:    andi a0, a4, 24430; RV64ZVE32F-NEXT:    beqz a0, .LBB46_44431; RV64ZVE32F-NEXT:  # %bb.3: # %cond.store14432; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma4433; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 14434; RV64ZVE32F-NEXT:    vmv.x.s a0, v94435; RV64ZVE32F-NEXT:    slli a0, a0, 34436; RV64ZVE32F-NEXT:    add a0, a1, a04437; RV64ZVE32F-NEXT:    sd t1, 0(a0)4438; RV64ZVE32F-NEXT:  .LBB46_4: # %else24439; RV64ZVE32F-NEXT:    andi a0, a4, 44440; RV64ZVE32F-NEXT:    vsetivli zero, 2, e16, mf2, ta, ma4441; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 24442; RV64ZVE32F-NEXT:    beqz a0, .LBB46_64443; RV64ZVE32F-NEXT:  # %bb.5: # %cond.store34444; RV64ZVE32F-NEXT:    vmv.x.s a0, v94445; RV64ZVE32F-NEXT:    slli a0, a0, 34446; RV64ZVE32F-NEXT:    add a0, a1, a04447; RV64ZVE32F-NEXT:    sd t0, 0(a0)4448; RV64ZVE32F-NEXT:  .LBB46_6: # %else44449; RV64ZVE32F-NEXT:    andi a0, a4, 84450; RV64ZVE32F-NEXT:    beqz a0, .LBB46_84451; RV64ZVE32F-NEXT:  # %bb.7: # %cond.store54452; RV64ZVE32F-NEXT:    vslidedown.vi v9, v9, 14453; RV64ZVE32F-NEXT:    vmv.x.s a0, v94454; RV64ZVE32F-NEXT:    slli a0, a0, 34455; RV64ZVE32F-NEXT:    add a0, a1, a04456; RV64ZVE32F-NEXT:    sd a7, 0(a0)4457; RV64ZVE32F-NEXT:  .LBB46_8: # %else64458; RV64ZVE32F-NEXT:    andi a0, a4, 164459; RV64ZVE32F-NEXT:    vsetivli zero, 4, e16, m1, ta, ma4460; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 44461; RV64ZVE32F-NEXT:    beqz a0, .LBB46_104462; RV64ZVE32F-NEXT:  # %bb.9: # %cond.store74463; RV64ZVE32F-NEXT:    vmv.x.s a0, v84464; RV64ZVE32F-NEXT:    slli a0, a0, 34465; RV64ZVE32F-NEXT:    add a0, a1, a04466; RV64ZVE32F-NEXT:    sd a6, 0(a0)4467; RV64ZVE32F-NEXT:  .LBB46_10: # %else84468; RV64ZVE32F-NEXT:    andi a0, a4, 324469; RV64ZVE32F-NEXT:    beqz a0, .LBB46_124470; RV64ZVE32F-NEXT:  # %bb.11: # %cond.store94471; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma4472; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 14473; RV64ZVE32F-NEXT:    vmv.x.s a0, v94474; RV64ZVE32F-NEXT:    slli a0, a0, 34475; RV64ZVE32F-NEXT:    add a0, a1, a04476; RV64ZVE32F-NEXT:    sd a5, 0(a0)4477; RV64ZVE32F-NEXT:  .LBB46_12: # %else104478; RV64ZVE32F-NEXT:    andi a0, a4, 644479; RV64ZVE32F-NEXT:    vsetivli zero, 2, e16, mf2, ta, ma4480; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 24481; RV64ZVE32F-NEXT:    bnez a0, .LBB46_154482; RV64ZVE32F-NEXT:  # %bb.13: # %else124483; RV64ZVE32F-NEXT:    andi a0, a4, -1284484; RV64ZVE32F-NEXT:    bnez a0, .LBB46_164485; RV64ZVE32F-NEXT:  .LBB46_14: # %else144486; RV64ZVE32F-NEXT:    ret4487; RV64ZVE32F-NEXT:  .LBB46_15: # %cond.store114488; RV64ZVE32F-NEXT:    vmv.x.s a0, v84489; RV64ZVE32F-NEXT:    slli a0, a0, 34490; RV64ZVE32F-NEXT:    add a0, a1, a04491; RV64ZVE32F-NEXT:    sd a3, 0(a0)4492; RV64ZVE32F-NEXT:    andi a0, a4, -1284493; RV64ZVE32F-NEXT:    beqz a0, .LBB46_144494; RV64ZVE32F-NEXT:  .LBB46_16: # %cond.store134495; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 14496; RV64ZVE32F-NEXT:    vmv.x.s a0, v84497; RV64ZVE32F-NEXT:    slli a0, a0, 34498; RV64ZVE32F-NEXT:    add a0, a1, a04499; RV64ZVE32F-NEXT:    sd a2, 0(a0)4500; RV64ZVE32F-NEXT:    ret4501  %eidxs = sext <8 x i16> %idxs to <8 x i64>4502  %ptrs = getelementptr inbounds i64, ptr %base, <8 x i64> %eidxs4503  call void @llvm.masked.scatter.v8i64.v8p0(<8 x i64> %val, <8 x ptr> %ptrs, i32 8, <8 x i1> %m)4504  ret void4505}4506 4507define void @mscatter_baseidx_zext_v8i16_v8i64(<8 x i64> %val, ptr %base, <8 x i16> %idxs, <8 x i1> %m) {4508; RV32V-LABEL: mscatter_baseidx_zext_v8i16_v8i64:4509; RV32V:       # %bb.0:4510; RV32V-NEXT:    li a1, 84511; RV32V-NEXT:    vsetivli zero, 8, e16, m1, ta, ma4512; RV32V-NEXT:    vwmulu.vx v14, v12, a14513; RV32V-NEXT:    vsetvli zero, zero, e64, m4, ta, ma4514; RV32V-NEXT:    vsoxei32.v v8, (a0), v14, v0.t4515; RV32V-NEXT:    ret4516;4517; RV64V-LABEL: mscatter_baseidx_zext_v8i16_v8i64:4518; RV64V:       # %bb.0:4519; RV64V-NEXT:    li a1, 84520; RV64V-NEXT:    vsetivli zero, 8, e16, m1, ta, ma4521; RV64V-NEXT:    vwmulu.vx v14, v12, a14522; RV64V-NEXT:    vsetvli zero, zero, e64, m4, ta, ma4523; RV64V-NEXT:    vsoxei32.v v8, (a0), v14, v0.t4524; RV64V-NEXT:    ret4525;4526; RV32ZVE32F-LABEL: mscatter_baseidx_zext_v8i16_v8i64:4527; RV32ZVE32F:       # %bb.0:4528; RV32ZVE32F-NEXT:    addi sp, sp, -164529; RV32ZVE32F-NEXT:    .cfi_def_cfa_offset 164530; RV32ZVE32F-NEXT:    sw s0, 12(sp) # 4-byte Folded Spill4531; RV32ZVE32F-NEXT:    sw s1, 8(sp) # 4-byte Folded Spill4532; RV32ZVE32F-NEXT:    sw s2, 4(sp) # 4-byte Folded Spill4533; RV32ZVE32F-NEXT:    .cfi_offset s0, -44534; RV32ZVE32F-NEXT:    .cfi_offset s1, -84535; RV32ZVE32F-NEXT:    .cfi_offset s2, -124536; RV32ZVE32F-NEXT:    .cfi_remember_state4537; RV32ZVE32F-NEXT:    lw a2, 56(a0)4538; RV32ZVE32F-NEXT:    lw a3, 60(a0)4539; RV32ZVE32F-NEXT:    lw a6, 40(a0)4540; RV32ZVE32F-NEXT:    lw a7, 44(a0)4541; RV32ZVE32F-NEXT:    lw a4, 48(a0)4542; RV32ZVE32F-NEXT:    lw a5, 52(a0)4543; RV32ZVE32F-NEXT:    lw t2, 24(a0)4544; RV32ZVE32F-NEXT:    lw t3, 28(a0)4545; RV32ZVE32F-NEXT:    lw t0, 32(a0)4546; RV32ZVE32F-NEXT:    lw t1, 36(a0)4547; RV32ZVE32F-NEXT:    lw t6, 8(a0)4548; RV32ZVE32F-NEXT:    lw s0, 12(a0)4549; RV32ZVE32F-NEXT:    lw t4, 16(a0)4550; RV32ZVE32F-NEXT:    lw t5, 20(a0)4551; RV32ZVE32F-NEXT:    vsetivli zero, 8, e32, m2, ta, ma4552; RV32ZVE32F-NEXT:    vmv.v.x v10, a14553; RV32ZVE32F-NEXT:    li s1, 84554; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma4555; RV32ZVE32F-NEXT:    vmv.x.s a1, v04556; RV32ZVE32F-NEXT:    andi s2, a1, 14557; RV32ZVE32F-NEXT:    vsetvli zero, zero, e16, m1, ta, ma4558; RV32ZVE32F-NEXT:    vwmaccu.vx v10, s1, v84559; RV32ZVE32F-NEXT:    bnez s2, .LBB47_104560; RV32ZVE32F-NEXT:  # %bb.1: # %else4561; RV32ZVE32F-NEXT:    andi a0, a1, 24562; RV32ZVE32F-NEXT:    bnez a0, .LBB47_114563; RV32ZVE32F-NEXT:  .LBB47_2: # %else24564; RV32ZVE32F-NEXT:    andi a0, a1, 44565; RV32ZVE32F-NEXT:    bnez a0, .LBB47_124566; RV32ZVE32F-NEXT:  .LBB47_3: # %else44567; RV32ZVE32F-NEXT:    andi a0, a1, 84568; RV32ZVE32F-NEXT:    bnez a0, .LBB47_134569; RV32ZVE32F-NEXT:  .LBB47_4: # %else64570; RV32ZVE32F-NEXT:    andi a0, a1, 164571; RV32ZVE32F-NEXT:    bnez a0, .LBB47_144572; RV32ZVE32F-NEXT:  .LBB47_5: # %else84573; RV32ZVE32F-NEXT:    andi a0, a1, 324574; RV32ZVE32F-NEXT:    bnez a0, .LBB47_154575; RV32ZVE32F-NEXT:  .LBB47_6: # %else104576; RV32ZVE32F-NEXT:    andi a0, a1, 644577; RV32ZVE32F-NEXT:    bnez a0, .LBB47_164578; RV32ZVE32F-NEXT:  .LBB47_7: # %else124579; RV32ZVE32F-NEXT:    andi a0, a1, -1284580; RV32ZVE32F-NEXT:    beqz a0, .LBB47_94581; RV32ZVE32F-NEXT:  .LBB47_8: # %cond.store134582; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma4583; RV32ZVE32F-NEXT:    vslidedown.vi v8, v10, 74584; RV32ZVE32F-NEXT:    vmv.x.s a0, v84585; RV32ZVE32F-NEXT:    sw a2, 0(a0)4586; RV32ZVE32F-NEXT:    sw a3, 4(a0)4587; RV32ZVE32F-NEXT:  .LBB47_9: # %else144588; RV32ZVE32F-NEXT:    lw s0, 12(sp) # 4-byte Folded Reload4589; RV32ZVE32F-NEXT:    lw s1, 8(sp) # 4-byte Folded Reload4590; RV32ZVE32F-NEXT:    lw s2, 4(sp) # 4-byte Folded Reload4591; RV32ZVE32F-NEXT:    .cfi_restore s04592; RV32ZVE32F-NEXT:    .cfi_restore s14593; RV32ZVE32F-NEXT:    .cfi_restore s24594; RV32ZVE32F-NEXT:    addi sp, sp, 164595; RV32ZVE32F-NEXT:    .cfi_def_cfa_offset 04596; RV32ZVE32F-NEXT:    ret4597; RV32ZVE32F-NEXT:  .LBB47_10: # %cond.store4598; RV32ZVE32F-NEXT:    .cfi_restore_state4599; RV32ZVE32F-NEXT:    lw s1, 0(a0)4600; RV32ZVE32F-NEXT:    lw a0, 4(a0)4601; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma4602; RV32ZVE32F-NEXT:    vmv.x.s s2, v104603; RV32ZVE32F-NEXT:    sw s1, 0(s2)4604; RV32ZVE32F-NEXT:    sw a0, 4(s2)4605; RV32ZVE32F-NEXT:    andi a0, a1, 24606; RV32ZVE32F-NEXT:    beqz a0, .LBB47_24607; RV32ZVE32F-NEXT:  .LBB47_11: # %cond.store14608; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma4609; RV32ZVE32F-NEXT:    vslidedown.vi v8, v10, 14610; RV32ZVE32F-NEXT:    vmv.x.s a0, v84611; RV32ZVE32F-NEXT:    sw t6, 0(a0)4612; RV32ZVE32F-NEXT:    sw s0, 4(a0)4613; RV32ZVE32F-NEXT:    andi a0, a1, 44614; RV32ZVE32F-NEXT:    beqz a0, .LBB47_34615; RV32ZVE32F-NEXT:  .LBB47_12: # %cond.store34616; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma4617; RV32ZVE32F-NEXT:    vslidedown.vi v8, v10, 24618; RV32ZVE32F-NEXT:    vmv.x.s a0, v84619; RV32ZVE32F-NEXT:    sw t4, 0(a0)4620; RV32ZVE32F-NEXT:    sw t5, 4(a0)4621; RV32ZVE32F-NEXT:    andi a0, a1, 84622; RV32ZVE32F-NEXT:    beqz a0, .LBB47_44623; RV32ZVE32F-NEXT:  .LBB47_13: # %cond.store54624; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma4625; RV32ZVE32F-NEXT:    vslidedown.vi v8, v10, 34626; RV32ZVE32F-NEXT:    vmv.x.s a0, v84627; RV32ZVE32F-NEXT:    sw t2, 0(a0)4628; RV32ZVE32F-NEXT:    sw t3, 4(a0)4629; RV32ZVE32F-NEXT:    andi a0, a1, 164630; RV32ZVE32F-NEXT:    beqz a0, .LBB47_54631; RV32ZVE32F-NEXT:  .LBB47_14: # %cond.store74632; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma4633; RV32ZVE32F-NEXT:    vslidedown.vi v8, v10, 44634; RV32ZVE32F-NEXT:    vmv.x.s a0, v84635; RV32ZVE32F-NEXT:    sw t0, 0(a0)4636; RV32ZVE32F-NEXT:    sw t1, 4(a0)4637; RV32ZVE32F-NEXT:    andi a0, a1, 324638; RV32ZVE32F-NEXT:    beqz a0, .LBB47_64639; RV32ZVE32F-NEXT:  .LBB47_15: # %cond.store94640; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma4641; RV32ZVE32F-NEXT:    vslidedown.vi v8, v10, 54642; RV32ZVE32F-NEXT:    vmv.x.s a0, v84643; RV32ZVE32F-NEXT:    sw a6, 0(a0)4644; RV32ZVE32F-NEXT:    sw a7, 4(a0)4645; RV32ZVE32F-NEXT:    andi a0, a1, 644646; RV32ZVE32F-NEXT:    beqz a0, .LBB47_74647; RV32ZVE32F-NEXT:  .LBB47_16: # %cond.store114648; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma4649; RV32ZVE32F-NEXT:    vslidedown.vi v8, v10, 64650; RV32ZVE32F-NEXT:    vmv.x.s a0, v84651; RV32ZVE32F-NEXT:    sw a4, 0(a0)4652; RV32ZVE32F-NEXT:    sw a5, 4(a0)4653; RV32ZVE32F-NEXT:    andi a0, a1, -1284654; RV32ZVE32F-NEXT:    bnez a0, .LBB47_84655; RV32ZVE32F-NEXT:    j .LBB47_94656;4657; RV64ZVE32F-LABEL: mscatter_baseidx_zext_v8i16_v8i64:4658; RV64ZVE32F:       # %bb.0:4659; RV64ZVE32F-NEXT:    ld a5, 40(a0)4660; RV64ZVE32F-NEXT:    ld a3, 48(a0)4661; RV64ZVE32F-NEXT:    ld a2, 56(a0)4662; RV64ZVE32F-NEXT:    ld t1, 8(a0)4663; RV64ZVE32F-NEXT:    ld t0, 16(a0)4664; RV64ZVE32F-NEXT:    ld a7, 24(a0)4665; RV64ZVE32F-NEXT:    ld a6, 32(a0)4666; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma4667; RV64ZVE32F-NEXT:    vmv.x.s a4, v04668; RV64ZVE32F-NEXT:    andi t2, a4, 14669; RV64ZVE32F-NEXT:    beqz t2, .LBB47_24670; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store4671; RV64ZVE32F-NEXT:    ld a0, 0(a0)4672; RV64ZVE32F-NEXT:    vsetvli zero, zero, e16, m2, ta, ma4673; RV64ZVE32F-NEXT:    vmv.x.s t2, v84674; RV64ZVE32F-NEXT:    slli t2, t2, 484675; RV64ZVE32F-NEXT:    srli t2, t2, 454676; RV64ZVE32F-NEXT:    add t2, a1, t24677; RV64ZVE32F-NEXT:    sd a0, 0(t2)4678; RV64ZVE32F-NEXT:  .LBB47_2: # %else4679; RV64ZVE32F-NEXT:    andi a0, a4, 24680; RV64ZVE32F-NEXT:    beqz a0, .LBB47_44681; RV64ZVE32F-NEXT:  # %bb.3: # %cond.store14682; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma4683; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 14684; RV64ZVE32F-NEXT:    vmv.x.s a0, v94685; RV64ZVE32F-NEXT:    slli a0, a0, 484686; RV64ZVE32F-NEXT:    srli a0, a0, 454687; RV64ZVE32F-NEXT:    add a0, a1, a04688; RV64ZVE32F-NEXT:    sd t1, 0(a0)4689; RV64ZVE32F-NEXT:  .LBB47_4: # %else24690; RV64ZVE32F-NEXT:    andi a0, a4, 44691; RV64ZVE32F-NEXT:    vsetivli zero, 2, e16, mf2, ta, ma4692; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 24693; RV64ZVE32F-NEXT:    beqz a0, .LBB47_64694; RV64ZVE32F-NEXT:  # %bb.5: # %cond.store34695; RV64ZVE32F-NEXT:    vmv.x.s a0, v94696; RV64ZVE32F-NEXT:    slli a0, a0, 484697; RV64ZVE32F-NEXT:    srli a0, a0, 454698; RV64ZVE32F-NEXT:    add a0, a1, a04699; RV64ZVE32F-NEXT:    sd t0, 0(a0)4700; RV64ZVE32F-NEXT:  .LBB47_6: # %else44701; RV64ZVE32F-NEXT:    andi a0, a4, 84702; RV64ZVE32F-NEXT:    beqz a0, .LBB47_84703; RV64ZVE32F-NEXT:  # %bb.7: # %cond.store54704; RV64ZVE32F-NEXT:    vslidedown.vi v9, v9, 14705; RV64ZVE32F-NEXT:    vmv.x.s a0, v94706; RV64ZVE32F-NEXT:    slli a0, a0, 484707; RV64ZVE32F-NEXT:    srli a0, a0, 454708; RV64ZVE32F-NEXT:    add a0, a1, a04709; RV64ZVE32F-NEXT:    sd a7, 0(a0)4710; RV64ZVE32F-NEXT:  .LBB47_8: # %else64711; RV64ZVE32F-NEXT:    andi a0, a4, 164712; RV64ZVE32F-NEXT:    vsetivli zero, 4, e16, m1, ta, ma4713; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 44714; RV64ZVE32F-NEXT:    beqz a0, .LBB47_104715; RV64ZVE32F-NEXT:  # %bb.9: # %cond.store74716; RV64ZVE32F-NEXT:    vmv.x.s a0, v84717; RV64ZVE32F-NEXT:    slli a0, a0, 484718; RV64ZVE32F-NEXT:    srli a0, a0, 454719; RV64ZVE32F-NEXT:    add a0, a1, a04720; RV64ZVE32F-NEXT:    sd a6, 0(a0)4721; RV64ZVE32F-NEXT:  .LBB47_10: # %else84722; RV64ZVE32F-NEXT:    andi a0, a4, 324723; RV64ZVE32F-NEXT:    beqz a0, .LBB47_124724; RV64ZVE32F-NEXT:  # %bb.11: # %cond.store94725; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma4726; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 14727; RV64ZVE32F-NEXT:    vmv.x.s a0, v94728; RV64ZVE32F-NEXT:    slli a0, a0, 484729; RV64ZVE32F-NEXT:    srli a0, a0, 454730; RV64ZVE32F-NEXT:    add a0, a1, a04731; RV64ZVE32F-NEXT:    sd a5, 0(a0)4732; RV64ZVE32F-NEXT:  .LBB47_12: # %else104733; RV64ZVE32F-NEXT:    andi a0, a4, 644734; RV64ZVE32F-NEXT:    vsetivli zero, 2, e16, mf2, ta, ma4735; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 24736; RV64ZVE32F-NEXT:    bnez a0, .LBB47_154737; RV64ZVE32F-NEXT:  # %bb.13: # %else124738; RV64ZVE32F-NEXT:    andi a0, a4, -1284739; RV64ZVE32F-NEXT:    bnez a0, .LBB47_164740; RV64ZVE32F-NEXT:  .LBB47_14: # %else144741; RV64ZVE32F-NEXT:    ret4742; RV64ZVE32F-NEXT:  .LBB47_15: # %cond.store114743; RV64ZVE32F-NEXT:    vmv.x.s a0, v84744; RV64ZVE32F-NEXT:    slli a0, a0, 484745; RV64ZVE32F-NEXT:    srli a0, a0, 454746; RV64ZVE32F-NEXT:    add a0, a1, a04747; RV64ZVE32F-NEXT:    sd a3, 0(a0)4748; RV64ZVE32F-NEXT:    andi a0, a4, -1284749; RV64ZVE32F-NEXT:    beqz a0, .LBB47_144750; RV64ZVE32F-NEXT:  .LBB47_16: # %cond.store134751; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 14752; RV64ZVE32F-NEXT:    vmv.x.s a0, v84753; RV64ZVE32F-NEXT:    slli a0, a0, 484754; RV64ZVE32F-NEXT:    srli a0, a0, 454755; RV64ZVE32F-NEXT:    add a0, a1, a04756; RV64ZVE32F-NEXT:    sd a2, 0(a0)4757; RV64ZVE32F-NEXT:    ret4758  %eidxs = zext <8 x i16> %idxs to <8 x i64>4759  %ptrs = getelementptr inbounds i64, ptr %base, <8 x i64> %eidxs4760  call void @llvm.masked.scatter.v8i64.v8p0(<8 x i64> %val, <8 x ptr> %ptrs, i32 8, <8 x i1> %m)4761  ret void4762}4763 4764define void @mscatter_baseidx_v8i32_v8i64(<8 x i64> %val, ptr %base, <8 x i32> %idxs, <8 x i1> %m) {4765; RV32V-LABEL: mscatter_baseidx_v8i32_v8i64:4766; RV32V:       # %bb.0:4767; RV32V-NEXT:    vsetivli zero, 8, e32, m2, ta, ma4768; RV32V-NEXT:    vsll.vi v12, v12, 34769; RV32V-NEXT:    vsetvli zero, zero, e64, m4, ta, ma4770; RV32V-NEXT:    vsoxei32.v v8, (a0), v12, v0.t4771; RV32V-NEXT:    ret4772;4773; RV64V-LABEL: mscatter_baseidx_v8i32_v8i64:4774; RV64V:       # %bb.0:4775; RV64V-NEXT:    li a1, 84776; RV64V-NEXT:    vsetivli zero, 8, e32, m2, ta, ma4777; RV64V-NEXT:    vwmulsu.vx v16, v12, a14778; RV64V-NEXT:    vsetvli zero, zero, e64, m4, ta, ma4779; RV64V-NEXT:    vsoxei64.v v8, (a0), v16, v0.t4780; RV64V-NEXT:    ret4781;4782; RV32ZVE32F-LABEL: mscatter_baseidx_v8i32_v8i64:4783; RV32ZVE32F:       # %bb.0:4784; RV32ZVE32F-NEXT:    addi sp, sp, -164785; RV32ZVE32F-NEXT:    .cfi_def_cfa_offset 164786; RV32ZVE32F-NEXT:    sw s0, 12(sp) # 4-byte Folded Spill4787; RV32ZVE32F-NEXT:    sw s1, 8(sp) # 4-byte Folded Spill4788; RV32ZVE32F-NEXT:    sw s2, 4(sp) # 4-byte Folded Spill4789; RV32ZVE32F-NEXT:    .cfi_offset s0, -44790; RV32ZVE32F-NEXT:    .cfi_offset s1, -84791; RV32ZVE32F-NEXT:    .cfi_offset s2, -124792; RV32ZVE32F-NEXT:    .cfi_remember_state4793; RV32ZVE32F-NEXT:    lw a2, 56(a0)4794; RV32ZVE32F-NEXT:    lw a3, 60(a0)4795; RV32ZVE32F-NEXT:    lw a6, 40(a0)4796; RV32ZVE32F-NEXT:    lw a7, 44(a0)4797; RV32ZVE32F-NEXT:    lw a4, 48(a0)4798; RV32ZVE32F-NEXT:    lw a5, 52(a0)4799; RV32ZVE32F-NEXT:    lw t3, 24(a0)4800; RV32ZVE32F-NEXT:    lw t4, 28(a0)4801; RV32ZVE32F-NEXT:    lw t1, 32(a0)4802; RV32ZVE32F-NEXT:    lw t2, 36(a0)4803; RV32ZVE32F-NEXT:    lw s0, 8(a0)4804; RV32ZVE32F-NEXT:    lw s1, 12(a0)4805; RV32ZVE32F-NEXT:    lw t5, 16(a0)4806; RV32ZVE32F-NEXT:    lw t6, 20(a0)4807; RV32ZVE32F-NEXT:    vsetivli zero, 8, e32, m2, ta, ma4808; RV32ZVE32F-NEXT:    vsll.vi v8, v8, 34809; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma4810; RV32ZVE32F-NEXT:    vmv.x.s t0, v04811; RV32ZVE32F-NEXT:    andi s2, t0, 14812; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma4813; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a14814; RV32ZVE32F-NEXT:    bnez s2, .LBB48_104815; RV32ZVE32F-NEXT:  # %bb.1: # %else4816; RV32ZVE32F-NEXT:    andi a0, t0, 24817; RV32ZVE32F-NEXT:    bnez a0, .LBB48_114818; RV32ZVE32F-NEXT:  .LBB48_2: # %else24819; RV32ZVE32F-NEXT:    andi a0, t0, 44820; RV32ZVE32F-NEXT:    bnez a0, .LBB48_124821; RV32ZVE32F-NEXT:  .LBB48_3: # %else44822; RV32ZVE32F-NEXT:    andi a0, t0, 84823; RV32ZVE32F-NEXT:    bnez a0, .LBB48_134824; RV32ZVE32F-NEXT:  .LBB48_4: # %else64825; RV32ZVE32F-NEXT:    andi a0, t0, 164826; RV32ZVE32F-NEXT:    bnez a0, .LBB48_144827; RV32ZVE32F-NEXT:  .LBB48_5: # %else84828; RV32ZVE32F-NEXT:    andi a0, t0, 324829; RV32ZVE32F-NEXT:    bnez a0, .LBB48_154830; RV32ZVE32F-NEXT:  .LBB48_6: # %else104831; RV32ZVE32F-NEXT:    andi a0, t0, 644832; RV32ZVE32F-NEXT:    bnez a0, .LBB48_164833; RV32ZVE32F-NEXT:  .LBB48_7: # %else124834; RV32ZVE32F-NEXT:    andi a0, t0, -1284835; RV32ZVE32F-NEXT:    beqz a0, .LBB48_94836; RV32ZVE32F-NEXT:  .LBB48_8: # %cond.store134837; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma4838; RV32ZVE32F-NEXT:    vslidedown.vi v8, v8, 74839; RV32ZVE32F-NEXT:    vmv.x.s a0, v84840; RV32ZVE32F-NEXT:    sw a2, 0(a0)4841; RV32ZVE32F-NEXT:    sw a3, 4(a0)4842; RV32ZVE32F-NEXT:  .LBB48_9: # %else144843; RV32ZVE32F-NEXT:    lw s0, 12(sp) # 4-byte Folded Reload4844; RV32ZVE32F-NEXT:    lw s1, 8(sp) # 4-byte Folded Reload4845; RV32ZVE32F-NEXT:    lw s2, 4(sp) # 4-byte Folded Reload4846; RV32ZVE32F-NEXT:    .cfi_restore s04847; RV32ZVE32F-NEXT:    .cfi_restore s14848; RV32ZVE32F-NEXT:    .cfi_restore s24849; RV32ZVE32F-NEXT:    addi sp, sp, 164850; RV32ZVE32F-NEXT:    .cfi_def_cfa_offset 04851; RV32ZVE32F-NEXT:    ret4852; RV32ZVE32F-NEXT:  .LBB48_10: # %cond.store4853; RV32ZVE32F-NEXT:    .cfi_restore_state4854; RV32ZVE32F-NEXT:    lw a1, 0(a0)4855; RV32ZVE32F-NEXT:    lw a0, 4(a0)4856; RV32ZVE32F-NEXT:    vmv.x.s s2, v84857; RV32ZVE32F-NEXT:    sw a1, 0(s2)4858; RV32ZVE32F-NEXT:    sw a0, 4(s2)4859; RV32ZVE32F-NEXT:    andi a0, t0, 24860; RV32ZVE32F-NEXT:    beqz a0, .LBB48_24861; RV32ZVE32F-NEXT:  .LBB48_11: # %cond.store14862; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma4863; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 14864; RV32ZVE32F-NEXT:    vmv.x.s a0, v104865; RV32ZVE32F-NEXT:    sw s0, 0(a0)4866; RV32ZVE32F-NEXT:    sw s1, 4(a0)4867; RV32ZVE32F-NEXT:    andi a0, t0, 44868; RV32ZVE32F-NEXT:    beqz a0, .LBB48_34869; RV32ZVE32F-NEXT:  .LBB48_12: # %cond.store34870; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma4871; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 24872; RV32ZVE32F-NEXT:    vmv.x.s a0, v104873; RV32ZVE32F-NEXT:    sw t5, 0(a0)4874; RV32ZVE32F-NEXT:    sw t6, 4(a0)4875; RV32ZVE32F-NEXT:    andi a0, t0, 84876; RV32ZVE32F-NEXT:    beqz a0, .LBB48_44877; RV32ZVE32F-NEXT:  .LBB48_13: # %cond.store54878; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma4879; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 34880; RV32ZVE32F-NEXT:    vmv.x.s a0, v104881; RV32ZVE32F-NEXT:    sw t3, 0(a0)4882; RV32ZVE32F-NEXT:    sw t4, 4(a0)4883; RV32ZVE32F-NEXT:    andi a0, t0, 164884; RV32ZVE32F-NEXT:    beqz a0, .LBB48_54885; RV32ZVE32F-NEXT:  .LBB48_14: # %cond.store74886; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma4887; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 44888; RV32ZVE32F-NEXT:    vmv.x.s a0, v104889; RV32ZVE32F-NEXT:    sw t1, 0(a0)4890; RV32ZVE32F-NEXT:    sw t2, 4(a0)4891; RV32ZVE32F-NEXT:    andi a0, t0, 324892; RV32ZVE32F-NEXT:    beqz a0, .LBB48_64893; RV32ZVE32F-NEXT:  .LBB48_15: # %cond.store94894; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma4895; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 54896; RV32ZVE32F-NEXT:    vmv.x.s a0, v104897; RV32ZVE32F-NEXT:    sw a6, 0(a0)4898; RV32ZVE32F-NEXT:    sw a7, 4(a0)4899; RV32ZVE32F-NEXT:    andi a0, t0, 644900; RV32ZVE32F-NEXT:    beqz a0, .LBB48_74901; RV32ZVE32F-NEXT:  .LBB48_16: # %cond.store114902; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma4903; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 64904; RV32ZVE32F-NEXT:    vmv.x.s a0, v104905; RV32ZVE32F-NEXT:    sw a4, 0(a0)4906; RV32ZVE32F-NEXT:    sw a5, 4(a0)4907; RV32ZVE32F-NEXT:    andi a0, t0, -1284908; RV32ZVE32F-NEXT:    bnez a0, .LBB48_84909; RV32ZVE32F-NEXT:    j .LBB48_94910;4911; RV64ZVE32F-LABEL: mscatter_baseidx_v8i32_v8i64:4912; RV64ZVE32F:       # %bb.0:4913; RV64ZVE32F-NEXT:    ld a5, 40(a0)4914; RV64ZVE32F-NEXT:    ld a3, 48(a0)4915; RV64ZVE32F-NEXT:    ld a2, 56(a0)4916; RV64ZVE32F-NEXT:    ld t1, 8(a0)4917; RV64ZVE32F-NEXT:    ld t0, 16(a0)4918; RV64ZVE32F-NEXT:    ld a7, 24(a0)4919; RV64ZVE32F-NEXT:    ld a6, 32(a0)4920; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma4921; RV64ZVE32F-NEXT:    vmv.x.s a4, v04922; RV64ZVE32F-NEXT:    andi t2, a4, 14923; RV64ZVE32F-NEXT:    beqz t2, .LBB48_24924; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store4925; RV64ZVE32F-NEXT:    ld a0, 0(a0)4926; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m4, ta, ma4927; RV64ZVE32F-NEXT:    vmv.x.s t2, v84928; RV64ZVE32F-NEXT:    slli t2, t2, 34929; RV64ZVE32F-NEXT:    add t2, a1, t24930; RV64ZVE32F-NEXT:    sd a0, 0(t2)4931; RV64ZVE32F-NEXT:  .LBB48_2: # %else4932; RV64ZVE32F-NEXT:    andi a0, a4, 24933; RV64ZVE32F-NEXT:    beqz a0, .LBB48_44934; RV64ZVE32F-NEXT:  # %bb.3: # %cond.store14935; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma4936; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 14937; RV64ZVE32F-NEXT:    vmv.x.s a0, v104938; RV64ZVE32F-NEXT:    slli a0, a0, 34939; RV64ZVE32F-NEXT:    add a0, a1, a04940; RV64ZVE32F-NEXT:    sd t1, 0(a0)4941; RV64ZVE32F-NEXT:  .LBB48_4: # %else24942; RV64ZVE32F-NEXT:    andi a0, a4, 44943; RV64ZVE32F-NEXT:    vsetivli zero, 2, e32, m1, ta, ma4944; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 24945; RV64ZVE32F-NEXT:    beqz a0, .LBB48_64946; RV64ZVE32F-NEXT:  # %bb.5: # %cond.store34947; RV64ZVE32F-NEXT:    vmv.x.s a0, v104948; RV64ZVE32F-NEXT:    slli a0, a0, 34949; RV64ZVE32F-NEXT:    add a0, a1, a04950; RV64ZVE32F-NEXT:    sd t0, 0(a0)4951; RV64ZVE32F-NEXT:  .LBB48_6: # %else44952; RV64ZVE32F-NEXT:    andi a0, a4, 84953; RV64ZVE32F-NEXT:    vsetivli zero, 4, e32, m2, ta, ma4954; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 44955; RV64ZVE32F-NEXT:    bnez a0, .LBB48_134956; RV64ZVE32F-NEXT:  # %bb.7: # %else64957; RV64ZVE32F-NEXT:    andi a0, a4, 164958; RV64ZVE32F-NEXT:    bnez a0, .LBB48_144959; RV64ZVE32F-NEXT:  .LBB48_8: # %else84960; RV64ZVE32F-NEXT:    andi a0, a4, 324961; RV64ZVE32F-NEXT:    beqz a0, .LBB48_104962; RV64ZVE32F-NEXT:  .LBB48_9: # %cond.store94963; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma4964; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 14965; RV64ZVE32F-NEXT:    vmv.x.s a0, v94966; RV64ZVE32F-NEXT:    slli a0, a0, 34967; RV64ZVE32F-NEXT:    add a0, a1, a04968; RV64ZVE32F-NEXT:    sd a5, 0(a0)4969; RV64ZVE32F-NEXT:  .LBB48_10: # %else104970; RV64ZVE32F-NEXT:    andi a0, a4, 644971; RV64ZVE32F-NEXT:    vsetivli zero, 2, e32, m1, ta, ma4972; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 24973; RV64ZVE32F-NEXT:    bnez a0, .LBB48_154974; RV64ZVE32F-NEXT:  # %bb.11: # %else124975; RV64ZVE32F-NEXT:    andi a0, a4, -1284976; RV64ZVE32F-NEXT:    bnez a0, .LBB48_164977; RV64ZVE32F-NEXT:  .LBB48_12: # %else144978; RV64ZVE32F-NEXT:    ret4979; RV64ZVE32F-NEXT:  .LBB48_13: # %cond.store54980; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma4981; RV64ZVE32F-NEXT:    vslidedown.vi v9, v10, 14982; RV64ZVE32F-NEXT:    vmv.x.s a0, v94983; RV64ZVE32F-NEXT:    slli a0, a0, 34984; RV64ZVE32F-NEXT:    add a0, a1, a04985; RV64ZVE32F-NEXT:    sd a7, 0(a0)4986; RV64ZVE32F-NEXT:    andi a0, a4, 164987; RV64ZVE32F-NEXT:    beqz a0, .LBB48_84988; RV64ZVE32F-NEXT:  .LBB48_14: # %cond.store74989; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma4990; RV64ZVE32F-NEXT:    vmv.x.s a0, v84991; RV64ZVE32F-NEXT:    slli a0, a0, 34992; RV64ZVE32F-NEXT:    add a0, a1, a04993; RV64ZVE32F-NEXT:    sd a6, 0(a0)4994; RV64ZVE32F-NEXT:    andi a0, a4, 324995; RV64ZVE32F-NEXT:    bnez a0, .LBB48_94996; RV64ZVE32F-NEXT:    j .LBB48_104997; RV64ZVE32F-NEXT:  .LBB48_15: # %cond.store114998; RV64ZVE32F-NEXT:    vmv.x.s a0, v84999; RV64ZVE32F-NEXT:    slli a0, a0, 35000; RV64ZVE32F-NEXT:    add a0, a1, a05001; RV64ZVE32F-NEXT:    sd a3, 0(a0)5002; RV64ZVE32F-NEXT:    andi a0, a4, -1285003; RV64ZVE32F-NEXT:    beqz a0, .LBB48_125004; RV64ZVE32F-NEXT:  .LBB48_16: # %cond.store135005; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 15006; RV64ZVE32F-NEXT:    vmv.x.s a0, v85007; RV64ZVE32F-NEXT:    slli a0, a0, 35008; RV64ZVE32F-NEXT:    add a0, a1, a05009; RV64ZVE32F-NEXT:    sd a2, 0(a0)5010; RV64ZVE32F-NEXT:    ret5011  %ptrs = getelementptr inbounds i64, ptr %base, <8 x i32> %idxs5012  call void @llvm.masked.scatter.v8i64.v8p0(<8 x i64> %val, <8 x ptr> %ptrs, i32 8, <8 x i1> %m)5013  ret void5014}5015 5016define void @mscatter_baseidx_sext_v8i32_v8i64(<8 x i64> %val, ptr %base, <8 x i32> %idxs, <8 x i1> %m) {5017; RV32V-LABEL: mscatter_baseidx_sext_v8i32_v8i64:5018; RV32V:       # %bb.0:5019; RV32V-NEXT:    vsetivli zero, 8, e32, m2, ta, ma5020; RV32V-NEXT:    vsll.vi v12, v12, 35021; RV32V-NEXT:    vsetvli zero, zero, e64, m4, ta, ma5022; RV32V-NEXT:    vsoxei32.v v8, (a0), v12, v0.t5023; RV32V-NEXT:    ret5024;5025; RV64V-LABEL: mscatter_baseidx_sext_v8i32_v8i64:5026; RV64V:       # %bb.0:5027; RV64V-NEXT:    li a1, 85028; RV64V-NEXT:    vsetivli zero, 8, e32, m2, ta, ma5029; RV64V-NEXT:    vwmulsu.vx v16, v12, a15030; RV64V-NEXT:    vsetvli zero, zero, e64, m4, ta, ma5031; RV64V-NEXT:    vsoxei64.v v8, (a0), v16, v0.t5032; RV64V-NEXT:    ret5033;5034; RV32ZVE32F-LABEL: mscatter_baseidx_sext_v8i32_v8i64:5035; RV32ZVE32F:       # %bb.0:5036; RV32ZVE32F-NEXT:    addi sp, sp, -165037; RV32ZVE32F-NEXT:    .cfi_def_cfa_offset 165038; RV32ZVE32F-NEXT:    sw s0, 12(sp) # 4-byte Folded Spill5039; RV32ZVE32F-NEXT:    sw s1, 8(sp) # 4-byte Folded Spill5040; RV32ZVE32F-NEXT:    sw s2, 4(sp) # 4-byte Folded Spill5041; RV32ZVE32F-NEXT:    .cfi_offset s0, -45042; RV32ZVE32F-NEXT:    .cfi_offset s1, -85043; RV32ZVE32F-NEXT:    .cfi_offset s2, -125044; RV32ZVE32F-NEXT:    .cfi_remember_state5045; RV32ZVE32F-NEXT:    lw a2, 56(a0)5046; RV32ZVE32F-NEXT:    lw a3, 60(a0)5047; RV32ZVE32F-NEXT:    lw a6, 40(a0)5048; RV32ZVE32F-NEXT:    lw a7, 44(a0)5049; RV32ZVE32F-NEXT:    lw a4, 48(a0)5050; RV32ZVE32F-NEXT:    lw a5, 52(a0)5051; RV32ZVE32F-NEXT:    lw t3, 24(a0)5052; RV32ZVE32F-NEXT:    lw t4, 28(a0)5053; RV32ZVE32F-NEXT:    lw t1, 32(a0)5054; RV32ZVE32F-NEXT:    lw t2, 36(a0)5055; RV32ZVE32F-NEXT:    lw s0, 8(a0)5056; RV32ZVE32F-NEXT:    lw s1, 12(a0)5057; RV32ZVE32F-NEXT:    lw t5, 16(a0)5058; RV32ZVE32F-NEXT:    lw t6, 20(a0)5059; RV32ZVE32F-NEXT:    vsetivli zero, 8, e32, m2, ta, ma5060; RV32ZVE32F-NEXT:    vsll.vi v8, v8, 35061; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma5062; RV32ZVE32F-NEXT:    vmv.x.s t0, v05063; RV32ZVE32F-NEXT:    andi s2, t0, 15064; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma5065; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a15066; RV32ZVE32F-NEXT:    bnez s2, .LBB49_105067; RV32ZVE32F-NEXT:  # %bb.1: # %else5068; RV32ZVE32F-NEXT:    andi a0, t0, 25069; RV32ZVE32F-NEXT:    bnez a0, .LBB49_115070; RV32ZVE32F-NEXT:  .LBB49_2: # %else25071; RV32ZVE32F-NEXT:    andi a0, t0, 45072; RV32ZVE32F-NEXT:    bnez a0, .LBB49_125073; RV32ZVE32F-NEXT:  .LBB49_3: # %else45074; RV32ZVE32F-NEXT:    andi a0, t0, 85075; RV32ZVE32F-NEXT:    bnez a0, .LBB49_135076; RV32ZVE32F-NEXT:  .LBB49_4: # %else65077; RV32ZVE32F-NEXT:    andi a0, t0, 165078; RV32ZVE32F-NEXT:    bnez a0, .LBB49_145079; RV32ZVE32F-NEXT:  .LBB49_5: # %else85080; RV32ZVE32F-NEXT:    andi a0, t0, 325081; RV32ZVE32F-NEXT:    bnez a0, .LBB49_155082; RV32ZVE32F-NEXT:  .LBB49_6: # %else105083; RV32ZVE32F-NEXT:    andi a0, t0, 645084; RV32ZVE32F-NEXT:    bnez a0, .LBB49_165085; RV32ZVE32F-NEXT:  .LBB49_7: # %else125086; RV32ZVE32F-NEXT:    andi a0, t0, -1285087; RV32ZVE32F-NEXT:    beqz a0, .LBB49_95088; RV32ZVE32F-NEXT:  .LBB49_8: # %cond.store135089; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma5090; RV32ZVE32F-NEXT:    vslidedown.vi v8, v8, 75091; RV32ZVE32F-NEXT:    vmv.x.s a0, v85092; RV32ZVE32F-NEXT:    sw a2, 0(a0)5093; RV32ZVE32F-NEXT:    sw a3, 4(a0)5094; RV32ZVE32F-NEXT:  .LBB49_9: # %else145095; RV32ZVE32F-NEXT:    lw s0, 12(sp) # 4-byte Folded Reload5096; RV32ZVE32F-NEXT:    lw s1, 8(sp) # 4-byte Folded Reload5097; RV32ZVE32F-NEXT:    lw s2, 4(sp) # 4-byte Folded Reload5098; RV32ZVE32F-NEXT:    .cfi_restore s05099; RV32ZVE32F-NEXT:    .cfi_restore s15100; RV32ZVE32F-NEXT:    .cfi_restore s25101; RV32ZVE32F-NEXT:    addi sp, sp, 165102; RV32ZVE32F-NEXT:    .cfi_def_cfa_offset 05103; RV32ZVE32F-NEXT:    ret5104; RV32ZVE32F-NEXT:  .LBB49_10: # %cond.store5105; RV32ZVE32F-NEXT:    .cfi_restore_state5106; RV32ZVE32F-NEXT:    lw a1, 0(a0)5107; RV32ZVE32F-NEXT:    lw a0, 4(a0)5108; RV32ZVE32F-NEXT:    vmv.x.s s2, v85109; RV32ZVE32F-NEXT:    sw a1, 0(s2)5110; RV32ZVE32F-NEXT:    sw a0, 4(s2)5111; RV32ZVE32F-NEXT:    andi a0, t0, 25112; RV32ZVE32F-NEXT:    beqz a0, .LBB49_25113; RV32ZVE32F-NEXT:  .LBB49_11: # %cond.store15114; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma5115; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 15116; RV32ZVE32F-NEXT:    vmv.x.s a0, v105117; RV32ZVE32F-NEXT:    sw s0, 0(a0)5118; RV32ZVE32F-NEXT:    sw s1, 4(a0)5119; RV32ZVE32F-NEXT:    andi a0, t0, 45120; RV32ZVE32F-NEXT:    beqz a0, .LBB49_35121; RV32ZVE32F-NEXT:  .LBB49_12: # %cond.store35122; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma5123; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 25124; RV32ZVE32F-NEXT:    vmv.x.s a0, v105125; RV32ZVE32F-NEXT:    sw t5, 0(a0)5126; RV32ZVE32F-NEXT:    sw t6, 4(a0)5127; RV32ZVE32F-NEXT:    andi a0, t0, 85128; RV32ZVE32F-NEXT:    beqz a0, .LBB49_45129; RV32ZVE32F-NEXT:  .LBB49_13: # %cond.store55130; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma5131; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 35132; RV32ZVE32F-NEXT:    vmv.x.s a0, v105133; RV32ZVE32F-NEXT:    sw t3, 0(a0)5134; RV32ZVE32F-NEXT:    sw t4, 4(a0)5135; RV32ZVE32F-NEXT:    andi a0, t0, 165136; RV32ZVE32F-NEXT:    beqz a0, .LBB49_55137; RV32ZVE32F-NEXT:  .LBB49_14: # %cond.store75138; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma5139; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 45140; RV32ZVE32F-NEXT:    vmv.x.s a0, v105141; RV32ZVE32F-NEXT:    sw t1, 0(a0)5142; RV32ZVE32F-NEXT:    sw t2, 4(a0)5143; RV32ZVE32F-NEXT:    andi a0, t0, 325144; RV32ZVE32F-NEXT:    beqz a0, .LBB49_65145; RV32ZVE32F-NEXT:  .LBB49_15: # %cond.store95146; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma5147; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 55148; RV32ZVE32F-NEXT:    vmv.x.s a0, v105149; RV32ZVE32F-NEXT:    sw a6, 0(a0)5150; RV32ZVE32F-NEXT:    sw a7, 4(a0)5151; RV32ZVE32F-NEXT:    andi a0, t0, 645152; RV32ZVE32F-NEXT:    beqz a0, .LBB49_75153; RV32ZVE32F-NEXT:  .LBB49_16: # %cond.store115154; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma5155; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 65156; RV32ZVE32F-NEXT:    vmv.x.s a0, v105157; RV32ZVE32F-NEXT:    sw a4, 0(a0)5158; RV32ZVE32F-NEXT:    sw a5, 4(a0)5159; RV32ZVE32F-NEXT:    andi a0, t0, -1285160; RV32ZVE32F-NEXT:    bnez a0, .LBB49_85161; RV32ZVE32F-NEXT:    j .LBB49_95162;5163; RV64ZVE32F-LABEL: mscatter_baseidx_sext_v8i32_v8i64:5164; RV64ZVE32F:       # %bb.0:5165; RV64ZVE32F-NEXT:    ld a5, 40(a0)5166; RV64ZVE32F-NEXT:    ld a3, 48(a0)5167; RV64ZVE32F-NEXT:    ld a2, 56(a0)5168; RV64ZVE32F-NEXT:    ld t1, 8(a0)5169; RV64ZVE32F-NEXT:    ld t0, 16(a0)5170; RV64ZVE32F-NEXT:    ld a7, 24(a0)5171; RV64ZVE32F-NEXT:    ld a6, 32(a0)5172; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma5173; RV64ZVE32F-NEXT:    vmv.x.s a4, v05174; RV64ZVE32F-NEXT:    andi t2, a4, 15175; RV64ZVE32F-NEXT:    beqz t2, .LBB49_25176; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store5177; RV64ZVE32F-NEXT:    ld a0, 0(a0)5178; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m4, ta, ma5179; RV64ZVE32F-NEXT:    vmv.x.s t2, v85180; RV64ZVE32F-NEXT:    slli t2, t2, 35181; RV64ZVE32F-NEXT:    add t2, a1, t25182; RV64ZVE32F-NEXT:    sd a0, 0(t2)5183; RV64ZVE32F-NEXT:  .LBB49_2: # %else5184; RV64ZVE32F-NEXT:    andi a0, a4, 25185; RV64ZVE32F-NEXT:    beqz a0, .LBB49_45186; RV64ZVE32F-NEXT:  # %bb.3: # %cond.store15187; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma5188; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 15189; RV64ZVE32F-NEXT:    vmv.x.s a0, v105190; RV64ZVE32F-NEXT:    slli a0, a0, 35191; RV64ZVE32F-NEXT:    add a0, a1, a05192; RV64ZVE32F-NEXT:    sd t1, 0(a0)5193; RV64ZVE32F-NEXT:  .LBB49_4: # %else25194; RV64ZVE32F-NEXT:    andi a0, a4, 45195; RV64ZVE32F-NEXT:    vsetivli zero, 2, e32, m1, ta, ma5196; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 25197; RV64ZVE32F-NEXT:    beqz a0, .LBB49_65198; RV64ZVE32F-NEXT:  # %bb.5: # %cond.store35199; RV64ZVE32F-NEXT:    vmv.x.s a0, v105200; RV64ZVE32F-NEXT:    slli a0, a0, 35201; RV64ZVE32F-NEXT:    add a0, a1, a05202; RV64ZVE32F-NEXT:    sd t0, 0(a0)5203; RV64ZVE32F-NEXT:  .LBB49_6: # %else45204; RV64ZVE32F-NEXT:    andi a0, a4, 85205; RV64ZVE32F-NEXT:    vsetivli zero, 4, e32, m2, ta, ma5206; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 45207; RV64ZVE32F-NEXT:    bnez a0, .LBB49_135208; RV64ZVE32F-NEXT:  # %bb.7: # %else65209; RV64ZVE32F-NEXT:    andi a0, a4, 165210; RV64ZVE32F-NEXT:    bnez a0, .LBB49_145211; RV64ZVE32F-NEXT:  .LBB49_8: # %else85212; RV64ZVE32F-NEXT:    andi a0, a4, 325213; RV64ZVE32F-NEXT:    beqz a0, .LBB49_105214; RV64ZVE32F-NEXT:  .LBB49_9: # %cond.store95215; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma5216; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 15217; RV64ZVE32F-NEXT:    vmv.x.s a0, v95218; RV64ZVE32F-NEXT:    slli a0, a0, 35219; RV64ZVE32F-NEXT:    add a0, a1, a05220; RV64ZVE32F-NEXT:    sd a5, 0(a0)5221; RV64ZVE32F-NEXT:  .LBB49_10: # %else105222; RV64ZVE32F-NEXT:    andi a0, a4, 645223; RV64ZVE32F-NEXT:    vsetivli zero, 2, e32, m1, ta, ma5224; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 25225; RV64ZVE32F-NEXT:    bnez a0, .LBB49_155226; RV64ZVE32F-NEXT:  # %bb.11: # %else125227; RV64ZVE32F-NEXT:    andi a0, a4, -1285228; RV64ZVE32F-NEXT:    bnez a0, .LBB49_165229; RV64ZVE32F-NEXT:  .LBB49_12: # %else145230; RV64ZVE32F-NEXT:    ret5231; RV64ZVE32F-NEXT:  .LBB49_13: # %cond.store55232; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma5233; RV64ZVE32F-NEXT:    vslidedown.vi v9, v10, 15234; RV64ZVE32F-NEXT:    vmv.x.s a0, v95235; RV64ZVE32F-NEXT:    slli a0, a0, 35236; RV64ZVE32F-NEXT:    add a0, a1, a05237; RV64ZVE32F-NEXT:    sd a7, 0(a0)5238; RV64ZVE32F-NEXT:    andi a0, a4, 165239; RV64ZVE32F-NEXT:    beqz a0, .LBB49_85240; RV64ZVE32F-NEXT:  .LBB49_14: # %cond.store75241; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma5242; RV64ZVE32F-NEXT:    vmv.x.s a0, v85243; RV64ZVE32F-NEXT:    slli a0, a0, 35244; RV64ZVE32F-NEXT:    add a0, a1, a05245; RV64ZVE32F-NEXT:    sd a6, 0(a0)5246; RV64ZVE32F-NEXT:    andi a0, a4, 325247; RV64ZVE32F-NEXT:    bnez a0, .LBB49_95248; RV64ZVE32F-NEXT:    j .LBB49_105249; RV64ZVE32F-NEXT:  .LBB49_15: # %cond.store115250; RV64ZVE32F-NEXT:    vmv.x.s a0, v85251; RV64ZVE32F-NEXT:    slli a0, a0, 35252; RV64ZVE32F-NEXT:    add a0, a1, a05253; RV64ZVE32F-NEXT:    sd a3, 0(a0)5254; RV64ZVE32F-NEXT:    andi a0, a4, -1285255; RV64ZVE32F-NEXT:    beqz a0, .LBB49_125256; RV64ZVE32F-NEXT:  .LBB49_16: # %cond.store135257; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 15258; RV64ZVE32F-NEXT:    vmv.x.s a0, v85259; RV64ZVE32F-NEXT:    slli a0, a0, 35260; RV64ZVE32F-NEXT:    add a0, a1, a05261; RV64ZVE32F-NEXT:    sd a2, 0(a0)5262; RV64ZVE32F-NEXT:    ret5263  %eidxs = sext <8 x i32> %idxs to <8 x i64>5264  %ptrs = getelementptr inbounds i64, ptr %base, <8 x i64> %eidxs5265  call void @llvm.masked.scatter.v8i64.v8p0(<8 x i64> %val, <8 x ptr> %ptrs, i32 8, <8 x i1> %m)5266  ret void5267}5268 5269define void @mscatter_baseidx_zext_v8i32_v8i64(<8 x i64> %val, ptr %base, <8 x i32> %idxs, <8 x i1> %m) {5270; RV32V-LABEL: mscatter_baseidx_zext_v8i32_v8i64:5271; RV32V:       # %bb.0:5272; RV32V-NEXT:    vsetivli zero, 8, e32, m2, ta, ma5273; RV32V-NEXT:    vsll.vi v12, v12, 35274; RV32V-NEXT:    vsetvli zero, zero, e64, m4, ta, ma5275; RV32V-NEXT:    vsoxei32.v v8, (a0), v12, v0.t5276; RV32V-NEXT:    ret5277;5278; RV64V-LABEL: mscatter_baseidx_zext_v8i32_v8i64:5279; RV64V:       # %bb.0:5280; RV64V-NEXT:    li a1, 85281; RV64V-NEXT:    vsetivli zero, 8, e32, m2, ta, ma5282; RV64V-NEXT:    vwmulu.vx v16, v12, a15283; RV64V-NEXT:    vsetvli zero, zero, e64, m4, ta, ma5284; RV64V-NEXT:    vsoxei64.v v8, (a0), v16, v0.t5285; RV64V-NEXT:    ret5286;5287; RV32ZVE32F-LABEL: mscatter_baseidx_zext_v8i32_v8i64:5288; RV32ZVE32F:       # %bb.0:5289; RV32ZVE32F-NEXT:    addi sp, sp, -165290; RV32ZVE32F-NEXT:    .cfi_def_cfa_offset 165291; RV32ZVE32F-NEXT:    sw s0, 12(sp) # 4-byte Folded Spill5292; RV32ZVE32F-NEXT:    sw s1, 8(sp) # 4-byte Folded Spill5293; RV32ZVE32F-NEXT:    sw s2, 4(sp) # 4-byte Folded Spill5294; RV32ZVE32F-NEXT:    .cfi_offset s0, -45295; RV32ZVE32F-NEXT:    .cfi_offset s1, -85296; RV32ZVE32F-NEXT:    .cfi_offset s2, -125297; RV32ZVE32F-NEXT:    .cfi_remember_state5298; RV32ZVE32F-NEXT:    lw a2, 56(a0)5299; RV32ZVE32F-NEXT:    lw a3, 60(a0)5300; RV32ZVE32F-NEXT:    lw a6, 40(a0)5301; RV32ZVE32F-NEXT:    lw a7, 44(a0)5302; RV32ZVE32F-NEXT:    lw a4, 48(a0)5303; RV32ZVE32F-NEXT:    lw a5, 52(a0)5304; RV32ZVE32F-NEXT:    lw t3, 24(a0)5305; RV32ZVE32F-NEXT:    lw t4, 28(a0)5306; RV32ZVE32F-NEXT:    lw t1, 32(a0)5307; RV32ZVE32F-NEXT:    lw t2, 36(a0)5308; RV32ZVE32F-NEXT:    lw s0, 8(a0)5309; RV32ZVE32F-NEXT:    lw s1, 12(a0)5310; RV32ZVE32F-NEXT:    lw t5, 16(a0)5311; RV32ZVE32F-NEXT:    lw t6, 20(a0)5312; RV32ZVE32F-NEXT:    vsetivli zero, 8, e32, m2, ta, ma5313; RV32ZVE32F-NEXT:    vsll.vi v8, v8, 35314; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma5315; RV32ZVE32F-NEXT:    vmv.x.s t0, v05316; RV32ZVE32F-NEXT:    andi s2, t0, 15317; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma5318; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a15319; RV32ZVE32F-NEXT:    bnez s2, .LBB50_105320; RV32ZVE32F-NEXT:  # %bb.1: # %else5321; RV32ZVE32F-NEXT:    andi a0, t0, 25322; RV32ZVE32F-NEXT:    bnez a0, .LBB50_115323; RV32ZVE32F-NEXT:  .LBB50_2: # %else25324; RV32ZVE32F-NEXT:    andi a0, t0, 45325; RV32ZVE32F-NEXT:    bnez a0, .LBB50_125326; RV32ZVE32F-NEXT:  .LBB50_3: # %else45327; RV32ZVE32F-NEXT:    andi a0, t0, 85328; RV32ZVE32F-NEXT:    bnez a0, .LBB50_135329; RV32ZVE32F-NEXT:  .LBB50_4: # %else65330; RV32ZVE32F-NEXT:    andi a0, t0, 165331; RV32ZVE32F-NEXT:    bnez a0, .LBB50_145332; RV32ZVE32F-NEXT:  .LBB50_5: # %else85333; RV32ZVE32F-NEXT:    andi a0, t0, 325334; RV32ZVE32F-NEXT:    bnez a0, .LBB50_155335; RV32ZVE32F-NEXT:  .LBB50_6: # %else105336; RV32ZVE32F-NEXT:    andi a0, t0, 645337; RV32ZVE32F-NEXT:    bnez a0, .LBB50_165338; RV32ZVE32F-NEXT:  .LBB50_7: # %else125339; RV32ZVE32F-NEXT:    andi a0, t0, -1285340; RV32ZVE32F-NEXT:    beqz a0, .LBB50_95341; RV32ZVE32F-NEXT:  .LBB50_8: # %cond.store135342; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma5343; RV32ZVE32F-NEXT:    vslidedown.vi v8, v8, 75344; RV32ZVE32F-NEXT:    vmv.x.s a0, v85345; RV32ZVE32F-NEXT:    sw a2, 0(a0)5346; RV32ZVE32F-NEXT:    sw a3, 4(a0)5347; RV32ZVE32F-NEXT:  .LBB50_9: # %else145348; RV32ZVE32F-NEXT:    lw s0, 12(sp) # 4-byte Folded Reload5349; RV32ZVE32F-NEXT:    lw s1, 8(sp) # 4-byte Folded Reload5350; RV32ZVE32F-NEXT:    lw s2, 4(sp) # 4-byte Folded Reload5351; RV32ZVE32F-NEXT:    .cfi_restore s05352; RV32ZVE32F-NEXT:    .cfi_restore s15353; RV32ZVE32F-NEXT:    .cfi_restore s25354; RV32ZVE32F-NEXT:    addi sp, sp, 165355; RV32ZVE32F-NEXT:    .cfi_def_cfa_offset 05356; RV32ZVE32F-NEXT:    ret5357; RV32ZVE32F-NEXT:  .LBB50_10: # %cond.store5358; RV32ZVE32F-NEXT:    .cfi_restore_state5359; RV32ZVE32F-NEXT:    lw a1, 0(a0)5360; RV32ZVE32F-NEXT:    lw a0, 4(a0)5361; RV32ZVE32F-NEXT:    vmv.x.s s2, v85362; RV32ZVE32F-NEXT:    sw a1, 0(s2)5363; RV32ZVE32F-NEXT:    sw a0, 4(s2)5364; RV32ZVE32F-NEXT:    andi a0, t0, 25365; RV32ZVE32F-NEXT:    beqz a0, .LBB50_25366; RV32ZVE32F-NEXT:  .LBB50_11: # %cond.store15367; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma5368; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 15369; RV32ZVE32F-NEXT:    vmv.x.s a0, v105370; RV32ZVE32F-NEXT:    sw s0, 0(a0)5371; RV32ZVE32F-NEXT:    sw s1, 4(a0)5372; RV32ZVE32F-NEXT:    andi a0, t0, 45373; RV32ZVE32F-NEXT:    beqz a0, .LBB50_35374; RV32ZVE32F-NEXT:  .LBB50_12: # %cond.store35375; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma5376; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 25377; RV32ZVE32F-NEXT:    vmv.x.s a0, v105378; RV32ZVE32F-NEXT:    sw t5, 0(a0)5379; RV32ZVE32F-NEXT:    sw t6, 4(a0)5380; RV32ZVE32F-NEXT:    andi a0, t0, 85381; RV32ZVE32F-NEXT:    beqz a0, .LBB50_45382; RV32ZVE32F-NEXT:  .LBB50_13: # %cond.store55383; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma5384; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 35385; RV32ZVE32F-NEXT:    vmv.x.s a0, v105386; RV32ZVE32F-NEXT:    sw t3, 0(a0)5387; RV32ZVE32F-NEXT:    sw t4, 4(a0)5388; RV32ZVE32F-NEXT:    andi a0, t0, 165389; RV32ZVE32F-NEXT:    beqz a0, .LBB50_55390; RV32ZVE32F-NEXT:  .LBB50_14: # %cond.store75391; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma5392; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 45393; RV32ZVE32F-NEXT:    vmv.x.s a0, v105394; RV32ZVE32F-NEXT:    sw t1, 0(a0)5395; RV32ZVE32F-NEXT:    sw t2, 4(a0)5396; RV32ZVE32F-NEXT:    andi a0, t0, 325397; RV32ZVE32F-NEXT:    beqz a0, .LBB50_65398; RV32ZVE32F-NEXT:  .LBB50_15: # %cond.store95399; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma5400; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 55401; RV32ZVE32F-NEXT:    vmv.x.s a0, v105402; RV32ZVE32F-NEXT:    sw a6, 0(a0)5403; RV32ZVE32F-NEXT:    sw a7, 4(a0)5404; RV32ZVE32F-NEXT:    andi a0, t0, 645405; RV32ZVE32F-NEXT:    beqz a0, .LBB50_75406; RV32ZVE32F-NEXT:  .LBB50_16: # %cond.store115407; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma5408; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 65409; RV32ZVE32F-NEXT:    vmv.x.s a0, v105410; RV32ZVE32F-NEXT:    sw a4, 0(a0)5411; RV32ZVE32F-NEXT:    sw a5, 4(a0)5412; RV32ZVE32F-NEXT:    andi a0, t0, -1285413; RV32ZVE32F-NEXT:    bnez a0, .LBB50_85414; RV32ZVE32F-NEXT:    j .LBB50_95415;5416; RV64ZVE32F-LABEL: mscatter_baseidx_zext_v8i32_v8i64:5417; RV64ZVE32F:       # %bb.0:5418; RV64ZVE32F-NEXT:    ld a5, 40(a0)5419; RV64ZVE32F-NEXT:    ld a3, 48(a0)5420; RV64ZVE32F-NEXT:    ld a2, 56(a0)5421; RV64ZVE32F-NEXT:    ld t1, 8(a0)5422; RV64ZVE32F-NEXT:    ld t0, 16(a0)5423; RV64ZVE32F-NEXT:    ld a7, 24(a0)5424; RV64ZVE32F-NEXT:    ld a6, 32(a0)5425; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma5426; RV64ZVE32F-NEXT:    vmv.x.s a4, v05427; RV64ZVE32F-NEXT:    andi t2, a4, 15428; RV64ZVE32F-NEXT:    beqz t2, .LBB50_25429; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store5430; RV64ZVE32F-NEXT:    ld a0, 0(a0)5431; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m4, ta, ma5432; RV64ZVE32F-NEXT:    vmv.x.s t2, v85433; RV64ZVE32F-NEXT:    slli t2, t2, 325434; RV64ZVE32F-NEXT:    srli t2, t2, 295435; RV64ZVE32F-NEXT:    add t2, a1, t25436; RV64ZVE32F-NEXT:    sd a0, 0(t2)5437; RV64ZVE32F-NEXT:  .LBB50_2: # %else5438; RV64ZVE32F-NEXT:    andi a0, a4, 25439; RV64ZVE32F-NEXT:    beqz a0, .LBB50_45440; RV64ZVE32F-NEXT:  # %bb.3: # %cond.store15441; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma5442; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 15443; RV64ZVE32F-NEXT:    vmv.x.s a0, v105444; RV64ZVE32F-NEXT:    slli a0, a0, 325445; RV64ZVE32F-NEXT:    srli a0, a0, 295446; RV64ZVE32F-NEXT:    add a0, a1, a05447; RV64ZVE32F-NEXT:    sd t1, 0(a0)5448; RV64ZVE32F-NEXT:  .LBB50_4: # %else25449; RV64ZVE32F-NEXT:    andi a0, a4, 45450; RV64ZVE32F-NEXT:    vsetivli zero, 2, e32, m1, ta, ma5451; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 25452; RV64ZVE32F-NEXT:    beqz a0, .LBB50_65453; RV64ZVE32F-NEXT:  # %bb.5: # %cond.store35454; RV64ZVE32F-NEXT:    vmv.x.s a0, v105455; RV64ZVE32F-NEXT:    slli a0, a0, 325456; RV64ZVE32F-NEXT:    srli a0, a0, 295457; RV64ZVE32F-NEXT:    add a0, a1, a05458; RV64ZVE32F-NEXT:    sd t0, 0(a0)5459; RV64ZVE32F-NEXT:  .LBB50_6: # %else45460; RV64ZVE32F-NEXT:    andi a0, a4, 85461; RV64ZVE32F-NEXT:    vsetivli zero, 4, e32, m2, ta, ma5462; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 45463; RV64ZVE32F-NEXT:    bnez a0, .LBB50_135464; RV64ZVE32F-NEXT:  # %bb.7: # %else65465; RV64ZVE32F-NEXT:    andi a0, a4, 165466; RV64ZVE32F-NEXT:    bnez a0, .LBB50_145467; RV64ZVE32F-NEXT:  .LBB50_8: # %else85468; RV64ZVE32F-NEXT:    andi a0, a4, 325469; RV64ZVE32F-NEXT:    beqz a0, .LBB50_105470; RV64ZVE32F-NEXT:  .LBB50_9: # %cond.store95471; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma5472; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 15473; RV64ZVE32F-NEXT:    vmv.x.s a0, v95474; RV64ZVE32F-NEXT:    slli a0, a0, 325475; RV64ZVE32F-NEXT:    srli a0, a0, 295476; RV64ZVE32F-NEXT:    add a0, a1, a05477; RV64ZVE32F-NEXT:    sd a5, 0(a0)5478; RV64ZVE32F-NEXT:  .LBB50_10: # %else105479; RV64ZVE32F-NEXT:    andi a0, a4, 645480; RV64ZVE32F-NEXT:    vsetivli zero, 2, e32, m1, ta, ma5481; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 25482; RV64ZVE32F-NEXT:    bnez a0, .LBB50_155483; RV64ZVE32F-NEXT:  # %bb.11: # %else125484; RV64ZVE32F-NEXT:    andi a0, a4, -1285485; RV64ZVE32F-NEXT:    bnez a0, .LBB50_165486; RV64ZVE32F-NEXT:  .LBB50_12: # %else145487; RV64ZVE32F-NEXT:    ret5488; RV64ZVE32F-NEXT:  .LBB50_13: # %cond.store55489; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma5490; RV64ZVE32F-NEXT:    vslidedown.vi v9, v10, 15491; RV64ZVE32F-NEXT:    vmv.x.s a0, v95492; RV64ZVE32F-NEXT:    slli a0, a0, 325493; RV64ZVE32F-NEXT:    srli a0, a0, 295494; RV64ZVE32F-NEXT:    add a0, a1, a05495; RV64ZVE32F-NEXT:    sd a7, 0(a0)5496; RV64ZVE32F-NEXT:    andi a0, a4, 165497; RV64ZVE32F-NEXT:    beqz a0, .LBB50_85498; RV64ZVE32F-NEXT:  .LBB50_14: # %cond.store75499; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma5500; RV64ZVE32F-NEXT:    vmv.x.s a0, v85501; RV64ZVE32F-NEXT:    slli a0, a0, 325502; RV64ZVE32F-NEXT:    srli a0, a0, 295503; RV64ZVE32F-NEXT:    add a0, a1, a05504; RV64ZVE32F-NEXT:    sd a6, 0(a0)5505; RV64ZVE32F-NEXT:    andi a0, a4, 325506; RV64ZVE32F-NEXT:    bnez a0, .LBB50_95507; RV64ZVE32F-NEXT:    j .LBB50_105508; RV64ZVE32F-NEXT:  .LBB50_15: # %cond.store115509; RV64ZVE32F-NEXT:    vmv.x.s a0, v85510; RV64ZVE32F-NEXT:    slli a0, a0, 325511; RV64ZVE32F-NEXT:    srli a0, a0, 295512; RV64ZVE32F-NEXT:    add a0, a1, a05513; RV64ZVE32F-NEXT:    sd a3, 0(a0)5514; RV64ZVE32F-NEXT:    andi a0, a4, -1285515; RV64ZVE32F-NEXT:    beqz a0, .LBB50_125516; RV64ZVE32F-NEXT:  .LBB50_16: # %cond.store135517; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 15518; RV64ZVE32F-NEXT:    vmv.x.s a0, v85519; RV64ZVE32F-NEXT:    slli a0, a0, 325520; RV64ZVE32F-NEXT:    srli a0, a0, 295521; RV64ZVE32F-NEXT:    add a0, a1, a05522; RV64ZVE32F-NEXT:    sd a2, 0(a0)5523; RV64ZVE32F-NEXT:    ret5524  %eidxs = zext <8 x i32> %idxs to <8 x i64>5525  %ptrs = getelementptr inbounds i64, ptr %base, <8 x i64> %eidxs5526  call void @llvm.masked.scatter.v8i64.v8p0(<8 x i64> %val, <8 x ptr> %ptrs, i32 8, <8 x i1> %m)5527  ret void5528}5529 5530define void @mscatter_baseidx_v8i64(<8 x i64> %val, ptr %base, <8 x i64> %idxs, <8 x i1> %m) {5531; RV32V-LABEL: mscatter_baseidx_v8i64:5532; RV32V:       # %bb.0:5533; RV32V-NEXT:    vsetivli zero, 8, e32, m2, ta, ma5534; RV32V-NEXT:    vnsrl.wi v16, v12, 05535; RV32V-NEXT:    vsll.vi v12, v16, 35536; RV32V-NEXT:    vsetvli zero, zero, e64, m4, ta, ma5537; RV32V-NEXT:    vsoxei32.v v8, (a0), v12, v0.t5538; RV32V-NEXT:    ret5539;5540; RV64V-LABEL: mscatter_baseidx_v8i64:5541; RV64V:       # %bb.0:5542; RV64V-NEXT:    vsetivli zero, 8, e64, m4, ta, ma5543; RV64V-NEXT:    vsll.vi v12, v12, 35544; RV64V-NEXT:    vsoxei64.v v8, (a0), v12, v0.t5545; RV64V-NEXT:    ret5546;5547; RV32ZVE32F-LABEL: mscatter_baseidx_v8i64:5548; RV32ZVE32F:       # %bb.0:5549; RV32ZVE32F-NEXT:    addi sp, sp, -485550; RV32ZVE32F-NEXT:    .cfi_def_cfa_offset 485551; RV32ZVE32F-NEXT:    sw s0, 44(sp) # 4-byte Folded Spill5552; RV32ZVE32F-NEXT:    sw s1, 40(sp) # 4-byte Folded Spill5553; RV32ZVE32F-NEXT:    sw s2, 36(sp) # 4-byte Folded Spill5554; RV32ZVE32F-NEXT:    sw s3, 32(sp) # 4-byte Folded Spill5555; RV32ZVE32F-NEXT:    sw s4, 28(sp) # 4-byte Folded Spill5556; RV32ZVE32F-NEXT:    sw s5, 24(sp) # 4-byte Folded Spill5557; RV32ZVE32F-NEXT:    sw s6, 20(sp) # 4-byte Folded Spill5558; RV32ZVE32F-NEXT:    sw s7, 16(sp) # 4-byte Folded Spill5559; RV32ZVE32F-NEXT:    sw s8, 12(sp) # 4-byte Folded Spill5560; RV32ZVE32F-NEXT:    sw s9, 8(sp) # 4-byte Folded Spill5561; RV32ZVE32F-NEXT:    .cfi_offset s0, -45562; RV32ZVE32F-NEXT:    .cfi_offset s1, -85563; RV32ZVE32F-NEXT:    .cfi_offset s2, -125564; RV32ZVE32F-NEXT:    .cfi_offset s3, -165565; RV32ZVE32F-NEXT:    .cfi_offset s4, -205566; RV32ZVE32F-NEXT:    .cfi_offset s5, -245567; RV32ZVE32F-NEXT:    .cfi_offset s6, -285568; RV32ZVE32F-NEXT:    .cfi_offset s7, -325569; RV32ZVE32F-NEXT:    .cfi_offset s8, -365570; RV32ZVE32F-NEXT:    .cfi_offset s9, -405571; RV32ZVE32F-NEXT:    .cfi_remember_state5572; RV32ZVE32F-NEXT:    lw a3, 56(a0)5573; RV32ZVE32F-NEXT:    lw a4, 60(a0)5574; RV32ZVE32F-NEXT:    lw a7, 40(a0)5575; RV32ZVE32F-NEXT:    lw t0, 44(a0)5576; RV32ZVE32F-NEXT:    lw a5, 48(a0)5577; RV32ZVE32F-NEXT:    lw a6, 52(a0)5578; RV32ZVE32F-NEXT:    lw t3, 24(a0)5579; RV32ZVE32F-NEXT:    lw t4, 28(a0)5580; RV32ZVE32F-NEXT:    lw t1, 32(a0)5581; RV32ZVE32F-NEXT:    lw t2, 36(a0)5582; RV32ZVE32F-NEXT:    lw s0, 8(a0)5583; RV32ZVE32F-NEXT:    lw s1, 12(a0)5584; RV32ZVE32F-NEXT:    lw t5, 16(a0)5585; RV32ZVE32F-NEXT:    lw t6, 20(a0)5586; RV32ZVE32F-NEXT:    lw s2, 32(a2)5587; RV32ZVE32F-NEXT:    lw s3, 40(a2)5588; RV32ZVE32F-NEXT:    lw s4, 48(a2)5589; RV32ZVE32F-NEXT:    lw s5, 56(a2)5590; RV32ZVE32F-NEXT:    lw s6, 0(a2)5591; RV32ZVE32F-NEXT:    lw s7, 8(a2)5592; RV32ZVE32F-NEXT:    lw s8, 16(a2)5593; RV32ZVE32F-NEXT:    lw s9, 24(a2)5594; RV32ZVE32F-NEXT:    vsetivli zero, 8, e32, m2, ta, ma5595; RV32ZVE32F-NEXT:    vmv.v.x v8, s65596; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma5597; RV32ZVE32F-NEXT:    vmv.x.s a2, v05598; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma5599; RV32ZVE32F-NEXT:    vslide1down.vx v8, v8, s75600; RV32ZVE32F-NEXT:    vslide1down.vx v8, v8, s85601; RV32ZVE32F-NEXT:    vslide1down.vx v8, v8, s95602; RV32ZVE32F-NEXT:    vslide1down.vx v8, v8, s25603; RV32ZVE32F-NEXT:    vslide1down.vx v8, v8, s35604; RV32ZVE32F-NEXT:    vslide1down.vx v8, v8, s45605; RV32ZVE32F-NEXT:    vslide1down.vx v8, v8, s55606; RV32ZVE32F-NEXT:    vsll.vi v8, v8, 35607; RV32ZVE32F-NEXT:    andi s2, a2, 15608; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a15609; RV32ZVE32F-NEXT:    bnez s2, .LBB51_105610; RV32ZVE32F-NEXT:  # %bb.1: # %else5611; RV32ZVE32F-NEXT:    andi a0, a2, 25612; RV32ZVE32F-NEXT:    bnez a0, .LBB51_115613; RV32ZVE32F-NEXT:  .LBB51_2: # %else25614; RV32ZVE32F-NEXT:    andi a0, a2, 45615; RV32ZVE32F-NEXT:    bnez a0, .LBB51_125616; RV32ZVE32F-NEXT:  .LBB51_3: # %else45617; RV32ZVE32F-NEXT:    andi a0, a2, 85618; RV32ZVE32F-NEXT:    bnez a0, .LBB51_135619; RV32ZVE32F-NEXT:  .LBB51_4: # %else65620; RV32ZVE32F-NEXT:    andi a0, a2, 165621; RV32ZVE32F-NEXT:    bnez a0, .LBB51_145622; RV32ZVE32F-NEXT:  .LBB51_5: # %else85623; RV32ZVE32F-NEXT:    andi a0, a2, 325624; RV32ZVE32F-NEXT:    bnez a0, .LBB51_155625; RV32ZVE32F-NEXT:  .LBB51_6: # %else105626; RV32ZVE32F-NEXT:    andi a0, a2, 645627; RV32ZVE32F-NEXT:    bnez a0, .LBB51_165628; RV32ZVE32F-NEXT:  .LBB51_7: # %else125629; RV32ZVE32F-NEXT:    andi a0, a2, -1285630; RV32ZVE32F-NEXT:    beqz a0, .LBB51_95631; RV32ZVE32F-NEXT:  .LBB51_8: # %cond.store135632; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma5633; RV32ZVE32F-NEXT:    vslidedown.vi v8, v8, 75634; RV32ZVE32F-NEXT:    vmv.x.s a0, v85635; RV32ZVE32F-NEXT:    sw a3, 0(a0)5636; RV32ZVE32F-NEXT:    sw a4, 4(a0)5637; RV32ZVE32F-NEXT:  .LBB51_9: # %else145638; RV32ZVE32F-NEXT:    lw s0, 44(sp) # 4-byte Folded Reload5639; RV32ZVE32F-NEXT:    lw s1, 40(sp) # 4-byte Folded Reload5640; RV32ZVE32F-NEXT:    lw s2, 36(sp) # 4-byte Folded Reload5641; RV32ZVE32F-NEXT:    lw s3, 32(sp) # 4-byte Folded Reload5642; RV32ZVE32F-NEXT:    lw s4, 28(sp) # 4-byte Folded Reload5643; RV32ZVE32F-NEXT:    lw s5, 24(sp) # 4-byte Folded Reload5644; RV32ZVE32F-NEXT:    lw s6, 20(sp) # 4-byte Folded Reload5645; RV32ZVE32F-NEXT:    lw s7, 16(sp) # 4-byte Folded Reload5646; RV32ZVE32F-NEXT:    lw s8, 12(sp) # 4-byte Folded Reload5647; RV32ZVE32F-NEXT:    lw s9, 8(sp) # 4-byte Folded Reload5648; RV32ZVE32F-NEXT:    .cfi_restore s05649; RV32ZVE32F-NEXT:    .cfi_restore s15650; RV32ZVE32F-NEXT:    .cfi_restore s25651; RV32ZVE32F-NEXT:    .cfi_restore s35652; RV32ZVE32F-NEXT:    .cfi_restore s45653; RV32ZVE32F-NEXT:    .cfi_restore s55654; RV32ZVE32F-NEXT:    .cfi_restore s65655; RV32ZVE32F-NEXT:    .cfi_restore s75656; RV32ZVE32F-NEXT:    .cfi_restore s85657; RV32ZVE32F-NEXT:    .cfi_restore s95658; RV32ZVE32F-NEXT:    addi sp, sp, 485659; RV32ZVE32F-NEXT:    .cfi_def_cfa_offset 05660; RV32ZVE32F-NEXT:    ret5661; RV32ZVE32F-NEXT:  .LBB51_10: # %cond.store5662; RV32ZVE32F-NEXT:    .cfi_restore_state5663; RV32ZVE32F-NEXT:    lw a1, 0(a0)5664; RV32ZVE32F-NEXT:    lw a0, 4(a0)5665; RV32ZVE32F-NEXT:    vmv.x.s s2, v85666; RV32ZVE32F-NEXT:    sw a1, 0(s2)5667; RV32ZVE32F-NEXT:    sw a0, 4(s2)5668; RV32ZVE32F-NEXT:    andi a0, a2, 25669; RV32ZVE32F-NEXT:    beqz a0, .LBB51_25670; RV32ZVE32F-NEXT:  .LBB51_11: # %cond.store15671; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma5672; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 15673; RV32ZVE32F-NEXT:    vmv.x.s a0, v105674; RV32ZVE32F-NEXT:    sw s0, 0(a0)5675; RV32ZVE32F-NEXT:    sw s1, 4(a0)5676; RV32ZVE32F-NEXT:    andi a0, a2, 45677; RV32ZVE32F-NEXT:    beqz a0, .LBB51_35678; RV32ZVE32F-NEXT:  .LBB51_12: # %cond.store35679; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma5680; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 25681; RV32ZVE32F-NEXT:    vmv.x.s a0, v105682; RV32ZVE32F-NEXT:    sw t5, 0(a0)5683; RV32ZVE32F-NEXT:    sw t6, 4(a0)5684; RV32ZVE32F-NEXT:    andi a0, a2, 85685; RV32ZVE32F-NEXT:    beqz a0, .LBB51_45686; RV32ZVE32F-NEXT:  .LBB51_13: # %cond.store55687; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma5688; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 35689; RV32ZVE32F-NEXT:    vmv.x.s a0, v105690; RV32ZVE32F-NEXT:    sw t3, 0(a0)5691; RV32ZVE32F-NEXT:    sw t4, 4(a0)5692; RV32ZVE32F-NEXT:    andi a0, a2, 165693; RV32ZVE32F-NEXT:    beqz a0, .LBB51_55694; RV32ZVE32F-NEXT:  .LBB51_14: # %cond.store75695; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma5696; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 45697; RV32ZVE32F-NEXT:    vmv.x.s a0, v105698; RV32ZVE32F-NEXT:    sw t1, 0(a0)5699; RV32ZVE32F-NEXT:    sw t2, 4(a0)5700; RV32ZVE32F-NEXT:    andi a0, a2, 325701; RV32ZVE32F-NEXT:    beqz a0, .LBB51_65702; RV32ZVE32F-NEXT:  .LBB51_15: # %cond.store95703; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma5704; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 55705; RV32ZVE32F-NEXT:    vmv.x.s a0, v105706; RV32ZVE32F-NEXT:    sw a7, 0(a0)5707; RV32ZVE32F-NEXT:    sw t0, 4(a0)5708; RV32ZVE32F-NEXT:    andi a0, a2, 645709; RV32ZVE32F-NEXT:    beqz a0, .LBB51_75710; RV32ZVE32F-NEXT:  .LBB51_16: # %cond.store115711; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma5712; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 65713; RV32ZVE32F-NEXT:    vmv.x.s a0, v105714; RV32ZVE32F-NEXT:    sw a5, 0(a0)5715; RV32ZVE32F-NEXT:    sw a6, 4(a0)5716; RV32ZVE32F-NEXT:    andi a0, a2, -1285717; RV32ZVE32F-NEXT:    bnez a0, .LBB51_85718; RV32ZVE32F-NEXT:    j .LBB51_95719;5720; RV64ZVE32F-LABEL: mscatter_baseidx_v8i64:5721; RV64ZVE32F:       # %bb.0:5722; RV64ZVE32F-NEXT:    addi sp, sp, -325723; RV64ZVE32F-NEXT:    .cfi_def_cfa_offset 325724; RV64ZVE32F-NEXT:    sd s0, 24(sp) # 8-byte Folded Spill5725; RV64ZVE32F-NEXT:    sd s1, 16(sp) # 8-byte Folded Spill5726; RV64ZVE32F-NEXT:    sd s2, 8(sp) # 8-byte Folded Spill5727; RV64ZVE32F-NEXT:    sd s3, 0(sp) # 8-byte Folded Spill5728; RV64ZVE32F-NEXT:    .cfi_offset s0, -85729; RV64ZVE32F-NEXT:    .cfi_offset s1, -165730; RV64ZVE32F-NEXT:    .cfi_offset s2, -245731; RV64ZVE32F-NEXT:    .cfi_offset s3, -325732; RV64ZVE32F-NEXT:    .cfi_remember_state5733; RV64ZVE32F-NEXT:    ld a5, 40(a0)5734; RV64ZVE32F-NEXT:    ld a4, 48(a0)5735; RV64ZVE32F-NEXT:    ld a3, 56(a0)5736; RV64ZVE32F-NEXT:    ld s0, 8(a0)5737; RV64ZVE32F-NEXT:    ld t5, 16(a0)5738; RV64ZVE32F-NEXT:    ld t3, 24(a0)5739; RV64ZVE32F-NEXT:    ld t1, 32(a0)5740; RV64ZVE32F-NEXT:    ld s2, 8(a2)5741; RV64ZVE32F-NEXT:    ld s1, 16(a2)5742; RV64ZVE32F-NEXT:    ld t6, 24(a2)5743; RV64ZVE32F-NEXT:    ld t4, 32(a2)5744; RV64ZVE32F-NEXT:    ld t2, 40(a2)5745; RV64ZVE32F-NEXT:    ld t0, 48(a2)5746; RV64ZVE32F-NEXT:    ld a6, 56(a2)5747; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma5748; RV64ZVE32F-NEXT:    vmv.x.s a7, v05749; RV64ZVE32F-NEXT:    andi s3, a7, 15750; RV64ZVE32F-NEXT:    bnez s3, .LBB51_105751; RV64ZVE32F-NEXT:  # %bb.1: # %else5752; RV64ZVE32F-NEXT:    andi a0, a7, 25753; RV64ZVE32F-NEXT:    bnez a0, .LBB51_115754; RV64ZVE32F-NEXT:  .LBB51_2: # %else25755; RV64ZVE32F-NEXT:    andi a0, a7, 45756; RV64ZVE32F-NEXT:    bnez a0, .LBB51_125757; RV64ZVE32F-NEXT:  .LBB51_3: # %else45758; RV64ZVE32F-NEXT:    andi a0, a7, 85759; RV64ZVE32F-NEXT:    bnez a0, .LBB51_135760; RV64ZVE32F-NEXT:  .LBB51_4: # %else65761; RV64ZVE32F-NEXT:    andi a0, a7, 165762; RV64ZVE32F-NEXT:    bnez a0, .LBB51_145763; RV64ZVE32F-NEXT:  .LBB51_5: # %else85764; RV64ZVE32F-NEXT:    andi a0, a7, 325765; RV64ZVE32F-NEXT:    bnez a0, .LBB51_155766; RV64ZVE32F-NEXT:  .LBB51_6: # %else105767; RV64ZVE32F-NEXT:    andi a0, a7, 645768; RV64ZVE32F-NEXT:    bnez a0, .LBB51_165769; RV64ZVE32F-NEXT:  .LBB51_7: # %else125770; RV64ZVE32F-NEXT:    andi a0, a7, -1285771; RV64ZVE32F-NEXT:    beqz a0, .LBB51_95772; RV64ZVE32F-NEXT:  .LBB51_8: # %cond.store135773; RV64ZVE32F-NEXT:    slli a6, a6, 35774; RV64ZVE32F-NEXT:    add a1, a1, a65775; RV64ZVE32F-NEXT:    sd a3, 0(a1)5776; RV64ZVE32F-NEXT:  .LBB51_9: # %else145777; RV64ZVE32F-NEXT:    ld s0, 24(sp) # 8-byte Folded Reload5778; RV64ZVE32F-NEXT:    ld s1, 16(sp) # 8-byte Folded Reload5779; RV64ZVE32F-NEXT:    ld s2, 8(sp) # 8-byte Folded Reload5780; RV64ZVE32F-NEXT:    ld s3, 0(sp) # 8-byte Folded Reload5781; RV64ZVE32F-NEXT:    .cfi_restore s05782; RV64ZVE32F-NEXT:    .cfi_restore s15783; RV64ZVE32F-NEXT:    .cfi_restore s25784; RV64ZVE32F-NEXT:    .cfi_restore s35785; RV64ZVE32F-NEXT:    addi sp, sp, 325786; RV64ZVE32F-NEXT:    .cfi_def_cfa_offset 05787; RV64ZVE32F-NEXT:    ret5788; RV64ZVE32F-NEXT:  .LBB51_10: # %cond.store5789; RV64ZVE32F-NEXT:    .cfi_restore_state5790; RV64ZVE32F-NEXT:    ld a2, 0(a2)5791; RV64ZVE32F-NEXT:    ld a0, 0(a0)5792; RV64ZVE32F-NEXT:    slli a2, a2, 35793; RV64ZVE32F-NEXT:    add a2, a1, a25794; RV64ZVE32F-NEXT:    sd a0, 0(a2)5795; RV64ZVE32F-NEXT:    andi a0, a7, 25796; RV64ZVE32F-NEXT:    beqz a0, .LBB51_25797; RV64ZVE32F-NEXT:  .LBB51_11: # %cond.store15798; RV64ZVE32F-NEXT:    slli s2, s2, 35799; RV64ZVE32F-NEXT:    add s2, a1, s25800; RV64ZVE32F-NEXT:    sd s0, 0(s2)5801; RV64ZVE32F-NEXT:    andi a0, a7, 45802; RV64ZVE32F-NEXT:    beqz a0, .LBB51_35803; RV64ZVE32F-NEXT:  .LBB51_12: # %cond.store35804; RV64ZVE32F-NEXT:    slli s1, s1, 35805; RV64ZVE32F-NEXT:    add s1, a1, s15806; RV64ZVE32F-NEXT:    sd t5, 0(s1)5807; RV64ZVE32F-NEXT:    andi a0, a7, 85808; RV64ZVE32F-NEXT:    beqz a0, .LBB51_45809; RV64ZVE32F-NEXT:  .LBB51_13: # %cond.store55810; RV64ZVE32F-NEXT:    slli t6, t6, 35811; RV64ZVE32F-NEXT:    add t6, a1, t65812; RV64ZVE32F-NEXT:    sd t3, 0(t6)5813; RV64ZVE32F-NEXT:    andi a0, a7, 165814; RV64ZVE32F-NEXT:    beqz a0, .LBB51_55815; RV64ZVE32F-NEXT:  .LBB51_14: # %cond.store75816; RV64ZVE32F-NEXT:    slli t4, t4, 35817; RV64ZVE32F-NEXT:    add t4, a1, t45818; RV64ZVE32F-NEXT:    sd t1, 0(t4)5819; RV64ZVE32F-NEXT:    andi a0, a7, 325820; RV64ZVE32F-NEXT:    beqz a0, .LBB51_65821; RV64ZVE32F-NEXT:  .LBB51_15: # %cond.store95822; RV64ZVE32F-NEXT:    slli t2, t2, 35823; RV64ZVE32F-NEXT:    add t2, a1, t25824; RV64ZVE32F-NEXT:    sd a5, 0(t2)5825; RV64ZVE32F-NEXT:    andi a0, a7, 645826; RV64ZVE32F-NEXT:    beqz a0, .LBB51_75827; RV64ZVE32F-NEXT:  .LBB51_16: # %cond.store115828; RV64ZVE32F-NEXT:    slli t0, t0, 35829; RV64ZVE32F-NEXT:    add t0, a1, t05830; RV64ZVE32F-NEXT:    sd a4, 0(t0)5831; RV64ZVE32F-NEXT:    andi a0, a7, -1285832; RV64ZVE32F-NEXT:    bnez a0, .LBB51_85833; RV64ZVE32F-NEXT:    j .LBB51_95834  %ptrs = getelementptr inbounds i64, ptr %base, <8 x i64> %idxs5835  call void @llvm.masked.scatter.v8i64.v8p0(<8 x i64> %val, <8 x ptr> %ptrs, i32 8, <8 x i1> %m)5836  ret void5837}5838 5839define void @mscatter_v1bf16(<1 x bfloat> %val, <1 x ptr> %ptrs, <1 x i1> %m) {5840; RV32V-LABEL: mscatter_v1bf16:5841; RV32V:       # %bb.0:5842; RV32V-NEXT:    vsetivli zero, 1, e16, mf4, ta, ma5843; RV32V-NEXT:    vsoxei32.v v8, (zero), v9, v0.t5844; RV32V-NEXT:    ret5845;5846; RV64V-LABEL: mscatter_v1bf16:5847; RV64V:       # %bb.0:5848; RV64V-NEXT:    vsetivli zero, 1, e16, mf4, ta, ma5849; RV64V-NEXT:    vsoxei64.v v8, (zero), v9, v0.t5850; RV64V-NEXT:    ret5851;5852; RV32ZVE32F-LABEL: mscatter_v1bf16:5853; RV32ZVE32F:       # %bb.0:5854; RV32ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma5855; RV32ZVE32F-NEXT:    vsoxei32.v v8, (zero), v9, v0.t5856; RV32ZVE32F-NEXT:    ret5857;5858; RV64ZVE32F-LABEL: mscatter_v1bf16:5859; RV64ZVE32F:       # %bb.0:5860; RV64ZVE32F-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma5861; RV64ZVE32F-NEXT:    vfirst.m a1, v05862; RV64ZVE32F-NEXT:    bnez a1, .LBB52_25863; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store5864; RV64ZVE32F-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma5865; RV64ZVE32F-NEXT:    vmv.x.s a1, v85866; RV64ZVE32F-NEXT:    fmv.h.x fa5, a15867; RV64ZVE32F-NEXT:    fsh fa5, 0(a0)5868; RV64ZVE32F-NEXT:  .LBB52_2: # %else5869; RV64ZVE32F-NEXT:    ret5870  call void @llvm.masked.scatter.v1bf16.v1p0(<1 x bfloat> %val, <1 x ptr> %ptrs, i32 2, <1 x i1> %m)5871  ret void5872}5873 5874define void @mscatter_v2bf16(<2 x bfloat> %val, <2 x ptr> %ptrs, <2 x i1> %m) {5875; RV32V-LABEL: mscatter_v2bf16:5876; RV32V:       # %bb.0:5877; RV32V-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma5878; RV32V-NEXT:    vsoxei32.v v8, (zero), v9, v0.t5879; RV32V-NEXT:    ret5880;5881; RV64V-LABEL: mscatter_v2bf16:5882; RV64V:       # %bb.0:5883; RV64V-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma5884; RV64V-NEXT:    vsoxei64.v v8, (zero), v9, v0.t5885; RV64V-NEXT:    ret5886;5887; RV32ZVE32F-LABEL: mscatter_v2bf16:5888; RV32ZVE32F:       # %bb.0:5889; RV32ZVE32F-NEXT:    vsetivli zero, 2, e16, mf2, ta, ma5890; RV32ZVE32F-NEXT:    vsoxei32.v v8, (zero), v9, v0.t5891; RV32ZVE32F-NEXT:    ret5892;5893; RV64ZVE32F-LABEL: mscatter_v2bf16:5894; RV64ZVE32F:       # %bb.0:5895; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma5896; RV64ZVE32F-NEXT:    vmv.x.s a2, v05897; RV64ZVE32F-NEXT:    andi a3, a2, 15898; RV64ZVE32F-NEXT:    bnez a3, .LBB53_35899; RV64ZVE32F-NEXT:  # %bb.1: # %else5900; RV64ZVE32F-NEXT:    andi a2, a2, 25901; RV64ZVE32F-NEXT:    bnez a2, .LBB53_45902; RV64ZVE32F-NEXT:  .LBB53_2: # %else25903; RV64ZVE32F-NEXT:    ret5904; RV64ZVE32F-NEXT:  .LBB53_3: # %cond.store5905; RV64ZVE32F-NEXT:    vsetvli zero, zero, e16, m2, ta, ma5906; RV64ZVE32F-NEXT:    vmv.x.s a3, v85907; RV64ZVE32F-NEXT:    fmv.h.x fa5, a35908; RV64ZVE32F-NEXT:    fsh fa5, 0(a0)5909; RV64ZVE32F-NEXT:    andi a2, a2, 25910; RV64ZVE32F-NEXT:    beqz a2, .LBB53_25911; RV64ZVE32F-NEXT:  .LBB53_4: # %cond.store15912; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma5913; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 15914; RV64ZVE32F-NEXT:    vmv.x.s a0, v85915; RV64ZVE32F-NEXT:    fmv.h.x fa5, a05916; RV64ZVE32F-NEXT:    fsh fa5, 0(a1)5917; RV64ZVE32F-NEXT:    ret5918  call void @llvm.masked.scatter.v2bf16.v2p0(<2 x bfloat> %val, <2 x ptr> %ptrs, i32 2, <2 x i1> %m)5919  ret void5920}5921 5922define void @mscatter_v4bf16(<4 x bfloat> %val, <4 x ptr> %ptrs, <4 x i1> %m) {5923; RV32-LABEL: mscatter_v4bf16:5924; RV32:       # %bb.0:5925; RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma5926; RV32-NEXT:    vsoxei32.v v8, (zero), v9, v0.t5927; RV32-NEXT:    ret5928;5929; RV64V-LABEL: mscatter_v4bf16:5930; RV64V:       # %bb.0:5931; RV64V-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma5932; RV64V-NEXT:    vsoxei64.v v8, (zero), v10, v0.t5933; RV64V-NEXT:    ret5934;5935; RV64ZVE32F-LABEL: mscatter_v4bf16:5936; RV64ZVE32F:       # %bb.0:5937; RV64ZVE32F-NEXT:    ld a4, 8(a0)5938; RV64ZVE32F-NEXT:    ld a2, 16(a0)5939; RV64ZVE32F-NEXT:    ld a1, 24(a0)5940; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma5941; RV64ZVE32F-NEXT:    vmv.x.s a3, v05942; RV64ZVE32F-NEXT:    andi a5, a3, 15943; RV64ZVE32F-NEXT:    bnez a5, .LBB54_55944; RV64ZVE32F-NEXT:  # %bb.1: # %else5945; RV64ZVE32F-NEXT:    andi a0, a3, 25946; RV64ZVE32F-NEXT:    bnez a0, .LBB54_65947; RV64ZVE32F-NEXT:  .LBB54_2: # %else25948; RV64ZVE32F-NEXT:    andi a0, a3, 45949; RV64ZVE32F-NEXT:    bnez a0, .LBB54_75950; RV64ZVE32F-NEXT:  .LBB54_3: # %else45951; RV64ZVE32F-NEXT:    andi a3, a3, 85952; RV64ZVE32F-NEXT:    bnez a3, .LBB54_85953; RV64ZVE32F-NEXT:  .LBB54_4: # %else65954; RV64ZVE32F-NEXT:    ret5955; RV64ZVE32F-NEXT:  .LBB54_5: # %cond.store5956; RV64ZVE32F-NEXT:    ld a0, 0(a0)5957; RV64ZVE32F-NEXT:    vsetvli zero, zero, e16, m2, ta, ma5958; RV64ZVE32F-NEXT:    vmv.x.s a5, v85959; RV64ZVE32F-NEXT:    fmv.h.x fa5, a55960; RV64ZVE32F-NEXT:    fsh fa5, 0(a0)5961; RV64ZVE32F-NEXT:    andi a0, a3, 25962; RV64ZVE32F-NEXT:    beqz a0, .LBB54_25963; RV64ZVE32F-NEXT:  .LBB54_6: # %cond.store15964; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma5965; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 15966; RV64ZVE32F-NEXT:    vmv.x.s a0, v95967; RV64ZVE32F-NEXT:    fmv.h.x fa5, a05968; RV64ZVE32F-NEXT:    fsh fa5, 0(a4)5969; RV64ZVE32F-NEXT:    andi a0, a3, 45970; RV64ZVE32F-NEXT:    beqz a0, .LBB54_35971; RV64ZVE32F-NEXT:  .LBB54_7: # %cond.store35972; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma5973; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 25974; RV64ZVE32F-NEXT:    vmv.x.s a0, v95975; RV64ZVE32F-NEXT:    fmv.h.x fa5, a05976; RV64ZVE32F-NEXT:    fsh fa5, 0(a2)5977; RV64ZVE32F-NEXT:    andi a3, a3, 85978; RV64ZVE32F-NEXT:    beqz a3, .LBB54_45979; RV64ZVE32F-NEXT:  .LBB54_8: # %cond.store55980; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma5981; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 35982; RV64ZVE32F-NEXT:    vmv.x.s a0, v85983; RV64ZVE32F-NEXT:    fmv.h.x fa5, a05984; RV64ZVE32F-NEXT:    fsh fa5, 0(a1)5985; RV64ZVE32F-NEXT:    ret5986  call void @llvm.masked.scatter.v4bf16.v4p0(<4 x bfloat> %val, <4 x ptr> %ptrs, i32 2, <4 x i1> %m)5987  ret void5988}5989 5990define void @mscatter_truemask_v4bf16(<4 x bfloat> %val, <4 x ptr> %ptrs) {5991; RV32-LABEL: mscatter_truemask_v4bf16:5992; RV32:       # %bb.0:5993; RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma5994; RV32-NEXT:    vsoxei32.v v8, (zero), v95995; RV32-NEXT:    ret5996;5997; RV64V-LABEL: mscatter_truemask_v4bf16:5998; RV64V:       # %bb.0:5999; RV64V-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma6000; RV64V-NEXT:    vsoxei64.v v8, (zero), v106001; RV64V-NEXT:    ret6002;6003; RV64ZVE32F-LABEL: mscatter_truemask_v4bf16:6004; RV64ZVE32F:       # %bb.0:6005; RV64ZVE32F-NEXT:    ld a1, 0(a0)6006; RV64ZVE32F-NEXT:    ld a2, 8(a0)6007; RV64ZVE32F-NEXT:    ld a3, 16(a0)6008; RV64ZVE32F-NEXT:    ld a0, 24(a0)6009; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma6010; RV64ZVE32F-NEXT:    vmv.x.s a4, v86011; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 16012; RV64ZVE32F-NEXT:    fmv.h.x fa5, a46013; RV64ZVE32F-NEXT:    vmv.x.s a4, v96014; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 26015; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 36016; RV64ZVE32F-NEXT:    fsh fa5, 0(a1)6017; RV64ZVE32F-NEXT:    vmv.x.s a1, v96018; RV64ZVE32F-NEXT:    fmv.h.x fa5, a46019; RV64ZVE32F-NEXT:    vmv.x.s a4, v86020; RV64ZVE32F-NEXT:    fsh fa5, 0(a2)6021; RV64ZVE32F-NEXT:    fmv.h.x fa5, a16022; RV64ZVE32F-NEXT:    fsh fa5, 0(a3)6023; RV64ZVE32F-NEXT:    fmv.h.x fa5, a46024; RV64ZVE32F-NEXT:    fsh fa5, 0(a0)6025; RV64ZVE32F-NEXT:    ret6026  call void @llvm.masked.scatter.v4bf16.v4p0(<4 x bfloat> %val, <4 x ptr> %ptrs, i32 2, <4 x i1> splat (i1 1))6027  ret void6028}6029 6030define void @mscatter_falsemask_v4bf16(<4 x bfloat> %val, <4 x ptr> %ptrs) {6031; CHECK-LABEL: mscatter_falsemask_v4bf16:6032; CHECK:       # %bb.0:6033; CHECK-NEXT:    ret6034  call void @llvm.masked.scatter.v4bf16.v4p0(<4 x bfloat> %val, <4 x ptr> %ptrs, i32 2, <4 x i1> zeroinitializer)6035  ret void6036}6037 6038define void @mscatter_v8bf16(<8 x bfloat> %val, <8 x ptr> %ptrs, <8 x i1> %m) {6039; RV32-LABEL: mscatter_v8bf16:6040; RV32:       # %bb.0:6041; RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma6042; RV32-NEXT:    vsoxei32.v v8, (zero), v10, v0.t6043; RV32-NEXT:    ret6044;6045; RV64V-LABEL: mscatter_v8bf16:6046; RV64V:       # %bb.0:6047; RV64V-NEXT:    vsetivli zero, 8, e16, m1, ta, ma6048; RV64V-NEXT:    vsoxei64.v v8, (zero), v12, v0.t6049; RV64V-NEXT:    ret6050;6051; RV64ZVE32F-LABEL: mscatter_v8bf16:6052; RV64ZVE32F:       # %bb.0:6053; RV64ZVE32F-NEXT:    ld a3, 40(a0)6054; RV64ZVE32F-NEXT:    ld a2, 48(a0)6055; RV64ZVE32F-NEXT:    ld a1, 56(a0)6056; RV64ZVE32F-NEXT:    ld t0, 8(a0)6057; RV64ZVE32F-NEXT:    ld a7, 16(a0)6058; RV64ZVE32F-NEXT:    ld a6, 24(a0)6059; RV64ZVE32F-NEXT:    ld a5, 32(a0)6060; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma6061; RV64ZVE32F-NEXT:    vmv.x.s a4, v06062; RV64ZVE32F-NEXT:    andi t1, a4, 16063; RV64ZVE32F-NEXT:    bnez t1, .LBB57_96064; RV64ZVE32F-NEXT:  # %bb.1: # %else6065; RV64ZVE32F-NEXT:    andi a0, a4, 26066; RV64ZVE32F-NEXT:    bnez a0, .LBB57_106067; RV64ZVE32F-NEXT:  .LBB57_2: # %else26068; RV64ZVE32F-NEXT:    andi a0, a4, 46069; RV64ZVE32F-NEXT:    bnez a0, .LBB57_116070; RV64ZVE32F-NEXT:  .LBB57_3: # %else46071; RV64ZVE32F-NEXT:    andi a0, a4, 86072; RV64ZVE32F-NEXT:    bnez a0, .LBB57_126073; RV64ZVE32F-NEXT:  .LBB57_4: # %else66074; RV64ZVE32F-NEXT:    andi a0, a4, 166075; RV64ZVE32F-NEXT:    bnez a0, .LBB57_136076; RV64ZVE32F-NEXT:  .LBB57_5: # %else86077; RV64ZVE32F-NEXT:    andi a0, a4, 326078; RV64ZVE32F-NEXT:    bnez a0, .LBB57_146079; RV64ZVE32F-NEXT:  .LBB57_6: # %else106080; RV64ZVE32F-NEXT:    andi a0, a4, 646081; RV64ZVE32F-NEXT:    bnez a0, .LBB57_156082; RV64ZVE32F-NEXT:  .LBB57_7: # %else126083; RV64ZVE32F-NEXT:    andi a0, a4, -1286084; RV64ZVE32F-NEXT:    bnez a0, .LBB57_166085; RV64ZVE32F-NEXT:  .LBB57_8: # %else146086; RV64ZVE32F-NEXT:    ret6087; RV64ZVE32F-NEXT:  .LBB57_9: # %cond.store6088; RV64ZVE32F-NEXT:    ld a0, 0(a0)6089; RV64ZVE32F-NEXT:    vsetvli zero, zero, e16, m2, ta, ma6090; RV64ZVE32F-NEXT:    vmv.x.s t1, v86091; RV64ZVE32F-NEXT:    fmv.h.x fa5, t16092; RV64ZVE32F-NEXT:    fsh fa5, 0(a0)6093; RV64ZVE32F-NEXT:    andi a0, a4, 26094; RV64ZVE32F-NEXT:    beqz a0, .LBB57_26095; RV64ZVE32F-NEXT:  .LBB57_10: # %cond.store16096; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma6097; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 16098; RV64ZVE32F-NEXT:    vmv.x.s a0, v96099; RV64ZVE32F-NEXT:    fmv.h.x fa5, a06100; RV64ZVE32F-NEXT:    fsh fa5, 0(t0)6101; RV64ZVE32F-NEXT:    andi a0, a4, 46102; RV64ZVE32F-NEXT:    beqz a0, .LBB57_36103; RV64ZVE32F-NEXT:  .LBB57_11: # %cond.store36104; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma6105; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 26106; RV64ZVE32F-NEXT:    vmv.x.s a0, v96107; RV64ZVE32F-NEXT:    fmv.h.x fa5, a06108; RV64ZVE32F-NEXT:    fsh fa5, 0(a7)6109; RV64ZVE32F-NEXT:    andi a0, a4, 86110; RV64ZVE32F-NEXT:    beqz a0, .LBB57_46111; RV64ZVE32F-NEXT:  .LBB57_12: # %cond.store56112; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma6113; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 36114; RV64ZVE32F-NEXT:    vmv.x.s a0, v96115; RV64ZVE32F-NEXT:    fmv.h.x fa5, a06116; RV64ZVE32F-NEXT:    fsh fa5, 0(a6)6117; RV64ZVE32F-NEXT:    andi a0, a4, 166118; RV64ZVE32F-NEXT:    beqz a0, .LBB57_56119; RV64ZVE32F-NEXT:  .LBB57_13: # %cond.store76120; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma6121; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 46122; RV64ZVE32F-NEXT:    vmv.x.s a0, v96123; RV64ZVE32F-NEXT:    fmv.h.x fa5, a06124; RV64ZVE32F-NEXT:    fsh fa5, 0(a5)6125; RV64ZVE32F-NEXT:    andi a0, a4, 326126; RV64ZVE32F-NEXT:    beqz a0, .LBB57_66127; RV64ZVE32F-NEXT:  .LBB57_14: # %cond.store96128; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma6129; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 56130; RV64ZVE32F-NEXT:    vmv.x.s a0, v96131; RV64ZVE32F-NEXT:    fmv.h.x fa5, a06132; RV64ZVE32F-NEXT:    fsh fa5, 0(a3)6133; RV64ZVE32F-NEXT:    andi a0, a4, 646134; RV64ZVE32F-NEXT:    beqz a0, .LBB57_76135; RV64ZVE32F-NEXT:  .LBB57_15: # %cond.store116136; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma6137; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 66138; RV64ZVE32F-NEXT:    vmv.x.s a0, v96139; RV64ZVE32F-NEXT:    fmv.h.x fa5, a06140; RV64ZVE32F-NEXT:    fsh fa5, 0(a2)6141; RV64ZVE32F-NEXT:    andi a0, a4, -1286142; RV64ZVE32F-NEXT:    beqz a0, .LBB57_86143; RV64ZVE32F-NEXT:  .LBB57_16: # %cond.store136144; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma6145; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 76146; RV64ZVE32F-NEXT:    vmv.x.s a0, v86147; RV64ZVE32F-NEXT:    fmv.h.x fa5, a06148; RV64ZVE32F-NEXT:    fsh fa5, 0(a1)6149; RV64ZVE32F-NEXT:    ret6150  call void @llvm.masked.scatter.v8bf16.v8p0(<8 x bfloat> %val, <8 x ptr> %ptrs, i32 2, <8 x i1> %m)6151  ret void6152}6153 6154define void @mscatter_baseidx_v8i8_v8bf16(<8 x bfloat> %val, ptr %base, <8 x i8> %idxs, <8 x i1> %m) {6155; RV32-LABEL: mscatter_baseidx_v8i8_v8bf16:6156; RV32:       # %bb.0:6157; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma6158; RV32-NEXT:    vsext.vf4 v10, v96159; RV32-NEXT:    vadd.vv v10, v10, v106160; RV32-NEXT:    vsetvli zero, zero, e16, m1, ta, ma6161; RV32-NEXT:    vsoxei32.v v8, (a0), v10, v0.t6162; RV32-NEXT:    ret6163;6164; RV64V-LABEL: mscatter_baseidx_v8i8_v8bf16:6165; RV64V:       # %bb.0:6166; RV64V-NEXT:    vsetivli zero, 8, e64, m4, ta, ma6167; RV64V-NEXT:    vsext.vf8 v12, v96168; RV64V-NEXT:    vadd.vv v12, v12, v126169; RV64V-NEXT:    vsetvli zero, zero, e16, m1, ta, ma6170; RV64V-NEXT:    vsoxei64.v v8, (a0), v12, v0.t6171; RV64V-NEXT:    ret6172;6173; RV64ZVE32F-LABEL: mscatter_baseidx_v8i8_v8bf16:6174; RV64ZVE32F:       # %bb.0:6175; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma6176; RV64ZVE32F-NEXT:    vmv.x.s a1, v06177; RV64ZVE32F-NEXT:    andi a2, a1, 16178; RV64ZVE32F-NEXT:    beqz a2, .LBB58_26179; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store6180; RV64ZVE32F-NEXT:    vmv.x.s a2, v96181; RV64ZVE32F-NEXT:    vsetvli zero, zero, e16, m2, ta, ma6182; RV64ZVE32F-NEXT:    vmv.x.s a3, v86183; RV64ZVE32F-NEXT:    slli a2, a2, 16184; RV64ZVE32F-NEXT:    add a2, a0, a26185; RV64ZVE32F-NEXT:    fmv.h.x fa5, a36186; RV64ZVE32F-NEXT:    fsh fa5, 0(a2)6187; RV64ZVE32F-NEXT:  .LBB58_2: # %else6188; RV64ZVE32F-NEXT:    andi a2, a1, 26189; RV64ZVE32F-NEXT:    beqz a2, .LBB58_46190; RV64ZVE32F-NEXT:  # %bb.3: # %cond.store16191; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma6192; RV64ZVE32F-NEXT:    vslidedown.vi v10, v9, 16193; RV64ZVE32F-NEXT:    vmv.x.s a2, v106194; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma6195; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 16196; RV64ZVE32F-NEXT:    vmv.x.s a3, v106197; RV64ZVE32F-NEXT:    slli a2, a2, 16198; RV64ZVE32F-NEXT:    add a2, a0, a26199; RV64ZVE32F-NEXT:    fmv.h.x fa5, a36200; RV64ZVE32F-NEXT:    fsh fa5, 0(a2)6201; RV64ZVE32F-NEXT:  .LBB58_4: # %else26202; RV64ZVE32F-NEXT:    andi a2, a1, 46203; RV64ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma6204; RV64ZVE32F-NEXT:    vslidedown.vi v10, v9, 26205; RV64ZVE32F-NEXT:    beqz a2, .LBB58_66206; RV64ZVE32F-NEXT:  # %bb.5: # %cond.store36207; RV64ZVE32F-NEXT:    vmv.x.s a2, v106208; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma6209; RV64ZVE32F-NEXT:    vslidedown.vi v11, v8, 26210; RV64ZVE32F-NEXT:    slli a2, a2, 16211; RV64ZVE32F-NEXT:    vmv.x.s a3, v116212; RV64ZVE32F-NEXT:    add a2, a0, a26213; RV64ZVE32F-NEXT:    fmv.h.x fa5, a36214; RV64ZVE32F-NEXT:    fsh fa5, 0(a2)6215; RV64ZVE32F-NEXT:  .LBB58_6: # %else46216; RV64ZVE32F-NEXT:    andi a2, a1, 86217; RV64ZVE32F-NEXT:    beqz a2, .LBB58_86218; RV64ZVE32F-NEXT:  # %bb.7: # %cond.store56219; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma6220; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 16221; RV64ZVE32F-NEXT:    vmv.x.s a2, v106222; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma6223; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 36224; RV64ZVE32F-NEXT:    vmv.x.s a3, v106225; RV64ZVE32F-NEXT:    slli a2, a2, 16226; RV64ZVE32F-NEXT:    add a2, a0, a26227; RV64ZVE32F-NEXT:    fmv.h.x fa5, a36228; RV64ZVE32F-NEXT:    fsh fa5, 0(a2)6229; RV64ZVE32F-NEXT:  .LBB58_8: # %else66230; RV64ZVE32F-NEXT:    andi a2, a1, 166231; RV64ZVE32F-NEXT:    vsetivli zero, 4, e8, mf2, ta, ma6232; RV64ZVE32F-NEXT:    vslidedown.vi v9, v9, 46233; RV64ZVE32F-NEXT:    beqz a2, .LBB58_106234; RV64ZVE32F-NEXT:  # %bb.9: # %cond.store76235; RV64ZVE32F-NEXT:    vmv.x.s a2, v96236; RV64ZVE32F-NEXT:    vsetvli zero, zero, e16, m1, ta, ma6237; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 46238; RV64ZVE32F-NEXT:    slli a2, a2, 16239; RV64ZVE32F-NEXT:    vmv.x.s a3, v106240; RV64ZVE32F-NEXT:    add a2, a0, a26241; RV64ZVE32F-NEXT:    fmv.h.x fa5, a36242; RV64ZVE32F-NEXT:    fsh fa5, 0(a2)6243; RV64ZVE32F-NEXT:  .LBB58_10: # %else86244; RV64ZVE32F-NEXT:    andi a2, a1, 326245; RV64ZVE32F-NEXT:    beqz a2, .LBB58_126246; RV64ZVE32F-NEXT:  # %bb.11: # %cond.store96247; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma6248; RV64ZVE32F-NEXT:    vslidedown.vi v10, v9, 16249; RV64ZVE32F-NEXT:    vmv.x.s a2, v106250; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma6251; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 56252; RV64ZVE32F-NEXT:    vmv.x.s a3, v106253; RV64ZVE32F-NEXT:    slli a2, a2, 16254; RV64ZVE32F-NEXT:    add a2, a0, a26255; RV64ZVE32F-NEXT:    fmv.h.x fa5, a36256; RV64ZVE32F-NEXT:    fsh fa5, 0(a2)6257; RV64ZVE32F-NEXT:  .LBB58_12: # %else106258; RV64ZVE32F-NEXT:    andi a2, a1, 646259; RV64ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma6260; RV64ZVE32F-NEXT:    vslidedown.vi v9, v9, 26261; RV64ZVE32F-NEXT:    bnez a2, .LBB58_156262; RV64ZVE32F-NEXT:  # %bb.13: # %else126263; RV64ZVE32F-NEXT:    andi a1, a1, -1286264; RV64ZVE32F-NEXT:    bnez a1, .LBB58_166265; RV64ZVE32F-NEXT:  .LBB58_14: # %else146266; RV64ZVE32F-NEXT:    ret6267; RV64ZVE32F-NEXT:  .LBB58_15: # %cond.store116268; RV64ZVE32F-NEXT:    vmv.x.s a2, v96269; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma6270; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 66271; RV64ZVE32F-NEXT:    slli a2, a2, 16272; RV64ZVE32F-NEXT:    vmv.x.s a3, v106273; RV64ZVE32F-NEXT:    add a2, a0, a26274; RV64ZVE32F-NEXT:    fmv.h.x fa5, a36275; RV64ZVE32F-NEXT:    fsh fa5, 0(a2)6276; RV64ZVE32F-NEXT:    andi a1, a1, -1286277; RV64ZVE32F-NEXT:    beqz a1, .LBB58_146278; RV64ZVE32F-NEXT:  .LBB58_16: # %cond.store136279; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma6280; RV64ZVE32F-NEXT:    vslidedown.vi v9, v9, 16281; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma6282; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 76283; RV64ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma6284; RV64ZVE32F-NEXT:    vmv.x.s a1, v96285; RV64ZVE32F-NEXT:    slli a1, a1, 16286; RV64ZVE32F-NEXT:    add a0, a0, a16287; RV64ZVE32F-NEXT:    vsetvli zero, zero, e16, m1, ta, ma6288; RV64ZVE32F-NEXT:    vmv.x.s a1, v86289; RV64ZVE32F-NEXT:    fmv.h.x fa5, a16290; RV64ZVE32F-NEXT:    fsh fa5, 0(a0)6291; RV64ZVE32F-NEXT:    ret6292  %ptrs = getelementptr inbounds bfloat, ptr %base, <8 x i8> %idxs6293  call void @llvm.masked.scatter.v8bf16.v8p0(<8 x bfloat> %val, <8 x ptr> %ptrs, i32 2, <8 x i1> %m)6294  ret void6295}6296 6297define void @mscatter_baseidx_sext_v8i8_v8bf16(<8 x bfloat> %val, ptr %base, <8 x i8> %idxs, <8 x i1> %m) {6298; RV32-LABEL: mscatter_baseidx_sext_v8i8_v8bf16:6299; RV32:       # %bb.0:6300; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma6301; RV32-NEXT:    vsext.vf4 v10, v96302; RV32-NEXT:    vadd.vv v10, v10, v106303; RV32-NEXT:    vsetvli zero, zero, e16, m1, ta, ma6304; RV32-NEXT:    vsoxei32.v v8, (a0), v10, v0.t6305; RV32-NEXT:    ret6306;6307; RV64V-LABEL: mscatter_baseidx_sext_v8i8_v8bf16:6308; RV64V:       # %bb.0:6309; RV64V-NEXT:    vsetivli zero, 8, e64, m4, ta, ma6310; RV64V-NEXT:    vsext.vf8 v12, v96311; RV64V-NEXT:    vadd.vv v12, v12, v126312; RV64V-NEXT:    vsetvli zero, zero, e16, m1, ta, ma6313; RV64V-NEXT:    vsoxei64.v v8, (a0), v12, v0.t6314; RV64V-NEXT:    ret6315;6316; RV64ZVE32F-LABEL: mscatter_baseidx_sext_v8i8_v8bf16:6317; RV64ZVE32F:       # %bb.0:6318; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma6319; RV64ZVE32F-NEXT:    vmv.x.s a1, v06320; RV64ZVE32F-NEXT:    andi a2, a1, 16321; RV64ZVE32F-NEXT:    beqz a2, .LBB59_26322; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store6323; RV64ZVE32F-NEXT:    vmv.x.s a2, v96324; RV64ZVE32F-NEXT:    vsetvli zero, zero, e16, m2, ta, ma6325; RV64ZVE32F-NEXT:    vmv.x.s a3, v86326; RV64ZVE32F-NEXT:    slli a2, a2, 16327; RV64ZVE32F-NEXT:    add a2, a0, a26328; RV64ZVE32F-NEXT:    fmv.h.x fa5, a36329; RV64ZVE32F-NEXT:    fsh fa5, 0(a2)6330; RV64ZVE32F-NEXT:  .LBB59_2: # %else6331; RV64ZVE32F-NEXT:    andi a2, a1, 26332; RV64ZVE32F-NEXT:    beqz a2, .LBB59_46333; RV64ZVE32F-NEXT:  # %bb.3: # %cond.store16334; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma6335; RV64ZVE32F-NEXT:    vslidedown.vi v10, v9, 16336; RV64ZVE32F-NEXT:    vmv.x.s a2, v106337; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma6338; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 16339; RV64ZVE32F-NEXT:    vmv.x.s a3, v106340; RV64ZVE32F-NEXT:    slli a2, a2, 16341; RV64ZVE32F-NEXT:    add a2, a0, a26342; RV64ZVE32F-NEXT:    fmv.h.x fa5, a36343; RV64ZVE32F-NEXT:    fsh fa5, 0(a2)6344; RV64ZVE32F-NEXT:  .LBB59_4: # %else26345; RV64ZVE32F-NEXT:    andi a2, a1, 46346; RV64ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma6347; RV64ZVE32F-NEXT:    vslidedown.vi v10, v9, 26348; RV64ZVE32F-NEXT:    beqz a2, .LBB59_66349; RV64ZVE32F-NEXT:  # %bb.5: # %cond.store36350; RV64ZVE32F-NEXT:    vmv.x.s a2, v106351; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma6352; RV64ZVE32F-NEXT:    vslidedown.vi v11, v8, 26353; RV64ZVE32F-NEXT:    slli a2, a2, 16354; RV64ZVE32F-NEXT:    vmv.x.s a3, v116355; RV64ZVE32F-NEXT:    add a2, a0, a26356; RV64ZVE32F-NEXT:    fmv.h.x fa5, a36357; RV64ZVE32F-NEXT:    fsh fa5, 0(a2)6358; RV64ZVE32F-NEXT:  .LBB59_6: # %else46359; RV64ZVE32F-NEXT:    andi a2, a1, 86360; RV64ZVE32F-NEXT:    beqz a2, .LBB59_86361; RV64ZVE32F-NEXT:  # %bb.7: # %cond.store56362; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma6363; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 16364; RV64ZVE32F-NEXT:    vmv.x.s a2, v106365; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma6366; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 36367; RV64ZVE32F-NEXT:    vmv.x.s a3, v106368; RV64ZVE32F-NEXT:    slli a2, a2, 16369; RV64ZVE32F-NEXT:    add a2, a0, a26370; RV64ZVE32F-NEXT:    fmv.h.x fa5, a36371; RV64ZVE32F-NEXT:    fsh fa5, 0(a2)6372; RV64ZVE32F-NEXT:  .LBB59_8: # %else66373; RV64ZVE32F-NEXT:    andi a2, a1, 166374; RV64ZVE32F-NEXT:    vsetivli zero, 4, e8, mf2, ta, ma6375; RV64ZVE32F-NEXT:    vslidedown.vi v9, v9, 46376; RV64ZVE32F-NEXT:    beqz a2, .LBB59_106377; RV64ZVE32F-NEXT:  # %bb.9: # %cond.store76378; RV64ZVE32F-NEXT:    vmv.x.s a2, v96379; RV64ZVE32F-NEXT:    vsetvli zero, zero, e16, m1, ta, ma6380; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 46381; RV64ZVE32F-NEXT:    slli a2, a2, 16382; RV64ZVE32F-NEXT:    vmv.x.s a3, v106383; RV64ZVE32F-NEXT:    add a2, a0, a26384; RV64ZVE32F-NEXT:    fmv.h.x fa5, a36385; RV64ZVE32F-NEXT:    fsh fa5, 0(a2)6386; RV64ZVE32F-NEXT:  .LBB59_10: # %else86387; RV64ZVE32F-NEXT:    andi a2, a1, 326388; RV64ZVE32F-NEXT:    beqz a2, .LBB59_126389; RV64ZVE32F-NEXT:  # %bb.11: # %cond.store96390; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma6391; RV64ZVE32F-NEXT:    vslidedown.vi v10, v9, 16392; RV64ZVE32F-NEXT:    vmv.x.s a2, v106393; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma6394; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 56395; RV64ZVE32F-NEXT:    vmv.x.s a3, v106396; RV64ZVE32F-NEXT:    slli a2, a2, 16397; RV64ZVE32F-NEXT:    add a2, a0, a26398; RV64ZVE32F-NEXT:    fmv.h.x fa5, a36399; RV64ZVE32F-NEXT:    fsh fa5, 0(a2)6400; RV64ZVE32F-NEXT:  .LBB59_12: # %else106401; RV64ZVE32F-NEXT:    andi a2, a1, 646402; RV64ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma6403; RV64ZVE32F-NEXT:    vslidedown.vi v9, v9, 26404; RV64ZVE32F-NEXT:    bnez a2, .LBB59_156405; RV64ZVE32F-NEXT:  # %bb.13: # %else126406; RV64ZVE32F-NEXT:    andi a1, a1, -1286407; RV64ZVE32F-NEXT:    bnez a1, .LBB59_166408; RV64ZVE32F-NEXT:  .LBB59_14: # %else146409; RV64ZVE32F-NEXT:    ret6410; RV64ZVE32F-NEXT:  .LBB59_15: # %cond.store116411; RV64ZVE32F-NEXT:    vmv.x.s a2, v96412; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma6413; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 66414; RV64ZVE32F-NEXT:    slli a2, a2, 16415; RV64ZVE32F-NEXT:    vmv.x.s a3, v106416; RV64ZVE32F-NEXT:    add a2, a0, a26417; RV64ZVE32F-NEXT:    fmv.h.x fa5, a36418; RV64ZVE32F-NEXT:    fsh fa5, 0(a2)6419; RV64ZVE32F-NEXT:    andi a1, a1, -1286420; RV64ZVE32F-NEXT:    beqz a1, .LBB59_146421; RV64ZVE32F-NEXT:  .LBB59_16: # %cond.store136422; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma6423; RV64ZVE32F-NEXT:    vslidedown.vi v9, v9, 16424; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma6425; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 76426; RV64ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma6427; RV64ZVE32F-NEXT:    vmv.x.s a1, v96428; RV64ZVE32F-NEXT:    slli a1, a1, 16429; RV64ZVE32F-NEXT:    add a0, a0, a16430; RV64ZVE32F-NEXT:    vsetvli zero, zero, e16, m1, ta, ma6431; RV64ZVE32F-NEXT:    vmv.x.s a1, v86432; RV64ZVE32F-NEXT:    fmv.h.x fa5, a16433; RV64ZVE32F-NEXT:    fsh fa5, 0(a0)6434; RV64ZVE32F-NEXT:    ret6435  %eidxs = sext <8 x i8> %idxs to <8 x i16>6436  %ptrs = getelementptr inbounds bfloat, ptr %base, <8 x i16> %eidxs6437  call void @llvm.masked.scatter.v8bf16.v8p0(<8 x bfloat> %val, <8 x ptr> %ptrs, i32 2, <8 x i1> %m)6438  ret void6439}6440 6441define void @mscatter_baseidx_zext_v8i8_v8bf16(<8 x bfloat> %val, ptr %base, <8 x i8> %idxs, <8 x i1> %m) {6442; RV32-LABEL: mscatter_baseidx_zext_v8i8_v8bf16:6443; RV32:       # %bb.0:6444; RV32-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma6445; RV32-NEXT:    vwaddu.vv v10, v9, v96446; RV32-NEXT:    vsetvli zero, zero, e16, m1, ta, ma6447; RV32-NEXT:    vsoxei16.v v8, (a0), v10, v0.t6448; RV32-NEXT:    ret6449;6450; RV64V-LABEL: mscatter_baseidx_zext_v8i8_v8bf16:6451; RV64V:       # %bb.0:6452; RV64V-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma6453; RV64V-NEXT:    vwaddu.vv v10, v9, v96454; RV64V-NEXT:    vsetvli zero, zero, e16, m1, ta, ma6455; RV64V-NEXT:    vsoxei16.v v8, (a0), v10, v0.t6456; RV64V-NEXT:    ret6457;6458; RV64ZVE32F-LABEL: mscatter_baseidx_zext_v8i8_v8bf16:6459; RV64ZVE32F:       # %bb.0:6460; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma6461; RV64ZVE32F-NEXT:    vmv.x.s a1, v06462; RV64ZVE32F-NEXT:    andi a2, a1, 16463; RV64ZVE32F-NEXT:    beqz a2, .LBB60_26464; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store6465; RV64ZVE32F-NEXT:    vmv.x.s a2, v96466; RV64ZVE32F-NEXT:    vsetvli zero, zero, e16, m2, ta, ma6467; RV64ZVE32F-NEXT:    vmv.x.s a3, v86468; RV64ZVE32F-NEXT:    zext.b a2, a26469; RV64ZVE32F-NEXT:    slli a2, a2, 16470; RV64ZVE32F-NEXT:    add a2, a0, a26471; RV64ZVE32F-NEXT:    fmv.h.x fa5, a36472; RV64ZVE32F-NEXT:    fsh fa5, 0(a2)6473; RV64ZVE32F-NEXT:  .LBB60_2: # %else6474; RV64ZVE32F-NEXT:    andi a2, a1, 26475; RV64ZVE32F-NEXT:    beqz a2, .LBB60_46476; RV64ZVE32F-NEXT:  # %bb.3: # %cond.store16477; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma6478; RV64ZVE32F-NEXT:    vslidedown.vi v10, v9, 16479; RV64ZVE32F-NEXT:    vmv.x.s a2, v106480; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma6481; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 16482; RV64ZVE32F-NEXT:    vmv.x.s a3, v106483; RV64ZVE32F-NEXT:    zext.b a2, a26484; RV64ZVE32F-NEXT:    slli a2, a2, 16485; RV64ZVE32F-NEXT:    add a2, a0, a26486; RV64ZVE32F-NEXT:    fmv.h.x fa5, a36487; RV64ZVE32F-NEXT:    fsh fa5, 0(a2)6488; RV64ZVE32F-NEXT:  .LBB60_4: # %else26489; RV64ZVE32F-NEXT:    andi a2, a1, 46490; RV64ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma6491; RV64ZVE32F-NEXT:    vslidedown.vi v10, v9, 26492; RV64ZVE32F-NEXT:    beqz a2, .LBB60_66493; RV64ZVE32F-NEXT:  # %bb.5: # %cond.store36494; RV64ZVE32F-NEXT:    vmv.x.s a2, v106495; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma6496; RV64ZVE32F-NEXT:    vslidedown.vi v11, v8, 26497; RV64ZVE32F-NEXT:    zext.b a2, a26498; RV64ZVE32F-NEXT:    vmv.x.s a3, v116499; RV64ZVE32F-NEXT:    slli a2, a2, 16500; RV64ZVE32F-NEXT:    add a2, a0, a26501; RV64ZVE32F-NEXT:    fmv.h.x fa5, a36502; RV64ZVE32F-NEXT:    fsh fa5, 0(a2)6503; RV64ZVE32F-NEXT:  .LBB60_6: # %else46504; RV64ZVE32F-NEXT:    andi a2, a1, 86505; RV64ZVE32F-NEXT:    beqz a2, .LBB60_86506; RV64ZVE32F-NEXT:  # %bb.7: # %cond.store56507; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma6508; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 16509; RV64ZVE32F-NEXT:    vmv.x.s a2, v106510; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma6511; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 36512; RV64ZVE32F-NEXT:    vmv.x.s a3, v106513; RV64ZVE32F-NEXT:    zext.b a2, a26514; RV64ZVE32F-NEXT:    slli a2, a2, 16515; RV64ZVE32F-NEXT:    add a2, a0, a26516; RV64ZVE32F-NEXT:    fmv.h.x fa5, a36517; RV64ZVE32F-NEXT:    fsh fa5, 0(a2)6518; RV64ZVE32F-NEXT:  .LBB60_8: # %else66519; RV64ZVE32F-NEXT:    andi a2, a1, 166520; RV64ZVE32F-NEXT:    vsetivli zero, 4, e8, mf2, ta, ma6521; RV64ZVE32F-NEXT:    vslidedown.vi v9, v9, 46522; RV64ZVE32F-NEXT:    beqz a2, .LBB60_106523; RV64ZVE32F-NEXT:  # %bb.9: # %cond.store76524; RV64ZVE32F-NEXT:    vmv.x.s a2, v96525; RV64ZVE32F-NEXT:    vsetvli zero, zero, e16, m1, ta, ma6526; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 46527; RV64ZVE32F-NEXT:    zext.b a2, a26528; RV64ZVE32F-NEXT:    vmv.x.s a3, v106529; RV64ZVE32F-NEXT:    slli a2, a2, 16530; RV64ZVE32F-NEXT:    add a2, a0, a26531; RV64ZVE32F-NEXT:    fmv.h.x fa5, a36532; RV64ZVE32F-NEXT:    fsh fa5, 0(a2)6533; RV64ZVE32F-NEXT:  .LBB60_10: # %else86534; RV64ZVE32F-NEXT:    andi a2, a1, 326535; RV64ZVE32F-NEXT:    beqz a2, .LBB60_126536; RV64ZVE32F-NEXT:  # %bb.11: # %cond.store96537; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma6538; RV64ZVE32F-NEXT:    vslidedown.vi v10, v9, 16539; RV64ZVE32F-NEXT:    vmv.x.s a2, v106540; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma6541; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 56542; RV64ZVE32F-NEXT:    vmv.x.s a3, v106543; RV64ZVE32F-NEXT:    zext.b a2, a26544; RV64ZVE32F-NEXT:    slli a2, a2, 16545; RV64ZVE32F-NEXT:    add a2, a0, a26546; RV64ZVE32F-NEXT:    fmv.h.x fa5, a36547; RV64ZVE32F-NEXT:    fsh fa5, 0(a2)6548; RV64ZVE32F-NEXT:  .LBB60_12: # %else106549; RV64ZVE32F-NEXT:    andi a2, a1, 646550; RV64ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma6551; RV64ZVE32F-NEXT:    vslidedown.vi v9, v9, 26552; RV64ZVE32F-NEXT:    bnez a2, .LBB60_156553; RV64ZVE32F-NEXT:  # %bb.13: # %else126554; RV64ZVE32F-NEXT:    andi a1, a1, -1286555; RV64ZVE32F-NEXT:    bnez a1, .LBB60_166556; RV64ZVE32F-NEXT:  .LBB60_14: # %else146557; RV64ZVE32F-NEXT:    ret6558; RV64ZVE32F-NEXT:  .LBB60_15: # %cond.store116559; RV64ZVE32F-NEXT:    vmv.x.s a2, v96560; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma6561; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 66562; RV64ZVE32F-NEXT:    zext.b a2, a26563; RV64ZVE32F-NEXT:    vmv.x.s a3, v106564; RV64ZVE32F-NEXT:    slli a2, a2, 16565; RV64ZVE32F-NEXT:    add a2, a0, a26566; RV64ZVE32F-NEXT:    fmv.h.x fa5, a36567; RV64ZVE32F-NEXT:    fsh fa5, 0(a2)6568; RV64ZVE32F-NEXT:    andi a1, a1, -1286569; RV64ZVE32F-NEXT:    beqz a1, .LBB60_146570; RV64ZVE32F-NEXT:  .LBB60_16: # %cond.store136571; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma6572; RV64ZVE32F-NEXT:    vslidedown.vi v9, v9, 16573; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma6574; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 76575; RV64ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma6576; RV64ZVE32F-NEXT:    vmv.x.s a1, v96577; RV64ZVE32F-NEXT:    zext.b a1, a16578; RV64ZVE32F-NEXT:    slli a1, a1, 16579; RV64ZVE32F-NEXT:    add a0, a0, a16580; RV64ZVE32F-NEXT:    vsetvli zero, zero, e16, m1, ta, ma6581; RV64ZVE32F-NEXT:    vmv.x.s a1, v86582; RV64ZVE32F-NEXT:    fmv.h.x fa5, a16583; RV64ZVE32F-NEXT:    fsh fa5, 0(a0)6584; RV64ZVE32F-NEXT:    ret6585  %eidxs = zext <8 x i8> %idxs to <8 x i16>6586  %ptrs = getelementptr inbounds bfloat, ptr %base, <8 x i16> %eidxs6587  call void @llvm.masked.scatter.v8bf16.v8p0(<8 x bfloat> %val, <8 x ptr> %ptrs, i32 2, <8 x i1> %m)6588  ret void6589}6590 6591define void @mscatter_baseidx_v8bf16(<8 x bfloat> %val, ptr %base, <8 x i16> %idxs, <8 x i1> %m) {6592; RV32-LABEL: mscatter_baseidx_v8bf16:6593; RV32:       # %bb.0:6594; RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma6595; RV32-NEXT:    vwadd.vv v10, v9, v96596; RV32-NEXT:    vsoxei32.v v8, (a0), v10, v0.t6597; RV32-NEXT:    ret6598;6599; RV64V-LABEL: mscatter_baseidx_v8bf16:6600; RV64V:       # %bb.0:6601; RV64V-NEXT:    vsetivli zero, 8, e64, m4, ta, ma6602; RV64V-NEXT:    vsext.vf4 v12, v96603; RV64V-NEXT:    vadd.vv v12, v12, v126604; RV64V-NEXT:    vsetvli zero, zero, e16, m1, ta, ma6605; RV64V-NEXT:    vsoxei64.v v8, (a0), v12, v0.t6606; RV64V-NEXT:    ret6607;6608; RV64ZVE32F-LABEL: mscatter_baseidx_v8bf16:6609; RV64ZVE32F:       # %bb.0:6610; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma6611; RV64ZVE32F-NEXT:    vmv.x.s a1, v06612; RV64ZVE32F-NEXT:    andi a2, a1, 16613; RV64ZVE32F-NEXT:    beqz a2, .LBB61_26614; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store6615; RV64ZVE32F-NEXT:    vsetvli zero, zero, e16, m2, ta, ma6616; RV64ZVE32F-NEXT:    vmv.x.s a2, v96617; RV64ZVE32F-NEXT:    vmv.x.s a3, v86618; RV64ZVE32F-NEXT:    slli a2, a2, 16619; RV64ZVE32F-NEXT:    add a2, a0, a26620; RV64ZVE32F-NEXT:    fmv.h.x fa5, a36621; RV64ZVE32F-NEXT:    fsh fa5, 0(a2)6622; RV64ZVE32F-NEXT:  .LBB61_2: # %else6623; RV64ZVE32F-NEXT:    andi a2, a1, 26624; RV64ZVE32F-NEXT:    beqz a2, .LBB61_46625; RV64ZVE32F-NEXT:  # %bb.3: # %cond.store16626; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma6627; RV64ZVE32F-NEXT:    vslidedown.vi v10, v9, 16628; RV64ZVE32F-NEXT:    vmv.x.s a2, v106629; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma6630; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 16631; RV64ZVE32F-NEXT:    vmv.x.s a3, v106632; RV64ZVE32F-NEXT:    slli a2, a2, 16633; RV64ZVE32F-NEXT:    add a2, a0, a26634; RV64ZVE32F-NEXT:    fmv.h.x fa5, a36635; RV64ZVE32F-NEXT:    fsh fa5, 0(a2)6636; RV64ZVE32F-NEXT:  .LBB61_4: # %else26637; RV64ZVE32F-NEXT:    andi a2, a1, 46638; RV64ZVE32F-NEXT:    vsetivli zero, 2, e16, mf2, ta, ma6639; RV64ZVE32F-NEXT:    vslidedown.vi v10, v9, 26640; RV64ZVE32F-NEXT:    beqz a2, .LBB61_66641; RV64ZVE32F-NEXT:  # %bb.5: # %cond.store36642; RV64ZVE32F-NEXT:    vmv.x.s a2, v106643; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma6644; RV64ZVE32F-NEXT:    vslidedown.vi v11, v8, 26645; RV64ZVE32F-NEXT:    slli a2, a2, 16646; RV64ZVE32F-NEXT:    vmv.x.s a3, v116647; RV64ZVE32F-NEXT:    add a2, a0, a26648; RV64ZVE32F-NEXT:    fmv.h.x fa5, a36649; RV64ZVE32F-NEXT:    fsh fa5, 0(a2)6650; RV64ZVE32F-NEXT:  .LBB61_6: # %else46651; RV64ZVE32F-NEXT:    andi a2, a1, 86652; RV64ZVE32F-NEXT:    beqz a2, .LBB61_86653; RV64ZVE32F-NEXT:  # %bb.7: # %cond.store56654; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma6655; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 16656; RV64ZVE32F-NEXT:    vmv.x.s a2, v106657; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma6658; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 36659; RV64ZVE32F-NEXT:    vmv.x.s a3, v106660; RV64ZVE32F-NEXT:    slli a2, a2, 16661; RV64ZVE32F-NEXT:    add a2, a0, a26662; RV64ZVE32F-NEXT:    fmv.h.x fa5, a36663; RV64ZVE32F-NEXT:    fsh fa5, 0(a2)6664; RV64ZVE32F-NEXT:  .LBB61_8: # %else66665; RV64ZVE32F-NEXT:    andi a2, a1, 166666; RV64ZVE32F-NEXT:    vsetivli zero, 4, e16, m1, ta, ma6667; RV64ZVE32F-NEXT:    vslidedown.vi v9, v9, 46668; RV64ZVE32F-NEXT:    beqz a2, .LBB61_106669; RV64ZVE32F-NEXT:  # %bb.9: # %cond.store76670; RV64ZVE32F-NEXT:    vmv.x.s a2, v96671; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 46672; RV64ZVE32F-NEXT:    slli a2, a2, 16673; RV64ZVE32F-NEXT:    vmv.x.s a3, v106674; RV64ZVE32F-NEXT:    add a2, a0, a26675; RV64ZVE32F-NEXT:    fmv.h.x fa5, a36676; RV64ZVE32F-NEXT:    fsh fa5, 0(a2)6677; RV64ZVE32F-NEXT:  .LBB61_10: # %else86678; RV64ZVE32F-NEXT:    andi a2, a1, 326679; RV64ZVE32F-NEXT:    beqz a2, .LBB61_126680; RV64ZVE32F-NEXT:  # %bb.11: # %cond.store96681; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma6682; RV64ZVE32F-NEXT:    vslidedown.vi v10, v9, 16683; RV64ZVE32F-NEXT:    vmv.x.s a2, v106684; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma6685; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 56686; RV64ZVE32F-NEXT:    vmv.x.s a3, v106687; RV64ZVE32F-NEXT:    slli a2, a2, 16688; RV64ZVE32F-NEXT:    add a2, a0, a26689; RV64ZVE32F-NEXT:    fmv.h.x fa5, a36690; RV64ZVE32F-NEXT:    fsh fa5, 0(a2)6691; RV64ZVE32F-NEXT:  .LBB61_12: # %else106692; RV64ZVE32F-NEXT:    andi a2, a1, 646693; RV64ZVE32F-NEXT:    vsetivli zero, 2, e16, mf2, ta, ma6694; RV64ZVE32F-NEXT:    vslidedown.vi v9, v9, 26695; RV64ZVE32F-NEXT:    bnez a2, .LBB61_156696; RV64ZVE32F-NEXT:  # %bb.13: # %else126697; RV64ZVE32F-NEXT:    andi a1, a1, -1286698; RV64ZVE32F-NEXT:    bnez a1, .LBB61_166699; RV64ZVE32F-NEXT:  .LBB61_14: # %else146700; RV64ZVE32F-NEXT:    ret6701; RV64ZVE32F-NEXT:  .LBB61_15: # %cond.store116702; RV64ZVE32F-NEXT:    vmv.x.s a2, v96703; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma6704; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 66705; RV64ZVE32F-NEXT:    slli a2, a2, 16706; RV64ZVE32F-NEXT:    vmv.x.s a3, v106707; RV64ZVE32F-NEXT:    add a2, a0, a26708; RV64ZVE32F-NEXT:    fmv.h.x fa5, a36709; RV64ZVE32F-NEXT:    fsh fa5, 0(a2)6710; RV64ZVE32F-NEXT:    andi a1, a1, -1286711; RV64ZVE32F-NEXT:    beqz a1, .LBB61_146712; RV64ZVE32F-NEXT:  .LBB61_16: # %cond.store136713; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma6714; RV64ZVE32F-NEXT:    vslidedown.vi v9, v9, 16715; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma6716; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 76717; RV64ZVE32F-NEXT:    vmv.x.s a1, v96718; RV64ZVE32F-NEXT:    slli a1, a1, 16719; RV64ZVE32F-NEXT:    add a0, a0, a16720; RV64ZVE32F-NEXT:    vmv.x.s a1, v86721; RV64ZVE32F-NEXT:    fmv.h.x fa5, a16722; RV64ZVE32F-NEXT:    fsh fa5, 0(a0)6723; RV64ZVE32F-NEXT:    ret6724  %ptrs = getelementptr inbounds bfloat, ptr %base, <8 x i16> %idxs6725  call void @llvm.masked.scatter.v8bf16.v8p0(<8 x bfloat> %val, <8 x ptr> %ptrs, i32 2, <8 x i1> %m)6726  ret void6727}6728 6729define void @mscatter_v1f16(<1 x half> %val, <1 x ptr> %ptrs, <1 x i1> %m) {6730; RV32V-LABEL: mscatter_v1f16:6731; RV32V:       # %bb.0:6732; RV32V-NEXT:    vsetivli zero, 1, e16, mf4, ta, ma6733; RV32V-NEXT:    vsoxei32.v v8, (zero), v9, v0.t6734; RV32V-NEXT:    ret6735;6736; RV64V-LABEL: mscatter_v1f16:6737; RV64V:       # %bb.0:6738; RV64V-NEXT:    vsetivli zero, 1, e16, mf4, ta, ma6739; RV64V-NEXT:    vsoxei64.v v8, (zero), v9, v0.t6740; RV64V-NEXT:    ret6741;6742; RV32ZVE32F-LABEL: mscatter_v1f16:6743; RV32ZVE32F:       # %bb.0:6744; RV32ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma6745; RV32ZVE32F-NEXT:    vsoxei32.v v8, (zero), v9, v0.t6746; RV32ZVE32F-NEXT:    ret6747;6748; RV64ZVE32F-ZVFH-LABEL: mscatter_v1f16:6749; RV64ZVE32F-ZVFH:       # %bb.0:6750; RV64ZVE32F-ZVFH-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma6751; RV64ZVE32F-ZVFH-NEXT:    vfirst.m a1, v06752; RV64ZVE32F-ZVFH-NEXT:    bnez a1, .LBB62_26753; RV64ZVE32F-ZVFH-NEXT:  # %bb.1: # %cond.store6754; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma6755; RV64ZVE32F-ZVFH-NEXT:    vse16.v v8, (a0)6756; RV64ZVE32F-ZVFH-NEXT:  .LBB62_2: # %else6757; RV64ZVE32F-ZVFH-NEXT:    ret6758;6759; RV64ZVE32F-ZVFHMIN-LABEL: mscatter_v1f16:6760; RV64ZVE32F-ZVFHMIN:       # %bb.0:6761; RV64ZVE32F-ZVFHMIN-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma6762; RV64ZVE32F-ZVFHMIN-NEXT:    vfirst.m a1, v06763; RV64ZVE32F-ZVFHMIN-NEXT:    bnez a1, .LBB62_26764; RV64ZVE32F-ZVFHMIN-NEXT:  # %bb.1: # %cond.store6765; RV64ZVE32F-ZVFHMIN-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma6766; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a1, v86767; RV64ZVE32F-ZVFHMIN-NEXT:    fmv.h.x fa5, a16768; RV64ZVE32F-ZVFHMIN-NEXT:    fsh fa5, 0(a0)6769; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB62_2: # %else6770; RV64ZVE32F-ZVFHMIN-NEXT:    ret6771  call void @llvm.masked.scatter.v1f16.v1p0(<1 x half> %val, <1 x ptr> %ptrs, i32 2, <1 x i1> %m)6772  ret void6773}6774 6775define void @mscatter_v2f16(<2 x half> %val, <2 x ptr> %ptrs, <2 x i1> %m) {6776; RV32V-LABEL: mscatter_v2f16:6777; RV32V:       # %bb.0:6778; RV32V-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma6779; RV32V-NEXT:    vsoxei32.v v8, (zero), v9, v0.t6780; RV32V-NEXT:    ret6781;6782; RV64V-LABEL: mscatter_v2f16:6783; RV64V:       # %bb.0:6784; RV64V-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma6785; RV64V-NEXT:    vsoxei64.v v8, (zero), v9, v0.t6786; RV64V-NEXT:    ret6787;6788; RV32ZVE32F-LABEL: mscatter_v2f16:6789; RV32ZVE32F:       # %bb.0:6790; RV32ZVE32F-NEXT:    vsetivli zero, 2, e16, mf2, ta, ma6791; RV32ZVE32F-NEXT:    vsoxei32.v v8, (zero), v9, v0.t6792; RV32ZVE32F-NEXT:    ret6793;6794; RV64ZVE32F-ZVFH-LABEL: mscatter_v2f16:6795; RV64ZVE32F-ZVFH:       # %bb.0:6796; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e8, m1, ta, ma6797; RV64ZVE32F-ZVFH-NEXT:    vmv.x.s a2, v06798; RV64ZVE32F-ZVFH-NEXT:    andi a3, a2, 16799; RV64ZVE32F-ZVFH-NEXT:    bnez a3, .LBB63_36800; RV64ZVE32F-ZVFH-NEXT:  # %bb.1: # %else6801; RV64ZVE32F-ZVFH-NEXT:    andi a2, a2, 26802; RV64ZVE32F-ZVFH-NEXT:    bnez a2, .LBB63_46803; RV64ZVE32F-ZVFH-NEXT:  .LBB63_2: # %else26804; RV64ZVE32F-ZVFH-NEXT:    ret6805; RV64ZVE32F-ZVFH-NEXT:  .LBB63_3: # %cond.store6806; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma6807; RV64ZVE32F-ZVFH-NEXT:    vse16.v v8, (a0)6808; RV64ZVE32F-ZVFH-NEXT:    andi a2, a2, 26809; RV64ZVE32F-ZVFH-NEXT:    beqz a2, .LBB63_26810; RV64ZVE32F-ZVFH-NEXT:  .LBB63_4: # %cond.store16811; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma6812; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v8, v8, 16813; RV64ZVE32F-ZVFH-NEXT:    vse16.v v8, (a1)6814; RV64ZVE32F-ZVFH-NEXT:    ret6815;6816; RV64ZVE32F-ZVFHMIN-LABEL: mscatter_v2f16:6817; RV64ZVE32F-ZVFHMIN:       # %bb.0:6818; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e8, m1, ta, ma6819; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a2, v06820; RV64ZVE32F-ZVFHMIN-NEXT:    andi a3, a2, 16821; RV64ZVE32F-ZVFHMIN-NEXT:    bnez a3, .LBB63_36822; RV64ZVE32F-ZVFHMIN-NEXT:  # %bb.1: # %else6823; RV64ZVE32F-ZVFHMIN-NEXT:    andi a2, a2, 26824; RV64ZVE32F-ZVFHMIN-NEXT:    bnez a2, .LBB63_46825; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB63_2: # %else26826; RV64ZVE32F-ZVFHMIN-NEXT:    ret6827; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB63_3: # %cond.store6828; RV64ZVE32F-ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m2, ta, ma6829; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a3, v86830; RV64ZVE32F-ZVFHMIN-NEXT:    fmv.h.x fa5, a36831; RV64ZVE32F-ZVFHMIN-NEXT:    fsh fa5, 0(a0)6832; RV64ZVE32F-ZVFHMIN-NEXT:    andi a2, a2, 26833; RV64ZVE32F-ZVFHMIN-NEXT:    beqz a2, .LBB63_26834; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB63_4: # %cond.store16835; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma6836; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v8, v8, 16837; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a0, v86838; RV64ZVE32F-ZVFHMIN-NEXT:    fmv.h.x fa5, a06839; RV64ZVE32F-ZVFHMIN-NEXT:    fsh fa5, 0(a1)6840; RV64ZVE32F-ZVFHMIN-NEXT:    ret6841  call void @llvm.masked.scatter.v2f16.v2p0(<2 x half> %val, <2 x ptr> %ptrs, i32 2, <2 x i1> %m)6842  ret void6843}6844 6845define void @mscatter_v4f16(<4 x half> %val, <4 x ptr> %ptrs, <4 x i1> %m) {6846; RV32-LABEL: mscatter_v4f16:6847; RV32:       # %bb.0:6848; RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma6849; RV32-NEXT:    vsoxei32.v v8, (zero), v9, v0.t6850; RV32-NEXT:    ret6851;6852; RV64V-LABEL: mscatter_v4f16:6853; RV64V:       # %bb.0:6854; RV64V-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma6855; RV64V-NEXT:    vsoxei64.v v8, (zero), v10, v0.t6856; RV64V-NEXT:    ret6857;6858; RV64ZVE32F-ZVFH-LABEL: mscatter_v4f16:6859; RV64ZVE32F-ZVFH:       # %bb.0:6860; RV64ZVE32F-ZVFH-NEXT:    ld a4, 8(a0)6861; RV64ZVE32F-ZVFH-NEXT:    ld a2, 16(a0)6862; RV64ZVE32F-ZVFH-NEXT:    ld a1, 24(a0)6863; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e8, m1, ta, ma6864; RV64ZVE32F-ZVFH-NEXT:    vmv.x.s a3, v06865; RV64ZVE32F-ZVFH-NEXT:    andi a5, a3, 16866; RV64ZVE32F-ZVFH-NEXT:    bnez a5, .LBB64_56867; RV64ZVE32F-ZVFH-NEXT:  # %bb.1: # %else6868; RV64ZVE32F-ZVFH-NEXT:    andi a0, a3, 26869; RV64ZVE32F-ZVFH-NEXT:    bnez a0, .LBB64_66870; RV64ZVE32F-ZVFH-NEXT:  .LBB64_2: # %else26871; RV64ZVE32F-ZVFH-NEXT:    andi a0, a3, 46872; RV64ZVE32F-ZVFH-NEXT:    bnez a0, .LBB64_76873; RV64ZVE32F-ZVFH-NEXT:  .LBB64_3: # %else46874; RV64ZVE32F-ZVFH-NEXT:    andi a3, a3, 86875; RV64ZVE32F-ZVFH-NEXT:    bnez a3, .LBB64_86876; RV64ZVE32F-ZVFH-NEXT:  .LBB64_4: # %else66877; RV64ZVE32F-ZVFH-NEXT:    ret6878; RV64ZVE32F-ZVFH-NEXT:  .LBB64_5: # %cond.store6879; RV64ZVE32F-ZVFH-NEXT:    ld a0, 0(a0)6880; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma6881; RV64ZVE32F-ZVFH-NEXT:    vse16.v v8, (a0)6882; RV64ZVE32F-ZVFH-NEXT:    andi a0, a3, 26883; RV64ZVE32F-ZVFH-NEXT:    beqz a0, .LBB64_26884; RV64ZVE32F-ZVFH-NEXT:  .LBB64_6: # %cond.store16885; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma6886; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v9, v8, 16887; RV64ZVE32F-ZVFH-NEXT:    vse16.v v9, (a4)6888; RV64ZVE32F-ZVFH-NEXT:    andi a0, a3, 46889; RV64ZVE32F-ZVFH-NEXT:    beqz a0, .LBB64_36890; RV64ZVE32F-ZVFH-NEXT:  .LBB64_7: # %cond.store36891; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma6892; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v9, v8, 26893; RV64ZVE32F-ZVFH-NEXT:    vse16.v v9, (a2)6894; RV64ZVE32F-ZVFH-NEXT:    andi a3, a3, 86895; RV64ZVE32F-ZVFH-NEXT:    beqz a3, .LBB64_46896; RV64ZVE32F-ZVFH-NEXT:  .LBB64_8: # %cond.store56897; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma6898; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v8, v8, 36899; RV64ZVE32F-ZVFH-NEXT:    vse16.v v8, (a1)6900; RV64ZVE32F-ZVFH-NEXT:    ret6901;6902; RV64ZVE32F-ZVFHMIN-LABEL: mscatter_v4f16:6903; RV64ZVE32F-ZVFHMIN:       # %bb.0:6904; RV64ZVE32F-ZVFHMIN-NEXT:    ld a4, 8(a0)6905; RV64ZVE32F-ZVFHMIN-NEXT:    ld a2, 16(a0)6906; RV64ZVE32F-ZVFHMIN-NEXT:    ld a1, 24(a0)6907; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e8, m1, ta, ma6908; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a3, v06909; RV64ZVE32F-ZVFHMIN-NEXT:    andi a5, a3, 16910; RV64ZVE32F-ZVFHMIN-NEXT:    bnez a5, .LBB64_56911; RV64ZVE32F-ZVFHMIN-NEXT:  # %bb.1: # %else6912; RV64ZVE32F-ZVFHMIN-NEXT:    andi a0, a3, 26913; RV64ZVE32F-ZVFHMIN-NEXT:    bnez a0, .LBB64_66914; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB64_2: # %else26915; RV64ZVE32F-ZVFHMIN-NEXT:    andi a0, a3, 46916; RV64ZVE32F-ZVFHMIN-NEXT:    bnez a0, .LBB64_76917; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB64_3: # %else46918; RV64ZVE32F-ZVFHMIN-NEXT:    andi a3, a3, 86919; RV64ZVE32F-ZVFHMIN-NEXT:    bnez a3, .LBB64_86920; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB64_4: # %else66921; RV64ZVE32F-ZVFHMIN-NEXT:    ret6922; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB64_5: # %cond.store6923; RV64ZVE32F-ZVFHMIN-NEXT:    ld a0, 0(a0)6924; RV64ZVE32F-ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m2, ta, ma6925; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a5, v86926; RV64ZVE32F-ZVFHMIN-NEXT:    fmv.h.x fa5, a56927; RV64ZVE32F-ZVFHMIN-NEXT:    fsh fa5, 0(a0)6928; RV64ZVE32F-ZVFHMIN-NEXT:    andi a0, a3, 26929; RV64ZVE32F-ZVFHMIN-NEXT:    beqz a0, .LBB64_26930; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB64_6: # %cond.store16931; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma6932; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v9, v8, 16933; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a0, v96934; RV64ZVE32F-ZVFHMIN-NEXT:    fmv.h.x fa5, a06935; RV64ZVE32F-ZVFHMIN-NEXT:    fsh fa5, 0(a4)6936; RV64ZVE32F-ZVFHMIN-NEXT:    andi a0, a3, 46937; RV64ZVE32F-ZVFHMIN-NEXT:    beqz a0, .LBB64_36938; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB64_7: # %cond.store36939; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma6940; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v9, v8, 26941; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a0, v96942; RV64ZVE32F-ZVFHMIN-NEXT:    fmv.h.x fa5, a06943; RV64ZVE32F-ZVFHMIN-NEXT:    fsh fa5, 0(a2)6944; RV64ZVE32F-ZVFHMIN-NEXT:    andi a3, a3, 86945; RV64ZVE32F-ZVFHMIN-NEXT:    beqz a3, .LBB64_46946; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB64_8: # %cond.store56947; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma6948; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v8, v8, 36949; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a0, v86950; RV64ZVE32F-ZVFHMIN-NEXT:    fmv.h.x fa5, a06951; RV64ZVE32F-ZVFHMIN-NEXT:    fsh fa5, 0(a1)6952; RV64ZVE32F-ZVFHMIN-NEXT:    ret6953  call void @llvm.masked.scatter.v4f16.v4p0(<4 x half> %val, <4 x ptr> %ptrs, i32 2, <4 x i1> %m)6954  ret void6955}6956 6957define void @mscatter_truemask_v4f16(<4 x half> %val, <4 x ptr> %ptrs) {6958; RV32-LABEL: mscatter_truemask_v4f16:6959; RV32:       # %bb.0:6960; RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma6961; RV32-NEXT:    vsoxei32.v v8, (zero), v96962; RV32-NEXT:    ret6963;6964; RV64V-LABEL: mscatter_truemask_v4f16:6965; RV64V:       # %bb.0:6966; RV64V-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma6967; RV64V-NEXT:    vsoxei64.v v8, (zero), v106968; RV64V-NEXT:    ret6969;6970; RV64ZVE32F-ZVFH-LABEL: mscatter_truemask_v4f16:6971; RV64ZVE32F-ZVFH:       # %bb.0:6972; RV64ZVE32F-ZVFH-NEXT:    ld a1, 0(a0)6973; RV64ZVE32F-ZVFH-NEXT:    ld a2, 8(a0)6974; RV64ZVE32F-ZVFH-NEXT:    ld a3, 16(a0)6975; RV64ZVE32F-ZVFH-NEXT:    ld a0, 24(a0)6976; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma6977; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v9, v8, 16978; RV64ZVE32F-ZVFH-NEXT:    vse16.v v8, (a1)6979; RV64ZVE32F-ZVFH-NEXT:    vse16.v v9, (a2)6980; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v9, v8, 26981; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v8, v8, 36982; RV64ZVE32F-ZVFH-NEXT:    vse16.v v9, (a3)6983; RV64ZVE32F-ZVFH-NEXT:    vse16.v v8, (a0)6984; RV64ZVE32F-ZVFH-NEXT:    ret6985;6986; RV64ZVE32F-ZVFHMIN-LABEL: mscatter_truemask_v4f16:6987; RV64ZVE32F-ZVFHMIN:       # %bb.0:6988; RV64ZVE32F-ZVFHMIN-NEXT:    ld a1, 0(a0)6989; RV64ZVE32F-ZVFHMIN-NEXT:    ld a2, 8(a0)6990; RV64ZVE32F-ZVFHMIN-NEXT:    ld a3, 16(a0)6991; RV64ZVE32F-ZVFHMIN-NEXT:    ld a0, 24(a0)6992; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma6993; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a4, v86994; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v9, v8, 16995; RV64ZVE32F-ZVFHMIN-NEXT:    fmv.h.x fa5, a46996; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a4, v96997; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v9, v8, 26998; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v8, v8, 36999; RV64ZVE32F-ZVFHMIN-NEXT:    fsh fa5, 0(a1)7000; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a1, v97001; RV64ZVE32F-ZVFHMIN-NEXT:    fmv.h.x fa5, a47002; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a4, v87003; RV64ZVE32F-ZVFHMIN-NEXT:    fsh fa5, 0(a2)7004; RV64ZVE32F-ZVFHMIN-NEXT:    fmv.h.x fa5, a17005; RV64ZVE32F-ZVFHMIN-NEXT:    fsh fa5, 0(a3)7006; RV64ZVE32F-ZVFHMIN-NEXT:    fmv.h.x fa5, a47007; RV64ZVE32F-ZVFHMIN-NEXT:    fsh fa5, 0(a0)7008; RV64ZVE32F-ZVFHMIN-NEXT:    ret7009  call void @llvm.masked.scatter.v4f16.v4p0(<4 x half> %val, <4 x ptr> %ptrs, i32 2, <4 x i1> splat (i1 1))7010  ret void7011}7012 7013define void @mscatter_falsemask_v4f16(<4 x half> %val, <4 x ptr> %ptrs) {7014; CHECK-LABEL: mscatter_falsemask_v4f16:7015; CHECK:       # %bb.0:7016; CHECK-NEXT:    ret7017  call void @llvm.masked.scatter.v4f16.v4p0(<4 x half> %val, <4 x ptr> %ptrs, i32 2, <4 x i1> zeroinitializer)7018  ret void7019}7020 7021define void @mscatter_v8f16(<8 x half> %val, <8 x ptr> %ptrs, <8 x i1> %m) {7022; RV32-LABEL: mscatter_v8f16:7023; RV32:       # %bb.0:7024; RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma7025; RV32-NEXT:    vsoxei32.v v8, (zero), v10, v0.t7026; RV32-NEXT:    ret7027;7028; RV64V-LABEL: mscatter_v8f16:7029; RV64V:       # %bb.0:7030; RV64V-NEXT:    vsetivli zero, 8, e16, m1, ta, ma7031; RV64V-NEXT:    vsoxei64.v v8, (zero), v12, v0.t7032; RV64V-NEXT:    ret7033;7034; RV64ZVE32F-ZVFH-LABEL: mscatter_v8f16:7035; RV64ZVE32F-ZVFH:       # %bb.0:7036; RV64ZVE32F-ZVFH-NEXT:    ld a3, 40(a0)7037; RV64ZVE32F-ZVFH-NEXT:    ld a2, 48(a0)7038; RV64ZVE32F-ZVFH-NEXT:    ld a1, 56(a0)7039; RV64ZVE32F-ZVFH-NEXT:    ld t0, 8(a0)7040; RV64ZVE32F-ZVFH-NEXT:    ld a7, 16(a0)7041; RV64ZVE32F-ZVFH-NEXT:    ld a6, 24(a0)7042; RV64ZVE32F-ZVFH-NEXT:    ld a5, 32(a0)7043; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e8, m1, ta, ma7044; RV64ZVE32F-ZVFH-NEXT:    vmv.x.s a4, v07045; RV64ZVE32F-ZVFH-NEXT:    andi t1, a4, 17046; RV64ZVE32F-ZVFH-NEXT:    bnez t1, .LBB67_97047; RV64ZVE32F-ZVFH-NEXT:  # %bb.1: # %else7048; RV64ZVE32F-ZVFH-NEXT:    andi a0, a4, 27049; RV64ZVE32F-ZVFH-NEXT:    bnez a0, .LBB67_107050; RV64ZVE32F-ZVFH-NEXT:  .LBB67_2: # %else27051; RV64ZVE32F-ZVFH-NEXT:    andi a0, a4, 47052; RV64ZVE32F-ZVFH-NEXT:    bnez a0, .LBB67_117053; RV64ZVE32F-ZVFH-NEXT:  .LBB67_3: # %else47054; RV64ZVE32F-ZVFH-NEXT:    andi a0, a4, 87055; RV64ZVE32F-ZVFH-NEXT:    bnez a0, .LBB67_127056; RV64ZVE32F-ZVFH-NEXT:  .LBB67_4: # %else67057; RV64ZVE32F-ZVFH-NEXT:    andi a0, a4, 167058; RV64ZVE32F-ZVFH-NEXT:    bnez a0, .LBB67_137059; RV64ZVE32F-ZVFH-NEXT:  .LBB67_5: # %else87060; RV64ZVE32F-ZVFH-NEXT:    andi a0, a4, 327061; RV64ZVE32F-ZVFH-NEXT:    bnez a0, .LBB67_147062; RV64ZVE32F-ZVFH-NEXT:  .LBB67_6: # %else107063; RV64ZVE32F-ZVFH-NEXT:    andi a0, a4, 647064; RV64ZVE32F-ZVFH-NEXT:    bnez a0, .LBB67_157065; RV64ZVE32F-ZVFH-NEXT:  .LBB67_7: # %else127066; RV64ZVE32F-ZVFH-NEXT:    andi a0, a4, -1287067; RV64ZVE32F-ZVFH-NEXT:    bnez a0, .LBB67_167068; RV64ZVE32F-ZVFH-NEXT:  .LBB67_8: # %else147069; RV64ZVE32F-ZVFH-NEXT:    ret7070; RV64ZVE32F-ZVFH-NEXT:  .LBB67_9: # %cond.store7071; RV64ZVE32F-ZVFH-NEXT:    ld a0, 0(a0)7072; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7073; RV64ZVE32F-ZVFH-NEXT:    vse16.v v8, (a0)7074; RV64ZVE32F-ZVFH-NEXT:    andi a0, a4, 27075; RV64ZVE32F-ZVFH-NEXT:    beqz a0, .LBB67_27076; RV64ZVE32F-ZVFH-NEXT:  .LBB67_10: # %cond.store17077; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7078; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v9, v8, 17079; RV64ZVE32F-ZVFH-NEXT:    vse16.v v9, (t0)7080; RV64ZVE32F-ZVFH-NEXT:    andi a0, a4, 47081; RV64ZVE32F-ZVFH-NEXT:    beqz a0, .LBB67_37082; RV64ZVE32F-ZVFH-NEXT:  .LBB67_11: # %cond.store37083; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7084; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v9, v8, 27085; RV64ZVE32F-ZVFH-NEXT:    vse16.v v9, (a7)7086; RV64ZVE32F-ZVFH-NEXT:    andi a0, a4, 87087; RV64ZVE32F-ZVFH-NEXT:    beqz a0, .LBB67_47088; RV64ZVE32F-ZVFH-NEXT:  .LBB67_12: # %cond.store57089; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7090; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v9, v8, 37091; RV64ZVE32F-ZVFH-NEXT:    vse16.v v9, (a6)7092; RV64ZVE32F-ZVFH-NEXT:    andi a0, a4, 167093; RV64ZVE32F-ZVFH-NEXT:    beqz a0, .LBB67_57094; RV64ZVE32F-ZVFH-NEXT:  .LBB67_13: # %cond.store77095; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7096; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v9, v8, 47097; RV64ZVE32F-ZVFH-NEXT:    vse16.v v9, (a5)7098; RV64ZVE32F-ZVFH-NEXT:    andi a0, a4, 327099; RV64ZVE32F-ZVFH-NEXT:    beqz a0, .LBB67_67100; RV64ZVE32F-ZVFH-NEXT:  .LBB67_14: # %cond.store97101; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7102; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v9, v8, 57103; RV64ZVE32F-ZVFH-NEXT:    vse16.v v9, (a3)7104; RV64ZVE32F-ZVFH-NEXT:    andi a0, a4, 647105; RV64ZVE32F-ZVFH-NEXT:    beqz a0, .LBB67_77106; RV64ZVE32F-ZVFH-NEXT:  .LBB67_15: # %cond.store117107; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7108; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v9, v8, 67109; RV64ZVE32F-ZVFH-NEXT:    vse16.v v9, (a2)7110; RV64ZVE32F-ZVFH-NEXT:    andi a0, a4, -1287111; RV64ZVE32F-ZVFH-NEXT:    beqz a0, .LBB67_87112; RV64ZVE32F-ZVFH-NEXT:  .LBB67_16: # %cond.store137113; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7114; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v8, v8, 77115; RV64ZVE32F-ZVFH-NEXT:    vse16.v v8, (a1)7116; RV64ZVE32F-ZVFH-NEXT:    ret7117;7118; RV64ZVE32F-ZVFHMIN-LABEL: mscatter_v8f16:7119; RV64ZVE32F-ZVFHMIN:       # %bb.0:7120; RV64ZVE32F-ZVFHMIN-NEXT:    ld a3, 40(a0)7121; RV64ZVE32F-ZVFHMIN-NEXT:    ld a2, 48(a0)7122; RV64ZVE32F-ZVFHMIN-NEXT:    ld a1, 56(a0)7123; RV64ZVE32F-ZVFHMIN-NEXT:    ld t0, 8(a0)7124; RV64ZVE32F-ZVFHMIN-NEXT:    ld a7, 16(a0)7125; RV64ZVE32F-ZVFHMIN-NEXT:    ld a6, 24(a0)7126; RV64ZVE32F-ZVFHMIN-NEXT:    ld a5, 32(a0)7127; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e8, m1, ta, ma7128; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a4, v07129; RV64ZVE32F-ZVFHMIN-NEXT:    andi t1, a4, 17130; RV64ZVE32F-ZVFHMIN-NEXT:    bnez t1, .LBB67_97131; RV64ZVE32F-ZVFHMIN-NEXT:  # %bb.1: # %else7132; RV64ZVE32F-ZVFHMIN-NEXT:    andi a0, a4, 27133; RV64ZVE32F-ZVFHMIN-NEXT:    bnez a0, .LBB67_107134; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB67_2: # %else27135; RV64ZVE32F-ZVFHMIN-NEXT:    andi a0, a4, 47136; RV64ZVE32F-ZVFHMIN-NEXT:    bnez a0, .LBB67_117137; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB67_3: # %else47138; RV64ZVE32F-ZVFHMIN-NEXT:    andi a0, a4, 87139; RV64ZVE32F-ZVFHMIN-NEXT:    bnez a0, .LBB67_127140; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB67_4: # %else67141; RV64ZVE32F-ZVFHMIN-NEXT:    andi a0, a4, 167142; RV64ZVE32F-ZVFHMIN-NEXT:    bnez a0, .LBB67_137143; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB67_5: # %else87144; RV64ZVE32F-ZVFHMIN-NEXT:    andi a0, a4, 327145; RV64ZVE32F-ZVFHMIN-NEXT:    bnez a0, .LBB67_147146; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB67_6: # %else107147; RV64ZVE32F-ZVFHMIN-NEXT:    andi a0, a4, 647148; RV64ZVE32F-ZVFHMIN-NEXT:    bnez a0, .LBB67_157149; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB67_7: # %else127150; RV64ZVE32F-ZVFHMIN-NEXT:    andi a0, a4, -1287151; RV64ZVE32F-ZVFHMIN-NEXT:    bnez a0, .LBB67_167152; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB67_8: # %else147153; RV64ZVE32F-ZVFHMIN-NEXT:    ret7154; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB67_9: # %cond.store7155; RV64ZVE32F-ZVFHMIN-NEXT:    ld a0, 0(a0)7156; RV64ZVE32F-ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m2, ta, ma7157; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s t1, v87158; RV64ZVE32F-ZVFHMIN-NEXT:    fmv.h.x fa5, t17159; RV64ZVE32F-ZVFHMIN-NEXT:    fsh fa5, 0(a0)7160; RV64ZVE32F-ZVFHMIN-NEXT:    andi a0, a4, 27161; RV64ZVE32F-ZVFHMIN-NEXT:    beqz a0, .LBB67_27162; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB67_10: # %cond.store17163; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7164; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v9, v8, 17165; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a0, v97166; RV64ZVE32F-ZVFHMIN-NEXT:    fmv.h.x fa5, a07167; RV64ZVE32F-ZVFHMIN-NEXT:    fsh fa5, 0(t0)7168; RV64ZVE32F-ZVFHMIN-NEXT:    andi a0, a4, 47169; RV64ZVE32F-ZVFHMIN-NEXT:    beqz a0, .LBB67_37170; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB67_11: # %cond.store37171; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7172; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v9, v8, 27173; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a0, v97174; RV64ZVE32F-ZVFHMIN-NEXT:    fmv.h.x fa5, a07175; RV64ZVE32F-ZVFHMIN-NEXT:    fsh fa5, 0(a7)7176; RV64ZVE32F-ZVFHMIN-NEXT:    andi a0, a4, 87177; RV64ZVE32F-ZVFHMIN-NEXT:    beqz a0, .LBB67_47178; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB67_12: # %cond.store57179; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7180; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v9, v8, 37181; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a0, v97182; RV64ZVE32F-ZVFHMIN-NEXT:    fmv.h.x fa5, a07183; RV64ZVE32F-ZVFHMIN-NEXT:    fsh fa5, 0(a6)7184; RV64ZVE32F-ZVFHMIN-NEXT:    andi a0, a4, 167185; RV64ZVE32F-ZVFHMIN-NEXT:    beqz a0, .LBB67_57186; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB67_13: # %cond.store77187; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7188; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v9, v8, 47189; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a0, v97190; RV64ZVE32F-ZVFHMIN-NEXT:    fmv.h.x fa5, a07191; RV64ZVE32F-ZVFHMIN-NEXT:    fsh fa5, 0(a5)7192; RV64ZVE32F-ZVFHMIN-NEXT:    andi a0, a4, 327193; RV64ZVE32F-ZVFHMIN-NEXT:    beqz a0, .LBB67_67194; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB67_14: # %cond.store97195; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7196; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v9, v8, 57197; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a0, v97198; RV64ZVE32F-ZVFHMIN-NEXT:    fmv.h.x fa5, a07199; RV64ZVE32F-ZVFHMIN-NEXT:    fsh fa5, 0(a3)7200; RV64ZVE32F-ZVFHMIN-NEXT:    andi a0, a4, 647201; RV64ZVE32F-ZVFHMIN-NEXT:    beqz a0, .LBB67_77202; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB67_15: # %cond.store117203; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7204; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v9, v8, 67205; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a0, v97206; RV64ZVE32F-ZVFHMIN-NEXT:    fmv.h.x fa5, a07207; RV64ZVE32F-ZVFHMIN-NEXT:    fsh fa5, 0(a2)7208; RV64ZVE32F-ZVFHMIN-NEXT:    andi a0, a4, -1287209; RV64ZVE32F-ZVFHMIN-NEXT:    beqz a0, .LBB67_87210; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB67_16: # %cond.store137211; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7212; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v8, v8, 77213; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a0, v87214; RV64ZVE32F-ZVFHMIN-NEXT:    fmv.h.x fa5, a07215; RV64ZVE32F-ZVFHMIN-NEXT:    fsh fa5, 0(a1)7216; RV64ZVE32F-ZVFHMIN-NEXT:    ret7217  call void @llvm.masked.scatter.v8f16.v8p0(<8 x half> %val, <8 x ptr> %ptrs, i32 2, <8 x i1> %m)7218  ret void7219}7220 7221define void @mscatter_baseidx_v8i8_v8f16(<8 x half> %val, ptr %base, <8 x i8> %idxs, <8 x i1> %m) {7222; RV32-LABEL: mscatter_baseidx_v8i8_v8f16:7223; RV32:       # %bb.0:7224; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma7225; RV32-NEXT:    vsext.vf4 v10, v97226; RV32-NEXT:    vadd.vv v10, v10, v107227; RV32-NEXT:    vsetvli zero, zero, e16, m1, ta, ma7228; RV32-NEXT:    vsoxei32.v v8, (a0), v10, v0.t7229; RV32-NEXT:    ret7230;7231; RV64V-LABEL: mscatter_baseidx_v8i8_v8f16:7232; RV64V:       # %bb.0:7233; RV64V-NEXT:    vsetivli zero, 8, e64, m4, ta, ma7234; RV64V-NEXT:    vsext.vf8 v12, v97235; RV64V-NEXT:    vadd.vv v12, v12, v127236; RV64V-NEXT:    vsetvli zero, zero, e16, m1, ta, ma7237; RV64V-NEXT:    vsoxei64.v v8, (a0), v12, v0.t7238; RV64V-NEXT:    ret7239;7240; RV64ZVE32F-ZVFH-LABEL: mscatter_baseidx_v8i8_v8f16:7241; RV64ZVE32F-ZVFH:       # %bb.0:7242; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e8, m1, ta, ma7243; RV64ZVE32F-ZVFH-NEXT:    vmv.x.s a1, v07244; RV64ZVE32F-ZVFH-NEXT:    andi a2, a1, 17245; RV64ZVE32F-ZVFH-NEXT:    beqz a2, .LBB68_27246; RV64ZVE32F-ZVFH-NEXT:  # %bb.1: # %cond.store7247; RV64ZVE32F-ZVFH-NEXT:    vmv.x.s a2, v97248; RV64ZVE32F-ZVFH-NEXT:    slli a2, a2, 17249; RV64ZVE32F-ZVFH-NEXT:    add a2, a0, a27250; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7251; RV64ZVE32F-ZVFH-NEXT:    vse16.v v8, (a2)7252; RV64ZVE32F-ZVFH-NEXT:  .LBB68_2: # %else7253; RV64ZVE32F-ZVFH-NEXT:    andi a2, a1, 27254; RV64ZVE32F-ZVFH-NEXT:    beqz a2, .LBB68_47255; RV64ZVE32F-ZVFH-NEXT:  # %bb.3: # %cond.store17256; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma7257; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v10, v9, 17258; RV64ZVE32F-ZVFH-NEXT:    vmv.x.s a2, v107259; RV64ZVE32F-ZVFH-NEXT:    slli a2, a2, 17260; RV64ZVE32F-ZVFH-NEXT:    add a2, a0, a27261; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7262; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v10, v8, 17263; RV64ZVE32F-ZVFH-NEXT:    vse16.v v10, (a2)7264; RV64ZVE32F-ZVFH-NEXT:  .LBB68_4: # %else27265; RV64ZVE32F-ZVFH-NEXT:    andi a2, a1, 47266; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma7267; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v10, v9, 27268; RV64ZVE32F-ZVFH-NEXT:    beqz a2, .LBB68_67269; RV64ZVE32F-ZVFH-NEXT:  # %bb.5: # %cond.store37270; RV64ZVE32F-ZVFH-NEXT:    vmv.x.s a2, v107271; RV64ZVE32F-ZVFH-NEXT:    slli a2, a2, 17272; RV64ZVE32F-ZVFH-NEXT:    add a2, a0, a27273; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7274; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v11, v8, 27275; RV64ZVE32F-ZVFH-NEXT:    vse16.v v11, (a2)7276; RV64ZVE32F-ZVFH-NEXT:  .LBB68_6: # %else47277; RV64ZVE32F-ZVFH-NEXT:    andi a2, a1, 87278; RV64ZVE32F-ZVFH-NEXT:    beqz a2, .LBB68_87279; RV64ZVE32F-ZVFH-NEXT:  # %bb.7: # %cond.store57280; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma7281; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v10, v10, 17282; RV64ZVE32F-ZVFH-NEXT:    vmv.x.s a2, v107283; RV64ZVE32F-ZVFH-NEXT:    slli a2, a2, 17284; RV64ZVE32F-ZVFH-NEXT:    add a2, a0, a27285; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7286; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v10, v8, 37287; RV64ZVE32F-ZVFH-NEXT:    vse16.v v10, (a2)7288; RV64ZVE32F-ZVFH-NEXT:  .LBB68_8: # %else67289; RV64ZVE32F-ZVFH-NEXT:    andi a2, a1, 167290; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 4, e8, mf2, ta, ma7291; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v9, v9, 47292; RV64ZVE32F-ZVFH-NEXT:    beqz a2, .LBB68_107293; RV64ZVE32F-ZVFH-NEXT:  # %bb.9: # %cond.store77294; RV64ZVE32F-ZVFH-NEXT:    vmv.x.s a2, v97295; RV64ZVE32F-ZVFH-NEXT:    slli a2, a2, 17296; RV64ZVE32F-ZVFH-NEXT:    add a2, a0, a27297; RV64ZVE32F-ZVFH-NEXT:    vsetvli zero, zero, e16, m1, ta, ma7298; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v10, v8, 47299; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7300; RV64ZVE32F-ZVFH-NEXT:    vse16.v v10, (a2)7301; RV64ZVE32F-ZVFH-NEXT:  .LBB68_10: # %else87302; RV64ZVE32F-ZVFH-NEXT:    andi a2, a1, 327303; RV64ZVE32F-ZVFH-NEXT:    beqz a2, .LBB68_127304; RV64ZVE32F-ZVFH-NEXT:  # %bb.11: # %cond.store97305; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma7306; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v10, v9, 17307; RV64ZVE32F-ZVFH-NEXT:    vmv.x.s a2, v107308; RV64ZVE32F-ZVFH-NEXT:    slli a2, a2, 17309; RV64ZVE32F-ZVFH-NEXT:    add a2, a0, a27310; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7311; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v10, v8, 57312; RV64ZVE32F-ZVFH-NEXT:    vse16.v v10, (a2)7313; RV64ZVE32F-ZVFH-NEXT:  .LBB68_12: # %else107314; RV64ZVE32F-ZVFH-NEXT:    andi a2, a1, 647315; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma7316; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v9, v9, 27317; RV64ZVE32F-ZVFH-NEXT:    bnez a2, .LBB68_157318; RV64ZVE32F-ZVFH-NEXT:  # %bb.13: # %else127319; RV64ZVE32F-ZVFH-NEXT:    andi a1, a1, -1287320; RV64ZVE32F-ZVFH-NEXT:    bnez a1, .LBB68_167321; RV64ZVE32F-ZVFH-NEXT:  .LBB68_14: # %else147322; RV64ZVE32F-ZVFH-NEXT:    ret7323; RV64ZVE32F-ZVFH-NEXT:  .LBB68_15: # %cond.store117324; RV64ZVE32F-ZVFH-NEXT:    vmv.x.s a2, v97325; RV64ZVE32F-ZVFH-NEXT:    slli a2, a2, 17326; RV64ZVE32F-ZVFH-NEXT:    add a2, a0, a27327; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7328; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v10, v8, 67329; RV64ZVE32F-ZVFH-NEXT:    vse16.v v10, (a2)7330; RV64ZVE32F-ZVFH-NEXT:    andi a1, a1, -1287331; RV64ZVE32F-ZVFH-NEXT:    beqz a1, .LBB68_147332; RV64ZVE32F-ZVFH-NEXT:  .LBB68_16: # %cond.store137333; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma7334; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v9, v9, 17335; RV64ZVE32F-ZVFH-NEXT:    vmv.x.s a1, v97336; RV64ZVE32F-ZVFH-NEXT:    slli a1, a1, 17337; RV64ZVE32F-ZVFH-NEXT:    add a0, a0, a17338; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7339; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v8, v8, 77340; RV64ZVE32F-ZVFH-NEXT:    vse16.v v8, (a0)7341; RV64ZVE32F-ZVFH-NEXT:    ret7342;7343; RV64ZVE32F-ZVFHMIN-LABEL: mscatter_baseidx_v8i8_v8f16:7344; RV64ZVE32F-ZVFHMIN:       # %bb.0:7345; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e8, m1, ta, ma7346; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a1, v07347; RV64ZVE32F-ZVFHMIN-NEXT:    andi a2, a1, 17348; RV64ZVE32F-ZVFHMIN-NEXT:    beqz a2, .LBB68_27349; RV64ZVE32F-ZVFHMIN-NEXT:  # %bb.1: # %cond.store7350; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a2, v97351; RV64ZVE32F-ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m2, ta, ma7352; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a3, v87353; RV64ZVE32F-ZVFHMIN-NEXT:    slli a2, a2, 17354; RV64ZVE32F-ZVFHMIN-NEXT:    add a2, a0, a27355; RV64ZVE32F-ZVFHMIN-NEXT:    fmv.h.x fa5, a37356; RV64ZVE32F-ZVFHMIN-NEXT:    fsh fa5, 0(a2)7357; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB68_2: # %else7358; RV64ZVE32F-ZVFHMIN-NEXT:    andi a2, a1, 27359; RV64ZVE32F-ZVFHMIN-NEXT:    beqz a2, .LBB68_47360; RV64ZVE32F-ZVFHMIN-NEXT:  # %bb.3: # %cond.store17361; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma7362; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v10, v9, 17363; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a2, v107364; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7365; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v10, v8, 17366; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a3, v107367; RV64ZVE32F-ZVFHMIN-NEXT:    slli a2, a2, 17368; RV64ZVE32F-ZVFHMIN-NEXT:    add a2, a0, a27369; RV64ZVE32F-ZVFHMIN-NEXT:    fmv.h.x fa5, a37370; RV64ZVE32F-ZVFHMIN-NEXT:    fsh fa5, 0(a2)7371; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB68_4: # %else27372; RV64ZVE32F-ZVFHMIN-NEXT:    andi a2, a1, 47373; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma7374; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v10, v9, 27375; RV64ZVE32F-ZVFHMIN-NEXT:    beqz a2, .LBB68_67376; RV64ZVE32F-ZVFHMIN-NEXT:  # %bb.5: # %cond.store37377; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a2, v107378; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7379; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v11, v8, 27380; RV64ZVE32F-ZVFHMIN-NEXT:    slli a2, a2, 17381; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a3, v117382; RV64ZVE32F-ZVFHMIN-NEXT:    add a2, a0, a27383; RV64ZVE32F-ZVFHMIN-NEXT:    fmv.h.x fa5, a37384; RV64ZVE32F-ZVFHMIN-NEXT:    fsh fa5, 0(a2)7385; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB68_6: # %else47386; RV64ZVE32F-ZVFHMIN-NEXT:    andi a2, a1, 87387; RV64ZVE32F-ZVFHMIN-NEXT:    beqz a2, .LBB68_87388; RV64ZVE32F-ZVFHMIN-NEXT:  # %bb.7: # %cond.store57389; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma7390; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v10, v10, 17391; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a2, v107392; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7393; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v10, v8, 37394; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a3, v107395; RV64ZVE32F-ZVFHMIN-NEXT:    slli a2, a2, 17396; RV64ZVE32F-ZVFHMIN-NEXT:    add a2, a0, a27397; RV64ZVE32F-ZVFHMIN-NEXT:    fmv.h.x fa5, a37398; RV64ZVE32F-ZVFHMIN-NEXT:    fsh fa5, 0(a2)7399; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB68_8: # %else67400; RV64ZVE32F-ZVFHMIN-NEXT:    andi a2, a1, 167401; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 4, e8, mf2, ta, ma7402; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v9, v9, 47403; RV64ZVE32F-ZVFHMIN-NEXT:    beqz a2, .LBB68_107404; RV64ZVE32F-ZVFHMIN-NEXT:  # %bb.9: # %cond.store77405; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a2, v97406; RV64ZVE32F-ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m1, ta, ma7407; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v10, v8, 47408; RV64ZVE32F-ZVFHMIN-NEXT:    slli a2, a2, 17409; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a3, v107410; RV64ZVE32F-ZVFHMIN-NEXT:    add a2, a0, a27411; RV64ZVE32F-ZVFHMIN-NEXT:    fmv.h.x fa5, a37412; RV64ZVE32F-ZVFHMIN-NEXT:    fsh fa5, 0(a2)7413; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB68_10: # %else87414; RV64ZVE32F-ZVFHMIN-NEXT:    andi a2, a1, 327415; RV64ZVE32F-ZVFHMIN-NEXT:    beqz a2, .LBB68_127416; RV64ZVE32F-ZVFHMIN-NEXT:  # %bb.11: # %cond.store97417; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma7418; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v10, v9, 17419; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a2, v107420; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7421; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v10, v8, 57422; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a3, v107423; RV64ZVE32F-ZVFHMIN-NEXT:    slli a2, a2, 17424; RV64ZVE32F-ZVFHMIN-NEXT:    add a2, a0, a27425; RV64ZVE32F-ZVFHMIN-NEXT:    fmv.h.x fa5, a37426; RV64ZVE32F-ZVFHMIN-NEXT:    fsh fa5, 0(a2)7427; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB68_12: # %else107428; RV64ZVE32F-ZVFHMIN-NEXT:    andi a2, a1, 647429; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma7430; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v9, v9, 27431; RV64ZVE32F-ZVFHMIN-NEXT:    bnez a2, .LBB68_157432; RV64ZVE32F-ZVFHMIN-NEXT:  # %bb.13: # %else127433; RV64ZVE32F-ZVFHMIN-NEXT:    andi a1, a1, -1287434; RV64ZVE32F-ZVFHMIN-NEXT:    bnez a1, .LBB68_167435; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB68_14: # %else147436; RV64ZVE32F-ZVFHMIN-NEXT:    ret7437; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB68_15: # %cond.store117438; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a2, v97439; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7440; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v10, v8, 67441; RV64ZVE32F-ZVFHMIN-NEXT:    slli a2, a2, 17442; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a3, v107443; RV64ZVE32F-ZVFHMIN-NEXT:    add a2, a0, a27444; RV64ZVE32F-ZVFHMIN-NEXT:    fmv.h.x fa5, a37445; RV64ZVE32F-ZVFHMIN-NEXT:    fsh fa5, 0(a2)7446; RV64ZVE32F-ZVFHMIN-NEXT:    andi a1, a1, -1287447; RV64ZVE32F-ZVFHMIN-NEXT:    beqz a1, .LBB68_147448; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB68_16: # %cond.store137449; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma7450; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v9, v9, 17451; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7452; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v8, v8, 77453; RV64ZVE32F-ZVFHMIN-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma7454; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a1, v97455; RV64ZVE32F-ZVFHMIN-NEXT:    slli a1, a1, 17456; RV64ZVE32F-ZVFHMIN-NEXT:    add a0, a0, a17457; RV64ZVE32F-ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m1, ta, ma7458; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a1, v87459; RV64ZVE32F-ZVFHMIN-NEXT:    fmv.h.x fa5, a17460; RV64ZVE32F-ZVFHMIN-NEXT:    fsh fa5, 0(a0)7461; RV64ZVE32F-ZVFHMIN-NEXT:    ret7462  %ptrs = getelementptr inbounds half, ptr %base, <8 x i8> %idxs7463  call void @llvm.masked.scatter.v8f16.v8p0(<8 x half> %val, <8 x ptr> %ptrs, i32 2, <8 x i1> %m)7464  ret void7465}7466 7467define void @mscatter_baseidx_sext_v8i8_v8f16(<8 x half> %val, ptr %base, <8 x i8> %idxs, <8 x i1> %m) {7468; RV32-LABEL: mscatter_baseidx_sext_v8i8_v8f16:7469; RV32:       # %bb.0:7470; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma7471; RV32-NEXT:    vsext.vf4 v10, v97472; RV32-NEXT:    vadd.vv v10, v10, v107473; RV32-NEXT:    vsetvli zero, zero, e16, m1, ta, ma7474; RV32-NEXT:    vsoxei32.v v8, (a0), v10, v0.t7475; RV32-NEXT:    ret7476;7477; RV64V-LABEL: mscatter_baseidx_sext_v8i8_v8f16:7478; RV64V:       # %bb.0:7479; RV64V-NEXT:    vsetivli zero, 8, e64, m4, ta, ma7480; RV64V-NEXT:    vsext.vf8 v12, v97481; RV64V-NEXT:    vadd.vv v12, v12, v127482; RV64V-NEXT:    vsetvli zero, zero, e16, m1, ta, ma7483; RV64V-NEXT:    vsoxei64.v v8, (a0), v12, v0.t7484; RV64V-NEXT:    ret7485;7486; RV64ZVE32F-ZVFH-LABEL: mscatter_baseidx_sext_v8i8_v8f16:7487; RV64ZVE32F-ZVFH:       # %bb.0:7488; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e8, m1, ta, ma7489; RV64ZVE32F-ZVFH-NEXT:    vmv.x.s a1, v07490; RV64ZVE32F-ZVFH-NEXT:    andi a2, a1, 17491; RV64ZVE32F-ZVFH-NEXT:    beqz a2, .LBB69_27492; RV64ZVE32F-ZVFH-NEXT:  # %bb.1: # %cond.store7493; RV64ZVE32F-ZVFH-NEXT:    vmv.x.s a2, v97494; RV64ZVE32F-ZVFH-NEXT:    slli a2, a2, 17495; RV64ZVE32F-ZVFH-NEXT:    add a2, a0, a27496; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7497; RV64ZVE32F-ZVFH-NEXT:    vse16.v v8, (a2)7498; RV64ZVE32F-ZVFH-NEXT:  .LBB69_2: # %else7499; RV64ZVE32F-ZVFH-NEXT:    andi a2, a1, 27500; RV64ZVE32F-ZVFH-NEXT:    beqz a2, .LBB69_47501; RV64ZVE32F-ZVFH-NEXT:  # %bb.3: # %cond.store17502; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma7503; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v10, v9, 17504; RV64ZVE32F-ZVFH-NEXT:    vmv.x.s a2, v107505; RV64ZVE32F-ZVFH-NEXT:    slli a2, a2, 17506; RV64ZVE32F-ZVFH-NEXT:    add a2, a0, a27507; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7508; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v10, v8, 17509; RV64ZVE32F-ZVFH-NEXT:    vse16.v v10, (a2)7510; RV64ZVE32F-ZVFH-NEXT:  .LBB69_4: # %else27511; RV64ZVE32F-ZVFH-NEXT:    andi a2, a1, 47512; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma7513; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v10, v9, 27514; RV64ZVE32F-ZVFH-NEXT:    beqz a2, .LBB69_67515; RV64ZVE32F-ZVFH-NEXT:  # %bb.5: # %cond.store37516; RV64ZVE32F-ZVFH-NEXT:    vmv.x.s a2, v107517; RV64ZVE32F-ZVFH-NEXT:    slli a2, a2, 17518; RV64ZVE32F-ZVFH-NEXT:    add a2, a0, a27519; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7520; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v11, v8, 27521; RV64ZVE32F-ZVFH-NEXT:    vse16.v v11, (a2)7522; RV64ZVE32F-ZVFH-NEXT:  .LBB69_6: # %else47523; RV64ZVE32F-ZVFH-NEXT:    andi a2, a1, 87524; RV64ZVE32F-ZVFH-NEXT:    beqz a2, .LBB69_87525; RV64ZVE32F-ZVFH-NEXT:  # %bb.7: # %cond.store57526; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma7527; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v10, v10, 17528; RV64ZVE32F-ZVFH-NEXT:    vmv.x.s a2, v107529; RV64ZVE32F-ZVFH-NEXT:    slli a2, a2, 17530; RV64ZVE32F-ZVFH-NEXT:    add a2, a0, a27531; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7532; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v10, v8, 37533; RV64ZVE32F-ZVFH-NEXT:    vse16.v v10, (a2)7534; RV64ZVE32F-ZVFH-NEXT:  .LBB69_8: # %else67535; RV64ZVE32F-ZVFH-NEXT:    andi a2, a1, 167536; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 4, e8, mf2, ta, ma7537; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v9, v9, 47538; RV64ZVE32F-ZVFH-NEXT:    beqz a2, .LBB69_107539; RV64ZVE32F-ZVFH-NEXT:  # %bb.9: # %cond.store77540; RV64ZVE32F-ZVFH-NEXT:    vmv.x.s a2, v97541; RV64ZVE32F-ZVFH-NEXT:    slli a2, a2, 17542; RV64ZVE32F-ZVFH-NEXT:    add a2, a0, a27543; RV64ZVE32F-ZVFH-NEXT:    vsetvli zero, zero, e16, m1, ta, ma7544; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v10, v8, 47545; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7546; RV64ZVE32F-ZVFH-NEXT:    vse16.v v10, (a2)7547; RV64ZVE32F-ZVFH-NEXT:  .LBB69_10: # %else87548; RV64ZVE32F-ZVFH-NEXT:    andi a2, a1, 327549; RV64ZVE32F-ZVFH-NEXT:    beqz a2, .LBB69_127550; RV64ZVE32F-ZVFH-NEXT:  # %bb.11: # %cond.store97551; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma7552; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v10, v9, 17553; RV64ZVE32F-ZVFH-NEXT:    vmv.x.s a2, v107554; RV64ZVE32F-ZVFH-NEXT:    slli a2, a2, 17555; RV64ZVE32F-ZVFH-NEXT:    add a2, a0, a27556; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7557; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v10, v8, 57558; RV64ZVE32F-ZVFH-NEXT:    vse16.v v10, (a2)7559; RV64ZVE32F-ZVFH-NEXT:  .LBB69_12: # %else107560; RV64ZVE32F-ZVFH-NEXT:    andi a2, a1, 647561; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma7562; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v9, v9, 27563; RV64ZVE32F-ZVFH-NEXT:    bnez a2, .LBB69_157564; RV64ZVE32F-ZVFH-NEXT:  # %bb.13: # %else127565; RV64ZVE32F-ZVFH-NEXT:    andi a1, a1, -1287566; RV64ZVE32F-ZVFH-NEXT:    bnez a1, .LBB69_167567; RV64ZVE32F-ZVFH-NEXT:  .LBB69_14: # %else147568; RV64ZVE32F-ZVFH-NEXT:    ret7569; RV64ZVE32F-ZVFH-NEXT:  .LBB69_15: # %cond.store117570; RV64ZVE32F-ZVFH-NEXT:    vmv.x.s a2, v97571; RV64ZVE32F-ZVFH-NEXT:    slli a2, a2, 17572; RV64ZVE32F-ZVFH-NEXT:    add a2, a0, a27573; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7574; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v10, v8, 67575; RV64ZVE32F-ZVFH-NEXT:    vse16.v v10, (a2)7576; RV64ZVE32F-ZVFH-NEXT:    andi a1, a1, -1287577; RV64ZVE32F-ZVFH-NEXT:    beqz a1, .LBB69_147578; RV64ZVE32F-ZVFH-NEXT:  .LBB69_16: # %cond.store137579; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma7580; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v9, v9, 17581; RV64ZVE32F-ZVFH-NEXT:    vmv.x.s a1, v97582; RV64ZVE32F-ZVFH-NEXT:    slli a1, a1, 17583; RV64ZVE32F-ZVFH-NEXT:    add a0, a0, a17584; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7585; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v8, v8, 77586; RV64ZVE32F-ZVFH-NEXT:    vse16.v v8, (a0)7587; RV64ZVE32F-ZVFH-NEXT:    ret7588;7589; RV64ZVE32F-ZVFHMIN-LABEL: mscatter_baseidx_sext_v8i8_v8f16:7590; RV64ZVE32F-ZVFHMIN:       # %bb.0:7591; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e8, m1, ta, ma7592; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a1, v07593; RV64ZVE32F-ZVFHMIN-NEXT:    andi a2, a1, 17594; RV64ZVE32F-ZVFHMIN-NEXT:    beqz a2, .LBB69_27595; RV64ZVE32F-ZVFHMIN-NEXT:  # %bb.1: # %cond.store7596; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a2, v97597; RV64ZVE32F-ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m2, ta, ma7598; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a3, v87599; RV64ZVE32F-ZVFHMIN-NEXT:    slli a2, a2, 17600; RV64ZVE32F-ZVFHMIN-NEXT:    add a2, a0, a27601; RV64ZVE32F-ZVFHMIN-NEXT:    fmv.h.x fa5, a37602; RV64ZVE32F-ZVFHMIN-NEXT:    fsh fa5, 0(a2)7603; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB69_2: # %else7604; RV64ZVE32F-ZVFHMIN-NEXT:    andi a2, a1, 27605; RV64ZVE32F-ZVFHMIN-NEXT:    beqz a2, .LBB69_47606; RV64ZVE32F-ZVFHMIN-NEXT:  # %bb.3: # %cond.store17607; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma7608; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v10, v9, 17609; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a2, v107610; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7611; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v10, v8, 17612; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a3, v107613; RV64ZVE32F-ZVFHMIN-NEXT:    slli a2, a2, 17614; RV64ZVE32F-ZVFHMIN-NEXT:    add a2, a0, a27615; RV64ZVE32F-ZVFHMIN-NEXT:    fmv.h.x fa5, a37616; RV64ZVE32F-ZVFHMIN-NEXT:    fsh fa5, 0(a2)7617; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB69_4: # %else27618; RV64ZVE32F-ZVFHMIN-NEXT:    andi a2, a1, 47619; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma7620; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v10, v9, 27621; RV64ZVE32F-ZVFHMIN-NEXT:    beqz a2, .LBB69_67622; RV64ZVE32F-ZVFHMIN-NEXT:  # %bb.5: # %cond.store37623; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a2, v107624; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7625; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v11, v8, 27626; RV64ZVE32F-ZVFHMIN-NEXT:    slli a2, a2, 17627; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a3, v117628; RV64ZVE32F-ZVFHMIN-NEXT:    add a2, a0, a27629; RV64ZVE32F-ZVFHMIN-NEXT:    fmv.h.x fa5, a37630; RV64ZVE32F-ZVFHMIN-NEXT:    fsh fa5, 0(a2)7631; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB69_6: # %else47632; RV64ZVE32F-ZVFHMIN-NEXT:    andi a2, a1, 87633; RV64ZVE32F-ZVFHMIN-NEXT:    beqz a2, .LBB69_87634; RV64ZVE32F-ZVFHMIN-NEXT:  # %bb.7: # %cond.store57635; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma7636; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v10, v10, 17637; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a2, v107638; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7639; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v10, v8, 37640; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a3, v107641; RV64ZVE32F-ZVFHMIN-NEXT:    slli a2, a2, 17642; RV64ZVE32F-ZVFHMIN-NEXT:    add a2, a0, a27643; RV64ZVE32F-ZVFHMIN-NEXT:    fmv.h.x fa5, a37644; RV64ZVE32F-ZVFHMIN-NEXT:    fsh fa5, 0(a2)7645; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB69_8: # %else67646; RV64ZVE32F-ZVFHMIN-NEXT:    andi a2, a1, 167647; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 4, e8, mf2, ta, ma7648; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v9, v9, 47649; RV64ZVE32F-ZVFHMIN-NEXT:    beqz a2, .LBB69_107650; RV64ZVE32F-ZVFHMIN-NEXT:  # %bb.9: # %cond.store77651; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a2, v97652; RV64ZVE32F-ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m1, ta, ma7653; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v10, v8, 47654; RV64ZVE32F-ZVFHMIN-NEXT:    slli a2, a2, 17655; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a3, v107656; RV64ZVE32F-ZVFHMIN-NEXT:    add a2, a0, a27657; RV64ZVE32F-ZVFHMIN-NEXT:    fmv.h.x fa5, a37658; RV64ZVE32F-ZVFHMIN-NEXT:    fsh fa5, 0(a2)7659; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB69_10: # %else87660; RV64ZVE32F-ZVFHMIN-NEXT:    andi a2, a1, 327661; RV64ZVE32F-ZVFHMIN-NEXT:    beqz a2, .LBB69_127662; RV64ZVE32F-ZVFHMIN-NEXT:  # %bb.11: # %cond.store97663; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma7664; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v10, v9, 17665; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a2, v107666; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7667; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v10, v8, 57668; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a3, v107669; RV64ZVE32F-ZVFHMIN-NEXT:    slli a2, a2, 17670; RV64ZVE32F-ZVFHMIN-NEXT:    add a2, a0, a27671; RV64ZVE32F-ZVFHMIN-NEXT:    fmv.h.x fa5, a37672; RV64ZVE32F-ZVFHMIN-NEXT:    fsh fa5, 0(a2)7673; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB69_12: # %else107674; RV64ZVE32F-ZVFHMIN-NEXT:    andi a2, a1, 647675; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma7676; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v9, v9, 27677; RV64ZVE32F-ZVFHMIN-NEXT:    bnez a2, .LBB69_157678; RV64ZVE32F-ZVFHMIN-NEXT:  # %bb.13: # %else127679; RV64ZVE32F-ZVFHMIN-NEXT:    andi a1, a1, -1287680; RV64ZVE32F-ZVFHMIN-NEXT:    bnez a1, .LBB69_167681; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB69_14: # %else147682; RV64ZVE32F-ZVFHMIN-NEXT:    ret7683; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB69_15: # %cond.store117684; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a2, v97685; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7686; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v10, v8, 67687; RV64ZVE32F-ZVFHMIN-NEXT:    slli a2, a2, 17688; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a3, v107689; RV64ZVE32F-ZVFHMIN-NEXT:    add a2, a0, a27690; RV64ZVE32F-ZVFHMIN-NEXT:    fmv.h.x fa5, a37691; RV64ZVE32F-ZVFHMIN-NEXT:    fsh fa5, 0(a2)7692; RV64ZVE32F-ZVFHMIN-NEXT:    andi a1, a1, -1287693; RV64ZVE32F-ZVFHMIN-NEXT:    beqz a1, .LBB69_147694; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB69_16: # %cond.store137695; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma7696; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v9, v9, 17697; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7698; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v8, v8, 77699; RV64ZVE32F-ZVFHMIN-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma7700; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a1, v97701; RV64ZVE32F-ZVFHMIN-NEXT:    slli a1, a1, 17702; RV64ZVE32F-ZVFHMIN-NEXT:    add a0, a0, a17703; RV64ZVE32F-ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m1, ta, ma7704; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a1, v87705; RV64ZVE32F-ZVFHMIN-NEXT:    fmv.h.x fa5, a17706; RV64ZVE32F-ZVFHMIN-NEXT:    fsh fa5, 0(a0)7707; RV64ZVE32F-ZVFHMIN-NEXT:    ret7708  %eidxs = sext <8 x i8> %idxs to <8 x i16>7709  %ptrs = getelementptr inbounds half, ptr %base, <8 x i16> %eidxs7710  call void @llvm.masked.scatter.v8f16.v8p0(<8 x half> %val, <8 x ptr> %ptrs, i32 2, <8 x i1> %m)7711  ret void7712}7713 7714define void @mscatter_baseidx_zext_v8i8_v8f16(<8 x half> %val, ptr %base, <8 x i8> %idxs, <8 x i1> %m) {7715; RV32-LABEL: mscatter_baseidx_zext_v8i8_v8f16:7716; RV32:       # %bb.0:7717; RV32-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma7718; RV32-NEXT:    vwaddu.vv v10, v9, v97719; RV32-NEXT:    vsetvli zero, zero, e16, m1, ta, ma7720; RV32-NEXT:    vsoxei16.v v8, (a0), v10, v0.t7721; RV32-NEXT:    ret7722;7723; RV64V-LABEL: mscatter_baseidx_zext_v8i8_v8f16:7724; RV64V:       # %bb.0:7725; RV64V-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma7726; RV64V-NEXT:    vwaddu.vv v10, v9, v97727; RV64V-NEXT:    vsetvli zero, zero, e16, m1, ta, ma7728; RV64V-NEXT:    vsoxei16.v v8, (a0), v10, v0.t7729; RV64V-NEXT:    ret7730;7731; RV64ZVE32F-ZVFH-LABEL: mscatter_baseidx_zext_v8i8_v8f16:7732; RV64ZVE32F-ZVFH:       # %bb.0:7733; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e8, m1, ta, ma7734; RV64ZVE32F-ZVFH-NEXT:    vmv.x.s a1, v07735; RV64ZVE32F-ZVFH-NEXT:    andi a2, a1, 17736; RV64ZVE32F-ZVFH-NEXT:    beqz a2, .LBB70_27737; RV64ZVE32F-ZVFH-NEXT:  # %bb.1: # %cond.store7738; RV64ZVE32F-ZVFH-NEXT:    vmv.x.s a2, v97739; RV64ZVE32F-ZVFH-NEXT:    zext.b a2, a27740; RV64ZVE32F-ZVFH-NEXT:    slli a2, a2, 17741; RV64ZVE32F-ZVFH-NEXT:    add a2, a0, a27742; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7743; RV64ZVE32F-ZVFH-NEXT:    vse16.v v8, (a2)7744; RV64ZVE32F-ZVFH-NEXT:  .LBB70_2: # %else7745; RV64ZVE32F-ZVFH-NEXT:    andi a2, a1, 27746; RV64ZVE32F-ZVFH-NEXT:    beqz a2, .LBB70_47747; RV64ZVE32F-ZVFH-NEXT:  # %bb.3: # %cond.store17748; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma7749; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v10, v9, 17750; RV64ZVE32F-ZVFH-NEXT:    vmv.x.s a2, v107751; RV64ZVE32F-ZVFH-NEXT:    zext.b a2, a27752; RV64ZVE32F-ZVFH-NEXT:    slli a2, a2, 17753; RV64ZVE32F-ZVFH-NEXT:    add a2, a0, a27754; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7755; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v10, v8, 17756; RV64ZVE32F-ZVFH-NEXT:    vse16.v v10, (a2)7757; RV64ZVE32F-ZVFH-NEXT:  .LBB70_4: # %else27758; RV64ZVE32F-ZVFH-NEXT:    andi a2, a1, 47759; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma7760; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v10, v9, 27761; RV64ZVE32F-ZVFH-NEXT:    beqz a2, .LBB70_67762; RV64ZVE32F-ZVFH-NEXT:  # %bb.5: # %cond.store37763; RV64ZVE32F-ZVFH-NEXT:    vmv.x.s a2, v107764; RV64ZVE32F-ZVFH-NEXT:    zext.b a2, a27765; RV64ZVE32F-ZVFH-NEXT:    slli a2, a2, 17766; RV64ZVE32F-ZVFH-NEXT:    add a2, a0, a27767; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7768; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v11, v8, 27769; RV64ZVE32F-ZVFH-NEXT:    vse16.v v11, (a2)7770; RV64ZVE32F-ZVFH-NEXT:  .LBB70_6: # %else47771; RV64ZVE32F-ZVFH-NEXT:    andi a2, a1, 87772; RV64ZVE32F-ZVFH-NEXT:    beqz a2, .LBB70_87773; RV64ZVE32F-ZVFH-NEXT:  # %bb.7: # %cond.store57774; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma7775; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v10, v10, 17776; RV64ZVE32F-ZVFH-NEXT:    vmv.x.s a2, v107777; RV64ZVE32F-ZVFH-NEXT:    zext.b a2, a27778; RV64ZVE32F-ZVFH-NEXT:    slli a2, a2, 17779; RV64ZVE32F-ZVFH-NEXT:    add a2, a0, a27780; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7781; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v10, v8, 37782; RV64ZVE32F-ZVFH-NEXT:    vse16.v v10, (a2)7783; RV64ZVE32F-ZVFH-NEXT:  .LBB70_8: # %else67784; RV64ZVE32F-ZVFH-NEXT:    andi a2, a1, 167785; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 4, e8, mf2, ta, ma7786; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v9, v9, 47787; RV64ZVE32F-ZVFH-NEXT:    beqz a2, .LBB70_107788; RV64ZVE32F-ZVFH-NEXT:  # %bb.9: # %cond.store77789; RV64ZVE32F-ZVFH-NEXT:    vmv.x.s a2, v97790; RV64ZVE32F-ZVFH-NEXT:    zext.b a2, a27791; RV64ZVE32F-ZVFH-NEXT:    slli a2, a2, 17792; RV64ZVE32F-ZVFH-NEXT:    add a2, a0, a27793; RV64ZVE32F-ZVFH-NEXT:    vsetvli zero, zero, e16, m1, ta, ma7794; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v10, v8, 47795; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7796; RV64ZVE32F-ZVFH-NEXT:    vse16.v v10, (a2)7797; RV64ZVE32F-ZVFH-NEXT:  .LBB70_10: # %else87798; RV64ZVE32F-ZVFH-NEXT:    andi a2, a1, 327799; RV64ZVE32F-ZVFH-NEXT:    beqz a2, .LBB70_127800; RV64ZVE32F-ZVFH-NEXT:  # %bb.11: # %cond.store97801; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma7802; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v10, v9, 17803; RV64ZVE32F-ZVFH-NEXT:    vmv.x.s a2, v107804; RV64ZVE32F-ZVFH-NEXT:    zext.b a2, a27805; RV64ZVE32F-ZVFH-NEXT:    slli a2, a2, 17806; RV64ZVE32F-ZVFH-NEXT:    add a2, a0, a27807; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7808; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v10, v8, 57809; RV64ZVE32F-ZVFH-NEXT:    vse16.v v10, (a2)7810; RV64ZVE32F-ZVFH-NEXT:  .LBB70_12: # %else107811; RV64ZVE32F-ZVFH-NEXT:    andi a2, a1, 647812; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma7813; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v9, v9, 27814; RV64ZVE32F-ZVFH-NEXT:    bnez a2, .LBB70_157815; RV64ZVE32F-ZVFH-NEXT:  # %bb.13: # %else127816; RV64ZVE32F-ZVFH-NEXT:    andi a1, a1, -1287817; RV64ZVE32F-ZVFH-NEXT:    bnez a1, .LBB70_167818; RV64ZVE32F-ZVFH-NEXT:  .LBB70_14: # %else147819; RV64ZVE32F-ZVFH-NEXT:    ret7820; RV64ZVE32F-ZVFH-NEXT:  .LBB70_15: # %cond.store117821; RV64ZVE32F-ZVFH-NEXT:    vmv.x.s a2, v97822; RV64ZVE32F-ZVFH-NEXT:    zext.b a2, a27823; RV64ZVE32F-ZVFH-NEXT:    slli a2, a2, 17824; RV64ZVE32F-ZVFH-NEXT:    add a2, a0, a27825; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7826; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v10, v8, 67827; RV64ZVE32F-ZVFH-NEXT:    vse16.v v10, (a2)7828; RV64ZVE32F-ZVFH-NEXT:    andi a1, a1, -1287829; RV64ZVE32F-ZVFH-NEXT:    beqz a1, .LBB70_147830; RV64ZVE32F-ZVFH-NEXT:  .LBB70_16: # %cond.store137831; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma7832; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v9, v9, 17833; RV64ZVE32F-ZVFH-NEXT:    vmv.x.s a1, v97834; RV64ZVE32F-ZVFH-NEXT:    zext.b a1, a17835; RV64ZVE32F-ZVFH-NEXT:    slli a1, a1, 17836; RV64ZVE32F-ZVFH-NEXT:    add a0, a0, a17837; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7838; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v8, v8, 77839; RV64ZVE32F-ZVFH-NEXT:    vse16.v v8, (a0)7840; RV64ZVE32F-ZVFH-NEXT:    ret7841;7842; RV64ZVE32F-ZVFHMIN-LABEL: mscatter_baseidx_zext_v8i8_v8f16:7843; RV64ZVE32F-ZVFHMIN:       # %bb.0:7844; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e8, m1, ta, ma7845; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a1, v07846; RV64ZVE32F-ZVFHMIN-NEXT:    andi a2, a1, 17847; RV64ZVE32F-ZVFHMIN-NEXT:    beqz a2, .LBB70_27848; RV64ZVE32F-ZVFHMIN-NEXT:  # %bb.1: # %cond.store7849; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a2, v97850; RV64ZVE32F-ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m2, ta, ma7851; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a3, v87852; RV64ZVE32F-ZVFHMIN-NEXT:    zext.b a2, a27853; RV64ZVE32F-ZVFHMIN-NEXT:    slli a2, a2, 17854; RV64ZVE32F-ZVFHMIN-NEXT:    add a2, a0, a27855; RV64ZVE32F-ZVFHMIN-NEXT:    fmv.h.x fa5, a37856; RV64ZVE32F-ZVFHMIN-NEXT:    fsh fa5, 0(a2)7857; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB70_2: # %else7858; RV64ZVE32F-ZVFHMIN-NEXT:    andi a2, a1, 27859; RV64ZVE32F-ZVFHMIN-NEXT:    beqz a2, .LBB70_47860; RV64ZVE32F-ZVFHMIN-NEXT:  # %bb.3: # %cond.store17861; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma7862; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v10, v9, 17863; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a2, v107864; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7865; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v10, v8, 17866; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a3, v107867; RV64ZVE32F-ZVFHMIN-NEXT:    zext.b a2, a27868; RV64ZVE32F-ZVFHMIN-NEXT:    slli a2, a2, 17869; RV64ZVE32F-ZVFHMIN-NEXT:    add a2, a0, a27870; RV64ZVE32F-ZVFHMIN-NEXT:    fmv.h.x fa5, a37871; RV64ZVE32F-ZVFHMIN-NEXT:    fsh fa5, 0(a2)7872; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB70_4: # %else27873; RV64ZVE32F-ZVFHMIN-NEXT:    andi a2, a1, 47874; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma7875; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v10, v9, 27876; RV64ZVE32F-ZVFHMIN-NEXT:    beqz a2, .LBB70_67877; RV64ZVE32F-ZVFHMIN-NEXT:  # %bb.5: # %cond.store37878; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a2, v107879; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7880; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v11, v8, 27881; RV64ZVE32F-ZVFHMIN-NEXT:    zext.b a2, a27882; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a3, v117883; RV64ZVE32F-ZVFHMIN-NEXT:    slli a2, a2, 17884; RV64ZVE32F-ZVFHMIN-NEXT:    add a2, a0, a27885; RV64ZVE32F-ZVFHMIN-NEXT:    fmv.h.x fa5, a37886; RV64ZVE32F-ZVFHMIN-NEXT:    fsh fa5, 0(a2)7887; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB70_6: # %else47888; RV64ZVE32F-ZVFHMIN-NEXT:    andi a2, a1, 87889; RV64ZVE32F-ZVFHMIN-NEXT:    beqz a2, .LBB70_87890; RV64ZVE32F-ZVFHMIN-NEXT:  # %bb.7: # %cond.store57891; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma7892; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v10, v10, 17893; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a2, v107894; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7895; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v10, v8, 37896; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a3, v107897; RV64ZVE32F-ZVFHMIN-NEXT:    zext.b a2, a27898; RV64ZVE32F-ZVFHMIN-NEXT:    slli a2, a2, 17899; RV64ZVE32F-ZVFHMIN-NEXT:    add a2, a0, a27900; RV64ZVE32F-ZVFHMIN-NEXT:    fmv.h.x fa5, a37901; RV64ZVE32F-ZVFHMIN-NEXT:    fsh fa5, 0(a2)7902; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB70_8: # %else67903; RV64ZVE32F-ZVFHMIN-NEXT:    andi a2, a1, 167904; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 4, e8, mf2, ta, ma7905; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v9, v9, 47906; RV64ZVE32F-ZVFHMIN-NEXT:    beqz a2, .LBB70_107907; RV64ZVE32F-ZVFHMIN-NEXT:  # %bb.9: # %cond.store77908; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a2, v97909; RV64ZVE32F-ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m1, ta, ma7910; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v10, v8, 47911; RV64ZVE32F-ZVFHMIN-NEXT:    zext.b a2, a27912; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a3, v107913; RV64ZVE32F-ZVFHMIN-NEXT:    slli a2, a2, 17914; RV64ZVE32F-ZVFHMIN-NEXT:    add a2, a0, a27915; RV64ZVE32F-ZVFHMIN-NEXT:    fmv.h.x fa5, a37916; RV64ZVE32F-ZVFHMIN-NEXT:    fsh fa5, 0(a2)7917; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB70_10: # %else87918; RV64ZVE32F-ZVFHMIN-NEXT:    andi a2, a1, 327919; RV64ZVE32F-ZVFHMIN-NEXT:    beqz a2, .LBB70_127920; RV64ZVE32F-ZVFHMIN-NEXT:  # %bb.11: # %cond.store97921; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma7922; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v10, v9, 17923; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a2, v107924; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7925; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v10, v8, 57926; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a3, v107927; RV64ZVE32F-ZVFHMIN-NEXT:    zext.b a2, a27928; RV64ZVE32F-ZVFHMIN-NEXT:    slli a2, a2, 17929; RV64ZVE32F-ZVFHMIN-NEXT:    add a2, a0, a27930; RV64ZVE32F-ZVFHMIN-NEXT:    fmv.h.x fa5, a37931; RV64ZVE32F-ZVFHMIN-NEXT:    fsh fa5, 0(a2)7932; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB70_12: # %else107933; RV64ZVE32F-ZVFHMIN-NEXT:    andi a2, a1, 647934; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma7935; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v9, v9, 27936; RV64ZVE32F-ZVFHMIN-NEXT:    bnez a2, .LBB70_157937; RV64ZVE32F-ZVFHMIN-NEXT:  # %bb.13: # %else127938; RV64ZVE32F-ZVFHMIN-NEXT:    andi a1, a1, -1287939; RV64ZVE32F-ZVFHMIN-NEXT:    bnez a1, .LBB70_167940; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB70_14: # %else147941; RV64ZVE32F-ZVFHMIN-NEXT:    ret7942; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB70_15: # %cond.store117943; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a2, v97944; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7945; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v10, v8, 67946; RV64ZVE32F-ZVFHMIN-NEXT:    zext.b a2, a27947; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a3, v107948; RV64ZVE32F-ZVFHMIN-NEXT:    slli a2, a2, 17949; RV64ZVE32F-ZVFHMIN-NEXT:    add a2, a0, a27950; RV64ZVE32F-ZVFHMIN-NEXT:    fmv.h.x fa5, a37951; RV64ZVE32F-ZVFHMIN-NEXT:    fsh fa5, 0(a2)7952; RV64ZVE32F-ZVFHMIN-NEXT:    andi a1, a1, -1287953; RV64ZVE32F-ZVFHMIN-NEXT:    beqz a1, .LBB70_147954; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB70_16: # %cond.store137955; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma7956; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v9, v9, 17957; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma7958; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v8, v8, 77959; RV64ZVE32F-ZVFHMIN-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma7960; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a1, v97961; RV64ZVE32F-ZVFHMIN-NEXT:    zext.b a1, a17962; RV64ZVE32F-ZVFHMIN-NEXT:    slli a1, a1, 17963; RV64ZVE32F-ZVFHMIN-NEXT:    add a0, a0, a17964; RV64ZVE32F-ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m1, ta, ma7965; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a1, v87966; RV64ZVE32F-ZVFHMIN-NEXT:    fmv.h.x fa5, a17967; RV64ZVE32F-ZVFHMIN-NEXT:    fsh fa5, 0(a0)7968; RV64ZVE32F-ZVFHMIN-NEXT:    ret7969  %eidxs = zext <8 x i8> %idxs to <8 x i16>7970  %ptrs = getelementptr inbounds half, ptr %base, <8 x i16> %eidxs7971  call void @llvm.masked.scatter.v8f16.v8p0(<8 x half> %val, <8 x ptr> %ptrs, i32 2, <8 x i1> %m)7972  ret void7973}7974 7975define void @mscatter_baseidx_v8f16(<8 x half> %val, ptr %base, <8 x i16> %idxs, <8 x i1> %m) {7976; RV32-LABEL: mscatter_baseidx_v8f16:7977; RV32:       # %bb.0:7978; RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma7979; RV32-NEXT:    vwadd.vv v10, v9, v97980; RV32-NEXT:    vsoxei32.v v8, (a0), v10, v0.t7981; RV32-NEXT:    ret7982;7983; RV64V-LABEL: mscatter_baseidx_v8f16:7984; RV64V:       # %bb.0:7985; RV64V-NEXT:    vsetivli zero, 8, e64, m4, ta, ma7986; RV64V-NEXT:    vsext.vf4 v12, v97987; RV64V-NEXT:    vadd.vv v12, v12, v127988; RV64V-NEXT:    vsetvli zero, zero, e16, m1, ta, ma7989; RV64V-NEXT:    vsoxei64.v v8, (a0), v12, v0.t7990; RV64V-NEXT:    ret7991;7992; RV64ZVE32F-ZVFH-LABEL: mscatter_baseidx_v8f16:7993; RV64ZVE32F-ZVFH:       # %bb.0:7994; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e8, m1, ta, ma7995; RV64ZVE32F-ZVFH-NEXT:    vmv.x.s a1, v07996; RV64ZVE32F-ZVFH-NEXT:    andi a2, a1, 17997; RV64ZVE32F-ZVFH-NEXT:    beqz a2, .LBB71_27998; RV64ZVE32F-ZVFH-NEXT:  # %bb.1: # %cond.store7999; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e16, m1, ta, ma8000; RV64ZVE32F-ZVFH-NEXT:    vmv.x.s a2, v98001; RV64ZVE32F-ZVFH-NEXT:    slli a2, a2, 18002; RV64ZVE32F-ZVFH-NEXT:    add a2, a0, a28003; RV64ZVE32F-ZVFH-NEXT:    vse16.v v8, (a2)8004; RV64ZVE32F-ZVFH-NEXT:  .LBB71_2: # %else8005; RV64ZVE32F-ZVFH-NEXT:    andi a2, a1, 28006; RV64ZVE32F-ZVFH-NEXT:    beqz a2, .LBB71_48007; RV64ZVE32F-ZVFH-NEXT:  # %bb.3: # %cond.store18008; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma8009; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v10, v9, 18010; RV64ZVE32F-ZVFH-NEXT:    vmv.x.s a2, v108011; RV64ZVE32F-ZVFH-NEXT:    slli a2, a2, 18012; RV64ZVE32F-ZVFH-NEXT:    add a2, a0, a28013; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e16, m1, ta, ma8014; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v10, v8, 18015; RV64ZVE32F-ZVFH-NEXT:    vse16.v v10, (a2)8016; RV64ZVE32F-ZVFH-NEXT:  .LBB71_4: # %else28017; RV64ZVE32F-ZVFH-NEXT:    andi a2, a1, 48018; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 2, e16, mf2, ta, ma8019; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v10, v9, 28020; RV64ZVE32F-ZVFH-NEXT:    beqz a2, .LBB71_68021; RV64ZVE32F-ZVFH-NEXT:  # %bb.5: # %cond.store38022; RV64ZVE32F-ZVFH-NEXT:    vmv.x.s a2, v108023; RV64ZVE32F-ZVFH-NEXT:    slli a2, a2, 18024; RV64ZVE32F-ZVFH-NEXT:    add a2, a0, a28025; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e16, m1, ta, ma8026; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v11, v8, 28027; RV64ZVE32F-ZVFH-NEXT:    vse16.v v11, (a2)8028; RV64ZVE32F-ZVFH-NEXT:  .LBB71_6: # %else48029; RV64ZVE32F-ZVFH-NEXT:    andi a2, a1, 88030; RV64ZVE32F-ZVFH-NEXT:    beqz a2, .LBB71_88031; RV64ZVE32F-ZVFH-NEXT:  # %bb.7: # %cond.store58032; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma8033; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v10, v10, 18034; RV64ZVE32F-ZVFH-NEXT:    vmv.x.s a2, v108035; RV64ZVE32F-ZVFH-NEXT:    slli a2, a2, 18036; RV64ZVE32F-ZVFH-NEXT:    add a2, a0, a28037; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e16, m1, ta, ma8038; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v10, v8, 38039; RV64ZVE32F-ZVFH-NEXT:    vse16.v v10, (a2)8040; RV64ZVE32F-ZVFH-NEXT:  .LBB71_8: # %else68041; RV64ZVE32F-ZVFH-NEXT:    andi a2, a1, 168042; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 4, e16, m1, ta, ma8043; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v9, v9, 48044; RV64ZVE32F-ZVFH-NEXT:    beqz a2, .LBB71_108045; RV64ZVE32F-ZVFH-NEXT:  # %bb.9: # %cond.store78046; RV64ZVE32F-ZVFH-NEXT:    vmv.x.s a2, v98047; RV64ZVE32F-ZVFH-NEXT:    slli a2, a2, 18048; RV64ZVE32F-ZVFH-NEXT:    add a2, a0, a28049; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v10, v8, 48050; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e16, m1, ta, ma8051; RV64ZVE32F-ZVFH-NEXT:    vse16.v v10, (a2)8052; RV64ZVE32F-ZVFH-NEXT:  .LBB71_10: # %else88053; RV64ZVE32F-ZVFH-NEXT:    andi a2, a1, 328054; RV64ZVE32F-ZVFH-NEXT:    beqz a2, .LBB71_128055; RV64ZVE32F-ZVFH-NEXT:  # %bb.11: # %cond.store98056; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma8057; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v10, v9, 18058; RV64ZVE32F-ZVFH-NEXT:    vmv.x.s a2, v108059; RV64ZVE32F-ZVFH-NEXT:    slli a2, a2, 18060; RV64ZVE32F-ZVFH-NEXT:    add a2, a0, a28061; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e16, m1, ta, ma8062; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v10, v8, 58063; RV64ZVE32F-ZVFH-NEXT:    vse16.v v10, (a2)8064; RV64ZVE32F-ZVFH-NEXT:  .LBB71_12: # %else108065; RV64ZVE32F-ZVFH-NEXT:    andi a2, a1, 648066; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 2, e16, mf2, ta, ma8067; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v9, v9, 28068; RV64ZVE32F-ZVFH-NEXT:    bnez a2, .LBB71_158069; RV64ZVE32F-ZVFH-NEXT:  # %bb.13: # %else128070; RV64ZVE32F-ZVFH-NEXT:    andi a1, a1, -1288071; RV64ZVE32F-ZVFH-NEXT:    bnez a1, .LBB71_168072; RV64ZVE32F-ZVFH-NEXT:  .LBB71_14: # %else148073; RV64ZVE32F-ZVFH-NEXT:    ret8074; RV64ZVE32F-ZVFH-NEXT:  .LBB71_15: # %cond.store118075; RV64ZVE32F-ZVFH-NEXT:    vmv.x.s a2, v98076; RV64ZVE32F-ZVFH-NEXT:    slli a2, a2, 18077; RV64ZVE32F-ZVFH-NEXT:    add a2, a0, a28078; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e16, m1, ta, ma8079; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v10, v8, 68080; RV64ZVE32F-ZVFH-NEXT:    vse16.v v10, (a2)8081; RV64ZVE32F-ZVFH-NEXT:    andi a1, a1, -1288082; RV64ZVE32F-ZVFH-NEXT:    beqz a1, .LBB71_148083; RV64ZVE32F-ZVFH-NEXT:  .LBB71_16: # %cond.store138084; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma8085; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v9, v9, 18086; RV64ZVE32F-ZVFH-NEXT:    vmv.x.s a1, v98087; RV64ZVE32F-ZVFH-NEXT:    slli a1, a1, 18088; RV64ZVE32F-ZVFH-NEXT:    add a0, a0, a18089; RV64ZVE32F-ZVFH-NEXT:    vsetivli zero, 1, e16, m1, ta, ma8090; RV64ZVE32F-ZVFH-NEXT:    vslidedown.vi v8, v8, 78091; RV64ZVE32F-ZVFH-NEXT:    vse16.v v8, (a0)8092; RV64ZVE32F-ZVFH-NEXT:    ret8093;8094; RV64ZVE32F-ZVFHMIN-LABEL: mscatter_baseidx_v8f16:8095; RV64ZVE32F-ZVFHMIN:       # %bb.0:8096; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e8, m1, ta, ma8097; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a1, v08098; RV64ZVE32F-ZVFHMIN-NEXT:    andi a2, a1, 18099; RV64ZVE32F-ZVFHMIN-NEXT:    beqz a2, .LBB71_28100; RV64ZVE32F-ZVFHMIN-NEXT:  # %bb.1: # %cond.store8101; RV64ZVE32F-ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m2, ta, ma8102; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a2, v98103; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a3, v88104; RV64ZVE32F-ZVFHMIN-NEXT:    slli a2, a2, 18105; RV64ZVE32F-ZVFHMIN-NEXT:    add a2, a0, a28106; RV64ZVE32F-ZVFHMIN-NEXT:    fmv.h.x fa5, a38107; RV64ZVE32F-ZVFHMIN-NEXT:    fsh fa5, 0(a2)8108; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB71_2: # %else8109; RV64ZVE32F-ZVFHMIN-NEXT:    andi a2, a1, 28110; RV64ZVE32F-ZVFHMIN-NEXT:    beqz a2, .LBB71_48111; RV64ZVE32F-ZVFHMIN-NEXT:  # %bb.3: # %cond.store18112; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma8113; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v10, v9, 18114; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a2, v108115; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma8116; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v10, v8, 18117; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a3, v108118; RV64ZVE32F-ZVFHMIN-NEXT:    slli a2, a2, 18119; RV64ZVE32F-ZVFHMIN-NEXT:    add a2, a0, a28120; RV64ZVE32F-ZVFHMIN-NEXT:    fmv.h.x fa5, a38121; RV64ZVE32F-ZVFHMIN-NEXT:    fsh fa5, 0(a2)8122; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB71_4: # %else28123; RV64ZVE32F-ZVFHMIN-NEXT:    andi a2, a1, 48124; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 2, e16, mf2, ta, ma8125; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v10, v9, 28126; RV64ZVE32F-ZVFHMIN-NEXT:    beqz a2, .LBB71_68127; RV64ZVE32F-ZVFHMIN-NEXT:  # %bb.5: # %cond.store38128; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a2, v108129; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma8130; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v11, v8, 28131; RV64ZVE32F-ZVFHMIN-NEXT:    slli a2, a2, 18132; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a3, v118133; RV64ZVE32F-ZVFHMIN-NEXT:    add a2, a0, a28134; RV64ZVE32F-ZVFHMIN-NEXT:    fmv.h.x fa5, a38135; RV64ZVE32F-ZVFHMIN-NEXT:    fsh fa5, 0(a2)8136; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB71_6: # %else48137; RV64ZVE32F-ZVFHMIN-NEXT:    andi a2, a1, 88138; RV64ZVE32F-ZVFHMIN-NEXT:    beqz a2, .LBB71_88139; RV64ZVE32F-ZVFHMIN-NEXT:  # %bb.7: # %cond.store58140; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma8141; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v10, v10, 18142; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a2, v108143; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma8144; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v10, v8, 38145; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a3, v108146; RV64ZVE32F-ZVFHMIN-NEXT:    slli a2, a2, 18147; RV64ZVE32F-ZVFHMIN-NEXT:    add a2, a0, a28148; RV64ZVE32F-ZVFHMIN-NEXT:    fmv.h.x fa5, a38149; RV64ZVE32F-ZVFHMIN-NEXT:    fsh fa5, 0(a2)8150; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB71_8: # %else68151; RV64ZVE32F-ZVFHMIN-NEXT:    andi a2, a1, 168152; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 4, e16, m1, ta, ma8153; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v9, v9, 48154; RV64ZVE32F-ZVFHMIN-NEXT:    beqz a2, .LBB71_108155; RV64ZVE32F-ZVFHMIN-NEXT:  # %bb.9: # %cond.store78156; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a2, v98157; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v10, v8, 48158; RV64ZVE32F-ZVFHMIN-NEXT:    slli a2, a2, 18159; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a3, v108160; RV64ZVE32F-ZVFHMIN-NEXT:    add a2, a0, a28161; RV64ZVE32F-ZVFHMIN-NEXT:    fmv.h.x fa5, a38162; RV64ZVE32F-ZVFHMIN-NEXT:    fsh fa5, 0(a2)8163; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB71_10: # %else88164; RV64ZVE32F-ZVFHMIN-NEXT:    andi a2, a1, 328165; RV64ZVE32F-ZVFHMIN-NEXT:    beqz a2, .LBB71_128166; RV64ZVE32F-ZVFHMIN-NEXT:  # %bb.11: # %cond.store98167; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma8168; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v10, v9, 18169; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a2, v108170; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma8171; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v10, v8, 58172; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a3, v108173; RV64ZVE32F-ZVFHMIN-NEXT:    slli a2, a2, 18174; RV64ZVE32F-ZVFHMIN-NEXT:    add a2, a0, a28175; RV64ZVE32F-ZVFHMIN-NEXT:    fmv.h.x fa5, a38176; RV64ZVE32F-ZVFHMIN-NEXT:    fsh fa5, 0(a2)8177; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB71_12: # %else108178; RV64ZVE32F-ZVFHMIN-NEXT:    andi a2, a1, 648179; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 2, e16, mf2, ta, ma8180; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v9, v9, 28181; RV64ZVE32F-ZVFHMIN-NEXT:    bnez a2, .LBB71_158182; RV64ZVE32F-ZVFHMIN-NEXT:  # %bb.13: # %else128183; RV64ZVE32F-ZVFHMIN-NEXT:    andi a1, a1, -1288184; RV64ZVE32F-ZVFHMIN-NEXT:    bnez a1, .LBB71_168185; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB71_14: # %else148186; RV64ZVE32F-ZVFHMIN-NEXT:    ret8187; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB71_15: # %cond.store118188; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a2, v98189; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma8190; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v10, v8, 68191; RV64ZVE32F-ZVFHMIN-NEXT:    slli a2, a2, 18192; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a3, v108193; RV64ZVE32F-ZVFHMIN-NEXT:    add a2, a0, a28194; RV64ZVE32F-ZVFHMIN-NEXT:    fmv.h.x fa5, a38195; RV64ZVE32F-ZVFHMIN-NEXT:    fsh fa5, 0(a2)8196; RV64ZVE32F-ZVFHMIN-NEXT:    andi a1, a1, -1288197; RV64ZVE32F-ZVFHMIN-NEXT:    beqz a1, .LBB71_148198; RV64ZVE32F-ZVFHMIN-NEXT:  .LBB71_16: # %cond.store138199; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma8200; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v9, v9, 18201; RV64ZVE32F-ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma8202; RV64ZVE32F-ZVFHMIN-NEXT:    vslidedown.vi v8, v8, 78203; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a1, v98204; RV64ZVE32F-ZVFHMIN-NEXT:    slli a1, a1, 18205; RV64ZVE32F-ZVFHMIN-NEXT:    add a0, a0, a18206; RV64ZVE32F-ZVFHMIN-NEXT:    vmv.x.s a1, v88207; RV64ZVE32F-ZVFHMIN-NEXT:    fmv.h.x fa5, a18208; RV64ZVE32F-ZVFHMIN-NEXT:    fsh fa5, 0(a0)8209; RV64ZVE32F-ZVFHMIN-NEXT:    ret8210  %ptrs = getelementptr inbounds half, ptr %base, <8 x i16> %idxs8211  call void @llvm.masked.scatter.v8f16.v8p0(<8 x half> %val, <8 x ptr> %ptrs, i32 2, <8 x i1> %m)8212  ret void8213}8214 8215define void @mscatter_v1f32(<1 x float> %val, <1 x ptr> %ptrs, <1 x i1> %m) {8216; RV32V-LABEL: mscatter_v1f32:8217; RV32V:       # %bb.0:8218; RV32V-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma8219; RV32V-NEXT:    vsoxei32.v v8, (zero), v9, v0.t8220; RV32V-NEXT:    ret8221;8222; RV64V-LABEL: mscatter_v1f32:8223; RV64V:       # %bb.0:8224; RV64V-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma8225; RV64V-NEXT:    vsoxei64.v v8, (zero), v9, v0.t8226; RV64V-NEXT:    ret8227;8228; RV32ZVE32F-LABEL: mscatter_v1f32:8229; RV32ZVE32F:       # %bb.0:8230; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma8231; RV32ZVE32F-NEXT:    vsoxei32.v v8, (zero), v9, v0.t8232; RV32ZVE32F-NEXT:    ret8233;8234; RV64ZVE32F-LABEL: mscatter_v1f32:8235; RV64ZVE32F:       # %bb.0:8236; RV64ZVE32F-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma8237; RV64ZVE32F-NEXT:    vfirst.m a1, v08238; RV64ZVE32F-NEXT:    bnez a1, .LBB72_28239; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store8240; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma8241; RV64ZVE32F-NEXT:    vse32.v v8, (a0)8242; RV64ZVE32F-NEXT:  .LBB72_2: # %else8243; RV64ZVE32F-NEXT:    ret8244  call void @llvm.masked.scatter.v1f32.v1p0(<1 x float> %val, <1 x ptr> %ptrs, i32 4, <1 x i1> %m)8245  ret void8246}8247 8248define void @mscatter_v2f32(<2 x float> %val, <2 x ptr> %ptrs, <2 x i1> %m) {8249; RV32V-LABEL: mscatter_v2f32:8250; RV32V:       # %bb.0:8251; RV32V-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma8252; RV32V-NEXT:    vsoxei32.v v8, (zero), v9, v0.t8253; RV32V-NEXT:    ret8254;8255; RV64V-LABEL: mscatter_v2f32:8256; RV64V:       # %bb.0:8257; RV64V-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma8258; RV64V-NEXT:    vsoxei64.v v8, (zero), v9, v0.t8259; RV64V-NEXT:    ret8260;8261; RV32ZVE32F-LABEL: mscatter_v2f32:8262; RV32ZVE32F:       # %bb.0:8263; RV32ZVE32F-NEXT:    vsetivli zero, 2, e32, m1, ta, ma8264; RV32ZVE32F-NEXT:    vsoxei32.v v8, (zero), v9, v0.t8265; RV32ZVE32F-NEXT:    ret8266;8267; RV64ZVE32F-LABEL: mscatter_v2f32:8268; RV64ZVE32F:       # %bb.0:8269; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma8270; RV64ZVE32F-NEXT:    vmv.x.s a2, v08271; RV64ZVE32F-NEXT:    andi a3, a2, 18272; RV64ZVE32F-NEXT:    bnez a3, .LBB73_38273; RV64ZVE32F-NEXT:  # %bb.1: # %else8274; RV64ZVE32F-NEXT:    andi a2, a2, 28275; RV64ZVE32F-NEXT:    bnez a2, .LBB73_48276; RV64ZVE32F-NEXT:  .LBB73_2: # %else28277; RV64ZVE32F-NEXT:    ret8278; RV64ZVE32F-NEXT:  .LBB73_3: # %cond.store8279; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma8280; RV64ZVE32F-NEXT:    vse32.v v8, (a0)8281; RV64ZVE32F-NEXT:    andi a2, a2, 28282; RV64ZVE32F-NEXT:    beqz a2, .LBB73_28283; RV64ZVE32F-NEXT:  .LBB73_4: # %cond.store18284; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma8285; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 18286; RV64ZVE32F-NEXT:    vse32.v v8, (a1)8287; RV64ZVE32F-NEXT:    ret8288  call void @llvm.masked.scatter.v2f32.v2p0(<2 x float> %val, <2 x ptr> %ptrs, i32 4, <2 x i1> %m)8289  ret void8290}8291 8292define void @mscatter_v4f32(<4 x float> %val, <4 x ptr> %ptrs, <4 x i1> %m) {8293; RV32-LABEL: mscatter_v4f32:8294; RV32:       # %bb.0:8295; RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, ma8296; RV32-NEXT:    vsoxei32.v v8, (zero), v9, v0.t8297; RV32-NEXT:    ret8298;8299; RV64V-LABEL: mscatter_v4f32:8300; RV64V:       # %bb.0:8301; RV64V-NEXT:    vsetivli zero, 4, e32, m1, ta, ma8302; RV64V-NEXT:    vsoxei64.v v8, (zero), v10, v0.t8303; RV64V-NEXT:    ret8304;8305; RV64ZVE32F-LABEL: mscatter_v4f32:8306; RV64ZVE32F:       # %bb.0:8307; RV64ZVE32F-NEXT:    ld a4, 8(a0)8308; RV64ZVE32F-NEXT:    ld a2, 16(a0)8309; RV64ZVE32F-NEXT:    ld a1, 24(a0)8310; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma8311; RV64ZVE32F-NEXT:    vmv.x.s a3, v08312; RV64ZVE32F-NEXT:    andi a5, a3, 18313; RV64ZVE32F-NEXT:    bnez a5, .LBB74_58314; RV64ZVE32F-NEXT:  # %bb.1: # %else8315; RV64ZVE32F-NEXT:    andi a0, a3, 28316; RV64ZVE32F-NEXT:    bnez a0, .LBB74_68317; RV64ZVE32F-NEXT:  .LBB74_2: # %else28318; RV64ZVE32F-NEXT:    andi a0, a3, 48319; RV64ZVE32F-NEXT:    bnez a0, .LBB74_78320; RV64ZVE32F-NEXT:  .LBB74_3: # %else48321; RV64ZVE32F-NEXT:    andi a3, a3, 88322; RV64ZVE32F-NEXT:    bnez a3, .LBB74_88323; RV64ZVE32F-NEXT:  .LBB74_4: # %else68324; RV64ZVE32F-NEXT:    ret8325; RV64ZVE32F-NEXT:  .LBB74_5: # %cond.store8326; RV64ZVE32F-NEXT:    ld a0, 0(a0)8327; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma8328; RV64ZVE32F-NEXT:    vse32.v v8, (a0)8329; RV64ZVE32F-NEXT:    andi a0, a3, 28330; RV64ZVE32F-NEXT:    beqz a0, .LBB74_28331; RV64ZVE32F-NEXT:  .LBB74_6: # %cond.store18332; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma8333; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 18334; RV64ZVE32F-NEXT:    vse32.v v9, (a4)8335; RV64ZVE32F-NEXT:    andi a0, a3, 48336; RV64ZVE32F-NEXT:    beqz a0, .LBB74_38337; RV64ZVE32F-NEXT:  .LBB74_7: # %cond.store38338; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma8339; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 28340; RV64ZVE32F-NEXT:    vse32.v v9, (a2)8341; RV64ZVE32F-NEXT:    andi a3, a3, 88342; RV64ZVE32F-NEXT:    beqz a3, .LBB74_48343; RV64ZVE32F-NEXT:  .LBB74_8: # %cond.store58344; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma8345; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 38346; RV64ZVE32F-NEXT:    vse32.v v8, (a1)8347; RV64ZVE32F-NEXT:    ret8348  call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> %val, <4 x ptr> %ptrs, i32 4, <4 x i1> %m)8349  ret void8350}8351 8352define void @mscatter_truemask_v4f32(<4 x float> %val, <4 x ptr> %ptrs) {8353; RV32-LABEL: mscatter_truemask_v4f32:8354; RV32:       # %bb.0:8355; RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, ma8356; RV32-NEXT:    vsoxei32.v v8, (zero), v98357; RV32-NEXT:    ret8358;8359; RV64V-LABEL: mscatter_truemask_v4f32:8360; RV64V:       # %bb.0:8361; RV64V-NEXT:    vsetivli zero, 4, e32, m1, ta, ma8362; RV64V-NEXT:    vsoxei64.v v8, (zero), v108363; RV64V-NEXT:    ret8364;8365; RV64ZVE32F-LABEL: mscatter_truemask_v4f32:8366; RV64ZVE32F:       # %bb.0:8367; RV64ZVE32F-NEXT:    ld a1, 0(a0)8368; RV64ZVE32F-NEXT:    ld a2, 8(a0)8369; RV64ZVE32F-NEXT:    ld a3, 16(a0)8370; RV64ZVE32F-NEXT:    ld a0, 24(a0)8371; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma8372; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 18373; RV64ZVE32F-NEXT:    vse32.v v8, (a1)8374; RV64ZVE32F-NEXT:    vse32.v v9, (a2)8375; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 28376; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 38377; RV64ZVE32F-NEXT:    vse32.v v9, (a3)8378; RV64ZVE32F-NEXT:    vse32.v v8, (a0)8379; RV64ZVE32F-NEXT:    ret8380  call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> %val, <4 x ptr> %ptrs, i32 4, <4 x i1> splat (i1 1))8381  ret void8382}8383 8384define void @mscatter_falsemask_v4f32(<4 x float> %val, <4 x ptr> %ptrs) {8385; CHECK-LABEL: mscatter_falsemask_v4f32:8386; CHECK:       # %bb.0:8387; CHECK-NEXT:    ret8388  call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> %val, <4 x ptr> %ptrs, i32 4, <4 x i1> zeroinitializer)8389  ret void8390}8391 8392define void @mscatter_v8f32(<8 x float> %val, <8 x ptr> %ptrs, <8 x i1> %m) {8393; RV32-LABEL: mscatter_v8f32:8394; RV32:       # %bb.0:8395; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma8396; RV32-NEXT:    vsoxei32.v v8, (zero), v10, v0.t8397; RV32-NEXT:    ret8398;8399; RV64V-LABEL: mscatter_v8f32:8400; RV64V:       # %bb.0:8401; RV64V-NEXT:    vsetivli zero, 8, e32, m2, ta, ma8402; RV64V-NEXT:    vsoxei64.v v8, (zero), v12, v0.t8403; RV64V-NEXT:    ret8404;8405; RV64ZVE32F-LABEL: mscatter_v8f32:8406; RV64ZVE32F:       # %bb.0:8407; RV64ZVE32F-NEXT:    ld a3, 40(a0)8408; RV64ZVE32F-NEXT:    ld a2, 48(a0)8409; RV64ZVE32F-NEXT:    ld a1, 56(a0)8410; RV64ZVE32F-NEXT:    ld t0, 8(a0)8411; RV64ZVE32F-NEXT:    ld a7, 16(a0)8412; RV64ZVE32F-NEXT:    ld a6, 24(a0)8413; RV64ZVE32F-NEXT:    ld a5, 32(a0)8414; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma8415; RV64ZVE32F-NEXT:    vmv.x.s a4, v08416; RV64ZVE32F-NEXT:    andi t1, a4, 18417; RV64ZVE32F-NEXT:    bnez t1, .LBB77_98418; RV64ZVE32F-NEXT:  # %bb.1: # %else8419; RV64ZVE32F-NEXT:    andi a0, a4, 28420; RV64ZVE32F-NEXT:    bnez a0, .LBB77_108421; RV64ZVE32F-NEXT:  .LBB77_2: # %else28422; RV64ZVE32F-NEXT:    andi a0, a4, 48423; RV64ZVE32F-NEXT:    bnez a0, .LBB77_118424; RV64ZVE32F-NEXT:  .LBB77_3: # %else48425; RV64ZVE32F-NEXT:    andi a0, a4, 88426; RV64ZVE32F-NEXT:    bnez a0, .LBB77_128427; RV64ZVE32F-NEXT:  .LBB77_4: # %else68428; RV64ZVE32F-NEXT:    andi a0, a4, 168429; RV64ZVE32F-NEXT:    bnez a0, .LBB77_138430; RV64ZVE32F-NEXT:  .LBB77_5: # %else88431; RV64ZVE32F-NEXT:    andi a0, a4, 328432; RV64ZVE32F-NEXT:    bnez a0, .LBB77_148433; RV64ZVE32F-NEXT:  .LBB77_6: # %else108434; RV64ZVE32F-NEXT:    andi a0, a4, 648435; RV64ZVE32F-NEXT:    bnez a0, .LBB77_158436; RV64ZVE32F-NEXT:  .LBB77_7: # %else128437; RV64ZVE32F-NEXT:    andi a0, a4, -1288438; RV64ZVE32F-NEXT:    bnez a0, .LBB77_168439; RV64ZVE32F-NEXT:  .LBB77_8: # %else148440; RV64ZVE32F-NEXT:    ret8441; RV64ZVE32F-NEXT:  .LBB77_9: # %cond.store8442; RV64ZVE32F-NEXT:    ld a0, 0(a0)8443; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma8444; RV64ZVE32F-NEXT:    vse32.v v8, (a0)8445; RV64ZVE32F-NEXT:    andi a0, a4, 28446; RV64ZVE32F-NEXT:    beqz a0, .LBB77_28447; RV64ZVE32F-NEXT:  .LBB77_10: # %cond.store18448; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma8449; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 18450; RV64ZVE32F-NEXT:    vse32.v v10, (t0)8451; RV64ZVE32F-NEXT:    andi a0, a4, 48452; RV64ZVE32F-NEXT:    beqz a0, .LBB77_38453; RV64ZVE32F-NEXT:  .LBB77_11: # %cond.store38454; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma8455; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 28456; RV64ZVE32F-NEXT:    vse32.v v10, (a7)8457; RV64ZVE32F-NEXT:    andi a0, a4, 88458; RV64ZVE32F-NEXT:    beqz a0, .LBB77_48459; RV64ZVE32F-NEXT:  .LBB77_12: # %cond.store58460; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma8461; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 38462; RV64ZVE32F-NEXT:    vse32.v v10, (a6)8463; RV64ZVE32F-NEXT:    andi a0, a4, 168464; RV64ZVE32F-NEXT:    beqz a0, .LBB77_58465; RV64ZVE32F-NEXT:  .LBB77_13: # %cond.store78466; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma8467; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 48468; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma8469; RV64ZVE32F-NEXT:    vse32.v v10, (a5)8470; RV64ZVE32F-NEXT:    andi a0, a4, 328471; RV64ZVE32F-NEXT:    beqz a0, .LBB77_68472; RV64ZVE32F-NEXT:  .LBB77_14: # %cond.store98473; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma8474; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 58475; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma8476; RV64ZVE32F-NEXT:    vse32.v v10, (a3)8477; RV64ZVE32F-NEXT:    andi a0, a4, 648478; RV64ZVE32F-NEXT:    beqz a0, .LBB77_78479; RV64ZVE32F-NEXT:  .LBB77_15: # %cond.store118480; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma8481; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 68482; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma8483; RV64ZVE32F-NEXT:    vse32.v v10, (a2)8484; RV64ZVE32F-NEXT:    andi a0, a4, -1288485; RV64ZVE32F-NEXT:    beqz a0, .LBB77_88486; RV64ZVE32F-NEXT:  .LBB77_16: # %cond.store138487; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma8488; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 78489; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma8490; RV64ZVE32F-NEXT:    vse32.v v8, (a1)8491; RV64ZVE32F-NEXT:    ret8492  call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> %val, <8 x ptr> %ptrs, i32 4, <8 x i1> %m)8493  ret void8494}8495 8496define void @mscatter_baseidx_v8i8_v8f32(<8 x float> %val, ptr %base, <8 x i8> %idxs, <8 x i1> %m) {8497; RV32-LABEL: mscatter_baseidx_v8i8_v8f32:8498; RV32:       # %bb.0:8499; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma8500; RV32-NEXT:    vsext.vf4 v12, v108501; RV32-NEXT:    vsll.vi v10, v12, 28502; RV32-NEXT:    vsoxei32.v v8, (a0), v10, v0.t8503; RV32-NEXT:    ret8504;8505; RV64V-LABEL: mscatter_baseidx_v8i8_v8f32:8506; RV64V:       # %bb.0:8507; RV64V-NEXT:    vsetivli zero, 8, e64, m4, ta, ma8508; RV64V-NEXT:    vsext.vf8 v12, v108509; RV64V-NEXT:    vsll.vi v12, v12, 28510; RV64V-NEXT:    vsetvli zero, zero, e32, m2, ta, ma8511; RV64V-NEXT:    vsoxei64.v v8, (a0), v12, v0.t8512; RV64V-NEXT:    ret8513;8514; RV64ZVE32F-LABEL: mscatter_baseidx_v8i8_v8f32:8515; RV64ZVE32F:       # %bb.0:8516; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma8517; RV64ZVE32F-NEXT:    vmv.x.s a1, v08518; RV64ZVE32F-NEXT:    andi a2, a1, 18519; RV64ZVE32F-NEXT:    beqz a2, .LBB78_28520; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store8521; RV64ZVE32F-NEXT:    vmv.x.s a2, v108522; RV64ZVE32F-NEXT:    slli a2, a2, 28523; RV64ZVE32F-NEXT:    add a2, a0, a28524; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma8525; RV64ZVE32F-NEXT:    vse32.v v8, (a2)8526; RV64ZVE32F-NEXT:  .LBB78_2: # %else8527; RV64ZVE32F-NEXT:    andi a2, a1, 28528; RV64ZVE32F-NEXT:    beqz a2, .LBB78_48529; RV64ZVE32F-NEXT:  # %bb.3: # %cond.store18530; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma8531; RV64ZVE32F-NEXT:    vslidedown.vi v11, v10, 18532; RV64ZVE32F-NEXT:    vmv.x.s a2, v118533; RV64ZVE32F-NEXT:    slli a2, a2, 28534; RV64ZVE32F-NEXT:    add a2, a0, a28535; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma8536; RV64ZVE32F-NEXT:    vslidedown.vi v11, v8, 18537; RV64ZVE32F-NEXT:    vse32.v v11, (a2)8538; RV64ZVE32F-NEXT:  .LBB78_4: # %else28539; RV64ZVE32F-NEXT:    andi a2, a1, 48540; RV64ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma8541; RV64ZVE32F-NEXT:    vslidedown.vi v11, v10, 28542; RV64ZVE32F-NEXT:    beqz a2, .LBB78_68543; RV64ZVE32F-NEXT:  # %bb.5: # %cond.store38544; RV64ZVE32F-NEXT:    vmv.x.s a2, v118545; RV64ZVE32F-NEXT:    slli a2, a2, 28546; RV64ZVE32F-NEXT:    add a2, a0, a28547; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma8548; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 28549; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma8550; RV64ZVE32F-NEXT:    vse32.v v12, (a2)8551; RV64ZVE32F-NEXT:  .LBB78_6: # %else48552; RV64ZVE32F-NEXT:    andi a2, a1, 88553; RV64ZVE32F-NEXT:    beqz a2, .LBB78_88554; RV64ZVE32F-NEXT:  # %bb.7: # %cond.store58555; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma8556; RV64ZVE32F-NEXT:    vslidedown.vi v11, v11, 18557; RV64ZVE32F-NEXT:    vmv.x.s a2, v118558; RV64ZVE32F-NEXT:    slli a2, a2, 28559; RV64ZVE32F-NEXT:    add a2, a0, a28560; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma8561; RV64ZVE32F-NEXT:    vslidedown.vi v11, v8, 38562; RV64ZVE32F-NEXT:    vse32.v v11, (a2)8563; RV64ZVE32F-NEXT:  .LBB78_8: # %else68564; RV64ZVE32F-NEXT:    andi a2, a1, 168565; RV64ZVE32F-NEXT:    vsetivli zero, 4, e8, mf2, ta, ma8566; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 48567; RV64ZVE32F-NEXT:    beqz a2, .LBB78_108568; RV64ZVE32F-NEXT:  # %bb.9: # %cond.store78569; RV64ZVE32F-NEXT:    vmv.x.s a2, v108570; RV64ZVE32F-NEXT:    slli a2, a2, 28571; RV64ZVE32F-NEXT:    add a2, a0, a28572; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma8573; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 48574; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma8575; RV64ZVE32F-NEXT:    vse32.v v12, (a2)8576; RV64ZVE32F-NEXT:  .LBB78_10: # %else88577; RV64ZVE32F-NEXT:    andi a2, a1, 328578; RV64ZVE32F-NEXT:    beqz a2, .LBB78_128579; RV64ZVE32F-NEXT:  # %bb.11: # %cond.store98580; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma8581; RV64ZVE32F-NEXT:    vslidedown.vi v11, v10, 18582; RV64ZVE32F-NEXT:    vmv.x.s a2, v118583; RV64ZVE32F-NEXT:    slli a2, a2, 28584; RV64ZVE32F-NEXT:    add a2, a0, a28585; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma8586; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 58587; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma8588; RV64ZVE32F-NEXT:    vse32.v v12, (a2)8589; RV64ZVE32F-NEXT:  .LBB78_12: # %else108590; RV64ZVE32F-NEXT:    andi a2, a1, 648591; RV64ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma8592; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 28593; RV64ZVE32F-NEXT:    bnez a2, .LBB78_158594; RV64ZVE32F-NEXT:  # %bb.13: # %else128595; RV64ZVE32F-NEXT:    andi a1, a1, -1288596; RV64ZVE32F-NEXT:    bnez a1, .LBB78_168597; RV64ZVE32F-NEXT:  .LBB78_14: # %else148598; RV64ZVE32F-NEXT:    ret8599; RV64ZVE32F-NEXT:  .LBB78_15: # %cond.store118600; RV64ZVE32F-NEXT:    vmv.x.s a2, v108601; RV64ZVE32F-NEXT:    slli a2, a2, 28602; RV64ZVE32F-NEXT:    add a2, a0, a28603; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma8604; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 68605; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma8606; RV64ZVE32F-NEXT:    vse32.v v12, (a2)8607; RV64ZVE32F-NEXT:    andi a1, a1, -1288608; RV64ZVE32F-NEXT:    beqz a1, .LBB78_148609; RV64ZVE32F-NEXT:  .LBB78_16: # %cond.store138610; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma8611; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 18612; RV64ZVE32F-NEXT:    vmv.x.s a1, v108613; RV64ZVE32F-NEXT:    slli a1, a1, 28614; RV64ZVE32F-NEXT:    add a0, a0, a18615; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma8616; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 78617; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma8618; RV64ZVE32F-NEXT:    vse32.v v8, (a0)8619; RV64ZVE32F-NEXT:    ret8620  %ptrs = getelementptr inbounds float, ptr %base, <8 x i8> %idxs8621  call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> %val, <8 x ptr> %ptrs, i32 4, <8 x i1> %m)8622  ret void8623}8624 8625define void @mscatter_baseidx_sext_v8i8_v8f32(<8 x float> %val, ptr %base, <8 x i8> %idxs, <8 x i1> %m) {8626; RV32-LABEL: mscatter_baseidx_sext_v8i8_v8f32:8627; RV32:       # %bb.0:8628; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma8629; RV32-NEXT:    vsext.vf4 v12, v108630; RV32-NEXT:    vsll.vi v10, v12, 28631; RV32-NEXT:    vsoxei32.v v8, (a0), v10, v0.t8632; RV32-NEXT:    ret8633;8634; RV64V-LABEL: mscatter_baseidx_sext_v8i8_v8f32:8635; RV64V:       # %bb.0:8636; RV64V-NEXT:    vsetivli zero, 8, e64, m4, ta, ma8637; RV64V-NEXT:    vsext.vf8 v12, v108638; RV64V-NEXT:    vsll.vi v12, v12, 28639; RV64V-NEXT:    vsetvli zero, zero, e32, m2, ta, ma8640; RV64V-NEXT:    vsoxei64.v v8, (a0), v12, v0.t8641; RV64V-NEXT:    ret8642;8643; RV64ZVE32F-LABEL: mscatter_baseidx_sext_v8i8_v8f32:8644; RV64ZVE32F:       # %bb.0:8645; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma8646; RV64ZVE32F-NEXT:    vmv.x.s a1, v08647; RV64ZVE32F-NEXT:    andi a2, a1, 18648; RV64ZVE32F-NEXT:    beqz a2, .LBB79_28649; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store8650; RV64ZVE32F-NEXT:    vmv.x.s a2, v108651; RV64ZVE32F-NEXT:    slli a2, a2, 28652; RV64ZVE32F-NEXT:    add a2, a0, a28653; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma8654; RV64ZVE32F-NEXT:    vse32.v v8, (a2)8655; RV64ZVE32F-NEXT:  .LBB79_2: # %else8656; RV64ZVE32F-NEXT:    andi a2, a1, 28657; RV64ZVE32F-NEXT:    beqz a2, .LBB79_48658; RV64ZVE32F-NEXT:  # %bb.3: # %cond.store18659; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma8660; RV64ZVE32F-NEXT:    vslidedown.vi v11, v10, 18661; RV64ZVE32F-NEXT:    vmv.x.s a2, v118662; RV64ZVE32F-NEXT:    slli a2, a2, 28663; RV64ZVE32F-NEXT:    add a2, a0, a28664; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma8665; RV64ZVE32F-NEXT:    vslidedown.vi v11, v8, 18666; RV64ZVE32F-NEXT:    vse32.v v11, (a2)8667; RV64ZVE32F-NEXT:  .LBB79_4: # %else28668; RV64ZVE32F-NEXT:    andi a2, a1, 48669; RV64ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma8670; RV64ZVE32F-NEXT:    vslidedown.vi v11, v10, 28671; RV64ZVE32F-NEXT:    beqz a2, .LBB79_68672; RV64ZVE32F-NEXT:  # %bb.5: # %cond.store38673; RV64ZVE32F-NEXT:    vmv.x.s a2, v118674; RV64ZVE32F-NEXT:    slli a2, a2, 28675; RV64ZVE32F-NEXT:    add a2, a0, a28676; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma8677; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 28678; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma8679; RV64ZVE32F-NEXT:    vse32.v v12, (a2)8680; RV64ZVE32F-NEXT:  .LBB79_6: # %else48681; RV64ZVE32F-NEXT:    andi a2, a1, 88682; RV64ZVE32F-NEXT:    beqz a2, .LBB79_88683; RV64ZVE32F-NEXT:  # %bb.7: # %cond.store58684; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma8685; RV64ZVE32F-NEXT:    vslidedown.vi v11, v11, 18686; RV64ZVE32F-NEXT:    vmv.x.s a2, v118687; RV64ZVE32F-NEXT:    slli a2, a2, 28688; RV64ZVE32F-NEXT:    add a2, a0, a28689; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma8690; RV64ZVE32F-NEXT:    vslidedown.vi v11, v8, 38691; RV64ZVE32F-NEXT:    vse32.v v11, (a2)8692; RV64ZVE32F-NEXT:  .LBB79_8: # %else68693; RV64ZVE32F-NEXT:    andi a2, a1, 168694; RV64ZVE32F-NEXT:    vsetivli zero, 4, e8, mf2, ta, ma8695; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 48696; RV64ZVE32F-NEXT:    beqz a2, .LBB79_108697; RV64ZVE32F-NEXT:  # %bb.9: # %cond.store78698; RV64ZVE32F-NEXT:    vmv.x.s a2, v108699; RV64ZVE32F-NEXT:    slli a2, a2, 28700; RV64ZVE32F-NEXT:    add a2, a0, a28701; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma8702; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 48703; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma8704; RV64ZVE32F-NEXT:    vse32.v v12, (a2)8705; RV64ZVE32F-NEXT:  .LBB79_10: # %else88706; RV64ZVE32F-NEXT:    andi a2, a1, 328707; RV64ZVE32F-NEXT:    beqz a2, .LBB79_128708; RV64ZVE32F-NEXT:  # %bb.11: # %cond.store98709; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma8710; RV64ZVE32F-NEXT:    vslidedown.vi v11, v10, 18711; RV64ZVE32F-NEXT:    vmv.x.s a2, v118712; RV64ZVE32F-NEXT:    slli a2, a2, 28713; RV64ZVE32F-NEXT:    add a2, a0, a28714; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma8715; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 58716; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma8717; RV64ZVE32F-NEXT:    vse32.v v12, (a2)8718; RV64ZVE32F-NEXT:  .LBB79_12: # %else108719; RV64ZVE32F-NEXT:    andi a2, a1, 648720; RV64ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma8721; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 28722; RV64ZVE32F-NEXT:    bnez a2, .LBB79_158723; RV64ZVE32F-NEXT:  # %bb.13: # %else128724; RV64ZVE32F-NEXT:    andi a1, a1, -1288725; RV64ZVE32F-NEXT:    bnez a1, .LBB79_168726; RV64ZVE32F-NEXT:  .LBB79_14: # %else148727; RV64ZVE32F-NEXT:    ret8728; RV64ZVE32F-NEXT:  .LBB79_15: # %cond.store118729; RV64ZVE32F-NEXT:    vmv.x.s a2, v108730; RV64ZVE32F-NEXT:    slli a2, a2, 28731; RV64ZVE32F-NEXT:    add a2, a0, a28732; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma8733; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 68734; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma8735; RV64ZVE32F-NEXT:    vse32.v v12, (a2)8736; RV64ZVE32F-NEXT:    andi a1, a1, -1288737; RV64ZVE32F-NEXT:    beqz a1, .LBB79_148738; RV64ZVE32F-NEXT:  .LBB79_16: # %cond.store138739; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma8740; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 18741; RV64ZVE32F-NEXT:    vmv.x.s a1, v108742; RV64ZVE32F-NEXT:    slli a1, a1, 28743; RV64ZVE32F-NEXT:    add a0, a0, a18744; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma8745; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 78746; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma8747; RV64ZVE32F-NEXT:    vse32.v v8, (a0)8748; RV64ZVE32F-NEXT:    ret8749  %eidxs = sext <8 x i8> %idxs to <8 x i32>8750  %ptrs = getelementptr inbounds float, ptr %base, <8 x i32> %eidxs8751  call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> %val, <8 x ptr> %ptrs, i32 4, <8 x i1> %m)8752  ret void8753}8754 8755define void @mscatter_baseidx_zext_v8i8_v8f32(<8 x float> %val, ptr %base, <8 x i8> %idxs, <8 x i1> %m) {8756; RV32-LABEL: mscatter_baseidx_zext_v8i8_v8f32:8757; RV32:       # %bb.0:8758; RV32-NEXT:    li a1, 48759; RV32-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma8760; RV32-NEXT:    vwmulu.vx v11, v10, a18761; RV32-NEXT:    vsetvli zero, zero, e32, m2, ta, ma8762; RV32-NEXT:    vsoxei16.v v8, (a0), v11, v0.t8763; RV32-NEXT:    ret8764;8765; RV64V-LABEL: mscatter_baseidx_zext_v8i8_v8f32:8766; RV64V:       # %bb.0:8767; RV64V-NEXT:    li a1, 48768; RV64V-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma8769; RV64V-NEXT:    vwmulu.vx v11, v10, a18770; RV64V-NEXT:    vsetvli zero, zero, e32, m2, ta, ma8771; RV64V-NEXT:    vsoxei16.v v8, (a0), v11, v0.t8772; RV64V-NEXT:    ret8773;8774; RV64ZVE32F-LABEL: mscatter_baseidx_zext_v8i8_v8f32:8775; RV64ZVE32F:       # %bb.0:8776; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma8777; RV64ZVE32F-NEXT:    vmv.x.s a1, v08778; RV64ZVE32F-NEXT:    andi a2, a1, 18779; RV64ZVE32F-NEXT:    beqz a2, .LBB80_28780; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store8781; RV64ZVE32F-NEXT:    vmv.x.s a2, v108782; RV64ZVE32F-NEXT:    zext.b a2, a28783; RV64ZVE32F-NEXT:    slli a2, a2, 28784; RV64ZVE32F-NEXT:    add a2, a0, a28785; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma8786; RV64ZVE32F-NEXT:    vse32.v v8, (a2)8787; RV64ZVE32F-NEXT:  .LBB80_2: # %else8788; RV64ZVE32F-NEXT:    andi a2, a1, 28789; RV64ZVE32F-NEXT:    beqz a2, .LBB80_48790; RV64ZVE32F-NEXT:  # %bb.3: # %cond.store18791; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma8792; RV64ZVE32F-NEXT:    vslidedown.vi v11, v10, 18793; RV64ZVE32F-NEXT:    vmv.x.s a2, v118794; RV64ZVE32F-NEXT:    zext.b a2, a28795; RV64ZVE32F-NEXT:    slli a2, a2, 28796; RV64ZVE32F-NEXT:    add a2, a0, a28797; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma8798; RV64ZVE32F-NEXT:    vslidedown.vi v11, v8, 18799; RV64ZVE32F-NEXT:    vse32.v v11, (a2)8800; RV64ZVE32F-NEXT:  .LBB80_4: # %else28801; RV64ZVE32F-NEXT:    andi a2, a1, 48802; RV64ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma8803; RV64ZVE32F-NEXT:    vslidedown.vi v11, v10, 28804; RV64ZVE32F-NEXT:    beqz a2, .LBB80_68805; RV64ZVE32F-NEXT:  # %bb.5: # %cond.store38806; RV64ZVE32F-NEXT:    vmv.x.s a2, v118807; RV64ZVE32F-NEXT:    zext.b a2, a28808; RV64ZVE32F-NEXT:    slli a2, a2, 28809; RV64ZVE32F-NEXT:    add a2, a0, a28810; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma8811; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 28812; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma8813; RV64ZVE32F-NEXT:    vse32.v v12, (a2)8814; RV64ZVE32F-NEXT:  .LBB80_6: # %else48815; RV64ZVE32F-NEXT:    andi a2, a1, 88816; RV64ZVE32F-NEXT:    beqz a2, .LBB80_88817; RV64ZVE32F-NEXT:  # %bb.7: # %cond.store58818; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma8819; RV64ZVE32F-NEXT:    vslidedown.vi v11, v11, 18820; RV64ZVE32F-NEXT:    vmv.x.s a2, v118821; RV64ZVE32F-NEXT:    zext.b a2, a28822; RV64ZVE32F-NEXT:    slli a2, a2, 28823; RV64ZVE32F-NEXT:    add a2, a0, a28824; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma8825; RV64ZVE32F-NEXT:    vslidedown.vi v11, v8, 38826; RV64ZVE32F-NEXT:    vse32.v v11, (a2)8827; RV64ZVE32F-NEXT:  .LBB80_8: # %else68828; RV64ZVE32F-NEXT:    andi a2, a1, 168829; RV64ZVE32F-NEXT:    vsetivli zero, 4, e8, mf2, ta, ma8830; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 48831; RV64ZVE32F-NEXT:    beqz a2, .LBB80_108832; RV64ZVE32F-NEXT:  # %bb.9: # %cond.store78833; RV64ZVE32F-NEXT:    vmv.x.s a2, v108834; RV64ZVE32F-NEXT:    zext.b a2, a28835; RV64ZVE32F-NEXT:    slli a2, a2, 28836; RV64ZVE32F-NEXT:    add a2, a0, a28837; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma8838; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 48839; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma8840; RV64ZVE32F-NEXT:    vse32.v v12, (a2)8841; RV64ZVE32F-NEXT:  .LBB80_10: # %else88842; RV64ZVE32F-NEXT:    andi a2, a1, 328843; RV64ZVE32F-NEXT:    beqz a2, .LBB80_128844; RV64ZVE32F-NEXT:  # %bb.11: # %cond.store98845; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma8846; RV64ZVE32F-NEXT:    vslidedown.vi v11, v10, 18847; RV64ZVE32F-NEXT:    vmv.x.s a2, v118848; RV64ZVE32F-NEXT:    zext.b a2, a28849; RV64ZVE32F-NEXT:    slli a2, a2, 28850; RV64ZVE32F-NEXT:    add a2, a0, a28851; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma8852; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 58853; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma8854; RV64ZVE32F-NEXT:    vse32.v v12, (a2)8855; RV64ZVE32F-NEXT:  .LBB80_12: # %else108856; RV64ZVE32F-NEXT:    andi a2, a1, 648857; RV64ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma8858; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 28859; RV64ZVE32F-NEXT:    bnez a2, .LBB80_158860; RV64ZVE32F-NEXT:  # %bb.13: # %else128861; RV64ZVE32F-NEXT:    andi a1, a1, -1288862; RV64ZVE32F-NEXT:    bnez a1, .LBB80_168863; RV64ZVE32F-NEXT:  .LBB80_14: # %else148864; RV64ZVE32F-NEXT:    ret8865; RV64ZVE32F-NEXT:  .LBB80_15: # %cond.store118866; RV64ZVE32F-NEXT:    vmv.x.s a2, v108867; RV64ZVE32F-NEXT:    zext.b a2, a28868; RV64ZVE32F-NEXT:    slli a2, a2, 28869; RV64ZVE32F-NEXT:    add a2, a0, a28870; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma8871; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 68872; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma8873; RV64ZVE32F-NEXT:    vse32.v v12, (a2)8874; RV64ZVE32F-NEXT:    andi a1, a1, -1288875; RV64ZVE32F-NEXT:    beqz a1, .LBB80_148876; RV64ZVE32F-NEXT:  .LBB80_16: # %cond.store138877; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma8878; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 18879; RV64ZVE32F-NEXT:    vmv.x.s a1, v108880; RV64ZVE32F-NEXT:    zext.b a1, a18881; RV64ZVE32F-NEXT:    slli a1, a1, 28882; RV64ZVE32F-NEXT:    add a0, a0, a18883; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma8884; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 78885; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma8886; RV64ZVE32F-NEXT:    vse32.v v8, (a0)8887; RV64ZVE32F-NEXT:    ret8888  %eidxs = zext <8 x i8> %idxs to <8 x i32>8889  %ptrs = getelementptr inbounds float, ptr %base, <8 x i32> %eidxs8890  call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> %val, <8 x ptr> %ptrs, i32 4, <8 x i1> %m)8891  ret void8892}8893 8894define void @mscatter_baseidx_v8i16_v8f32(<8 x float> %val, ptr %base, <8 x i16> %idxs, <8 x i1> %m) {8895; RV32-LABEL: mscatter_baseidx_v8i16_v8f32:8896; RV32:       # %bb.0:8897; RV32-NEXT:    li a1, 48898; RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma8899; RV32-NEXT:    vwmulsu.vx v12, v10, a18900; RV32-NEXT:    vsetvli zero, zero, e32, m2, ta, ma8901; RV32-NEXT:    vsoxei32.v v8, (a0), v12, v0.t8902; RV32-NEXT:    ret8903;8904; RV64V-LABEL: mscatter_baseidx_v8i16_v8f32:8905; RV64V:       # %bb.0:8906; RV64V-NEXT:    vsetivli zero, 8, e64, m4, ta, ma8907; RV64V-NEXT:    vsext.vf4 v12, v108908; RV64V-NEXT:    vsll.vi v12, v12, 28909; RV64V-NEXT:    vsetvli zero, zero, e32, m2, ta, ma8910; RV64V-NEXT:    vsoxei64.v v8, (a0), v12, v0.t8911; RV64V-NEXT:    ret8912;8913; RV64ZVE32F-LABEL: mscatter_baseidx_v8i16_v8f32:8914; RV64ZVE32F:       # %bb.0:8915; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma8916; RV64ZVE32F-NEXT:    vmv.x.s a1, v08917; RV64ZVE32F-NEXT:    andi a2, a1, 18918; RV64ZVE32F-NEXT:    beqz a2, .LBB81_28919; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store8920; RV64ZVE32F-NEXT:    vsetvli zero, zero, e16, m2, ta, ma8921; RV64ZVE32F-NEXT:    vmv.x.s a2, v108922; RV64ZVE32F-NEXT:    slli a2, a2, 28923; RV64ZVE32F-NEXT:    add a2, a0, a28924; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma8925; RV64ZVE32F-NEXT:    vse32.v v8, (a2)8926; RV64ZVE32F-NEXT:  .LBB81_2: # %else8927; RV64ZVE32F-NEXT:    andi a2, a1, 28928; RV64ZVE32F-NEXT:    beqz a2, .LBB81_48929; RV64ZVE32F-NEXT:  # %bb.3: # %cond.store18930; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma8931; RV64ZVE32F-NEXT:    vslidedown.vi v11, v10, 18932; RV64ZVE32F-NEXT:    vmv.x.s a2, v118933; RV64ZVE32F-NEXT:    slli a2, a2, 28934; RV64ZVE32F-NEXT:    add a2, a0, a28935; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma8936; RV64ZVE32F-NEXT:    vslidedown.vi v11, v8, 18937; RV64ZVE32F-NEXT:    vse32.v v11, (a2)8938; RV64ZVE32F-NEXT:  .LBB81_4: # %else28939; RV64ZVE32F-NEXT:    andi a2, a1, 48940; RV64ZVE32F-NEXT:    vsetivli zero, 2, e16, mf2, ta, ma8941; RV64ZVE32F-NEXT:    vslidedown.vi v11, v10, 28942; RV64ZVE32F-NEXT:    beqz a2, .LBB81_68943; RV64ZVE32F-NEXT:  # %bb.5: # %cond.store38944; RV64ZVE32F-NEXT:    vmv.x.s a2, v118945; RV64ZVE32F-NEXT:    slli a2, a2, 28946; RV64ZVE32F-NEXT:    add a2, a0, a28947; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma8948; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 28949; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma8950; RV64ZVE32F-NEXT:    vse32.v v12, (a2)8951; RV64ZVE32F-NEXT:  .LBB81_6: # %else48952; RV64ZVE32F-NEXT:    andi a2, a1, 88953; RV64ZVE32F-NEXT:    beqz a2, .LBB81_88954; RV64ZVE32F-NEXT:  # %bb.7: # %cond.store58955; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma8956; RV64ZVE32F-NEXT:    vslidedown.vi v11, v11, 18957; RV64ZVE32F-NEXT:    vmv.x.s a2, v118958; RV64ZVE32F-NEXT:    slli a2, a2, 28959; RV64ZVE32F-NEXT:    add a2, a0, a28960; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma8961; RV64ZVE32F-NEXT:    vslidedown.vi v11, v8, 38962; RV64ZVE32F-NEXT:    vse32.v v11, (a2)8963; RV64ZVE32F-NEXT:  .LBB81_8: # %else68964; RV64ZVE32F-NEXT:    andi a2, a1, 168965; RV64ZVE32F-NEXT:    vsetivli zero, 4, e16, m1, ta, ma8966; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 48967; RV64ZVE32F-NEXT:    beqz a2, .LBB81_108968; RV64ZVE32F-NEXT:  # %bb.9: # %cond.store78969; RV64ZVE32F-NEXT:    vmv.x.s a2, v108970; RV64ZVE32F-NEXT:    slli a2, a2, 28971; RV64ZVE32F-NEXT:    add a2, a0, a28972; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma8973; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 48974; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma8975; RV64ZVE32F-NEXT:    vse32.v v12, (a2)8976; RV64ZVE32F-NEXT:  .LBB81_10: # %else88977; RV64ZVE32F-NEXT:    andi a2, a1, 328978; RV64ZVE32F-NEXT:    beqz a2, .LBB81_128979; RV64ZVE32F-NEXT:  # %bb.11: # %cond.store98980; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma8981; RV64ZVE32F-NEXT:    vslidedown.vi v11, v10, 18982; RV64ZVE32F-NEXT:    vmv.x.s a2, v118983; RV64ZVE32F-NEXT:    slli a2, a2, 28984; RV64ZVE32F-NEXT:    add a2, a0, a28985; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma8986; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 58987; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma8988; RV64ZVE32F-NEXT:    vse32.v v12, (a2)8989; RV64ZVE32F-NEXT:  .LBB81_12: # %else108990; RV64ZVE32F-NEXT:    andi a2, a1, 648991; RV64ZVE32F-NEXT:    vsetivli zero, 2, e16, mf2, ta, ma8992; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 28993; RV64ZVE32F-NEXT:    bnez a2, .LBB81_158994; RV64ZVE32F-NEXT:  # %bb.13: # %else128995; RV64ZVE32F-NEXT:    andi a1, a1, -1288996; RV64ZVE32F-NEXT:    bnez a1, .LBB81_168997; RV64ZVE32F-NEXT:  .LBB81_14: # %else148998; RV64ZVE32F-NEXT:    ret8999; RV64ZVE32F-NEXT:  .LBB81_15: # %cond.store119000; RV64ZVE32F-NEXT:    vmv.x.s a2, v109001; RV64ZVE32F-NEXT:    slli a2, a2, 29002; RV64ZVE32F-NEXT:    add a2, a0, a29003; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma9004; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 69005; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma9006; RV64ZVE32F-NEXT:    vse32.v v12, (a2)9007; RV64ZVE32F-NEXT:    andi a1, a1, -1289008; RV64ZVE32F-NEXT:    beqz a1, .LBB81_149009; RV64ZVE32F-NEXT:  .LBB81_16: # %cond.store139010; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma9011; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 19012; RV64ZVE32F-NEXT:    vmv.x.s a1, v109013; RV64ZVE32F-NEXT:    slli a1, a1, 29014; RV64ZVE32F-NEXT:    add a0, a0, a19015; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma9016; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 79017; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma9018; RV64ZVE32F-NEXT:    vse32.v v8, (a0)9019; RV64ZVE32F-NEXT:    ret9020  %ptrs = getelementptr inbounds float, ptr %base, <8 x i16> %idxs9021  call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> %val, <8 x ptr> %ptrs, i32 4, <8 x i1> %m)9022  ret void9023}9024 9025define void @mscatter_baseidx_sext_v8i16_v8f32(<8 x float> %val, ptr %base, <8 x i16> %idxs, <8 x i1> %m) {9026; RV32-LABEL: mscatter_baseidx_sext_v8i16_v8f32:9027; RV32:       # %bb.0:9028; RV32-NEXT:    li a1, 49029; RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma9030; RV32-NEXT:    vwmulsu.vx v12, v10, a19031; RV32-NEXT:    vsetvli zero, zero, e32, m2, ta, ma9032; RV32-NEXT:    vsoxei32.v v8, (a0), v12, v0.t9033; RV32-NEXT:    ret9034;9035; RV64V-LABEL: mscatter_baseidx_sext_v8i16_v8f32:9036; RV64V:       # %bb.0:9037; RV64V-NEXT:    vsetivli zero, 8, e64, m4, ta, ma9038; RV64V-NEXT:    vsext.vf4 v12, v109039; RV64V-NEXT:    vsll.vi v12, v12, 29040; RV64V-NEXT:    vsetvli zero, zero, e32, m2, ta, ma9041; RV64V-NEXT:    vsoxei64.v v8, (a0), v12, v0.t9042; RV64V-NEXT:    ret9043;9044; RV64ZVE32F-LABEL: mscatter_baseidx_sext_v8i16_v8f32:9045; RV64ZVE32F:       # %bb.0:9046; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma9047; RV64ZVE32F-NEXT:    vmv.x.s a1, v09048; RV64ZVE32F-NEXT:    andi a2, a1, 19049; RV64ZVE32F-NEXT:    beqz a2, .LBB82_29050; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store9051; RV64ZVE32F-NEXT:    vsetvli zero, zero, e16, m2, ta, ma9052; RV64ZVE32F-NEXT:    vmv.x.s a2, v109053; RV64ZVE32F-NEXT:    slli a2, a2, 29054; RV64ZVE32F-NEXT:    add a2, a0, a29055; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma9056; RV64ZVE32F-NEXT:    vse32.v v8, (a2)9057; RV64ZVE32F-NEXT:  .LBB82_2: # %else9058; RV64ZVE32F-NEXT:    andi a2, a1, 29059; RV64ZVE32F-NEXT:    beqz a2, .LBB82_49060; RV64ZVE32F-NEXT:  # %bb.3: # %cond.store19061; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma9062; RV64ZVE32F-NEXT:    vslidedown.vi v11, v10, 19063; RV64ZVE32F-NEXT:    vmv.x.s a2, v119064; RV64ZVE32F-NEXT:    slli a2, a2, 29065; RV64ZVE32F-NEXT:    add a2, a0, a29066; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma9067; RV64ZVE32F-NEXT:    vslidedown.vi v11, v8, 19068; RV64ZVE32F-NEXT:    vse32.v v11, (a2)9069; RV64ZVE32F-NEXT:  .LBB82_4: # %else29070; RV64ZVE32F-NEXT:    andi a2, a1, 49071; RV64ZVE32F-NEXT:    vsetivli zero, 2, e16, mf2, ta, ma9072; RV64ZVE32F-NEXT:    vslidedown.vi v11, v10, 29073; RV64ZVE32F-NEXT:    beqz a2, .LBB82_69074; RV64ZVE32F-NEXT:  # %bb.5: # %cond.store39075; RV64ZVE32F-NEXT:    vmv.x.s a2, v119076; RV64ZVE32F-NEXT:    slli a2, a2, 29077; RV64ZVE32F-NEXT:    add a2, a0, a29078; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma9079; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 29080; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma9081; RV64ZVE32F-NEXT:    vse32.v v12, (a2)9082; RV64ZVE32F-NEXT:  .LBB82_6: # %else49083; RV64ZVE32F-NEXT:    andi a2, a1, 89084; RV64ZVE32F-NEXT:    beqz a2, .LBB82_89085; RV64ZVE32F-NEXT:  # %bb.7: # %cond.store59086; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma9087; RV64ZVE32F-NEXT:    vslidedown.vi v11, v11, 19088; RV64ZVE32F-NEXT:    vmv.x.s a2, v119089; RV64ZVE32F-NEXT:    slli a2, a2, 29090; RV64ZVE32F-NEXT:    add a2, a0, a29091; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma9092; RV64ZVE32F-NEXT:    vslidedown.vi v11, v8, 39093; RV64ZVE32F-NEXT:    vse32.v v11, (a2)9094; RV64ZVE32F-NEXT:  .LBB82_8: # %else69095; RV64ZVE32F-NEXT:    andi a2, a1, 169096; RV64ZVE32F-NEXT:    vsetivli zero, 4, e16, m1, ta, ma9097; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 49098; RV64ZVE32F-NEXT:    beqz a2, .LBB82_109099; RV64ZVE32F-NEXT:  # %bb.9: # %cond.store79100; RV64ZVE32F-NEXT:    vmv.x.s a2, v109101; RV64ZVE32F-NEXT:    slli a2, a2, 29102; RV64ZVE32F-NEXT:    add a2, a0, a29103; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma9104; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 49105; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma9106; RV64ZVE32F-NEXT:    vse32.v v12, (a2)9107; RV64ZVE32F-NEXT:  .LBB82_10: # %else89108; RV64ZVE32F-NEXT:    andi a2, a1, 329109; RV64ZVE32F-NEXT:    beqz a2, .LBB82_129110; RV64ZVE32F-NEXT:  # %bb.11: # %cond.store99111; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma9112; RV64ZVE32F-NEXT:    vslidedown.vi v11, v10, 19113; RV64ZVE32F-NEXT:    vmv.x.s a2, v119114; RV64ZVE32F-NEXT:    slli a2, a2, 29115; RV64ZVE32F-NEXT:    add a2, a0, a29116; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma9117; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 59118; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma9119; RV64ZVE32F-NEXT:    vse32.v v12, (a2)9120; RV64ZVE32F-NEXT:  .LBB82_12: # %else109121; RV64ZVE32F-NEXT:    andi a2, a1, 649122; RV64ZVE32F-NEXT:    vsetivli zero, 2, e16, mf2, ta, ma9123; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 29124; RV64ZVE32F-NEXT:    bnez a2, .LBB82_159125; RV64ZVE32F-NEXT:  # %bb.13: # %else129126; RV64ZVE32F-NEXT:    andi a1, a1, -1289127; RV64ZVE32F-NEXT:    bnez a1, .LBB82_169128; RV64ZVE32F-NEXT:  .LBB82_14: # %else149129; RV64ZVE32F-NEXT:    ret9130; RV64ZVE32F-NEXT:  .LBB82_15: # %cond.store119131; RV64ZVE32F-NEXT:    vmv.x.s a2, v109132; RV64ZVE32F-NEXT:    slli a2, a2, 29133; RV64ZVE32F-NEXT:    add a2, a0, a29134; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma9135; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 69136; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma9137; RV64ZVE32F-NEXT:    vse32.v v12, (a2)9138; RV64ZVE32F-NEXT:    andi a1, a1, -1289139; RV64ZVE32F-NEXT:    beqz a1, .LBB82_149140; RV64ZVE32F-NEXT:  .LBB82_16: # %cond.store139141; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma9142; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 19143; RV64ZVE32F-NEXT:    vmv.x.s a1, v109144; RV64ZVE32F-NEXT:    slli a1, a1, 29145; RV64ZVE32F-NEXT:    add a0, a0, a19146; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma9147; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 79148; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma9149; RV64ZVE32F-NEXT:    vse32.v v8, (a0)9150; RV64ZVE32F-NEXT:    ret9151  %eidxs = sext <8 x i16> %idxs to <8 x i32>9152  %ptrs = getelementptr inbounds float, ptr %base, <8 x i32> %eidxs9153  call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> %val, <8 x ptr> %ptrs, i32 4, <8 x i1> %m)9154  ret void9155}9156 9157define void @mscatter_baseidx_zext_v8i16_v8f32(<8 x float> %val, ptr %base, <8 x i16> %idxs, <8 x i1> %m) {9158; RV32-LABEL: mscatter_baseidx_zext_v8i16_v8f32:9159; RV32:       # %bb.0:9160; RV32-NEXT:    li a1, 49161; RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma9162; RV32-NEXT:    vwmulu.vx v12, v10, a19163; RV32-NEXT:    vsetvli zero, zero, e32, m2, ta, ma9164; RV32-NEXT:    vsoxei32.v v8, (a0), v12, v0.t9165; RV32-NEXT:    ret9166;9167; RV64V-LABEL: mscatter_baseidx_zext_v8i16_v8f32:9168; RV64V:       # %bb.0:9169; RV64V-NEXT:    li a1, 49170; RV64V-NEXT:    vsetivli zero, 8, e16, m1, ta, ma9171; RV64V-NEXT:    vwmulu.vx v12, v10, a19172; RV64V-NEXT:    vsetvli zero, zero, e32, m2, ta, ma9173; RV64V-NEXT:    vsoxei32.v v8, (a0), v12, v0.t9174; RV64V-NEXT:    ret9175;9176; RV64ZVE32F-LABEL: mscatter_baseidx_zext_v8i16_v8f32:9177; RV64ZVE32F:       # %bb.0:9178; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma9179; RV64ZVE32F-NEXT:    vmv.x.s a1, v09180; RV64ZVE32F-NEXT:    andi a2, a1, 19181; RV64ZVE32F-NEXT:    beqz a2, .LBB83_29182; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store9183; RV64ZVE32F-NEXT:    vsetvli zero, zero, e16, m2, ta, ma9184; RV64ZVE32F-NEXT:    vmv.x.s a2, v109185; RV64ZVE32F-NEXT:    slli a2, a2, 489186; RV64ZVE32F-NEXT:    srli a2, a2, 469187; RV64ZVE32F-NEXT:    add a2, a0, a29188; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma9189; RV64ZVE32F-NEXT:    vse32.v v8, (a2)9190; RV64ZVE32F-NEXT:  .LBB83_2: # %else9191; RV64ZVE32F-NEXT:    andi a2, a1, 29192; RV64ZVE32F-NEXT:    beqz a2, .LBB83_49193; RV64ZVE32F-NEXT:  # %bb.3: # %cond.store19194; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma9195; RV64ZVE32F-NEXT:    vslidedown.vi v11, v10, 19196; RV64ZVE32F-NEXT:    vmv.x.s a2, v119197; RV64ZVE32F-NEXT:    slli a2, a2, 489198; RV64ZVE32F-NEXT:    srli a2, a2, 469199; RV64ZVE32F-NEXT:    add a2, a0, a29200; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma9201; RV64ZVE32F-NEXT:    vslidedown.vi v11, v8, 19202; RV64ZVE32F-NEXT:    vse32.v v11, (a2)9203; RV64ZVE32F-NEXT:  .LBB83_4: # %else29204; RV64ZVE32F-NEXT:    andi a2, a1, 49205; RV64ZVE32F-NEXT:    vsetivli zero, 2, e16, mf2, ta, ma9206; RV64ZVE32F-NEXT:    vslidedown.vi v11, v10, 29207; RV64ZVE32F-NEXT:    beqz a2, .LBB83_69208; RV64ZVE32F-NEXT:  # %bb.5: # %cond.store39209; RV64ZVE32F-NEXT:    vmv.x.s a2, v119210; RV64ZVE32F-NEXT:    slli a2, a2, 489211; RV64ZVE32F-NEXT:    srli a2, a2, 469212; RV64ZVE32F-NEXT:    add a2, a0, a29213; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma9214; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 29215; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma9216; RV64ZVE32F-NEXT:    vse32.v v12, (a2)9217; RV64ZVE32F-NEXT:  .LBB83_6: # %else49218; RV64ZVE32F-NEXT:    andi a2, a1, 89219; RV64ZVE32F-NEXT:    beqz a2, .LBB83_89220; RV64ZVE32F-NEXT:  # %bb.7: # %cond.store59221; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma9222; RV64ZVE32F-NEXT:    vslidedown.vi v11, v11, 19223; RV64ZVE32F-NEXT:    vmv.x.s a2, v119224; RV64ZVE32F-NEXT:    slli a2, a2, 489225; RV64ZVE32F-NEXT:    srli a2, a2, 469226; RV64ZVE32F-NEXT:    add a2, a0, a29227; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma9228; RV64ZVE32F-NEXT:    vslidedown.vi v11, v8, 39229; RV64ZVE32F-NEXT:    vse32.v v11, (a2)9230; RV64ZVE32F-NEXT:  .LBB83_8: # %else69231; RV64ZVE32F-NEXT:    andi a2, a1, 169232; RV64ZVE32F-NEXT:    vsetivli zero, 4, e16, m1, ta, ma9233; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 49234; RV64ZVE32F-NEXT:    beqz a2, .LBB83_109235; RV64ZVE32F-NEXT:  # %bb.9: # %cond.store79236; RV64ZVE32F-NEXT:    vmv.x.s a2, v109237; RV64ZVE32F-NEXT:    slli a2, a2, 489238; RV64ZVE32F-NEXT:    srli a2, a2, 469239; RV64ZVE32F-NEXT:    add a2, a0, a29240; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma9241; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 49242; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma9243; RV64ZVE32F-NEXT:    vse32.v v12, (a2)9244; RV64ZVE32F-NEXT:  .LBB83_10: # %else89245; RV64ZVE32F-NEXT:    andi a2, a1, 329246; RV64ZVE32F-NEXT:    beqz a2, .LBB83_129247; RV64ZVE32F-NEXT:  # %bb.11: # %cond.store99248; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma9249; RV64ZVE32F-NEXT:    vslidedown.vi v11, v10, 19250; RV64ZVE32F-NEXT:    vmv.x.s a2, v119251; RV64ZVE32F-NEXT:    slli a2, a2, 489252; RV64ZVE32F-NEXT:    srli a2, a2, 469253; RV64ZVE32F-NEXT:    add a2, a0, a29254; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma9255; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 59256; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma9257; RV64ZVE32F-NEXT:    vse32.v v12, (a2)9258; RV64ZVE32F-NEXT:  .LBB83_12: # %else109259; RV64ZVE32F-NEXT:    andi a2, a1, 649260; RV64ZVE32F-NEXT:    vsetivli zero, 2, e16, mf2, ta, ma9261; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 29262; RV64ZVE32F-NEXT:    bnez a2, .LBB83_159263; RV64ZVE32F-NEXT:  # %bb.13: # %else129264; RV64ZVE32F-NEXT:    andi a1, a1, -1289265; RV64ZVE32F-NEXT:    bnez a1, .LBB83_169266; RV64ZVE32F-NEXT:  .LBB83_14: # %else149267; RV64ZVE32F-NEXT:    ret9268; RV64ZVE32F-NEXT:  .LBB83_15: # %cond.store119269; RV64ZVE32F-NEXT:    vmv.x.s a2, v109270; RV64ZVE32F-NEXT:    slli a2, a2, 489271; RV64ZVE32F-NEXT:    srli a2, a2, 469272; RV64ZVE32F-NEXT:    add a2, a0, a29273; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma9274; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 69275; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma9276; RV64ZVE32F-NEXT:    vse32.v v12, (a2)9277; RV64ZVE32F-NEXT:    andi a1, a1, -1289278; RV64ZVE32F-NEXT:    beqz a1, .LBB83_149279; RV64ZVE32F-NEXT:  .LBB83_16: # %cond.store139280; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma9281; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 19282; RV64ZVE32F-NEXT:    vmv.x.s a1, v109283; RV64ZVE32F-NEXT:    slli a1, a1, 489284; RV64ZVE32F-NEXT:    srli a1, a1, 469285; RV64ZVE32F-NEXT:    add a0, a0, a19286; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma9287; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 79288; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma9289; RV64ZVE32F-NEXT:    vse32.v v8, (a0)9290; RV64ZVE32F-NEXT:    ret9291  %eidxs = zext <8 x i16> %idxs to <8 x i32>9292  %ptrs = getelementptr inbounds float, ptr %base, <8 x i32> %eidxs9293  call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> %val, <8 x ptr> %ptrs, i32 4, <8 x i1> %m)9294  ret void9295}9296 9297define void @mscatter_baseidx_v8f32(<8 x float> %val, ptr %base, <8 x i32> %idxs, <8 x i1> %m) {9298; RV32-LABEL: mscatter_baseidx_v8f32:9299; RV32:       # %bb.0:9300; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma9301; RV32-NEXT:    vsll.vi v10, v10, 29302; RV32-NEXT:    vsoxei32.v v8, (a0), v10, v0.t9303; RV32-NEXT:    ret9304;9305; RV64V-LABEL: mscatter_baseidx_v8f32:9306; RV64V:       # %bb.0:9307; RV64V-NEXT:    li a1, 49308; RV64V-NEXT:    vsetivli zero, 8, e32, m2, ta, ma9309; RV64V-NEXT:    vwmulsu.vx v12, v10, a19310; RV64V-NEXT:    vsoxei64.v v8, (a0), v12, v0.t9311; RV64V-NEXT:    ret9312;9313; RV64ZVE32F-LABEL: mscatter_baseidx_v8f32:9314; RV64ZVE32F:       # %bb.0:9315; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma9316; RV64ZVE32F-NEXT:    vmv.x.s a1, v09317; RV64ZVE32F-NEXT:    andi a2, a1, 19318; RV64ZVE32F-NEXT:    beqz a2, .LBB84_29319; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store9320; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma9321; RV64ZVE32F-NEXT:    vmv.x.s a2, v109322; RV64ZVE32F-NEXT:    slli a2, a2, 29323; RV64ZVE32F-NEXT:    add a2, a0, a29324; RV64ZVE32F-NEXT:    vse32.v v8, (a2)9325; RV64ZVE32F-NEXT:  .LBB84_2: # %else9326; RV64ZVE32F-NEXT:    andi a2, a1, 29327; RV64ZVE32F-NEXT:    beqz a2, .LBB84_49328; RV64ZVE32F-NEXT:  # %bb.3: # %cond.store19329; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma9330; RV64ZVE32F-NEXT:    vslidedown.vi v12, v10, 19331; RV64ZVE32F-NEXT:    vmv.x.s a2, v129332; RV64ZVE32F-NEXT:    slli a2, a2, 29333; RV64ZVE32F-NEXT:    add a2, a0, a29334; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 19335; RV64ZVE32F-NEXT:    vse32.v v12, (a2)9336; RV64ZVE32F-NEXT:  .LBB84_4: # %else29337; RV64ZVE32F-NEXT:    andi a2, a1, 49338; RV64ZVE32F-NEXT:    vsetivli zero, 2, e32, m1, ta, ma9339; RV64ZVE32F-NEXT:    vslidedown.vi v12, v10, 29340; RV64ZVE32F-NEXT:    beqz a2, .LBB84_69341; RV64ZVE32F-NEXT:  # %bb.5: # %cond.store39342; RV64ZVE32F-NEXT:    vmv.x.s a2, v129343; RV64ZVE32F-NEXT:    slli a2, a2, 29344; RV64ZVE32F-NEXT:    add a2, a0, a29345; RV64ZVE32F-NEXT:    vslidedown.vi v13, v8, 29346; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma9347; RV64ZVE32F-NEXT:    vse32.v v13, (a2)9348; RV64ZVE32F-NEXT:  .LBB84_6: # %else49349; RV64ZVE32F-NEXT:    andi a2, a1, 89350; RV64ZVE32F-NEXT:    vsetivli zero, 4, e32, m2, ta, ma9351; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 49352; RV64ZVE32F-NEXT:    bnez a2, .LBB84_139353; RV64ZVE32F-NEXT:  # %bb.7: # %else69354; RV64ZVE32F-NEXT:    andi a2, a1, 169355; RV64ZVE32F-NEXT:    bnez a2, .LBB84_149356; RV64ZVE32F-NEXT:  .LBB84_8: # %else89357; RV64ZVE32F-NEXT:    andi a2, a1, 329358; RV64ZVE32F-NEXT:    beqz a2, .LBB84_109359; RV64ZVE32F-NEXT:  .LBB84_9: # %cond.store99360; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma9361; RV64ZVE32F-NEXT:    vslidedown.vi v11, v10, 19362; RV64ZVE32F-NEXT:    vmv.x.s a2, v119363; RV64ZVE32F-NEXT:    slli a2, a2, 29364; RV64ZVE32F-NEXT:    add a2, a0, a29365; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma9366; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 59367; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma9368; RV64ZVE32F-NEXT:    vse32.v v12, (a2)9369; RV64ZVE32F-NEXT:  .LBB84_10: # %else109370; RV64ZVE32F-NEXT:    andi a2, a1, 649371; RV64ZVE32F-NEXT:    vsetivli zero, 2, e32, m1, ta, ma9372; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 29373; RV64ZVE32F-NEXT:    bnez a2, .LBB84_159374; RV64ZVE32F-NEXT:  # %bb.11: # %else129375; RV64ZVE32F-NEXT:    andi a1, a1, -1289376; RV64ZVE32F-NEXT:    bnez a1, .LBB84_169377; RV64ZVE32F-NEXT:  .LBB84_12: # %else149378; RV64ZVE32F-NEXT:    ret9379; RV64ZVE32F-NEXT:  .LBB84_13: # %cond.store59380; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma9381; RV64ZVE32F-NEXT:    vslidedown.vi v11, v12, 19382; RV64ZVE32F-NEXT:    vmv.x.s a2, v119383; RV64ZVE32F-NEXT:    slli a2, a2, 29384; RV64ZVE32F-NEXT:    add a2, a0, a29385; RV64ZVE32F-NEXT:    vslidedown.vi v11, v8, 39386; RV64ZVE32F-NEXT:    vse32.v v11, (a2)9387; RV64ZVE32F-NEXT:    andi a2, a1, 169388; RV64ZVE32F-NEXT:    beqz a2, .LBB84_89389; RV64ZVE32F-NEXT:  .LBB84_14: # %cond.store79390; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma9391; RV64ZVE32F-NEXT:    vmv.x.s a2, v109392; RV64ZVE32F-NEXT:    slli a2, a2, 29393; RV64ZVE32F-NEXT:    add a2, a0, a29394; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 49395; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma9396; RV64ZVE32F-NEXT:    vse32.v v12, (a2)9397; RV64ZVE32F-NEXT:    andi a2, a1, 329398; RV64ZVE32F-NEXT:    bnez a2, .LBB84_99399; RV64ZVE32F-NEXT:    j .LBB84_109400; RV64ZVE32F-NEXT:  .LBB84_15: # %cond.store119401; RV64ZVE32F-NEXT:    vmv.x.s a2, v109402; RV64ZVE32F-NEXT:    slli a2, a2, 29403; RV64ZVE32F-NEXT:    add a2, a0, a29404; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma9405; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 69406; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma9407; RV64ZVE32F-NEXT:    vse32.v v12, (a2)9408; RV64ZVE32F-NEXT:    andi a1, a1, -1289409; RV64ZVE32F-NEXT:    beqz a1, .LBB84_129410; RV64ZVE32F-NEXT:  .LBB84_16: # %cond.store139411; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma9412; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 19413; RV64ZVE32F-NEXT:    vmv.x.s a1, v109414; RV64ZVE32F-NEXT:    slli a1, a1, 29415; RV64ZVE32F-NEXT:    add a0, a0, a19416; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma9417; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 79418; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma9419; RV64ZVE32F-NEXT:    vse32.v v8, (a0)9420; RV64ZVE32F-NEXT:    ret9421  %ptrs = getelementptr inbounds float, ptr %base, <8 x i32> %idxs9422  call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> %val, <8 x ptr> %ptrs, i32 4, <8 x i1> %m)9423  ret void9424}9425 9426define void @mscatter_v1f64(<1 x double> %val, <1 x ptr> %ptrs, <1 x i1> %m) {9427; RV32V-LABEL: mscatter_v1f64:9428; RV32V:       # %bb.0:9429; RV32V-NEXT:    vsetivli zero, 1, e64, m1, ta, ma9430; RV32V-NEXT:    vsoxei32.v v8, (zero), v9, v0.t9431; RV32V-NEXT:    ret9432;9433; RV64V-LABEL: mscatter_v1f64:9434; RV64V:       # %bb.0:9435; RV64V-NEXT:    vsetivli zero, 1, e64, m1, ta, ma9436; RV64V-NEXT:    vsoxei64.v v8, (zero), v9, v0.t9437; RV64V-NEXT:    ret9438;9439; RV32ZVE32F-LABEL: mscatter_v1f64:9440; RV32ZVE32F:       # %bb.0:9441; RV32ZVE32F-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma9442; RV32ZVE32F-NEXT:    vfirst.m a0, v09443; RV32ZVE32F-NEXT:    bnez a0, .LBB85_29444; RV32ZVE32F-NEXT:  # %bb.1: # %cond.store9445; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma9446; RV32ZVE32F-NEXT:    vmv.x.s a0, v89447; RV32ZVE32F-NEXT:    fsd fa0, 0(a0)9448; RV32ZVE32F-NEXT:  .LBB85_2: # %else9449; RV32ZVE32F-NEXT:    ret9450;9451; RV64ZVE32F-LABEL: mscatter_v1f64:9452; RV64ZVE32F:       # %bb.0:9453; RV64ZVE32F-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma9454; RV64ZVE32F-NEXT:    vfirst.m a1, v09455; RV64ZVE32F-NEXT:    bnez a1, .LBB85_29456; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store9457; RV64ZVE32F-NEXT:    fsd fa0, 0(a0)9458; RV64ZVE32F-NEXT:  .LBB85_2: # %else9459; RV64ZVE32F-NEXT:    ret9460  call void @llvm.masked.scatter.v1f64.v1p0(<1 x double> %val, <1 x ptr> %ptrs, i32 8, <1 x i1> %m)9461  ret void9462}9463 9464define void @mscatter_v2f64(<2 x double> %val, <2 x ptr> %ptrs, <2 x i1> %m) {9465; RV32V-LABEL: mscatter_v2f64:9466; RV32V:       # %bb.0:9467; RV32V-NEXT:    vsetivli zero, 2, e64, m1, ta, ma9468; RV32V-NEXT:    vsoxei32.v v8, (zero), v9, v0.t9469; RV32V-NEXT:    ret9470;9471; RV64V-LABEL: mscatter_v2f64:9472; RV64V:       # %bb.0:9473; RV64V-NEXT:    vsetivli zero, 2, e64, m1, ta, ma9474; RV64V-NEXT:    vsoxei64.v v8, (zero), v9, v0.t9475; RV64V-NEXT:    ret9476;9477; RV32ZVE32F-LABEL: mscatter_v2f64:9478; RV32ZVE32F:       # %bb.0:9479; RV32ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma9480; RV32ZVE32F-NEXT:    vmv.x.s a0, v09481; RV32ZVE32F-NEXT:    andi a1, a0, 19482; RV32ZVE32F-NEXT:    bnez a1, .LBB86_39483; RV32ZVE32F-NEXT:  # %bb.1: # %else9484; RV32ZVE32F-NEXT:    andi a0, a0, 29485; RV32ZVE32F-NEXT:    bnez a0, .LBB86_49486; RV32ZVE32F-NEXT:  .LBB86_2: # %else29487; RV32ZVE32F-NEXT:    ret9488; RV32ZVE32F-NEXT:  .LBB86_3: # %cond.store9489; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m4, ta, ma9490; RV32ZVE32F-NEXT:    vmv.x.s a1, v89491; RV32ZVE32F-NEXT:    fsd fa0, 0(a1)9492; RV32ZVE32F-NEXT:    andi a0, a0, 29493; RV32ZVE32F-NEXT:    beqz a0, .LBB86_29494; RV32ZVE32F-NEXT:  .LBB86_4: # %cond.store19495; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma9496; RV32ZVE32F-NEXT:    vslidedown.vi v8, v8, 19497; RV32ZVE32F-NEXT:    vmv.x.s a0, v89498; RV32ZVE32F-NEXT:    fsd fa1, 0(a0)9499; RV32ZVE32F-NEXT:    ret9500;9501; RV64ZVE32F-LABEL: mscatter_v2f64:9502; RV64ZVE32F:       # %bb.0:9503; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma9504; RV64ZVE32F-NEXT:    vmv.x.s a2, v09505; RV64ZVE32F-NEXT:    andi a3, a2, 19506; RV64ZVE32F-NEXT:    bnez a3, .LBB86_39507; RV64ZVE32F-NEXT:  # %bb.1: # %else9508; RV64ZVE32F-NEXT:    andi a2, a2, 29509; RV64ZVE32F-NEXT:    bnez a2, .LBB86_49510; RV64ZVE32F-NEXT:  .LBB86_2: # %else29511; RV64ZVE32F-NEXT:    ret9512; RV64ZVE32F-NEXT:  .LBB86_3: # %cond.store9513; RV64ZVE32F-NEXT:    fsd fa0, 0(a0)9514; RV64ZVE32F-NEXT:    andi a2, a2, 29515; RV64ZVE32F-NEXT:    beqz a2, .LBB86_29516; RV64ZVE32F-NEXT:  .LBB86_4: # %cond.store19517; RV64ZVE32F-NEXT:    fsd fa1, 0(a1)9518; RV64ZVE32F-NEXT:    ret9519  call void @llvm.masked.scatter.v2f64.v2p0(<2 x double> %val, <2 x ptr> %ptrs, i32 8, <2 x i1> %m)9520  ret void9521}9522 9523define void @mscatter_v4f64(<4 x double> %val, <4 x ptr> %ptrs, <4 x i1> %m) {9524; RV32V-LABEL: mscatter_v4f64:9525; RV32V:       # %bb.0:9526; RV32V-NEXT:    vsetivli zero, 4, e64, m2, ta, ma9527; RV32V-NEXT:    vsoxei32.v v8, (zero), v10, v0.t9528; RV32V-NEXT:    ret9529;9530; RV64V-LABEL: mscatter_v4f64:9531; RV64V:       # %bb.0:9532; RV64V-NEXT:    vsetivli zero, 4, e64, m2, ta, ma9533; RV64V-NEXT:    vsoxei64.v v8, (zero), v10, v0.t9534; RV64V-NEXT:    ret9535;9536; RV32ZVE32F-LABEL: mscatter_v4f64:9537; RV32ZVE32F:       # %bb.0:9538; RV32ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma9539; RV32ZVE32F-NEXT:    vmv.x.s a0, v09540; RV32ZVE32F-NEXT:    andi a1, a0, 19541; RV32ZVE32F-NEXT:    bnez a1, .LBB87_59542; RV32ZVE32F-NEXT:  # %bb.1: # %else9543; RV32ZVE32F-NEXT:    andi a1, a0, 29544; RV32ZVE32F-NEXT:    bnez a1, .LBB87_69545; RV32ZVE32F-NEXT:  .LBB87_2: # %else29546; RV32ZVE32F-NEXT:    andi a1, a0, 49547; RV32ZVE32F-NEXT:    bnez a1, .LBB87_79548; RV32ZVE32F-NEXT:  .LBB87_3: # %else49549; RV32ZVE32F-NEXT:    andi a0, a0, 89550; RV32ZVE32F-NEXT:    bnez a0, .LBB87_89551; RV32ZVE32F-NEXT:  .LBB87_4: # %else69552; RV32ZVE32F-NEXT:    ret9553; RV32ZVE32F-NEXT:  .LBB87_5: # %cond.store9554; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m4, ta, ma9555; RV32ZVE32F-NEXT:    vmv.x.s a1, v89556; RV32ZVE32F-NEXT:    fsd fa0, 0(a1)9557; RV32ZVE32F-NEXT:    andi a1, a0, 29558; RV32ZVE32F-NEXT:    beqz a1, .LBB87_29559; RV32ZVE32F-NEXT:  .LBB87_6: # %cond.store19560; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma9561; RV32ZVE32F-NEXT:    vslidedown.vi v9, v8, 19562; RV32ZVE32F-NEXT:    vmv.x.s a1, v99563; RV32ZVE32F-NEXT:    fsd fa1, 0(a1)9564; RV32ZVE32F-NEXT:    andi a1, a0, 49565; RV32ZVE32F-NEXT:    beqz a1, .LBB87_39566; RV32ZVE32F-NEXT:  .LBB87_7: # %cond.store39567; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma9568; RV32ZVE32F-NEXT:    vslidedown.vi v9, v8, 29569; RV32ZVE32F-NEXT:    vmv.x.s a1, v99570; RV32ZVE32F-NEXT:    fsd fa2, 0(a1)9571; RV32ZVE32F-NEXT:    andi a0, a0, 89572; RV32ZVE32F-NEXT:    beqz a0, .LBB87_49573; RV32ZVE32F-NEXT:  .LBB87_8: # %cond.store59574; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma9575; RV32ZVE32F-NEXT:    vslidedown.vi v8, v8, 39576; RV32ZVE32F-NEXT:    vmv.x.s a0, v89577; RV32ZVE32F-NEXT:    fsd fa3, 0(a0)9578; RV32ZVE32F-NEXT:    ret9579;9580; RV64ZVE32F-LABEL: mscatter_v4f64:9581; RV64ZVE32F:       # %bb.0:9582; RV64ZVE32F-NEXT:    ld a4, 8(a0)9583; RV64ZVE32F-NEXT:    ld a2, 16(a0)9584; RV64ZVE32F-NEXT:    ld a1, 24(a0)9585; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma9586; RV64ZVE32F-NEXT:    vmv.x.s a3, v09587; RV64ZVE32F-NEXT:    andi a5, a3, 19588; RV64ZVE32F-NEXT:    bnez a5, .LBB87_59589; RV64ZVE32F-NEXT:  # %bb.1: # %else9590; RV64ZVE32F-NEXT:    andi a0, a3, 29591; RV64ZVE32F-NEXT:    bnez a0, .LBB87_69592; RV64ZVE32F-NEXT:  .LBB87_2: # %else29593; RV64ZVE32F-NEXT:    andi a0, a3, 49594; RV64ZVE32F-NEXT:    bnez a0, .LBB87_79595; RV64ZVE32F-NEXT:  .LBB87_3: # %else49596; RV64ZVE32F-NEXT:    andi a3, a3, 89597; RV64ZVE32F-NEXT:    bnez a3, .LBB87_89598; RV64ZVE32F-NEXT:  .LBB87_4: # %else69599; RV64ZVE32F-NEXT:    ret9600; RV64ZVE32F-NEXT:  .LBB87_5: # %cond.store9601; RV64ZVE32F-NEXT:    ld a0, 0(a0)9602; RV64ZVE32F-NEXT:    fsd fa0, 0(a0)9603; RV64ZVE32F-NEXT:    andi a0, a3, 29604; RV64ZVE32F-NEXT:    beqz a0, .LBB87_29605; RV64ZVE32F-NEXT:  .LBB87_6: # %cond.store19606; RV64ZVE32F-NEXT:    fsd fa1, 0(a4)9607; RV64ZVE32F-NEXT:    andi a0, a3, 49608; RV64ZVE32F-NEXT:    beqz a0, .LBB87_39609; RV64ZVE32F-NEXT:  .LBB87_7: # %cond.store39610; RV64ZVE32F-NEXT:    fsd fa2, 0(a2)9611; RV64ZVE32F-NEXT:    andi a3, a3, 89612; RV64ZVE32F-NEXT:    beqz a3, .LBB87_49613; RV64ZVE32F-NEXT:  .LBB87_8: # %cond.store59614; RV64ZVE32F-NEXT:    fsd fa3, 0(a1)9615; RV64ZVE32F-NEXT:    ret9616  call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> %val, <4 x ptr> %ptrs, i32 8, <4 x i1> %m)9617  ret void9618}9619 9620define void @mscatter_truemask_v4f64(<4 x double> %val, <4 x ptr> %ptrs) {9621; RV32V-LABEL: mscatter_truemask_v4f64:9622; RV32V:       # %bb.0:9623; RV32V-NEXT:    vsetivli zero, 4, e64, m2, ta, ma9624; RV32V-NEXT:    vsoxei32.v v8, (zero), v109625; RV32V-NEXT:    ret9626;9627; RV64V-LABEL: mscatter_truemask_v4f64:9628; RV64V:       # %bb.0:9629; RV64V-NEXT:    vsetivli zero, 4, e64, m2, ta, ma9630; RV64V-NEXT:    vsoxei64.v v8, (zero), v109631; RV64V-NEXT:    ret9632;9633; RV32ZVE32F-LABEL: mscatter_truemask_v4f64:9634; RV32ZVE32F:       # %bb.0:9635; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma9636; RV32ZVE32F-NEXT:    vmv.x.s a0, v89637; RV32ZVE32F-NEXT:    vslidedown.vi v9, v8, 19638; RV32ZVE32F-NEXT:    fsd fa0, 0(a0)9639; RV32ZVE32F-NEXT:    vmv.x.s a0, v99640; RV32ZVE32F-NEXT:    vslidedown.vi v9, v8, 29641; RV32ZVE32F-NEXT:    vslidedown.vi v8, v8, 39642; RV32ZVE32F-NEXT:    fsd fa1, 0(a0)9643; RV32ZVE32F-NEXT:    vmv.x.s a0, v99644; RV32ZVE32F-NEXT:    fsd fa2, 0(a0)9645; RV32ZVE32F-NEXT:    vmv.x.s a0, v89646; RV32ZVE32F-NEXT:    fsd fa3, 0(a0)9647; RV32ZVE32F-NEXT:    ret9648;9649; RV64ZVE32F-LABEL: mscatter_truemask_v4f64:9650; RV64ZVE32F:       # %bb.0:9651; RV64ZVE32F-NEXT:    ld a1, 0(a0)9652; RV64ZVE32F-NEXT:    ld a2, 8(a0)9653; RV64ZVE32F-NEXT:    ld a3, 16(a0)9654; RV64ZVE32F-NEXT:    ld a0, 24(a0)9655; RV64ZVE32F-NEXT:    fsd fa0, 0(a1)9656; RV64ZVE32F-NEXT:    fsd fa1, 0(a2)9657; RV64ZVE32F-NEXT:    fsd fa2, 0(a3)9658; RV64ZVE32F-NEXT:    fsd fa3, 0(a0)9659; RV64ZVE32F-NEXT:    ret9660  call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> %val, <4 x ptr> %ptrs, i32 8, <4 x i1> splat (i1 1))9661  ret void9662}9663 9664define void @mscatter_falsemask_v4f64(<4 x double> %val, <4 x ptr> %ptrs) {9665; CHECK-LABEL: mscatter_falsemask_v4f64:9666; CHECK:       # %bb.0:9667; CHECK-NEXT:    ret9668  call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> %val, <4 x ptr> %ptrs, i32 8, <4 x i1> zeroinitializer)9669  ret void9670}9671 9672define void @mscatter_v8f64(<8 x double> %val, <8 x ptr> %ptrs, <8 x i1> %m) {9673; RV32V-LABEL: mscatter_v8f64:9674; RV32V:       # %bb.0:9675; RV32V-NEXT:    vsetivli zero, 8, e64, m4, ta, ma9676; RV32V-NEXT:    vsoxei32.v v8, (zero), v12, v0.t9677; RV32V-NEXT:    ret9678;9679; RV64V-LABEL: mscatter_v8f64:9680; RV64V:       # %bb.0:9681; RV64V-NEXT:    vsetivli zero, 8, e64, m4, ta, ma9682; RV64V-NEXT:    vsoxei64.v v8, (zero), v12, v0.t9683; RV64V-NEXT:    ret9684;9685; RV32ZVE32F-LABEL: mscatter_v8f64:9686; RV32ZVE32F:       # %bb.0:9687; RV32ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma9688; RV32ZVE32F-NEXT:    vmv.x.s a0, v09689; RV32ZVE32F-NEXT:    andi a1, a0, 19690; RV32ZVE32F-NEXT:    bnez a1, .LBB90_99691; RV32ZVE32F-NEXT:  # %bb.1: # %else9692; RV32ZVE32F-NEXT:    andi a1, a0, 29693; RV32ZVE32F-NEXT:    bnez a1, .LBB90_109694; RV32ZVE32F-NEXT:  .LBB90_2: # %else29695; RV32ZVE32F-NEXT:    andi a1, a0, 49696; RV32ZVE32F-NEXT:    bnez a1, .LBB90_119697; RV32ZVE32F-NEXT:  .LBB90_3: # %else49698; RV32ZVE32F-NEXT:    andi a1, a0, 89699; RV32ZVE32F-NEXT:    bnez a1, .LBB90_129700; RV32ZVE32F-NEXT:  .LBB90_4: # %else69701; RV32ZVE32F-NEXT:    andi a1, a0, 169702; RV32ZVE32F-NEXT:    bnez a1, .LBB90_139703; RV32ZVE32F-NEXT:  .LBB90_5: # %else89704; RV32ZVE32F-NEXT:    andi a1, a0, 329705; RV32ZVE32F-NEXT:    bnez a1, .LBB90_149706; RV32ZVE32F-NEXT:  .LBB90_6: # %else109707; RV32ZVE32F-NEXT:    andi a1, a0, 649708; RV32ZVE32F-NEXT:    bnez a1, .LBB90_159709; RV32ZVE32F-NEXT:  .LBB90_7: # %else129710; RV32ZVE32F-NEXT:    andi a0, a0, -1289711; RV32ZVE32F-NEXT:    bnez a0, .LBB90_169712; RV32ZVE32F-NEXT:  .LBB90_8: # %else149713; RV32ZVE32F-NEXT:    ret9714; RV32ZVE32F-NEXT:  .LBB90_9: # %cond.store9715; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m4, ta, ma9716; RV32ZVE32F-NEXT:    vmv.x.s a1, v89717; RV32ZVE32F-NEXT:    fsd fa0, 0(a1)9718; RV32ZVE32F-NEXT:    andi a1, a0, 29719; RV32ZVE32F-NEXT:    beqz a1, .LBB90_29720; RV32ZVE32F-NEXT:  .LBB90_10: # %cond.store19721; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma9722; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 19723; RV32ZVE32F-NEXT:    vmv.x.s a1, v109724; RV32ZVE32F-NEXT:    fsd fa1, 0(a1)9725; RV32ZVE32F-NEXT:    andi a1, a0, 49726; RV32ZVE32F-NEXT:    beqz a1, .LBB90_39727; RV32ZVE32F-NEXT:  .LBB90_11: # %cond.store39728; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma9729; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 29730; RV32ZVE32F-NEXT:    vmv.x.s a1, v109731; RV32ZVE32F-NEXT:    fsd fa2, 0(a1)9732; RV32ZVE32F-NEXT:    andi a1, a0, 89733; RV32ZVE32F-NEXT:    beqz a1, .LBB90_49734; RV32ZVE32F-NEXT:  .LBB90_12: # %cond.store59735; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma9736; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 39737; RV32ZVE32F-NEXT:    vmv.x.s a1, v109738; RV32ZVE32F-NEXT:    fsd fa3, 0(a1)9739; RV32ZVE32F-NEXT:    andi a1, a0, 169740; RV32ZVE32F-NEXT:    beqz a1, .LBB90_59741; RV32ZVE32F-NEXT:  .LBB90_13: # %cond.store79742; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma9743; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 49744; RV32ZVE32F-NEXT:    vmv.x.s a1, v109745; RV32ZVE32F-NEXT:    fsd fa4, 0(a1)9746; RV32ZVE32F-NEXT:    andi a1, a0, 329747; RV32ZVE32F-NEXT:    beqz a1, .LBB90_69748; RV32ZVE32F-NEXT:  .LBB90_14: # %cond.store99749; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma9750; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 59751; RV32ZVE32F-NEXT:    vmv.x.s a1, v109752; RV32ZVE32F-NEXT:    fsd fa5, 0(a1)9753; RV32ZVE32F-NEXT:    andi a1, a0, 649754; RV32ZVE32F-NEXT:    beqz a1, .LBB90_79755; RV32ZVE32F-NEXT:  .LBB90_15: # %cond.store119756; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma9757; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 69758; RV32ZVE32F-NEXT:    vmv.x.s a1, v109759; RV32ZVE32F-NEXT:    fsd fa6, 0(a1)9760; RV32ZVE32F-NEXT:    andi a0, a0, -1289761; RV32ZVE32F-NEXT:    beqz a0, .LBB90_89762; RV32ZVE32F-NEXT:  .LBB90_16: # %cond.store139763; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma9764; RV32ZVE32F-NEXT:    vslidedown.vi v8, v8, 79765; RV32ZVE32F-NEXT:    vmv.x.s a0, v89766; RV32ZVE32F-NEXT:    fsd fa7, 0(a0)9767; RV32ZVE32F-NEXT:    ret9768;9769; RV64ZVE32F-LABEL: mscatter_v8f64:9770; RV64ZVE32F:       # %bb.0:9771; RV64ZVE32F-NEXT:    ld a3, 40(a0)9772; RV64ZVE32F-NEXT:    ld a2, 48(a0)9773; RV64ZVE32F-NEXT:    ld a1, 56(a0)9774; RV64ZVE32F-NEXT:    ld t0, 8(a0)9775; RV64ZVE32F-NEXT:    ld a7, 16(a0)9776; RV64ZVE32F-NEXT:    ld a6, 24(a0)9777; RV64ZVE32F-NEXT:    ld a5, 32(a0)9778; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma9779; RV64ZVE32F-NEXT:    vmv.x.s a4, v09780; RV64ZVE32F-NEXT:    andi t1, a4, 19781; RV64ZVE32F-NEXT:    bnez t1, .LBB90_99782; RV64ZVE32F-NEXT:  # %bb.1: # %else9783; RV64ZVE32F-NEXT:    andi a0, a4, 29784; RV64ZVE32F-NEXT:    bnez a0, .LBB90_109785; RV64ZVE32F-NEXT:  .LBB90_2: # %else29786; RV64ZVE32F-NEXT:    andi a0, a4, 49787; RV64ZVE32F-NEXT:    bnez a0, .LBB90_119788; RV64ZVE32F-NEXT:  .LBB90_3: # %else49789; RV64ZVE32F-NEXT:    andi a0, a4, 89790; RV64ZVE32F-NEXT:    bnez a0, .LBB90_129791; RV64ZVE32F-NEXT:  .LBB90_4: # %else69792; RV64ZVE32F-NEXT:    andi a0, a4, 169793; RV64ZVE32F-NEXT:    bnez a0, .LBB90_139794; RV64ZVE32F-NEXT:  .LBB90_5: # %else89795; RV64ZVE32F-NEXT:    andi a0, a4, 329796; RV64ZVE32F-NEXT:    bnez a0, .LBB90_149797; RV64ZVE32F-NEXT:  .LBB90_6: # %else109798; RV64ZVE32F-NEXT:    andi a0, a4, 649799; RV64ZVE32F-NEXT:    bnez a0, .LBB90_159800; RV64ZVE32F-NEXT:  .LBB90_7: # %else129801; RV64ZVE32F-NEXT:    andi a0, a4, -1289802; RV64ZVE32F-NEXT:    bnez a0, .LBB90_169803; RV64ZVE32F-NEXT:  .LBB90_8: # %else149804; RV64ZVE32F-NEXT:    ret9805; RV64ZVE32F-NEXT:  .LBB90_9: # %cond.store9806; RV64ZVE32F-NEXT:    ld a0, 0(a0)9807; RV64ZVE32F-NEXT:    fsd fa0, 0(a0)9808; RV64ZVE32F-NEXT:    andi a0, a4, 29809; RV64ZVE32F-NEXT:    beqz a0, .LBB90_29810; RV64ZVE32F-NEXT:  .LBB90_10: # %cond.store19811; RV64ZVE32F-NEXT:    fsd fa1, 0(t0)9812; RV64ZVE32F-NEXT:    andi a0, a4, 49813; RV64ZVE32F-NEXT:    beqz a0, .LBB90_39814; RV64ZVE32F-NEXT:  .LBB90_11: # %cond.store39815; RV64ZVE32F-NEXT:    fsd fa2, 0(a7)9816; RV64ZVE32F-NEXT:    andi a0, a4, 89817; RV64ZVE32F-NEXT:    beqz a0, .LBB90_49818; RV64ZVE32F-NEXT:  .LBB90_12: # %cond.store59819; RV64ZVE32F-NEXT:    fsd fa3, 0(a6)9820; RV64ZVE32F-NEXT:    andi a0, a4, 169821; RV64ZVE32F-NEXT:    beqz a0, .LBB90_59822; RV64ZVE32F-NEXT:  .LBB90_13: # %cond.store79823; RV64ZVE32F-NEXT:    fsd fa4, 0(a5)9824; RV64ZVE32F-NEXT:    andi a0, a4, 329825; RV64ZVE32F-NEXT:    beqz a0, .LBB90_69826; RV64ZVE32F-NEXT:  .LBB90_14: # %cond.store99827; RV64ZVE32F-NEXT:    fsd fa5, 0(a3)9828; RV64ZVE32F-NEXT:    andi a0, a4, 649829; RV64ZVE32F-NEXT:    beqz a0, .LBB90_79830; RV64ZVE32F-NEXT:  .LBB90_15: # %cond.store119831; RV64ZVE32F-NEXT:    fsd fa6, 0(a2)9832; RV64ZVE32F-NEXT:    andi a0, a4, -1289833; RV64ZVE32F-NEXT:    beqz a0, .LBB90_89834; RV64ZVE32F-NEXT:  .LBB90_16: # %cond.store139835; RV64ZVE32F-NEXT:    fsd fa7, 0(a1)9836; RV64ZVE32F-NEXT:    ret9837  call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> %val, <8 x ptr> %ptrs, i32 8, <8 x i1> %m)9838  ret void9839}9840 9841define void @mscatter_baseidx_v8i8_v8f64(<8 x double> %val, ptr %base, <8 x i8> %idxs, <8 x i1> %m) {9842; RV32V-LABEL: mscatter_baseidx_v8i8_v8f64:9843; RV32V:       # %bb.0:9844; RV32V-NEXT:    vsetivli zero, 8, e32, m2, ta, ma9845; RV32V-NEXT:    vsext.vf4 v14, v129846; RV32V-NEXT:    vsll.vi v12, v14, 39847; RV32V-NEXT:    vsetvli zero, zero, e64, m4, ta, ma9848; RV32V-NEXT:    vsoxei32.v v8, (a0), v12, v0.t9849; RV32V-NEXT:    ret9850;9851; RV64V-LABEL: mscatter_baseidx_v8i8_v8f64:9852; RV64V:       # %bb.0:9853; RV64V-NEXT:    vsetivli zero, 8, e64, m4, ta, ma9854; RV64V-NEXT:    vsext.vf8 v16, v129855; RV64V-NEXT:    vsll.vi v12, v16, 39856; RV64V-NEXT:    vsoxei64.v v8, (a0), v12, v0.t9857; RV64V-NEXT:    ret9858;9859; RV32ZVE32F-LABEL: mscatter_baseidx_v8i8_v8f64:9860; RV32ZVE32F:       # %bb.0:9861; RV32ZVE32F-NEXT:    vsetivli zero, 8, e32, m2, ta, ma9862; RV32ZVE32F-NEXT:    vsext.vf4 v10, v89863; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma9864; RV32ZVE32F-NEXT:    vmv.x.s a1, v09865; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma9866; RV32ZVE32F-NEXT:    vsll.vi v8, v10, 39867; RV32ZVE32F-NEXT:    andi a2, a1, 19868; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a09869; RV32ZVE32F-NEXT:    bnez a2, .LBB91_99870; RV32ZVE32F-NEXT:  # %bb.1: # %else9871; RV32ZVE32F-NEXT:    andi a0, a1, 29872; RV32ZVE32F-NEXT:    bnez a0, .LBB91_109873; RV32ZVE32F-NEXT:  .LBB91_2: # %else29874; RV32ZVE32F-NEXT:    andi a0, a1, 49875; RV32ZVE32F-NEXT:    bnez a0, .LBB91_119876; RV32ZVE32F-NEXT:  .LBB91_3: # %else49877; RV32ZVE32F-NEXT:    andi a0, a1, 89878; RV32ZVE32F-NEXT:    bnez a0, .LBB91_129879; RV32ZVE32F-NEXT:  .LBB91_4: # %else69880; RV32ZVE32F-NEXT:    andi a0, a1, 169881; RV32ZVE32F-NEXT:    bnez a0, .LBB91_139882; RV32ZVE32F-NEXT:  .LBB91_5: # %else89883; RV32ZVE32F-NEXT:    andi a0, a1, 329884; RV32ZVE32F-NEXT:    bnez a0, .LBB91_149885; RV32ZVE32F-NEXT:  .LBB91_6: # %else109886; RV32ZVE32F-NEXT:    andi a0, a1, 649887; RV32ZVE32F-NEXT:    bnez a0, .LBB91_159888; RV32ZVE32F-NEXT:  .LBB91_7: # %else129889; RV32ZVE32F-NEXT:    andi a0, a1, -1289890; RV32ZVE32F-NEXT:    bnez a0, .LBB91_169891; RV32ZVE32F-NEXT:  .LBB91_8: # %else149892; RV32ZVE32F-NEXT:    ret9893; RV32ZVE32F-NEXT:  .LBB91_9: # %cond.store9894; RV32ZVE32F-NEXT:    vmv.x.s a0, v89895; RV32ZVE32F-NEXT:    fsd fa0, 0(a0)9896; RV32ZVE32F-NEXT:    andi a0, a1, 29897; RV32ZVE32F-NEXT:    beqz a0, .LBB91_29898; RV32ZVE32F-NEXT:  .LBB91_10: # %cond.store19899; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma9900; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 19901; RV32ZVE32F-NEXT:    vmv.x.s a0, v109902; RV32ZVE32F-NEXT:    fsd fa1, 0(a0)9903; RV32ZVE32F-NEXT:    andi a0, a1, 49904; RV32ZVE32F-NEXT:    beqz a0, .LBB91_39905; RV32ZVE32F-NEXT:  .LBB91_11: # %cond.store39906; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma9907; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 29908; RV32ZVE32F-NEXT:    vmv.x.s a0, v109909; RV32ZVE32F-NEXT:    fsd fa2, 0(a0)9910; RV32ZVE32F-NEXT:    andi a0, a1, 89911; RV32ZVE32F-NEXT:    beqz a0, .LBB91_49912; RV32ZVE32F-NEXT:  .LBB91_12: # %cond.store59913; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma9914; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 39915; RV32ZVE32F-NEXT:    vmv.x.s a0, v109916; RV32ZVE32F-NEXT:    fsd fa3, 0(a0)9917; RV32ZVE32F-NEXT:    andi a0, a1, 169918; RV32ZVE32F-NEXT:    beqz a0, .LBB91_59919; RV32ZVE32F-NEXT:  .LBB91_13: # %cond.store79920; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma9921; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 49922; RV32ZVE32F-NEXT:    vmv.x.s a0, v109923; RV32ZVE32F-NEXT:    fsd fa4, 0(a0)9924; RV32ZVE32F-NEXT:    andi a0, a1, 329925; RV32ZVE32F-NEXT:    beqz a0, .LBB91_69926; RV32ZVE32F-NEXT:  .LBB91_14: # %cond.store99927; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma9928; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 59929; RV32ZVE32F-NEXT:    vmv.x.s a0, v109930; RV32ZVE32F-NEXT:    fsd fa5, 0(a0)9931; RV32ZVE32F-NEXT:    andi a0, a1, 649932; RV32ZVE32F-NEXT:    beqz a0, .LBB91_79933; RV32ZVE32F-NEXT:  .LBB91_15: # %cond.store119934; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma9935; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 69936; RV32ZVE32F-NEXT:    vmv.x.s a0, v109937; RV32ZVE32F-NEXT:    fsd fa6, 0(a0)9938; RV32ZVE32F-NEXT:    andi a0, a1, -1289939; RV32ZVE32F-NEXT:    beqz a0, .LBB91_89940; RV32ZVE32F-NEXT:  .LBB91_16: # %cond.store139941; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma9942; RV32ZVE32F-NEXT:    vslidedown.vi v8, v8, 79943; RV32ZVE32F-NEXT:    vmv.x.s a0, v89944; RV32ZVE32F-NEXT:    fsd fa7, 0(a0)9945; RV32ZVE32F-NEXT:    ret9946;9947; RV64ZVE32F-LABEL: mscatter_baseidx_v8i8_v8f64:9948; RV64ZVE32F:       # %bb.0:9949; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma9950; RV64ZVE32F-NEXT:    vmv.x.s a1, v09951; RV64ZVE32F-NEXT:    andi a2, a1, 19952; RV64ZVE32F-NEXT:    beqz a2, .LBB91_29953; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store9954; RV64ZVE32F-NEXT:    vmv.x.s a2, v89955; RV64ZVE32F-NEXT:    slli a2, a2, 39956; RV64ZVE32F-NEXT:    add a2, a0, a29957; RV64ZVE32F-NEXT:    fsd fa0, 0(a2)9958; RV64ZVE32F-NEXT:  .LBB91_2: # %else9959; RV64ZVE32F-NEXT:    andi a2, a1, 29960; RV64ZVE32F-NEXT:    beqz a2, .LBB91_49961; RV64ZVE32F-NEXT:  # %bb.3: # %cond.store19962; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma9963; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 19964; RV64ZVE32F-NEXT:    vmv.x.s a2, v99965; RV64ZVE32F-NEXT:    slli a2, a2, 39966; RV64ZVE32F-NEXT:    add a2, a0, a29967; RV64ZVE32F-NEXT:    fsd fa1, 0(a2)9968; RV64ZVE32F-NEXT:  .LBB91_4: # %else29969; RV64ZVE32F-NEXT:    andi a2, a1, 49970; RV64ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma9971; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 29972; RV64ZVE32F-NEXT:    beqz a2, .LBB91_69973; RV64ZVE32F-NEXT:  # %bb.5: # %cond.store39974; RV64ZVE32F-NEXT:    vmv.x.s a2, v99975; RV64ZVE32F-NEXT:    slli a2, a2, 39976; RV64ZVE32F-NEXT:    add a2, a0, a29977; RV64ZVE32F-NEXT:    fsd fa2, 0(a2)9978; RV64ZVE32F-NEXT:  .LBB91_6: # %else49979; RV64ZVE32F-NEXT:    andi a2, a1, 89980; RV64ZVE32F-NEXT:    beqz a2, .LBB91_89981; RV64ZVE32F-NEXT:  # %bb.7: # %cond.store59982; RV64ZVE32F-NEXT:    vslidedown.vi v9, v9, 19983; RV64ZVE32F-NEXT:    vmv.x.s a2, v99984; RV64ZVE32F-NEXT:    slli a2, a2, 39985; RV64ZVE32F-NEXT:    add a2, a0, a29986; RV64ZVE32F-NEXT:    fsd fa3, 0(a2)9987; RV64ZVE32F-NEXT:  .LBB91_8: # %else69988; RV64ZVE32F-NEXT:    andi a2, a1, 169989; RV64ZVE32F-NEXT:    vsetivli zero, 4, e8, mf2, ta, ma9990; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 49991; RV64ZVE32F-NEXT:    beqz a2, .LBB91_109992; RV64ZVE32F-NEXT:  # %bb.9: # %cond.store79993; RV64ZVE32F-NEXT:    vmv.x.s a2, v89994; RV64ZVE32F-NEXT:    slli a2, a2, 39995; RV64ZVE32F-NEXT:    add a2, a0, a29996; RV64ZVE32F-NEXT:    fsd fa4, 0(a2)9997; RV64ZVE32F-NEXT:  .LBB91_10: # %else89998; RV64ZVE32F-NEXT:    andi a2, a1, 329999; RV64ZVE32F-NEXT:    beqz a2, .LBB91_1210000; RV64ZVE32F-NEXT:  # %bb.11: # %cond.store910001; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma10002; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 110003; RV64ZVE32F-NEXT:    vmv.x.s a2, v910004; RV64ZVE32F-NEXT:    slli a2, a2, 310005; RV64ZVE32F-NEXT:    add a2, a0, a210006; RV64ZVE32F-NEXT:    fsd fa5, 0(a2)10007; RV64ZVE32F-NEXT:  .LBB91_12: # %else1010008; RV64ZVE32F-NEXT:    andi a2, a1, 6410009; RV64ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma10010; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 210011; RV64ZVE32F-NEXT:    bnez a2, .LBB91_1510012; RV64ZVE32F-NEXT:  # %bb.13: # %else1210013; RV64ZVE32F-NEXT:    andi a1, a1, -12810014; RV64ZVE32F-NEXT:    bnez a1, .LBB91_1610015; RV64ZVE32F-NEXT:  .LBB91_14: # %else1410016; RV64ZVE32F-NEXT:    ret10017; RV64ZVE32F-NEXT:  .LBB91_15: # %cond.store1110018; RV64ZVE32F-NEXT:    vmv.x.s a2, v810019; RV64ZVE32F-NEXT:    slli a2, a2, 310020; RV64ZVE32F-NEXT:    add a2, a0, a210021; RV64ZVE32F-NEXT:    fsd fa6, 0(a2)10022; RV64ZVE32F-NEXT:    andi a1, a1, -12810023; RV64ZVE32F-NEXT:    beqz a1, .LBB91_1410024; RV64ZVE32F-NEXT:  .LBB91_16: # %cond.store1310025; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 110026; RV64ZVE32F-NEXT:    vmv.x.s a1, v810027; RV64ZVE32F-NEXT:    slli a1, a1, 310028; RV64ZVE32F-NEXT:    add a0, a0, a110029; RV64ZVE32F-NEXT:    fsd fa7, 0(a0)10030; RV64ZVE32F-NEXT:    ret10031  %ptrs = getelementptr inbounds double, ptr %base, <8 x i8> %idxs10032  call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> %val, <8 x ptr> %ptrs, i32 8, <8 x i1> %m)10033  ret void10034}10035 10036define void @mscatter_baseidx_sext_v8i8_v8f64(<8 x double> %val, ptr %base, <8 x i8> %idxs, <8 x i1> %m) {10037; RV32V-LABEL: mscatter_baseidx_sext_v8i8_v8f64:10038; RV32V:       # %bb.0:10039; RV32V-NEXT:    vsetivli zero, 8, e32, m2, ta, ma10040; RV32V-NEXT:    vsext.vf4 v14, v1210041; RV32V-NEXT:    vsll.vi v12, v14, 310042; RV32V-NEXT:    vsetvli zero, zero, e64, m4, ta, ma10043; RV32V-NEXT:    vsoxei32.v v8, (a0), v12, v0.t10044; RV32V-NEXT:    ret10045;10046; RV64V-LABEL: mscatter_baseidx_sext_v8i8_v8f64:10047; RV64V:       # %bb.0:10048; RV64V-NEXT:    vsetivli zero, 8, e64, m4, ta, ma10049; RV64V-NEXT:    vsext.vf8 v16, v1210050; RV64V-NEXT:    vsll.vi v12, v16, 310051; RV64V-NEXT:    vsoxei64.v v8, (a0), v12, v0.t10052; RV64V-NEXT:    ret10053;10054; RV32ZVE32F-LABEL: mscatter_baseidx_sext_v8i8_v8f64:10055; RV32ZVE32F:       # %bb.0:10056; RV32ZVE32F-NEXT:    vsetivli zero, 8, e32, m2, ta, ma10057; RV32ZVE32F-NEXT:    vsext.vf4 v10, v810058; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma10059; RV32ZVE32F-NEXT:    vmv.x.s a1, v010060; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma10061; RV32ZVE32F-NEXT:    vsll.vi v8, v10, 310062; RV32ZVE32F-NEXT:    andi a2, a1, 110063; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a010064; RV32ZVE32F-NEXT:    bnez a2, .LBB92_910065; RV32ZVE32F-NEXT:  # %bb.1: # %else10066; RV32ZVE32F-NEXT:    andi a0, a1, 210067; RV32ZVE32F-NEXT:    bnez a0, .LBB92_1010068; RV32ZVE32F-NEXT:  .LBB92_2: # %else210069; RV32ZVE32F-NEXT:    andi a0, a1, 410070; RV32ZVE32F-NEXT:    bnez a0, .LBB92_1110071; RV32ZVE32F-NEXT:  .LBB92_3: # %else410072; RV32ZVE32F-NEXT:    andi a0, a1, 810073; RV32ZVE32F-NEXT:    bnez a0, .LBB92_1210074; RV32ZVE32F-NEXT:  .LBB92_4: # %else610075; RV32ZVE32F-NEXT:    andi a0, a1, 1610076; RV32ZVE32F-NEXT:    bnez a0, .LBB92_1310077; RV32ZVE32F-NEXT:  .LBB92_5: # %else810078; RV32ZVE32F-NEXT:    andi a0, a1, 3210079; RV32ZVE32F-NEXT:    bnez a0, .LBB92_1410080; RV32ZVE32F-NEXT:  .LBB92_6: # %else1010081; RV32ZVE32F-NEXT:    andi a0, a1, 6410082; RV32ZVE32F-NEXT:    bnez a0, .LBB92_1510083; RV32ZVE32F-NEXT:  .LBB92_7: # %else1210084; RV32ZVE32F-NEXT:    andi a0, a1, -12810085; RV32ZVE32F-NEXT:    bnez a0, .LBB92_1610086; RV32ZVE32F-NEXT:  .LBB92_8: # %else1410087; RV32ZVE32F-NEXT:    ret10088; RV32ZVE32F-NEXT:  .LBB92_9: # %cond.store10089; RV32ZVE32F-NEXT:    vmv.x.s a0, v810090; RV32ZVE32F-NEXT:    fsd fa0, 0(a0)10091; RV32ZVE32F-NEXT:    andi a0, a1, 210092; RV32ZVE32F-NEXT:    beqz a0, .LBB92_210093; RV32ZVE32F-NEXT:  .LBB92_10: # %cond.store110094; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma10095; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 110096; RV32ZVE32F-NEXT:    vmv.x.s a0, v1010097; RV32ZVE32F-NEXT:    fsd fa1, 0(a0)10098; RV32ZVE32F-NEXT:    andi a0, a1, 410099; RV32ZVE32F-NEXT:    beqz a0, .LBB92_310100; RV32ZVE32F-NEXT:  .LBB92_11: # %cond.store310101; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma10102; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 210103; RV32ZVE32F-NEXT:    vmv.x.s a0, v1010104; RV32ZVE32F-NEXT:    fsd fa2, 0(a0)10105; RV32ZVE32F-NEXT:    andi a0, a1, 810106; RV32ZVE32F-NEXT:    beqz a0, .LBB92_410107; RV32ZVE32F-NEXT:  .LBB92_12: # %cond.store510108; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma10109; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 310110; RV32ZVE32F-NEXT:    vmv.x.s a0, v1010111; RV32ZVE32F-NEXT:    fsd fa3, 0(a0)10112; RV32ZVE32F-NEXT:    andi a0, a1, 1610113; RV32ZVE32F-NEXT:    beqz a0, .LBB92_510114; RV32ZVE32F-NEXT:  .LBB92_13: # %cond.store710115; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma10116; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 410117; RV32ZVE32F-NEXT:    vmv.x.s a0, v1010118; RV32ZVE32F-NEXT:    fsd fa4, 0(a0)10119; RV32ZVE32F-NEXT:    andi a0, a1, 3210120; RV32ZVE32F-NEXT:    beqz a0, .LBB92_610121; RV32ZVE32F-NEXT:  .LBB92_14: # %cond.store910122; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma10123; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 510124; RV32ZVE32F-NEXT:    vmv.x.s a0, v1010125; RV32ZVE32F-NEXT:    fsd fa5, 0(a0)10126; RV32ZVE32F-NEXT:    andi a0, a1, 6410127; RV32ZVE32F-NEXT:    beqz a0, .LBB92_710128; RV32ZVE32F-NEXT:  .LBB92_15: # %cond.store1110129; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma10130; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 610131; RV32ZVE32F-NEXT:    vmv.x.s a0, v1010132; RV32ZVE32F-NEXT:    fsd fa6, 0(a0)10133; RV32ZVE32F-NEXT:    andi a0, a1, -12810134; RV32ZVE32F-NEXT:    beqz a0, .LBB92_810135; RV32ZVE32F-NEXT:  .LBB92_16: # %cond.store1310136; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma10137; RV32ZVE32F-NEXT:    vslidedown.vi v8, v8, 710138; RV32ZVE32F-NEXT:    vmv.x.s a0, v810139; RV32ZVE32F-NEXT:    fsd fa7, 0(a0)10140; RV32ZVE32F-NEXT:    ret10141;10142; RV64ZVE32F-LABEL: mscatter_baseidx_sext_v8i8_v8f64:10143; RV64ZVE32F:       # %bb.0:10144; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma10145; RV64ZVE32F-NEXT:    vmv.x.s a1, v010146; RV64ZVE32F-NEXT:    andi a2, a1, 110147; RV64ZVE32F-NEXT:    beqz a2, .LBB92_210148; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store10149; RV64ZVE32F-NEXT:    vmv.x.s a2, v810150; RV64ZVE32F-NEXT:    slli a2, a2, 310151; RV64ZVE32F-NEXT:    add a2, a0, a210152; RV64ZVE32F-NEXT:    fsd fa0, 0(a2)10153; RV64ZVE32F-NEXT:  .LBB92_2: # %else10154; RV64ZVE32F-NEXT:    andi a2, a1, 210155; RV64ZVE32F-NEXT:    beqz a2, .LBB92_410156; RV64ZVE32F-NEXT:  # %bb.3: # %cond.store110157; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma10158; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 110159; RV64ZVE32F-NEXT:    vmv.x.s a2, v910160; RV64ZVE32F-NEXT:    slli a2, a2, 310161; RV64ZVE32F-NEXT:    add a2, a0, a210162; RV64ZVE32F-NEXT:    fsd fa1, 0(a2)10163; RV64ZVE32F-NEXT:  .LBB92_4: # %else210164; RV64ZVE32F-NEXT:    andi a2, a1, 410165; RV64ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma10166; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 210167; RV64ZVE32F-NEXT:    beqz a2, .LBB92_610168; RV64ZVE32F-NEXT:  # %bb.5: # %cond.store310169; RV64ZVE32F-NEXT:    vmv.x.s a2, v910170; RV64ZVE32F-NEXT:    slli a2, a2, 310171; RV64ZVE32F-NEXT:    add a2, a0, a210172; RV64ZVE32F-NEXT:    fsd fa2, 0(a2)10173; RV64ZVE32F-NEXT:  .LBB92_6: # %else410174; RV64ZVE32F-NEXT:    andi a2, a1, 810175; RV64ZVE32F-NEXT:    beqz a2, .LBB92_810176; RV64ZVE32F-NEXT:  # %bb.7: # %cond.store510177; RV64ZVE32F-NEXT:    vslidedown.vi v9, v9, 110178; RV64ZVE32F-NEXT:    vmv.x.s a2, v910179; RV64ZVE32F-NEXT:    slli a2, a2, 310180; RV64ZVE32F-NEXT:    add a2, a0, a210181; RV64ZVE32F-NEXT:    fsd fa3, 0(a2)10182; RV64ZVE32F-NEXT:  .LBB92_8: # %else610183; RV64ZVE32F-NEXT:    andi a2, a1, 1610184; RV64ZVE32F-NEXT:    vsetivli zero, 4, e8, mf2, ta, ma10185; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 410186; RV64ZVE32F-NEXT:    beqz a2, .LBB92_1010187; RV64ZVE32F-NEXT:  # %bb.9: # %cond.store710188; RV64ZVE32F-NEXT:    vmv.x.s a2, v810189; RV64ZVE32F-NEXT:    slli a2, a2, 310190; RV64ZVE32F-NEXT:    add a2, a0, a210191; RV64ZVE32F-NEXT:    fsd fa4, 0(a2)10192; RV64ZVE32F-NEXT:  .LBB92_10: # %else810193; RV64ZVE32F-NEXT:    andi a2, a1, 3210194; RV64ZVE32F-NEXT:    beqz a2, .LBB92_1210195; RV64ZVE32F-NEXT:  # %bb.11: # %cond.store910196; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma10197; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 110198; RV64ZVE32F-NEXT:    vmv.x.s a2, v910199; RV64ZVE32F-NEXT:    slli a2, a2, 310200; RV64ZVE32F-NEXT:    add a2, a0, a210201; RV64ZVE32F-NEXT:    fsd fa5, 0(a2)10202; RV64ZVE32F-NEXT:  .LBB92_12: # %else1010203; RV64ZVE32F-NEXT:    andi a2, a1, 6410204; RV64ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma10205; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 210206; RV64ZVE32F-NEXT:    bnez a2, .LBB92_1510207; RV64ZVE32F-NEXT:  # %bb.13: # %else1210208; RV64ZVE32F-NEXT:    andi a1, a1, -12810209; RV64ZVE32F-NEXT:    bnez a1, .LBB92_1610210; RV64ZVE32F-NEXT:  .LBB92_14: # %else1410211; RV64ZVE32F-NEXT:    ret10212; RV64ZVE32F-NEXT:  .LBB92_15: # %cond.store1110213; RV64ZVE32F-NEXT:    vmv.x.s a2, v810214; RV64ZVE32F-NEXT:    slli a2, a2, 310215; RV64ZVE32F-NEXT:    add a2, a0, a210216; RV64ZVE32F-NEXT:    fsd fa6, 0(a2)10217; RV64ZVE32F-NEXT:    andi a1, a1, -12810218; RV64ZVE32F-NEXT:    beqz a1, .LBB92_1410219; RV64ZVE32F-NEXT:  .LBB92_16: # %cond.store1310220; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 110221; RV64ZVE32F-NEXT:    vmv.x.s a1, v810222; RV64ZVE32F-NEXT:    slli a1, a1, 310223; RV64ZVE32F-NEXT:    add a0, a0, a110224; RV64ZVE32F-NEXT:    fsd fa7, 0(a0)10225; RV64ZVE32F-NEXT:    ret10226  %eidxs = sext <8 x i8> %idxs to <8 x i64>10227  %ptrs = getelementptr inbounds double, ptr %base, <8 x i64> %eidxs10228  call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> %val, <8 x ptr> %ptrs, i32 8, <8 x i1> %m)10229  ret void10230}10231 10232define void @mscatter_baseidx_zext_v8i8_v8f64(<8 x double> %val, ptr %base, <8 x i8> %idxs, <8 x i1> %m) {10233; RV32V-LABEL: mscatter_baseidx_zext_v8i8_v8f64:10234; RV32V:       # %bb.0:10235; RV32V-NEXT:    li a1, 810236; RV32V-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma10237; RV32V-NEXT:    vwmulu.vx v13, v12, a110238; RV32V-NEXT:    vsetvli zero, zero, e64, m4, ta, ma10239; RV32V-NEXT:    vsoxei16.v v8, (a0), v13, v0.t10240; RV32V-NEXT:    ret10241;10242; RV64V-LABEL: mscatter_baseidx_zext_v8i8_v8f64:10243; RV64V:       # %bb.0:10244; RV64V-NEXT:    li a1, 810245; RV64V-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma10246; RV64V-NEXT:    vwmulu.vx v13, v12, a110247; RV64V-NEXT:    vsetvli zero, zero, e64, m4, ta, ma10248; RV64V-NEXT:    vsoxei16.v v8, (a0), v13, v0.t10249; RV64V-NEXT:    ret10250;10251; RV32ZVE32F-LABEL: mscatter_baseidx_zext_v8i8_v8f64:10252; RV32ZVE32F:       # %bb.0:10253; RV32ZVE32F-NEXT:    vsetivli zero, 8, e32, m2, ta, ma10254; RV32ZVE32F-NEXT:    vzext.vf4 v10, v810255; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma10256; RV32ZVE32F-NEXT:    vmv.x.s a1, v010257; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma10258; RV32ZVE32F-NEXT:    vsll.vi v8, v10, 310259; RV32ZVE32F-NEXT:    andi a2, a1, 110260; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a010261; RV32ZVE32F-NEXT:    bnez a2, .LBB93_910262; RV32ZVE32F-NEXT:  # %bb.1: # %else10263; RV32ZVE32F-NEXT:    andi a0, a1, 210264; RV32ZVE32F-NEXT:    bnez a0, .LBB93_1010265; RV32ZVE32F-NEXT:  .LBB93_2: # %else210266; RV32ZVE32F-NEXT:    andi a0, a1, 410267; RV32ZVE32F-NEXT:    bnez a0, .LBB93_1110268; RV32ZVE32F-NEXT:  .LBB93_3: # %else410269; RV32ZVE32F-NEXT:    andi a0, a1, 810270; RV32ZVE32F-NEXT:    bnez a0, .LBB93_1210271; RV32ZVE32F-NEXT:  .LBB93_4: # %else610272; RV32ZVE32F-NEXT:    andi a0, a1, 1610273; RV32ZVE32F-NEXT:    bnez a0, .LBB93_1310274; RV32ZVE32F-NEXT:  .LBB93_5: # %else810275; RV32ZVE32F-NEXT:    andi a0, a1, 3210276; RV32ZVE32F-NEXT:    bnez a0, .LBB93_1410277; RV32ZVE32F-NEXT:  .LBB93_6: # %else1010278; RV32ZVE32F-NEXT:    andi a0, a1, 6410279; RV32ZVE32F-NEXT:    bnez a0, .LBB93_1510280; RV32ZVE32F-NEXT:  .LBB93_7: # %else1210281; RV32ZVE32F-NEXT:    andi a0, a1, -12810282; RV32ZVE32F-NEXT:    bnez a0, .LBB93_1610283; RV32ZVE32F-NEXT:  .LBB93_8: # %else1410284; RV32ZVE32F-NEXT:    ret10285; RV32ZVE32F-NEXT:  .LBB93_9: # %cond.store10286; RV32ZVE32F-NEXT:    vmv.x.s a0, v810287; RV32ZVE32F-NEXT:    fsd fa0, 0(a0)10288; RV32ZVE32F-NEXT:    andi a0, a1, 210289; RV32ZVE32F-NEXT:    beqz a0, .LBB93_210290; RV32ZVE32F-NEXT:  .LBB93_10: # %cond.store110291; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma10292; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 110293; RV32ZVE32F-NEXT:    vmv.x.s a0, v1010294; RV32ZVE32F-NEXT:    fsd fa1, 0(a0)10295; RV32ZVE32F-NEXT:    andi a0, a1, 410296; RV32ZVE32F-NEXT:    beqz a0, .LBB93_310297; RV32ZVE32F-NEXT:  .LBB93_11: # %cond.store310298; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma10299; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 210300; RV32ZVE32F-NEXT:    vmv.x.s a0, v1010301; RV32ZVE32F-NEXT:    fsd fa2, 0(a0)10302; RV32ZVE32F-NEXT:    andi a0, a1, 810303; RV32ZVE32F-NEXT:    beqz a0, .LBB93_410304; RV32ZVE32F-NEXT:  .LBB93_12: # %cond.store510305; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma10306; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 310307; RV32ZVE32F-NEXT:    vmv.x.s a0, v1010308; RV32ZVE32F-NEXT:    fsd fa3, 0(a0)10309; RV32ZVE32F-NEXT:    andi a0, a1, 1610310; RV32ZVE32F-NEXT:    beqz a0, .LBB93_510311; RV32ZVE32F-NEXT:  .LBB93_13: # %cond.store710312; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma10313; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 410314; RV32ZVE32F-NEXT:    vmv.x.s a0, v1010315; RV32ZVE32F-NEXT:    fsd fa4, 0(a0)10316; RV32ZVE32F-NEXT:    andi a0, a1, 3210317; RV32ZVE32F-NEXT:    beqz a0, .LBB93_610318; RV32ZVE32F-NEXT:  .LBB93_14: # %cond.store910319; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma10320; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 510321; RV32ZVE32F-NEXT:    vmv.x.s a0, v1010322; RV32ZVE32F-NEXT:    fsd fa5, 0(a0)10323; RV32ZVE32F-NEXT:    andi a0, a1, 6410324; RV32ZVE32F-NEXT:    beqz a0, .LBB93_710325; RV32ZVE32F-NEXT:  .LBB93_15: # %cond.store1110326; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma10327; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 610328; RV32ZVE32F-NEXT:    vmv.x.s a0, v1010329; RV32ZVE32F-NEXT:    fsd fa6, 0(a0)10330; RV32ZVE32F-NEXT:    andi a0, a1, -12810331; RV32ZVE32F-NEXT:    beqz a0, .LBB93_810332; RV32ZVE32F-NEXT:  .LBB93_16: # %cond.store1310333; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma10334; RV32ZVE32F-NEXT:    vslidedown.vi v8, v8, 710335; RV32ZVE32F-NEXT:    vmv.x.s a0, v810336; RV32ZVE32F-NEXT:    fsd fa7, 0(a0)10337; RV32ZVE32F-NEXT:    ret10338;10339; RV64ZVE32F-LABEL: mscatter_baseidx_zext_v8i8_v8f64:10340; RV64ZVE32F:       # %bb.0:10341; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma10342; RV64ZVE32F-NEXT:    vmv.x.s a1, v010343; RV64ZVE32F-NEXT:    andi a2, a1, 110344; RV64ZVE32F-NEXT:    beqz a2, .LBB93_210345; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store10346; RV64ZVE32F-NEXT:    vmv.x.s a2, v810347; RV64ZVE32F-NEXT:    zext.b a2, a210348; RV64ZVE32F-NEXT:    slli a2, a2, 310349; RV64ZVE32F-NEXT:    add a2, a0, a210350; RV64ZVE32F-NEXT:    fsd fa0, 0(a2)10351; RV64ZVE32F-NEXT:  .LBB93_2: # %else10352; RV64ZVE32F-NEXT:    andi a2, a1, 210353; RV64ZVE32F-NEXT:    beqz a2, .LBB93_410354; RV64ZVE32F-NEXT:  # %bb.3: # %cond.store110355; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma10356; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 110357; RV64ZVE32F-NEXT:    vmv.x.s a2, v910358; RV64ZVE32F-NEXT:    zext.b a2, a210359; RV64ZVE32F-NEXT:    slli a2, a2, 310360; RV64ZVE32F-NEXT:    add a2, a0, a210361; RV64ZVE32F-NEXT:    fsd fa1, 0(a2)10362; RV64ZVE32F-NEXT:  .LBB93_4: # %else210363; RV64ZVE32F-NEXT:    andi a2, a1, 410364; RV64ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma10365; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 210366; RV64ZVE32F-NEXT:    beqz a2, .LBB93_610367; RV64ZVE32F-NEXT:  # %bb.5: # %cond.store310368; RV64ZVE32F-NEXT:    vmv.x.s a2, v910369; RV64ZVE32F-NEXT:    zext.b a2, a210370; RV64ZVE32F-NEXT:    slli a2, a2, 310371; RV64ZVE32F-NEXT:    add a2, a0, a210372; RV64ZVE32F-NEXT:    fsd fa2, 0(a2)10373; RV64ZVE32F-NEXT:  .LBB93_6: # %else410374; RV64ZVE32F-NEXT:    andi a2, a1, 810375; RV64ZVE32F-NEXT:    beqz a2, .LBB93_810376; RV64ZVE32F-NEXT:  # %bb.7: # %cond.store510377; RV64ZVE32F-NEXT:    vslidedown.vi v9, v9, 110378; RV64ZVE32F-NEXT:    vmv.x.s a2, v910379; RV64ZVE32F-NEXT:    zext.b a2, a210380; RV64ZVE32F-NEXT:    slli a2, a2, 310381; RV64ZVE32F-NEXT:    add a2, a0, a210382; RV64ZVE32F-NEXT:    fsd fa3, 0(a2)10383; RV64ZVE32F-NEXT:  .LBB93_8: # %else610384; RV64ZVE32F-NEXT:    andi a2, a1, 1610385; RV64ZVE32F-NEXT:    vsetivli zero, 4, e8, mf2, ta, ma10386; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 410387; RV64ZVE32F-NEXT:    beqz a2, .LBB93_1010388; RV64ZVE32F-NEXT:  # %bb.9: # %cond.store710389; RV64ZVE32F-NEXT:    vmv.x.s a2, v810390; RV64ZVE32F-NEXT:    zext.b a2, a210391; RV64ZVE32F-NEXT:    slli a2, a2, 310392; RV64ZVE32F-NEXT:    add a2, a0, a210393; RV64ZVE32F-NEXT:    fsd fa4, 0(a2)10394; RV64ZVE32F-NEXT:  .LBB93_10: # %else810395; RV64ZVE32F-NEXT:    andi a2, a1, 3210396; RV64ZVE32F-NEXT:    beqz a2, .LBB93_1210397; RV64ZVE32F-NEXT:  # %bb.11: # %cond.store910398; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma10399; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 110400; RV64ZVE32F-NEXT:    vmv.x.s a2, v910401; RV64ZVE32F-NEXT:    zext.b a2, a210402; RV64ZVE32F-NEXT:    slli a2, a2, 310403; RV64ZVE32F-NEXT:    add a2, a0, a210404; RV64ZVE32F-NEXT:    fsd fa5, 0(a2)10405; RV64ZVE32F-NEXT:  .LBB93_12: # %else1010406; RV64ZVE32F-NEXT:    andi a2, a1, 6410407; RV64ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma10408; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 210409; RV64ZVE32F-NEXT:    bnez a2, .LBB93_1510410; RV64ZVE32F-NEXT:  # %bb.13: # %else1210411; RV64ZVE32F-NEXT:    andi a1, a1, -12810412; RV64ZVE32F-NEXT:    bnez a1, .LBB93_1610413; RV64ZVE32F-NEXT:  .LBB93_14: # %else1410414; RV64ZVE32F-NEXT:    ret10415; RV64ZVE32F-NEXT:  .LBB93_15: # %cond.store1110416; RV64ZVE32F-NEXT:    vmv.x.s a2, v810417; RV64ZVE32F-NEXT:    zext.b a2, a210418; RV64ZVE32F-NEXT:    slli a2, a2, 310419; RV64ZVE32F-NEXT:    add a2, a0, a210420; RV64ZVE32F-NEXT:    fsd fa6, 0(a2)10421; RV64ZVE32F-NEXT:    andi a1, a1, -12810422; RV64ZVE32F-NEXT:    beqz a1, .LBB93_1410423; RV64ZVE32F-NEXT:  .LBB93_16: # %cond.store1310424; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 110425; RV64ZVE32F-NEXT:    vmv.x.s a1, v810426; RV64ZVE32F-NEXT:    zext.b a1, a110427; RV64ZVE32F-NEXT:    slli a1, a1, 310428; RV64ZVE32F-NEXT:    add a0, a0, a110429; RV64ZVE32F-NEXT:    fsd fa7, 0(a0)10430; RV64ZVE32F-NEXT:    ret10431  %eidxs = zext <8 x i8> %idxs to <8 x i64>10432  %ptrs = getelementptr inbounds double, ptr %base, <8 x i64> %eidxs10433  call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> %val, <8 x ptr> %ptrs, i32 8, <8 x i1> %m)10434  ret void10435}10436 10437define void @mscatter_baseidx_v8i16_v8f64(<8 x double> %val, ptr %base, <8 x i16> %idxs, <8 x i1> %m) {10438; RV32V-LABEL: mscatter_baseidx_v8i16_v8f64:10439; RV32V:       # %bb.0:10440; RV32V-NEXT:    li a1, 810441; RV32V-NEXT:    vsetivli zero, 8, e16, m1, ta, ma10442; RV32V-NEXT:    vwmulsu.vx v14, v12, a110443; RV32V-NEXT:    vsetvli zero, zero, e64, m4, ta, ma10444; RV32V-NEXT:    vsoxei32.v v8, (a0), v14, v0.t10445; RV32V-NEXT:    ret10446;10447; RV64V-LABEL: mscatter_baseidx_v8i16_v8f64:10448; RV64V:       # %bb.0:10449; RV64V-NEXT:    vsetivli zero, 8, e64, m4, ta, ma10450; RV64V-NEXT:    vsext.vf4 v16, v1210451; RV64V-NEXT:    vsll.vi v12, v16, 310452; RV64V-NEXT:    vsoxei64.v v8, (a0), v12, v0.t10453; RV64V-NEXT:    ret10454;10455; RV32ZVE32F-LABEL: mscatter_baseidx_v8i16_v8f64:10456; RV32ZVE32F:       # %bb.0:10457; RV32ZVE32F-NEXT:    vsetivli zero, 8, e32, m2, ta, ma10458; RV32ZVE32F-NEXT:    vmv.v.x v10, a010459; RV32ZVE32F-NEXT:    li a1, 810460; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma10461; RV32ZVE32F-NEXT:    vmv.x.s a0, v010462; RV32ZVE32F-NEXT:    andi a2, a0, 110463; RV32ZVE32F-NEXT:    vsetvli zero, zero, e16, m1, ta, ma10464; RV32ZVE32F-NEXT:    vwmaccus.vx v10, a1, v810465; RV32ZVE32F-NEXT:    bnez a2, .LBB94_910466; RV32ZVE32F-NEXT:  # %bb.1: # %else10467; RV32ZVE32F-NEXT:    andi a1, a0, 210468; RV32ZVE32F-NEXT:    bnez a1, .LBB94_1010469; RV32ZVE32F-NEXT:  .LBB94_2: # %else210470; RV32ZVE32F-NEXT:    andi a1, a0, 410471; RV32ZVE32F-NEXT:    bnez a1, .LBB94_1110472; RV32ZVE32F-NEXT:  .LBB94_3: # %else410473; RV32ZVE32F-NEXT:    andi a1, a0, 810474; RV32ZVE32F-NEXT:    bnez a1, .LBB94_1210475; RV32ZVE32F-NEXT:  .LBB94_4: # %else610476; RV32ZVE32F-NEXT:    andi a1, a0, 1610477; RV32ZVE32F-NEXT:    bnez a1, .LBB94_1310478; RV32ZVE32F-NEXT:  .LBB94_5: # %else810479; RV32ZVE32F-NEXT:    andi a1, a0, 3210480; RV32ZVE32F-NEXT:    bnez a1, .LBB94_1410481; RV32ZVE32F-NEXT:  .LBB94_6: # %else1010482; RV32ZVE32F-NEXT:    andi a1, a0, 6410483; RV32ZVE32F-NEXT:    bnez a1, .LBB94_1510484; RV32ZVE32F-NEXT:  .LBB94_7: # %else1210485; RV32ZVE32F-NEXT:    andi a0, a0, -12810486; RV32ZVE32F-NEXT:    bnez a0, .LBB94_1610487; RV32ZVE32F-NEXT:  .LBB94_8: # %else1410488; RV32ZVE32F-NEXT:    ret10489; RV32ZVE32F-NEXT:  .LBB94_9: # %cond.store10490; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma10491; RV32ZVE32F-NEXT:    vmv.x.s a1, v1010492; RV32ZVE32F-NEXT:    fsd fa0, 0(a1)10493; RV32ZVE32F-NEXT:    andi a1, a0, 210494; RV32ZVE32F-NEXT:    beqz a1, .LBB94_210495; RV32ZVE32F-NEXT:  .LBB94_10: # %cond.store110496; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma10497; RV32ZVE32F-NEXT:    vslidedown.vi v8, v10, 110498; RV32ZVE32F-NEXT:    vmv.x.s a1, v810499; RV32ZVE32F-NEXT:    fsd fa1, 0(a1)10500; RV32ZVE32F-NEXT:    andi a1, a0, 410501; RV32ZVE32F-NEXT:    beqz a1, .LBB94_310502; RV32ZVE32F-NEXT:  .LBB94_11: # %cond.store310503; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma10504; RV32ZVE32F-NEXT:    vslidedown.vi v8, v10, 210505; RV32ZVE32F-NEXT:    vmv.x.s a1, v810506; RV32ZVE32F-NEXT:    fsd fa2, 0(a1)10507; RV32ZVE32F-NEXT:    andi a1, a0, 810508; RV32ZVE32F-NEXT:    beqz a1, .LBB94_410509; RV32ZVE32F-NEXT:  .LBB94_12: # %cond.store510510; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma10511; RV32ZVE32F-NEXT:    vslidedown.vi v8, v10, 310512; RV32ZVE32F-NEXT:    vmv.x.s a1, v810513; RV32ZVE32F-NEXT:    fsd fa3, 0(a1)10514; RV32ZVE32F-NEXT:    andi a1, a0, 1610515; RV32ZVE32F-NEXT:    beqz a1, .LBB94_510516; RV32ZVE32F-NEXT:  .LBB94_13: # %cond.store710517; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma10518; RV32ZVE32F-NEXT:    vslidedown.vi v8, v10, 410519; RV32ZVE32F-NEXT:    vmv.x.s a1, v810520; RV32ZVE32F-NEXT:    fsd fa4, 0(a1)10521; RV32ZVE32F-NEXT:    andi a1, a0, 3210522; RV32ZVE32F-NEXT:    beqz a1, .LBB94_610523; RV32ZVE32F-NEXT:  .LBB94_14: # %cond.store910524; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma10525; RV32ZVE32F-NEXT:    vslidedown.vi v8, v10, 510526; RV32ZVE32F-NEXT:    vmv.x.s a1, v810527; RV32ZVE32F-NEXT:    fsd fa5, 0(a1)10528; RV32ZVE32F-NEXT:    andi a1, a0, 6410529; RV32ZVE32F-NEXT:    beqz a1, .LBB94_710530; RV32ZVE32F-NEXT:  .LBB94_15: # %cond.store1110531; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma10532; RV32ZVE32F-NEXT:    vslidedown.vi v8, v10, 610533; RV32ZVE32F-NEXT:    vmv.x.s a1, v810534; RV32ZVE32F-NEXT:    fsd fa6, 0(a1)10535; RV32ZVE32F-NEXT:    andi a0, a0, -12810536; RV32ZVE32F-NEXT:    beqz a0, .LBB94_810537; RV32ZVE32F-NEXT:  .LBB94_16: # %cond.store1310538; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma10539; RV32ZVE32F-NEXT:    vslidedown.vi v8, v10, 710540; RV32ZVE32F-NEXT:    vmv.x.s a0, v810541; RV32ZVE32F-NEXT:    fsd fa7, 0(a0)10542; RV32ZVE32F-NEXT:    ret10543;10544; RV64ZVE32F-LABEL: mscatter_baseidx_v8i16_v8f64:10545; RV64ZVE32F:       # %bb.0:10546; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma10547; RV64ZVE32F-NEXT:    vmv.x.s a1, v010548; RV64ZVE32F-NEXT:    andi a2, a1, 110549; RV64ZVE32F-NEXT:    beqz a2, .LBB94_210550; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store10551; RV64ZVE32F-NEXT:    vsetvli zero, zero, e16, m2, ta, ma10552; RV64ZVE32F-NEXT:    vmv.x.s a2, v810553; RV64ZVE32F-NEXT:    slli a2, a2, 310554; RV64ZVE32F-NEXT:    add a2, a0, a210555; RV64ZVE32F-NEXT:    fsd fa0, 0(a2)10556; RV64ZVE32F-NEXT:  .LBB94_2: # %else10557; RV64ZVE32F-NEXT:    andi a2, a1, 210558; RV64ZVE32F-NEXT:    beqz a2, .LBB94_410559; RV64ZVE32F-NEXT:  # %bb.3: # %cond.store110560; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma10561; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 110562; RV64ZVE32F-NEXT:    vmv.x.s a2, v910563; RV64ZVE32F-NEXT:    slli a2, a2, 310564; RV64ZVE32F-NEXT:    add a2, a0, a210565; RV64ZVE32F-NEXT:    fsd fa1, 0(a2)10566; RV64ZVE32F-NEXT:  .LBB94_4: # %else210567; RV64ZVE32F-NEXT:    andi a2, a1, 410568; RV64ZVE32F-NEXT:    vsetivli zero, 2, e16, mf2, ta, ma10569; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 210570; RV64ZVE32F-NEXT:    beqz a2, .LBB94_610571; RV64ZVE32F-NEXT:  # %bb.5: # %cond.store310572; RV64ZVE32F-NEXT:    vmv.x.s a2, v910573; RV64ZVE32F-NEXT:    slli a2, a2, 310574; RV64ZVE32F-NEXT:    add a2, a0, a210575; RV64ZVE32F-NEXT:    fsd fa2, 0(a2)10576; RV64ZVE32F-NEXT:  .LBB94_6: # %else410577; RV64ZVE32F-NEXT:    andi a2, a1, 810578; RV64ZVE32F-NEXT:    beqz a2, .LBB94_810579; RV64ZVE32F-NEXT:  # %bb.7: # %cond.store510580; RV64ZVE32F-NEXT:    vslidedown.vi v9, v9, 110581; RV64ZVE32F-NEXT:    vmv.x.s a2, v910582; RV64ZVE32F-NEXT:    slli a2, a2, 310583; RV64ZVE32F-NEXT:    add a2, a0, a210584; RV64ZVE32F-NEXT:    fsd fa3, 0(a2)10585; RV64ZVE32F-NEXT:  .LBB94_8: # %else610586; RV64ZVE32F-NEXT:    andi a2, a1, 1610587; RV64ZVE32F-NEXT:    vsetivli zero, 4, e16, m1, ta, ma10588; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 410589; RV64ZVE32F-NEXT:    beqz a2, .LBB94_1010590; RV64ZVE32F-NEXT:  # %bb.9: # %cond.store710591; RV64ZVE32F-NEXT:    vmv.x.s a2, v810592; RV64ZVE32F-NEXT:    slli a2, a2, 310593; RV64ZVE32F-NEXT:    add a2, a0, a210594; RV64ZVE32F-NEXT:    fsd fa4, 0(a2)10595; RV64ZVE32F-NEXT:  .LBB94_10: # %else810596; RV64ZVE32F-NEXT:    andi a2, a1, 3210597; RV64ZVE32F-NEXT:    beqz a2, .LBB94_1210598; RV64ZVE32F-NEXT:  # %bb.11: # %cond.store910599; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma10600; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 110601; RV64ZVE32F-NEXT:    vmv.x.s a2, v910602; RV64ZVE32F-NEXT:    slli a2, a2, 310603; RV64ZVE32F-NEXT:    add a2, a0, a210604; RV64ZVE32F-NEXT:    fsd fa5, 0(a2)10605; RV64ZVE32F-NEXT:  .LBB94_12: # %else1010606; RV64ZVE32F-NEXT:    andi a2, a1, 6410607; RV64ZVE32F-NEXT:    vsetivli zero, 2, e16, mf2, ta, ma10608; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 210609; RV64ZVE32F-NEXT:    bnez a2, .LBB94_1510610; RV64ZVE32F-NEXT:  # %bb.13: # %else1210611; RV64ZVE32F-NEXT:    andi a1, a1, -12810612; RV64ZVE32F-NEXT:    bnez a1, .LBB94_1610613; RV64ZVE32F-NEXT:  .LBB94_14: # %else1410614; RV64ZVE32F-NEXT:    ret10615; RV64ZVE32F-NEXT:  .LBB94_15: # %cond.store1110616; RV64ZVE32F-NEXT:    vmv.x.s a2, v810617; RV64ZVE32F-NEXT:    slli a2, a2, 310618; RV64ZVE32F-NEXT:    add a2, a0, a210619; RV64ZVE32F-NEXT:    fsd fa6, 0(a2)10620; RV64ZVE32F-NEXT:    andi a1, a1, -12810621; RV64ZVE32F-NEXT:    beqz a1, .LBB94_1410622; RV64ZVE32F-NEXT:  .LBB94_16: # %cond.store1310623; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 110624; RV64ZVE32F-NEXT:    vmv.x.s a1, v810625; RV64ZVE32F-NEXT:    slli a1, a1, 310626; RV64ZVE32F-NEXT:    add a0, a0, a110627; RV64ZVE32F-NEXT:    fsd fa7, 0(a0)10628; RV64ZVE32F-NEXT:    ret10629  %ptrs = getelementptr inbounds double, ptr %base, <8 x i16> %idxs10630  call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> %val, <8 x ptr> %ptrs, i32 8, <8 x i1> %m)10631  ret void10632}10633 10634define void @mscatter_baseidx_sext_v8i16_v8f64(<8 x double> %val, ptr %base, <8 x i16> %idxs, <8 x i1> %m) {10635; RV32V-LABEL: mscatter_baseidx_sext_v8i16_v8f64:10636; RV32V:       # %bb.0:10637; RV32V-NEXT:    li a1, 810638; RV32V-NEXT:    vsetivli zero, 8, e16, m1, ta, ma10639; RV32V-NEXT:    vwmulsu.vx v14, v12, a110640; RV32V-NEXT:    vsetvli zero, zero, e64, m4, ta, ma10641; RV32V-NEXT:    vsoxei32.v v8, (a0), v14, v0.t10642; RV32V-NEXT:    ret10643;10644; RV64V-LABEL: mscatter_baseidx_sext_v8i16_v8f64:10645; RV64V:       # %bb.0:10646; RV64V-NEXT:    vsetivli zero, 8, e64, m4, ta, ma10647; RV64V-NEXT:    vsext.vf4 v16, v1210648; RV64V-NEXT:    vsll.vi v12, v16, 310649; RV64V-NEXT:    vsoxei64.v v8, (a0), v12, v0.t10650; RV64V-NEXT:    ret10651;10652; RV32ZVE32F-LABEL: mscatter_baseidx_sext_v8i16_v8f64:10653; RV32ZVE32F:       # %bb.0:10654; RV32ZVE32F-NEXT:    vsetivli zero, 8, e32, m2, ta, ma10655; RV32ZVE32F-NEXT:    vmv.v.x v10, a010656; RV32ZVE32F-NEXT:    li a1, 810657; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma10658; RV32ZVE32F-NEXT:    vmv.x.s a0, v010659; RV32ZVE32F-NEXT:    andi a2, a0, 110660; RV32ZVE32F-NEXT:    vsetvli zero, zero, e16, m1, ta, ma10661; RV32ZVE32F-NEXT:    vwmaccus.vx v10, a1, v810662; RV32ZVE32F-NEXT:    bnez a2, .LBB95_910663; RV32ZVE32F-NEXT:  # %bb.1: # %else10664; RV32ZVE32F-NEXT:    andi a1, a0, 210665; RV32ZVE32F-NEXT:    bnez a1, .LBB95_1010666; RV32ZVE32F-NEXT:  .LBB95_2: # %else210667; RV32ZVE32F-NEXT:    andi a1, a0, 410668; RV32ZVE32F-NEXT:    bnez a1, .LBB95_1110669; RV32ZVE32F-NEXT:  .LBB95_3: # %else410670; RV32ZVE32F-NEXT:    andi a1, a0, 810671; RV32ZVE32F-NEXT:    bnez a1, .LBB95_1210672; RV32ZVE32F-NEXT:  .LBB95_4: # %else610673; RV32ZVE32F-NEXT:    andi a1, a0, 1610674; RV32ZVE32F-NEXT:    bnez a1, .LBB95_1310675; RV32ZVE32F-NEXT:  .LBB95_5: # %else810676; RV32ZVE32F-NEXT:    andi a1, a0, 3210677; RV32ZVE32F-NEXT:    bnez a1, .LBB95_1410678; RV32ZVE32F-NEXT:  .LBB95_6: # %else1010679; RV32ZVE32F-NEXT:    andi a1, a0, 6410680; RV32ZVE32F-NEXT:    bnez a1, .LBB95_1510681; RV32ZVE32F-NEXT:  .LBB95_7: # %else1210682; RV32ZVE32F-NEXT:    andi a0, a0, -12810683; RV32ZVE32F-NEXT:    bnez a0, .LBB95_1610684; RV32ZVE32F-NEXT:  .LBB95_8: # %else1410685; RV32ZVE32F-NEXT:    ret10686; RV32ZVE32F-NEXT:  .LBB95_9: # %cond.store10687; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma10688; RV32ZVE32F-NEXT:    vmv.x.s a1, v1010689; RV32ZVE32F-NEXT:    fsd fa0, 0(a1)10690; RV32ZVE32F-NEXT:    andi a1, a0, 210691; RV32ZVE32F-NEXT:    beqz a1, .LBB95_210692; RV32ZVE32F-NEXT:  .LBB95_10: # %cond.store110693; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma10694; RV32ZVE32F-NEXT:    vslidedown.vi v8, v10, 110695; RV32ZVE32F-NEXT:    vmv.x.s a1, v810696; RV32ZVE32F-NEXT:    fsd fa1, 0(a1)10697; RV32ZVE32F-NEXT:    andi a1, a0, 410698; RV32ZVE32F-NEXT:    beqz a1, .LBB95_310699; RV32ZVE32F-NEXT:  .LBB95_11: # %cond.store310700; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma10701; RV32ZVE32F-NEXT:    vslidedown.vi v8, v10, 210702; RV32ZVE32F-NEXT:    vmv.x.s a1, v810703; RV32ZVE32F-NEXT:    fsd fa2, 0(a1)10704; RV32ZVE32F-NEXT:    andi a1, a0, 810705; RV32ZVE32F-NEXT:    beqz a1, .LBB95_410706; RV32ZVE32F-NEXT:  .LBB95_12: # %cond.store510707; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma10708; RV32ZVE32F-NEXT:    vslidedown.vi v8, v10, 310709; RV32ZVE32F-NEXT:    vmv.x.s a1, v810710; RV32ZVE32F-NEXT:    fsd fa3, 0(a1)10711; RV32ZVE32F-NEXT:    andi a1, a0, 1610712; RV32ZVE32F-NEXT:    beqz a1, .LBB95_510713; RV32ZVE32F-NEXT:  .LBB95_13: # %cond.store710714; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma10715; RV32ZVE32F-NEXT:    vslidedown.vi v8, v10, 410716; RV32ZVE32F-NEXT:    vmv.x.s a1, v810717; RV32ZVE32F-NEXT:    fsd fa4, 0(a1)10718; RV32ZVE32F-NEXT:    andi a1, a0, 3210719; RV32ZVE32F-NEXT:    beqz a1, .LBB95_610720; RV32ZVE32F-NEXT:  .LBB95_14: # %cond.store910721; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma10722; RV32ZVE32F-NEXT:    vslidedown.vi v8, v10, 510723; RV32ZVE32F-NEXT:    vmv.x.s a1, v810724; RV32ZVE32F-NEXT:    fsd fa5, 0(a1)10725; RV32ZVE32F-NEXT:    andi a1, a0, 6410726; RV32ZVE32F-NEXT:    beqz a1, .LBB95_710727; RV32ZVE32F-NEXT:  .LBB95_15: # %cond.store1110728; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma10729; RV32ZVE32F-NEXT:    vslidedown.vi v8, v10, 610730; RV32ZVE32F-NEXT:    vmv.x.s a1, v810731; RV32ZVE32F-NEXT:    fsd fa6, 0(a1)10732; RV32ZVE32F-NEXT:    andi a0, a0, -12810733; RV32ZVE32F-NEXT:    beqz a0, .LBB95_810734; RV32ZVE32F-NEXT:  .LBB95_16: # %cond.store1310735; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma10736; RV32ZVE32F-NEXT:    vslidedown.vi v8, v10, 710737; RV32ZVE32F-NEXT:    vmv.x.s a0, v810738; RV32ZVE32F-NEXT:    fsd fa7, 0(a0)10739; RV32ZVE32F-NEXT:    ret10740;10741; RV64ZVE32F-LABEL: mscatter_baseidx_sext_v8i16_v8f64:10742; RV64ZVE32F:       # %bb.0:10743; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma10744; RV64ZVE32F-NEXT:    vmv.x.s a1, v010745; RV64ZVE32F-NEXT:    andi a2, a1, 110746; RV64ZVE32F-NEXT:    beqz a2, .LBB95_210747; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store10748; RV64ZVE32F-NEXT:    vsetvli zero, zero, e16, m2, ta, ma10749; RV64ZVE32F-NEXT:    vmv.x.s a2, v810750; RV64ZVE32F-NEXT:    slli a2, a2, 310751; RV64ZVE32F-NEXT:    add a2, a0, a210752; RV64ZVE32F-NEXT:    fsd fa0, 0(a2)10753; RV64ZVE32F-NEXT:  .LBB95_2: # %else10754; RV64ZVE32F-NEXT:    andi a2, a1, 210755; RV64ZVE32F-NEXT:    beqz a2, .LBB95_410756; RV64ZVE32F-NEXT:  # %bb.3: # %cond.store110757; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma10758; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 110759; RV64ZVE32F-NEXT:    vmv.x.s a2, v910760; RV64ZVE32F-NEXT:    slli a2, a2, 310761; RV64ZVE32F-NEXT:    add a2, a0, a210762; RV64ZVE32F-NEXT:    fsd fa1, 0(a2)10763; RV64ZVE32F-NEXT:  .LBB95_4: # %else210764; RV64ZVE32F-NEXT:    andi a2, a1, 410765; RV64ZVE32F-NEXT:    vsetivli zero, 2, e16, mf2, ta, ma10766; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 210767; RV64ZVE32F-NEXT:    beqz a2, .LBB95_610768; RV64ZVE32F-NEXT:  # %bb.5: # %cond.store310769; RV64ZVE32F-NEXT:    vmv.x.s a2, v910770; RV64ZVE32F-NEXT:    slli a2, a2, 310771; RV64ZVE32F-NEXT:    add a2, a0, a210772; RV64ZVE32F-NEXT:    fsd fa2, 0(a2)10773; RV64ZVE32F-NEXT:  .LBB95_6: # %else410774; RV64ZVE32F-NEXT:    andi a2, a1, 810775; RV64ZVE32F-NEXT:    beqz a2, .LBB95_810776; RV64ZVE32F-NEXT:  # %bb.7: # %cond.store510777; RV64ZVE32F-NEXT:    vslidedown.vi v9, v9, 110778; RV64ZVE32F-NEXT:    vmv.x.s a2, v910779; RV64ZVE32F-NEXT:    slli a2, a2, 310780; RV64ZVE32F-NEXT:    add a2, a0, a210781; RV64ZVE32F-NEXT:    fsd fa3, 0(a2)10782; RV64ZVE32F-NEXT:  .LBB95_8: # %else610783; RV64ZVE32F-NEXT:    andi a2, a1, 1610784; RV64ZVE32F-NEXT:    vsetivli zero, 4, e16, m1, ta, ma10785; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 410786; RV64ZVE32F-NEXT:    beqz a2, .LBB95_1010787; RV64ZVE32F-NEXT:  # %bb.9: # %cond.store710788; RV64ZVE32F-NEXT:    vmv.x.s a2, v810789; RV64ZVE32F-NEXT:    slli a2, a2, 310790; RV64ZVE32F-NEXT:    add a2, a0, a210791; RV64ZVE32F-NEXT:    fsd fa4, 0(a2)10792; RV64ZVE32F-NEXT:  .LBB95_10: # %else810793; RV64ZVE32F-NEXT:    andi a2, a1, 3210794; RV64ZVE32F-NEXT:    beqz a2, .LBB95_1210795; RV64ZVE32F-NEXT:  # %bb.11: # %cond.store910796; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma10797; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 110798; RV64ZVE32F-NEXT:    vmv.x.s a2, v910799; RV64ZVE32F-NEXT:    slli a2, a2, 310800; RV64ZVE32F-NEXT:    add a2, a0, a210801; RV64ZVE32F-NEXT:    fsd fa5, 0(a2)10802; RV64ZVE32F-NEXT:  .LBB95_12: # %else1010803; RV64ZVE32F-NEXT:    andi a2, a1, 6410804; RV64ZVE32F-NEXT:    vsetivli zero, 2, e16, mf2, ta, ma10805; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 210806; RV64ZVE32F-NEXT:    bnez a2, .LBB95_1510807; RV64ZVE32F-NEXT:  # %bb.13: # %else1210808; RV64ZVE32F-NEXT:    andi a1, a1, -12810809; RV64ZVE32F-NEXT:    bnez a1, .LBB95_1610810; RV64ZVE32F-NEXT:  .LBB95_14: # %else1410811; RV64ZVE32F-NEXT:    ret10812; RV64ZVE32F-NEXT:  .LBB95_15: # %cond.store1110813; RV64ZVE32F-NEXT:    vmv.x.s a2, v810814; RV64ZVE32F-NEXT:    slli a2, a2, 310815; RV64ZVE32F-NEXT:    add a2, a0, a210816; RV64ZVE32F-NEXT:    fsd fa6, 0(a2)10817; RV64ZVE32F-NEXT:    andi a1, a1, -12810818; RV64ZVE32F-NEXT:    beqz a1, .LBB95_1410819; RV64ZVE32F-NEXT:  .LBB95_16: # %cond.store1310820; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 110821; RV64ZVE32F-NEXT:    vmv.x.s a1, v810822; RV64ZVE32F-NEXT:    slli a1, a1, 310823; RV64ZVE32F-NEXT:    add a0, a0, a110824; RV64ZVE32F-NEXT:    fsd fa7, 0(a0)10825; RV64ZVE32F-NEXT:    ret10826  %eidxs = sext <8 x i16> %idxs to <8 x i64>10827  %ptrs = getelementptr inbounds double, ptr %base, <8 x i64> %eidxs10828  call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> %val, <8 x ptr> %ptrs, i32 8, <8 x i1> %m)10829  ret void10830}10831 10832define void @mscatter_baseidx_zext_v8i16_v8f64(<8 x double> %val, ptr %base, <8 x i16> %idxs, <8 x i1> %m) {10833; RV32V-LABEL: mscatter_baseidx_zext_v8i16_v8f64:10834; RV32V:       # %bb.0:10835; RV32V-NEXT:    li a1, 810836; RV32V-NEXT:    vsetivli zero, 8, e16, m1, ta, ma10837; RV32V-NEXT:    vwmulu.vx v14, v12, a110838; RV32V-NEXT:    vsetvli zero, zero, e64, m4, ta, ma10839; RV32V-NEXT:    vsoxei32.v v8, (a0), v14, v0.t10840; RV32V-NEXT:    ret10841;10842; RV64V-LABEL: mscatter_baseidx_zext_v8i16_v8f64:10843; RV64V:       # %bb.0:10844; RV64V-NEXT:    li a1, 810845; RV64V-NEXT:    vsetivli zero, 8, e16, m1, ta, ma10846; RV64V-NEXT:    vwmulu.vx v14, v12, a110847; RV64V-NEXT:    vsetvli zero, zero, e64, m4, ta, ma10848; RV64V-NEXT:    vsoxei32.v v8, (a0), v14, v0.t10849; RV64V-NEXT:    ret10850;10851; RV32ZVE32F-LABEL: mscatter_baseidx_zext_v8i16_v8f64:10852; RV32ZVE32F:       # %bb.0:10853; RV32ZVE32F-NEXT:    vsetivli zero, 8, e32, m2, ta, ma10854; RV32ZVE32F-NEXT:    vmv.v.x v10, a010855; RV32ZVE32F-NEXT:    li a1, 810856; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma10857; RV32ZVE32F-NEXT:    vmv.x.s a0, v010858; RV32ZVE32F-NEXT:    andi a2, a0, 110859; RV32ZVE32F-NEXT:    vsetvli zero, zero, e16, m1, ta, ma10860; RV32ZVE32F-NEXT:    vwmaccu.vx v10, a1, v810861; RV32ZVE32F-NEXT:    bnez a2, .LBB96_910862; RV32ZVE32F-NEXT:  # %bb.1: # %else10863; RV32ZVE32F-NEXT:    andi a1, a0, 210864; RV32ZVE32F-NEXT:    bnez a1, .LBB96_1010865; RV32ZVE32F-NEXT:  .LBB96_2: # %else210866; RV32ZVE32F-NEXT:    andi a1, a0, 410867; RV32ZVE32F-NEXT:    bnez a1, .LBB96_1110868; RV32ZVE32F-NEXT:  .LBB96_3: # %else410869; RV32ZVE32F-NEXT:    andi a1, a0, 810870; RV32ZVE32F-NEXT:    bnez a1, .LBB96_1210871; RV32ZVE32F-NEXT:  .LBB96_4: # %else610872; RV32ZVE32F-NEXT:    andi a1, a0, 1610873; RV32ZVE32F-NEXT:    bnez a1, .LBB96_1310874; RV32ZVE32F-NEXT:  .LBB96_5: # %else810875; RV32ZVE32F-NEXT:    andi a1, a0, 3210876; RV32ZVE32F-NEXT:    bnez a1, .LBB96_1410877; RV32ZVE32F-NEXT:  .LBB96_6: # %else1010878; RV32ZVE32F-NEXT:    andi a1, a0, 6410879; RV32ZVE32F-NEXT:    bnez a1, .LBB96_1510880; RV32ZVE32F-NEXT:  .LBB96_7: # %else1210881; RV32ZVE32F-NEXT:    andi a0, a0, -12810882; RV32ZVE32F-NEXT:    bnez a0, .LBB96_1610883; RV32ZVE32F-NEXT:  .LBB96_8: # %else1410884; RV32ZVE32F-NEXT:    ret10885; RV32ZVE32F-NEXT:  .LBB96_9: # %cond.store10886; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma10887; RV32ZVE32F-NEXT:    vmv.x.s a1, v1010888; RV32ZVE32F-NEXT:    fsd fa0, 0(a1)10889; RV32ZVE32F-NEXT:    andi a1, a0, 210890; RV32ZVE32F-NEXT:    beqz a1, .LBB96_210891; RV32ZVE32F-NEXT:  .LBB96_10: # %cond.store110892; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma10893; RV32ZVE32F-NEXT:    vslidedown.vi v8, v10, 110894; RV32ZVE32F-NEXT:    vmv.x.s a1, v810895; RV32ZVE32F-NEXT:    fsd fa1, 0(a1)10896; RV32ZVE32F-NEXT:    andi a1, a0, 410897; RV32ZVE32F-NEXT:    beqz a1, .LBB96_310898; RV32ZVE32F-NEXT:  .LBB96_11: # %cond.store310899; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma10900; RV32ZVE32F-NEXT:    vslidedown.vi v8, v10, 210901; RV32ZVE32F-NEXT:    vmv.x.s a1, v810902; RV32ZVE32F-NEXT:    fsd fa2, 0(a1)10903; RV32ZVE32F-NEXT:    andi a1, a0, 810904; RV32ZVE32F-NEXT:    beqz a1, .LBB96_410905; RV32ZVE32F-NEXT:  .LBB96_12: # %cond.store510906; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma10907; RV32ZVE32F-NEXT:    vslidedown.vi v8, v10, 310908; RV32ZVE32F-NEXT:    vmv.x.s a1, v810909; RV32ZVE32F-NEXT:    fsd fa3, 0(a1)10910; RV32ZVE32F-NEXT:    andi a1, a0, 1610911; RV32ZVE32F-NEXT:    beqz a1, .LBB96_510912; RV32ZVE32F-NEXT:  .LBB96_13: # %cond.store710913; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma10914; RV32ZVE32F-NEXT:    vslidedown.vi v8, v10, 410915; RV32ZVE32F-NEXT:    vmv.x.s a1, v810916; RV32ZVE32F-NEXT:    fsd fa4, 0(a1)10917; RV32ZVE32F-NEXT:    andi a1, a0, 3210918; RV32ZVE32F-NEXT:    beqz a1, .LBB96_610919; RV32ZVE32F-NEXT:  .LBB96_14: # %cond.store910920; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma10921; RV32ZVE32F-NEXT:    vslidedown.vi v8, v10, 510922; RV32ZVE32F-NEXT:    vmv.x.s a1, v810923; RV32ZVE32F-NEXT:    fsd fa5, 0(a1)10924; RV32ZVE32F-NEXT:    andi a1, a0, 6410925; RV32ZVE32F-NEXT:    beqz a1, .LBB96_710926; RV32ZVE32F-NEXT:  .LBB96_15: # %cond.store1110927; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma10928; RV32ZVE32F-NEXT:    vslidedown.vi v8, v10, 610929; RV32ZVE32F-NEXT:    vmv.x.s a1, v810930; RV32ZVE32F-NEXT:    fsd fa6, 0(a1)10931; RV32ZVE32F-NEXT:    andi a0, a0, -12810932; RV32ZVE32F-NEXT:    beqz a0, .LBB96_810933; RV32ZVE32F-NEXT:  .LBB96_16: # %cond.store1310934; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma10935; RV32ZVE32F-NEXT:    vslidedown.vi v8, v10, 710936; RV32ZVE32F-NEXT:    vmv.x.s a0, v810937; RV32ZVE32F-NEXT:    fsd fa7, 0(a0)10938; RV32ZVE32F-NEXT:    ret10939;10940; RV64ZVE32F-LABEL: mscatter_baseidx_zext_v8i16_v8f64:10941; RV64ZVE32F:       # %bb.0:10942; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma10943; RV64ZVE32F-NEXT:    vmv.x.s a1, v010944; RV64ZVE32F-NEXT:    andi a2, a1, 110945; RV64ZVE32F-NEXT:    beqz a2, .LBB96_210946; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store10947; RV64ZVE32F-NEXT:    vsetvli zero, zero, e16, m2, ta, ma10948; RV64ZVE32F-NEXT:    vmv.x.s a2, v810949; RV64ZVE32F-NEXT:    slli a2, a2, 4810950; RV64ZVE32F-NEXT:    srli a2, a2, 4510951; RV64ZVE32F-NEXT:    add a2, a0, a210952; RV64ZVE32F-NEXT:    fsd fa0, 0(a2)10953; RV64ZVE32F-NEXT:  .LBB96_2: # %else10954; RV64ZVE32F-NEXT:    andi a2, a1, 210955; RV64ZVE32F-NEXT:    beqz a2, .LBB96_410956; RV64ZVE32F-NEXT:  # %bb.3: # %cond.store110957; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma10958; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 110959; RV64ZVE32F-NEXT:    vmv.x.s a2, v910960; RV64ZVE32F-NEXT:    slli a2, a2, 4810961; RV64ZVE32F-NEXT:    srli a2, a2, 4510962; RV64ZVE32F-NEXT:    add a2, a0, a210963; RV64ZVE32F-NEXT:    fsd fa1, 0(a2)10964; RV64ZVE32F-NEXT:  .LBB96_4: # %else210965; RV64ZVE32F-NEXT:    andi a2, a1, 410966; RV64ZVE32F-NEXT:    vsetivli zero, 2, e16, mf2, ta, ma10967; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 210968; RV64ZVE32F-NEXT:    beqz a2, .LBB96_610969; RV64ZVE32F-NEXT:  # %bb.5: # %cond.store310970; RV64ZVE32F-NEXT:    vmv.x.s a2, v910971; RV64ZVE32F-NEXT:    slli a2, a2, 4810972; RV64ZVE32F-NEXT:    srli a2, a2, 4510973; RV64ZVE32F-NEXT:    add a2, a0, a210974; RV64ZVE32F-NEXT:    fsd fa2, 0(a2)10975; RV64ZVE32F-NEXT:  .LBB96_6: # %else410976; RV64ZVE32F-NEXT:    andi a2, a1, 810977; RV64ZVE32F-NEXT:    beqz a2, .LBB96_810978; RV64ZVE32F-NEXT:  # %bb.7: # %cond.store510979; RV64ZVE32F-NEXT:    vslidedown.vi v9, v9, 110980; RV64ZVE32F-NEXT:    vmv.x.s a2, v910981; RV64ZVE32F-NEXT:    slli a2, a2, 4810982; RV64ZVE32F-NEXT:    srli a2, a2, 4510983; RV64ZVE32F-NEXT:    add a2, a0, a210984; RV64ZVE32F-NEXT:    fsd fa3, 0(a2)10985; RV64ZVE32F-NEXT:  .LBB96_8: # %else610986; RV64ZVE32F-NEXT:    andi a2, a1, 1610987; RV64ZVE32F-NEXT:    vsetivli zero, 4, e16, m1, ta, ma10988; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 410989; RV64ZVE32F-NEXT:    beqz a2, .LBB96_1010990; RV64ZVE32F-NEXT:  # %bb.9: # %cond.store710991; RV64ZVE32F-NEXT:    vmv.x.s a2, v810992; RV64ZVE32F-NEXT:    slli a2, a2, 4810993; RV64ZVE32F-NEXT:    srli a2, a2, 4510994; RV64ZVE32F-NEXT:    add a2, a0, a210995; RV64ZVE32F-NEXT:    fsd fa4, 0(a2)10996; RV64ZVE32F-NEXT:  .LBB96_10: # %else810997; RV64ZVE32F-NEXT:    andi a2, a1, 3210998; RV64ZVE32F-NEXT:    beqz a2, .LBB96_1210999; RV64ZVE32F-NEXT:  # %bb.11: # %cond.store911000; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma11001; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 111002; RV64ZVE32F-NEXT:    vmv.x.s a2, v911003; RV64ZVE32F-NEXT:    slli a2, a2, 4811004; RV64ZVE32F-NEXT:    srli a2, a2, 4511005; RV64ZVE32F-NEXT:    add a2, a0, a211006; RV64ZVE32F-NEXT:    fsd fa5, 0(a2)11007; RV64ZVE32F-NEXT:  .LBB96_12: # %else1011008; RV64ZVE32F-NEXT:    andi a2, a1, 6411009; RV64ZVE32F-NEXT:    vsetivli zero, 2, e16, mf2, ta, ma11010; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 211011; RV64ZVE32F-NEXT:    bnez a2, .LBB96_1511012; RV64ZVE32F-NEXT:  # %bb.13: # %else1211013; RV64ZVE32F-NEXT:    andi a1, a1, -12811014; RV64ZVE32F-NEXT:    bnez a1, .LBB96_1611015; RV64ZVE32F-NEXT:  .LBB96_14: # %else1411016; RV64ZVE32F-NEXT:    ret11017; RV64ZVE32F-NEXT:  .LBB96_15: # %cond.store1111018; RV64ZVE32F-NEXT:    vmv.x.s a2, v811019; RV64ZVE32F-NEXT:    slli a2, a2, 4811020; RV64ZVE32F-NEXT:    srli a2, a2, 4511021; RV64ZVE32F-NEXT:    add a2, a0, a211022; RV64ZVE32F-NEXT:    fsd fa6, 0(a2)11023; RV64ZVE32F-NEXT:    andi a1, a1, -12811024; RV64ZVE32F-NEXT:    beqz a1, .LBB96_1411025; RV64ZVE32F-NEXT:  .LBB96_16: # %cond.store1311026; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 111027; RV64ZVE32F-NEXT:    vmv.x.s a1, v811028; RV64ZVE32F-NEXT:    slli a1, a1, 4811029; RV64ZVE32F-NEXT:    srli a1, a1, 4511030; RV64ZVE32F-NEXT:    add a0, a0, a111031; RV64ZVE32F-NEXT:    fsd fa7, 0(a0)11032; RV64ZVE32F-NEXT:    ret11033  %eidxs = zext <8 x i16> %idxs to <8 x i64>11034  %ptrs = getelementptr inbounds double, ptr %base, <8 x i64> %eidxs11035  call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> %val, <8 x ptr> %ptrs, i32 8, <8 x i1> %m)11036  ret void11037}11038 11039define void @mscatter_baseidx_v8i32_v8f64(<8 x double> %val, ptr %base, <8 x i32> %idxs, <8 x i1> %m) {11040; RV32V-LABEL: mscatter_baseidx_v8i32_v8f64:11041; RV32V:       # %bb.0:11042; RV32V-NEXT:    vsetivli zero, 8, e32, m2, ta, ma11043; RV32V-NEXT:    vsll.vi v12, v12, 311044; RV32V-NEXT:    vsetvli zero, zero, e64, m4, ta, ma11045; RV32V-NEXT:    vsoxei32.v v8, (a0), v12, v0.t11046; RV32V-NEXT:    ret11047;11048; RV64V-LABEL: mscatter_baseidx_v8i32_v8f64:11049; RV64V:       # %bb.0:11050; RV64V-NEXT:    li a1, 811051; RV64V-NEXT:    vsetivli zero, 8, e32, m2, ta, ma11052; RV64V-NEXT:    vwmulsu.vx v16, v12, a111053; RV64V-NEXT:    vsetvli zero, zero, e64, m4, ta, ma11054; RV64V-NEXT:    vsoxei64.v v8, (a0), v16, v0.t11055; RV64V-NEXT:    ret11056;11057; RV32ZVE32F-LABEL: mscatter_baseidx_v8i32_v8f64:11058; RV32ZVE32F:       # %bb.0:11059; RV32ZVE32F-NEXT:    vsetivli zero, 8, e32, m2, ta, ma11060; RV32ZVE32F-NEXT:    vsll.vi v8, v8, 311061; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma11062; RV32ZVE32F-NEXT:    vmv.x.s a1, v011063; RV32ZVE32F-NEXT:    andi a2, a1, 111064; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma11065; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a011066; RV32ZVE32F-NEXT:    bnez a2, .LBB97_911067; RV32ZVE32F-NEXT:  # %bb.1: # %else11068; RV32ZVE32F-NEXT:    andi a0, a1, 211069; RV32ZVE32F-NEXT:    bnez a0, .LBB97_1011070; RV32ZVE32F-NEXT:  .LBB97_2: # %else211071; RV32ZVE32F-NEXT:    andi a0, a1, 411072; RV32ZVE32F-NEXT:    bnez a0, .LBB97_1111073; RV32ZVE32F-NEXT:  .LBB97_3: # %else411074; RV32ZVE32F-NEXT:    andi a0, a1, 811075; RV32ZVE32F-NEXT:    bnez a0, .LBB97_1211076; RV32ZVE32F-NEXT:  .LBB97_4: # %else611077; RV32ZVE32F-NEXT:    andi a0, a1, 1611078; RV32ZVE32F-NEXT:    bnez a0, .LBB97_1311079; RV32ZVE32F-NEXT:  .LBB97_5: # %else811080; RV32ZVE32F-NEXT:    andi a0, a1, 3211081; RV32ZVE32F-NEXT:    bnez a0, .LBB97_1411082; RV32ZVE32F-NEXT:  .LBB97_6: # %else1011083; RV32ZVE32F-NEXT:    andi a0, a1, 6411084; RV32ZVE32F-NEXT:    bnez a0, .LBB97_1511085; RV32ZVE32F-NEXT:  .LBB97_7: # %else1211086; RV32ZVE32F-NEXT:    andi a0, a1, -12811087; RV32ZVE32F-NEXT:    bnez a0, .LBB97_1611088; RV32ZVE32F-NEXT:  .LBB97_8: # %else1411089; RV32ZVE32F-NEXT:    ret11090; RV32ZVE32F-NEXT:  .LBB97_9: # %cond.store11091; RV32ZVE32F-NEXT:    vmv.x.s a0, v811092; RV32ZVE32F-NEXT:    fsd fa0, 0(a0)11093; RV32ZVE32F-NEXT:    andi a0, a1, 211094; RV32ZVE32F-NEXT:    beqz a0, .LBB97_211095; RV32ZVE32F-NEXT:  .LBB97_10: # %cond.store111096; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma11097; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 111098; RV32ZVE32F-NEXT:    vmv.x.s a0, v1011099; RV32ZVE32F-NEXT:    fsd fa1, 0(a0)11100; RV32ZVE32F-NEXT:    andi a0, a1, 411101; RV32ZVE32F-NEXT:    beqz a0, .LBB97_311102; RV32ZVE32F-NEXT:  .LBB97_11: # %cond.store311103; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma11104; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 211105; RV32ZVE32F-NEXT:    vmv.x.s a0, v1011106; RV32ZVE32F-NEXT:    fsd fa2, 0(a0)11107; RV32ZVE32F-NEXT:    andi a0, a1, 811108; RV32ZVE32F-NEXT:    beqz a0, .LBB97_411109; RV32ZVE32F-NEXT:  .LBB97_12: # %cond.store511110; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma11111; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 311112; RV32ZVE32F-NEXT:    vmv.x.s a0, v1011113; RV32ZVE32F-NEXT:    fsd fa3, 0(a0)11114; RV32ZVE32F-NEXT:    andi a0, a1, 1611115; RV32ZVE32F-NEXT:    beqz a0, .LBB97_511116; RV32ZVE32F-NEXT:  .LBB97_13: # %cond.store711117; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma11118; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 411119; RV32ZVE32F-NEXT:    vmv.x.s a0, v1011120; RV32ZVE32F-NEXT:    fsd fa4, 0(a0)11121; RV32ZVE32F-NEXT:    andi a0, a1, 3211122; RV32ZVE32F-NEXT:    beqz a0, .LBB97_611123; RV32ZVE32F-NEXT:  .LBB97_14: # %cond.store911124; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma11125; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 511126; RV32ZVE32F-NEXT:    vmv.x.s a0, v1011127; RV32ZVE32F-NEXT:    fsd fa5, 0(a0)11128; RV32ZVE32F-NEXT:    andi a0, a1, 6411129; RV32ZVE32F-NEXT:    beqz a0, .LBB97_711130; RV32ZVE32F-NEXT:  .LBB97_15: # %cond.store1111131; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma11132; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 611133; RV32ZVE32F-NEXT:    vmv.x.s a0, v1011134; RV32ZVE32F-NEXT:    fsd fa6, 0(a0)11135; RV32ZVE32F-NEXT:    andi a0, a1, -12811136; RV32ZVE32F-NEXT:    beqz a0, .LBB97_811137; RV32ZVE32F-NEXT:  .LBB97_16: # %cond.store1311138; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma11139; RV32ZVE32F-NEXT:    vslidedown.vi v8, v8, 711140; RV32ZVE32F-NEXT:    vmv.x.s a0, v811141; RV32ZVE32F-NEXT:    fsd fa7, 0(a0)11142; RV32ZVE32F-NEXT:    ret11143;11144; RV64ZVE32F-LABEL: mscatter_baseidx_v8i32_v8f64:11145; RV64ZVE32F:       # %bb.0:11146; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma11147; RV64ZVE32F-NEXT:    vmv.x.s a1, v011148; RV64ZVE32F-NEXT:    andi a2, a1, 111149; RV64ZVE32F-NEXT:    beqz a2, .LBB97_211150; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store11151; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m4, ta, ma11152; RV64ZVE32F-NEXT:    vmv.x.s a2, v811153; RV64ZVE32F-NEXT:    slli a2, a2, 311154; RV64ZVE32F-NEXT:    add a2, a0, a211155; RV64ZVE32F-NEXT:    fsd fa0, 0(a2)11156; RV64ZVE32F-NEXT:  .LBB97_2: # %else11157; RV64ZVE32F-NEXT:    andi a2, a1, 211158; RV64ZVE32F-NEXT:    beqz a2, .LBB97_411159; RV64ZVE32F-NEXT:  # %bb.3: # %cond.store111160; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma11161; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 111162; RV64ZVE32F-NEXT:    vmv.x.s a2, v1011163; RV64ZVE32F-NEXT:    slli a2, a2, 311164; RV64ZVE32F-NEXT:    add a2, a0, a211165; RV64ZVE32F-NEXT:    fsd fa1, 0(a2)11166; RV64ZVE32F-NEXT:  .LBB97_4: # %else211167; RV64ZVE32F-NEXT:    andi a2, a1, 411168; RV64ZVE32F-NEXT:    vsetivli zero, 2, e32, m1, ta, ma11169; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 211170; RV64ZVE32F-NEXT:    beqz a2, .LBB97_611171; RV64ZVE32F-NEXT:  # %bb.5: # %cond.store311172; RV64ZVE32F-NEXT:    vmv.x.s a2, v1011173; RV64ZVE32F-NEXT:    slli a2, a2, 311174; RV64ZVE32F-NEXT:    add a2, a0, a211175; RV64ZVE32F-NEXT:    fsd fa2, 0(a2)11176; RV64ZVE32F-NEXT:  .LBB97_6: # %else411177; RV64ZVE32F-NEXT:    andi a2, a1, 811178; RV64ZVE32F-NEXT:    vsetivli zero, 4, e32, m2, ta, ma11179; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 411180; RV64ZVE32F-NEXT:    bnez a2, .LBB97_1311181; RV64ZVE32F-NEXT:  # %bb.7: # %else611182; RV64ZVE32F-NEXT:    andi a2, a1, 1611183; RV64ZVE32F-NEXT:    bnez a2, .LBB97_1411184; RV64ZVE32F-NEXT:  .LBB97_8: # %else811185; RV64ZVE32F-NEXT:    andi a2, a1, 3211186; RV64ZVE32F-NEXT:    beqz a2, .LBB97_1011187; RV64ZVE32F-NEXT:  .LBB97_9: # %cond.store911188; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma11189; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 111190; RV64ZVE32F-NEXT:    vmv.x.s a2, v911191; RV64ZVE32F-NEXT:    slli a2, a2, 311192; RV64ZVE32F-NEXT:    add a2, a0, a211193; RV64ZVE32F-NEXT:    fsd fa5, 0(a2)11194; RV64ZVE32F-NEXT:  .LBB97_10: # %else1011195; RV64ZVE32F-NEXT:    andi a2, a1, 6411196; RV64ZVE32F-NEXT:    vsetivli zero, 2, e32, m1, ta, ma11197; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 211198; RV64ZVE32F-NEXT:    bnez a2, .LBB97_1511199; RV64ZVE32F-NEXT:  # %bb.11: # %else1211200; RV64ZVE32F-NEXT:    andi a1, a1, -12811201; RV64ZVE32F-NEXT:    bnez a1, .LBB97_1611202; RV64ZVE32F-NEXT:  .LBB97_12: # %else1411203; RV64ZVE32F-NEXT:    ret11204; RV64ZVE32F-NEXT:  .LBB97_13: # %cond.store511205; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma11206; RV64ZVE32F-NEXT:    vslidedown.vi v9, v10, 111207; RV64ZVE32F-NEXT:    vmv.x.s a2, v911208; RV64ZVE32F-NEXT:    slli a2, a2, 311209; RV64ZVE32F-NEXT:    add a2, a0, a211210; RV64ZVE32F-NEXT:    fsd fa3, 0(a2)11211; RV64ZVE32F-NEXT:    andi a2, a1, 1611212; RV64ZVE32F-NEXT:    beqz a2, .LBB97_811213; RV64ZVE32F-NEXT:  .LBB97_14: # %cond.store711214; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma11215; RV64ZVE32F-NEXT:    vmv.x.s a2, v811216; RV64ZVE32F-NEXT:    slli a2, a2, 311217; RV64ZVE32F-NEXT:    add a2, a0, a211218; RV64ZVE32F-NEXT:    fsd fa4, 0(a2)11219; RV64ZVE32F-NEXT:    andi a2, a1, 3211220; RV64ZVE32F-NEXT:    bnez a2, .LBB97_911221; RV64ZVE32F-NEXT:    j .LBB97_1011222; RV64ZVE32F-NEXT:  .LBB97_15: # %cond.store1111223; RV64ZVE32F-NEXT:    vmv.x.s a2, v811224; RV64ZVE32F-NEXT:    slli a2, a2, 311225; RV64ZVE32F-NEXT:    add a2, a0, a211226; RV64ZVE32F-NEXT:    fsd fa6, 0(a2)11227; RV64ZVE32F-NEXT:    andi a1, a1, -12811228; RV64ZVE32F-NEXT:    beqz a1, .LBB97_1211229; RV64ZVE32F-NEXT:  .LBB97_16: # %cond.store1311230; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 111231; RV64ZVE32F-NEXT:    vmv.x.s a1, v811232; RV64ZVE32F-NEXT:    slli a1, a1, 311233; RV64ZVE32F-NEXT:    add a0, a0, a111234; RV64ZVE32F-NEXT:    fsd fa7, 0(a0)11235; RV64ZVE32F-NEXT:    ret11236  %ptrs = getelementptr inbounds double, ptr %base, <8 x i32> %idxs11237  call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> %val, <8 x ptr> %ptrs, i32 8, <8 x i1> %m)11238  ret void11239}11240 11241define void @mscatter_baseidx_sext_v8i32_v8f64(<8 x double> %val, ptr %base, <8 x i32> %idxs, <8 x i1> %m) {11242; RV32V-LABEL: mscatter_baseidx_sext_v8i32_v8f64:11243; RV32V:       # %bb.0:11244; RV32V-NEXT:    vsetivli zero, 8, e32, m2, ta, ma11245; RV32V-NEXT:    vsll.vi v12, v12, 311246; RV32V-NEXT:    vsetvli zero, zero, e64, m4, ta, ma11247; RV32V-NEXT:    vsoxei32.v v8, (a0), v12, v0.t11248; RV32V-NEXT:    ret11249;11250; RV64V-LABEL: mscatter_baseidx_sext_v8i32_v8f64:11251; RV64V:       # %bb.0:11252; RV64V-NEXT:    li a1, 811253; RV64V-NEXT:    vsetivli zero, 8, e32, m2, ta, ma11254; RV64V-NEXT:    vwmulsu.vx v16, v12, a111255; RV64V-NEXT:    vsetvli zero, zero, e64, m4, ta, ma11256; RV64V-NEXT:    vsoxei64.v v8, (a0), v16, v0.t11257; RV64V-NEXT:    ret11258;11259; RV32ZVE32F-LABEL: mscatter_baseidx_sext_v8i32_v8f64:11260; RV32ZVE32F:       # %bb.0:11261; RV32ZVE32F-NEXT:    vsetivli zero, 8, e32, m2, ta, ma11262; RV32ZVE32F-NEXT:    vsll.vi v8, v8, 311263; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma11264; RV32ZVE32F-NEXT:    vmv.x.s a1, v011265; RV32ZVE32F-NEXT:    andi a2, a1, 111266; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma11267; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a011268; RV32ZVE32F-NEXT:    bnez a2, .LBB98_911269; RV32ZVE32F-NEXT:  # %bb.1: # %else11270; RV32ZVE32F-NEXT:    andi a0, a1, 211271; RV32ZVE32F-NEXT:    bnez a0, .LBB98_1011272; RV32ZVE32F-NEXT:  .LBB98_2: # %else211273; RV32ZVE32F-NEXT:    andi a0, a1, 411274; RV32ZVE32F-NEXT:    bnez a0, .LBB98_1111275; RV32ZVE32F-NEXT:  .LBB98_3: # %else411276; RV32ZVE32F-NEXT:    andi a0, a1, 811277; RV32ZVE32F-NEXT:    bnez a0, .LBB98_1211278; RV32ZVE32F-NEXT:  .LBB98_4: # %else611279; RV32ZVE32F-NEXT:    andi a0, a1, 1611280; RV32ZVE32F-NEXT:    bnez a0, .LBB98_1311281; RV32ZVE32F-NEXT:  .LBB98_5: # %else811282; RV32ZVE32F-NEXT:    andi a0, a1, 3211283; RV32ZVE32F-NEXT:    bnez a0, .LBB98_1411284; RV32ZVE32F-NEXT:  .LBB98_6: # %else1011285; RV32ZVE32F-NEXT:    andi a0, a1, 6411286; RV32ZVE32F-NEXT:    bnez a0, .LBB98_1511287; RV32ZVE32F-NEXT:  .LBB98_7: # %else1211288; RV32ZVE32F-NEXT:    andi a0, a1, -12811289; RV32ZVE32F-NEXT:    bnez a0, .LBB98_1611290; RV32ZVE32F-NEXT:  .LBB98_8: # %else1411291; RV32ZVE32F-NEXT:    ret11292; RV32ZVE32F-NEXT:  .LBB98_9: # %cond.store11293; RV32ZVE32F-NEXT:    vmv.x.s a0, v811294; RV32ZVE32F-NEXT:    fsd fa0, 0(a0)11295; RV32ZVE32F-NEXT:    andi a0, a1, 211296; RV32ZVE32F-NEXT:    beqz a0, .LBB98_211297; RV32ZVE32F-NEXT:  .LBB98_10: # %cond.store111298; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma11299; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 111300; RV32ZVE32F-NEXT:    vmv.x.s a0, v1011301; RV32ZVE32F-NEXT:    fsd fa1, 0(a0)11302; RV32ZVE32F-NEXT:    andi a0, a1, 411303; RV32ZVE32F-NEXT:    beqz a0, .LBB98_311304; RV32ZVE32F-NEXT:  .LBB98_11: # %cond.store311305; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma11306; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 211307; RV32ZVE32F-NEXT:    vmv.x.s a0, v1011308; RV32ZVE32F-NEXT:    fsd fa2, 0(a0)11309; RV32ZVE32F-NEXT:    andi a0, a1, 811310; RV32ZVE32F-NEXT:    beqz a0, .LBB98_411311; RV32ZVE32F-NEXT:  .LBB98_12: # %cond.store511312; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma11313; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 311314; RV32ZVE32F-NEXT:    vmv.x.s a0, v1011315; RV32ZVE32F-NEXT:    fsd fa3, 0(a0)11316; RV32ZVE32F-NEXT:    andi a0, a1, 1611317; RV32ZVE32F-NEXT:    beqz a0, .LBB98_511318; RV32ZVE32F-NEXT:  .LBB98_13: # %cond.store711319; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma11320; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 411321; RV32ZVE32F-NEXT:    vmv.x.s a0, v1011322; RV32ZVE32F-NEXT:    fsd fa4, 0(a0)11323; RV32ZVE32F-NEXT:    andi a0, a1, 3211324; RV32ZVE32F-NEXT:    beqz a0, .LBB98_611325; RV32ZVE32F-NEXT:  .LBB98_14: # %cond.store911326; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma11327; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 511328; RV32ZVE32F-NEXT:    vmv.x.s a0, v1011329; RV32ZVE32F-NEXT:    fsd fa5, 0(a0)11330; RV32ZVE32F-NEXT:    andi a0, a1, 6411331; RV32ZVE32F-NEXT:    beqz a0, .LBB98_711332; RV32ZVE32F-NEXT:  .LBB98_15: # %cond.store1111333; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma11334; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 611335; RV32ZVE32F-NEXT:    vmv.x.s a0, v1011336; RV32ZVE32F-NEXT:    fsd fa6, 0(a0)11337; RV32ZVE32F-NEXT:    andi a0, a1, -12811338; RV32ZVE32F-NEXT:    beqz a0, .LBB98_811339; RV32ZVE32F-NEXT:  .LBB98_16: # %cond.store1311340; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma11341; RV32ZVE32F-NEXT:    vslidedown.vi v8, v8, 711342; RV32ZVE32F-NEXT:    vmv.x.s a0, v811343; RV32ZVE32F-NEXT:    fsd fa7, 0(a0)11344; RV32ZVE32F-NEXT:    ret11345;11346; RV64ZVE32F-LABEL: mscatter_baseidx_sext_v8i32_v8f64:11347; RV64ZVE32F:       # %bb.0:11348; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma11349; RV64ZVE32F-NEXT:    vmv.x.s a1, v011350; RV64ZVE32F-NEXT:    andi a2, a1, 111351; RV64ZVE32F-NEXT:    beqz a2, .LBB98_211352; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store11353; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m4, ta, ma11354; RV64ZVE32F-NEXT:    vmv.x.s a2, v811355; RV64ZVE32F-NEXT:    slli a2, a2, 311356; RV64ZVE32F-NEXT:    add a2, a0, a211357; RV64ZVE32F-NEXT:    fsd fa0, 0(a2)11358; RV64ZVE32F-NEXT:  .LBB98_2: # %else11359; RV64ZVE32F-NEXT:    andi a2, a1, 211360; RV64ZVE32F-NEXT:    beqz a2, .LBB98_411361; RV64ZVE32F-NEXT:  # %bb.3: # %cond.store111362; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma11363; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 111364; RV64ZVE32F-NEXT:    vmv.x.s a2, v1011365; RV64ZVE32F-NEXT:    slli a2, a2, 311366; RV64ZVE32F-NEXT:    add a2, a0, a211367; RV64ZVE32F-NEXT:    fsd fa1, 0(a2)11368; RV64ZVE32F-NEXT:  .LBB98_4: # %else211369; RV64ZVE32F-NEXT:    andi a2, a1, 411370; RV64ZVE32F-NEXT:    vsetivli zero, 2, e32, m1, ta, ma11371; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 211372; RV64ZVE32F-NEXT:    beqz a2, .LBB98_611373; RV64ZVE32F-NEXT:  # %bb.5: # %cond.store311374; RV64ZVE32F-NEXT:    vmv.x.s a2, v1011375; RV64ZVE32F-NEXT:    slli a2, a2, 311376; RV64ZVE32F-NEXT:    add a2, a0, a211377; RV64ZVE32F-NEXT:    fsd fa2, 0(a2)11378; RV64ZVE32F-NEXT:  .LBB98_6: # %else411379; RV64ZVE32F-NEXT:    andi a2, a1, 811380; RV64ZVE32F-NEXT:    vsetivli zero, 4, e32, m2, ta, ma11381; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 411382; RV64ZVE32F-NEXT:    bnez a2, .LBB98_1311383; RV64ZVE32F-NEXT:  # %bb.7: # %else611384; RV64ZVE32F-NEXT:    andi a2, a1, 1611385; RV64ZVE32F-NEXT:    bnez a2, .LBB98_1411386; RV64ZVE32F-NEXT:  .LBB98_8: # %else811387; RV64ZVE32F-NEXT:    andi a2, a1, 3211388; RV64ZVE32F-NEXT:    beqz a2, .LBB98_1011389; RV64ZVE32F-NEXT:  .LBB98_9: # %cond.store911390; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma11391; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 111392; RV64ZVE32F-NEXT:    vmv.x.s a2, v911393; RV64ZVE32F-NEXT:    slli a2, a2, 311394; RV64ZVE32F-NEXT:    add a2, a0, a211395; RV64ZVE32F-NEXT:    fsd fa5, 0(a2)11396; RV64ZVE32F-NEXT:  .LBB98_10: # %else1011397; RV64ZVE32F-NEXT:    andi a2, a1, 6411398; RV64ZVE32F-NEXT:    vsetivli zero, 2, e32, m1, ta, ma11399; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 211400; RV64ZVE32F-NEXT:    bnez a2, .LBB98_1511401; RV64ZVE32F-NEXT:  # %bb.11: # %else1211402; RV64ZVE32F-NEXT:    andi a1, a1, -12811403; RV64ZVE32F-NEXT:    bnez a1, .LBB98_1611404; RV64ZVE32F-NEXT:  .LBB98_12: # %else1411405; RV64ZVE32F-NEXT:    ret11406; RV64ZVE32F-NEXT:  .LBB98_13: # %cond.store511407; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma11408; RV64ZVE32F-NEXT:    vslidedown.vi v9, v10, 111409; RV64ZVE32F-NEXT:    vmv.x.s a2, v911410; RV64ZVE32F-NEXT:    slli a2, a2, 311411; RV64ZVE32F-NEXT:    add a2, a0, a211412; RV64ZVE32F-NEXT:    fsd fa3, 0(a2)11413; RV64ZVE32F-NEXT:    andi a2, a1, 1611414; RV64ZVE32F-NEXT:    beqz a2, .LBB98_811415; RV64ZVE32F-NEXT:  .LBB98_14: # %cond.store711416; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma11417; RV64ZVE32F-NEXT:    vmv.x.s a2, v811418; RV64ZVE32F-NEXT:    slli a2, a2, 311419; RV64ZVE32F-NEXT:    add a2, a0, a211420; RV64ZVE32F-NEXT:    fsd fa4, 0(a2)11421; RV64ZVE32F-NEXT:    andi a2, a1, 3211422; RV64ZVE32F-NEXT:    bnez a2, .LBB98_911423; RV64ZVE32F-NEXT:    j .LBB98_1011424; RV64ZVE32F-NEXT:  .LBB98_15: # %cond.store1111425; RV64ZVE32F-NEXT:    vmv.x.s a2, v811426; RV64ZVE32F-NEXT:    slli a2, a2, 311427; RV64ZVE32F-NEXT:    add a2, a0, a211428; RV64ZVE32F-NEXT:    fsd fa6, 0(a2)11429; RV64ZVE32F-NEXT:    andi a1, a1, -12811430; RV64ZVE32F-NEXT:    beqz a1, .LBB98_1211431; RV64ZVE32F-NEXT:  .LBB98_16: # %cond.store1311432; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 111433; RV64ZVE32F-NEXT:    vmv.x.s a1, v811434; RV64ZVE32F-NEXT:    slli a1, a1, 311435; RV64ZVE32F-NEXT:    add a0, a0, a111436; RV64ZVE32F-NEXT:    fsd fa7, 0(a0)11437; RV64ZVE32F-NEXT:    ret11438  %eidxs = sext <8 x i32> %idxs to <8 x i64>11439  %ptrs = getelementptr inbounds double, ptr %base, <8 x i64> %eidxs11440  call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> %val, <8 x ptr> %ptrs, i32 8, <8 x i1> %m)11441  ret void11442}11443 11444define void @mscatter_baseidx_zext_v8i32_v8f64(<8 x double> %val, ptr %base, <8 x i32> %idxs, <8 x i1> %m) {11445; RV32V-LABEL: mscatter_baseidx_zext_v8i32_v8f64:11446; RV32V:       # %bb.0:11447; RV32V-NEXT:    vsetivli zero, 8, e32, m2, ta, ma11448; RV32V-NEXT:    vsll.vi v12, v12, 311449; RV32V-NEXT:    vsetvli zero, zero, e64, m4, ta, ma11450; RV32V-NEXT:    vsoxei32.v v8, (a0), v12, v0.t11451; RV32V-NEXT:    ret11452;11453; RV64V-LABEL: mscatter_baseidx_zext_v8i32_v8f64:11454; RV64V:       # %bb.0:11455; RV64V-NEXT:    li a1, 811456; RV64V-NEXT:    vsetivli zero, 8, e32, m2, ta, ma11457; RV64V-NEXT:    vwmulu.vx v16, v12, a111458; RV64V-NEXT:    vsetvli zero, zero, e64, m4, ta, ma11459; RV64V-NEXT:    vsoxei64.v v8, (a0), v16, v0.t11460; RV64V-NEXT:    ret11461;11462; RV32ZVE32F-LABEL: mscatter_baseidx_zext_v8i32_v8f64:11463; RV32ZVE32F:       # %bb.0:11464; RV32ZVE32F-NEXT:    vsetivli zero, 8, e32, m2, ta, ma11465; RV32ZVE32F-NEXT:    vsll.vi v8, v8, 311466; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma11467; RV32ZVE32F-NEXT:    vmv.x.s a1, v011468; RV32ZVE32F-NEXT:    andi a2, a1, 111469; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma11470; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a011471; RV32ZVE32F-NEXT:    bnez a2, .LBB99_911472; RV32ZVE32F-NEXT:  # %bb.1: # %else11473; RV32ZVE32F-NEXT:    andi a0, a1, 211474; RV32ZVE32F-NEXT:    bnez a0, .LBB99_1011475; RV32ZVE32F-NEXT:  .LBB99_2: # %else211476; RV32ZVE32F-NEXT:    andi a0, a1, 411477; RV32ZVE32F-NEXT:    bnez a0, .LBB99_1111478; RV32ZVE32F-NEXT:  .LBB99_3: # %else411479; RV32ZVE32F-NEXT:    andi a0, a1, 811480; RV32ZVE32F-NEXT:    bnez a0, .LBB99_1211481; RV32ZVE32F-NEXT:  .LBB99_4: # %else611482; RV32ZVE32F-NEXT:    andi a0, a1, 1611483; RV32ZVE32F-NEXT:    bnez a0, .LBB99_1311484; RV32ZVE32F-NEXT:  .LBB99_5: # %else811485; RV32ZVE32F-NEXT:    andi a0, a1, 3211486; RV32ZVE32F-NEXT:    bnez a0, .LBB99_1411487; RV32ZVE32F-NEXT:  .LBB99_6: # %else1011488; RV32ZVE32F-NEXT:    andi a0, a1, 6411489; RV32ZVE32F-NEXT:    bnez a0, .LBB99_1511490; RV32ZVE32F-NEXT:  .LBB99_7: # %else1211491; RV32ZVE32F-NEXT:    andi a0, a1, -12811492; RV32ZVE32F-NEXT:    bnez a0, .LBB99_1611493; RV32ZVE32F-NEXT:  .LBB99_8: # %else1411494; RV32ZVE32F-NEXT:    ret11495; RV32ZVE32F-NEXT:  .LBB99_9: # %cond.store11496; RV32ZVE32F-NEXT:    vmv.x.s a0, v811497; RV32ZVE32F-NEXT:    fsd fa0, 0(a0)11498; RV32ZVE32F-NEXT:    andi a0, a1, 211499; RV32ZVE32F-NEXT:    beqz a0, .LBB99_211500; RV32ZVE32F-NEXT:  .LBB99_10: # %cond.store111501; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma11502; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 111503; RV32ZVE32F-NEXT:    vmv.x.s a0, v1011504; RV32ZVE32F-NEXT:    fsd fa1, 0(a0)11505; RV32ZVE32F-NEXT:    andi a0, a1, 411506; RV32ZVE32F-NEXT:    beqz a0, .LBB99_311507; RV32ZVE32F-NEXT:  .LBB99_11: # %cond.store311508; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma11509; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 211510; RV32ZVE32F-NEXT:    vmv.x.s a0, v1011511; RV32ZVE32F-NEXT:    fsd fa2, 0(a0)11512; RV32ZVE32F-NEXT:    andi a0, a1, 811513; RV32ZVE32F-NEXT:    beqz a0, .LBB99_411514; RV32ZVE32F-NEXT:  .LBB99_12: # %cond.store511515; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma11516; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 311517; RV32ZVE32F-NEXT:    vmv.x.s a0, v1011518; RV32ZVE32F-NEXT:    fsd fa3, 0(a0)11519; RV32ZVE32F-NEXT:    andi a0, a1, 1611520; RV32ZVE32F-NEXT:    beqz a0, .LBB99_511521; RV32ZVE32F-NEXT:  .LBB99_13: # %cond.store711522; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma11523; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 411524; RV32ZVE32F-NEXT:    vmv.x.s a0, v1011525; RV32ZVE32F-NEXT:    fsd fa4, 0(a0)11526; RV32ZVE32F-NEXT:    andi a0, a1, 3211527; RV32ZVE32F-NEXT:    beqz a0, .LBB99_611528; RV32ZVE32F-NEXT:  .LBB99_14: # %cond.store911529; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma11530; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 511531; RV32ZVE32F-NEXT:    vmv.x.s a0, v1011532; RV32ZVE32F-NEXT:    fsd fa5, 0(a0)11533; RV32ZVE32F-NEXT:    andi a0, a1, 6411534; RV32ZVE32F-NEXT:    beqz a0, .LBB99_711535; RV32ZVE32F-NEXT:  .LBB99_15: # %cond.store1111536; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma11537; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 611538; RV32ZVE32F-NEXT:    vmv.x.s a0, v1011539; RV32ZVE32F-NEXT:    fsd fa6, 0(a0)11540; RV32ZVE32F-NEXT:    andi a0, a1, -12811541; RV32ZVE32F-NEXT:    beqz a0, .LBB99_811542; RV32ZVE32F-NEXT:  .LBB99_16: # %cond.store1311543; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma11544; RV32ZVE32F-NEXT:    vslidedown.vi v8, v8, 711545; RV32ZVE32F-NEXT:    vmv.x.s a0, v811546; RV32ZVE32F-NEXT:    fsd fa7, 0(a0)11547; RV32ZVE32F-NEXT:    ret11548;11549; RV64ZVE32F-LABEL: mscatter_baseidx_zext_v8i32_v8f64:11550; RV64ZVE32F:       # %bb.0:11551; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma11552; RV64ZVE32F-NEXT:    vmv.x.s a1, v011553; RV64ZVE32F-NEXT:    andi a2, a1, 111554; RV64ZVE32F-NEXT:    beqz a2, .LBB99_211555; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store11556; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m4, ta, ma11557; RV64ZVE32F-NEXT:    vmv.x.s a2, v811558; RV64ZVE32F-NEXT:    slli a2, a2, 3211559; RV64ZVE32F-NEXT:    srli a2, a2, 2911560; RV64ZVE32F-NEXT:    add a2, a0, a211561; RV64ZVE32F-NEXT:    fsd fa0, 0(a2)11562; RV64ZVE32F-NEXT:  .LBB99_2: # %else11563; RV64ZVE32F-NEXT:    andi a2, a1, 211564; RV64ZVE32F-NEXT:    beqz a2, .LBB99_411565; RV64ZVE32F-NEXT:  # %bb.3: # %cond.store111566; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma11567; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 111568; RV64ZVE32F-NEXT:    vmv.x.s a2, v1011569; RV64ZVE32F-NEXT:    slli a2, a2, 3211570; RV64ZVE32F-NEXT:    srli a2, a2, 2911571; RV64ZVE32F-NEXT:    add a2, a0, a211572; RV64ZVE32F-NEXT:    fsd fa1, 0(a2)11573; RV64ZVE32F-NEXT:  .LBB99_4: # %else211574; RV64ZVE32F-NEXT:    andi a2, a1, 411575; RV64ZVE32F-NEXT:    vsetivli zero, 2, e32, m1, ta, ma11576; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 211577; RV64ZVE32F-NEXT:    beqz a2, .LBB99_611578; RV64ZVE32F-NEXT:  # %bb.5: # %cond.store311579; RV64ZVE32F-NEXT:    vmv.x.s a2, v1011580; RV64ZVE32F-NEXT:    slli a2, a2, 3211581; RV64ZVE32F-NEXT:    srli a2, a2, 2911582; RV64ZVE32F-NEXT:    add a2, a0, a211583; RV64ZVE32F-NEXT:    fsd fa2, 0(a2)11584; RV64ZVE32F-NEXT:  .LBB99_6: # %else411585; RV64ZVE32F-NEXT:    andi a2, a1, 811586; RV64ZVE32F-NEXT:    vsetivli zero, 4, e32, m2, ta, ma11587; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 411588; RV64ZVE32F-NEXT:    bnez a2, .LBB99_1311589; RV64ZVE32F-NEXT:  # %bb.7: # %else611590; RV64ZVE32F-NEXT:    andi a2, a1, 1611591; RV64ZVE32F-NEXT:    bnez a2, .LBB99_1411592; RV64ZVE32F-NEXT:  .LBB99_8: # %else811593; RV64ZVE32F-NEXT:    andi a2, a1, 3211594; RV64ZVE32F-NEXT:    beqz a2, .LBB99_1011595; RV64ZVE32F-NEXT:  .LBB99_9: # %cond.store911596; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma11597; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 111598; RV64ZVE32F-NEXT:    vmv.x.s a2, v911599; RV64ZVE32F-NEXT:    slli a2, a2, 3211600; RV64ZVE32F-NEXT:    srli a2, a2, 2911601; RV64ZVE32F-NEXT:    add a2, a0, a211602; RV64ZVE32F-NEXT:    fsd fa5, 0(a2)11603; RV64ZVE32F-NEXT:  .LBB99_10: # %else1011604; RV64ZVE32F-NEXT:    andi a2, a1, 6411605; RV64ZVE32F-NEXT:    vsetivli zero, 2, e32, m1, ta, ma11606; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 211607; RV64ZVE32F-NEXT:    bnez a2, .LBB99_1511608; RV64ZVE32F-NEXT:  # %bb.11: # %else1211609; RV64ZVE32F-NEXT:    andi a1, a1, -12811610; RV64ZVE32F-NEXT:    bnez a1, .LBB99_1611611; RV64ZVE32F-NEXT:  .LBB99_12: # %else1411612; RV64ZVE32F-NEXT:    ret11613; RV64ZVE32F-NEXT:  .LBB99_13: # %cond.store511614; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma11615; RV64ZVE32F-NEXT:    vslidedown.vi v9, v10, 111616; RV64ZVE32F-NEXT:    vmv.x.s a2, v911617; RV64ZVE32F-NEXT:    slli a2, a2, 3211618; RV64ZVE32F-NEXT:    srli a2, a2, 2911619; RV64ZVE32F-NEXT:    add a2, a0, a211620; RV64ZVE32F-NEXT:    fsd fa3, 0(a2)11621; RV64ZVE32F-NEXT:    andi a2, a1, 1611622; RV64ZVE32F-NEXT:    beqz a2, .LBB99_811623; RV64ZVE32F-NEXT:  .LBB99_14: # %cond.store711624; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma11625; RV64ZVE32F-NEXT:    vmv.x.s a2, v811626; RV64ZVE32F-NEXT:    slli a2, a2, 3211627; RV64ZVE32F-NEXT:    srli a2, a2, 2911628; RV64ZVE32F-NEXT:    add a2, a0, a211629; RV64ZVE32F-NEXT:    fsd fa4, 0(a2)11630; RV64ZVE32F-NEXT:    andi a2, a1, 3211631; RV64ZVE32F-NEXT:    bnez a2, .LBB99_911632; RV64ZVE32F-NEXT:    j .LBB99_1011633; RV64ZVE32F-NEXT:  .LBB99_15: # %cond.store1111634; RV64ZVE32F-NEXT:    vmv.x.s a2, v811635; RV64ZVE32F-NEXT:    slli a2, a2, 3211636; RV64ZVE32F-NEXT:    srli a2, a2, 2911637; RV64ZVE32F-NEXT:    add a2, a0, a211638; RV64ZVE32F-NEXT:    fsd fa6, 0(a2)11639; RV64ZVE32F-NEXT:    andi a1, a1, -12811640; RV64ZVE32F-NEXT:    beqz a1, .LBB99_1211641; RV64ZVE32F-NEXT:  .LBB99_16: # %cond.store1311642; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 111643; RV64ZVE32F-NEXT:    vmv.x.s a1, v811644; RV64ZVE32F-NEXT:    slli a1, a1, 3211645; RV64ZVE32F-NEXT:    srli a1, a1, 2911646; RV64ZVE32F-NEXT:    add a0, a0, a111647; RV64ZVE32F-NEXT:    fsd fa7, 0(a0)11648; RV64ZVE32F-NEXT:    ret11649  %eidxs = zext <8 x i32> %idxs to <8 x i64>11650  %ptrs = getelementptr inbounds double, ptr %base, <8 x i64> %eidxs11651  call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> %val, <8 x ptr> %ptrs, i32 8, <8 x i1> %m)11652  ret void11653}11654 11655define void @mscatter_baseidx_v8f64(<8 x double> %val, ptr %base, <8 x i64> %idxs, <8 x i1> %m) {11656; RV32V-LABEL: mscatter_baseidx_v8f64:11657; RV32V:       # %bb.0:11658; RV32V-NEXT:    vsetivli zero, 8, e32, m2, ta, ma11659; RV32V-NEXT:    vnsrl.wi v16, v12, 011660; RV32V-NEXT:    vsll.vi v12, v16, 311661; RV32V-NEXT:    vsetvli zero, zero, e64, m4, ta, ma11662; RV32V-NEXT:    vsoxei32.v v8, (a0), v12, v0.t11663; RV32V-NEXT:    ret11664;11665; RV64V-LABEL: mscatter_baseidx_v8f64:11666; RV64V:       # %bb.0:11667; RV64V-NEXT:    vsetivli zero, 8, e64, m4, ta, ma11668; RV64V-NEXT:    vsll.vi v12, v12, 311669; RV64V-NEXT:    vsoxei64.v v8, (a0), v12, v0.t11670; RV64V-NEXT:    ret11671;11672; RV32ZVE32F-LABEL: mscatter_baseidx_v8f64:11673; RV32ZVE32F:       # %bb.0:11674; RV32ZVE32F-NEXT:    lw a2, 32(a1)11675; RV32ZVE32F-NEXT:    lw a3, 40(a1)11676; RV32ZVE32F-NEXT:    lw a4, 48(a1)11677; RV32ZVE32F-NEXT:    lw a5, 56(a1)11678; RV32ZVE32F-NEXT:    lw a6, 0(a1)11679; RV32ZVE32F-NEXT:    lw a7, 8(a1)11680; RV32ZVE32F-NEXT:    lw t0, 16(a1)11681; RV32ZVE32F-NEXT:    lw t1, 24(a1)11682; RV32ZVE32F-NEXT:    vsetivli zero, 8, e32, m2, ta, ma11683; RV32ZVE32F-NEXT:    vmv.v.x v8, a611684; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma11685; RV32ZVE32F-NEXT:    vmv.x.s a1, v011686; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma11687; RV32ZVE32F-NEXT:    vslide1down.vx v8, v8, a711688; RV32ZVE32F-NEXT:    vslide1down.vx v8, v8, t011689; RV32ZVE32F-NEXT:    vslide1down.vx v8, v8, t111690; RV32ZVE32F-NEXT:    vslide1down.vx v8, v8, a211691; RV32ZVE32F-NEXT:    vslide1down.vx v8, v8, a311692; RV32ZVE32F-NEXT:    vslide1down.vx v8, v8, a411693; RV32ZVE32F-NEXT:    vslide1down.vx v8, v8, a511694; RV32ZVE32F-NEXT:    vsll.vi v8, v8, 311695; RV32ZVE32F-NEXT:    andi a2, a1, 111696; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a011697; RV32ZVE32F-NEXT:    bnez a2, .LBB100_911698; RV32ZVE32F-NEXT:  # %bb.1: # %else11699; RV32ZVE32F-NEXT:    andi a0, a1, 211700; RV32ZVE32F-NEXT:    bnez a0, .LBB100_1011701; RV32ZVE32F-NEXT:  .LBB100_2: # %else211702; RV32ZVE32F-NEXT:    andi a0, a1, 411703; RV32ZVE32F-NEXT:    bnez a0, .LBB100_1111704; RV32ZVE32F-NEXT:  .LBB100_3: # %else411705; RV32ZVE32F-NEXT:    andi a0, a1, 811706; RV32ZVE32F-NEXT:    bnez a0, .LBB100_1211707; RV32ZVE32F-NEXT:  .LBB100_4: # %else611708; RV32ZVE32F-NEXT:    andi a0, a1, 1611709; RV32ZVE32F-NEXT:    bnez a0, .LBB100_1311710; RV32ZVE32F-NEXT:  .LBB100_5: # %else811711; RV32ZVE32F-NEXT:    andi a0, a1, 3211712; RV32ZVE32F-NEXT:    bnez a0, .LBB100_1411713; RV32ZVE32F-NEXT:  .LBB100_6: # %else1011714; RV32ZVE32F-NEXT:    andi a0, a1, 6411715; RV32ZVE32F-NEXT:    bnez a0, .LBB100_1511716; RV32ZVE32F-NEXT:  .LBB100_7: # %else1211717; RV32ZVE32F-NEXT:    andi a0, a1, -12811718; RV32ZVE32F-NEXT:    bnez a0, .LBB100_1611719; RV32ZVE32F-NEXT:  .LBB100_8: # %else1411720; RV32ZVE32F-NEXT:    ret11721; RV32ZVE32F-NEXT:  .LBB100_9: # %cond.store11722; RV32ZVE32F-NEXT:    vmv.x.s a0, v811723; RV32ZVE32F-NEXT:    fsd fa0, 0(a0)11724; RV32ZVE32F-NEXT:    andi a0, a1, 211725; RV32ZVE32F-NEXT:    beqz a0, .LBB100_211726; RV32ZVE32F-NEXT:  .LBB100_10: # %cond.store111727; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma11728; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 111729; RV32ZVE32F-NEXT:    vmv.x.s a0, v1011730; RV32ZVE32F-NEXT:    fsd fa1, 0(a0)11731; RV32ZVE32F-NEXT:    andi a0, a1, 411732; RV32ZVE32F-NEXT:    beqz a0, .LBB100_311733; RV32ZVE32F-NEXT:  .LBB100_11: # %cond.store311734; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma11735; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 211736; RV32ZVE32F-NEXT:    vmv.x.s a0, v1011737; RV32ZVE32F-NEXT:    fsd fa2, 0(a0)11738; RV32ZVE32F-NEXT:    andi a0, a1, 811739; RV32ZVE32F-NEXT:    beqz a0, .LBB100_411740; RV32ZVE32F-NEXT:  .LBB100_12: # %cond.store511741; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma11742; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 311743; RV32ZVE32F-NEXT:    vmv.x.s a0, v1011744; RV32ZVE32F-NEXT:    fsd fa3, 0(a0)11745; RV32ZVE32F-NEXT:    andi a0, a1, 1611746; RV32ZVE32F-NEXT:    beqz a0, .LBB100_511747; RV32ZVE32F-NEXT:  .LBB100_13: # %cond.store711748; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma11749; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 411750; RV32ZVE32F-NEXT:    vmv.x.s a0, v1011751; RV32ZVE32F-NEXT:    fsd fa4, 0(a0)11752; RV32ZVE32F-NEXT:    andi a0, a1, 3211753; RV32ZVE32F-NEXT:    beqz a0, .LBB100_611754; RV32ZVE32F-NEXT:  .LBB100_14: # %cond.store911755; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma11756; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 511757; RV32ZVE32F-NEXT:    vmv.x.s a0, v1011758; RV32ZVE32F-NEXT:    fsd fa5, 0(a0)11759; RV32ZVE32F-NEXT:    andi a0, a1, 6411760; RV32ZVE32F-NEXT:    beqz a0, .LBB100_711761; RV32ZVE32F-NEXT:  .LBB100_15: # %cond.store1111762; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma11763; RV32ZVE32F-NEXT:    vslidedown.vi v10, v8, 611764; RV32ZVE32F-NEXT:    vmv.x.s a0, v1011765; RV32ZVE32F-NEXT:    fsd fa6, 0(a0)11766; RV32ZVE32F-NEXT:    andi a0, a1, -12811767; RV32ZVE32F-NEXT:    beqz a0, .LBB100_811768; RV32ZVE32F-NEXT:  .LBB100_16: # %cond.store1311769; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma11770; RV32ZVE32F-NEXT:    vslidedown.vi v8, v8, 711771; RV32ZVE32F-NEXT:    vmv.x.s a0, v811772; RV32ZVE32F-NEXT:    fsd fa7, 0(a0)11773; RV32ZVE32F-NEXT:    ret11774;11775; RV64ZVE32F-LABEL: mscatter_baseidx_v8f64:11776; RV64ZVE32F:       # %bb.0:11777; RV64ZVE32F-NEXT:    ld t1, 8(a1)11778; RV64ZVE32F-NEXT:    ld t0, 16(a1)11779; RV64ZVE32F-NEXT:    ld a7, 24(a1)11780; RV64ZVE32F-NEXT:    ld a6, 32(a1)11781; RV64ZVE32F-NEXT:    ld a5, 40(a1)11782; RV64ZVE32F-NEXT:    ld a4, 48(a1)11783; RV64ZVE32F-NEXT:    ld a2, 56(a1)11784; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma11785; RV64ZVE32F-NEXT:    vmv.x.s a3, v011786; RV64ZVE32F-NEXT:    andi t2, a3, 111787; RV64ZVE32F-NEXT:    bnez t2, .LBB100_911788; RV64ZVE32F-NEXT:  # %bb.1: # %else11789; RV64ZVE32F-NEXT:    andi a1, a3, 211790; RV64ZVE32F-NEXT:    bnez a1, .LBB100_1011791; RV64ZVE32F-NEXT:  .LBB100_2: # %else211792; RV64ZVE32F-NEXT:    andi a1, a3, 411793; RV64ZVE32F-NEXT:    bnez a1, .LBB100_1111794; RV64ZVE32F-NEXT:  .LBB100_3: # %else411795; RV64ZVE32F-NEXT:    andi a1, a3, 811796; RV64ZVE32F-NEXT:    bnez a1, .LBB100_1211797; RV64ZVE32F-NEXT:  .LBB100_4: # %else611798; RV64ZVE32F-NEXT:    andi a1, a3, 1611799; RV64ZVE32F-NEXT:    bnez a1, .LBB100_1311800; RV64ZVE32F-NEXT:  .LBB100_5: # %else811801; RV64ZVE32F-NEXT:    andi a1, a3, 3211802; RV64ZVE32F-NEXT:    bnez a1, .LBB100_1411803; RV64ZVE32F-NEXT:  .LBB100_6: # %else1011804; RV64ZVE32F-NEXT:    andi a1, a3, 6411805; RV64ZVE32F-NEXT:    bnez a1, .LBB100_1511806; RV64ZVE32F-NEXT:  .LBB100_7: # %else1211807; RV64ZVE32F-NEXT:    andi a1, a3, -12811808; RV64ZVE32F-NEXT:    bnez a1, .LBB100_1611809; RV64ZVE32F-NEXT:  .LBB100_8: # %else1411810; RV64ZVE32F-NEXT:    ret11811; RV64ZVE32F-NEXT:  .LBB100_9: # %cond.store11812; RV64ZVE32F-NEXT:    ld a1, 0(a1)11813; RV64ZVE32F-NEXT:    slli a1, a1, 311814; RV64ZVE32F-NEXT:    add a1, a0, a111815; RV64ZVE32F-NEXT:    fsd fa0, 0(a1)11816; RV64ZVE32F-NEXT:    andi a1, a3, 211817; RV64ZVE32F-NEXT:    beqz a1, .LBB100_211818; RV64ZVE32F-NEXT:  .LBB100_10: # %cond.store111819; RV64ZVE32F-NEXT:    slli t1, t1, 311820; RV64ZVE32F-NEXT:    add t1, a0, t111821; RV64ZVE32F-NEXT:    fsd fa1, 0(t1)11822; RV64ZVE32F-NEXT:    andi a1, a3, 411823; RV64ZVE32F-NEXT:    beqz a1, .LBB100_311824; RV64ZVE32F-NEXT:  .LBB100_11: # %cond.store311825; RV64ZVE32F-NEXT:    slli t0, t0, 311826; RV64ZVE32F-NEXT:    add t0, a0, t011827; RV64ZVE32F-NEXT:    fsd fa2, 0(t0)11828; RV64ZVE32F-NEXT:    andi a1, a3, 811829; RV64ZVE32F-NEXT:    beqz a1, .LBB100_411830; RV64ZVE32F-NEXT:  .LBB100_12: # %cond.store511831; RV64ZVE32F-NEXT:    slli a7, a7, 311832; RV64ZVE32F-NEXT:    add a7, a0, a711833; RV64ZVE32F-NEXT:    fsd fa3, 0(a7)11834; RV64ZVE32F-NEXT:    andi a1, a3, 1611835; RV64ZVE32F-NEXT:    beqz a1, .LBB100_511836; RV64ZVE32F-NEXT:  .LBB100_13: # %cond.store711837; RV64ZVE32F-NEXT:    slli a6, a6, 311838; RV64ZVE32F-NEXT:    add a6, a0, a611839; RV64ZVE32F-NEXT:    fsd fa4, 0(a6)11840; RV64ZVE32F-NEXT:    andi a1, a3, 3211841; RV64ZVE32F-NEXT:    beqz a1, .LBB100_611842; RV64ZVE32F-NEXT:  .LBB100_14: # %cond.store911843; RV64ZVE32F-NEXT:    slli a5, a5, 311844; RV64ZVE32F-NEXT:    add a5, a0, a511845; RV64ZVE32F-NEXT:    fsd fa5, 0(a5)11846; RV64ZVE32F-NEXT:    andi a1, a3, 6411847; RV64ZVE32F-NEXT:    beqz a1, .LBB100_711848; RV64ZVE32F-NEXT:  .LBB100_15: # %cond.store1111849; RV64ZVE32F-NEXT:    slli a4, a4, 311850; RV64ZVE32F-NEXT:    add a4, a0, a411851; RV64ZVE32F-NEXT:    fsd fa6, 0(a4)11852; RV64ZVE32F-NEXT:    andi a1, a3, -12811853; RV64ZVE32F-NEXT:    beqz a1, .LBB100_811854; RV64ZVE32F-NEXT:  .LBB100_16: # %cond.store1311855; RV64ZVE32F-NEXT:    slli a2, a2, 311856; RV64ZVE32F-NEXT:    add a0, a0, a211857; RV64ZVE32F-NEXT:    fsd fa7, 0(a0)11858; RV64ZVE32F-NEXT:    ret11859  %ptrs = getelementptr inbounds double, ptr %base, <8 x i64> %idxs11860  call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> %val, <8 x ptr> %ptrs, i32 8, <8 x i1> %m)11861  ret void11862}11863 11864define void @mscatter_baseidx_v16i8(<16 x i8> %val, ptr %base, <16 x i8> %idxs, <16 x i1> %m) {11865; RV32-LABEL: mscatter_baseidx_v16i8:11866; RV32:       # %bb.0:11867; RV32-NEXT:    vsetivli zero, 16, e32, m4, ta, ma11868; RV32-NEXT:    vsext.vf4 v12, v911869; RV32-NEXT:    vsetvli zero, zero, e8, m1, ta, ma11870; RV32-NEXT:    vsoxei32.v v8, (a0), v12, v0.t11871; RV32-NEXT:    ret11872;11873; RV64V-LABEL: mscatter_baseidx_v16i8:11874; RV64V:       # %bb.0:11875; RV64V-NEXT:    vsetivli zero, 16, e64, m8, ta, ma11876; RV64V-NEXT:    vsext.vf8 v16, v911877; RV64V-NEXT:    vsetvli zero, zero, e8, m1, ta, ma11878; RV64V-NEXT:    vsoxei64.v v8, (a0), v16, v0.t11879; RV64V-NEXT:    ret11880;11881; RV64ZVE32F-LABEL: mscatter_baseidx_v16i8:11882; RV64ZVE32F:       # %bb.0:11883; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma11884; RV64ZVE32F-NEXT:    vmv.x.s a1, v011885; RV64ZVE32F-NEXT:    andi a2, a1, 111886; RV64ZVE32F-NEXT:    beqz a2, .LBB101_211887; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store11888; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma11889; RV64ZVE32F-NEXT:    vmv.x.s a2, v911890; RV64ZVE32F-NEXT:    add a2, a0, a211891; RV64ZVE32F-NEXT:    vse8.v v8, (a2)11892; RV64ZVE32F-NEXT:  .LBB101_2: # %else11893; RV64ZVE32F-NEXT:    andi a2, a1, 211894; RV64ZVE32F-NEXT:    beqz a2, .LBB101_411895; RV64ZVE32F-NEXT:  # %bb.3: # %cond.store111896; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma11897; RV64ZVE32F-NEXT:    vslidedown.vi v10, v9, 111898; RV64ZVE32F-NEXT:    vmv.x.s a2, v1011899; RV64ZVE32F-NEXT:    add a2, a0, a211900; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma11901; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 111902; RV64ZVE32F-NEXT:    vse8.v v10, (a2)11903; RV64ZVE32F-NEXT:  .LBB101_4: # %else211904; RV64ZVE32F-NEXT:    andi a2, a1, 411905; RV64ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma11906; RV64ZVE32F-NEXT:    vslidedown.vi v10, v9, 211907; RV64ZVE32F-NEXT:    beqz a2, .LBB101_611908; RV64ZVE32F-NEXT:  # %bb.5: # %cond.store311909; RV64ZVE32F-NEXT:    vmv.x.s a2, v1011910; RV64ZVE32F-NEXT:    add a2, a0, a211911; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma11912; RV64ZVE32F-NEXT:    vslidedown.vi v11, v8, 211913; RV64ZVE32F-NEXT:    vse8.v v11, (a2)11914; RV64ZVE32F-NEXT:  .LBB101_6: # %else411915; RV64ZVE32F-NEXT:    andi a2, a1, 811916; RV64ZVE32F-NEXT:    beqz a2, .LBB101_811917; RV64ZVE32F-NEXT:  # %bb.7: # %cond.store511918; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma11919; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 111920; RV64ZVE32F-NEXT:    vmv.x.s a2, v1011921; RV64ZVE32F-NEXT:    add a2, a0, a211922; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma11923; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 311924; RV64ZVE32F-NEXT:    vse8.v v10, (a2)11925; RV64ZVE32F-NEXT:  .LBB101_8: # %else611926; RV64ZVE32F-NEXT:    andi a2, a1, 1611927; RV64ZVE32F-NEXT:    vsetivli zero, 4, e8, mf2, ta, ma11928; RV64ZVE32F-NEXT:    vslidedown.vi v10, v9, 411929; RV64ZVE32F-NEXT:    beqz a2, .LBB101_1011930; RV64ZVE32F-NEXT:  # %bb.9: # %cond.store711931; RV64ZVE32F-NEXT:    vmv.x.s a2, v1011932; RV64ZVE32F-NEXT:    add a2, a0, a211933; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma11934; RV64ZVE32F-NEXT:    vslidedown.vi v11, v8, 411935; RV64ZVE32F-NEXT:    vse8.v v11, (a2)11936; RV64ZVE32F-NEXT:  .LBB101_10: # %else811937; RV64ZVE32F-NEXT:    andi a2, a1, 3211938; RV64ZVE32F-NEXT:    beqz a2, .LBB101_1211939; RV64ZVE32F-NEXT:  # %bb.11: # %cond.store911940; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma11941; RV64ZVE32F-NEXT:    vslidedown.vi v11, v10, 111942; RV64ZVE32F-NEXT:    vmv.x.s a2, v1111943; RV64ZVE32F-NEXT:    add a2, a0, a211944; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma11945; RV64ZVE32F-NEXT:    vslidedown.vi v11, v8, 511946; RV64ZVE32F-NEXT:    vse8.v v11, (a2)11947; RV64ZVE32F-NEXT:  .LBB101_12: # %else1011948; RV64ZVE32F-NEXT:    andi a2, a1, 6411949; RV64ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma11950; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 211951; RV64ZVE32F-NEXT:    beqz a2, .LBB101_1411952; RV64ZVE32F-NEXT:  # %bb.13: # %cond.store1111953; RV64ZVE32F-NEXT:    vmv.x.s a2, v1011954; RV64ZVE32F-NEXT:    add a2, a0, a211955; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma11956; RV64ZVE32F-NEXT:    vslidedown.vi v11, v8, 611957; RV64ZVE32F-NEXT:    vse8.v v11, (a2)11958; RV64ZVE32F-NEXT:  .LBB101_14: # %else1211959; RV64ZVE32F-NEXT:    andi a2, a1, 12811960; RV64ZVE32F-NEXT:    beqz a2, .LBB101_1611961; RV64ZVE32F-NEXT:  # %bb.15: # %cond.store1311962; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma11963; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 111964; RV64ZVE32F-NEXT:    vmv.x.s a2, v1011965; RV64ZVE32F-NEXT:    add a2, a0, a211966; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma11967; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 711968; RV64ZVE32F-NEXT:    vse8.v v10, (a2)11969; RV64ZVE32F-NEXT:  .LBB101_16: # %else1411970; RV64ZVE32F-NEXT:    andi a2, a1, 25611971; RV64ZVE32F-NEXT:    vsetivli zero, 8, e8, m1, ta, ma11972; RV64ZVE32F-NEXT:    vslidedown.vi v9, v9, 811973; RV64ZVE32F-NEXT:    beqz a2, .LBB101_1811974; RV64ZVE32F-NEXT:  # %bb.17: # %cond.store1511975; RV64ZVE32F-NEXT:    vmv.x.s a2, v911976; RV64ZVE32F-NEXT:    add a2, a0, a211977; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 811978; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma11979; RV64ZVE32F-NEXT:    vse8.v v10, (a2)11980; RV64ZVE32F-NEXT:  .LBB101_18: # %else1611981; RV64ZVE32F-NEXT:    andi a2, a1, 51211982; RV64ZVE32F-NEXT:    beqz a2, .LBB101_2011983; RV64ZVE32F-NEXT:  # %bb.19: # %cond.store1711984; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma11985; RV64ZVE32F-NEXT:    vslidedown.vi v10, v9, 111986; RV64ZVE32F-NEXT:    vmv.x.s a2, v1011987; RV64ZVE32F-NEXT:    add a2, a0, a211988; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma11989; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 911990; RV64ZVE32F-NEXT:    vse8.v v10, (a2)11991; RV64ZVE32F-NEXT:  .LBB101_20: # %else1811992; RV64ZVE32F-NEXT:    andi a2, a1, 102411993; RV64ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma11994; RV64ZVE32F-NEXT:    vslidedown.vi v10, v9, 211995; RV64ZVE32F-NEXT:    beqz a2, .LBB101_2211996; RV64ZVE32F-NEXT:  # %bb.21: # %cond.store1911997; RV64ZVE32F-NEXT:    vmv.x.s a2, v1011998; RV64ZVE32F-NEXT:    add a2, a0, a211999; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma12000; RV64ZVE32F-NEXT:    vslidedown.vi v11, v8, 1012001; RV64ZVE32F-NEXT:    vse8.v v11, (a2)12002; RV64ZVE32F-NEXT:  .LBB101_22: # %else2012003; RV64ZVE32F-NEXT:    slli a2, a1, 5212004; RV64ZVE32F-NEXT:    bgez a2, .LBB101_2412005; RV64ZVE32F-NEXT:  # %bb.23: # %cond.store2112006; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma12007; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 112008; RV64ZVE32F-NEXT:    vmv.x.s a2, v1012009; RV64ZVE32F-NEXT:    add a2, a0, a212010; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma12011; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 1112012; RV64ZVE32F-NEXT:    vse8.v v10, (a2)12013; RV64ZVE32F-NEXT:  .LBB101_24: # %else2212014; RV64ZVE32F-NEXT:    slli a2, a1, 5112015; RV64ZVE32F-NEXT:    vsetivli zero, 4, e8, mf2, ta, ma12016; RV64ZVE32F-NEXT:    vslidedown.vi v9, v9, 412017; RV64ZVE32F-NEXT:    bgez a2, .LBB101_2612018; RV64ZVE32F-NEXT:  # %bb.25: # %cond.store2312019; RV64ZVE32F-NEXT:    vmv.x.s a2, v912020; RV64ZVE32F-NEXT:    add a2, a0, a212021; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma12022; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 1212023; RV64ZVE32F-NEXT:    vse8.v v10, (a2)12024; RV64ZVE32F-NEXT:  .LBB101_26: # %else2412025; RV64ZVE32F-NEXT:    slli a2, a1, 5012026; RV64ZVE32F-NEXT:    bgez a2, .LBB101_2812027; RV64ZVE32F-NEXT:  # %bb.27: # %cond.store2512028; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma12029; RV64ZVE32F-NEXT:    vslidedown.vi v10, v9, 112030; RV64ZVE32F-NEXT:    vmv.x.s a2, v1012031; RV64ZVE32F-NEXT:    add a2, a0, a212032; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma12033; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 1312034; RV64ZVE32F-NEXT:    vse8.v v10, (a2)12035; RV64ZVE32F-NEXT:  .LBB101_28: # %else2612036; RV64ZVE32F-NEXT:    slli a2, a1, 4912037; RV64ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma12038; RV64ZVE32F-NEXT:    vslidedown.vi v9, v9, 212039; RV64ZVE32F-NEXT:    bgez a2, .LBB101_3012040; RV64ZVE32F-NEXT:  # %bb.29: # %cond.store2712041; RV64ZVE32F-NEXT:    vmv.x.s a2, v912042; RV64ZVE32F-NEXT:    add a2, a0, a212043; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma12044; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 1412045; RV64ZVE32F-NEXT:    vse8.v v10, (a2)12046; RV64ZVE32F-NEXT:  .LBB101_30: # %else2812047; RV64ZVE32F-NEXT:    lui a2, 104856812048; RV64ZVE32F-NEXT:    and a1, a1, a212049; RV64ZVE32F-NEXT:    beqz a1, .LBB101_3212050; RV64ZVE32F-NEXT:  # %bb.31: # %cond.store2912051; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma12052; RV64ZVE32F-NEXT:    vslidedown.vi v9, v9, 112053; RV64ZVE32F-NEXT:    vmv.x.s a1, v912054; RV64ZVE32F-NEXT:    add a0, a0, a112055; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma12056; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 1512057; RV64ZVE32F-NEXT:    vse8.v v8, (a0)12058; RV64ZVE32F-NEXT:  .LBB101_32: # %else3012059; RV64ZVE32F-NEXT:    ret12060  %ptrs = getelementptr inbounds i8, ptr %base, <16 x i8> %idxs12061  call void @llvm.masked.scatter.v16i8.v16p0(<16 x i8> %val, <16 x ptr> %ptrs, i32 1, <16 x i1> %m)12062  ret void12063}12064 12065define void @mscatter_baseidx_v32i8(<32 x i8> %val, ptr %base, <32 x i8> %idxs, <32 x i1> %m) {12066; RV32-LABEL: mscatter_baseidx_v32i8:12067; RV32:       # %bb.0:12068; RV32-NEXT:    li a1, 3212069; RV32-NEXT:    vsetvli zero, a1, e32, m8, ta, ma12070; RV32-NEXT:    vsext.vf4 v16, v1012071; RV32-NEXT:    vsetvli zero, zero, e8, m2, ta, ma12072; RV32-NEXT:    vsoxei32.v v8, (a0), v16, v0.t12073; RV32-NEXT:    ret12074;12075; RV64V-LABEL: mscatter_baseidx_v32i8:12076; RV64V:       # %bb.0:12077; RV64V-NEXT:    vsetivli zero, 16, e64, m8, ta, ma12078; RV64V-NEXT:    vsext.vf8 v16, v1012079; RV64V-NEXT:    vsetvli zero, zero, e8, m1, ta, ma12080; RV64V-NEXT:    vsoxei64.v v8, (a0), v16, v0.t12081; RV64V-NEXT:    vsetivli zero, 16, e8, m2, ta, ma12082; RV64V-NEXT:    vslidedown.vi v16, v8, 1612083; RV64V-NEXT:    vslidedown.vi v18, v10, 1612084; RV64V-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma12085; RV64V-NEXT:    vslidedown.vi v0, v0, 212086; RV64V-NEXT:    vsetivli zero, 16, e64, m8, ta, ma12087; RV64V-NEXT:    vsext.vf8 v8, v1812088; RV64V-NEXT:    vsetvli zero, zero, e8, m1, ta, ma12089; RV64V-NEXT:    vsoxei64.v v16, (a0), v8, v0.t12090; RV64V-NEXT:    ret12091;12092; RV64ZVE32F-LABEL: mscatter_baseidx_v32i8:12093; RV64ZVE32F:       # %bb.0:12094; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma12095; RV64ZVE32F-NEXT:    vmv.x.s a1, v012096; RV64ZVE32F-NEXT:    andi a2, a1, 112097; RV64ZVE32F-NEXT:    beqz a2, .LBB102_212098; RV64ZVE32F-NEXT:  # %bb.1: # %cond.store12099; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma12100; RV64ZVE32F-NEXT:    vmv.x.s a2, v1012101; RV64ZVE32F-NEXT:    add a2, a0, a212102; RV64ZVE32F-NEXT:    vse8.v v8, (a2)12103; RV64ZVE32F-NEXT:  .LBB102_2: # %else12104; RV64ZVE32F-NEXT:    andi a2, a1, 212105; RV64ZVE32F-NEXT:    beqz a2, .LBB102_412106; RV64ZVE32F-NEXT:  # %bb.3: # %cond.store112107; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma12108; RV64ZVE32F-NEXT:    vslidedown.vi v12, v10, 112109; RV64ZVE32F-NEXT:    vmv.x.s a2, v1212110; RV64ZVE32F-NEXT:    add a2, a0, a212111; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma12112; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 112113; RV64ZVE32F-NEXT:    vse8.v v12, (a2)12114; RV64ZVE32F-NEXT:  .LBB102_4: # %else212115; RV64ZVE32F-NEXT:    andi a2, a1, 412116; RV64ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma12117; RV64ZVE32F-NEXT:    vslidedown.vi v12, v10, 212118; RV64ZVE32F-NEXT:    beqz a2, .LBB102_612119; RV64ZVE32F-NEXT:  # %bb.5: # %cond.store312120; RV64ZVE32F-NEXT:    vmv.x.s a2, v1212121; RV64ZVE32F-NEXT:    add a2, a0, a212122; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma12123; RV64ZVE32F-NEXT:    vslidedown.vi v13, v8, 212124; RV64ZVE32F-NEXT:    vse8.v v13, (a2)12125; RV64ZVE32F-NEXT:  .LBB102_6: # %else412126; RV64ZVE32F-NEXT:    andi a2, a1, 812127; RV64ZVE32F-NEXT:    beqz a2, .LBB102_812128; RV64ZVE32F-NEXT:  # %bb.7: # %cond.store512129; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma12130; RV64ZVE32F-NEXT:    vslidedown.vi v12, v12, 112131; RV64ZVE32F-NEXT:    vmv.x.s a2, v1212132; RV64ZVE32F-NEXT:    add a2, a0, a212133; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma12134; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 312135; RV64ZVE32F-NEXT:    vse8.v v12, (a2)12136; RV64ZVE32F-NEXT:  .LBB102_8: # %else612137; RV64ZVE32F-NEXT:    andi a2, a1, 1612138; RV64ZVE32F-NEXT:    vsetivli zero, 4, e8, mf2, ta, ma12139; RV64ZVE32F-NEXT:    vslidedown.vi v12, v10, 412140; RV64ZVE32F-NEXT:    beqz a2, .LBB102_1012141; RV64ZVE32F-NEXT:  # %bb.9: # %cond.store712142; RV64ZVE32F-NEXT:    vmv.x.s a2, v1212143; RV64ZVE32F-NEXT:    add a2, a0, a212144; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma12145; RV64ZVE32F-NEXT:    vslidedown.vi v13, v8, 412146; RV64ZVE32F-NEXT:    vse8.v v13, (a2)12147; RV64ZVE32F-NEXT:  .LBB102_10: # %else812148; RV64ZVE32F-NEXT:    andi a2, a1, 3212149; RV64ZVE32F-NEXT:    beqz a2, .LBB102_1212150; RV64ZVE32F-NEXT:  # %bb.11: # %cond.store912151; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma12152; RV64ZVE32F-NEXT:    vslidedown.vi v13, v12, 112153; RV64ZVE32F-NEXT:    vmv.x.s a2, v1312154; RV64ZVE32F-NEXT:    add a2, a0, a212155; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma12156; RV64ZVE32F-NEXT:    vslidedown.vi v13, v8, 512157; RV64ZVE32F-NEXT:    vse8.v v13, (a2)12158; RV64ZVE32F-NEXT:  .LBB102_12: # %else1012159; RV64ZVE32F-NEXT:    andi a2, a1, 6412160; RV64ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma12161; RV64ZVE32F-NEXT:    vslidedown.vi v12, v12, 212162; RV64ZVE32F-NEXT:    beqz a2, .LBB102_1412163; RV64ZVE32F-NEXT:  # %bb.13: # %cond.store1112164; RV64ZVE32F-NEXT:    vmv.x.s a2, v1212165; RV64ZVE32F-NEXT:    add a2, a0, a212166; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma12167; RV64ZVE32F-NEXT:    vslidedown.vi v13, v8, 612168; RV64ZVE32F-NEXT:    vse8.v v13, (a2)12169; RV64ZVE32F-NEXT:  .LBB102_14: # %else1212170; RV64ZVE32F-NEXT:    andi a2, a1, 12812171; RV64ZVE32F-NEXT:    beqz a2, .LBB102_1612172; RV64ZVE32F-NEXT:  # %bb.15: # %cond.store1312173; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma12174; RV64ZVE32F-NEXT:    vslidedown.vi v12, v12, 112175; RV64ZVE32F-NEXT:    vmv.x.s a2, v1212176; RV64ZVE32F-NEXT:    add a2, a0, a212177; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma12178; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 712179; RV64ZVE32F-NEXT:    vse8.v v12, (a2)12180; RV64ZVE32F-NEXT:  .LBB102_16: # %else1412181; RV64ZVE32F-NEXT:    andi a2, a1, 25612182; RV64ZVE32F-NEXT:    vsetivli zero, 8, e8, m1, ta, ma12183; RV64ZVE32F-NEXT:    vslidedown.vi v12, v10, 812184; RV64ZVE32F-NEXT:    beqz a2, .LBB102_1812185; RV64ZVE32F-NEXT:  # %bb.17: # %cond.store1512186; RV64ZVE32F-NEXT:    vmv.x.s a2, v1212187; RV64ZVE32F-NEXT:    add a2, a0, a212188; RV64ZVE32F-NEXT:    vslidedown.vi v13, v8, 812189; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma12190; RV64ZVE32F-NEXT:    vse8.v v13, (a2)12191; RV64ZVE32F-NEXT:  .LBB102_18: # %else1612192; RV64ZVE32F-NEXT:    andi a2, a1, 51212193; RV64ZVE32F-NEXT:    beqz a2, .LBB102_2012194; RV64ZVE32F-NEXT:  # %bb.19: # %cond.store1712195; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma12196; RV64ZVE32F-NEXT:    vslidedown.vi v13, v12, 112197; RV64ZVE32F-NEXT:    vmv.x.s a2, v1312198; RV64ZVE32F-NEXT:    add a2, a0, a212199; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma12200; RV64ZVE32F-NEXT:    vslidedown.vi v13, v8, 912201; RV64ZVE32F-NEXT:    vse8.v v13, (a2)12202; RV64ZVE32F-NEXT:  .LBB102_20: # %else1812203; RV64ZVE32F-NEXT:    andi a2, a1, 102412204; RV64ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma12205; RV64ZVE32F-NEXT:    vslidedown.vi v13, v12, 212206; RV64ZVE32F-NEXT:    beqz a2, .LBB102_2212207; RV64ZVE32F-NEXT:  # %bb.21: # %cond.store1912208; RV64ZVE32F-NEXT:    vmv.x.s a2, v1312209; RV64ZVE32F-NEXT:    add a2, a0, a212210; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma12211; RV64ZVE32F-NEXT:    vslidedown.vi v14, v8, 1012212; RV64ZVE32F-NEXT:    vse8.v v14, (a2)12213; RV64ZVE32F-NEXT:  .LBB102_22: # %else2012214; RV64ZVE32F-NEXT:    slli a2, a1, 5212215; RV64ZVE32F-NEXT:    bgez a2, .LBB102_2412216; RV64ZVE32F-NEXT:  # %bb.23: # %cond.store2112217; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma12218; RV64ZVE32F-NEXT:    vslidedown.vi v13, v13, 112219; RV64ZVE32F-NEXT:    vmv.x.s a2, v1312220; RV64ZVE32F-NEXT:    add a2, a0, a212221; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma12222; RV64ZVE32F-NEXT:    vslidedown.vi v13, v8, 1112223; RV64ZVE32F-NEXT:    vse8.v v13, (a2)12224; RV64ZVE32F-NEXT:  .LBB102_24: # %else2212225; RV64ZVE32F-NEXT:    slli a2, a1, 5112226; RV64ZVE32F-NEXT:    vsetivli zero, 4, e8, mf2, ta, ma12227; RV64ZVE32F-NEXT:    vslidedown.vi v12, v12, 412228; RV64ZVE32F-NEXT:    bgez a2, .LBB102_2612229; RV64ZVE32F-NEXT:  # %bb.25: # %cond.store2312230; RV64ZVE32F-NEXT:    vmv.x.s a2, v1212231; RV64ZVE32F-NEXT:    add a2, a0, a212232; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma12233; RV64ZVE32F-NEXT:    vslidedown.vi v13, v8, 1212234; RV64ZVE32F-NEXT:    vse8.v v13, (a2)12235; RV64ZVE32F-NEXT:  .LBB102_26: # %else2412236; RV64ZVE32F-NEXT:    slli a2, a1, 5012237; RV64ZVE32F-NEXT:    bgez a2, .LBB102_2812238; RV64ZVE32F-NEXT:  # %bb.27: # %cond.store2512239; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma12240; RV64ZVE32F-NEXT:    vslidedown.vi v13, v12, 112241; RV64ZVE32F-NEXT:    vmv.x.s a2, v1312242; RV64ZVE32F-NEXT:    add a2, a0, a212243; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma12244; RV64ZVE32F-NEXT:    vslidedown.vi v13, v8, 1312245; RV64ZVE32F-NEXT:    vse8.v v13, (a2)12246; RV64ZVE32F-NEXT:  .LBB102_28: # %else2612247; RV64ZVE32F-NEXT:    slli a2, a1, 4912248; RV64ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma12249; RV64ZVE32F-NEXT:    vslidedown.vi v12, v12, 212250; RV64ZVE32F-NEXT:    bgez a2, .LBB102_3012251; RV64ZVE32F-NEXT:  # %bb.29: # %cond.store2712252; RV64ZVE32F-NEXT:    vmv.x.s a2, v1212253; RV64ZVE32F-NEXT:    add a2, a0, a212254; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma12255; RV64ZVE32F-NEXT:    vslidedown.vi v13, v8, 1412256; RV64ZVE32F-NEXT:    vse8.v v13, (a2)12257; RV64ZVE32F-NEXT:  .LBB102_30: # %else2812258; RV64ZVE32F-NEXT:    slli a2, a1, 4812259; RV64ZVE32F-NEXT:    vsetivli zero, 16, e8, m2, ta, ma12260; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 1612261; RV64ZVE32F-NEXT:    bltz a2, .LBB102_6312262; RV64ZVE32F-NEXT:  # %bb.31: # %else3012263; RV64ZVE32F-NEXT:    slli a2, a1, 4712264; RV64ZVE32F-NEXT:    bltz a2, .LBB102_6412265; RV64ZVE32F-NEXT:  .LBB102_32: # %else3212266; RV64ZVE32F-NEXT:    slli a2, a1, 4612267; RV64ZVE32F-NEXT:    bgez a2, .LBB102_3412268; RV64ZVE32F-NEXT:  .LBB102_33: # %cond.store3312269; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma12270; RV64ZVE32F-NEXT:    vslidedown.vi v11, v10, 112271; RV64ZVE32F-NEXT:    vmv.x.s a2, v1112272; RV64ZVE32F-NEXT:    add a2, a0, a212273; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m2, ta, ma12274; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 1712275; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma12276; RV64ZVE32F-NEXT:    vse8.v v12, (a2)12277; RV64ZVE32F-NEXT:  .LBB102_34: # %else3412278; RV64ZVE32F-NEXT:    slli a2, a1, 4512279; RV64ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma12280; RV64ZVE32F-NEXT:    vslidedown.vi v11, v10, 212281; RV64ZVE32F-NEXT:    bgez a2, .LBB102_3612282; RV64ZVE32F-NEXT:  # %bb.35: # %cond.store3512283; RV64ZVE32F-NEXT:    vmv.x.s a2, v1112284; RV64ZVE32F-NEXT:    add a2, a0, a212285; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m2, ta, ma12286; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 1812287; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma12288; RV64ZVE32F-NEXT:    vse8.v v12, (a2)12289; RV64ZVE32F-NEXT:  .LBB102_36: # %else3612290; RV64ZVE32F-NEXT:    slli a2, a1, 4412291; RV64ZVE32F-NEXT:    bgez a2, .LBB102_3812292; RV64ZVE32F-NEXT:  # %bb.37: # %cond.store3712293; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma12294; RV64ZVE32F-NEXT:    vslidedown.vi v11, v11, 112295; RV64ZVE32F-NEXT:    vmv.x.s a2, v1112296; RV64ZVE32F-NEXT:    add a2, a0, a212297; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m2, ta, ma12298; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 1912299; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma12300; RV64ZVE32F-NEXT:    vse8.v v12, (a2)12301; RV64ZVE32F-NEXT:  .LBB102_38: # %else3812302; RV64ZVE32F-NEXT:    slli a2, a1, 4312303; RV64ZVE32F-NEXT:    vsetivli zero, 4, e8, mf2, ta, ma12304; RV64ZVE32F-NEXT:    vslidedown.vi v11, v10, 412305; RV64ZVE32F-NEXT:    bgez a2, .LBB102_4012306; RV64ZVE32F-NEXT:  # %bb.39: # %cond.store3912307; RV64ZVE32F-NEXT:    vmv.x.s a2, v1112308; RV64ZVE32F-NEXT:    add a2, a0, a212309; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m2, ta, ma12310; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 2012311; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma12312; RV64ZVE32F-NEXT:    vse8.v v12, (a2)12313; RV64ZVE32F-NEXT:  .LBB102_40: # %else4012314; RV64ZVE32F-NEXT:    slli a2, a1, 4212315; RV64ZVE32F-NEXT:    bgez a2, .LBB102_4212316; RV64ZVE32F-NEXT:  # %bb.41: # %cond.store4112317; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma12318; RV64ZVE32F-NEXT:    vslidedown.vi v12, v11, 112319; RV64ZVE32F-NEXT:    vmv.x.s a2, v1212320; RV64ZVE32F-NEXT:    add a2, a0, a212321; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m2, ta, ma12322; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 2112323; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma12324; RV64ZVE32F-NEXT:    vse8.v v12, (a2)12325; RV64ZVE32F-NEXT:  .LBB102_42: # %else4212326; RV64ZVE32F-NEXT:    slli a2, a1, 4112327; RV64ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma12328; RV64ZVE32F-NEXT:    vslidedown.vi v11, v11, 212329; RV64ZVE32F-NEXT:    bgez a2, .LBB102_4412330; RV64ZVE32F-NEXT:  # %bb.43: # %cond.store4312331; RV64ZVE32F-NEXT:    vmv.x.s a2, v1112332; RV64ZVE32F-NEXT:    add a2, a0, a212333; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m2, ta, ma12334; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 2212335; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma12336; RV64ZVE32F-NEXT:    vse8.v v12, (a2)12337; RV64ZVE32F-NEXT:  .LBB102_44: # %else4412338; RV64ZVE32F-NEXT:    slli a2, a1, 4012339; RV64ZVE32F-NEXT:    bgez a2, .LBB102_4612340; RV64ZVE32F-NEXT:  # %bb.45: # %cond.store4512341; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma12342; RV64ZVE32F-NEXT:    vslidedown.vi v11, v11, 112343; RV64ZVE32F-NEXT:    vmv.x.s a2, v1112344; RV64ZVE32F-NEXT:    add a2, a0, a212345; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m2, ta, ma12346; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 2312347; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma12348; RV64ZVE32F-NEXT:    vse8.v v12, (a2)12349; RV64ZVE32F-NEXT:  .LBB102_46: # %else4612350; RV64ZVE32F-NEXT:    slli a2, a1, 3912351; RV64ZVE32F-NEXT:    vsetivli zero, 8, e8, m1, ta, ma12352; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 812353; RV64ZVE32F-NEXT:    bgez a2, .LBB102_4812354; RV64ZVE32F-NEXT:  # %bb.47: # %cond.store4712355; RV64ZVE32F-NEXT:    vmv.x.s a2, v1012356; RV64ZVE32F-NEXT:    add a2, a0, a212357; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m2, ta, ma12358; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 2412359; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma12360; RV64ZVE32F-NEXT:    vse8.v v12, (a2)12361; RV64ZVE32F-NEXT:  .LBB102_48: # %else4812362; RV64ZVE32F-NEXT:    slli a2, a1, 3812363; RV64ZVE32F-NEXT:    bgez a2, .LBB102_5012364; RV64ZVE32F-NEXT:  # %bb.49: # %cond.store4912365; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma12366; RV64ZVE32F-NEXT:    vslidedown.vi v11, v10, 112367; RV64ZVE32F-NEXT:    vmv.x.s a2, v1112368; RV64ZVE32F-NEXT:    add a2, a0, a212369; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m2, ta, ma12370; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 2512371; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma12372; RV64ZVE32F-NEXT:    vse8.v v12, (a2)12373; RV64ZVE32F-NEXT:  .LBB102_50: # %else5012374; RV64ZVE32F-NEXT:    slli a2, a1, 3712375; RV64ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma12376; RV64ZVE32F-NEXT:    vslidedown.vi v11, v10, 212377; RV64ZVE32F-NEXT:    bgez a2, .LBB102_5212378; RV64ZVE32F-NEXT:  # %bb.51: # %cond.store5112379; RV64ZVE32F-NEXT:    vmv.x.s a2, v1112380; RV64ZVE32F-NEXT:    add a2, a0, a212381; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m2, ta, ma12382; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 2612383; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma12384; RV64ZVE32F-NEXT:    vse8.v v12, (a2)12385; RV64ZVE32F-NEXT:  .LBB102_52: # %else5212386; RV64ZVE32F-NEXT:    slli a2, a1, 3612387; RV64ZVE32F-NEXT:    bgez a2, .LBB102_5412388; RV64ZVE32F-NEXT:  # %bb.53: # %cond.store5312389; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma12390; RV64ZVE32F-NEXT:    vslidedown.vi v11, v11, 112391; RV64ZVE32F-NEXT:    vmv.x.s a2, v1112392; RV64ZVE32F-NEXT:    add a2, a0, a212393; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m2, ta, ma12394; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 2712395; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma12396; RV64ZVE32F-NEXT:    vse8.v v12, (a2)12397; RV64ZVE32F-NEXT:  .LBB102_54: # %else5412398; RV64ZVE32F-NEXT:    slli a2, a1, 3512399; RV64ZVE32F-NEXT:    vsetivli zero, 4, e8, mf2, ta, ma12400; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 412401; RV64ZVE32F-NEXT:    bgez a2, .LBB102_5612402; RV64ZVE32F-NEXT:  # %bb.55: # %cond.store5512403; RV64ZVE32F-NEXT:    vmv.x.s a2, v1012404; RV64ZVE32F-NEXT:    add a2, a0, a212405; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m2, ta, ma12406; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 2812407; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma12408; RV64ZVE32F-NEXT:    vse8.v v12, (a2)12409; RV64ZVE32F-NEXT:  .LBB102_56: # %else5612410; RV64ZVE32F-NEXT:    slli a2, a1, 3412411; RV64ZVE32F-NEXT:    bgez a2, .LBB102_5812412; RV64ZVE32F-NEXT:  # %bb.57: # %cond.store5712413; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma12414; RV64ZVE32F-NEXT:    vslidedown.vi v11, v10, 112415; RV64ZVE32F-NEXT:    vmv.x.s a2, v1112416; RV64ZVE32F-NEXT:    add a2, a0, a212417; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m2, ta, ma12418; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 2912419; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma12420; RV64ZVE32F-NEXT:    vse8.v v12, (a2)12421; RV64ZVE32F-NEXT:  .LBB102_58: # %else5812422; RV64ZVE32F-NEXT:    slli a2, a1, 3312423; RV64ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma12424; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 212425; RV64ZVE32F-NEXT:    bgez a2, .LBB102_6012426; RV64ZVE32F-NEXT:  # %bb.59: # %cond.store5912427; RV64ZVE32F-NEXT:    vmv.x.s a2, v1012428; RV64ZVE32F-NEXT:    add a2, a0, a212429; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m2, ta, ma12430; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 3012431; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma12432; RV64ZVE32F-NEXT:    vse8.v v12, (a2)12433; RV64ZVE32F-NEXT:  .LBB102_60: # %else6012434; RV64ZVE32F-NEXT:    lui a2, 52428812435; RV64ZVE32F-NEXT:    and a1, a1, a212436; RV64ZVE32F-NEXT:    beqz a1, .LBB102_6212437; RV64ZVE32F-NEXT:  # %bb.61: # %cond.store6112438; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma12439; RV64ZVE32F-NEXT:    vslidedown.vi v10, v10, 112440; RV64ZVE32F-NEXT:    vmv.x.s a1, v1012441; RV64ZVE32F-NEXT:    add a0, a0, a112442; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m2, ta, ma12443; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 3112444; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma12445; RV64ZVE32F-NEXT:    vse8.v v8, (a0)12446; RV64ZVE32F-NEXT:  .LBB102_62: # %else6212447; RV64ZVE32F-NEXT:    ret12448; RV64ZVE32F-NEXT:  .LBB102_63: # %cond.store2912449; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma12450; RV64ZVE32F-NEXT:    vslidedown.vi v11, v12, 112451; RV64ZVE32F-NEXT:    vmv.x.s a2, v1112452; RV64ZVE32F-NEXT:    add a2, a0, a212453; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma12454; RV64ZVE32F-NEXT:    vslidedown.vi v11, v8, 1512455; RV64ZVE32F-NEXT:    vse8.v v11, (a2)12456; RV64ZVE32F-NEXT:    slli a2, a1, 4712457; RV64ZVE32F-NEXT:    bgez a2, .LBB102_3212458; RV64ZVE32F-NEXT:  .LBB102_64: # %cond.store3112459; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m2, ta, ma12460; RV64ZVE32F-NEXT:    vmv.x.s a2, v1012461; RV64ZVE32F-NEXT:    add a2, a0, a212462; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 1612463; RV64ZVE32F-NEXT:    vsetivli zero, 1, e8, m1, ta, ma12464; RV64ZVE32F-NEXT:    vse8.v v12, (a2)12465; RV64ZVE32F-NEXT:    slli a2, a1, 4612466; RV64ZVE32F-NEXT:    bltz a2, .LBB102_3312467; RV64ZVE32F-NEXT:    j .LBB102_3412468  %ptrs = getelementptr inbounds i8, ptr %base, <32 x i8> %idxs12469  call void @llvm.masked.scatter.v32i8.v32p0(<32 x i8> %val, <32 x ptr> %ptrs, i32 1, <32 x i1> %m)12470  ret void12471}12472 12473define void @mscatter_unit_stride(<8 x i16> %val, ptr %base) {12474; CHECK-LABEL: mscatter_unit_stride:12475; CHECK:       # %bb.0:12476; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma12477; CHECK-NEXT:    vse16.v v8, (a0)12478; CHECK-NEXT:    ret12479  %ptrs = getelementptr inbounds i16, ptr %base, <8 x i64>  <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7>12480  call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> %val, <8 x ptr> %ptrs, i32 2, <8 x i1> splat (i1 true))12481  ret void12482}12483 12484define void @mscatter_unit_stride_with_offset(<8 x i16> %val, ptr %base) {12485; CHECK-LABEL: mscatter_unit_stride_with_offset:12486; CHECK:       # %bb.0:12487; CHECK-NEXT:    addi a0, a0, 1012488; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma12489; CHECK-NEXT:    vse16.v v8, (a0)12490; CHECK-NEXT:    ret12491  %ptrs = getelementptr inbounds i16, ptr %base, <8 x i64>  <i64 5, i64 6, i64 7, i64 8, i64 9, i64 10, i64 11, i64 12>12492  call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> %val, <8 x ptr> %ptrs, i32 2, <8 x i1> splat (i1 true))12493  ret void12494}12495 12496define void @mscatter_shuffle_reverse(<8 x i16> %val, ptr %base) {12497; CHECK-LABEL: mscatter_shuffle_reverse:12498; CHECK:       # %bb.0:12499; CHECK-NEXT:    addi a0, a0, 1412500; CHECK-NEXT:    li a1, -212501; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma12502; CHECK-NEXT:    vsse16.v v8, (a0), a112503; CHECK-NEXT:    ret12504  %ptrs = getelementptr inbounds i16, ptr %base, <8 x i64>  <i64 7, i64 6, i64 5, i64 4, i64 3, i64 2, i64 1, i64 0>12505  call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> %val, <8 x ptr> %ptrs, i32 2, <8 x i1> splat (i1 true))12506  ret void12507}12508 12509define void @mscatter_shuffle_rotate(<8 x i16> %val, ptr %base) {12510; RV32-LABEL: mscatter_shuffle_rotate:12511; RV32:       # %bb.0:12512; RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma12513; RV32-NEXT:    vslidedown.vi v9, v8, 412514; RV32-NEXT:    vslideup.vi v9, v8, 412515; RV32-NEXT:    vse16.v v9, (a0)12516; RV32-NEXT:    ret12517;12518; RV64V-LABEL: mscatter_shuffle_rotate:12519; RV64V:       # %bb.0:12520; RV64V-NEXT:    vsetivli zero, 8, e16, m1, ta, ma12521; RV64V-NEXT:    vslidedown.vi v9, v8, 412522; RV64V-NEXT:    vslideup.vi v9, v8, 412523; RV64V-NEXT:    vse16.v v9, (a0)12524; RV64V-NEXT:    ret12525;12526; RV64ZVE32F-LABEL: mscatter_shuffle_rotate:12527; RV64ZVE32F:       # %bb.0:12528; RV64ZVE32F-NEXT:    addi a1, a0, 612529; RV64ZVE32F-NEXT:    addi a2, a0, 412530; RV64ZVE32F-NEXT:    addi a3, a0, 212531; RV64ZVE32F-NEXT:    addi a4, a0, 1412532; RV64ZVE32F-NEXT:    addi a5, a0, 1212533; RV64ZVE32F-NEXT:    addi a6, a0, 1012534; RV64ZVE32F-NEXT:    addi a7, a0, 812535; RV64ZVE32F-NEXT:    vsetivli zero, 1, e16, m1, ta, ma12536; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 112537; RV64ZVE32F-NEXT:    vse16.v v8, (a7)12538; RV64ZVE32F-NEXT:    vse16.v v9, (a6)12539; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 212540; RV64ZVE32F-NEXT:    vse16.v v9, (a5)12541; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 312542; RV64ZVE32F-NEXT:    vse16.v v9, (a4)12543; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 412544; RV64ZVE32F-NEXT:    vse16.v v9, (a0)12545; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 512546; RV64ZVE32F-NEXT:    vse16.v v9, (a3)12547; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 612548; RV64ZVE32F-NEXT:    vslidedown.vi v8, v8, 712549; RV64ZVE32F-NEXT:    vse16.v v9, (a2)12550; RV64ZVE32F-NEXT:    vse16.v v8, (a1)12551; RV64ZVE32F-NEXT:    ret12552  %ptrs = getelementptr inbounds i16, ptr %base, <8 x i64>  <i64 4, i64 5, i64 6, i64 7, i64 0, i64 1, i64 2, i64 3>12553  call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> %val, <8 x ptr> %ptrs, i32 2, <8 x i1> splat (i1 true))12554  ret void12555}12556;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:12557; RV32V-ZVFH: {{.*}}12558; RV32V-ZVFHMIN: {{.*}}12559; RV32ZVE32F-ZVFH: {{.*}}12560; RV32ZVE32F-ZVFHMIN: {{.*}}12561; RV64: {{.*}}12562; RV64V-ZVFH: {{.*}}12563; RV64V-ZVFHMIN: {{.*}}12564