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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,RV32 %s4; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,RV64 %s6 7define <2 x half> @vp_nearbyint_v2f16(<2 x half> %va, <2 x i1> %m, i32 zeroext %evl) {8; CHECK-LABEL: vp_nearbyint_v2f16:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma11; CHECK-NEXT: vfabs.v v9, v8, v0.t12; CHECK-NEXT: li a0, 2513; CHECK-NEXT: slli a0, a0, 1014; CHECK-NEXT: fmv.h.x fa5, a015; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu16; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t17; CHECK-NEXT: frflags a018; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma19; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t20; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t21; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu22; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t23; CHECK-NEXT: fsflags a024; CHECK-NEXT: ret25 %v = call <2 x half> @llvm.vp.nearbyint.v2f16(<2 x half> %va, <2 x i1> %m, i32 %evl)26 ret <2 x half> %v27}28 29define <2 x half> @vp_nearbyint_v2f16_unmasked(<2 x half> %va, i32 zeroext %evl) {30; CHECK-LABEL: vp_nearbyint_v2f16_unmasked:31; CHECK: # %bb.0:32; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma33; CHECK-NEXT: vfabs.v v9, v834; CHECK-NEXT: li a0, 2535; CHECK-NEXT: slli a0, a0, 1036; CHECK-NEXT: fmv.h.x fa5, a037; CHECK-NEXT: vmflt.vf v0, v9, fa538; CHECK-NEXT: frflags a039; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t40; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t41; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu42; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t43; CHECK-NEXT: fsflags a044; CHECK-NEXT: ret45 %v = call <2 x half> @llvm.vp.nearbyint.v2f16(<2 x half> %va, <2 x i1> splat (i1 true), i32 %evl)46 ret <2 x half> %v47}48 49define <4 x half> @vp_nearbyint_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl) {50; CHECK-LABEL: vp_nearbyint_v4f16:51; CHECK: # %bb.0:52; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma53; CHECK-NEXT: vfabs.v v9, v8, v0.t54; CHECK-NEXT: li a0, 2555; CHECK-NEXT: slli a0, a0, 1056; CHECK-NEXT: fmv.h.x fa5, a057; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu58; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t59; CHECK-NEXT: frflags a060; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma61; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t62; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t63; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu64; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t65; CHECK-NEXT: fsflags a066; CHECK-NEXT: ret67 %v = call <4 x half> @llvm.vp.nearbyint.v4f16(<4 x half> %va, <4 x i1> %m, i32 %evl)68 ret <4 x half> %v69}70 71define <4 x half> @vp_nearbyint_v4f16_unmasked(<4 x half> %va, i32 zeroext %evl) {72; CHECK-LABEL: vp_nearbyint_v4f16_unmasked:73; CHECK: # %bb.0:74; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma75; CHECK-NEXT: vfabs.v v9, v876; CHECK-NEXT: li a0, 2577; CHECK-NEXT: slli a0, a0, 1078; CHECK-NEXT: fmv.h.x fa5, a079; CHECK-NEXT: vmflt.vf v0, v9, fa580; CHECK-NEXT: frflags a081; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t82; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t83; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu84; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t85; CHECK-NEXT: fsflags a086; CHECK-NEXT: ret87 %v = call <4 x half> @llvm.vp.nearbyint.v4f16(<4 x half> %va, <4 x i1> splat (i1 true), i32 %evl)88 ret <4 x half> %v89}90 91define <8 x half> @vp_nearbyint_v8f16(<8 x half> %va, <8 x i1> %m, i32 zeroext %evl) {92; CHECK-LABEL: vp_nearbyint_v8f16:93; CHECK: # %bb.0:94; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma95; CHECK-NEXT: vfabs.v v9, v8, v0.t96; CHECK-NEXT: li a0, 2597; CHECK-NEXT: slli a0, a0, 1098; CHECK-NEXT: fmv.h.x fa5, a099; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu100; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t101; CHECK-NEXT: frflags a0102; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma103; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t104; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t105; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu106; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t107; CHECK-NEXT: fsflags a0108; CHECK-NEXT: ret109 %v = call <8 x half> @llvm.vp.nearbyint.v8f16(<8 x half> %va, <8 x i1> %m, i32 %evl)110 ret <8 x half> %v111}112 113define <8 x half> @vp_nearbyint_v8f16_unmasked(<8 x half> %va, i32 zeroext %evl) {114; CHECK-LABEL: vp_nearbyint_v8f16_unmasked:115; CHECK: # %bb.0:116; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma117; CHECK-NEXT: vfabs.v v9, v8118; CHECK-NEXT: li a0, 25119; CHECK-NEXT: slli a0, a0, 10120; CHECK-NEXT: fmv.h.x fa5, a0121; CHECK-NEXT: vmflt.vf v0, v9, fa5122; CHECK-NEXT: frflags a0123; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t124; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t125; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu126; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t127; CHECK-NEXT: fsflags a0128; CHECK-NEXT: ret129 %v = call <8 x half> @llvm.vp.nearbyint.v8f16(<8 x half> %va, <8 x i1> splat (i1 true), i32 %evl)130 ret <8 x half> %v131}132 133define <16 x half> @vp_nearbyint_v16f16(<16 x half> %va, <16 x i1> %m, i32 zeroext %evl) {134; CHECK-LABEL: vp_nearbyint_v16f16:135; CHECK: # %bb.0:136; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma137; CHECK-NEXT: vmv1r.v v10, v0138; CHECK-NEXT: vfabs.v v12, v8, v0.t139; CHECK-NEXT: li a0, 25140; CHECK-NEXT: slli a0, a0, 10141; CHECK-NEXT: fmv.h.x fa5, a0142; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu143; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t144; CHECK-NEXT: frflags a0145; CHECK-NEXT: vmv1r.v v0, v10146; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma147; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t148; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t149; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu150; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t151; CHECK-NEXT: fsflags a0152; CHECK-NEXT: ret153 %v = call <16 x half> @llvm.vp.nearbyint.v16f16(<16 x half> %va, <16 x i1> %m, i32 %evl)154 ret <16 x half> %v155}156 157define <16 x half> @vp_nearbyint_v16f16_unmasked(<16 x half> %va, i32 zeroext %evl) {158; CHECK-LABEL: vp_nearbyint_v16f16_unmasked:159; CHECK: # %bb.0:160; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma161; CHECK-NEXT: vfabs.v v10, v8162; CHECK-NEXT: li a0, 25163; CHECK-NEXT: slli a0, a0, 10164; CHECK-NEXT: fmv.h.x fa5, a0165; CHECK-NEXT: vmflt.vf v0, v10, fa5166; CHECK-NEXT: frflags a0167; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t168; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t169; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu170; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t171; CHECK-NEXT: fsflags a0172; CHECK-NEXT: ret173 %v = call <16 x half> @llvm.vp.nearbyint.v16f16(<16 x half> %va, <16 x i1> splat (i1 true), i32 %evl)174 ret <16 x half> %v175}176 177define <2 x float> @vp_nearbyint_v2f32(<2 x float> %va, <2 x i1> %m, i32 zeroext %evl) {178; CHECK-LABEL: vp_nearbyint_v2f32:179; CHECK: # %bb.0:180; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma181; CHECK-NEXT: vfabs.v v9, v8, v0.t182; CHECK-NEXT: lui a0, 307200183; CHECK-NEXT: fmv.w.x fa5, a0184; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu185; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t186; CHECK-NEXT: frflags a0187; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma188; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t189; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t190; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu191; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t192; CHECK-NEXT: fsflags a0193; CHECK-NEXT: ret194 %v = call <2 x float> @llvm.vp.nearbyint.v2f32(<2 x float> %va, <2 x i1> %m, i32 %evl)195 ret <2 x float> %v196}197 198define <2 x float> @vp_nearbyint_v2f32_unmasked(<2 x float> %va, i32 zeroext %evl) {199; CHECK-LABEL: vp_nearbyint_v2f32_unmasked:200; CHECK: # %bb.0:201; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma202; CHECK-NEXT: vfabs.v v9, v8203; CHECK-NEXT: lui a0, 307200204; CHECK-NEXT: fmv.w.x fa5, a0205; CHECK-NEXT: vmflt.vf v0, v9, fa5206; CHECK-NEXT: frflags a0207; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t208; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t209; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu210; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t211; CHECK-NEXT: fsflags a0212; CHECK-NEXT: ret213 %v = call <2 x float> @llvm.vp.nearbyint.v2f32(<2 x float> %va, <2 x i1> splat (i1 true), i32 %evl)214 ret <2 x float> %v215}216 217define <4 x float> @vp_nearbyint_v4f32(<4 x float> %va, <4 x i1> %m, i32 zeroext %evl) {218; CHECK-LABEL: vp_nearbyint_v4f32:219; CHECK: # %bb.0:220; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma221; CHECK-NEXT: vfabs.v v9, v8, v0.t222; CHECK-NEXT: lui a0, 307200223; CHECK-NEXT: fmv.w.x fa5, a0224; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu225; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t226; CHECK-NEXT: frflags a0227; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma228; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t229; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t230; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu231; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t232; CHECK-NEXT: fsflags a0233; CHECK-NEXT: ret234 %v = call <4 x float> @llvm.vp.nearbyint.v4f32(<4 x float> %va, <4 x i1> %m, i32 %evl)235 ret <4 x float> %v236}237 238define <4 x float> @vp_nearbyint_v4f32_unmasked(<4 x float> %va, i32 zeroext %evl) {239; CHECK-LABEL: vp_nearbyint_v4f32_unmasked:240; CHECK: # %bb.0:241; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma242; CHECK-NEXT: vfabs.v v9, v8243; CHECK-NEXT: lui a0, 307200244; CHECK-NEXT: fmv.w.x fa5, a0245; CHECK-NEXT: vmflt.vf v0, v9, fa5246; CHECK-NEXT: frflags a0247; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t248; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t249; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu250; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t251; CHECK-NEXT: fsflags a0252; CHECK-NEXT: ret253 %v = call <4 x float> @llvm.vp.nearbyint.v4f32(<4 x float> %va, <4 x i1> splat (i1 true), i32 %evl)254 ret <4 x float> %v255}256 257define <8 x float> @vp_nearbyint_v8f32(<8 x float> %va, <8 x i1> %m, i32 zeroext %evl) {258; CHECK-LABEL: vp_nearbyint_v8f32:259; CHECK: # %bb.0:260; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma261; CHECK-NEXT: vmv1r.v v10, v0262; CHECK-NEXT: vfabs.v v12, v8, v0.t263; CHECK-NEXT: lui a0, 307200264; CHECK-NEXT: fmv.w.x fa5, a0265; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu266; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t267; CHECK-NEXT: frflags a0268; CHECK-NEXT: vmv1r.v v0, v10269; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma270; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t271; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t272; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu273; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t274; CHECK-NEXT: fsflags a0275; CHECK-NEXT: ret276 %v = call <8 x float> @llvm.vp.nearbyint.v8f32(<8 x float> %va, <8 x i1> %m, i32 %evl)277 ret <8 x float> %v278}279 280define <8 x float> @vp_nearbyint_v8f32_unmasked(<8 x float> %va, i32 zeroext %evl) {281; CHECK-LABEL: vp_nearbyint_v8f32_unmasked:282; CHECK: # %bb.0:283; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma284; CHECK-NEXT: vfabs.v v10, v8285; CHECK-NEXT: lui a0, 307200286; CHECK-NEXT: fmv.w.x fa5, a0287; CHECK-NEXT: vmflt.vf v0, v10, fa5288; CHECK-NEXT: frflags a0289; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t290; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t291; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu292; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t293; CHECK-NEXT: fsflags a0294; CHECK-NEXT: ret295 %v = call <8 x float> @llvm.vp.nearbyint.v8f32(<8 x float> %va, <8 x i1> splat (i1 true), i32 %evl)296 ret <8 x float> %v297}298 299define <16 x float> @vp_nearbyint_v16f32(<16 x float> %va, <16 x i1> %m, i32 zeroext %evl) {300; CHECK-LABEL: vp_nearbyint_v16f32:301; CHECK: # %bb.0:302; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma303; CHECK-NEXT: vmv1r.v v12, v0304; CHECK-NEXT: vfabs.v v16, v8, v0.t305; CHECK-NEXT: lui a0, 307200306; CHECK-NEXT: fmv.w.x fa5, a0307; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu308; CHECK-NEXT: vmflt.vf v12, v16, fa5, v0.t309; CHECK-NEXT: frflags a0310; CHECK-NEXT: vmv1r.v v0, v12311; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma312; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t313; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t314; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu315; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t316; CHECK-NEXT: fsflags a0317; CHECK-NEXT: ret318 %v = call <16 x float> @llvm.vp.nearbyint.v16f32(<16 x float> %va, <16 x i1> %m, i32 %evl)319 ret <16 x float> %v320}321 322define <16 x float> @vp_nearbyint_v16f32_unmasked(<16 x float> %va, i32 zeroext %evl) {323; CHECK-LABEL: vp_nearbyint_v16f32_unmasked:324; CHECK: # %bb.0:325; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma326; CHECK-NEXT: vfabs.v v12, v8327; CHECK-NEXT: lui a0, 307200328; CHECK-NEXT: fmv.w.x fa5, a0329; CHECK-NEXT: vmflt.vf v0, v12, fa5330; CHECK-NEXT: frflags a0331; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t332; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t333; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu334; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t335; CHECK-NEXT: fsflags a0336; CHECK-NEXT: ret337 %v = call <16 x float> @llvm.vp.nearbyint.v16f32(<16 x float> %va, <16 x i1> splat (i1 true), i32 %evl)338 ret <16 x float> %v339}340 341define <2 x double> @vp_nearbyint_v2f64(<2 x double> %va, <2 x i1> %m, i32 zeroext %evl) {342; RV32-LABEL: vp_nearbyint_v2f64:343; RV32: # %bb.0:344; RV32-NEXT: lui a1, %hi(.LCPI16_0)345; RV32-NEXT: fld fa5, %lo(.LCPI16_0)(a1)346; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma347; RV32-NEXT: vfabs.v v9, v8, v0.t348; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu349; RV32-NEXT: vmflt.vf v0, v9, fa5, v0.t350; RV32-NEXT: frflags a0351; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma352; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t353; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t354; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu355; RV32-NEXT: vfsgnj.vv v8, v9, v8, v0.t356; RV32-NEXT: fsflags a0357; RV32-NEXT: ret358;359; RV64-LABEL: vp_nearbyint_v2f64:360; RV64: # %bb.0:361; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma362; RV64-NEXT: vfabs.v v9, v8, v0.t363; RV64-NEXT: li a0, 1075364; RV64-NEXT: slli a0, a0, 52365; RV64-NEXT: fmv.d.x fa5, a0366; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu367; RV64-NEXT: vmflt.vf v0, v9, fa5, v0.t368; RV64-NEXT: frflags a0369; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma370; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t371; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t372; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu373; RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t374; RV64-NEXT: fsflags a0375; RV64-NEXT: ret376 %v = call <2 x double> @llvm.vp.nearbyint.v2f64(<2 x double> %va, <2 x i1> %m, i32 %evl)377 ret <2 x double> %v378}379 380define <2 x double> @vp_nearbyint_v2f64_unmasked(<2 x double> %va, i32 zeroext %evl) {381; RV32-LABEL: vp_nearbyint_v2f64_unmasked:382; RV32: # %bb.0:383; RV32-NEXT: lui a1, %hi(.LCPI17_0)384; RV32-NEXT: fld fa5, %lo(.LCPI17_0)(a1)385; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma386; RV32-NEXT: vfabs.v v9, v8387; RV32-NEXT: vmflt.vf v0, v9, fa5388; RV32-NEXT: frflags a0389; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t390; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t391; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu392; RV32-NEXT: vfsgnj.vv v8, v9, v8, v0.t393; RV32-NEXT: fsflags a0394; RV32-NEXT: ret395;396; RV64-LABEL: vp_nearbyint_v2f64_unmasked:397; RV64: # %bb.0:398; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma399; RV64-NEXT: vfabs.v v9, v8400; RV64-NEXT: li a0, 1075401; RV64-NEXT: slli a0, a0, 52402; RV64-NEXT: fmv.d.x fa5, a0403; RV64-NEXT: vmflt.vf v0, v9, fa5404; RV64-NEXT: frflags a0405; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t406; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t407; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu408; RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t409; RV64-NEXT: fsflags a0410; RV64-NEXT: ret411 %v = call <2 x double> @llvm.vp.nearbyint.v2f64(<2 x double> %va, <2 x i1> splat (i1 true), i32 %evl)412 ret <2 x double> %v413}414 415define <4 x double> @vp_nearbyint_v4f64(<4 x double> %va, <4 x i1> %m, i32 zeroext %evl) {416; RV32-LABEL: vp_nearbyint_v4f64:417; RV32: # %bb.0:418; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma419; RV32-NEXT: vmv1r.v v10, v0420; RV32-NEXT: lui a0, %hi(.LCPI18_0)421; RV32-NEXT: fld fa5, %lo(.LCPI18_0)(a0)422; RV32-NEXT: vfabs.v v12, v8, v0.t423; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, mu424; RV32-NEXT: vmflt.vf v10, v12, fa5, v0.t425; RV32-NEXT: frflags a0426; RV32-NEXT: vmv1r.v v0, v10427; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, ma428; RV32-NEXT: vfcvt.x.f.v v12, v8, v0.t429; RV32-NEXT: vfcvt.f.x.v v12, v12, v0.t430; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, mu431; RV32-NEXT: vfsgnj.vv v8, v12, v8, v0.t432; RV32-NEXT: fsflags a0433; RV32-NEXT: ret434;435; RV64-LABEL: vp_nearbyint_v4f64:436; RV64: # %bb.0:437; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma438; RV64-NEXT: vmv1r.v v10, v0439; RV64-NEXT: vfabs.v v12, v8, v0.t440; RV64-NEXT: li a0, 1075441; RV64-NEXT: slli a0, a0, 52442; RV64-NEXT: fmv.d.x fa5, a0443; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, mu444; RV64-NEXT: vmflt.vf v10, v12, fa5, v0.t445; RV64-NEXT: frflags a0446; RV64-NEXT: vmv1r.v v0, v10447; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, ma448; RV64-NEXT: vfcvt.x.f.v v12, v8, v0.t449; RV64-NEXT: vfcvt.f.x.v v12, v12, v0.t450; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, mu451; RV64-NEXT: vfsgnj.vv v8, v12, v8, v0.t452; RV64-NEXT: fsflags a0453; RV64-NEXT: ret454 %v = call <4 x double> @llvm.vp.nearbyint.v4f64(<4 x double> %va, <4 x i1> %m, i32 %evl)455 ret <4 x double> %v456}457 458define <4 x double> @vp_nearbyint_v4f64_unmasked(<4 x double> %va, i32 zeroext %evl) {459; RV32-LABEL: vp_nearbyint_v4f64_unmasked:460; RV32: # %bb.0:461; RV32-NEXT: lui a1, %hi(.LCPI19_0)462; RV32-NEXT: fld fa5, %lo(.LCPI19_0)(a1)463; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma464; RV32-NEXT: vfabs.v v10, v8465; RV32-NEXT: vmflt.vf v0, v10, fa5466; RV32-NEXT: frflags a0467; RV32-NEXT: vfcvt.x.f.v v10, v8, v0.t468; RV32-NEXT: vfcvt.f.x.v v10, v10, v0.t469; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, mu470; RV32-NEXT: vfsgnj.vv v8, v10, v8, v0.t471; RV32-NEXT: fsflags a0472; RV32-NEXT: ret473;474; RV64-LABEL: vp_nearbyint_v4f64_unmasked:475; RV64: # %bb.0:476; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma477; RV64-NEXT: vfabs.v v10, v8478; RV64-NEXT: li a0, 1075479; RV64-NEXT: slli a0, a0, 52480; RV64-NEXT: fmv.d.x fa5, a0481; RV64-NEXT: vmflt.vf v0, v10, fa5482; RV64-NEXT: frflags a0483; RV64-NEXT: vfcvt.x.f.v v10, v8, v0.t484; RV64-NEXT: vfcvt.f.x.v v10, v10, v0.t485; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, mu486; RV64-NEXT: vfsgnj.vv v8, v10, v8, v0.t487; RV64-NEXT: fsflags a0488; RV64-NEXT: ret489 %v = call <4 x double> @llvm.vp.nearbyint.v4f64(<4 x double> %va, <4 x i1> splat (i1 true), i32 %evl)490 ret <4 x double> %v491}492 493define <8 x double> @vp_nearbyint_v8f64(<8 x double> %va, <8 x i1> %m, i32 zeroext %evl) {494; RV32-LABEL: vp_nearbyint_v8f64:495; RV32: # %bb.0:496; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma497; RV32-NEXT: vmv1r.v v12, v0498; RV32-NEXT: lui a0, %hi(.LCPI20_0)499; RV32-NEXT: fld fa5, %lo(.LCPI20_0)(a0)500; RV32-NEXT: vfabs.v v16, v8, v0.t501; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu502; RV32-NEXT: vmflt.vf v12, v16, fa5, v0.t503; RV32-NEXT: frflags a0504; RV32-NEXT: vmv1r.v v0, v12505; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, ma506; RV32-NEXT: vfcvt.x.f.v v16, v8, v0.t507; RV32-NEXT: vfcvt.f.x.v v16, v16, v0.t508; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu509; RV32-NEXT: vfsgnj.vv v8, v16, v8, v0.t510; RV32-NEXT: fsflags a0511; RV32-NEXT: ret512;513; RV64-LABEL: vp_nearbyint_v8f64:514; RV64: # %bb.0:515; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma516; RV64-NEXT: vmv1r.v v12, v0517; RV64-NEXT: vfabs.v v16, v8, v0.t518; RV64-NEXT: li a0, 1075519; RV64-NEXT: slli a0, a0, 52520; RV64-NEXT: fmv.d.x fa5, a0521; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, mu522; RV64-NEXT: vmflt.vf v12, v16, fa5, v0.t523; RV64-NEXT: frflags a0524; RV64-NEXT: vmv1r.v v0, v12525; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, ma526; RV64-NEXT: vfcvt.x.f.v v16, v8, v0.t527; RV64-NEXT: vfcvt.f.x.v v16, v16, v0.t528; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, mu529; RV64-NEXT: vfsgnj.vv v8, v16, v8, v0.t530; RV64-NEXT: fsflags a0531; RV64-NEXT: ret532 %v = call <8 x double> @llvm.vp.nearbyint.v8f64(<8 x double> %va, <8 x i1> %m, i32 %evl)533 ret <8 x double> %v534}535 536define <8 x double> @vp_nearbyint_v8f64_unmasked(<8 x double> %va, i32 zeroext %evl) {537; RV32-LABEL: vp_nearbyint_v8f64_unmasked:538; RV32: # %bb.0:539; RV32-NEXT: lui a1, %hi(.LCPI21_0)540; RV32-NEXT: fld fa5, %lo(.LCPI21_0)(a1)541; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma542; RV32-NEXT: vfabs.v v12, v8543; RV32-NEXT: vmflt.vf v0, v12, fa5544; RV32-NEXT: frflags a0545; RV32-NEXT: vfcvt.x.f.v v12, v8, v0.t546; RV32-NEXT: vfcvt.f.x.v v12, v12, v0.t547; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu548; RV32-NEXT: vfsgnj.vv v8, v12, v8, v0.t549; RV32-NEXT: fsflags a0550; RV32-NEXT: ret551;552; RV64-LABEL: vp_nearbyint_v8f64_unmasked:553; RV64: # %bb.0:554; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma555; RV64-NEXT: vfabs.v v12, v8556; RV64-NEXT: li a0, 1075557; RV64-NEXT: slli a0, a0, 52558; RV64-NEXT: fmv.d.x fa5, a0559; RV64-NEXT: vmflt.vf v0, v12, fa5560; RV64-NEXT: frflags a0561; RV64-NEXT: vfcvt.x.f.v v12, v8, v0.t562; RV64-NEXT: vfcvt.f.x.v v12, v12, v0.t563; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, mu564; RV64-NEXT: vfsgnj.vv v8, v12, v8, v0.t565; RV64-NEXT: fsflags a0566; RV64-NEXT: ret567 %v = call <8 x double> @llvm.vp.nearbyint.v8f64(<8 x double> %va, <8 x i1> splat (i1 true), i32 %evl)568 ret <8 x double> %v569}570 571define <15 x double> @vp_nearbyint_v15f64(<15 x double> %va, <15 x i1> %m, i32 zeroext %evl) {572; RV32-LABEL: vp_nearbyint_v15f64:573; RV32: # %bb.0:574; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma575; RV32-NEXT: vmv1r.v v16, v0576; RV32-NEXT: lui a0, %hi(.LCPI22_0)577; RV32-NEXT: fld fa5, %lo(.LCPI22_0)(a0)578; RV32-NEXT: vfabs.v v24, v8, v0.t579; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu580; RV32-NEXT: vmflt.vf v16, v24, fa5, v0.t581; RV32-NEXT: frflags a0582; RV32-NEXT: vmv1r.v v0, v16583; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma584; RV32-NEXT: vfcvt.x.f.v v24, v8, v0.t585; RV32-NEXT: vfcvt.f.x.v v24, v24, v0.t586; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu587; RV32-NEXT: vfsgnj.vv v8, v24, v8, v0.t588; RV32-NEXT: fsflags a0589; RV32-NEXT: ret590;591; RV64-LABEL: vp_nearbyint_v15f64:592; RV64: # %bb.0:593; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma594; RV64-NEXT: vmv1r.v v16, v0595; RV64-NEXT: vfabs.v v24, v8, v0.t596; RV64-NEXT: li a0, 1075597; RV64-NEXT: slli a0, a0, 52598; RV64-NEXT: fmv.d.x fa5, a0599; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu600; RV64-NEXT: vmflt.vf v16, v24, fa5, v0.t601; RV64-NEXT: frflags a0602; RV64-NEXT: vmv1r.v v0, v16603; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma604; RV64-NEXT: vfcvt.x.f.v v24, v8, v0.t605; RV64-NEXT: vfcvt.f.x.v v24, v24, v0.t606; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu607; RV64-NEXT: vfsgnj.vv v8, v24, v8, v0.t608; RV64-NEXT: fsflags a0609; RV64-NEXT: ret610 %v = call <15 x double> @llvm.vp.nearbyint.v15f64(<15 x double> %va, <15 x i1> %m, i32 %evl)611 ret <15 x double> %v612}613 614define <15 x double> @vp_nearbyint_v15f64_unmasked(<15 x double> %va, i32 zeroext %evl) {615; RV32-LABEL: vp_nearbyint_v15f64_unmasked:616; RV32: # %bb.0:617; RV32-NEXT: lui a1, %hi(.LCPI23_0)618; RV32-NEXT: fld fa5, %lo(.LCPI23_0)(a1)619; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma620; RV32-NEXT: vfabs.v v16, v8621; RV32-NEXT: vmflt.vf v0, v16, fa5622; RV32-NEXT: frflags a0623; RV32-NEXT: vfcvt.x.f.v v16, v8, v0.t624; RV32-NEXT: vfcvt.f.x.v v16, v16, v0.t625; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu626; RV32-NEXT: vfsgnj.vv v8, v16, v8, v0.t627; RV32-NEXT: fsflags a0628; RV32-NEXT: ret629;630; RV64-LABEL: vp_nearbyint_v15f64_unmasked:631; RV64: # %bb.0:632; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma633; RV64-NEXT: vfabs.v v16, v8634; RV64-NEXT: li a0, 1075635; RV64-NEXT: slli a0, a0, 52636; RV64-NEXT: fmv.d.x fa5, a0637; RV64-NEXT: vmflt.vf v0, v16, fa5638; RV64-NEXT: frflags a0639; RV64-NEXT: vfcvt.x.f.v v16, v8, v0.t640; RV64-NEXT: vfcvt.f.x.v v16, v16, v0.t641; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu642; RV64-NEXT: vfsgnj.vv v8, v16, v8, v0.t643; RV64-NEXT: fsflags a0644; RV64-NEXT: ret645 %v = call <15 x double> @llvm.vp.nearbyint.v15f64(<15 x double> %va, <15 x i1> splat (i1 true), i32 %evl)646 ret <15 x double> %v647}648 649define <16 x double> @vp_nearbyint_v16f64(<16 x double> %va, <16 x i1> %m, i32 zeroext %evl) {650; RV32-LABEL: vp_nearbyint_v16f64:651; RV32: # %bb.0:652; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma653; RV32-NEXT: vmv1r.v v16, v0654; RV32-NEXT: lui a0, %hi(.LCPI24_0)655; RV32-NEXT: fld fa5, %lo(.LCPI24_0)(a0)656; RV32-NEXT: vfabs.v v24, v8, v0.t657; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu658; RV32-NEXT: vmflt.vf v16, v24, fa5, v0.t659; RV32-NEXT: frflags a0660; RV32-NEXT: vmv1r.v v0, v16661; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma662; RV32-NEXT: vfcvt.x.f.v v24, v8, v0.t663; RV32-NEXT: vfcvt.f.x.v v24, v24, v0.t664; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu665; RV32-NEXT: vfsgnj.vv v8, v24, v8, v0.t666; RV32-NEXT: fsflags a0667; RV32-NEXT: ret668;669; RV64-LABEL: vp_nearbyint_v16f64:670; RV64: # %bb.0:671; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma672; RV64-NEXT: vmv1r.v v16, v0673; RV64-NEXT: vfabs.v v24, v8, v0.t674; RV64-NEXT: li a0, 1075675; RV64-NEXT: slli a0, a0, 52676; RV64-NEXT: fmv.d.x fa5, a0677; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu678; RV64-NEXT: vmflt.vf v16, v24, fa5, v0.t679; RV64-NEXT: frflags a0680; RV64-NEXT: vmv1r.v v0, v16681; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma682; RV64-NEXT: vfcvt.x.f.v v24, v8, v0.t683; RV64-NEXT: vfcvt.f.x.v v24, v24, v0.t684; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu685; RV64-NEXT: vfsgnj.vv v8, v24, v8, v0.t686; RV64-NEXT: fsflags a0687; RV64-NEXT: ret688 %v = call <16 x double> @llvm.vp.nearbyint.v16f64(<16 x double> %va, <16 x i1> %m, i32 %evl)689 ret <16 x double> %v690}691 692define <16 x double> @vp_nearbyint_v16f64_unmasked(<16 x double> %va, i32 zeroext %evl) {693; RV32-LABEL: vp_nearbyint_v16f64_unmasked:694; RV32: # %bb.0:695; RV32-NEXT: lui a1, %hi(.LCPI25_0)696; RV32-NEXT: fld fa5, %lo(.LCPI25_0)(a1)697; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma698; RV32-NEXT: vfabs.v v16, v8699; RV32-NEXT: vmflt.vf v0, v16, fa5700; RV32-NEXT: frflags a0701; RV32-NEXT: vfcvt.x.f.v v16, v8, v0.t702; RV32-NEXT: vfcvt.f.x.v v16, v16, v0.t703; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu704; RV32-NEXT: vfsgnj.vv v8, v16, v8, v0.t705; RV32-NEXT: fsflags a0706; RV32-NEXT: ret707;708; RV64-LABEL: vp_nearbyint_v16f64_unmasked:709; RV64: # %bb.0:710; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma711; RV64-NEXT: vfabs.v v16, v8712; RV64-NEXT: li a0, 1075713; RV64-NEXT: slli a0, a0, 52714; RV64-NEXT: fmv.d.x fa5, a0715; RV64-NEXT: vmflt.vf v0, v16, fa5716; RV64-NEXT: frflags a0717; RV64-NEXT: vfcvt.x.f.v v16, v8, v0.t718; RV64-NEXT: vfcvt.f.x.v v16, v16, v0.t719; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu720; RV64-NEXT: vfsgnj.vv v8, v16, v8, v0.t721; RV64-NEXT: fsflags a0722; RV64-NEXT: ret723 %v = call <16 x double> @llvm.vp.nearbyint.v16f64(<16 x double> %va, <16 x i1> splat (i1 true), i32 %evl)724 ret <16 x double> %v725}726 727define <32 x double> @vp_nearbyint_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroext %evl) {728; RV32-LABEL: vp_nearbyint_v32f64:729; RV32: # %bb.0:730; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma731; RV32-NEXT: vmv1r.v v6, v0732; RV32-NEXT: li a2, 16733; RV32-NEXT: vslidedown.vi v7, v0, 2734; RV32-NEXT: mv a1, a0735; RV32-NEXT: bltu a0, a2, .LBB26_2736; RV32-NEXT: # %bb.1:737; RV32-NEXT: li a1, 16738; RV32-NEXT: .LBB26_2:739; RV32-NEXT: vmv1r.v v0, v6740; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma741; RV32-NEXT: vfabs.v v24, v8, v0.t742; RV32-NEXT: lui a1, %hi(.LCPI26_0)743; RV32-NEXT: fld fa5, %lo(.LCPI26_0)(a1)744; RV32-NEXT: addi a1, a0, -16745; RV32-NEXT: sltu a0, a0, a1746; RV32-NEXT: addi a0, a0, -1747; RV32-NEXT: and a0, a0, a1748; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu749; RV32-NEXT: vmflt.vf v6, v24, fa5, v0.t750; RV32-NEXT: frflags a1751; RV32-NEXT: vmv1r.v v0, v6752; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma753; RV32-NEXT: vfcvt.x.f.v v24, v8, v0.t754; RV32-NEXT: vfcvt.f.x.v v24, v24, v0.t755; RV32-NEXT: fsflags a1756; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu757; RV32-NEXT: vfsgnj.vv v8, v24, v8, v0.t758; RV32-NEXT: vmv1r.v v0, v7759; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma760; RV32-NEXT: vfabs.v v24, v16, v0.t761; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu762; RV32-NEXT: vmflt.vf v7, v24, fa5, v0.t763; RV32-NEXT: frflags a0764; RV32-NEXT: vmv1r.v v0, v7765; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma766; RV32-NEXT: vfcvt.x.f.v v24, v16, v0.t767; RV32-NEXT: vfcvt.f.x.v v24, v24, v0.t768; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu769; RV32-NEXT: vfsgnj.vv v16, v24, v16, v0.t770; RV32-NEXT: fsflags a0771; RV32-NEXT: ret772;773; RV64-LABEL: vp_nearbyint_v32f64:774; RV64: # %bb.0:775; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma776; RV64-NEXT: vmv1r.v v6, v0777; RV64-NEXT: li a2, 16778; RV64-NEXT: vslidedown.vi v7, v0, 2779; RV64-NEXT: mv a1, a0780; RV64-NEXT: bltu a0, a2, .LBB26_2781; RV64-NEXT: # %bb.1:782; RV64-NEXT: li a1, 16783; RV64-NEXT: .LBB26_2:784; RV64-NEXT: vmv1r.v v0, v6785; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma786; RV64-NEXT: vfabs.v v24, v8, v0.t787; RV64-NEXT: li a1, 1075788; RV64-NEXT: slli a1, a1, 52789; RV64-NEXT: fmv.d.x fa5, a1790; RV64-NEXT: addi a1, a0, -16791; RV64-NEXT: sltu a0, a0, a1792; RV64-NEXT: addi a0, a0, -1793; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu794; RV64-NEXT: vmflt.vf v6, v24, fa5, v0.t795; RV64-NEXT: and a0, a0, a1796; RV64-NEXT: frflags a1797; RV64-NEXT: vmv1r.v v0, v6798; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma799; RV64-NEXT: vfcvt.x.f.v v24, v8, v0.t800; RV64-NEXT: vfcvt.f.x.v v24, v24, v0.t801; RV64-NEXT: fsflags a1802; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu803; RV64-NEXT: vfsgnj.vv v8, v24, v8, v0.t804; RV64-NEXT: vmv1r.v v0, v7805; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma806; RV64-NEXT: vfabs.v v24, v16, v0.t807; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu808; RV64-NEXT: vmflt.vf v7, v24, fa5, v0.t809; RV64-NEXT: frflags a0810; RV64-NEXT: vmv1r.v v0, v7811; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma812; RV64-NEXT: vfcvt.x.f.v v24, v16, v0.t813; RV64-NEXT: vfcvt.f.x.v v24, v24, v0.t814; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu815; RV64-NEXT: vfsgnj.vv v16, v24, v16, v0.t816; RV64-NEXT: fsflags a0817; RV64-NEXT: ret818 %v = call <32 x double> @llvm.vp.nearbyint.v32f64(<32 x double> %va, <32 x i1> %m, i32 %evl)819 ret <32 x double> %v820}821 822define <32 x double> @vp_nearbyint_v32f64_unmasked(<32 x double> %va, i32 zeroext %evl) {823; RV32-LABEL: vp_nearbyint_v32f64_unmasked:824; RV32: # %bb.0:825; RV32-NEXT: li a2, 16826; RV32-NEXT: mv a1, a0827; RV32-NEXT: bltu a0, a2, .LBB27_2828; RV32-NEXT: # %bb.1:829; RV32-NEXT: li a1, 16830; RV32-NEXT: .LBB27_2:831; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma832; RV32-NEXT: vfabs.v v24, v8833; RV32-NEXT: lui a2, %hi(.LCPI27_0)834; RV32-NEXT: fld fa5, %lo(.LCPI27_0)(a2)835; RV32-NEXT: addi a2, a0, -16836; RV32-NEXT: sltu a0, a0, a2837; RV32-NEXT: addi a0, a0, -1838; RV32-NEXT: and a0, a0, a2839; RV32-NEXT: frflags a2840; RV32-NEXT: vmflt.vf v0, v24, fa5841; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma842; RV32-NEXT: vfabs.v v24, v16843; RV32-NEXT: vmflt.vf v7, v24, fa5844; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma845; RV32-NEXT: vfcvt.x.f.v v24, v8, v0.t846; RV32-NEXT: vfcvt.f.x.v v24, v24, v0.t847; RV32-NEXT: fsflags a2848; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu849; RV32-NEXT: vfsgnj.vv v8, v24, v8, v0.t850; RV32-NEXT: frflags a1851; RV32-NEXT: vmv1r.v v0, v7852; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma853; RV32-NEXT: vfcvt.x.f.v v24, v16, v0.t854; RV32-NEXT: vfcvt.f.x.v v24, v24, v0.t855; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu856; RV32-NEXT: vfsgnj.vv v16, v24, v16, v0.t857; RV32-NEXT: fsflags a1858; RV32-NEXT: ret859;860; RV64-LABEL: vp_nearbyint_v32f64_unmasked:861; RV64: # %bb.0:862; RV64-NEXT: li a2, 16863; RV64-NEXT: mv a1, a0864; RV64-NEXT: bltu a0, a2, .LBB27_2865; RV64-NEXT: # %bb.1:866; RV64-NEXT: li a1, 16867; RV64-NEXT: .LBB27_2:868; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma869; RV64-NEXT: vfabs.v v24, v8870; RV64-NEXT: li a2, 1075871; RV64-NEXT: slli a2, a2, 52872; RV64-NEXT: fmv.d.x fa5, a2873; RV64-NEXT: addi a2, a0, -16874; RV64-NEXT: sltu a0, a0, a2875; RV64-NEXT: addi a0, a0, -1876; RV64-NEXT: and a0, a0, a2877; RV64-NEXT: frflags a2878; RV64-NEXT: vmflt.vf v0, v24, fa5879; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma880; RV64-NEXT: vfabs.v v24, v16881; RV64-NEXT: vmflt.vf v7, v24, fa5882; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma883; RV64-NEXT: vfcvt.x.f.v v24, v8, v0.t884; RV64-NEXT: vfcvt.f.x.v v24, v24, v0.t885; RV64-NEXT: fsflags a2886; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu887; RV64-NEXT: vfsgnj.vv v8, v24, v8, v0.t888; RV64-NEXT: frflags a1889; RV64-NEXT: vmv1r.v v0, v7890; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma891; RV64-NEXT: vfcvt.x.f.v v24, v16, v0.t892; RV64-NEXT: vfcvt.f.x.v v24, v24, v0.t893; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu894; RV64-NEXT: vfsgnj.vv v16, v24, v16, v0.t895; RV64-NEXT: fsflags a1896; RV64-NEXT: ret897 %v = call <32 x double> @llvm.vp.nearbyint.v32f64(<32 x double> %va, <32 x i1> splat (i1 true), i32 %evl)898 ret <32 x double> %v899}900