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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK3; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK4 5define void @vls3i8(ptr align 8 %array) {6; CHECK-LABEL: vls3i8:7; CHECK: # %bb.0: # %entry8; CHECK-NEXT: vsetivli zero, 3, e8, mf4, ta, ma9; CHECK-NEXT: vle8.v v8, (a0)10; CHECK-NEXT: vadd.vv v8, v8, v811; CHECK-NEXT: vse8.v v8, (a0)12; CHECK-NEXT: ret13entry:14 %arr = getelementptr inbounds <3 x i8>, ptr %array, i64 015 %1 = load <3 x i8>, ptr %array, align 116 %2 = add<3 x i8> %1, %117 store <3 x i8> %2, ptr %array, align 118 ret void19}20 21define void @vls3(ptr align 8 %array) {22; CHECK-LABEL: vls3:23; CHECK: # %bb.0: # %entry24; CHECK-NEXT: vsetivli zero, 3, e32, m1, ta, ma25; CHECK-NEXT: vle32.v v8, (a0)26; CHECK-NEXT: vadd.vv v8, v8, v827; CHECK-NEXT: vse32.v v8, (a0)28; CHECK-NEXT: ret29entry:30 %arr = getelementptr inbounds <3 x i32>, ptr %array, i64 031 %1 = load <3 x i32>, ptr %array, align 432 %2 = add<3 x i32> %1, %133 store <3 x i32> %2, ptr %array, align 434 ret void35}36 37define void @vls5(ptr align 8 %array) {38; CHECK-LABEL: vls5:39; CHECK: # %bb.0: # %entry40; CHECK-NEXT: vsetivli zero, 5, e32, m2, ta, ma41; CHECK-NEXT: vle32.v v8, (a0)42; CHECK-NEXT: vadd.vv v8, v8, v843; CHECK-NEXT: vse32.v v8, (a0)44; CHECK-NEXT: ret45entry:46 %arr = getelementptr inbounds <5 x i32>, ptr %array, i64 047 %1 = load <5 x i32>, ptr %array, align 448 %2 = add<5 x i32> %1, %149 store <5 x i32> %2, ptr %array, align 450 ret void51}52 53define void @vls6(ptr align 8 %array) {54; CHECK-LABEL: vls6:55; CHECK: # %bb.0: # %entry56; CHECK-NEXT: vsetivli zero, 6, e32, m2, ta, ma57; CHECK-NEXT: vle32.v v8, (a0)58; CHECK-NEXT: vadd.vv v8, v8, v859; CHECK-NEXT: vse32.v v8, (a0)60; CHECK-NEXT: ret61entry:62 %arr = getelementptr inbounds <6 x i32>, ptr %array, i64 063 %1 = load <6 x i32>, ptr %array, align 464 %2 = add<6 x i32> %1, %165 store <6 x i32> %2, ptr %array, align 466 ret void67}68 69define void @vls7(ptr align 8 %array) {70; CHECK-LABEL: vls7:71; CHECK: # %bb.0: # %entry72; CHECK-NEXT: vsetivli zero, 7, e32, m2, ta, ma73; CHECK-NEXT: vle32.v v8, (a0)74; CHECK-NEXT: vadd.vv v8, v8, v875; CHECK-NEXT: vse32.v v8, (a0)76; CHECK-NEXT: ret77entry:78 %arr = getelementptr inbounds <7 x i32>, ptr %array, i64 079 %1 = load <7 x i32>, ptr %array, align 480 %2 = add<7 x i32> %1, %181 store <7 x i32> %2, ptr %array, align 482 ret void83}84 85 86define void @vls9(ptr align 8 %array) {87; CHECK-LABEL: vls9:88; CHECK: # %bb.0: # %entry89; CHECK-NEXT: vsetivli zero, 9, e32, m4, ta, ma90; CHECK-NEXT: vle32.v v8, (a0)91; CHECK-NEXT: vadd.vv v8, v8, v892; CHECK-NEXT: vse32.v v8, (a0)93; CHECK-NEXT: ret94entry:95 %arr = getelementptr inbounds <9 x i32>, ptr %array, i64 096 %1 = load <9 x i32>, ptr %array, align 497 %2 = add<9 x i32> %1, %198 store <9 x i32> %2, ptr %array, align 499 ret void100}101 102 103define void @vls10(ptr align 8 %array) {104; CHECK-LABEL: vls10:105; CHECK: # %bb.0: # %entry106; CHECK-NEXT: vsetivli zero, 10, e32, m4, ta, ma107; CHECK-NEXT: vle32.v v8, (a0)108; CHECK-NEXT: vadd.vv v8, v8, v8109; CHECK-NEXT: vse32.v v8, (a0)110; CHECK-NEXT: ret111entry:112 %arr = getelementptr inbounds <10 x i32>, ptr %array, i64 0113 %1 = load <10 x i32>, ptr %array, align 4114 %2 = add<10 x i32> %1, %1115 store <10 x i32> %2, ptr %array, align 4116 ret void117}118 119define void @vls11(ptr align 8 %array) {120; CHECK-LABEL: vls11:121; CHECK: # %bb.0: # %entry122; CHECK-NEXT: vsetivli zero, 11, e32, m4, ta, ma123; CHECK-NEXT: vle32.v v8, (a0)124; CHECK-NEXT: vadd.vv v8, v8, v8125; CHECK-NEXT: vse32.v v8, (a0)126; CHECK-NEXT: ret127entry:128 %arr = getelementptr inbounds <11 x i32>, ptr %array, i64 0129 %1 = load <11 x i32>, ptr %array, align 4130 %2 = add<11 x i32> %1, %1131 store <11 x i32> %2, ptr %array, align 4132 ret void133}134