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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s4; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck %s6 7define half @vpreduce_fadd_v2f16(half %s, <2 x half> %v, <2 x i1> %m, i32 zeroext %evl) {8; CHECK-LABEL: vpreduce_fadd_v2f16:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma11; CHECK-NEXT: vfmv.s.f v9, fa012; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma13; CHECK-NEXT: vfredusum.vs v9, v8, v9, v0.t14; CHECK-NEXT: vfmv.f.s fa0, v915; CHECK-NEXT: ret16 %r = call reassoc half @llvm.vp.reduce.fadd.v2f16(half %s, <2 x half> %v, <2 x i1> %m, i32 %evl)17 ret half %r18}19 20define half @vpreduce_ord_fadd_v2f16(half %s, <2 x half> %v, <2 x i1> %m, i32 zeroext %evl) {21; CHECK-LABEL: vpreduce_ord_fadd_v2f16:22; CHECK: # %bb.0:23; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma24; CHECK-NEXT: vfmv.s.f v9, fa025; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma26; CHECK-NEXT: vfredosum.vs v9, v8, v9, v0.t27; CHECK-NEXT: vfmv.f.s fa0, v928; CHECK-NEXT: ret29 %r = call half @llvm.vp.reduce.fadd.v2f16(half %s, <2 x half> %v, <2 x i1> %m, i32 %evl)30 ret half %r31}32 33define half @vpreduce_fadd_v4f16(half %s, <4 x half> %v, <4 x i1> %m, i32 zeroext %evl) {34; CHECK-LABEL: vpreduce_fadd_v4f16:35; CHECK: # %bb.0:36; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma37; CHECK-NEXT: vfmv.s.f v9, fa038; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma39; CHECK-NEXT: vfredusum.vs v9, v8, v9, v0.t40; CHECK-NEXT: vfmv.f.s fa0, v941; CHECK-NEXT: ret42 %r = call reassoc half @llvm.vp.reduce.fadd.v4f16(half %s, <4 x half> %v, <4 x i1> %m, i32 %evl)43 ret half %r44}45 46define half @vpreduce_ord_fadd_v4f16(half %s, <4 x half> %v, <4 x i1> %m, i32 zeroext %evl) {47; CHECK-LABEL: vpreduce_ord_fadd_v4f16:48; CHECK: # %bb.0:49; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma50; CHECK-NEXT: vfmv.s.f v9, fa051; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma52; CHECK-NEXT: vfredosum.vs v9, v8, v9, v0.t53; CHECK-NEXT: vfmv.f.s fa0, v954; CHECK-NEXT: ret55 %r = call half @llvm.vp.reduce.fadd.v4f16(half %s, <4 x half> %v, <4 x i1> %m, i32 %evl)56 ret half %r57}58 59define float @vpreduce_fadd_v2f32(float %s, <2 x float> %v, <2 x i1> %m, i32 zeroext %evl) {60; CHECK-LABEL: vpreduce_fadd_v2f32:61; CHECK: # %bb.0:62; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma63; CHECK-NEXT: vfmv.s.f v9, fa064; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma65; CHECK-NEXT: vfredusum.vs v9, v8, v9, v0.t66; CHECK-NEXT: vfmv.f.s fa0, v967; CHECK-NEXT: ret68 %r = call reassoc float @llvm.vp.reduce.fadd.v2f32(float %s, <2 x float> %v, <2 x i1> %m, i32 %evl)69 ret float %r70}71 72define float @vpreduce_ord_fadd_v2f32(float %s, <2 x float> %v, <2 x i1> %m, i32 zeroext %evl) {73; CHECK-LABEL: vpreduce_ord_fadd_v2f32:74; CHECK: # %bb.0:75; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma76; CHECK-NEXT: vfmv.s.f v9, fa077; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma78; CHECK-NEXT: vfredosum.vs v9, v8, v9, v0.t79; CHECK-NEXT: vfmv.f.s fa0, v980; CHECK-NEXT: ret81 %r = call float @llvm.vp.reduce.fadd.v2f32(float %s, <2 x float> %v, <2 x i1> %m, i32 %evl)82 ret float %r83}84 85define float @vpreduce_fadd_v4f32(float %s, <4 x float> %v, <4 x i1> %m, i32 zeroext %evl) {86; CHECK-LABEL: vpreduce_fadd_v4f32:87; CHECK: # %bb.0:88; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma89; CHECK-NEXT: vfmv.s.f v9, fa090; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma91; CHECK-NEXT: vfredusum.vs v9, v8, v9, v0.t92; CHECK-NEXT: vfmv.f.s fa0, v993; CHECK-NEXT: ret94 %r = call reassoc float @llvm.vp.reduce.fadd.v4f32(float %s, <4 x float> %v, <4 x i1> %m, i32 %evl)95 ret float %r96}97 98define float @vpreduce_ord_fadd_v4f32(float %s, <4 x float> %v, <4 x i1> %m, i32 zeroext %evl) {99; CHECK-LABEL: vpreduce_ord_fadd_v4f32:100; CHECK: # %bb.0:101; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma102; CHECK-NEXT: vfmv.s.f v9, fa0103; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma104; CHECK-NEXT: vfredosum.vs v9, v8, v9, v0.t105; CHECK-NEXT: vfmv.f.s fa0, v9106; CHECK-NEXT: ret107 %r = call float @llvm.vp.reduce.fadd.v4f32(float %s, <4 x float> %v, <4 x i1> %m, i32 %evl)108 ret float %r109}110 111define float @vpreduce_fadd_v64f32(float %s, <64 x float> %v, <64 x i1> %m, i32 zeroext %evl) {112; CHECK-LABEL: vpreduce_fadd_v64f32:113; CHECK: # %bb.0:114; CHECK-NEXT: li a2, 32115; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma116; CHECK-NEXT: vslidedown.vi v24, v0, 4117; CHECK-NEXT: mv a1, a0118; CHECK-NEXT: bltu a0, a2, .LBB8_2119; CHECK-NEXT: # %bb.1:120; CHECK-NEXT: li a1, 32121; CHECK-NEXT: .LBB8_2:122; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma123; CHECK-NEXT: vfmv.s.f v25, fa0124; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma125; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t126; CHECK-NEXT: addi a1, a0, -32127; CHECK-NEXT: sltu a0, a0, a1128; CHECK-NEXT: addi a0, a0, -1129; CHECK-NEXT: and a0, a0, a1130; CHECK-NEXT: vmv1r.v v0, v24131; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma132; CHECK-NEXT: vfredusum.vs v25, v16, v25, v0.t133; CHECK-NEXT: vfmv.f.s fa0, v25134; CHECK-NEXT: ret135 %r = call reassoc float @llvm.vp.reduce.fadd.v64f32(float %s, <64 x float> %v, <64 x i1> %m, i32 %evl)136 ret float %r137}138 139define float @vpreduce_ord_fadd_v64f32(float %s, <64 x float> %v, <64 x i1> %m, i32 zeroext %evl) {140; CHECK-LABEL: vpreduce_ord_fadd_v64f32:141; CHECK: # %bb.0:142; CHECK-NEXT: li a2, 32143; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma144; CHECK-NEXT: vslidedown.vi v24, v0, 4145; CHECK-NEXT: mv a1, a0146; CHECK-NEXT: bltu a0, a2, .LBB9_2147; CHECK-NEXT: # %bb.1:148; CHECK-NEXT: li a1, 32149; CHECK-NEXT: .LBB9_2:150; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma151; CHECK-NEXT: vfmv.s.f v25, fa0152; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma153; CHECK-NEXT: vfredosum.vs v25, v8, v25, v0.t154; CHECK-NEXT: addi a1, a0, -32155; CHECK-NEXT: sltu a0, a0, a1156; CHECK-NEXT: addi a0, a0, -1157; CHECK-NEXT: and a0, a0, a1158; CHECK-NEXT: vmv1r.v v0, v24159; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma160; CHECK-NEXT: vfredosum.vs v25, v16, v25, v0.t161; CHECK-NEXT: vfmv.f.s fa0, v25162; CHECK-NEXT: ret163 %r = call float @llvm.vp.reduce.fadd.v64f32(float %s, <64 x float> %v, <64 x i1> %m, i32 %evl)164 ret float %r165}166 167define double @vpreduce_fadd_v2f64(double %s, <2 x double> %v, <2 x i1> %m, i32 zeroext %evl) {168; CHECK-LABEL: vpreduce_fadd_v2f64:169; CHECK: # %bb.0:170; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma171; CHECK-NEXT: vfmv.s.f v9, fa0172; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma173; CHECK-NEXT: vfredusum.vs v9, v8, v9, v0.t174; CHECK-NEXT: vfmv.f.s fa0, v9175; CHECK-NEXT: ret176 %r = call reassoc double @llvm.vp.reduce.fadd.v2f64(double %s, <2 x double> %v, <2 x i1> %m, i32 %evl)177 ret double %r178}179 180define double @vpreduce_ord_fadd_v2f64(double %s, <2 x double> %v, <2 x i1> %m, i32 zeroext %evl) {181; CHECK-LABEL: vpreduce_ord_fadd_v2f64:182; CHECK: # %bb.0:183; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma184; CHECK-NEXT: vfmv.s.f v9, fa0185; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma186; CHECK-NEXT: vfredosum.vs v9, v8, v9, v0.t187; CHECK-NEXT: vfmv.f.s fa0, v9188; CHECK-NEXT: ret189 %r = call double @llvm.vp.reduce.fadd.v2f64(double %s, <2 x double> %v, <2 x i1> %m, i32 %evl)190 ret double %r191}192 193define double @vpreduce_fadd_v3f64(double %s, <3 x double> %v, <3 x i1> %m, i32 zeroext %evl) {194; CHECK-LABEL: vpreduce_fadd_v3f64:195; CHECK: # %bb.0:196; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma197; CHECK-NEXT: vfmv.s.f v10, fa0198; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma199; CHECK-NEXT: vfredusum.vs v10, v8, v10, v0.t200; CHECK-NEXT: vfmv.f.s fa0, v10201; CHECK-NEXT: ret202 %r = call reassoc double @llvm.vp.reduce.fadd.v3f64(double %s, <3 x double> %v, <3 x i1> %m, i32 %evl)203 ret double %r204}205 206define double @vpreduce_ord_fadd_v3f64(double %s, <3 x double> %v, <3 x i1> %m, i32 zeroext %evl) {207; CHECK-LABEL: vpreduce_ord_fadd_v3f64:208; CHECK: # %bb.0:209; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma210; CHECK-NEXT: vfmv.s.f v10, fa0211; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma212; CHECK-NEXT: vfredosum.vs v10, v8, v10, v0.t213; CHECK-NEXT: vfmv.f.s fa0, v10214; CHECK-NEXT: ret215 %r = call double @llvm.vp.reduce.fadd.v3f64(double %s, <3 x double> %v, <3 x i1> %m, i32 %evl)216 ret double %r217}218 219define double @vpreduce_fadd_v4f64(double %s, <4 x double> %v, <4 x i1> %m, i32 zeroext %evl) {220; CHECK-LABEL: vpreduce_fadd_v4f64:221; CHECK: # %bb.0:222; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma223; CHECK-NEXT: vfmv.s.f v10, fa0224; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma225; CHECK-NEXT: vfredusum.vs v10, v8, v10, v0.t226; CHECK-NEXT: vfmv.f.s fa0, v10227; CHECK-NEXT: ret228 %r = call reassoc double @llvm.vp.reduce.fadd.v4f64(double %s, <4 x double> %v, <4 x i1> %m, i32 %evl)229 ret double %r230}231 232define double @vpreduce_ord_fadd_v4f64(double %s, <4 x double> %v, <4 x i1> %m, i32 zeroext %evl) {233; CHECK-LABEL: vpreduce_ord_fadd_v4f64:234; CHECK: # %bb.0:235; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma236; CHECK-NEXT: vfmv.s.f v10, fa0237; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma238; CHECK-NEXT: vfredosum.vs v10, v8, v10, v0.t239; CHECK-NEXT: vfmv.f.s fa0, v10240; CHECK-NEXT: ret241 %r = call double @llvm.vp.reduce.fadd.v4f64(double %s, <4 x double> %v, <4 x i1> %m, i32 %evl)242 ret double %r243}244 245define float @vpreduce_fminimum_v4f32(float %start, <4 x float> %val, <4 x i1> %m, i32 zeroext %evl) {246; CHECK-LABEL: vpreduce_fminimum_v4f32:247; CHECK: # %bb.0:248; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma249; CHECK-NEXT: vmfne.vv v9, v8, v8, v0.t250; CHECK-NEXT: feq.s a1, fa0, fa0251; CHECK-NEXT: vcpop.m a2, v9, v0.t252; CHECK-NEXT: xori a1, a1, 1253; CHECK-NEXT: or a1, a2, a1254; CHECK-NEXT: beqz a1, .LBB16_2255; CHECK-NEXT: # %bb.1:256; CHECK-NEXT: lui a0, 523264257; CHECK-NEXT: fmv.w.x fa0, a0258; CHECK-NEXT: ret259; CHECK-NEXT: .LBB16_2:260; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma261; CHECK-NEXT: vfmv.s.f v9, fa0262; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma263; CHECK-NEXT: vfredmin.vs v9, v8, v9, v0.t264; CHECK-NEXT: vfmv.f.s fa0, v9265; CHECK-NEXT: ret266 %s = call float @llvm.vp.reduce.fminimum.v4f32(float %start, <4 x float> %val, <4 x i1> %m, i32 %evl)267 ret float %s268}269 270define float @vpreduce_fmaximum_v4f32(float %start, <4 x float> %val, <4 x i1> %m, i32 zeroext %evl) {271; CHECK-LABEL: vpreduce_fmaximum_v4f32:272; CHECK: # %bb.0:273; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma274; CHECK-NEXT: vmfne.vv v9, v8, v8, v0.t275; CHECK-NEXT: feq.s a1, fa0, fa0276; CHECK-NEXT: vcpop.m a2, v9, v0.t277; CHECK-NEXT: xori a1, a1, 1278; CHECK-NEXT: or a1, a2, a1279; CHECK-NEXT: beqz a1, .LBB17_2280; CHECK-NEXT: # %bb.1:281; CHECK-NEXT: lui a0, 523264282; CHECK-NEXT: fmv.w.x fa0, a0283; CHECK-NEXT: ret284; CHECK-NEXT: .LBB17_2:285; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma286; CHECK-NEXT: vfmv.s.f v9, fa0287; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma288; CHECK-NEXT: vfredmax.vs v9, v8, v9, v0.t289; CHECK-NEXT: vfmv.f.s fa0, v9290; CHECK-NEXT: ret291 %s = call float @llvm.vp.reduce.fmaximum.v4f32(float %start, <4 x float> %val, <4 x i1> %m, i32 %evl)292 ret float %s293}294