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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,RV32 %s3; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,RV64 %s4 5define half @vreduce_fadd_v1f16(<1 x half> %v, half %s) {6; CHECK-LABEL: vreduce_fadd_v1f16:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma9; CHECK-NEXT: vfmv.f.s fa5, v810; CHECK-NEXT: fadd.h fa0, fa0, fa511; CHECK-NEXT: ret12 %red = call reassoc half @llvm.vector.reduce.fadd.v1f16(half %s, <1 x half> %v)13 ret half %red14}15 16define half @vreduce_ord_fadd_v1f16(<1 x half> %v, half %s) {17; CHECK-LABEL: vreduce_ord_fadd_v1f16:18; CHECK: # %bb.0:19; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma20; CHECK-NEXT: vfmv.s.f v9, fa021; CHECK-NEXT: vfredosum.vs v8, v8, v922; CHECK-NEXT: vfmv.f.s fa0, v823; CHECK-NEXT: ret24 %red = call half @llvm.vector.reduce.fadd.v1f16(half %s, <1 x half> %v)25 ret half %red26}27 28define half @vreduce_fadd_v2f16(ptr %x, half %s) {29; CHECK-LABEL: vreduce_fadd_v2f16:30; CHECK: # %bb.0:31; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma32; CHECK-NEXT: vle16.v v8, (a0)33; CHECK-NEXT: vfmv.s.f v9, fa034; CHECK-NEXT: vfredusum.vs v8, v8, v935; CHECK-NEXT: vfmv.f.s fa0, v836; CHECK-NEXT: ret37 %v = load <2 x half>, ptr %x38 %red = call reassoc half @llvm.vector.reduce.fadd.v2f16(half %s, <2 x half> %v)39 ret half %red40}41 42define half @vreduce_ord_fadd_v2f16(ptr %x, half %s) {43; CHECK-LABEL: vreduce_ord_fadd_v2f16:44; CHECK: # %bb.0:45; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma46; CHECK-NEXT: vle16.v v8, (a0)47; CHECK-NEXT: vfmv.s.f v9, fa048; CHECK-NEXT: vfredosum.vs v8, v8, v949; CHECK-NEXT: vfmv.f.s fa0, v850; CHECK-NEXT: ret51 %v = load <2 x half>, ptr %x52 %red = call half @llvm.vector.reduce.fadd.v2f16(half %s, <2 x half> %v)53 ret half %red54}55 56define half @vreduce_fadd_v4f16(ptr %x, half %s) {57; CHECK-LABEL: vreduce_fadd_v4f16:58; CHECK: # %bb.0:59; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma60; CHECK-NEXT: vle16.v v8, (a0)61; CHECK-NEXT: vfmv.s.f v9, fa062; CHECK-NEXT: vfredusum.vs v8, v8, v963; CHECK-NEXT: vfmv.f.s fa0, v864; CHECK-NEXT: ret65 %v = load <4 x half>, ptr %x66 %red = call reassoc half @llvm.vector.reduce.fadd.v4f16(half %s, <4 x half> %v)67 ret half %red68}69 70define half @vreduce_ord_fadd_v4f16(ptr %x, half %s) {71; CHECK-LABEL: vreduce_ord_fadd_v4f16:72; CHECK: # %bb.0:73; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma74; CHECK-NEXT: vle16.v v8, (a0)75; CHECK-NEXT: vfmv.s.f v9, fa076; CHECK-NEXT: vfredosum.vs v8, v8, v977; CHECK-NEXT: vfmv.f.s fa0, v878; CHECK-NEXT: ret79 %v = load <4 x half>, ptr %x80 %red = call half @llvm.vector.reduce.fadd.v4f16(half %s, <4 x half> %v)81 ret half %red82}83 84define half @vreduce_fadd_v7f16(ptr %x, half %s) {85; CHECK-LABEL: vreduce_fadd_v7f16:86; CHECK: # %bb.0:87; CHECK-NEXT: vsetivli zero, 7, e16, m1, ta, ma88; CHECK-NEXT: vle16.v v8, (a0)89; CHECK-NEXT: vfmv.s.f v9, fa090; CHECK-NEXT: vfredusum.vs v8, v8, v991; CHECK-NEXT: vfmv.f.s fa0, v892; CHECK-NEXT: ret93 %v = load <7 x half>, ptr %x94 %red = call reassoc half @llvm.vector.reduce.fadd.v7f16(half %s, <7 x half> %v)95 ret half %red96}97 98define half @vreduce_fadd_v8f16(ptr %x, half %s) {99; CHECK-LABEL: vreduce_fadd_v8f16:100; CHECK: # %bb.0:101; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma102; CHECK-NEXT: vle16.v v8, (a0)103; CHECK-NEXT: vfmv.s.f v9, fa0104; CHECK-NEXT: vfredusum.vs v8, v8, v9105; CHECK-NEXT: vfmv.f.s fa0, v8106; CHECK-NEXT: ret107 %v = load <8 x half>, ptr %x108 %red = call reassoc half @llvm.vector.reduce.fadd.v8f16(half %s, <8 x half> %v)109 ret half %red110}111 112define half @vreduce_ord_fadd_v8f16(ptr %x, half %s) {113; CHECK-LABEL: vreduce_ord_fadd_v8f16:114; CHECK: # %bb.0:115; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma116; CHECK-NEXT: vle16.v v8, (a0)117; CHECK-NEXT: vfmv.s.f v9, fa0118; CHECK-NEXT: vfredosum.vs v8, v8, v9119; CHECK-NEXT: vfmv.f.s fa0, v8120; CHECK-NEXT: ret121 %v = load <8 x half>, ptr %x122 %red = call half @llvm.vector.reduce.fadd.v8f16(half %s, <8 x half> %v)123 ret half %red124}125 126define half @vreduce_fadd_v16f16(ptr %x, half %s) {127; CHECK-LABEL: vreduce_fadd_v16f16:128; CHECK: # %bb.0:129; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma130; CHECK-NEXT: vle16.v v8, (a0)131; CHECK-NEXT: vfmv.s.f v10, fa0132; CHECK-NEXT: vfredusum.vs v8, v8, v10133; CHECK-NEXT: vfmv.f.s fa0, v8134; CHECK-NEXT: ret135 %v = load <16 x half>, ptr %x136 %red = call reassoc half @llvm.vector.reduce.fadd.v16f16(half %s, <16 x half> %v)137 ret half %red138}139 140define half @vreduce_ord_fadd_v16f16(ptr %x, half %s) {141; CHECK-LABEL: vreduce_ord_fadd_v16f16:142; CHECK: # %bb.0:143; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma144; CHECK-NEXT: vle16.v v8, (a0)145; CHECK-NEXT: vfmv.s.f v10, fa0146; CHECK-NEXT: vfredosum.vs v8, v8, v10147; CHECK-NEXT: vfmv.f.s fa0, v8148; CHECK-NEXT: ret149 %v = load <16 x half>, ptr %x150 %red = call half @llvm.vector.reduce.fadd.v16f16(half %s, <16 x half> %v)151 ret half %red152}153 154define half @vreduce_fadd_v32f16(ptr %x, half %s) {155; CHECK-LABEL: vreduce_fadd_v32f16:156; CHECK: # %bb.0:157; CHECK-NEXT: li a1, 32158; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma159; CHECK-NEXT: vle16.v v8, (a0)160; CHECK-NEXT: vfmv.s.f v12, fa0161; CHECK-NEXT: vfredusum.vs v8, v8, v12162; CHECK-NEXT: vfmv.f.s fa0, v8163; CHECK-NEXT: ret164 %v = load <32 x half>, ptr %x165 %red = call reassoc half @llvm.vector.reduce.fadd.v32f16(half %s, <32 x half> %v)166 ret half %red167}168 169define half @vreduce_ord_fadd_v32f16(ptr %x, half %s) {170; CHECK-LABEL: vreduce_ord_fadd_v32f16:171; CHECK: # %bb.0:172; CHECK-NEXT: li a1, 32173; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma174; CHECK-NEXT: vle16.v v8, (a0)175; CHECK-NEXT: vfmv.s.f v12, fa0176; CHECK-NEXT: vfredosum.vs v8, v8, v12177; CHECK-NEXT: vfmv.f.s fa0, v8178; CHECK-NEXT: ret179 %v = load <32 x half>, ptr %x180 %red = call half @llvm.vector.reduce.fadd.v32f16(half %s, <32 x half> %v)181 ret half %red182}183 184define half @vreduce_fadd_v64f16(ptr %x, half %s) {185; CHECK-LABEL: vreduce_fadd_v64f16:186; CHECK: # %bb.0:187; CHECK-NEXT: li a1, 64188; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma189; CHECK-NEXT: vle16.v v8, (a0)190; CHECK-NEXT: vfmv.s.f v16, fa0191; CHECK-NEXT: vfredusum.vs v8, v8, v16192; CHECK-NEXT: vfmv.f.s fa0, v8193; CHECK-NEXT: ret194 %v = load <64 x half>, ptr %x195 %red = call reassoc half @llvm.vector.reduce.fadd.v64f16(half %s, <64 x half> %v)196 ret half %red197}198 199define half @vreduce_ord_fadd_v64f16(ptr %x, half %s) {200; CHECK-LABEL: vreduce_ord_fadd_v64f16:201; CHECK: # %bb.0:202; CHECK-NEXT: li a1, 64203; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma204; CHECK-NEXT: vle16.v v8, (a0)205; CHECK-NEXT: vfmv.s.f v16, fa0206; CHECK-NEXT: vfredosum.vs v8, v8, v16207; CHECK-NEXT: vfmv.f.s fa0, v8208; CHECK-NEXT: ret209 %v = load <64 x half>, ptr %x210 %red = call half @llvm.vector.reduce.fadd.v64f16(half %s, <64 x half> %v)211 ret half %red212}213 214define half @vreduce_fadd_v128f16(ptr %x, half %s) {215; CHECK-LABEL: vreduce_fadd_v128f16:216; CHECK: # %bb.0:217; CHECK-NEXT: li a1, 64218; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma219; CHECK-NEXT: vle16.v v8, (a0)220; CHECK-NEXT: addi a0, a0, 128221; CHECK-NEXT: vle16.v v16, (a0)222; CHECK-NEXT: vfadd.vv v8, v8, v16223; CHECK-NEXT: vfmv.s.f v16, fa0224; CHECK-NEXT: vfredusum.vs v8, v8, v16225; CHECK-NEXT: vfmv.f.s fa0, v8226; CHECK-NEXT: ret227 %v = load <128 x half>, ptr %x228 %red = call reassoc half @llvm.vector.reduce.fadd.v128f16(half %s, <128 x half> %v)229 ret half %red230}231 232define half @vreduce_ord_fadd_v128f16(ptr %x, half %s) {233; CHECK-LABEL: vreduce_ord_fadd_v128f16:234; CHECK: # %bb.0:235; CHECK-NEXT: addi a1, a0, 128236; CHECK-NEXT: li a2, 64237; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma238; CHECK-NEXT: vle16.v v8, (a0)239; CHECK-NEXT: vle16.v v16, (a1)240; CHECK-NEXT: vfmv.s.f v24, fa0241; CHECK-NEXT: vfredosum.vs v8, v8, v24242; CHECK-NEXT: vfredosum.vs v8, v16, v8243; CHECK-NEXT: vfmv.f.s fa0, v8244; CHECK-NEXT: ret245 %v = load <128 x half>, ptr %x246 %red = call half @llvm.vector.reduce.fadd.v128f16(half %s, <128 x half> %v)247 ret half %red248}249 250define float @vreduce_fadd_v1f32(<1 x float> %v, float %s) {251; CHECK-LABEL: vreduce_fadd_v1f32:252; CHECK: # %bb.0:253; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma254; CHECK-NEXT: vfmv.f.s fa5, v8255; CHECK-NEXT: fadd.s fa0, fa0, fa5256; CHECK-NEXT: ret257 %red = call reassoc float @llvm.vector.reduce.fadd.v1f32(float %s, <1 x float> %v)258 ret float %red259}260 261define float @vreduce_ord_fadd_v1f32(<1 x float> %v, float %s) {262; CHECK-LABEL: vreduce_ord_fadd_v1f32:263; CHECK: # %bb.0:264; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma265; CHECK-NEXT: vfmv.s.f v9, fa0266; CHECK-NEXT: vfredosum.vs v8, v8, v9267; CHECK-NEXT: vfmv.f.s fa0, v8268; CHECK-NEXT: ret269 %red = call float @llvm.vector.reduce.fadd.v1f32(float %s, <1 x float> %v)270 ret float %red271}272 273define float @vreduce_fwadd_v1f32(<1 x half> %v, float %s) {274; CHECK-LABEL: vreduce_fwadd_v1f32:275; CHECK: # %bb.0:276; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma277; CHECK-NEXT: vfwcvt.f.f.v v9, v8278; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma279; CHECK-NEXT: vfmv.f.s fa5, v9280; CHECK-NEXT: fadd.s fa0, fa0, fa5281; CHECK-NEXT: ret282 %e = fpext <1 x half> %v to <1 x float>283 %red = call reassoc float @llvm.vector.reduce.fadd.v1f32(float %s, <1 x float> %e)284 ret float %red285}286 287define float @vreduce_ord_fwadd_v1f32(<1 x half> %v, float %s) {288; CHECK-LABEL: vreduce_ord_fwadd_v1f32:289; CHECK: # %bb.0:290; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma291; CHECK-NEXT: vfmv.s.f v9, fa0292; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma293; CHECK-NEXT: vfwredosum.vs v8, v8, v9294; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma295; CHECK-NEXT: vfmv.f.s fa0, v8296; CHECK-NEXT: ret297 %e = fpext <1 x half> %v to <1 x float>298 %red = call float @llvm.vector.reduce.fadd.v1f32(float %s, <1 x float> %e)299 ret float %red300}301 302define float @vreduce_fadd_v2f32(ptr %x, float %s) {303; CHECK-LABEL: vreduce_fadd_v2f32:304; CHECK: # %bb.0:305; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma306; CHECK-NEXT: vle32.v v8, (a0)307; CHECK-NEXT: vfmv.s.f v9, fa0308; CHECK-NEXT: vfredusum.vs v8, v8, v9309; CHECK-NEXT: vfmv.f.s fa0, v8310; CHECK-NEXT: ret311 %v = load <2 x float>, ptr %x312 %red = call reassoc float @llvm.vector.reduce.fadd.v2f32(float %s, <2 x float> %v)313 ret float %red314}315 316define float @vreduce_ord_fadd_v2f32(ptr %x, float %s) {317; CHECK-LABEL: vreduce_ord_fadd_v2f32:318; CHECK: # %bb.0:319; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma320; CHECK-NEXT: vle32.v v8, (a0)321; CHECK-NEXT: vfmv.s.f v9, fa0322; CHECK-NEXT: vfredosum.vs v8, v8, v9323; CHECK-NEXT: vfmv.f.s fa0, v8324; CHECK-NEXT: ret325 %v = load <2 x float>, ptr %x326 %red = call float @llvm.vector.reduce.fadd.v2f32(float %s, <2 x float> %v)327 ret float %red328}329 330define float @vreduce_fwadd_v2f32(ptr %x, float %s) {331; CHECK-LABEL: vreduce_fwadd_v2f32:332; CHECK: # %bb.0:333; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma334; CHECK-NEXT: vle16.v v8, (a0)335; CHECK-NEXT: vfmv.s.f v9, fa0336; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma337; CHECK-NEXT: vfwredusum.vs v8, v8, v9338; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma339; CHECK-NEXT: vfmv.f.s fa0, v8340; CHECK-NEXT: ret341 %v = load <2 x half>, ptr %x342 %e = fpext <2 x half> %v to <2 x float>343 %red = call reassoc float @llvm.vector.reduce.fadd.v2f32(float %s, <2 x float> %e)344 ret float %red345}346 347define float @vreduce_ord_fwadd_v2f32(ptr %x, float %s) {348; CHECK-LABEL: vreduce_ord_fwadd_v2f32:349; CHECK: # %bb.0:350; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma351; CHECK-NEXT: vle16.v v8, (a0)352; CHECK-NEXT: vfmv.s.f v9, fa0353; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma354; CHECK-NEXT: vfwredosum.vs v8, v8, v9355; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma356; CHECK-NEXT: vfmv.f.s fa0, v8357; CHECK-NEXT: ret358 %v = load <2 x half>, ptr %x359 %e = fpext <2 x half> %v to <2 x float>360 %red = call float @llvm.vector.reduce.fadd.v2f32(float %s, <2 x float> %e)361 ret float %red362}363 364define float @vreduce_fadd_v4f32(ptr %x, float %s) {365; CHECK-LABEL: vreduce_fadd_v4f32:366; CHECK: # %bb.0:367; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma368; CHECK-NEXT: vle32.v v8, (a0)369; CHECK-NEXT: vfmv.s.f v9, fa0370; CHECK-NEXT: vfredusum.vs v8, v8, v9371; CHECK-NEXT: vfmv.f.s fa0, v8372; CHECK-NEXT: ret373 %v = load <4 x float>, ptr %x374 %red = call reassoc float @llvm.vector.reduce.fadd.v4f32(float %s, <4 x float> %v)375 ret float %red376}377 378define float @vreduce_ord_fadd_v4f32(ptr %x, float %s) {379; CHECK-LABEL: vreduce_ord_fadd_v4f32:380; CHECK: # %bb.0:381; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma382; CHECK-NEXT: vle32.v v8, (a0)383; CHECK-NEXT: vfmv.s.f v9, fa0384; CHECK-NEXT: vfredosum.vs v8, v8, v9385; CHECK-NEXT: vfmv.f.s fa0, v8386; CHECK-NEXT: ret387 %v = load <4 x float>, ptr %x388 %red = call float @llvm.vector.reduce.fadd.v4f32(float %s, <4 x float> %v)389 ret float %red390}391 392define float @vreduce_fwadd_v4f32(ptr %x, float %s) {393; CHECK-LABEL: vreduce_fwadd_v4f32:394; CHECK: # %bb.0:395; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma396; CHECK-NEXT: vle16.v v8, (a0)397; CHECK-NEXT: vfmv.s.f v9, fa0398; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma399; CHECK-NEXT: vfwredusum.vs v8, v8, v9400; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma401; CHECK-NEXT: vfmv.f.s fa0, v8402; CHECK-NEXT: ret403 %v = load <4 x half>, ptr %x404 %e = fpext <4 x half> %v to <4 x float>405 %red = call reassoc float @llvm.vector.reduce.fadd.v4f32(float %s, <4 x float> %e)406 ret float %red407}408 409define float @vreduce_ord_fwadd_v4f32(ptr %x, float %s) {410; CHECK-LABEL: vreduce_ord_fwadd_v4f32:411; CHECK: # %bb.0:412; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma413; CHECK-NEXT: vle16.v v8, (a0)414; CHECK-NEXT: vfmv.s.f v9, fa0415; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma416; CHECK-NEXT: vfwredosum.vs v8, v8, v9417; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma418; CHECK-NEXT: vfmv.f.s fa0, v8419; CHECK-NEXT: ret420 %v = load <4 x half>, ptr %x421 %e = fpext <4 x half> %v to <4 x float>422 %red = call float @llvm.vector.reduce.fadd.v4f32(float %s, <4 x float> %e)423 ret float %red424}425 426define float @vreduce_fadd_v7f32(ptr %x, float %s) {427; CHECK-LABEL: vreduce_fadd_v7f32:428; CHECK: # %bb.0:429; CHECK-NEXT: vsetivli zero, 7, e32, m2, ta, ma430; CHECK-NEXT: vle32.v v8, (a0)431; CHECK-NEXT: vfmv.s.f v10, fa0432; CHECK-NEXT: vfredusum.vs v8, v8, v10433; CHECK-NEXT: vfmv.f.s fa0, v8434; CHECK-NEXT: ret435 %v = load <7 x float>, ptr %x436 %red = call reassoc float @llvm.vector.reduce.fadd.v7f32(float %s, <7 x float> %v)437 ret float %red438}439 440define float @vreduce_ord_fadd_v7f32(ptr %x, float %s) {441; CHECK-LABEL: vreduce_ord_fadd_v7f32:442; CHECK: # %bb.0:443; CHECK-NEXT: vsetivli zero, 7, e32, m2, ta, ma444; CHECK-NEXT: vle32.v v8, (a0)445; CHECK-NEXT: vfmv.s.f v10, fa0446; CHECK-NEXT: vfredosum.vs v8, v8, v10447; CHECK-NEXT: vfmv.f.s fa0, v8448; CHECK-NEXT: ret449 %v = load <7 x float>, ptr %x450 %red = call float @llvm.vector.reduce.fadd.v7f32(float %s, <7 x float> %v)451 ret float %red452}453 454define float @vreduce_fadd_v7f32_neutralstart(ptr %x) {455; CHECK-LABEL: vreduce_fadd_v7f32_neutralstart:456; CHECK: # %bb.0:457; CHECK-NEXT: vsetivli zero, 7, e32, m2, ta, ma458; CHECK-NEXT: vle32.v v8, (a0)459; CHECK-NEXT: lui a0, 524288460; CHECK-NEXT: vmv.s.x v10, a0461; CHECK-NEXT: vfredusum.vs v8, v8, v10462; CHECK-NEXT: vfmv.f.s fa0, v8463; CHECK-NEXT: ret464 %v = load <7 x float>, ptr %x465 %red = call reassoc float @llvm.vector.reduce.fadd.v7f32(float -0.0, <7 x float> %v)466 ret float %red467}468 469define float @vreduce_fadd_v7f32_neutralstart_nsz(ptr %x) {470; CHECK-LABEL: vreduce_fadd_v7f32_neutralstart_nsz:471; CHECK: # %bb.0:472; CHECK-NEXT: vsetivli zero, 7, e32, m2, ta, ma473; CHECK-NEXT: vle32.v v8, (a0)474; CHECK-NEXT: lui a0, 524288475; CHECK-NEXT: vmv.s.x v10, a0476; CHECK-NEXT: vfredosum.vs v8, v8, v10477; CHECK-NEXT: vfmv.f.s fa0, v8478; CHECK-NEXT: ret479 %v = load <7 x float>, ptr %x480 %red = call nsz float @llvm.vector.reduce.fadd.v7f32(float -0.0, <7 x float> %v)481 ret float %red482}483 484define float @vreduce_fadd_v7f32_neutralstart_fast(ptr %x) {485; CHECK-LABEL: vreduce_fadd_v7f32_neutralstart_fast:486; CHECK: # %bb.0:487; CHECK-NEXT: vsetivli zero, 7, e32, m2, ta, ma488; CHECK-NEXT: vle32.v v8, (a0)489; CHECK-NEXT: vmv.s.x v10, zero490; CHECK-NEXT: vfredusum.vs v8, v8, v10491; CHECK-NEXT: vfmv.f.s fa0, v8492; CHECK-NEXT: ret493 %v = load <7 x float>, ptr %x494 %red = call fast float @llvm.vector.reduce.fadd.v7f32(float -0.0, <7 x float> %v)495 ret float %red496}497 498define float @vreduce_fadd_v8f32(ptr %x, float %s) {499; CHECK-LABEL: vreduce_fadd_v8f32:500; CHECK: # %bb.0:501; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma502; CHECK-NEXT: vle32.v v8, (a0)503; CHECK-NEXT: vfmv.s.f v10, fa0504; CHECK-NEXT: vfredusum.vs v8, v8, v10505; CHECK-NEXT: vfmv.f.s fa0, v8506; CHECK-NEXT: ret507 %v = load <8 x float>, ptr %x508 %red = call reassoc float @llvm.vector.reduce.fadd.v8f32(float %s, <8 x float> %v)509 ret float %red510}511 512define float @vreduce_ord_fadd_v8f32(ptr %x, float %s) {513; CHECK-LABEL: vreduce_ord_fadd_v8f32:514; CHECK: # %bb.0:515; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma516; CHECK-NEXT: vle32.v v8, (a0)517; CHECK-NEXT: vfmv.s.f v10, fa0518; CHECK-NEXT: vfredosum.vs v8, v8, v10519; CHECK-NEXT: vfmv.f.s fa0, v8520; CHECK-NEXT: ret521 %v = load <8 x float>, ptr %x522 %red = call float @llvm.vector.reduce.fadd.v8f32(float %s, <8 x float> %v)523 ret float %red524}525 526define float @vreduce_fwadd_v8f32(ptr %x, float %s) {527; CHECK-LABEL: vreduce_fwadd_v8f32:528; CHECK: # %bb.0:529; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma530; CHECK-NEXT: vle16.v v8, (a0)531; CHECK-NEXT: vfmv.s.f v9, fa0532; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma533; CHECK-NEXT: vfwredusum.vs v8, v8, v9534; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma535; CHECK-NEXT: vfmv.f.s fa0, v8536; CHECK-NEXT: ret537 %v = load <8 x half>, ptr %x538 %e = fpext <8 x half> %v to <8 x float>539 %red = call reassoc float @llvm.vector.reduce.fadd.v8f32(float %s, <8 x float> %e)540 ret float %red541}542 543define float @vreduce_ord_fwadd_v8f32(ptr %x, float %s) {544; CHECK-LABEL: vreduce_ord_fwadd_v8f32:545; CHECK: # %bb.0:546; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma547; CHECK-NEXT: vle16.v v8, (a0)548; CHECK-NEXT: vfmv.s.f v9, fa0549; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma550; CHECK-NEXT: vfwredosum.vs v8, v8, v9551; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma552; CHECK-NEXT: vfmv.f.s fa0, v8553; CHECK-NEXT: ret554 %v = load <8 x half>, ptr %x555 %e = fpext <8 x half> %v to <8 x float>556 %red = call float @llvm.vector.reduce.fadd.v8f32(float %s, <8 x float> %e)557 ret float %red558}559 560define float @vreduce_fadd_v16f32(ptr %x, float %s) {561; CHECK-LABEL: vreduce_fadd_v16f32:562; CHECK: # %bb.0:563; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma564; CHECK-NEXT: vle32.v v8, (a0)565; CHECK-NEXT: vfmv.s.f v12, fa0566; CHECK-NEXT: vfredusum.vs v8, v8, v12567; CHECK-NEXT: vfmv.f.s fa0, v8568; CHECK-NEXT: ret569 %v = load <16 x float>, ptr %x570 %red = call reassoc float @llvm.vector.reduce.fadd.v16f32(float %s, <16 x float> %v)571 ret float %red572}573 574define float @vreduce_ord_fadd_v16f32(ptr %x, float %s) {575; CHECK-LABEL: vreduce_ord_fadd_v16f32:576; CHECK: # %bb.0:577; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma578; CHECK-NEXT: vle32.v v8, (a0)579; CHECK-NEXT: vfmv.s.f v12, fa0580; CHECK-NEXT: vfredosum.vs v8, v8, v12581; CHECK-NEXT: vfmv.f.s fa0, v8582; CHECK-NEXT: ret583 %v = load <16 x float>, ptr %x584 %red = call float @llvm.vector.reduce.fadd.v16f32(float %s, <16 x float> %v)585 ret float %red586}587 588define float @vreduce_fwadd_v16f32(ptr %x, float %s) {589; CHECK-LABEL: vreduce_fwadd_v16f32:590; CHECK: # %bb.0:591; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma592; CHECK-NEXT: vle16.v v8, (a0)593; CHECK-NEXT: vfmv.s.f v10, fa0594; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma595; CHECK-NEXT: vfwredusum.vs v8, v8, v10596; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma597; CHECK-NEXT: vfmv.f.s fa0, v8598; CHECK-NEXT: ret599 %v = load <16 x half>, ptr %x600 %e = fpext <16 x half> %v to <16 x float>601 %red = call reassoc float @llvm.vector.reduce.fadd.v16f32(float %s, <16 x float> %e)602 ret float %red603}604 605define float @vreduce_ord_fwadd_v16f32(ptr %x, float %s) {606; CHECK-LABEL: vreduce_ord_fwadd_v16f32:607; CHECK: # %bb.0:608; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma609; CHECK-NEXT: vle16.v v8, (a0)610; CHECK-NEXT: vfmv.s.f v10, fa0611; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma612; CHECK-NEXT: vfwredosum.vs v8, v8, v10613; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma614; CHECK-NEXT: vfmv.f.s fa0, v8615; CHECK-NEXT: ret616 %v = load <16 x half>, ptr %x617 %e = fpext <16 x half> %v to <16 x float>618 %red = call float @llvm.vector.reduce.fadd.v16f32(float %s, <16 x float> %e)619 ret float %red620}621 622define float @vreduce_fadd_v32f32(ptr %x, float %s) {623; CHECK-LABEL: vreduce_fadd_v32f32:624; CHECK: # %bb.0:625; CHECK-NEXT: li a1, 32626; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma627; CHECK-NEXT: vle32.v v8, (a0)628; CHECK-NEXT: vfmv.s.f v16, fa0629; CHECK-NEXT: vfredusum.vs v8, v8, v16630; CHECK-NEXT: vfmv.f.s fa0, v8631; CHECK-NEXT: ret632 %v = load <32 x float>, ptr %x633 %red = call reassoc float @llvm.vector.reduce.fadd.v32f32(float %s, <32 x float> %v)634 ret float %red635}636 637define float @vreduce_ord_fadd_v32f32(ptr %x, float %s) {638; CHECK-LABEL: vreduce_ord_fadd_v32f32:639; CHECK: # %bb.0:640; CHECK-NEXT: li a1, 32641; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma642; CHECK-NEXT: vle32.v v8, (a0)643; CHECK-NEXT: vfmv.s.f v16, fa0644; CHECK-NEXT: vfredosum.vs v8, v8, v16645; CHECK-NEXT: vfmv.f.s fa0, v8646; CHECK-NEXT: ret647 %v = load <32 x float>, ptr %x648 %red = call float @llvm.vector.reduce.fadd.v32f32(float %s, <32 x float> %v)649 ret float %red650}651 652define float @vreduce_fwadd_v32f32(ptr %x, float %s) {653; CHECK-LABEL: vreduce_fwadd_v32f32:654; CHECK: # %bb.0:655; CHECK-NEXT: li a1, 32656; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma657; CHECK-NEXT: vle16.v v8, (a0)658; CHECK-NEXT: vfmv.s.f v12, fa0659; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma660; CHECK-NEXT: vfwredusum.vs v8, v8, v12661; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma662; CHECK-NEXT: vfmv.f.s fa0, v8663; CHECK-NEXT: ret664 %v = load <32 x half>, ptr %x665 %e = fpext <32 x half> %v to <32 x float>666 %red = call reassoc float @llvm.vector.reduce.fadd.v32f32(float %s, <32 x float> %e)667 ret float %red668}669 670define float @vreduce_ord_fwadd_v32f32(ptr %x, float %s) {671; CHECK-LABEL: vreduce_ord_fwadd_v32f32:672; CHECK: # %bb.0:673; CHECK-NEXT: li a1, 32674; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma675; CHECK-NEXT: vle16.v v8, (a0)676; CHECK-NEXT: vfmv.s.f v12, fa0677; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma678; CHECK-NEXT: vfwredosum.vs v8, v8, v12679; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma680; CHECK-NEXT: vfmv.f.s fa0, v8681; CHECK-NEXT: ret682 %v = load <32 x half>, ptr %x683 %e = fpext <32 x half> %v to <32 x float>684 %red = call float @llvm.vector.reduce.fadd.v32f32(float %s, <32 x float> %e)685 ret float %red686}687 688define float @vreduce_fadd_v64f32(ptr %x, float %s) {689; CHECK-LABEL: vreduce_fadd_v64f32:690; CHECK: # %bb.0:691; CHECK-NEXT: li a1, 32692; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma693; CHECK-NEXT: vle32.v v8, (a0)694; CHECK-NEXT: addi a0, a0, 128695; CHECK-NEXT: vle32.v v16, (a0)696; CHECK-NEXT: vfadd.vv v8, v8, v16697; CHECK-NEXT: vfmv.s.f v16, fa0698; CHECK-NEXT: vfredusum.vs v8, v8, v16699; CHECK-NEXT: vfmv.f.s fa0, v8700; CHECK-NEXT: ret701 %v = load <64 x float>, ptr %x702 %red = call reassoc float @llvm.vector.reduce.fadd.v64f32(float %s, <64 x float> %v)703 ret float %red704}705 706define float @vreduce_ord_fadd_v64f32(ptr %x, float %s) {707; CHECK-LABEL: vreduce_ord_fadd_v64f32:708; CHECK: # %bb.0:709; CHECK-NEXT: addi a1, a0, 128710; CHECK-NEXT: li a2, 32711; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma712; CHECK-NEXT: vle32.v v8, (a0)713; CHECK-NEXT: vle32.v v16, (a1)714; CHECK-NEXT: vfmv.s.f v24, fa0715; CHECK-NEXT: vfredosum.vs v8, v8, v24716; CHECK-NEXT: vfredosum.vs v8, v16, v8717; CHECK-NEXT: vfmv.f.s fa0, v8718; CHECK-NEXT: ret719 %v = load <64 x float>, ptr %x720 %red = call float @llvm.vector.reduce.fadd.v64f32(float %s, <64 x float> %v)721 ret float %red722}723 724define float @vreduce_fwadd_v64f32(ptr %x, float %s) {725; CHECK-LABEL: vreduce_fwadd_v64f32:726; CHECK: # %bb.0:727; CHECK-NEXT: li a1, 64728; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma729; CHECK-NEXT: vle16.v v8, (a0)730; CHECK-NEXT: li a0, 32731; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma732; CHECK-NEXT: vslidedown.vx v16, v8, a0733; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma734; CHECK-NEXT: vfwadd.vv v24, v8, v16735; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma736; CHECK-NEXT: vfmv.s.f v8, fa0737; CHECK-NEXT: vfredusum.vs v8, v24, v8738; CHECK-NEXT: vfmv.f.s fa0, v8739; CHECK-NEXT: ret740 %v = load <64 x half>, ptr %x741 %e = fpext <64 x half> %v to <64 x float>742 %red = call reassoc float @llvm.vector.reduce.fadd.v64f32(float %s, <64 x float> %e)743 ret float %red744}745 746define float @vreduce_ord_fwadd_v64f32(ptr %x, float %s) {747; CHECK-LABEL: vreduce_ord_fwadd_v64f32:748; CHECK: # %bb.0:749; CHECK-NEXT: li a1, 64750; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma751; CHECK-NEXT: vle16.v v8, (a0)752; CHECK-NEXT: li a0, 32753; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma754; CHECK-NEXT: vfmv.s.f v24, fa0755; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma756; CHECK-NEXT: vslidedown.vx v16, v8, a0757; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma758; CHECK-NEXT: vfwredosum.vs v8, v8, v24759; CHECK-NEXT: vfwredosum.vs v8, v16, v8760; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma761; CHECK-NEXT: vfmv.f.s fa0, v8762; CHECK-NEXT: ret763 %v = load <64 x half>, ptr %x764 %e = fpext <64 x half> %v to <64 x float>765 %red = call float @llvm.vector.reduce.fadd.v64f32(float %s, <64 x float> %e)766 ret float %red767}768 769define double @vreduce_fadd_v1f64(<1 x double> %v, double %s) {770; CHECK-LABEL: vreduce_fadd_v1f64:771; CHECK: # %bb.0:772; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma773; CHECK-NEXT: vfmv.f.s fa5, v8774; CHECK-NEXT: fadd.d fa0, fa0, fa5775; CHECK-NEXT: ret776 %red = call reassoc double @llvm.vector.reduce.fadd.v1f64(double %s, <1 x double> %v)777 ret double %red778}779 780define double @vreduce_ord_fadd_v1f64(<1 x double> %v, double %s) {781; CHECK-LABEL: vreduce_ord_fadd_v1f64:782; CHECK: # %bb.0:783; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma784; CHECK-NEXT: vfmv.s.f v9, fa0785; CHECK-NEXT: vfredosum.vs v8, v8, v9786; CHECK-NEXT: vfmv.f.s fa0, v8787; CHECK-NEXT: ret788 %red = call double @llvm.vector.reduce.fadd.v1f64(double %s, <1 x double> %v)789 ret double %red790}791 792define double @vreduce_fwadd_v1f64(<1 x float> %v, double %s) {793; CHECK-LABEL: vreduce_fwadd_v1f64:794; CHECK: # %bb.0:795; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma796; CHECK-NEXT: vfwcvt.f.f.v v9, v8797; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma798; CHECK-NEXT: vfmv.f.s fa5, v9799; CHECK-NEXT: fadd.d fa0, fa0, fa5800; CHECK-NEXT: ret801 %e = fpext <1 x float> %v to <1 x double>802 %red = call reassoc double @llvm.vector.reduce.fadd.v1f64(double %s, <1 x double> %e)803 ret double %red804}805 806define double @vreduce_ord_fwadd_v1f64(<1 x float> %v, double %s) {807; CHECK-LABEL: vreduce_ord_fwadd_v1f64:808; CHECK: # %bb.0:809; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma810; CHECK-NEXT: vfmv.s.f v9, fa0811; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma812; CHECK-NEXT: vfwredosum.vs v8, v8, v9813; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma814; CHECK-NEXT: vfmv.f.s fa0, v8815; CHECK-NEXT: ret816 %e = fpext <1 x float> %v to <1 x double>817 %red = call double @llvm.vector.reduce.fadd.v1f64(double %s, <1 x double> %e)818 ret double %red819}820 821define double @vreduce_fadd_v2f64(ptr %x, double %s) {822; CHECK-LABEL: vreduce_fadd_v2f64:823; CHECK: # %bb.0:824; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma825; CHECK-NEXT: vle64.v v8, (a0)826; CHECK-NEXT: vfmv.s.f v9, fa0827; CHECK-NEXT: vfredusum.vs v8, v8, v9828; CHECK-NEXT: vfmv.f.s fa0, v8829; CHECK-NEXT: ret830 %v = load <2 x double>, ptr %x831 %red = call reassoc double @llvm.vector.reduce.fadd.v2f64(double %s, <2 x double> %v)832 ret double %red833}834 835define double @vreduce_ord_fadd_v2f64(ptr %x, double %s) {836; CHECK-LABEL: vreduce_ord_fadd_v2f64:837; CHECK: # %bb.0:838; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma839; CHECK-NEXT: vle64.v v8, (a0)840; CHECK-NEXT: vfmv.s.f v9, fa0841; CHECK-NEXT: vfredosum.vs v8, v8, v9842; CHECK-NEXT: vfmv.f.s fa0, v8843; CHECK-NEXT: ret844 %v = load <2 x double>, ptr %x845 %red = call double @llvm.vector.reduce.fadd.v2f64(double %s, <2 x double> %v)846 ret double %red847}848 849define double @vreduce_fwadd_v2f64(ptr %x, double %s) {850; CHECK-LABEL: vreduce_fwadd_v2f64:851; CHECK: # %bb.0:852; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma853; CHECK-NEXT: vle32.v v8, (a0)854; CHECK-NEXT: vfmv.s.f v9, fa0855; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma856; CHECK-NEXT: vfwredusum.vs v8, v8, v9857; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma858; CHECK-NEXT: vfmv.f.s fa0, v8859; CHECK-NEXT: ret860 %v = load <2 x float>, ptr %x861 %e = fpext <2 x float> %v to <2 x double>862 %red = call reassoc double @llvm.vector.reduce.fadd.v2f64(double %s, <2 x double> %e)863 ret double %red864}865 866define double @vreduce_ord_fwadd_v2f64(ptr %x, double %s) {867; CHECK-LABEL: vreduce_ord_fwadd_v2f64:868; CHECK: # %bb.0:869; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma870; CHECK-NEXT: vle32.v v8, (a0)871; CHECK-NEXT: vfmv.s.f v9, fa0872; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma873; CHECK-NEXT: vfwredosum.vs v8, v8, v9874; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma875; CHECK-NEXT: vfmv.f.s fa0, v8876; CHECK-NEXT: ret877 %v = load <2 x float>, ptr %x878 %e = fpext <2 x float> %v to <2 x double>879 %red = call double @llvm.vector.reduce.fadd.v2f64(double %s, <2 x double> %e)880 ret double %red881}882 883define double @vreduce_fadd_v4f64(ptr %x, double %s) {884; CHECK-LABEL: vreduce_fadd_v4f64:885; CHECK: # %bb.0:886; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma887; CHECK-NEXT: vle64.v v8, (a0)888; CHECK-NEXT: vfmv.s.f v10, fa0889; CHECK-NEXT: vfredusum.vs v8, v8, v10890; CHECK-NEXT: vfmv.f.s fa0, v8891; CHECK-NEXT: ret892 %v = load <4 x double>, ptr %x893 %red = call reassoc double @llvm.vector.reduce.fadd.v4f64(double %s, <4 x double> %v)894 ret double %red895}896 897define double @vreduce_ord_fadd_v4f64(ptr %x, double %s) {898; CHECK-LABEL: vreduce_ord_fadd_v4f64:899; CHECK: # %bb.0:900; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma901; CHECK-NEXT: vle64.v v8, (a0)902; CHECK-NEXT: vfmv.s.f v10, fa0903; CHECK-NEXT: vfredosum.vs v8, v8, v10904; CHECK-NEXT: vfmv.f.s fa0, v8905; CHECK-NEXT: ret906 %v = load <4 x double>, ptr %x907 %red = call double @llvm.vector.reduce.fadd.v4f64(double %s, <4 x double> %v)908 ret double %red909}910 911define double @vreduce_fwadd_v4f64(ptr %x, double %s) {912; CHECK-LABEL: vreduce_fwadd_v4f64:913; CHECK: # %bb.0:914; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma915; CHECK-NEXT: vle32.v v8, (a0)916; CHECK-NEXT: vfmv.s.f v9, fa0917; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma918; CHECK-NEXT: vfwredusum.vs v8, v8, v9919; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma920; CHECK-NEXT: vfmv.f.s fa0, v8921; CHECK-NEXT: ret922 %v = load <4 x float>, ptr %x923 %e = fpext <4 x float> %v to <4 x double>924 %red = call reassoc double @llvm.vector.reduce.fadd.v4f64(double %s, <4 x double> %e)925 ret double %red926}927 928define double @vreduce_ord_fwadd_v4f64(ptr %x, double %s) {929; CHECK-LABEL: vreduce_ord_fwadd_v4f64:930; CHECK: # %bb.0:931; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma932; CHECK-NEXT: vle32.v v8, (a0)933; CHECK-NEXT: vfmv.s.f v9, fa0934; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma935; CHECK-NEXT: vfwredosum.vs v8, v8, v9936; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma937; CHECK-NEXT: vfmv.f.s fa0, v8938; CHECK-NEXT: ret939 %v = load <4 x float>, ptr %x940 %e = fpext <4 x float> %v to <4 x double>941 %red = call double @llvm.vector.reduce.fadd.v4f64(double %s, <4 x double> %e)942 ret double %red943}944 945define double @vreduce_fadd_v8f64(ptr %x, double %s) {946; CHECK-LABEL: vreduce_fadd_v8f64:947; CHECK: # %bb.0:948; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma949; CHECK-NEXT: vle64.v v8, (a0)950; CHECK-NEXT: vfmv.s.f v12, fa0951; CHECK-NEXT: vfredusum.vs v8, v8, v12952; CHECK-NEXT: vfmv.f.s fa0, v8953; CHECK-NEXT: ret954 %v = load <8 x double>, ptr %x955 %red = call reassoc double @llvm.vector.reduce.fadd.v8f64(double %s, <8 x double> %v)956 ret double %red957}958 959define double @vreduce_ord_fadd_v8f64(ptr %x, double %s) {960; CHECK-LABEL: vreduce_ord_fadd_v8f64:961; CHECK: # %bb.0:962; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma963; CHECK-NEXT: vle64.v v8, (a0)964; CHECK-NEXT: vfmv.s.f v12, fa0965; CHECK-NEXT: vfredosum.vs v8, v8, v12966; CHECK-NEXT: vfmv.f.s fa0, v8967; CHECK-NEXT: ret968 %v = load <8 x double>, ptr %x969 %red = call double @llvm.vector.reduce.fadd.v8f64(double %s, <8 x double> %v)970 ret double %red971}972 973define double @vreduce_fwadd_v8f64(ptr %x, double %s) {974; CHECK-LABEL: vreduce_fwadd_v8f64:975; CHECK: # %bb.0:976; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma977; CHECK-NEXT: vle32.v v8, (a0)978; CHECK-NEXT: vfmv.s.f v10, fa0979; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma980; CHECK-NEXT: vfwredusum.vs v8, v8, v10981; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma982; CHECK-NEXT: vfmv.f.s fa0, v8983; CHECK-NEXT: ret984 %v = load <8 x float>, ptr %x985 %e = fpext <8 x float> %v to <8 x double>986 %red = call reassoc double @llvm.vector.reduce.fadd.v8f64(double %s, <8 x double> %e)987 ret double %red988}989 990define double @vreduce_ord_fwadd_v8f64(ptr %x, double %s) {991; CHECK-LABEL: vreduce_ord_fwadd_v8f64:992; CHECK: # %bb.0:993; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma994; CHECK-NEXT: vle32.v v8, (a0)995; CHECK-NEXT: vfmv.s.f v10, fa0996; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma997; CHECK-NEXT: vfwredosum.vs v8, v8, v10998; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma999; CHECK-NEXT: vfmv.f.s fa0, v81000; CHECK-NEXT: ret1001 %v = load <8 x float>, ptr %x1002 %e = fpext <8 x float> %v to <8 x double>1003 %red = call double @llvm.vector.reduce.fadd.v8f64(double %s, <8 x double> %e)1004 ret double %red1005}1006 1007define double @vreduce_fadd_v16f64(ptr %x, double %s) {1008; CHECK-LABEL: vreduce_fadd_v16f64:1009; CHECK: # %bb.0:1010; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma1011; CHECK-NEXT: vle64.v v8, (a0)1012; CHECK-NEXT: vfmv.s.f v16, fa01013; CHECK-NEXT: vfredusum.vs v8, v8, v161014; CHECK-NEXT: vfmv.f.s fa0, v81015; CHECK-NEXT: ret1016 %v = load <16 x double>, ptr %x1017 %red = call reassoc double @llvm.vector.reduce.fadd.v16f64(double %s, <16 x double> %v)1018 ret double %red1019}1020 1021define double @vreduce_ord_fadd_v16f64(ptr %x, double %s) {1022; CHECK-LABEL: vreduce_ord_fadd_v16f64:1023; CHECK: # %bb.0:1024; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma1025; CHECK-NEXT: vle64.v v8, (a0)1026; CHECK-NEXT: vfmv.s.f v16, fa01027; CHECK-NEXT: vfredosum.vs v8, v8, v161028; CHECK-NEXT: vfmv.f.s fa0, v81029; CHECK-NEXT: ret1030 %v = load <16 x double>, ptr %x1031 %red = call double @llvm.vector.reduce.fadd.v16f64(double %s, <16 x double> %v)1032 ret double %red1033}1034 1035define double @vreduce_fwadd_v16f64(ptr %x, double %s) {1036; CHECK-LABEL: vreduce_fwadd_v16f64:1037; CHECK: # %bb.0:1038; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma1039; CHECK-NEXT: vle32.v v8, (a0)1040; CHECK-NEXT: vfmv.s.f v12, fa01041; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma1042; CHECK-NEXT: vfwredusum.vs v8, v8, v121043; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma1044; CHECK-NEXT: vfmv.f.s fa0, v81045; CHECK-NEXT: ret1046 %v = load <16 x float>, ptr %x1047 %e = fpext <16 x float> %v to <16 x double>1048 %red = call reassoc double @llvm.vector.reduce.fadd.v16f64(double %s, <16 x double> %e)1049 ret double %red1050}1051 1052define double @vreduce_ord_fwadd_v16f64(ptr %x, double %s) {1053; CHECK-LABEL: vreduce_ord_fwadd_v16f64:1054; CHECK: # %bb.0:1055; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma1056; CHECK-NEXT: vle32.v v8, (a0)1057; CHECK-NEXT: vfmv.s.f v12, fa01058; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma1059; CHECK-NEXT: vfwredosum.vs v8, v8, v121060; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma1061; CHECK-NEXT: vfmv.f.s fa0, v81062; CHECK-NEXT: ret1063 %v = load <16 x float>, ptr %x1064 %e = fpext <16 x float> %v to <16 x double>1065 %red = call double @llvm.vector.reduce.fadd.v16f64(double %s, <16 x double> %e)1066 ret double %red1067}1068 1069define double @vreduce_fadd_v32f64(ptr %x, double %s) {1070; CHECK-LABEL: vreduce_fadd_v32f64:1071; CHECK: # %bb.0:1072; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma1073; CHECK-NEXT: vle64.v v8, (a0)1074; CHECK-NEXT: addi a0, a0, 1281075; CHECK-NEXT: vle64.v v16, (a0)1076; CHECK-NEXT: vfadd.vv v8, v8, v161077; CHECK-NEXT: vfmv.s.f v16, fa01078; CHECK-NEXT: vfredusum.vs v8, v8, v161079; CHECK-NEXT: vfmv.f.s fa0, v81080; CHECK-NEXT: ret1081 %v = load <32 x double>, ptr %x1082 %red = call reassoc double @llvm.vector.reduce.fadd.v32f64(double %s, <32 x double> %v)1083 ret double %red1084}1085 1086define double @vreduce_ord_fadd_v32f64(ptr %x, double %s) {1087; CHECK-LABEL: vreduce_ord_fadd_v32f64:1088; CHECK: # %bb.0:1089; CHECK-NEXT: addi a1, a0, 1281090; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma1091; CHECK-NEXT: vle64.v v8, (a0)1092; CHECK-NEXT: vle64.v v16, (a1)1093; CHECK-NEXT: vfmv.s.f v24, fa01094; CHECK-NEXT: vfredosum.vs v8, v8, v241095; CHECK-NEXT: vfredosum.vs v8, v16, v81096; CHECK-NEXT: vfmv.f.s fa0, v81097; CHECK-NEXT: ret1098 %v = load <32 x double>, ptr %x1099 %red = call double @llvm.vector.reduce.fadd.v32f64(double %s, <32 x double> %v)1100 ret double %red1101}1102 1103define double @vreduce_fwadd_v32f64(ptr %x, double %s) {1104; CHECK-LABEL: vreduce_fwadd_v32f64:1105; CHECK: # %bb.0:1106; CHECK-NEXT: li a1, 321107; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma1108; CHECK-NEXT: vle32.v v8, (a0)1109; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma1110; CHECK-NEXT: vslidedown.vi v16, v8, 161111; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma1112; CHECK-NEXT: vfwadd.vv v24, v8, v161113; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma1114; CHECK-NEXT: vfmv.s.f v8, fa01115; CHECK-NEXT: vfredusum.vs v8, v24, v81116; CHECK-NEXT: vfmv.f.s fa0, v81117; CHECK-NEXT: ret1118 %v = load <32 x float>, ptr %x1119 %e = fpext <32 x float> %v to <32 x double>1120 %red = call reassoc double @llvm.vector.reduce.fadd.v32f64(double %s, <32 x double> %e)1121 ret double %red1122}1123 1124define double @vreduce_ord_fwadd_v32f64(ptr %x, double %s) {1125; CHECK-LABEL: vreduce_ord_fwadd_v32f64:1126; CHECK: # %bb.0:1127; CHECK-NEXT: li a1, 321128; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma1129; CHECK-NEXT: vle32.v v8, (a0)1130; CHECK-NEXT: vsetivli zero, 16, e64, m1, ta, ma1131; CHECK-NEXT: vfmv.s.f v24, fa01132; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma1133; CHECK-NEXT: vslidedown.vi v16, v8, 161134; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma1135; CHECK-NEXT: vfwredosum.vs v8, v8, v241136; CHECK-NEXT: vfwredosum.vs v8, v16, v81137; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma1138; CHECK-NEXT: vfmv.f.s fa0, v81139; CHECK-NEXT: ret1140 %v = load <32 x float>, ptr %x1141 %e = fpext <32 x float> %v to <32 x double>1142 %red = call double @llvm.vector.reduce.fadd.v32f64(double %s, <32 x double> %e)1143 ret double %red1144}1145 1146define half @vreduce_fmin_v2f16(ptr %x) {1147; CHECK-LABEL: vreduce_fmin_v2f16:1148; CHECK: # %bb.0:1149; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma1150; CHECK-NEXT: vle16.v v8, (a0)1151; CHECK-NEXT: vfredmin.vs v8, v8, v81152; CHECK-NEXT: vfmv.f.s fa0, v81153; CHECK-NEXT: ret1154 %v = load <2 x half>, ptr %x1155 %red = call half @llvm.vector.reduce.fmin.v2f16(<2 x half> %v)1156 ret half %red1157}1158 1159define half @vreduce_fmin_v4f16(ptr %x) {1160; CHECK-LABEL: vreduce_fmin_v4f16:1161; CHECK: # %bb.0:1162; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma1163; CHECK-NEXT: vle16.v v8, (a0)1164; CHECK-NEXT: vfredmin.vs v8, v8, v81165; CHECK-NEXT: vfmv.f.s fa0, v81166; CHECK-NEXT: ret1167 %v = load <4 x half>, ptr %x1168 %red = call half @llvm.vector.reduce.fmin.v4f16(<4 x half> %v)1169 ret half %red1170}1171 1172define half @vreduce_fmin_v4f16_nonans(ptr %x) {1173; CHECK-LABEL: vreduce_fmin_v4f16_nonans:1174; CHECK: # %bb.0:1175; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma1176; CHECK-NEXT: vle16.v v8, (a0)1177; CHECK-NEXT: vfredmin.vs v8, v8, v81178; CHECK-NEXT: vfmv.f.s fa0, v81179; CHECK-NEXT: ret1180 %v = load <4 x half>, ptr %x1181 %red = call nnan half @llvm.vector.reduce.fmin.v4f16(<4 x half> %v)1182 ret half %red1183}1184 1185define half @vreduce_fmin_v4f16_nonans_noinfs(ptr %x) {1186; CHECK-LABEL: vreduce_fmin_v4f16_nonans_noinfs:1187; CHECK: # %bb.0:1188; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma1189; CHECK-NEXT: vle16.v v8, (a0)1190; CHECK-NEXT: vfredmin.vs v8, v8, v81191; CHECK-NEXT: vfmv.f.s fa0, v81192; CHECK-NEXT: ret1193 %v = load <4 x half>, ptr %x1194 %red = call nnan ninf half @llvm.vector.reduce.fmin.v4f16(<4 x half> %v)1195 ret half %red1196}1197 1198define half @vreduce_fmin_v128f16(ptr %x) {1199; CHECK-LABEL: vreduce_fmin_v128f16:1200; CHECK: # %bb.0:1201; CHECK-NEXT: li a1, 641202; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma1203; CHECK-NEXT: vle16.v v8, (a0)1204; CHECK-NEXT: addi a0, a0, 1281205; CHECK-NEXT: vle16.v v16, (a0)1206; CHECK-NEXT: vfmin.vv v8, v8, v161207; CHECK-NEXT: vfredmin.vs v8, v8, v81208; CHECK-NEXT: vfmv.f.s fa0, v81209; CHECK-NEXT: ret1210 %v = load <128 x half>, ptr %x1211 %red = call half @llvm.vector.reduce.fmin.v128f16(<128 x half> %v)1212 ret half %red1213}1214 1215define float @vreduce_fmin_v2f32(ptr %x) {1216; CHECK-LABEL: vreduce_fmin_v2f32:1217; CHECK: # %bb.0:1218; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma1219; CHECK-NEXT: vle32.v v8, (a0)1220; CHECK-NEXT: vfredmin.vs v8, v8, v81221; CHECK-NEXT: vfmv.f.s fa0, v81222; CHECK-NEXT: ret1223 %v = load <2 x float>, ptr %x1224 %red = call float @llvm.vector.reduce.fmin.v2f32(<2 x float> %v)1225 ret float %red1226}1227 1228define float @vreduce_fmin_v4f32(ptr %x) {1229; CHECK-LABEL: vreduce_fmin_v4f32:1230; CHECK: # %bb.0:1231; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma1232; CHECK-NEXT: vle32.v v8, (a0)1233; CHECK-NEXT: vfredmin.vs v8, v8, v81234; CHECK-NEXT: vfmv.f.s fa0, v81235; CHECK-NEXT: ret1236 %v = load <4 x float>, ptr %x1237 %red = call float @llvm.vector.reduce.fmin.v4f32(<4 x float> %v)1238 ret float %red1239}1240 1241define float @vreduce_fmin_v4f32_nonans(ptr %x) {1242; CHECK-LABEL: vreduce_fmin_v4f32_nonans:1243; CHECK: # %bb.0:1244; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma1245; CHECK-NEXT: vle32.v v8, (a0)1246; CHECK-NEXT: vfredmin.vs v8, v8, v81247; CHECK-NEXT: vfmv.f.s fa0, v81248; CHECK-NEXT: ret1249 %v = load <4 x float>, ptr %x1250 %red = call nnan float @llvm.vector.reduce.fmin.v4f32(<4 x float> %v)1251 ret float %red1252}1253 1254define float @vreduce_fmin_v4f32_nonans_noinfs(ptr %x) {1255; CHECK-LABEL: vreduce_fmin_v4f32_nonans_noinfs:1256; CHECK: # %bb.0:1257; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma1258; CHECK-NEXT: vle32.v v8, (a0)1259; CHECK-NEXT: vfredmin.vs v8, v8, v81260; CHECK-NEXT: vfmv.f.s fa0, v81261; CHECK-NEXT: ret1262 %v = load <4 x float>, ptr %x1263 %red = call nnan ninf float @llvm.vector.reduce.fmin.v4f32(<4 x float> %v)1264 ret float %red1265}1266 1267define float @vreduce_fmin_v7f32(ptr %x) {1268; CHECK-LABEL: vreduce_fmin_v7f32:1269; CHECK: # %bb.0:1270; CHECK-NEXT: vsetivli zero, 7, e32, m2, ta, ma1271; CHECK-NEXT: vle32.v v8, (a0)1272; CHECK-NEXT: lui a0, 5232641273; CHECK-NEXT: vmv.s.x v10, a01274; CHECK-NEXT: vfredmin.vs v8, v8, v101275; CHECK-NEXT: vfmv.f.s fa0, v81276; CHECK-NEXT: ret1277 %v = load <7 x float>, ptr %x1278 %red = call float @llvm.vector.reduce.fmin.v7f32(<7 x float> %v)1279 ret float %red1280}1281 1282define float @vreduce_fmin_v128f32(ptr %x) {1283; CHECK-LABEL: vreduce_fmin_v128f32:1284; CHECK: # %bb.0:1285; CHECK-NEXT: li a1, 321286; CHECK-NEXT: addi a2, a0, 3841287; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma1288; CHECK-NEXT: vle32.v v8, (a2)1289; CHECK-NEXT: addi a1, a0, 2561290; CHECK-NEXT: vle32.v v16, (a0)1291; CHECK-NEXT: addi a0, a0, 1281292; CHECK-NEXT: vle32.v v24, (a0)1293; CHECK-NEXT: vle32.v v0, (a1)1294; CHECK-NEXT: vfmin.vv v8, v24, v81295; CHECK-NEXT: vfmin.vv v16, v16, v01296; CHECK-NEXT: vfmin.vv v8, v16, v81297; CHECK-NEXT: vfredmin.vs v8, v8, v81298; CHECK-NEXT: vfmv.f.s fa0, v81299; CHECK-NEXT: ret1300 %v = load <128 x float>, ptr %x1301 %red = call float @llvm.vector.reduce.fmin.v128f32(<128 x float> %v)1302 ret float %red1303}1304 1305define double @vreduce_fmin_v2f64(ptr %x) {1306; CHECK-LABEL: vreduce_fmin_v2f64:1307; CHECK: # %bb.0:1308; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma1309; CHECK-NEXT: vle64.v v8, (a0)1310; CHECK-NEXT: vfredmin.vs v8, v8, v81311; CHECK-NEXT: vfmv.f.s fa0, v81312; CHECK-NEXT: ret1313 %v = load <2 x double>, ptr %x1314 %red = call double @llvm.vector.reduce.fmin.v2f64(<2 x double> %v)1315 ret double %red1316}1317 1318define double @vreduce_fmin_v4f64(ptr %x) {1319; CHECK-LABEL: vreduce_fmin_v4f64:1320; CHECK: # %bb.0:1321; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma1322; CHECK-NEXT: vle64.v v8, (a0)1323; CHECK-NEXT: vfredmin.vs v8, v8, v81324; CHECK-NEXT: vfmv.f.s fa0, v81325; CHECK-NEXT: ret1326 %v = load <4 x double>, ptr %x1327 %red = call double @llvm.vector.reduce.fmin.v4f64(<4 x double> %v)1328 ret double %red1329}1330 1331define double @vreduce_fmin_v4f64_nonans(ptr %x) {1332; CHECK-LABEL: vreduce_fmin_v4f64_nonans:1333; CHECK: # %bb.0:1334; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma1335; CHECK-NEXT: vle64.v v8, (a0)1336; CHECK-NEXT: vfredmin.vs v8, v8, v81337; CHECK-NEXT: vfmv.f.s fa0, v81338; CHECK-NEXT: ret1339 %v = load <4 x double>, ptr %x1340 %red = call nnan double @llvm.vector.reduce.fmin.v4f64(<4 x double> %v)1341 ret double %red1342}1343 1344define double @vreduce_fmin_v4f64_nonans_noinfs(ptr %x) {1345; CHECK-LABEL: vreduce_fmin_v4f64_nonans_noinfs:1346; CHECK: # %bb.0:1347; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma1348; CHECK-NEXT: vle64.v v8, (a0)1349; CHECK-NEXT: vfredmin.vs v8, v8, v81350; CHECK-NEXT: vfmv.f.s fa0, v81351; CHECK-NEXT: ret1352 %v = load <4 x double>, ptr %x1353 %red = call nnan ninf double @llvm.vector.reduce.fmin.v4f64(<4 x double> %v)1354 ret double %red1355}1356 1357define double @vreduce_fmin_v32f64(ptr %x) {1358; CHECK-LABEL: vreduce_fmin_v32f64:1359; CHECK: # %bb.0:1360; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma1361; CHECK-NEXT: vle64.v v8, (a0)1362; CHECK-NEXT: addi a0, a0, 1281363; CHECK-NEXT: vle64.v v16, (a0)1364; CHECK-NEXT: vfmin.vv v8, v8, v161365; CHECK-NEXT: vfredmin.vs v8, v8, v81366; CHECK-NEXT: vfmv.f.s fa0, v81367; CHECK-NEXT: ret1368 %v = load <32 x double>, ptr %x1369 %red = call double @llvm.vector.reduce.fmin.v32f64(<32 x double> %v)1370 ret double %red1371}1372 1373define half @vreduce_fmax_v2f16(ptr %x) {1374; CHECK-LABEL: vreduce_fmax_v2f16:1375; CHECK: # %bb.0:1376; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma1377; CHECK-NEXT: vle16.v v8, (a0)1378; CHECK-NEXT: vfredmax.vs v8, v8, v81379; CHECK-NEXT: vfmv.f.s fa0, v81380; CHECK-NEXT: ret1381 %v = load <2 x half>, ptr %x1382 %red = call half @llvm.vector.reduce.fmax.v2f16(<2 x half> %v)1383 ret half %red1384}1385 1386define half @vreduce_fmax_v4f16(ptr %x) {1387; CHECK-LABEL: vreduce_fmax_v4f16:1388; CHECK: # %bb.0:1389; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma1390; CHECK-NEXT: vle16.v v8, (a0)1391; CHECK-NEXT: vfredmax.vs v8, v8, v81392; CHECK-NEXT: vfmv.f.s fa0, v81393; CHECK-NEXT: ret1394 %v = load <4 x half>, ptr %x1395 %red = call half @llvm.vector.reduce.fmax.v4f16(<4 x half> %v)1396 ret half %red1397}1398 1399define half @vreduce_fmax_v4f16_nonans(ptr %x) {1400; CHECK-LABEL: vreduce_fmax_v4f16_nonans:1401; CHECK: # %bb.0:1402; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma1403; CHECK-NEXT: vle16.v v8, (a0)1404; CHECK-NEXT: vfredmax.vs v8, v8, v81405; CHECK-NEXT: vfmv.f.s fa0, v81406; CHECK-NEXT: ret1407 %v = load <4 x half>, ptr %x1408 %red = call nnan half @llvm.vector.reduce.fmax.v4f16(<4 x half> %v)1409 ret half %red1410}1411 1412define half @vreduce_fmax_v4f16_nonans_noinfs(ptr %x) {1413; CHECK-LABEL: vreduce_fmax_v4f16_nonans_noinfs:1414; CHECK: # %bb.0:1415; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma1416; CHECK-NEXT: vle16.v v8, (a0)1417; CHECK-NEXT: vfredmax.vs v8, v8, v81418; CHECK-NEXT: vfmv.f.s fa0, v81419; CHECK-NEXT: ret1420 %v = load <4 x half>, ptr %x1421 %red = call nnan ninf half @llvm.vector.reduce.fmax.v4f16(<4 x half> %v)1422 ret half %red1423}1424 1425define half @vreduce_fmax_v128f16(ptr %x) {1426; CHECK-LABEL: vreduce_fmax_v128f16:1427; CHECK: # %bb.0:1428; CHECK-NEXT: li a1, 641429; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma1430; CHECK-NEXT: vle16.v v8, (a0)1431; CHECK-NEXT: addi a0, a0, 1281432; CHECK-NEXT: vle16.v v16, (a0)1433; CHECK-NEXT: vfmax.vv v8, v8, v161434; CHECK-NEXT: vfredmax.vs v8, v8, v81435; CHECK-NEXT: vfmv.f.s fa0, v81436; CHECK-NEXT: ret1437 %v = load <128 x half>, ptr %x1438 %red = call half @llvm.vector.reduce.fmax.v128f16(<128 x half> %v)1439 ret half %red1440}1441 1442define float @vreduce_fmax_v2f32(ptr %x) {1443; CHECK-LABEL: vreduce_fmax_v2f32:1444; CHECK: # %bb.0:1445; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma1446; CHECK-NEXT: vle32.v v8, (a0)1447; CHECK-NEXT: vfredmax.vs v8, v8, v81448; CHECK-NEXT: vfmv.f.s fa0, v81449; CHECK-NEXT: ret1450 %v = load <2 x float>, ptr %x1451 %red = call float @llvm.vector.reduce.fmax.v2f32(<2 x float> %v)1452 ret float %red1453}1454 1455define float @vreduce_fmax_v4f32(ptr %x) {1456; CHECK-LABEL: vreduce_fmax_v4f32:1457; CHECK: # %bb.0:1458; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma1459; CHECK-NEXT: vle32.v v8, (a0)1460; CHECK-NEXT: vfredmax.vs v8, v8, v81461; CHECK-NEXT: vfmv.f.s fa0, v81462; CHECK-NEXT: ret1463 %v = load <4 x float>, ptr %x1464 %red = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> %v)1465 ret float %red1466}1467 1468define float @vreduce_fmax_v4f32_nonans(ptr %x) {1469; CHECK-LABEL: vreduce_fmax_v4f32_nonans:1470; CHECK: # %bb.0:1471; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma1472; CHECK-NEXT: vle32.v v8, (a0)1473; CHECK-NEXT: vfredmax.vs v8, v8, v81474; CHECK-NEXT: vfmv.f.s fa0, v81475; CHECK-NEXT: ret1476 %v = load <4 x float>, ptr %x1477 %red = call nnan float @llvm.vector.reduce.fmax.v4f32(<4 x float> %v)1478 ret float %red1479}1480 1481define float @vreduce_fmax_v4f32_nonans_noinfs(ptr %x) {1482; CHECK-LABEL: vreduce_fmax_v4f32_nonans_noinfs:1483; CHECK: # %bb.0:1484; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma1485; CHECK-NEXT: vle32.v v8, (a0)1486; CHECK-NEXT: vfredmax.vs v8, v8, v81487; CHECK-NEXT: vfmv.f.s fa0, v81488; CHECK-NEXT: ret1489 %v = load <4 x float>, ptr %x1490 %red = call nnan ninf float @llvm.vector.reduce.fmax.v4f32(<4 x float> %v)1491 ret float %red1492}1493 1494define float @vreduce_fmax_v7f32(ptr %x) {1495; CHECK-LABEL: vreduce_fmax_v7f32:1496; CHECK: # %bb.0:1497; CHECK-NEXT: vsetivli zero, 7, e32, m2, ta, ma1498; CHECK-NEXT: vle32.v v8, (a0)1499; CHECK-NEXT: lui a0, 10475521500; CHECK-NEXT: vmv.s.x v10, a01501; CHECK-NEXT: vfredmax.vs v8, v8, v101502; CHECK-NEXT: vfmv.f.s fa0, v81503; CHECK-NEXT: ret1504 %v = load <7 x float>, ptr %x1505 %red = call float @llvm.vector.reduce.fmax.v7f32(<7 x float> %v)1506 ret float %red1507}1508 1509define float @vreduce_fmax_v128f32(ptr %x) {1510; CHECK-LABEL: vreduce_fmax_v128f32:1511; CHECK: # %bb.0:1512; CHECK-NEXT: li a1, 321513; CHECK-NEXT: addi a2, a0, 3841514; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma1515; CHECK-NEXT: vle32.v v8, (a2)1516; CHECK-NEXT: addi a1, a0, 2561517; CHECK-NEXT: vle32.v v16, (a0)1518; CHECK-NEXT: addi a0, a0, 1281519; CHECK-NEXT: vle32.v v24, (a0)1520; CHECK-NEXT: vle32.v v0, (a1)1521; CHECK-NEXT: vfmax.vv v8, v24, v81522; CHECK-NEXT: vfmax.vv v16, v16, v01523; CHECK-NEXT: vfmax.vv v8, v16, v81524; CHECK-NEXT: vfredmax.vs v8, v8, v81525; CHECK-NEXT: vfmv.f.s fa0, v81526; CHECK-NEXT: ret1527 %v = load <128 x float>, ptr %x1528 %red = call float @llvm.vector.reduce.fmax.v128f32(<128 x float> %v)1529 ret float %red1530}1531 1532define double @vreduce_fmax_v2f64(ptr %x) {1533; CHECK-LABEL: vreduce_fmax_v2f64:1534; CHECK: # %bb.0:1535; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma1536; CHECK-NEXT: vle64.v v8, (a0)1537; CHECK-NEXT: vfredmax.vs v8, v8, v81538; CHECK-NEXT: vfmv.f.s fa0, v81539; CHECK-NEXT: ret1540 %v = load <2 x double>, ptr %x1541 %red = call double @llvm.vector.reduce.fmax.v2f64(<2 x double> %v)1542 ret double %red1543}1544 1545define double @vreduce_fmax_v4f64(ptr %x) {1546; CHECK-LABEL: vreduce_fmax_v4f64:1547; CHECK: # %bb.0:1548; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma1549; CHECK-NEXT: vle64.v v8, (a0)1550; CHECK-NEXT: vfredmax.vs v8, v8, v81551; CHECK-NEXT: vfmv.f.s fa0, v81552; CHECK-NEXT: ret1553 %v = load <4 x double>, ptr %x1554 %red = call double @llvm.vector.reduce.fmax.v4f64(<4 x double> %v)1555 ret double %red1556}1557 1558define double @vreduce_fmax_v4f64_nonans(ptr %x) {1559; CHECK-LABEL: vreduce_fmax_v4f64_nonans:1560; CHECK: # %bb.0:1561; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma1562; CHECK-NEXT: vle64.v v8, (a0)1563; CHECK-NEXT: vfredmax.vs v8, v8, v81564; CHECK-NEXT: vfmv.f.s fa0, v81565; CHECK-NEXT: ret1566 %v = load <4 x double>, ptr %x1567 %red = call nnan double @llvm.vector.reduce.fmax.v4f64(<4 x double> %v)1568 ret double %red1569}1570 1571define double @vreduce_fmax_v4f64_nonans_noinfs(ptr %x) {1572; CHECK-LABEL: vreduce_fmax_v4f64_nonans_noinfs:1573; CHECK: # %bb.0:1574; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma1575; CHECK-NEXT: vle64.v v8, (a0)1576; CHECK-NEXT: vfredmax.vs v8, v8, v81577; CHECK-NEXT: vfmv.f.s fa0, v81578; CHECK-NEXT: ret1579 %v = load <4 x double>, ptr %x1580 %red = call nnan ninf double @llvm.vector.reduce.fmax.v4f64(<4 x double> %v)1581 ret double %red1582}1583 1584define double @vreduce_fmax_v32f64(ptr %x) {1585; CHECK-LABEL: vreduce_fmax_v32f64:1586; CHECK: # %bb.0:1587; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma1588; CHECK-NEXT: vle64.v v8, (a0)1589; CHECK-NEXT: addi a0, a0, 1281590; CHECK-NEXT: vle64.v v16, (a0)1591; CHECK-NEXT: vfmax.vv v8, v8, v161592; CHECK-NEXT: vfredmax.vs v8, v8, v81593; CHECK-NEXT: vfmv.f.s fa0, v81594; CHECK-NEXT: ret1595 %v = load <32 x double>, ptr %x1596 %red = call double @llvm.vector.reduce.fmax.v32f64(<32 x double> %v)1597 ret double %red1598}1599 1600define float @vreduce_nsz_fadd_v4f32(ptr %x, float %s) {1601; CHECK-LABEL: vreduce_nsz_fadd_v4f32:1602; CHECK: # %bb.0:1603; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma1604; CHECK-NEXT: vle32.v v8, (a0)1605; CHECK-NEXT: vfmv.s.f v9, fa01606; CHECK-NEXT: vfredusum.vs v8, v8, v91607; CHECK-NEXT: vfmv.f.s fa0, v81608; CHECK-NEXT: ret1609 %v = load <4 x float>, ptr %x1610 %red = call reassoc nsz float @llvm.vector.reduce.fadd.v4f32(float %s, <4 x float> %v)1611 ret float %red1612}1613 1614define float @vreduce_fminimum_v2f32(ptr %x) {1615; CHECK-LABEL: vreduce_fminimum_v2f32:1616; CHECK: # %bb.0:1617; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma1618; CHECK-NEXT: vle32.v v8, (a0)1619; CHECK-NEXT: vmfne.vv v9, v8, v81620; CHECK-NEXT: vcpop.m a0, v91621; CHECK-NEXT: beqz a0, .LBB107_21622; CHECK-NEXT: # %bb.1:1623; CHECK-NEXT: lui a0, 5232641624; CHECK-NEXT: fmv.w.x fa0, a01625; CHECK-NEXT: ret1626; CHECK-NEXT: .LBB107_2:1627; CHECK-NEXT: vfredmin.vs v8, v8, v81628; CHECK-NEXT: vfmv.f.s fa0, v81629; CHECK-NEXT: ret1630 %v = load <2 x float>, ptr %x1631 %red = call float @llvm.vector.reduce.fminimum.v2f32(<2 x float> %v)1632 ret float %red1633}1634 1635define float @vreduce_fminimum_v2f32_nonans(ptr %x) {1636; CHECK-LABEL: vreduce_fminimum_v2f32_nonans:1637; CHECK: # %bb.0:1638; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma1639; CHECK-NEXT: vle32.v v8, (a0)1640; CHECK-NEXT: vfredmin.vs v8, v8, v81641; CHECK-NEXT: vfmv.f.s fa0, v81642; CHECK-NEXT: ret1643 %v = load <2 x float>, ptr %x1644 %red = call nnan float @llvm.vector.reduce.fminimum.v2f32(<2 x float> %v)1645 ret float %red1646}1647 1648define float @vreduce_fminimum_v4f32(ptr %x) {1649; CHECK-LABEL: vreduce_fminimum_v4f32:1650; CHECK: # %bb.0:1651; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma1652; CHECK-NEXT: vle32.v v8, (a0)1653; CHECK-NEXT: vmfne.vv v9, v8, v81654; CHECK-NEXT: vcpop.m a0, v91655; CHECK-NEXT: beqz a0, .LBB109_21656; CHECK-NEXT: # %bb.1:1657; CHECK-NEXT: lui a0, 5232641658; CHECK-NEXT: fmv.w.x fa0, a01659; CHECK-NEXT: ret1660; CHECK-NEXT: .LBB109_2:1661; CHECK-NEXT: vfredmin.vs v8, v8, v81662; CHECK-NEXT: vfmv.f.s fa0, v81663; CHECK-NEXT: ret1664 %v = load <4 x float>, ptr %x1665 %red = call float @llvm.vector.reduce.fminimum.v4f32(<4 x float> %v)1666 ret float %red1667}1668 1669define float @vreduce_fminimum_v4f32_nonans(ptr %x) {1670; CHECK-LABEL: vreduce_fminimum_v4f32_nonans:1671; CHECK: # %bb.0:1672; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma1673; CHECK-NEXT: vle32.v v8, (a0)1674; CHECK-NEXT: vfredmin.vs v8, v8, v81675; CHECK-NEXT: vfmv.f.s fa0, v81676; CHECK-NEXT: ret1677 %v = load <4 x float>, ptr %x1678 %red = call nnan float @llvm.vector.reduce.fminimum.v4f32(<4 x float> %v)1679 ret float %red1680}1681 1682define float @vreduce_fminimum_v7f32(ptr %x) {1683; CHECK-LABEL: vreduce_fminimum_v7f32:1684; CHECK: # %bb.0:1685; CHECK-NEXT: vsetivli zero, 7, e32, m2, ta, ma1686; CHECK-NEXT: vle32.v v8, (a0)1687; CHECK-NEXT: vmfne.vv v10, v8, v81688; CHECK-NEXT: vcpop.m a0, v101689; CHECK-NEXT: beqz a0, .LBB111_21690; CHECK-NEXT: # %bb.1:1691; CHECK-NEXT: lui a0, 5232641692; CHECK-NEXT: fmv.w.x fa0, a01693; CHECK-NEXT: ret1694; CHECK-NEXT: .LBB111_2:1695; CHECK-NEXT: lui a0, 5222401696; CHECK-NEXT: vmv.s.x v10, a01697; CHECK-NEXT: vfredmin.vs v8, v8, v101698; CHECK-NEXT: vfmv.f.s fa0, v81699; CHECK-NEXT: ret1700 %v = load <7 x float>, ptr %x1701 %red = call float @llvm.vector.reduce.fminimum.v7f32(<7 x float> %v)1702 ret float %red1703}1704 1705define float @vreduce_fminimum_v7f32_nonans(ptr %x) {1706; CHECK-LABEL: vreduce_fminimum_v7f32_nonans:1707; CHECK: # %bb.0:1708; CHECK-NEXT: vsetivli zero, 7, e32, m2, ta, ma1709; CHECK-NEXT: vle32.v v8, (a0)1710; CHECK-NEXT: lui a0, 5222401711; CHECK-NEXT: vmv.s.x v10, a01712; CHECK-NEXT: vfredmin.vs v8, v8, v101713; CHECK-NEXT: vfmv.f.s fa0, v81714; CHECK-NEXT: ret1715 %v = load <7 x float>, ptr %x1716 %red = call nnan float @llvm.vector.reduce.fminimum.v7f32(<7 x float> %v)1717 ret float %red1718}1719 1720define float @vreduce_fminimum_v8f32(ptr %x) {1721; CHECK-LABEL: vreduce_fminimum_v8f32:1722; CHECK: # %bb.0:1723; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma1724; CHECK-NEXT: vle32.v v8, (a0)1725; CHECK-NEXT: vmfne.vv v10, v8, v81726; CHECK-NEXT: vcpop.m a0, v101727; CHECK-NEXT: beqz a0, .LBB113_21728; CHECK-NEXT: # %bb.1:1729; CHECK-NEXT: lui a0, 5232641730; CHECK-NEXT: fmv.w.x fa0, a01731; CHECK-NEXT: ret1732; CHECK-NEXT: .LBB113_2:1733; CHECK-NEXT: vfredmin.vs v8, v8, v81734; CHECK-NEXT: vfmv.f.s fa0, v81735; CHECK-NEXT: ret1736 %v = load <8 x float>, ptr %x1737 %red = call float @llvm.vector.reduce.fminimum.v8f32(<8 x float> %v)1738 ret float %red1739}1740 1741define float @vreduce_fminimum_v8f32_nonans(ptr %x) {1742; CHECK-LABEL: vreduce_fminimum_v8f32_nonans:1743; CHECK: # %bb.0:1744; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma1745; CHECK-NEXT: vle32.v v8, (a0)1746; CHECK-NEXT: vfredmin.vs v8, v8, v81747; CHECK-NEXT: vfmv.f.s fa0, v81748; CHECK-NEXT: ret1749 %v = load <8 x float>, ptr %x1750 %red = call nnan float @llvm.vector.reduce.fminimum.v8f32(<8 x float> %v)1751 ret float %red1752}1753 1754define float @vreduce_fminimum_v16f32(ptr %x) {1755; CHECK-LABEL: vreduce_fminimum_v16f32:1756; CHECK: # %bb.0:1757; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma1758; CHECK-NEXT: vle32.v v8, (a0)1759; CHECK-NEXT: vmfne.vv v12, v8, v81760; CHECK-NEXT: vcpop.m a0, v121761; CHECK-NEXT: beqz a0, .LBB115_21762; CHECK-NEXT: # %bb.1:1763; CHECK-NEXT: lui a0, 5232641764; CHECK-NEXT: fmv.w.x fa0, a01765; CHECK-NEXT: ret1766; CHECK-NEXT: .LBB115_2:1767; CHECK-NEXT: vfredmin.vs v8, v8, v81768; CHECK-NEXT: vfmv.f.s fa0, v81769; CHECK-NEXT: ret1770 %v = load <16 x float>, ptr %x1771 %red = call float @llvm.vector.reduce.fminimum.v16f32(<16 x float> %v)1772 ret float %red1773}1774 1775define float @vreduce_fminimum_v16f32_nonans(ptr %x) {1776; CHECK-LABEL: vreduce_fminimum_v16f32_nonans:1777; CHECK: # %bb.0:1778; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma1779; CHECK-NEXT: vle32.v v8, (a0)1780; CHECK-NEXT: vfredmin.vs v8, v8, v81781; CHECK-NEXT: vfmv.f.s fa0, v81782; CHECK-NEXT: ret1783 %v = load <16 x float>, ptr %x1784 %red = call nnan float @llvm.vector.reduce.fminimum.v16f32(<16 x float> %v)1785 ret float %red1786}1787 1788define float @vreduce_fminimum_v32f32(ptr %x) {1789; CHECK-LABEL: vreduce_fminimum_v32f32:1790; CHECK: # %bb.0:1791; CHECK-NEXT: li a1, 321792; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma1793; CHECK-NEXT: vle32.v v8, (a0)1794; CHECK-NEXT: vmfne.vv v16, v8, v81795; CHECK-NEXT: vcpop.m a0, v161796; CHECK-NEXT: beqz a0, .LBB117_21797; CHECK-NEXT: # %bb.1:1798; CHECK-NEXT: lui a0, 5232641799; CHECK-NEXT: fmv.w.x fa0, a01800; CHECK-NEXT: ret1801; CHECK-NEXT: .LBB117_2:1802; CHECK-NEXT: vfredmin.vs v8, v8, v81803; CHECK-NEXT: vfmv.f.s fa0, v81804; CHECK-NEXT: ret1805 %v = load <32 x float>, ptr %x1806 %red = call float @llvm.vector.reduce.fminimum.v32f32(<32 x float> %v)1807 ret float %red1808}1809 1810define float @vreduce_fminimum_v32f32_nonans(ptr %x) {1811; CHECK-LABEL: vreduce_fminimum_v32f32_nonans:1812; CHECK: # %bb.0:1813; CHECK-NEXT: li a1, 321814; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma1815; CHECK-NEXT: vle32.v v8, (a0)1816; CHECK-NEXT: vfredmin.vs v8, v8, v81817; CHECK-NEXT: vfmv.f.s fa0, v81818; CHECK-NEXT: ret1819 %v = load <32 x float>, ptr %x1820 %red = call nnan float @llvm.vector.reduce.fminimum.v32f32(<32 x float> %v)1821 ret float %red1822}1823 1824define float @vreduce_fminimum_v64f32(ptr %x) {1825; CHECK-LABEL: vreduce_fminimum_v64f32:1826; CHECK: # %bb.0:1827; CHECK-NEXT: addi a1, a0, 1281828; CHECK-NEXT: li a2, 321829; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma1830; CHECK-NEXT: vle32.v v16, (a0)1831; CHECK-NEXT: vle32.v v24, (a1)1832; CHECK-NEXT: vmfeq.vv v0, v16, v161833; CHECK-NEXT: vmfeq.vv v7, v24, v241834; CHECK-NEXT: vmerge.vvm v8, v16, v24, v01835; CHECK-NEXT: vmv1r.v v0, v71836; CHECK-NEXT: vmerge.vvm v16, v24, v16, v01837; CHECK-NEXT: vfmin.vv v8, v16, v81838; CHECK-NEXT: vmfne.vv v16, v8, v81839; CHECK-NEXT: vcpop.m a0, v161840; CHECK-NEXT: beqz a0, .LBB119_21841; CHECK-NEXT: # %bb.1:1842; CHECK-NEXT: lui a0, 5232641843; CHECK-NEXT: fmv.w.x fa0, a01844; CHECK-NEXT: ret1845; CHECK-NEXT: .LBB119_2:1846; CHECK-NEXT: vfredmin.vs v8, v8, v81847; CHECK-NEXT: vfmv.f.s fa0, v81848; CHECK-NEXT: ret1849 %v = load <64 x float>, ptr %x1850 %red = call float @llvm.vector.reduce.fminimum.v64f32(<64 x float> %v)1851 ret float %red1852}1853 1854define float @vreduce_fminimum_v64f32_nonans(ptr %x) {1855; CHECK-LABEL: vreduce_fminimum_v64f32_nonans:1856; CHECK: # %bb.0:1857; CHECK-NEXT: li a1, 321858; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma1859; CHECK-NEXT: vle32.v v8, (a0)1860; CHECK-NEXT: addi a0, a0, 1281861; CHECK-NEXT: vle32.v v16, (a0)1862; CHECK-NEXT: vfmin.vv v8, v8, v161863; CHECK-NEXT: vfredmin.vs v8, v8, v81864; CHECK-NEXT: vfmv.f.s fa0, v81865; CHECK-NEXT: ret1866 %v = load <64 x float>, ptr %x1867 %red = call nnan float @llvm.vector.reduce.fminimum.v64f32(<64 x float> %v)1868 ret float %red1869}1870 1871define float @vreduce_fminimum_v128f32(ptr %x) {1872; CHECK-LABEL: vreduce_fminimum_v128f32:1873; CHECK: # %bb.0:1874; CHECK-NEXT: addi sp, sp, -161875; CHECK-NEXT: .cfi_def_cfa_offset 161876; CHECK-NEXT: csrr a1, vlenb1877; CHECK-NEXT: slli a1, a1, 41878; CHECK-NEXT: sub sp, sp, a11879; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb1880; CHECK-NEXT: li a1, 321881; CHECK-NEXT: addi a2, a0, 1281882; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma1883; CHECK-NEXT: vle32.v v24, (a2)1884; CHECK-NEXT: addi a1, a0, 3841885; CHECK-NEXT: vle32.v v16, (a1)1886; CHECK-NEXT: addi a1, a0, 2561887; CHECK-NEXT: vle32.v v8, (a0)1888; CHECK-NEXT: csrr a0, vlenb1889; CHECK-NEXT: slli a0, a0, 31890; CHECK-NEXT: add a0, sp, a01891; CHECK-NEXT: addi a0, a0, 161892; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill1893; CHECK-NEXT: vmfeq.vv v0, v24, v241894; CHECK-NEXT: vmfeq.vv v7, v16, v161895; CHECK-NEXT: vmerge.vvm v8, v24, v16, v01896; CHECK-NEXT: addi a0, sp, 161897; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill1898; CHECK-NEXT: vle32.v v8, (a1)1899; CHECK-NEXT: vmv1r.v v0, v71900; CHECK-NEXT: vmerge.vvm v16, v16, v24, v01901; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload1902; CHECK-NEXT: vfmin.vv v24, v16, v241903; CHECK-NEXT: csrr a0, vlenb1904; CHECK-NEXT: slli a0, a0, 31905; CHECK-NEXT: add a0, sp, a01906; CHECK-NEXT: addi a0, a0, 161907; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload1908; CHECK-NEXT: vmfeq.vv v0, v16, v161909; CHECK-NEXT: vmfeq.vv v7, v8, v81910; CHECK-NEXT: csrr a0, vlenb1911; CHECK-NEXT: slli a0, a0, 31912; CHECK-NEXT: add a0, sp, a01913; CHECK-NEXT: addi a0, a0, 161914; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload1915; CHECK-NEXT: vmerge.vvm v16, v16, v8, v01916; CHECK-NEXT: addi a0, sp, 161917; CHECK-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill1918; CHECK-NEXT: vmv1r.v v0, v71919; CHECK-NEXT: csrr a0, vlenb1920; CHECK-NEXT: slli a0, a0, 31921; CHECK-NEXT: add a0, sp, a01922; CHECK-NEXT: addi a0, a0, 161923; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload1924; CHECK-NEXT: vmerge.vvm v8, v8, v16, v01925; CHECK-NEXT: addi a0, sp, 161926; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload1927; CHECK-NEXT: vfmin.vv v16, v8, v161928; CHECK-NEXT: vmfeq.vv v0, v16, v161929; CHECK-NEXT: vmfeq.vv v7, v24, v241930; CHECK-NEXT: vmerge.vvm v8, v16, v24, v01931; CHECK-NEXT: vmv1r.v v0, v71932; CHECK-NEXT: vmerge.vvm v16, v24, v16, v01933; CHECK-NEXT: vfmin.vv v8, v16, v81934; CHECK-NEXT: vmfne.vv v16, v8, v81935; CHECK-NEXT: vcpop.m a0, v161936; CHECK-NEXT: beqz a0, .LBB121_21937; CHECK-NEXT: # %bb.1:1938; CHECK-NEXT: lui a0, 5232641939; CHECK-NEXT: fmv.w.x fa0, a01940; CHECK-NEXT: j .LBB121_31941; CHECK-NEXT: .LBB121_2:1942; CHECK-NEXT: vfredmin.vs v8, v8, v81943; CHECK-NEXT: vfmv.f.s fa0, v81944; CHECK-NEXT: .LBB121_3:1945; CHECK-NEXT: csrr a0, vlenb1946; CHECK-NEXT: slli a0, a0, 41947; CHECK-NEXT: add sp, sp, a01948; CHECK-NEXT: .cfi_def_cfa sp, 161949; CHECK-NEXT: addi sp, sp, 161950; CHECK-NEXT: .cfi_def_cfa_offset 01951; CHECK-NEXT: ret1952 %v = load <128 x float>, ptr %x1953 %red = call float @llvm.vector.reduce.fminimum.v128f32(<128 x float> %v)1954 ret float %red1955}1956 1957define float @vreduce_fminimum_v128f32_nonans(ptr %x) {1958; CHECK-LABEL: vreduce_fminimum_v128f32_nonans:1959; CHECK: # %bb.0:1960; CHECK-NEXT: li a1, 321961; CHECK-NEXT: addi a2, a0, 3841962; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma1963; CHECK-NEXT: vle32.v v8, (a2)1964; CHECK-NEXT: addi a1, a0, 2561965; CHECK-NEXT: vle32.v v16, (a0)1966; CHECK-NEXT: addi a0, a0, 1281967; CHECK-NEXT: vle32.v v24, (a0)1968; CHECK-NEXT: vle32.v v0, (a1)1969; CHECK-NEXT: vfmin.vv v8, v24, v81970; CHECK-NEXT: vfmin.vv v16, v16, v01971; CHECK-NEXT: vfmin.vv v8, v16, v81972; CHECK-NEXT: vfredmin.vs v8, v8, v81973; CHECK-NEXT: vfmv.f.s fa0, v81974; CHECK-NEXT: ret1975 %v = load <128 x float>, ptr %x1976 %red = call nnan float @llvm.vector.reduce.fminimum.v128f32(<128 x float> %v)1977 ret float %red1978}1979 1980define double @vreduce_fminimum_v2f64(ptr %x) {1981; RV32-LABEL: vreduce_fminimum_v2f64:1982; RV32: # %bb.0:1983; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma1984; RV32-NEXT: vle64.v v8, (a0)1985; RV32-NEXT: vmfne.vv v9, v8, v81986; RV32-NEXT: vcpop.m a0, v91987; RV32-NEXT: beqz a0, .LBB123_21988; RV32-NEXT: # %bb.1:1989; RV32-NEXT: lui a0, %hi(.LCPI123_0)1990; RV32-NEXT: fld fa0, %lo(.LCPI123_0)(a0)1991; RV32-NEXT: ret1992; RV32-NEXT: .LBB123_2:1993; RV32-NEXT: vfredmin.vs v8, v8, v81994; RV32-NEXT: vfmv.f.s fa0, v81995; RV32-NEXT: ret1996;1997; RV64-LABEL: vreduce_fminimum_v2f64:1998; RV64: # %bb.0:1999; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma2000; RV64-NEXT: vle64.v v8, (a0)2001; RV64-NEXT: vmfne.vv v9, v8, v82002; RV64-NEXT: vcpop.m a0, v92003; RV64-NEXT: beqz a0, .LBB123_22004; RV64-NEXT: # %bb.1:2005; RV64-NEXT: lui a0, 40952006; RV64-NEXT: slli a0, a0, 392007; RV64-NEXT: fmv.d.x fa0, a02008; RV64-NEXT: ret2009; RV64-NEXT: .LBB123_2:2010; RV64-NEXT: vfredmin.vs v8, v8, v82011; RV64-NEXT: vfmv.f.s fa0, v82012; RV64-NEXT: ret2013 %v = load <2 x double>, ptr %x2014 %red = call double @llvm.vector.reduce.fminimum.v2f64(<2 x double> %v)2015 ret double %red2016}2017 2018define double @vreduce_fminimum_v2f64_nonans(ptr %x) {2019; CHECK-LABEL: vreduce_fminimum_v2f64_nonans:2020; CHECK: # %bb.0:2021; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma2022; CHECK-NEXT: vle64.v v8, (a0)2023; CHECK-NEXT: vfredmin.vs v8, v8, v82024; CHECK-NEXT: vfmv.f.s fa0, v82025; CHECK-NEXT: ret2026 %v = load <2 x double>, ptr %x2027 %red = call nnan double @llvm.vector.reduce.fminimum.v2f64(<2 x double> %v)2028 ret double %red2029}2030 2031define double @vreduce_fminimum_v4f64(ptr %x) {2032; RV32-LABEL: vreduce_fminimum_v4f64:2033; RV32: # %bb.0:2034; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma2035; RV32-NEXT: vle64.v v8, (a0)2036; RV32-NEXT: vmfne.vv v10, v8, v82037; RV32-NEXT: vcpop.m a0, v102038; RV32-NEXT: beqz a0, .LBB125_22039; RV32-NEXT: # %bb.1:2040; RV32-NEXT: lui a0, %hi(.LCPI125_0)2041; RV32-NEXT: fld fa0, %lo(.LCPI125_0)(a0)2042; RV32-NEXT: ret2043; RV32-NEXT: .LBB125_2:2044; RV32-NEXT: vfredmin.vs v8, v8, v82045; RV32-NEXT: vfmv.f.s fa0, v82046; RV32-NEXT: ret2047;2048; RV64-LABEL: vreduce_fminimum_v4f64:2049; RV64: # %bb.0:2050; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma2051; RV64-NEXT: vle64.v v8, (a0)2052; RV64-NEXT: vmfne.vv v10, v8, v82053; RV64-NEXT: vcpop.m a0, v102054; RV64-NEXT: beqz a0, .LBB125_22055; RV64-NEXT: # %bb.1:2056; RV64-NEXT: lui a0, 40952057; RV64-NEXT: slli a0, a0, 392058; RV64-NEXT: fmv.d.x fa0, a02059; RV64-NEXT: ret2060; RV64-NEXT: .LBB125_2:2061; RV64-NEXT: vfredmin.vs v8, v8, v82062; RV64-NEXT: vfmv.f.s fa0, v82063; RV64-NEXT: ret2064 %v = load <4 x double>, ptr %x2065 %red = call double @llvm.vector.reduce.fminimum.v4f64(<4 x double> %v)2066 ret double %red2067}2068 2069define double @vreduce_fminimum_v4f64_nonans(ptr %x) {2070; CHECK-LABEL: vreduce_fminimum_v4f64_nonans:2071; CHECK: # %bb.0:2072; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma2073; CHECK-NEXT: vle64.v v8, (a0)2074; CHECK-NEXT: vfredmin.vs v8, v8, v82075; CHECK-NEXT: vfmv.f.s fa0, v82076; CHECK-NEXT: ret2077 %v = load <4 x double>, ptr %x2078 %red = call nnan double @llvm.vector.reduce.fminimum.v4f64(<4 x double> %v)2079 ret double %red2080}2081 2082define double @vreduce_fminimum_v8f64(ptr %x) {2083; RV32-LABEL: vreduce_fminimum_v8f64:2084; RV32: # %bb.0:2085; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma2086; RV32-NEXT: vle64.v v8, (a0)2087; RV32-NEXT: vmfne.vv v12, v8, v82088; RV32-NEXT: vcpop.m a0, v122089; RV32-NEXT: beqz a0, .LBB127_22090; RV32-NEXT: # %bb.1:2091; RV32-NEXT: lui a0, %hi(.LCPI127_0)2092; RV32-NEXT: fld fa0, %lo(.LCPI127_0)(a0)2093; RV32-NEXT: ret2094; RV32-NEXT: .LBB127_2:2095; RV32-NEXT: vfredmin.vs v8, v8, v82096; RV32-NEXT: vfmv.f.s fa0, v82097; RV32-NEXT: ret2098;2099; RV64-LABEL: vreduce_fminimum_v8f64:2100; RV64: # %bb.0:2101; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma2102; RV64-NEXT: vle64.v v8, (a0)2103; RV64-NEXT: vmfne.vv v12, v8, v82104; RV64-NEXT: vcpop.m a0, v122105; RV64-NEXT: beqz a0, .LBB127_22106; RV64-NEXT: # %bb.1:2107; RV64-NEXT: lui a0, 40952108; RV64-NEXT: slli a0, a0, 392109; RV64-NEXT: fmv.d.x fa0, a02110; RV64-NEXT: ret2111; RV64-NEXT: .LBB127_2:2112; RV64-NEXT: vfredmin.vs v8, v8, v82113; RV64-NEXT: vfmv.f.s fa0, v82114; RV64-NEXT: ret2115 %v = load <8 x double>, ptr %x2116 %red = call double @llvm.vector.reduce.fminimum.v8f64(<8 x double> %v)2117 ret double %red2118}2119 2120define double @vreduce_fminimum_v8f64_nonans(ptr %x) {2121; CHECK-LABEL: vreduce_fminimum_v8f64_nonans:2122; CHECK: # %bb.0:2123; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma2124; CHECK-NEXT: vle64.v v8, (a0)2125; CHECK-NEXT: vfredmin.vs v8, v8, v82126; CHECK-NEXT: vfmv.f.s fa0, v82127; CHECK-NEXT: ret2128 %v = load <8 x double>, ptr %x2129 %red = call nnan double @llvm.vector.reduce.fminimum.v8f64(<8 x double> %v)2130 ret double %red2131}2132 2133define double @vreduce_fminimum_v16f64(ptr %x) {2134; RV32-LABEL: vreduce_fminimum_v16f64:2135; RV32: # %bb.0:2136; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma2137; RV32-NEXT: vle64.v v8, (a0)2138; RV32-NEXT: vmfne.vv v16, v8, v82139; RV32-NEXT: vcpop.m a0, v162140; RV32-NEXT: beqz a0, .LBB129_22141; RV32-NEXT: # %bb.1:2142; RV32-NEXT: lui a0, %hi(.LCPI129_0)2143; RV32-NEXT: fld fa0, %lo(.LCPI129_0)(a0)2144; RV32-NEXT: ret2145; RV32-NEXT: .LBB129_2:2146; RV32-NEXT: vfredmin.vs v8, v8, v82147; RV32-NEXT: vfmv.f.s fa0, v82148; RV32-NEXT: ret2149;2150; RV64-LABEL: vreduce_fminimum_v16f64:2151; RV64: # %bb.0:2152; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma2153; RV64-NEXT: vle64.v v8, (a0)2154; RV64-NEXT: vmfne.vv v16, v8, v82155; RV64-NEXT: vcpop.m a0, v162156; RV64-NEXT: beqz a0, .LBB129_22157; RV64-NEXT: # %bb.1:2158; RV64-NEXT: lui a0, 40952159; RV64-NEXT: slli a0, a0, 392160; RV64-NEXT: fmv.d.x fa0, a02161; RV64-NEXT: ret2162; RV64-NEXT: .LBB129_2:2163; RV64-NEXT: vfredmin.vs v8, v8, v82164; RV64-NEXT: vfmv.f.s fa0, v82165; RV64-NEXT: ret2166 %v = load <16 x double>, ptr %x2167 %red = call double @llvm.vector.reduce.fminimum.v16f64(<16 x double> %v)2168 ret double %red2169}2170 2171define double @vreduce_fminimum_v16f64_nonans(ptr %x) {2172; CHECK-LABEL: vreduce_fminimum_v16f64_nonans:2173; CHECK: # %bb.0:2174; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma2175; CHECK-NEXT: vle64.v v8, (a0)2176; CHECK-NEXT: vfredmin.vs v8, v8, v82177; CHECK-NEXT: vfmv.f.s fa0, v82178; CHECK-NEXT: ret2179 %v = load <16 x double>, ptr %x2180 %red = call nnan double @llvm.vector.reduce.fminimum.v16f64(<16 x double> %v)2181 ret double %red2182}2183 2184define double @vreduce_fminimum_v32f64(ptr %x) {2185; RV32-LABEL: vreduce_fminimum_v32f64:2186; RV32: # %bb.0:2187; RV32-NEXT: addi a1, a0, 1282188; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma2189; RV32-NEXT: vle64.v v16, (a0)2190; RV32-NEXT: vle64.v v24, (a1)2191; RV32-NEXT: vmfeq.vv v0, v16, v162192; RV32-NEXT: vmfeq.vv v7, v24, v242193; RV32-NEXT: vmerge.vvm v8, v16, v24, v02194; RV32-NEXT: vmv1r.v v0, v72195; RV32-NEXT: vmerge.vvm v16, v24, v16, v02196; RV32-NEXT: vfmin.vv v8, v16, v82197; RV32-NEXT: vmfne.vv v16, v8, v82198; RV32-NEXT: vcpop.m a0, v162199; RV32-NEXT: beqz a0, .LBB131_22200; RV32-NEXT: # %bb.1:2201; RV32-NEXT: lui a0, %hi(.LCPI131_0)2202; RV32-NEXT: fld fa0, %lo(.LCPI131_0)(a0)2203; RV32-NEXT: ret2204; RV32-NEXT: .LBB131_2:2205; RV32-NEXT: vfredmin.vs v8, v8, v82206; RV32-NEXT: vfmv.f.s fa0, v82207; RV32-NEXT: ret2208;2209; RV64-LABEL: vreduce_fminimum_v32f64:2210; RV64: # %bb.0:2211; RV64-NEXT: addi a1, a0, 1282212; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma2213; RV64-NEXT: vle64.v v16, (a0)2214; RV64-NEXT: vle64.v v24, (a1)2215; RV64-NEXT: vmfeq.vv v0, v16, v162216; RV64-NEXT: vmfeq.vv v7, v24, v242217; RV64-NEXT: vmerge.vvm v8, v16, v24, v02218; RV64-NEXT: vmv1r.v v0, v72219; RV64-NEXT: vmerge.vvm v16, v24, v16, v02220; RV64-NEXT: vfmin.vv v8, v16, v82221; RV64-NEXT: vmfne.vv v16, v8, v82222; RV64-NEXT: vcpop.m a0, v162223; RV64-NEXT: beqz a0, .LBB131_22224; RV64-NEXT: # %bb.1:2225; RV64-NEXT: lui a0, 40952226; RV64-NEXT: slli a0, a0, 392227; RV64-NEXT: fmv.d.x fa0, a02228; RV64-NEXT: ret2229; RV64-NEXT: .LBB131_2:2230; RV64-NEXT: vfredmin.vs v8, v8, v82231; RV64-NEXT: vfmv.f.s fa0, v82232; RV64-NEXT: ret2233 %v = load <32 x double>, ptr %x2234 %red = call double @llvm.vector.reduce.fminimum.v32f64(<32 x double> %v)2235 ret double %red2236}2237 2238define double @vreduce_fminimum_v32f64_nonans(ptr %x) {2239; CHECK-LABEL: vreduce_fminimum_v32f64_nonans:2240; CHECK: # %bb.0:2241; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma2242; CHECK-NEXT: vle64.v v8, (a0)2243; CHECK-NEXT: addi a0, a0, 1282244; CHECK-NEXT: vle64.v v16, (a0)2245; CHECK-NEXT: vfmin.vv v8, v8, v162246; CHECK-NEXT: vfredmin.vs v8, v8, v82247; CHECK-NEXT: vfmv.f.s fa0, v82248; CHECK-NEXT: ret2249 %v = load <32 x double>, ptr %x2250 %red = call nnan double @llvm.vector.reduce.fminimum.v32f64(<32 x double> %v)2251 ret double %red2252}2253 2254define double @vreduce_fminimum_v64f64(ptr %x) {2255; RV32-LABEL: vreduce_fminimum_v64f64:2256; RV32: # %bb.0:2257; RV32-NEXT: addi sp, sp, -162258; RV32-NEXT: .cfi_def_cfa_offset 162259; RV32-NEXT: csrr a1, vlenb2260; RV32-NEXT: slli a1, a1, 42261; RV32-NEXT: sub sp, sp, a12262; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb2263; RV32-NEXT: addi a1, a0, 1282264; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma2265; RV32-NEXT: vle64.v v24, (a1)2266; RV32-NEXT: addi a1, a0, 3842267; RV32-NEXT: vle64.v v16, (a1)2268; RV32-NEXT: addi a1, a0, 2562269; RV32-NEXT: vle64.v v8, (a0)2270; RV32-NEXT: csrr a0, vlenb2271; RV32-NEXT: slli a0, a0, 32272; RV32-NEXT: add a0, sp, a02273; RV32-NEXT: addi a0, a0, 162274; RV32-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill2275; RV32-NEXT: vmfeq.vv v0, v24, v242276; RV32-NEXT: vmfeq.vv v7, v16, v162277; RV32-NEXT: vmerge.vvm v8, v24, v16, v02278; RV32-NEXT: addi a0, sp, 162279; RV32-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill2280; RV32-NEXT: vle64.v v8, (a1)2281; RV32-NEXT: vmv1r.v v0, v72282; RV32-NEXT: vmerge.vvm v16, v16, v24, v02283; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload2284; RV32-NEXT: vfmin.vv v24, v16, v242285; RV32-NEXT: csrr a0, vlenb2286; RV32-NEXT: slli a0, a0, 32287; RV32-NEXT: add a0, sp, a02288; RV32-NEXT: addi a0, a0, 162289; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload2290; RV32-NEXT: vmfeq.vv v0, v16, v162291; RV32-NEXT: vmfeq.vv v7, v8, v82292; RV32-NEXT: csrr a0, vlenb2293; RV32-NEXT: slli a0, a0, 32294; RV32-NEXT: add a0, sp, a02295; RV32-NEXT: addi a0, a0, 162296; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload2297; RV32-NEXT: vmerge.vvm v16, v16, v8, v02298; RV32-NEXT: addi a0, sp, 162299; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill2300; RV32-NEXT: vmv1r.v v0, v72301; RV32-NEXT: csrr a0, vlenb2302; RV32-NEXT: slli a0, a0, 32303; RV32-NEXT: add a0, sp, a02304; RV32-NEXT: addi a0, a0, 162305; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload2306; RV32-NEXT: vmerge.vvm v8, v8, v16, v02307; RV32-NEXT: addi a0, sp, 162308; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload2309; RV32-NEXT: vfmin.vv v16, v8, v162310; RV32-NEXT: vmfeq.vv v0, v16, v162311; RV32-NEXT: vmfeq.vv v7, v24, v242312; RV32-NEXT: vmerge.vvm v8, v16, v24, v02313; RV32-NEXT: vmv1r.v v0, v72314; RV32-NEXT: vmerge.vvm v16, v24, v16, v02315; RV32-NEXT: vfmin.vv v8, v16, v82316; RV32-NEXT: vmfne.vv v16, v8, v82317; RV32-NEXT: vcpop.m a0, v162318; RV32-NEXT: beqz a0, .LBB133_22319; RV32-NEXT: # %bb.1:2320; RV32-NEXT: lui a0, %hi(.LCPI133_0)2321; RV32-NEXT: fld fa0, %lo(.LCPI133_0)(a0)2322; RV32-NEXT: j .LBB133_32323; RV32-NEXT: .LBB133_2:2324; RV32-NEXT: vfredmin.vs v8, v8, v82325; RV32-NEXT: vfmv.f.s fa0, v82326; RV32-NEXT: .LBB133_3:2327; RV32-NEXT: csrr a0, vlenb2328; RV32-NEXT: slli a0, a0, 42329; RV32-NEXT: add sp, sp, a02330; RV32-NEXT: .cfi_def_cfa sp, 162331; RV32-NEXT: addi sp, sp, 162332; RV32-NEXT: .cfi_def_cfa_offset 02333; RV32-NEXT: ret2334;2335; RV64-LABEL: vreduce_fminimum_v64f64:2336; RV64: # %bb.0:2337; RV64-NEXT: addi sp, sp, -162338; RV64-NEXT: .cfi_def_cfa_offset 162339; RV64-NEXT: csrr a1, vlenb2340; RV64-NEXT: slli a1, a1, 42341; RV64-NEXT: sub sp, sp, a12342; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb2343; RV64-NEXT: addi a1, a0, 1282344; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma2345; RV64-NEXT: vle64.v v24, (a1)2346; RV64-NEXT: addi a1, a0, 3842347; RV64-NEXT: vle64.v v16, (a1)2348; RV64-NEXT: addi a1, a0, 2562349; RV64-NEXT: vle64.v v8, (a0)2350; RV64-NEXT: csrr a0, vlenb2351; RV64-NEXT: slli a0, a0, 32352; RV64-NEXT: add a0, sp, a02353; RV64-NEXT: addi a0, a0, 162354; RV64-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill2355; RV64-NEXT: vmfeq.vv v0, v24, v242356; RV64-NEXT: vmfeq.vv v7, v16, v162357; RV64-NEXT: vmerge.vvm v8, v24, v16, v02358; RV64-NEXT: addi a0, sp, 162359; RV64-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill2360; RV64-NEXT: vle64.v v8, (a1)2361; RV64-NEXT: vmv1r.v v0, v72362; RV64-NEXT: vmerge.vvm v16, v16, v24, v02363; RV64-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload2364; RV64-NEXT: vfmin.vv v24, v16, v242365; RV64-NEXT: csrr a0, vlenb2366; RV64-NEXT: slli a0, a0, 32367; RV64-NEXT: add a0, sp, a02368; RV64-NEXT: addi a0, a0, 162369; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload2370; RV64-NEXT: vmfeq.vv v0, v16, v162371; RV64-NEXT: vmfeq.vv v7, v8, v82372; RV64-NEXT: csrr a0, vlenb2373; RV64-NEXT: slli a0, a0, 32374; RV64-NEXT: add a0, sp, a02375; RV64-NEXT: addi a0, a0, 162376; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload2377; RV64-NEXT: vmerge.vvm v16, v16, v8, v02378; RV64-NEXT: addi a0, sp, 162379; RV64-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill2380; RV64-NEXT: vmv1r.v v0, v72381; RV64-NEXT: csrr a0, vlenb2382; RV64-NEXT: slli a0, a0, 32383; RV64-NEXT: add a0, sp, a02384; RV64-NEXT: addi a0, a0, 162385; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload2386; RV64-NEXT: vmerge.vvm v8, v8, v16, v02387; RV64-NEXT: addi a0, sp, 162388; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload2389; RV64-NEXT: vfmin.vv v16, v8, v162390; RV64-NEXT: vmfeq.vv v0, v16, v162391; RV64-NEXT: vmfeq.vv v7, v24, v242392; RV64-NEXT: vmerge.vvm v8, v16, v24, v02393; RV64-NEXT: vmv1r.v v0, v72394; RV64-NEXT: vmerge.vvm v16, v24, v16, v02395; RV64-NEXT: vfmin.vv v8, v16, v82396; RV64-NEXT: vmfne.vv v16, v8, v82397; RV64-NEXT: vcpop.m a0, v162398; RV64-NEXT: beqz a0, .LBB133_22399; RV64-NEXT: # %bb.1:2400; RV64-NEXT: lui a0, 40952401; RV64-NEXT: slli a0, a0, 392402; RV64-NEXT: fmv.d.x fa0, a02403; RV64-NEXT: j .LBB133_32404; RV64-NEXT: .LBB133_2:2405; RV64-NEXT: vfredmin.vs v8, v8, v82406; RV64-NEXT: vfmv.f.s fa0, v82407; RV64-NEXT: .LBB133_3:2408; RV64-NEXT: csrr a0, vlenb2409; RV64-NEXT: slli a0, a0, 42410; RV64-NEXT: add sp, sp, a02411; RV64-NEXT: .cfi_def_cfa sp, 162412; RV64-NEXT: addi sp, sp, 162413; RV64-NEXT: .cfi_def_cfa_offset 02414; RV64-NEXT: ret2415 %v = load <64 x double>, ptr %x2416 %red = call double @llvm.vector.reduce.fminimum.v64f64(<64 x double> %v)2417 ret double %red2418}2419 2420define double @vreduce_fminimum_v64f64_nonans(ptr %x) {2421; CHECK-LABEL: vreduce_fminimum_v64f64_nonans:2422; CHECK: # %bb.0:2423; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma2424; CHECK-NEXT: vle64.v v8, (a0)2425; CHECK-NEXT: addi a1, a0, 3842426; CHECK-NEXT: vle64.v v16, (a1)2427; CHECK-NEXT: addi a1, a0, 2562428; CHECK-NEXT: addi a0, a0, 1282429; CHECK-NEXT: vle64.v v24, (a0)2430; CHECK-NEXT: vle64.v v0, (a1)2431; CHECK-NEXT: vfmin.vv v16, v24, v162432; CHECK-NEXT: vfmin.vv v8, v8, v02433; CHECK-NEXT: vfmin.vv v8, v8, v162434; CHECK-NEXT: vfredmin.vs v8, v8, v82435; CHECK-NEXT: vfmv.f.s fa0, v82436; CHECK-NEXT: ret2437 %v = load <64 x double>, ptr %x2438 %red = call nnan double @llvm.vector.reduce.fminimum.v64f64(<64 x double> %v)2439 ret double %red2440}2441 2442define float @vreduce_fmaximum_v2f32(ptr %x) {2443; CHECK-LABEL: vreduce_fmaximum_v2f32:2444; CHECK: # %bb.0:2445; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma2446; CHECK-NEXT: vle32.v v8, (a0)2447; CHECK-NEXT: vmfne.vv v9, v8, v82448; CHECK-NEXT: vcpop.m a0, v92449; CHECK-NEXT: beqz a0, .LBB135_22450; CHECK-NEXT: # %bb.1:2451; CHECK-NEXT: lui a0, 5232642452; CHECK-NEXT: fmv.w.x fa0, a02453; CHECK-NEXT: ret2454; CHECK-NEXT: .LBB135_2:2455; CHECK-NEXT: vfredmax.vs v8, v8, v82456; CHECK-NEXT: vfmv.f.s fa0, v82457; CHECK-NEXT: ret2458 %v = load <2 x float>, ptr %x2459 %red = call float @llvm.vector.reduce.fmaximum.v2f32(<2 x float> %v)2460 ret float %red2461}2462 2463define float @vreduce_fmaximum_v2f32_nonans(ptr %x) {2464; CHECK-LABEL: vreduce_fmaximum_v2f32_nonans:2465; CHECK: # %bb.0:2466; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma2467; CHECK-NEXT: vle32.v v8, (a0)2468; CHECK-NEXT: vfredmax.vs v8, v8, v82469; CHECK-NEXT: vfmv.f.s fa0, v82470; CHECK-NEXT: ret2471 %v = load <2 x float>, ptr %x2472 %red = call nnan float @llvm.vector.reduce.fmaximum.v2f32(<2 x float> %v)2473 ret float %red2474}2475 2476define float @vreduce_fmaximum_v4f32(ptr %x) {2477; CHECK-LABEL: vreduce_fmaximum_v4f32:2478; CHECK: # %bb.0:2479; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma2480; CHECK-NEXT: vle32.v v8, (a0)2481; CHECK-NEXT: vmfne.vv v9, v8, v82482; CHECK-NEXT: vcpop.m a0, v92483; CHECK-NEXT: beqz a0, .LBB137_22484; CHECK-NEXT: # %bb.1:2485; CHECK-NEXT: lui a0, 5232642486; CHECK-NEXT: fmv.w.x fa0, a02487; CHECK-NEXT: ret2488; CHECK-NEXT: .LBB137_2:2489; CHECK-NEXT: vfredmax.vs v8, v8, v82490; CHECK-NEXT: vfmv.f.s fa0, v82491; CHECK-NEXT: ret2492 %v = load <4 x float>, ptr %x2493 %red = call float @llvm.vector.reduce.fmaximum.v4f32(<4 x float> %v)2494 ret float %red2495}2496 2497define float @vreduce_fmaximum_v4f32_nonans(ptr %x) {2498; CHECK-LABEL: vreduce_fmaximum_v4f32_nonans:2499; CHECK: # %bb.0:2500; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma2501; CHECK-NEXT: vle32.v v8, (a0)2502; CHECK-NEXT: vfredmax.vs v8, v8, v82503; CHECK-NEXT: vfmv.f.s fa0, v82504; CHECK-NEXT: ret2505 %v = load <4 x float>, ptr %x2506 %red = call nnan float @llvm.vector.reduce.fmaximum.v4f32(<4 x float> %v)2507 ret float %red2508}2509 2510define float @vreduce_fmaximum_v7f32(ptr %x) {2511; CHECK-LABEL: vreduce_fmaximum_v7f32:2512; CHECK: # %bb.0:2513; CHECK-NEXT: vsetivli zero, 7, e32, m2, ta, ma2514; CHECK-NEXT: vle32.v v8, (a0)2515; CHECK-NEXT: vmfne.vv v10, v8, v82516; CHECK-NEXT: vcpop.m a0, v102517; CHECK-NEXT: beqz a0, .LBB139_22518; CHECK-NEXT: # %bb.1:2519; CHECK-NEXT: lui a0, 5232642520; CHECK-NEXT: fmv.w.x fa0, a02521; CHECK-NEXT: ret2522; CHECK-NEXT: .LBB139_2:2523; CHECK-NEXT: lui a0, 10465282524; CHECK-NEXT: vmv.s.x v10, a02525; CHECK-NEXT: vfredmax.vs v8, v8, v102526; CHECK-NEXT: vfmv.f.s fa0, v82527; CHECK-NEXT: ret2528 %v = load <7 x float>, ptr %x2529 %red = call float @llvm.vector.reduce.fmaximum.v7f32(<7 x float> %v)2530 ret float %red2531}2532 2533define float @vreduce_fmaximum_v7f32_nonans(ptr %x) {2534; CHECK-LABEL: vreduce_fmaximum_v7f32_nonans:2535; CHECK: # %bb.0:2536; CHECK-NEXT: vsetivli zero, 7, e32, m2, ta, ma2537; CHECK-NEXT: vle32.v v8, (a0)2538; CHECK-NEXT: lui a0, 10465282539; CHECK-NEXT: vmv.s.x v10, a02540; CHECK-NEXT: vfredmax.vs v8, v8, v102541; CHECK-NEXT: vfmv.f.s fa0, v82542; CHECK-NEXT: ret2543 %v = load <7 x float>, ptr %x2544 %red = call nnan float @llvm.vector.reduce.fmaximum.v7f32(<7 x float> %v)2545 ret float %red2546}2547 2548define float @vreduce_fmaximum_v8f32(ptr %x) {2549; CHECK-LABEL: vreduce_fmaximum_v8f32:2550; CHECK: # %bb.0:2551; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma2552; CHECK-NEXT: vle32.v v8, (a0)2553; CHECK-NEXT: vmfne.vv v10, v8, v82554; CHECK-NEXT: vcpop.m a0, v102555; CHECK-NEXT: beqz a0, .LBB141_22556; CHECK-NEXT: # %bb.1:2557; CHECK-NEXT: lui a0, 5232642558; CHECK-NEXT: fmv.w.x fa0, a02559; CHECK-NEXT: ret2560; CHECK-NEXT: .LBB141_2:2561; CHECK-NEXT: vfredmax.vs v8, v8, v82562; CHECK-NEXT: vfmv.f.s fa0, v82563; CHECK-NEXT: ret2564 %v = load <8 x float>, ptr %x2565 %red = call float @llvm.vector.reduce.fmaximum.v8f32(<8 x float> %v)2566 ret float %red2567}2568 2569define float @vreduce_fmaximum_v8f32_nonans(ptr %x) {2570; CHECK-LABEL: vreduce_fmaximum_v8f32_nonans:2571; CHECK: # %bb.0:2572; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma2573; CHECK-NEXT: vle32.v v8, (a0)2574; CHECK-NEXT: vfredmax.vs v8, v8, v82575; CHECK-NEXT: vfmv.f.s fa0, v82576; CHECK-NEXT: ret2577 %v = load <8 x float>, ptr %x2578 %red = call nnan float @llvm.vector.reduce.fmaximum.v8f32(<8 x float> %v)2579 ret float %red2580}2581 2582define float @vreduce_fmaximum_v16f32(ptr %x) {2583; CHECK-LABEL: vreduce_fmaximum_v16f32:2584; CHECK: # %bb.0:2585; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma2586; CHECK-NEXT: vle32.v v8, (a0)2587; CHECK-NEXT: vmfne.vv v12, v8, v82588; CHECK-NEXT: vcpop.m a0, v122589; CHECK-NEXT: beqz a0, .LBB143_22590; CHECK-NEXT: # %bb.1:2591; CHECK-NEXT: lui a0, 5232642592; CHECK-NEXT: fmv.w.x fa0, a02593; CHECK-NEXT: ret2594; CHECK-NEXT: .LBB143_2:2595; CHECK-NEXT: vfredmax.vs v8, v8, v82596; CHECK-NEXT: vfmv.f.s fa0, v82597; CHECK-NEXT: ret2598 %v = load <16 x float>, ptr %x2599 %red = call float @llvm.vector.reduce.fmaximum.v16f32(<16 x float> %v)2600 ret float %red2601}2602 2603define float @vreduce_fmaximum_v16f32_nonans(ptr %x) {2604; CHECK-LABEL: vreduce_fmaximum_v16f32_nonans:2605; CHECK: # %bb.0:2606; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma2607; CHECK-NEXT: vle32.v v8, (a0)2608; CHECK-NEXT: vfredmax.vs v8, v8, v82609; CHECK-NEXT: vfmv.f.s fa0, v82610; CHECK-NEXT: ret2611 %v = load <16 x float>, ptr %x2612 %red = call nnan float @llvm.vector.reduce.fmaximum.v16f32(<16 x float> %v)2613 ret float %red2614}2615 2616define float @vreduce_fmaximum_v32f32(ptr %x) {2617; CHECK-LABEL: vreduce_fmaximum_v32f32:2618; CHECK: # %bb.0:2619; CHECK-NEXT: li a1, 322620; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma2621; CHECK-NEXT: vle32.v v8, (a0)2622; CHECK-NEXT: vmfne.vv v16, v8, v82623; CHECK-NEXT: vcpop.m a0, v162624; CHECK-NEXT: beqz a0, .LBB145_22625; CHECK-NEXT: # %bb.1:2626; CHECK-NEXT: lui a0, 5232642627; CHECK-NEXT: fmv.w.x fa0, a02628; CHECK-NEXT: ret2629; CHECK-NEXT: .LBB145_2:2630; CHECK-NEXT: vfredmax.vs v8, v8, v82631; CHECK-NEXT: vfmv.f.s fa0, v82632; CHECK-NEXT: ret2633 %v = load <32 x float>, ptr %x2634 %red = call float @llvm.vector.reduce.fmaximum.v32f32(<32 x float> %v)2635 ret float %red2636}2637 2638define float @vreduce_fmaximum_v32f32_nonans(ptr %x) {2639; CHECK-LABEL: vreduce_fmaximum_v32f32_nonans:2640; CHECK: # %bb.0:2641; CHECK-NEXT: li a1, 322642; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma2643; CHECK-NEXT: vle32.v v8, (a0)2644; CHECK-NEXT: vfredmax.vs v8, v8, v82645; CHECK-NEXT: vfmv.f.s fa0, v82646; CHECK-NEXT: ret2647 %v = load <32 x float>, ptr %x2648 %red = call nnan float @llvm.vector.reduce.fmaximum.v32f32(<32 x float> %v)2649 ret float %red2650}2651 2652define float @vreduce_fmaximum_v64f32(ptr %x) {2653; CHECK-LABEL: vreduce_fmaximum_v64f32:2654; CHECK: # %bb.0:2655; CHECK-NEXT: addi a1, a0, 1282656; CHECK-NEXT: li a2, 322657; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma2658; CHECK-NEXT: vle32.v v16, (a0)2659; CHECK-NEXT: vle32.v v24, (a1)2660; CHECK-NEXT: vmfeq.vv v0, v16, v162661; CHECK-NEXT: vmfeq.vv v7, v24, v242662; CHECK-NEXT: vmerge.vvm v8, v16, v24, v02663; CHECK-NEXT: vmv1r.v v0, v72664; CHECK-NEXT: vmerge.vvm v16, v24, v16, v02665; CHECK-NEXT: vfmax.vv v8, v16, v82666; CHECK-NEXT: vmfne.vv v16, v8, v82667; CHECK-NEXT: vcpop.m a0, v162668; CHECK-NEXT: beqz a0, .LBB147_22669; CHECK-NEXT: # %bb.1:2670; CHECK-NEXT: lui a0, 5232642671; CHECK-NEXT: fmv.w.x fa0, a02672; CHECK-NEXT: ret2673; CHECK-NEXT: .LBB147_2:2674; CHECK-NEXT: vfredmax.vs v8, v8, v82675; CHECK-NEXT: vfmv.f.s fa0, v82676; CHECK-NEXT: ret2677 %v = load <64 x float>, ptr %x2678 %red = call float @llvm.vector.reduce.fmaximum.v64f32(<64 x float> %v)2679 ret float %red2680}2681 2682define float @vreduce_fmaximum_v64f32_nonans(ptr %x) {2683; CHECK-LABEL: vreduce_fmaximum_v64f32_nonans:2684; CHECK: # %bb.0:2685; CHECK-NEXT: li a1, 322686; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma2687; CHECK-NEXT: vle32.v v8, (a0)2688; CHECK-NEXT: addi a0, a0, 1282689; CHECK-NEXT: vle32.v v16, (a0)2690; CHECK-NEXT: vfmax.vv v8, v8, v162691; CHECK-NEXT: vfredmax.vs v8, v8, v82692; CHECK-NEXT: vfmv.f.s fa0, v82693; CHECK-NEXT: ret2694 %v = load <64 x float>, ptr %x2695 %red = call nnan float @llvm.vector.reduce.fmaximum.v64f32(<64 x float> %v)2696 ret float %red2697}2698 2699define float @vreduce_fmaximum_v128f32(ptr %x) {2700; CHECK-LABEL: vreduce_fmaximum_v128f32:2701; CHECK: # %bb.0:2702; CHECK-NEXT: addi sp, sp, -162703; CHECK-NEXT: .cfi_def_cfa_offset 162704; CHECK-NEXT: csrr a1, vlenb2705; CHECK-NEXT: slli a1, a1, 42706; CHECK-NEXT: sub sp, sp, a12707; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb2708; CHECK-NEXT: li a1, 322709; CHECK-NEXT: addi a2, a0, 1282710; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma2711; CHECK-NEXT: vle32.v v24, (a2)2712; CHECK-NEXT: addi a1, a0, 3842713; CHECK-NEXT: vle32.v v16, (a1)2714; CHECK-NEXT: addi a1, a0, 2562715; CHECK-NEXT: vle32.v v8, (a0)2716; CHECK-NEXT: csrr a0, vlenb2717; CHECK-NEXT: slli a0, a0, 32718; CHECK-NEXT: add a0, sp, a02719; CHECK-NEXT: addi a0, a0, 162720; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill2721; CHECK-NEXT: vmfeq.vv v0, v24, v242722; CHECK-NEXT: vmfeq.vv v7, v16, v162723; CHECK-NEXT: vmerge.vvm v8, v24, v16, v02724; CHECK-NEXT: addi a0, sp, 162725; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill2726; CHECK-NEXT: vle32.v v8, (a1)2727; CHECK-NEXT: vmv1r.v v0, v72728; CHECK-NEXT: vmerge.vvm v16, v16, v24, v02729; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload2730; CHECK-NEXT: vfmax.vv v24, v16, v242731; CHECK-NEXT: csrr a0, vlenb2732; CHECK-NEXT: slli a0, a0, 32733; CHECK-NEXT: add a0, sp, a02734; CHECK-NEXT: addi a0, a0, 162735; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload2736; CHECK-NEXT: vmfeq.vv v0, v16, v162737; CHECK-NEXT: vmfeq.vv v7, v8, v82738; CHECK-NEXT: csrr a0, vlenb2739; CHECK-NEXT: slli a0, a0, 32740; CHECK-NEXT: add a0, sp, a02741; CHECK-NEXT: addi a0, a0, 162742; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload2743; CHECK-NEXT: vmerge.vvm v16, v16, v8, v02744; CHECK-NEXT: addi a0, sp, 162745; CHECK-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill2746; CHECK-NEXT: vmv1r.v v0, v72747; CHECK-NEXT: csrr a0, vlenb2748; CHECK-NEXT: slli a0, a0, 32749; CHECK-NEXT: add a0, sp, a02750; CHECK-NEXT: addi a0, a0, 162751; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload2752; CHECK-NEXT: vmerge.vvm v8, v8, v16, v02753; CHECK-NEXT: addi a0, sp, 162754; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload2755; CHECK-NEXT: vfmax.vv v16, v8, v162756; CHECK-NEXT: vmfeq.vv v0, v16, v162757; CHECK-NEXT: vmfeq.vv v7, v24, v242758; CHECK-NEXT: vmerge.vvm v8, v16, v24, v02759; CHECK-NEXT: vmv1r.v v0, v72760; CHECK-NEXT: vmerge.vvm v16, v24, v16, v02761; CHECK-NEXT: vfmax.vv v8, v16, v82762; CHECK-NEXT: vmfne.vv v16, v8, v82763; CHECK-NEXT: vcpop.m a0, v162764; CHECK-NEXT: beqz a0, .LBB149_22765; CHECK-NEXT: # %bb.1:2766; CHECK-NEXT: lui a0, 5232642767; CHECK-NEXT: fmv.w.x fa0, a02768; CHECK-NEXT: j .LBB149_32769; CHECK-NEXT: .LBB149_2:2770; CHECK-NEXT: vfredmax.vs v8, v8, v82771; CHECK-NEXT: vfmv.f.s fa0, v82772; CHECK-NEXT: .LBB149_3:2773; CHECK-NEXT: csrr a0, vlenb2774; CHECK-NEXT: slli a0, a0, 42775; CHECK-NEXT: add sp, sp, a02776; CHECK-NEXT: .cfi_def_cfa sp, 162777; CHECK-NEXT: addi sp, sp, 162778; CHECK-NEXT: .cfi_def_cfa_offset 02779; CHECK-NEXT: ret2780 %v = load <128 x float>, ptr %x2781 %red = call float @llvm.vector.reduce.fmaximum.v128f32(<128 x float> %v)2782 ret float %red2783}2784 2785define float @vreduce_fmaximum_v128f32_nonans(ptr %x) {2786; CHECK-LABEL: vreduce_fmaximum_v128f32_nonans:2787; CHECK: # %bb.0:2788; CHECK-NEXT: li a1, 322789; CHECK-NEXT: addi a2, a0, 3842790; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma2791; CHECK-NEXT: vle32.v v8, (a2)2792; CHECK-NEXT: addi a1, a0, 2562793; CHECK-NEXT: vle32.v v16, (a0)2794; CHECK-NEXT: addi a0, a0, 1282795; CHECK-NEXT: vle32.v v24, (a0)2796; CHECK-NEXT: vle32.v v0, (a1)2797; CHECK-NEXT: vfmax.vv v8, v24, v82798; CHECK-NEXT: vfmax.vv v16, v16, v02799; CHECK-NEXT: vfmax.vv v8, v16, v82800; CHECK-NEXT: vfredmax.vs v8, v8, v82801; CHECK-NEXT: vfmv.f.s fa0, v82802; CHECK-NEXT: ret2803 %v = load <128 x float>, ptr %x2804 %red = call nnan float @llvm.vector.reduce.fmaximum.v128f32(<128 x float> %v)2805 ret float %red2806}2807 2808define double @vreduce_fmaximum_v2f64(ptr %x) {2809; RV32-LABEL: vreduce_fmaximum_v2f64:2810; RV32: # %bb.0:2811; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma2812; RV32-NEXT: vle64.v v8, (a0)2813; RV32-NEXT: vmfne.vv v9, v8, v82814; RV32-NEXT: vcpop.m a0, v92815; RV32-NEXT: beqz a0, .LBB151_22816; RV32-NEXT: # %bb.1:2817; RV32-NEXT: lui a0, %hi(.LCPI151_0)2818; RV32-NEXT: fld fa0, %lo(.LCPI151_0)(a0)2819; RV32-NEXT: ret2820; RV32-NEXT: .LBB151_2:2821; RV32-NEXT: vfredmax.vs v8, v8, v82822; RV32-NEXT: vfmv.f.s fa0, v82823; RV32-NEXT: ret2824;2825; RV64-LABEL: vreduce_fmaximum_v2f64:2826; RV64: # %bb.0:2827; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma2828; RV64-NEXT: vle64.v v8, (a0)2829; RV64-NEXT: vmfne.vv v9, v8, v82830; RV64-NEXT: vcpop.m a0, v92831; RV64-NEXT: beqz a0, .LBB151_22832; RV64-NEXT: # %bb.1:2833; RV64-NEXT: lui a0, 40952834; RV64-NEXT: slli a0, a0, 392835; RV64-NEXT: fmv.d.x fa0, a02836; RV64-NEXT: ret2837; RV64-NEXT: .LBB151_2:2838; RV64-NEXT: vfredmax.vs v8, v8, v82839; RV64-NEXT: vfmv.f.s fa0, v82840; RV64-NEXT: ret2841 %v = load <2 x double>, ptr %x2842 %red = call double @llvm.vector.reduce.fmaximum.v2f64(<2 x double> %v)2843 ret double %red2844}2845 2846define double @vreduce_fmaximum_v2f64_nonans(ptr %x) {2847; CHECK-LABEL: vreduce_fmaximum_v2f64_nonans:2848; CHECK: # %bb.0:2849; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma2850; CHECK-NEXT: vle64.v v8, (a0)2851; CHECK-NEXT: vfredmax.vs v8, v8, v82852; CHECK-NEXT: vfmv.f.s fa0, v82853; CHECK-NEXT: ret2854 %v = load <2 x double>, ptr %x2855 %red = call nnan double @llvm.vector.reduce.fmaximum.v2f64(<2 x double> %v)2856 ret double %red2857}2858 2859define double @vreduce_fmaximum_v4f64(ptr %x) {2860; RV32-LABEL: vreduce_fmaximum_v4f64:2861; RV32: # %bb.0:2862; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma2863; RV32-NEXT: vle64.v v8, (a0)2864; RV32-NEXT: vmfne.vv v10, v8, v82865; RV32-NEXT: vcpop.m a0, v102866; RV32-NEXT: beqz a0, .LBB153_22867; RV32-NEXT: # %bb.1:2868; RV32-NEXT: lui a0, %hi(.LCPI153_0)2869; RV32-NEXT: fld fa0, %lo(.LCPI153_0)(a0)2870; RV32-NEXT: ret2871; RV32-NEXT: .LBB153_2:2872; RV32-NEXT: vfredmax.vs v8, v8, v82873; RV32-NEXT: vfmv.f.s fa0, v82874; RV32-NEXT: ret2875;2876; RV64-LABEL: vreduce_fmaximum_v4f64:2877; RV64: # %bb.0:2878; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma2879; RV64-NEXT: vle64.v v8, (a0)2880; RV64-NEXT: vmfne.vv v10, v8, v82881; RV64-NEXT: vcpop.m a0, v102882; RV64-NEXT: beqz a0, .LBB153_22883; RV64-NEXT: # %bb.1:2884; RV64-NEXT: lui a0, 40952885; RV64-NEXT: slli a0, a0, 392886; RV64-NEXT: fmv.d.x fa0, a02887; RV64-NEXT: ret2888; RV64-NEXT: .LBB153_2:2889; RV64-NEXT: vfredmax.vs v8, v8, v82890; RV64-NEXT: vfmv.f.s fa0, v82891; RV64-NEXT: ret2892 %v = load <4 x double>, ptr %x2893 %red = call double @llvm.vector.reduce.fmaximum.v4f64(<4 x double> %v)2894 ret double %red2895}2896 2897define double @vreduce_fmaximum_v4f64_nonans(ptr %x) {2898; CHECK-LABEL: vreduce_fmaximum_v4f64_nonans:2899; CHECK: # %bb.0:2900; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma2901; CHECK-NEXT: vle64.v v8, (a0)2902; CHECK-NEXT: vfredmax.vs v8, v8, v82903; CHECK-NEXT: vfmv.f.s fa0, v82904; CHECK-NEXT: ret2905 %v = load <4 x double>, ptr %x2906 %red = call nnan double @llvm.vector.reduce.fmaximum.v4f64(<4 x double> %v)2907 ret double %red2908}2909 2910define double @vreduce_fmaximum_v8f64(ptr %x) {2911; RV32-LABEL: vreduce_fmaximum_v8f64:2912; RV32: # %bb.0:2913; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma2914; RV32-NEXT: vle64.v v8, (a0)2915; RV32-NEXT: vmfne.vv v12, v8, v82916; RV32-NEXT: vcpop.m a0, v122917; RV32-NEXT: beqz a0, .LBB155_22918; RV32-NEXT: # %bb.1:2919; RV32-NEXT: lui a0, %hi(.LCPI155_0)2920; RV32-NEXT: fld fa0, %lo(.LCPI155_0)(a0)2921; RV32-NEXT: ret2922; RV32-NEXT: .LBB155_2:2923; RV32-NEXT: vfredmax.vs v8, v8, v82924; RV32-NEXT: vfmv.f.s fa0, v82925; RV32-NEXT: ret2926;2927; RV64-LABEL: vreduce_fmaximum_v8f64:2928; RV64: # %bb.0:2929; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma2930; RV64-NEXT: vle64.v v8, (a0)2931; RV64-NEXT: vmfne.vv v12, v8, v82932; RV64-NEXT: vcpop.m a0, v122933; RV64-NEXT: beqz a0, .LBB155_22934; RV64-NEXT: # %bb.1:2935; RV64-NEXT: lui a0, 40952936; RV64-NEXT: slli a0, a0, 392937; RV64-NEXT: fmv.d.x fa0, a02938; RV64-NEXT: ret2939; RV64-NEXT: .LBB155_2:2940; RV64-NEXT: vfredmax.vs v8, v8, v82941; RV64-NEXT: vfmv.f.s fa0, v82942; RV64-NEXT: ret2943 %v = load <8 x double>, ptr %x2944 %red = call double @llvm.vector.reduce.fmaximum.v8f64(<8 x double> %v)2945 ret double %red2946}2947 2948define double @vreduce_fmaximum_v8f64_nonans(ptr %x) {2949; CHECK-LABEL: vreduce_fmaximum_v8f64_nonans:2950; CHECK: # %bb.0:2951; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma2952; CHECK-NEXT: vle64.v v8, (a0)2953; CHECK-NEXT: vfredmax.vs v8, v8, v82954; CHECK-NEXT: vfmv.f.s fa0, v82955; CHECK-NEXT: ret2956 %v = load <8 x double>, ptr %x2957 %red = call nnan double @llvm.vector.reduce.fmaximum.v8f64(<8 x double> %v)2958 ret double %red2959}2960 2961define double @vreduce_fmaximum_v16f64(ptr %x) {2962; RV32-LABEL: vreduce_fmaximum_v16f64:2963; RV32: # %bb.0:2964; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma2965; RV32-NEXT: vle64.v v8, (a0)2966; RV32-NEXT: vmfne.vv v16, v8, v82967; RV32-NEXT: vcpop.m a0, v162968; RV32-NEXT: beqz a0, .LBB157_22969; RV32-NEXT: # %bb.1:2970; RV32-NEXT: lui a0, %hi(.LCPI157_0)2971; RV32-NEXT: fld fa0, %lo(.LCPI157_0)(a0)2972; RV32-NEXT: ret2973; RV32-NEXT: .LBB157_2:2974; RV32-NEXT: vfredmax.vs v8, v8, v82975; RV32-NEXT: vfmv.f.s fa0, v82976; RV32-NEXT: ret2977;2978; RV64-LABEL: vreduce_fmaximum_v16f64:2979; RV64: # %bb.0:2980; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma2981; RV64-NEXT: vle64.v v8, (a0)2982; RV64-NEXT: vmfne.vv v16, v8, v82983; RV64-NEXT: vcpop.m a0, v162984; RV64-NEXT: beqz a0, .LBB157_22985; RV64-NEXT: # %bb.1:2986; RV64-NEXT: lui a0, 40952987; RV64-NEXT: slli a0, a0, 392988; RV64-NEXT: fmv.d.x fa0, a02989; RV64-NEXT: ret2990; RV64-NEXT: .LBB157_2:2991; RV64-NEXT: vfredmax.vs v8, v8, v82992; RV64-NEXT: vfmv.f.s fa0, v82993; RV64-NEXT: ret2994 %v = load <16 x double>, ptr %x2995 %red = call double @llvm.vector.reduce.fmaximum.v16f64(<16 x double> %v)2996 ret double %red2997}2998 2999define double @vreduce_fmaximum_v16f64_nonans(ptr %x) {3000; CHECK-LABEL: vreduce_fmaximum_v16f64_nonans:3001; CHECK: # %bb.0:3002; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma3003; CHECK-NEXT: vle64.v v8, (a0)3004; CHECK-NEXT: vfredmax.vs v8, v8, v83005; CHECK-NEXT: vfmv.f.s fa0, v83006; CHECK-NEXT: ret3007 %v = load <16 x double>, ptr %x3008 %red = call nnan double @llvm.vector.reduce.fmaximum.v16f64(<16 x double> %v)3009 ret double %red3010}3011 3012define double @vreduce_fmaximum_v32f64(ptr %x) {3013; RV32-LABEL: vreduce_fmaximum_v32f64:3014; RV32: # %bb.0:3015; RV32-NEXT: addi a1, a0, 1283016; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma3017; RV32-NEXT: vle64.v v16, (a0)3018; RV32-NEXT: vle64.v v24, (a1)3019; RV32-NEXT: vmfeq.vv v0, v16, v163020; RV32-NEXT: vmfeq.vv v7, v24, v243021; RV32-NEXT: vmerge.vvm v8, v16, v24, v03022; RV32-NEXT: vmv1r.v v0, v73023; RV32-NEXT: vmerge.vvm v16, v24, v16, v03024; RV32-NEXT: vfmax.vv v8, v16, v83025; RV32-NEXT: vmfne.vv v16, v8, v83026; RV32-NEXT: vcpop.m a0, v163027; RV32-NEXT: beqz a0, .LBB159_23028; RV32-NEXT: # %bb.1:3029; RV32-NEXT: lui a0, %hi(.LCPI159_0)3030; RV32-NEXT: fld fa0, %lo(.LCPI159_0)(a0)3031; RV32-NEXT: ret3032; RV32-NEXT: .LBB159_2:3033; RV32-NEXT: vfredmax.vs v8, v8, v83034; RV32-NEXT: vfmv.f.s fa0, v83035; RV32-NEXT: ret3036;3037; RV64-LABEL: vreduce_fmaximum_v32f64:3038; RV64: # %bb.0:3039; RV64-NEXT: addi a1, a0, 1283040; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma3041; RV64-NEXT: vle64.v v16, (a0)3042; RV64-NEXT: vle64.v v24, (a1)3043; RV64-NEXT: vmfeq.vv v0, v16, v163044; RV64-NEXT: vmfeq.vv v7, v24, v243045; RV64-NEXT: vmerge.vvm v8, v16, v24, v03046; RV64-NEXT: vmv1r.v v0, v73047; RV64-NEXT: vmerge.vvm v16, v24, v16, v03048; RV64-NEXT: vfmax.vv v8, v16, v83049; RV64-NEXT: vmfne.vv v16, v8, v83050; RV64-NEXT: vcpop.m a0, v163051; RV64-NEXT: beqz a0, .LBB159_23052; RV64-NEXT: # %bb.1:3053; RV64-NEXT: lui a0, 40953054; RV64-NEXT: slli a0, a0, 393055; RV64-NEXT: fmv.d.x fa0, a03056; RV64-NEXT: ret3057; RV64-NEXT: .LBB159_2:3058; RV64-NEXT: vfredmax.vs v8, v8, v83059; RV64-NEXT: vfmv.f.s fa0, v83060; RV64-NEXT: ret3061 %v = load <32 x double>, ptr %x3062 %red = call double @llvm.vector.reduce.fmaximum.v32f64(<32 x double> %v)3063 ret double %red3064}3065 3066define double @vreduce_fmaximum_v32f64_nonans(ptr %x) {3067; CHECK-LABEL: vreduce_fmaximum_v32f64_nonans:3068; CHECK: # %bb.0:3069; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma3070; CHECK-NEXT: vle64.v v8, (a0)3071; CHECK-NEXT: addi a0, a0, 1283072; CHECK-NEXT: vle64.v v16, (a0)3073; CHECK-NEXT: vfmax.vv v8, v8, v163074; CHECK-NEXT: vfredmax.vs v8, v8, v83075; CHECK-NEXT: vfmv.f.s fa0, v83076; CHECK-NEXT: ret3077 %v = load <32 x double>, ptr %x3078 %red = call nnan double @llvm.vector.reduce.fmaximum.v32f64(<32 x double> %v)3079 ret double %red3080}3081 3082define double @vreduce_fmaximum_v64f64(ptr %x) {3083; RV32-LABEL: vreduce_fmaximum_v64f64:3084; RV32: # %bb.0:3085; RV32-NEXT: addi sp, sp, -163086; RV32-NEXT: .cfi_def_cfa_offset 163087; RV32-NEXT: csrr a1, vlenb3088; RV32-NEXT: slli a1, a1, 43089; RV32-NEXT: sub sp, sp, a13090; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb3091; RV32-NEXT: addi a1, a0, 1283092; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma3093; RV32-NEXT: vle64.v v24, (a1)3094; RV32-NEXT: addi a1, a0, 3843095; RV32-NEXT: vle64.v v16, (a1)3096; RV32-NEXT: addi a1, a0, 2563097; RV32-NEXT: vle64.v v8, (a0)3098; RV32-NEXT: csrr a0, vlenb3099; RV32-NEXT: slli a0, a0, 33100; RV32-NEXT: add a0, sp, a03101; RV32-NEXT: addi a0, a0, 163102; RV32-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill3103; RV32-NEXT: vmfeq.vv v0, v24, v243104; RV32-NEXT: vmfeq.vv v7, v16, v163105; RV32-NEXT: vmerge.vvm v8, v24, v16, v03106; RV32-NEXT: addi a0, sp, 163107; RV32-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill3108; RV32-NEXT: vle64.v v8, (a1)3109; RV32-NEXT: vmv1r.v v0, v73110; RV32-NEXT: vmerge.vvm v16, v16, v24, v03111; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload3112; RV32-NEXT: vfmax.vv v24, v16, v243113; RV32-NEXT: csrr a0, vlenb3114; RV32-NEXT: slli a0, a0, 33115; RV32-NEXT: add a0, sp, a03116; RV32-NEXT: addi a0, a0, 163117; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload3118; RV32-NEXT: vmfeq.vv v0, v16, v163119; RV32-NEXT: vmfeq.vv v7, v8, v83120; RV32-NEXT: csrr a0, vlenb3121; RV32-NEXT: slli a0, a0, 33122; RV32-NEXT: add a0, sp, a03123; RV32-NEXT: addi a0, a0, 163124; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload3125; RV32-NEXT: vmerge.vvm v16, v16, v8, v03126; RV32-NEXT: addi a0, sp, 163127; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill3128; RV32-NEXT: vmv1r.v v0, v73129; RV32-NEXT: csrr a0, vlenb3130; RV32-NEXT: slli a0, a0, 33131; RV32-NEXT: add a0, sp, a03132; RV32-NEXT: addi a0, a0, 163133; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload3134; RV32-NEXT: vmerge.vvm v8, v8, v16, v03135; RV32-NEXT: addi a0, sp, 163136; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload3137; RV32-NEXT: vfmax.vv v16, v8, v163138; RV32-NEXT: vmfeq.vv v0, v16, v163139; RV32-NEXT: vmfeq.vv v7, v24, v243140; RV32-NEXT: vmerge.vvm v8, v16, v24, v03141; RV32-NEXT: vmv1r.v v0, v73142; RV32-NEXT: vmerge.vvm v16, v24, v16, v03143; RV32-NEXT: vfmax.vv v8, v16, v83144; RV32-NEXT: vmfne.vv v16, v8, v83145; RV32-NEXT: vcpop.m a0, v163146; RV32-NEXT: beqz a0, .LBB161_23147; RV32-NEXT: # %bb.1:3148; RV32-NEXT: lui a0, %hi(.LCPI161_0)3149; RV32-NEXT: fld fa0, %lo(.LCPI161_0)(a0)3150; RV32-NEXT: j .LBB161_33151; RV32-NEXT: .LBB161_2:3152; RV32-NEXT: vfredmax.vs v8, v8, v83153; RV32-NEXT: vfmv.f.s fa0, v83154; RV32-NEXT: .LBB161_3:3155; RV32-NEXT: csrr a0, vlenb3156; RV32-NEXT: slli a0, a0, 43157; RV32-NEXT: add sp, sp, a03158; RV32-NEXT: .cfi_def_cfa sp, 163159; RV32-NEXT: addi sp, sp, 163160; RV32-NEXT: .cfi_def_cfa_offset 03161; RV32-NEXT: ret3162;3163; RV64-LABEL: vreduce_fmaximum_v64f64:3164; RV64: # %bb.0:3165; RV64-NEXT: addi sp, sp, -163166; RV64-NEXT: .cfi_def_cfa_offset 163167; RV64-NEXT: csrr a1, vlenb3168; RV64-NEXT: slli a1, a1, 43169; RV64-NEXT: sub sp, sp, a13170; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb3171; RV64-NEXT: addi a1, a0, 1283172; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma3173; RV64-NEXT: vle64.v v24, (a1)3174; RV64-NEXT: addi a1, a0, 3843175; RV64-NEXT: vle64.v v16, (a1)3176; RV64-NEXT: addi a1, a0, 2563177; RV64-NEXT: vle64.v v8, (a0)3178; RV64-NEXT: csrr a0, vlenb3179; RV64-NEXT: slli a0, a0, 33180; RV64-NEXT: add a0, sp, a03181; RV64-NEXT: addi a0, a0, 163182; RV64-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill3183; RV64-NEXT: vmfeq.vv v0, v24, v243184; RV64-NEXT: vmfeq.vv v7, v16, v163185; RV64-NEXT: vmerge.vvm v8, v24, v16, v03186; RV64-NEXT: addi a0, sp, 163187; RV64-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill3188; RV64-NEXT: vle64.v v8, (a1)3189; RV64-NEXT: vmv1r.v v0, v73190; RV64-NEXT: vmerge.vvm v16, v16, v24, v03191; RV64-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload3192; RV64-NEXT: vfmax.vv v24, v16, v243193; RV64-NEXT: csrr a0, vlenb3194; RV64-NEXT: slli a0, a0, 33195; RV64-NEXT: add a0, sp, a03196; RV64-NEXT: addi a0, a0, 163197; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload3198; RV64-NEXT: vmfeq.vv v0, v16, v163199; RV64-NEXT: vmfeq.vv v7, v8, v83200; RV64-NEXT: csrr a0, vlenb3201; RV64-NEXT: slli a0, a0, 33202; RV64-NEXT: add a0, sp, a03203; RV64-NEXT: addi a0, a0, 163204; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload3205; RV64-NEXT: vmerge.vvm v16, v16, v8, v03206; RV64-NEXT: addi a0, sp, 163207; RV64-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill3208; RV64-NEXT: vmv1r.v v0, v73209; RV64-NEXT: csrr a0, vlenb3210; RV64-NEXT: slli a0, a0, 33211; RV64-NEXT: add a0, sp, a03212; RV64-NEXT: addi a0, a0, 163213; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload3214; RV64-NEXT: vmerge.vvm v8, v8, v16, v03215; RV64-NEXT: addi a0, sp, 163216; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload3217; RV64-NEXT: vfmax.vv v16, v8, v163218; RV64-NEXT: vmfeq.vv v0, v16, v163219; RV64-NEXT: vmfeq.vv v7, v24, v243220; RV64-NEXT: vmerge.vvm v8, v16, v24, v03221; RV64-NEXT: vmv1r.v v0, v73222; RV64-NEXT: vmerge.vvm v16, v24, v16, v03223; RV64-NEXT: vfmax.vv v8, v16, v83224; RV64-NEXT: vmfne.vv v16, v8, v83225; RV64-NEXT: vcpop.m a0, v163226; RV64-NEXT: beqz a0, .LBB161_23227; RV64-NEXT: # %bb.1:3228; RV64-NEXT: lui a0, 40953229; RV64-NEXT: slli a0, a0, 393230; RV64-NEXT: fmv.d.x fa0, a03231; RV64-NEXT: j .LBB161_33232; RV64-NEXT: .LBB161_2:3233; RV64-NEXT: vfredmax.vs v8, v8, v83234; RV64-NEXT: vfmv.f.s fa0, v83235; RV64-NEXT: .LBB161_3:3236; RV64-NEXT: csrr a0, vlenb3237; RV64-NEXT: slli a0, a0, 43238; RV64-NEXT: add sp, sp, a03239; RV64-NEXT: .cfi_def_cfa sp, 163240; RV64-NEXT: addi sp, sp, 163241; RV64-NEXT: .cfi_def_cfa_offset 03242; RV64-NEXT: ret3243 %v = load <64 x double>, ptr %x3244 %red = call double @llvm.vector.reduce.fmaximum.v64f64(<64 x double> %v)3245 ret double %red3246}3247 3248define double @vreduce_fmaximum_v64f64_nonans(ptr %x) {3249; CHECK-LABEL: vreduce_fmaximum_v64f64_nonans:3250; CHECK: # %bb.0:3251; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma3252; CHECK-NEXT: vle64.v v8, (a0)3253; CHECK-NEXT: addi a1, a0, 3843254; CHECK-NEXT: vle64.v v16, (a1)3255; CHECK-NEXT: addi a1, a0, 2563256; CHECK-NEXT: addi a0, a0, 1283257; CHECK-NEXT: vle64.v v24, (a0)3258; CHECK-NEXT: vle64.v v0, (a1)3259; CHECK-NEXT: vfmax.vv v16, v24, v163260; CHECK-NEXT: vfmax.vv v8, v8, v03261; CHECK-NEXT: vfmax.vv v8, v8, v163262; CHECK-NEXT: vfredmax.vs v8, v8, v83263; CHECK-NEXT: vfmv.f.s fa0, v83264; CHECK-NEXT: ret3265 %v = load <64 x double>, ptr %x3266 %red = call nnan double @llvm.vector.reduce.fmaximum.v64f64(<64 x double> %v)3267 ret double %red3268}3269