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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \3; RUN: | FileCheck %s --check-prefixes=CHECK,RV324; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \5; RUN: | FileCheck %s --check-prefixes=CHECK,RV646 7define signext i8 @vpreduce_add_v2i8(i8 signext %s, <2 x i8> %v, <2 x i1> %m, i32 zeroext %evl) {8; CHECK-LABEL: vpreduce_add_v2i8:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma11; CHECK-NEXT: vmv.s.x v9, a012; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma13; CHECK-NEXT: vredsum.vs v9, v8, v9, v0.t14; CHECK-NEXT: vmv.x.s a0, v915; CHECK-NEXT: ret16 %r = call i8 @llvm.vp.reduce.add.v2i8(i8 %s, <2 x i8> %v, <2 x i1> %m, i32 %evl)17 ret i8 %r18}19 20define signext i8 @vpreduce_umax_v2i8(i8 signext %s, <2 x i8> %v, <2 x i1> %m, i32 zeroext %evl) {21; CHECK-LABEL: vpreduce_umax_v2i8:22; CHECK: # %bb.0:23; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma24; CHECK-NEXT: vmv.s.x v9, a025; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma26; CHECK-NEXT: vredmaxu.vs v9, v8, v9, v0.t27; CHECK-NEXT: vmv.x.s a0, v928; CHECK-NEXT: ret29 %r = call i8 @llvm.vp.reduce.umax.v2i8(i8 %s, <2 x i8> %v, <2 x i1> %m, i32 %evl)30 ret i8 %r31}32 33define signext i8 @vpreduce_smax_v2i8(i8 signext %s, <2 x i8> %v, <2 x i1> %m, i32 zeroext %evl) {34; CHECK-LABEL: vpreduce_smax_v2i8:35; CHECK: # %bb.0:36; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma37; CHECK-NEXT: vmv.s.x v9, a038; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma39; CHECK-NEXT: vredmax.vs v9, v8, v9, v0.t40; CHECK-NEXT: vmv.x.s a0, v941; CHECK-NEXT: ret42 %r = call i8 @llvm.vp.reduce.smax.v2i8(i8 %s, <2 x i8> %v, <2 x i1> %m, i32 %evl)43 ret i8 %r44}45 46define signext i8 @vpreduce_umin_v2i8(i8 signext %s, <2 x i8> %v, <2 x i1> %m, i32 zeroext %evl) {47; CHECK-LABEL: vpreduce_umin_v2i8:48; CHECK: # %bb.0:49; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma50; CHECK-NEXT: vmv.s.x v9, a051; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma52; CHECK-NEXT: vredminu.vs v9, v8, v9, v0.t53; CHECK-NEXT: vmv.x.s a0, v954; CHECK-NEXT: ret55 %r = call i8 @llvm.vp.reduce.umin.v2i8(i8 %s, <2 x i8> %v, <2 x i1> %m, i32 %evl)56 ret i8 %r57}58 59define signext i8 @vpreduce_smin_v2i8(i8 signext %s, <2 x i8> %v, <2 x i1> %m, i32 zeroext %evl) {60; CHECK-LABEL: vpreduce_smin_v2i8:61; CHECK: # %bb.0:62; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma63; CHECK-NEXT: vmv.s.x v9, a064; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma65; CHECK-NEXT: vredmin.vs v9, v8, v9, v0.t66; CHECK-NEXT: vmv.x.s a0, v967; CHECK-NEXT: ret68 %r = call i8 @llvm.vp.reduce.smin.v2i8(i8 %s, <2 x i8> %v, <2 x i1> %m, i32 %evl)69 ret i8 %r70}71 72define signext i8 @vpreduce_and_v2i8(i8 signext %s, <2 x i8> %v, <2 x i1> %m, i32 zeroext %evl) {73; CHECK-LABEL: vpreduce_and_v2i8:74; CHECK: # %bb.0:75; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma76; CHECK-NEXT: vmv.s.x v9, a077; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma78; CHECK-NEXT: vredand.vs v9, v8, v9, v0.t79; CHECK-NEXT: vmv.x.s a0, v980; CHECK-NEXT: ret81 %r = call i8 @llvm.vp.reduce.and.v2i8(i8 %s, <2 x i8> %v, <2 x i1> %m, i32 %evl)82 ret i8 %r83}84 85define signext i8 @vpreduce_or_v2i8(i8 signext %s, <2 x i8> %v, <2 x i1> %m, i32 zeroext %evl) {86; CHECK-LABEL: vpreduce_or_v2i8:87; CHECK: # %bb.0:88; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma89; CHECK-NEXT: vmv.s.x v9, a090; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma91; CHECK-NEXT: vredor.vs v9, v8, v9, v0.t92; CHECK-NEXT: vmv.x.s a0, v993; CHECK-NEXT: ret94 %r = call i8 @llvm.vp.reduce.or.v2i8(i8 %s, <2 x i8> %v, <2 x i1> %m, i32 %evl)95 ret i8 %r96}97 98define signext i8 @vpreduce_xor_v2i8(i8 signext %s, <2 x i8> %v, <2 x i1> %m, i32 zeroext %evl) {99; CHECK-LABEL: vpreduce_xor_v2i8:100; CHECK: # %bb.0:101; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma102; CHECK-NEXT: vmv.s.x v9, a0103; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma104; CHECK-NEXT: vredxor.vs v9, v8, v9, v0.t105; CHECK-NEXT: vmv.x.s a0, v9106; CHECK-NEXT: ret107 %r = call i8 @llvm.vp.reduce.xor.v2i8(i8 %s, <2 x i8> %v, <2 x i1> %m, i32 %evl)108 ret i8 %r109}110 111define signext i8 @vpreduce_umin_v3i8(i8 signext %s, <3 x i8> %v, <3 x i1> %m, i32 zeroext %evl) {112; CHECK-LABEL: vpreduce_umin_v3i8:113; CHECK: # %bb.0:114; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma115; CHECK-NEXT: vmv.s.x v9, a0116; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma117; CHECK-NEXT: vredminu.vs v9, v8, v9, v0.t118; CHECK-NEXT: vmv.x.s a0, v9119; CHECK-NEXT: ret120 %r = call i8 @llvm.vp.reduce.umin.v3i8(i8 %s, <3 x i8> %v, <3 x i1> %m, i32 %evl)121 ret i8 %r122}123 124define signext i8 @vpreduce_add_v4i8(i8 signext %s, <4 x i8> %v, <4 x i1> %m, i32 zeroext %evl) {125; CHECK-LABEL: vpreduce_add_v4i8:126; CHECK: # %bb.0:127; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma128; CHECK-NEXT: vmv.s.x v9, a0129; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma130; CHECK-NEXT: vredsum.vs v9, v8, v9, v0.t131; CHECK-NEXT: vmv.x.s a0, v9132; CHECK-NEXT: ret133 %r = call i8 @llvm.vp.reduce.add.v4i8(i8 %s, <4 x i8> %v, <4 x i1> %m, i32 %evl)134 ret i8 %r135}136 137define signext i8 @vpreduce_umax_v4i8(i8 signext %s, <4 x i8> %v, <4 x i1> %m, i32 zeroext %evl) {138; CHECK-LABEL: vpreduce_umax_v4i8:139; CHECK: # %bb.0:140; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma141; CHECK-NEXT: vmv.s.x v9, a0142; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma143; CHECK-NEXT: vredmaxu.vs v9, v8, v9, v0.t144; CHECK-NEXT: vmv.x.s a0, v9145; CHECK-NEXT: ret146 %r = call i8 @llvm.vp.reduce.umax.v4i8(i8 %s, <4 x i8> %v, <4 x i1> %m, i32 %evl)147 ret i8 %r148}149 150define signext i8 @vpreduce_smax_v4i8(i8 signext %s, <4 x i8> %v, <4 x i1> %m, i32 zeroext %evl) {151; CHECK-LABEL: vpreduce_smax_v4i8:152; CHECK: # %bb.0:153; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma154; CHECK-NEXT: vmv.s.x v9, a0155; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma156; CHECK-NEXT: vredmax.vs v9, v8, v9, v0.t157; CHECK-NEXT: vmv.x.s a0, v9158; CHECK-NEXT: ret159 %r = call i8 @llvm.vp.reduce.smax.v4i8(i8 %s, <4 x i8> %v, <4 x i1> %m, i32 %evl)160 ret i8 %r161}162 163define signext i8 @vpreduce_umin_v4i8(i8 signext %s, <4 x i8> %v, <4 x i1> %m, i32 zeroext %evl) {164; CHECK-LABEL: vpreduce_umin_v4i8:165; CHECK: # %bb.0:166; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma167; CHECK-NEXT: vmv.s.x v9, a0168; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma169; CHECK-NEXT: vredminu.vs v9, v8, v9, v0.t170; CHECK-NEXT: vmv.x.s a0, v9171; CHECK-NEXT: ret172 %r = call i8 @llvm.vp.reduce.umin.v4i8(i8 %s, <4 x i8> %v, <4 x i1> %m, i32 %evl)173 ret i8 %r174}175 176define signext i8 @vpreduce_smin_v4i8(i8 signext %s, <4 x i8> %v, <4 x i1> %m, i32 zeroext %evl) {177; CHECK-LABEL: vpreduce_smin_v4i8:178; CHECK: # %bb.0:179; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma180; CHECK-NEXT: vmv.s.x v9, a0181; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma182; CHECK-NEXT: vredmin.vs v9, v8, v9, v0.t183; CHECK-NEXT: vmv.x.s a0, v9184; CHECK-NEXT: ret185 %r = call i8 @llvm.vp.reduce.smin.v4i8(i8 %s, <4 x i8> %v, <4 x i1> %m, i32 %evl)186 ret i8 %r187}188 189define signext i8 @vpreduce_and_v4i8(i8 signext %s, <4 x i8> %v, <4 x i1> %m, i32 zeroext %evl) {190; CHECK-LABEL: vpreduce_and_v4i8:191; CHECK: # %bb.0:192; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma193; CHECK-NEXT: vmv.s.x v9, a0194; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma195; CHECK-NEXT: vredand.vs v9, v8, v9, v0.t196; CHECK-NEXT: vmv.x.s a0, v9197; CHECK-NEXT: ret198 %r = call i8 @llvm.vp.reduce.and.v4i8(i8 %s, <4 x i8> %v, <4 x i1> %m, i32 %evl)199 ret i8 %r200}201 202define signext i8 @vpreduce_or_v4i8(i8 signext %s, <4 x i8> %v, <4 x i1> %m, i32 zeroext %evl) {203; CHECK-LABEL: vpreduce_or_v4i8:204; CHECK: # %bb.0:205; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma206; CHECK-NEXT: vmv.s.x v9, a0207; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma208; CHECK-NEXT: vredor.vs v9, v8, v9, v0.t209; CHECK-NEXT: vmv.x.s a0, v9210; CHECK-NEXT: ret211 %r = call i8 @llvm.vp.reduce.or.v4i8(i8 %s, <4 x i8> %v, <4 x i1> %m, i32 %evl)212 ret i8 %r213}214 215define signext i8 @vpreduce_xor_v4i8(i8 signext %s, <4 x i8> %v, <4 x i1> %m, i32 zeroext %evl) {216; CHECK-LABEL: vpreduce_xor_v4i8:217; CHECK: # %bb.0:218; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma219; CHECK-NEXT: vmv.s.x v9, a0220; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma221; CHECK-NEXT: vredxor.vs v9, v8, v9, v0.t222; CHECK-NEXT: vmv.x.s a0, v9223; CHECK-NEXT: ret224 %r = call i8 @llvm.vp.reduce.xor.v4i8(i8 %s, <4 x i8> %v, <4 x i1> %m, i32 %evl)225 ret i8 %r226}227 228define signext i16 @vpreduce_add_v2i16(i16 signext %s, <2 x i16> %v, <2 x i1> %m, i32 zeroext %evl) {229; CHECK-LABEL: vpreduce_add_v2i16:230; CHECK: # %bb.0:231; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma232; CHECK-NEXT: vmv.s.x v9, a0233; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma234; CHECK-NEXT: vredsum.vs v9, v8, v9, v0.t235; CHECK-NEXT: vmv.x.s a0, v9236; CHECK-NEXT: ret237 %r = call i16 @llvm.vp.reduce.add.v2i16(i16 %s, <2 x i16> %v, <2 x i1> %m, i32 %evl)238 ret i16 %r239}240 241define signext i16 @vpreduce_umax_v2i16(i16 signext %s, <2 x i16> %v, <2 x i1> %m, i32 zeroext %evl) {242; CHECK-LABEL: vpreduce_umax_v2i16:243; CHECK: # %bb.0:244; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma245; CHECK-NEXT: vmv.s.x v9, a0246; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma247; CHECK-NEXT: vredmaxu.vs v9, v8, v9, v0.t248; CHECK-NEXT: vmv.x.s a0, v9249; CHECK-NEXT: ret250 %r = call i16 @llvm.vp.reduce.umax.v2i16(i16 %s, <2 x i16> %v, <2 x i1> %m, i32 %evl)251 ret i16 %r252}253 254define signext i16 @vpreduce_smax_v2i16(i16 signext %s, <2 x i16> %v, <2 x i1> %m, i32 zeroext %evl) {255; CHECK-LABEL: vpreduce_smax_v2i16:256; CHECK: # %bb.0:257; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma258; CHECK-NEXT: vmv.s.x v9, a0259; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma260; CHECK-NEXT: vredmax.vs v9, v8, v9, v0.t261; CHECK-NEXT: vmv.x.s a0, v9262; CHECK-NEXT: ret263 %r = call i16 @llvm.vp.reduce.smax.v2i16(i16 %s, <2 x i16> %v, <2 x i1> %m, i32 %evl)264 ret i16 %r265}266 267define signext i16 @vpreduce_umin_v2i16(i16 signext %s, <2 x i16> %v, <2 x i1> %m, i32 zeroext %evl) {268; CHECK-LABEL: vpreduce_umin_v2i16:269; CHECK: # %bb.0:270; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma271; CHECK-NEXT: vmv.s.x v9, a0272; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma273; CHECK-NEXT: vredminu.vs v9, v8, v9, v0.t274; CHECK-NEXT: vmv.x.s a0, v9275; CHECK-NEXT: ret276 %r = call i16 @llvm.vp.reduce.umin.v2i16(i16 %s, <2 x i16> %v, <2 x i1> %m, i32 %evl)277 ret i16 %r278}279 280define signext i16 @vpreduce_smin_v2i16(i16 signext %s, <2 x i16> %v, <2 x i1> %m, i32 zeroext %evl) {281; CHECK-LABEL: vpreduce_smin_v2i16:282; CHECK: # %bb.0:283; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma284; CHECK-NEXT: vmv.s.x v9, a0285; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma286; CHECK-NEXT: vredmin.vs v9, v8, v9, v0.t287; CHECK-NEXT: vmv.x.s a0, v9288; CHECK-NEXT: ret289 %r = call i16 @llvm.vp.reduce.smin.v2i16(i16 %s, <2 x i16> %v, <2 x i1> %m, i32 %evl)290 ret i16 %r291}292 293define signext i16 @vpreduce_and_v2i16(i16 signext %s, <2 x i16> %v, <2 x i1> %m, i32 zeroext %evl) {294; CHECK-LABEL: vpreduce_and_v2i16:295; CHECK: # %bb.0:296; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma297; CHECK-NEXT: vmv.s.x v9, a0298; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma299; CHECK-NEXT: vredand.vs v9, v8, v9, v0.t300; CHECK-NEXT: vmv.x.s a0, v9301; CHECK-NEXT: ret302 %r = call i16 @llvm.vp.reduce.and.v2i16(i16 %s, <2 x i16> %v, <2 x i1> %m, i32 %evl)303 ret i16 %r304}305 306define signext i16 @vpreduce_or_v2i16(i16 signext %s, <2 x i16> %v, <2 x i1> %m, i32 zeroext %evl) {307; CHECK-LABEL: vpreduce_or_v2i16:308; CHECK: # %bb.0:309; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma310; CHECK-NEXT: vmv.s.x v9, a0311; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma312; CHECK-NEXT: vredor.vs v9, v8, v9, v0.t313; CHECK-NEXT: vmv.x.s a0, v9314; CHECK-NEXT: ret315 %r = call i16 @llvm.vp.reduce.or.v2i16(i16 %s, <2 x i16> %v, <2 x i1> %m, i32 %evl)316 ret i16 %r317}318 319define signext i16 @vpreduce_xor_v2i16(i16 signext %s, <2 x i16> %v, <2 x i1> %m, i32 zeroext %evl) {320; CHECK-LABEL: vpreduce_xor_v2i16:321; CHECK: # %bb.0:322; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma323; CHECK-NEXT: vmv.s.x v9, a0324; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma325; CHECK-NEXT: vredxor.vs v9, v8, v9, v0.t326; CHECK-NEXT: vmv.x.s a0, v9327; CHECK-NEXT: ret328 %r = call i16 @llvm.vp.reduce.xor.v2i16(i16 %s, <2 x i16> %v, <2 x i1> %m, i32 %evl)329 ret i16 %r330}331 332define signext i16 @vpreduce_add_v4i16(i16 signext %s, <4 x i16> %v, <4 x i1> %m, i32 zeroext %evl) {333; CHECK-LABEL: vpreduce_add_v4i16:334; CHECK: # %bb.0:335; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma336; CHECK-NEXT: vmv.s.x v9, a0337; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma338; CHECK-NEXT: vredsum.vs v9, v8, v9, v0.t339; CHECK-NEXT: vmv.x.s a0, v9340; CHECK-NEXT: ret341 %r = call i16 @llvm.vp.reduce.add.v4i16(i16 %s, <4 x i16> %v, <4 x i1> %m, i32 %evl)342 ret i16 %r343}344 345define signext i16 @vpreduce_umax_v4i16(i16 signext %s, <4 x i16> %v, <4 x i1> %m, i32 zeroext %evl) {346; CHECK-LABEL: vpreduce_umax_v4i16:347; CHECK: # %bb.0:348; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma349; CHECK-NEXT: vmv.s.x v9, a0350; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma351; CHECK-NEXT: vredmaxu.vs v9, v8, v9, v0.t352; CHECK-NEXT: vmv.x.s a0, v9353; CHECK-NEXT: ret354 %r = call i16 @llvm.vp.reduce.umax.v4i16(i16 %s, <4 x i16> %v, <4 x i1> %m, i32 %evl)355 ret i16 %r356}357 358define signext i16 @vpreduce_smax_v4i16(i16 signext %s, <4 x i16> %v, <4 x i1> %m, i32 zeroext %evl) {359; CHECK-LABEL: vpreduce_smax_v4i16:360; CHECK: # %bb.0:361; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma362; CHECK-NEXT: vmv.s.x v9, a0363; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma364; CHECK-NEXT: vredmax.vs v9, v8, v9, v0.t365; CHECK-NEXT: vmv.x.s a0, v9366; CHECK-NEXT: ret367 %r = call i16 @llvm.vp.reduce.smax.v4i16(i16 %s, <4 x i16> %v, <4 x i1> %m, i32 %evl)368 ret i16 %r369}370 371define signext i16 @vpreduce_umin_v4i16(i16 signext %s, <4 x i16> %v, <4 x i1> %m, i32 zeroext %evl) {372; CHECK-LABEL: vpreduce_umin_v4i16:373; CHECK: # %bb.0:374; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma375; CHECK-NEXT: vmv.s.x v9, a0376; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma377; CHECK-NEXT: vredminu.vs v9, v8, v9, v0.t378; CHECK-NEXT: vmv.x.s a0, v9379; CHECK-NEXT: ret380 %r = call i16 @llvm.vp.reduce.umin.v4i16(i16 %s, <4 x i16> %v, <4 x i1> %m, i32 %evl)381 ret i16 %r382}383 384define signext i16 @vpreduce_smin_v4i16(i16 signext %s, <4 x i16> %v, <4 x i1> %m, i32 zeroext %evl) {385; CHECK-LABEL: vpreduce_smin_v4i16:386; CHECK: # %bb.0:387; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma388; CHECK-NEXT: vmv.s.x v9, a0389; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma390; CHECK-NEXT: vredmin.vs v9, v8, v9, v0.t391; CHECK-NEXT: vmv.x.s a0, v9392; CHECK-NEXT: ret393 %r = call i16 @llvm.vp.reduce.smin.v4i16(i16 %s, <4 x i16> %v, <4 x i1> %m, i32 %evl)394 ret i16 %r395}396 397define signext i16 @vpreduce_and_v4i16(i16 signext %s, <4 x i16> %v, <4 x i1> %m, i32 zeroext %evl) {398; CHECK-LABEL: vpreduce_and_v4i16:399; CHECK: # %bb.0:400; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma401; CHECK-NEXT: vmv.s.x v9, a0402; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma403; CHECK-NEXT: vredand.vs v9, v8, v9, v0.t404; CHECK-NEXT: vmv.x.s a0, v9405; CHECK-NEXT: ret406 %r = call i16 @llvm.vp.reduce.and.v4i16(i16 %s, <4 x i16> %v, <4 x i1> %m, i32 %evl)407 ret i16 %r408}409 410define signext i16 @vpreduce_or_v4i16(i16 signext %s, <4 x i16> %v, <4 x i1> %m, i32 zeroext %evl) {411; CHECK-LABEL: vpreduce_or_v4i16:412; CHECK: # %bb.0:413; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma414; CHECK-NEXT: vmv.s.x v9, a0415; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma416; CHECK-NEXT: vredor.vs v9, v8, v9, v0.t417; CHECK-NEXT: vmv.x.s a0, v9418; CHECK-NEXT: ret419 %r = call i16 @llvm.vp.reduce.or.v4i16(i16 %s, <4 x i16> %v, <4 x i1> %m, i32 %evl)420 ret i16 %r421}422 423define signext i16 @vpreduce_xor_v4i16(i16 signext %s, <4 x i16> %v, <4 x i1> %m, i32 zeroext %evl) {424; CHECK-LABEL: vpreduce_xor_v4i16:425; CHECK: # %bb.0:426; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma427; CHECK-NEXT: vmv.s.x v9, a0428; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma429; CHECK-NEXT: vredxor.vs v9, v8, v9, v0.t430; CHECK-NEXT: vmv.x.s a0, v9431; CHECK-NEXT: ret432 %r = call i16 @llvm.vp.reduce.xor.v4i16(i16 %s, <4 x i16> %v, <4 x i1> %m, i32 %evl)433 ret i16 %r434}435 436define signext i32 @vpreduce_add_v2i32(i32 signext %s, <2 x i32> %v, <2 x i1> %m, i32 zeroext %evl) {437; CHECK-LABEL: vpreduce_add_v2i32:438; CHECK: # %bb.0:439; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma440; CHECK-NEXT: vmv.s.x v9, a0441; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma442; CHECK-NEXT: vredsum.vs v9, v8, v9, v0.t443; CHECK-NEXT: vmv.x.s a0, v9444; CHECK-NEXT: ret445 %r = call i32 @llvm.vp.reduce.add.v2i32(i32 %s, <2 x i32> %v, <2 x i1> %m, i32 %evl)446 ret i32 %r447}448 449define signext i32 @vpreduce_umax_v2i32(i32 signext %s, <2 x i32> %v, <2 x i1> %m, i32 zeroext %evl) {450; CHECK-LABEL: vpreduce_umax_v2i32:451; CHECK: # %bb.0:452; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma453; CHECK-NEXT: vmv.s.x v9, a0454; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma455; CHECK-NEXT: vredmaxu.vs v9, v8, v9, v0.t456; CHECK-NEXT: vmv.x.s a0, v9457; CHECK-NEXT: ret458 %r = call i32 @llvm.vp.reduce.umax.v2i32(i32 %s, <2 x i32> %v, <2 x i1> %m, i32 %evl)459 ret i32 %r460}461 462define signext i32 @vpreduce_smax_v2i32(i32 signext %s, <2 x i32> %v, <2 x i1> %m, i32 zeroext %evl) {463; CHECK-LABEL: vpreduce_smax_v2i32:464; CHECK: # %bb.0:465; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma466; CHECK-NEXT: vmv.s.x v9, a0467; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma468; CHECK-NEXT: vredmax.vs v9, v8, v9, v0.t469; CHECK-NEXT: vmv.x.s a0, v9470; CHECK-NEXT: ret471 %r = call i32 @llvm.vp.reduce.smax.v2i32(i32 %s, <2 x i32> %v, <2 x i1> %m, i32 %evl)472 ret i32 %r473}474 475define signext i32 @vpreduce_umin_v2i32(i32 signext %s, <2 x i32> %v, <2 x i1> %m, i32 zeroext %evl) {476; CHECK-LABEL: vpreduce_umin_v2i32:477; CHECK: # %bb.0:478; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma479; CHECK-NEXT: vmv.s.x v9, a0480; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma481; CHECK-NEXT: vredminu.vs v9, v8, v9, v0.t482; CHECK-NEXT: vmv.x.s a0, v9483; CHECK-NEXT: ret484 %r = call i32 @llvm.vp.reduce.umin.v2i32(i32 %s, <2 x i32> %v, <2 x i1> %m, i32 %evl)485 ret i32 %r486}487 488define signext i32 @vpreduce_smin_v2i32(i32 signext %s, <2 x i32> %v, <2 x i1> %m, i32 zeroext %evl) {489; CHECK-LABEL: vpreduce_smin_v2i32:490; CHECK: # %bb.0:491; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma492; CHECK-NEXT: vmv.s.x v9, a0493; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma494; CHECK-NEXT: vredmin.vs v9, v8, v9, v0.t495; CHECK-NEXT: vmv.x.s a0, v9496; CHECK-NEXT: ret497 %r = call i32 @llvm.vp.reduce.smin.v2i32(i32 %s, <2 x i32> %v, <2 x i1> %m, i32 %evl)498 ret i32 %r499}500 501define signext i32 @vpreduce_and_v2i32(i32 signext %s, <2 x i32> %v, <2 x i1> %m, i32 zeroext %evl) {502; CHECK-LABEL: vpreduce_and_v2i32:503; CHECK: # %bb.0:504; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma505; CHECK-NEXT: vmv.s.x v9, a0506; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma507; CHECK-NEXT: vredand.vs v9, v8, v9, v0.t508; CHECK-NEXT: vmv.x.s a0, v9509; CHECK-NEXT: ret510 %r = call i32 @llvm.vp.reduce.and.v2i32(i32 %s, <2 x i32> %v, <2 x i1> %m, i32 %evl)511 ret i32 %r512}513 514define signext i32 @vpreduce_or_v2i32(i32 signext %s, <2 x i32> %v, <2 x i1> %m, i32 zeroext %evl) {515; CHECK-LABEL: vpreduce_or_v2i32:516; CHECK: # %bb.0:517; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma518; CHECK-NEXT: vmv.s.x v9, a0519; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma520; CHECK-NEXT: vredor.vs v9, v8, v9, v0.t521; CHECK-NEXT: vmv.x.s a0, v9522; CHECK-NEXT: ret523 %r = call i32 @llvm.vp.reduce.or.v2i32(i32 %s, <2 x i32> %v, <2 x i1> %m, i32 %evl)524 ret i32 %r525}526 527define signext i32 @vpreduce_xor_v2i32(i32 signext %s, <2 x i32> %v, <2 x i1> %m, i32 zeroext %evl) {528; CHECK-LABEL: vpreduce_xor_v2i32:529; CHECK: # %bb.0:530; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma531; CHECK-NEXT: vmv.s.x v9, a0532; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma533; CHECK-NEXT: vredxor.vs v9, v8, v9, v0.t534; CHECK-NEXT: vmv.x.s a0, v9535; CHECK-NEXT: ret536 %r = call i32 @llvm.vp.reduce.xor.v2i32(i32 %s, <2 x i32> %v, <2 x i1> %m, i32 %evl)537 ret i32 %r538}539 540define signext i32 @vpreduce_add_v4i32(i32 signext %s, <4 x i32> %v, <4 x i1> %m, i32 zeroext %evl) {541; CHECK-LABEL: vpreduce_add_v4i32:542; CHECK: # %bb.0:543; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma544; CHECK-NEXT: vmv.s.x v9, a0545; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma546; CHECK-NEXT: vredsum.vs v9, v8, v9, v0.t547; CHECK-NEXT: vmv.x.s a0, v9548; CHECK-NEXT: ret549 %r = call i32 @llvm.vp.reduce.add.v4i32(i32 %s, <4 x i32> %v, <4 x i1> %m, i32 %evl)550 ret i32 %r551}552 553define signext i32 @vpreduce_umax_v4i32(i32 signext %s, <4 x i32> %v, <4 x i1> %m, i32 zeroext %evl) {554; CHECK-LABEL: vpreduce_umax_v4i32:555; CHECK: # %bb.0:556; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma557; CHECK-NEXT: vmv.s.x v9, a0558; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma559; CHECK-NEXT: vredmaxu.vs v9, v8, v9, v0.t560; CHECK-NEXT: vmv.x.s a0, v9561; CHECK-NEXT: ret562 %r = call i32 @llvm.vp.reduce.umax.v4i32(i32 %s, <4 x i32> %v, <4 x i1> %m, i32 %evl)563 ret i32 %r564}565 566define signext i32 @vpreduce_smax_v4i32(i32 signext %s, <4 x i32> %v, <4 x i1> %m, i32 zeroext %evl) {567; CHECK-LABEL: vpreduce_smax_v4i32:568; CHECK: # %bb.0:569; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma570; CHECK-NEXT: vmv.s.x v9, a0571; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma572; CHECK-NEXT: vredmax.vs v9, v8, v9, v0.t573; CHECK-NEXT: vmv.x.s a0, v9574; CHECK-NEXT: ret575 %r = call i32 @llvm.vp.reduce.smax.v4i32(i32 %s, <4 x i32> %v, <4 x i1> %m, i32 %evl)576 ret i32 %r577}578 579define signext i32 @vpreduce_umin_v4i32(i32 signext %s, <4 x i32> %v, <4 x i1> %m, i32 zeroext %evl) {580; CHECK-LABEL: vpreduce_umin_v4i32:581; CHECK: # %bb.0:582; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma583; CHECK-NEXT: vmv.s.x v9, a0584; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma585; CHECK-NEXT: vredminu.vs v9, v8, v9, v0.t586; CHECK-NEXT: vmv.x.s a0, v9587; CHECK-NEXT: ret588 %r = call i32 @llvm.vp.reduce.umin.v4i32(i32 %s, <4 x i32> %v, <4 x i1> %m, i32 %evl)589 ret i32 %r590}591 592define signext i32 @vpreduce_smin_v4i32(i32 signext %s, <4 x i32> %v, <4 x i1> %m, i32 zeroext %evl) {593; CHECK-LABEL: vpreduce_smin_v4i32:594; CHECK: # %bb.0:595; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma596; CHECK-NEXT: vmv.s.x v9, a0597; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma598; CHECK-NEXT: vredmin.vs v9, v8, v9, v0.t599; CHECK-NEXT: vmv.x.s a0, v9600; CHECK-NEXT: ret601 %r = call i32 @llvm.vp.reduce.smin.v4i32(i32 %s, <4 x i32> %v, <4 x i1> %m, i32 %evl)602 ret i32 %r603}604 605define signext i32 @vpreduce_and_v4i32(i32 signext %s, <4 x i32> %v, <4 x i1> %m, i32 zeroext %evl) {606; CHECK-LABEL: vpreduce_and_v4i32:607; CHECK: # %bb.0:608; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma609; CHECK-NEXT: vmv.s.x v9, a0610; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma611; CHECK-NEXT: vredand.vs v9, v8, v9, v0.t612; CHECK-NEXT: vmv.x.s a0, v9613; CHECK-NEXT: ret614 %r = call i32 @llvm.vp.reduce.and.v4i32(i32 %s, <4 x i32> %v, <4 x i1> %m, i32 %evl)615 ret i32 %r616}617 618define signext i32 @vpreduce_or_v4i32(i32 signext %s, <4 x i32> %v, <4 x i1> %m, i32 zeroext %evl) {619; CHECK-LABEL: vpreduce_or_v4i32:620; CHECK: # %bb.0:621; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma622; CHECK-NEXT: vmv.s.x v9, a0623; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma624; CHECK-NEXT: vredor.vs v9, v8, v9, v0.t625; CHECK-NEXT: vmv.x.s a0, v9626; CHECK-NEXT: ret627 %r = call i32 @llvm.vp.reduce.or.v4i32(i32 %s, <4 x i32> %v, <4 x i1> %m, i32 %evl)628 ret i32 %r629}630 631define signext i32 @vpreduce_xor_v4i32(i32 signext %s, <4 x i32> %v, <4 x i1> %m, i32 zeroext %evl) {632; CHECK-LABEL: vpreduce_xor_v4i32:633; CHECK: # %bb.0:634; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma635; CHECK-NEXT: vmv.s.x v9, a0636; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma637; CHECK-NEXT: vredxor.vs v9, v8, v9, v0.t638; CHECK-NEXT: vmv.x.s a0, v9639; CHECK-NEXT: ret640 %r = call i32 @llvm.vp.reduce.xor.v4i32(i32 %s, <4 x i32> %v, <4 x i1> %m, i32 %evl)641 ret i32 %r642}643 644define signext i32 @vpreduce_xor_v64i32(i32 signext %s, <64 x i32> %v, <64 x i1> %m, i32 zeroext %evl) {645; CHECK-LABEL: vpreduce_xor_v64i32:646; CHECK: # %bb.0:647; CHECK-NEXT: li a3, 32648; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma649; CHECK-NEXT: vslidedown.vi v24, v0, 4650; CHECK-NEXT: mv a2, a1651; CHECK-NEXT: bltu a1, a3, .LBB49_2652; CHECK-NEXT: # %bb.1:653; CHECK-NEXT: li a2, 32654; CHECK-NEXT: .LBB49_2:655; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma656; CHECK-NEXT: vmv.s.x v25, a0657; CHECK-NEXT: addi a0, a1, -32658; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma659; CHECK-NEXT: vredxor.vs v25, v8, v25, v0.t660; CHECK-NEXT: sltu a1, a1, a0661; CHECK-NEXT: addi a1, a1, -1662; CHECK-NEXT: and a0, a1, a0663; CHECK-NEXT: vmv1r.v v0, v24664; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma665; CHECK-NEXT: vredxor.vs v25, v16, v25, v0.t666; CHECK-NEXT: vmv.x.s a0, v25667; CHECK-NEXT: ret668 %r = call i32 @llvm.vp.reduce.xor.v64i32(i32 %s, <64 x i32> %v, <64 x i1> %m, i32 %evl)669 ret i32 %r670}671 672define signext i64 @vpreduce_add_v2i64(i64 signext %s, <2 x i64> %v, <2 x i1> %m, i32 zeroext %evl) {673; RV32-LABEL: vpreduce_add_v2i64:674; RV32: # %bb.0:675; RV32-NEXT: addi sp, sp, -16676; RV32-NEXT: .cfi_def_cfa_offset 16677; RV32-NEXT: sw a0, 8(sp)678; RV32-NEXT: sw a1, 12(sp)679; RV32-NEXT: addi a0, sp, 8680; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma681; RV32-NEXT: vlse64.v v9, (a0), zero682; RV32-NEXT: li a1, 32683; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma684; RV32-NEXT: vredsum.vs v9, v8, v9, v0.t685; RV32-NEXT: vmv.x.s a0, v9686; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma687; RV32-NEXT: vsrl.vx v8, v9, a1688; RV32-NEXT: vmv.x.s a1, v8689; RV32-NEXT: addi sp, sp, 16690; RV32-NEXT: .cfi_def_cfa_offset 0691; RV32-NEXT: ret692;693; RV64-LABEL: vpreduce_add_v2i64:694; RV64: # %bb.0:695; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma696; RV64-NEXT: vmv.s.x v9, a0697; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma698; RV64-NEXT: vredsum.vs v9, v8, v9, v0.t699; RV64-NEXT: vmv.x.s a0, v9700; RV64-NEXT: ret701 %r = call i64 @llvm.vp.reduce.add.v2i64(i64 %s, <2 x i64> %v, <2 x i1> %m, i32 %evl)702 ret i64 %r703}704 705define signext i64 @vpreduce_umax_v2i64(i64 signext %s, <2 x i64> %v, <2 x i1> %m, i32 zeroext %evl) {706; RV32-LABEL: vpreduce_umax_v2i64:707; RV32: # %bb.0:708; RV32-NEXT: addi sp, sp, -16709; RV32-NEXT: .cfi_def_cfa_offset 16710; RV32-NEXT: sw a0, 8(sp)711; RV32-NEXT: sw a1, 12(sp)712; RV32-NEXT: addi a0, sp, 8713; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma714; RV32-NEXT: vlse64.v v9, (a0), zero715; RV32-NEXT: li a1, 32716; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma717; RV32-NEXT: vredmaxu.vs v9, v8, v9, v0.t718; RV32-NEXT: vmv.x.s a0, v9719; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma720; RV32-NEXT: vsrl.vx v8, v9, a1721; RV32-NEXT: vmv.x.s a1, v8722; RV32-NEXT: addi sp, sp, 16723; RV32-NEXT: .cfi_def_cfa_offset 0724; RV32-NEXT: ret725;726; RV64-LABEL: vpreduce_umax_v2i64:727; RV64: # %bb.0:728; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma729; RV64-NEXT: vmv.s.x v9, a0730; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma731; RV64-NEXT: vredmaxu.vs v9, v8, v9, v0.t732; RV64-NEXT: vmv.x.s a0, v9733; RV64-NEXT: ret734 %r = call i64 @llvm.vp.reduce.umax.v2i64(i64 %s, <2 x i64> %v, <2 x i1> %m, i32 %evl)735 ret i64 %r736}737 738define signext i64 @vpreduce_smax_v2i64(i64 signext %s, <2 x i64> %v, <2 x i1> %m, i32 zeroext %evl) {739; RV32-LABEL: vpreduce_smax_v2i64:740; RV32: # %bb.0:741; RV32-NEXT: addi sp, sp, -16742; RV32-NEXT: .cfi_def_cfa_offset 16743; RV32-NEXT: sw a0, 8(sp)744; RV32-NEXT: sw a1, 12(sp)745; RV32-NEXT: addi a0, sp, 8746; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma747; RV32-NEXT: vlse64.v v9, (a0), zero748; RV32-NEXT: li a1, 32749; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma750; RV32-NEXT: vredmax.vs v9, v8, v9, v0.t751; RV32-NEXT: vmv.x.s a0, v9752; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma753; RV32-NEXT: vsrl.vx v8, v9, a1754; RV32-NEXT: vmv.x.s a1, v8755; RV32-NEXT: addi sp, sp, 16756; RV32-NEXT: .cfi_def_cfa_offset 0757; RV32-NEXT: ret758;759; RV64-LABEL: vpreduce_smax_v2i64:760; RV64: # %bb.0:761; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma762; RV64-NEXT: vmv.s.x v9, a0763; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma764; RV64-NEXT: vredmax.vs v9, v8, v9, v0.t765; RV64-NEXT: vmv.x.s a0, v9766; RV64-NEXT: ret767 %r = call i64 @llvm.vp.reduce.smax.v2i64(i64 %s, <2 x i64> %v, <2 x i1> %m, i32 %evl)768 ret i64 %r769}770 771define signext i64 @vpreduce_umin_v2i64(i64 signext %s, <2 x i64> %v, <2 x i1> %m, i32 zeroext %evl) {772; RV32-LABEL: vpreduce_umin_v2i64:773; RV32: # %bb.0:774; RV32-NEXT: addi sp, sp, -16775; RV32-NEXT: .cfi_def_cfa_offset 16776; RV32-NEXT: sw a0, 8(sp)777; RV32-NEXT: sw a1, 12(sp)778; RV32-NEXT: addi a0, sp, 8779; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma780; RV32-NEXT: vlse64.v v9, (a0), zero781; RV32-NEXT: li a1, 32782; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma783; RV32-NEXT: vredminu.vs v9, v8, v9, v0.t784; RV32-NEXT: vmv.x.s a0, v9785; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma786; RV32-NEXT: vsrl.vx v8, v9, a1787; RV32-NEXT: vmv.x.s a1, v8788; RV32-NEXT: addi sp, sp, 16789; RV32-NEXT: .cfi_def_cfa_offset 0790; RV32-NEXT: ret791;792; RV64-LABEL: vpreduce_umin_v2i64:793; RV64: # %bb.0:794; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma795; RV64-NEXT: vmv.s.x v9, a0796; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma797; RV64-NEXT: vredminu.vs v9, v8, v9, v0.t798; RV64-NEXT: vmv.x.s a0, v9799; RV64-NEXT: ret800 %r = call i64 @llvm.vp.reduce.umin.v2i64(i64 %s, <2 x i64> %v, <2 x i1> %m, i32 %evl)801 ret i64 %r802}803 804define signext i64 @vpreduce_smin_v2i64(i64 signext %s, <2 x i64> %v, <2 x i1> %m, i32 zeroext %evl) {805; RV32-LABEL: vpreduce_smin_v2i64:806; RV32: # %bb.0:807; RV32-NEXT: addi sp, sp, -16808; RV32-NEXT: .cfi_def_cfa_offset 16809; RV32-NEXT: sw a0, 8(sp)810; RV32-NEXT: sw a1, 12(sp)811; RV32-NEXT: addi a0, sp, 8812; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma813; RV32-NEXT: vlse64.v v9, (a0), zero814; RV32-NEXT: li a1, 32815; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma816; RV32-NEXT: vredmin.vs v9, v8, v9, v0.t817; RV32-NEXT: vmv.x.s a0, v9818; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma819; RV32-NEXT: vsrl.vx v8, v9, a1820; RV32-NEXT: vmv.x.s a1, v8821; RV32-NEXT: addi sp, sp, 16822; RV32-NEXT: .cfi_def_cfa_offset 0823; RV32-NEXT: ret824;825; RV64-LABEL: vpreduce_smin_v2i64:826; RV64: # %bb.0:827; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma828; RV64-NEXT: vmv.s.x v9, a0829; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma830; RV64-NEXT: vredmin.vs v9, v8, v9, v0.t831; RV64-NEXT: vmv.x.s a0, v9832; RV64-NEXT: ret833 %r = call i64 @llvm.vp.reduce.smin.v2i64(i64 %s, <2 x i64> %v, <2 x i1> %m, i32 %evl)834 ret i64 %r835}836 837define signext i64 @vpreduce_and_v2i64(i64 signext %s, <2 x i64> %v, <2 x i1> %m, i32 zeroext %evl) {838; RV32-LABEL: vpreduce_and_v2i64:839; RV32: # %bb.0:840; RV32-NEXT: addi sp, sp, -16841; RV32-NEXT: .cfi_def_cfa_offset 16842; RV32-NEXT: sw a0, 8(sp)843; RV32-NEXT: sw a1, 12(sp)844; RV32-NEXT: addi a0, sp, 8845; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma846; RV32-NEXT: vlse64.v v9, (a0), zero847; RV32-NEXT: li a1, 32848; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma849; RV32-NEXT: vredand.vs v9, v8, v9, v0.t850; RV32-NEXT: vmv.x.s a0, v9851; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma852; RV32-NEXT: vsrl.vx v8, v9, a1853; RV32-NEXT: vmv.x.s a1, v8854; RV32-NEXT: addi sp, sp, 16855; RV32-NEXT: .cfi_def_cfa_offset 0856; RV32-NEXT: ret857;858; RV64-LABEL: vpreduce_and_v2i64:859; RV64: # %bb.0:860; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma861; RV64-NEXT: vmv.s.x v9, a0862; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma863; RV64-NEXT: vredand.vs v9, v8, v9, v0.t864; RV64-NEXT: vmv.x.s a0, v9865; RV64-NEXT: ret866 %r = call i64 @llvm.vp.reduce.and.v2i64(i64 %s, <2 x i64> %v, <2 x i1> %m, i32 %evl)867 ret i64 %r868}869 870define signext i64 @vpreduce_or_v2i64(i64 signext %s, <2 x i64> %v, <2 x i1> %m, i32 zeroext %evl) {871; RV32-LABEL: vpreduce_or_v2i64:872; RV32: # %bb.0:873; RV32-NEXT: addi sp, sp, -16874; RV32-NEXT: .cfi_def_cfa_offset 16875; RV32-NEXT: sw a0, 8(sp)876; RV32-NEXT: sw a1, 12(sp)877; RV32-NEXT: addi a0, sp, 8878; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma879; RV32-NEXT: vlse64.v v9, (a0), zero880; RV32-NEXT: li a1, 32881; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma882; RV32-NEXT: vredor.vs v9, v8, v9, v0.t883; RV32-NEXT: vmv.x.s a0, v9884; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma885; RV32-NEXT: vsrl.vx v8, v9, a1886; RV32-NEXT: vmv.x.s a1, v8887; RV32-NEXT: addi sp, sp, 16888; RV32-NEXT: .cfi_def_cfa_offset 0889; RV32-NEXT: ret890;891; RV64-LABEL: vpreduce_or_v2i64:892; RV64: # %bb.0:893; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma894; RV64-NEXT: vmv.s.x v9, a0895; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma896; RV64-NEXT: vredor.vs v9, v8, v9, v0.t897; RV64-NEXT: vmv.x.s a0, v9898; RV64-NEXT: ret899 %r = call i64 @llvm.vp.reduce.or.v2i64(i64 %s, <2 x i64> %v, <2 x i1> %m, i32 %evl)900 ret i64 %r901}902 903define signext i64 @vpreduce_xor_v2i64(i64 signext %s, <2 x i64> %v, <2 x i1> %m, i32 zeroext %evl) {904; RV32-LABEL: vpreduce_xor_v2i64:905; RV32: # %bb.0:906; RV32-NEXT: addi sp, sp, -16907; RV32-NEXT: .cfi_def_cfa_offset 16908; RV32-NEXT: sw a0, 8(sp)909; RV32-NEXT: sw a1, 12(sp)910; RV32-NEXT: addi a0, sp, 8911; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma912; RV32-NEXT: vlse64.v v9, (a0), zero913; RV32-NEXT: li a1, 32914; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma915; RV32-NEXT: vredxor.vs v9, v8, v9, v0.t916; RV32-NEXT: vmv.x.s a0, v9917; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma918; RV32-NEXT: vsrl.vx v8, v9, a1919; RV32-NEXT: vmv.x.s a1, v8920; RV32-NEXT: addi sp, sp, 16921; RV32-NEXT: .cfi_def_cfa_offset 0922; RV32-NEXT: ret923;924; RV64-LABEL: vpreduce_xor_v2i64:925; RV64: # %bb.0:926; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma927; RV64-NEXT: vmv.s.x v9, a0928; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma929; RV64-NEXT: vredxor.vs v9, v8, v9, v0.t930; RV64-NEXT: vmv.x.s a0, v9931; RV64-NEXT: ret932 %r = call i64 @llvm.vp.reduce.xor.v2i64(i64 %s, <2 x i64> %v, <2 x i1> %m, i32 %evl)933 ret i64 %r934}935 936define signext i64 @vpreduce_add_v4i64(i64 signext %s, <4 x i64> %v, <4 x i1> %m, i32 zeroext %evl) {937; RV32-LABEL: vpreduce_add_v4i64:938; RV32: # %bb.0:939; RV32-NEXT: addi sp, sp, -16940; RV32-NEXT: .cfi_def_cfa_offset 16941; RV32-NEXT: sw a0, 8(sp)942; RV32-NEXT: sw a1, 12(sp)943; RV32-NEXT: addi a0, sp, 8944; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma945; RV32-NEXT: vlse64.v v10, (a0), zero946; RV32-NEXT: li a1, 32947; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma948; RV32-NEXT: vredsum.vs v10, v8, v10, v0.t949; RV32-NEXT: vmv.x.s a0, v10950; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma951; RV32-NEXT: vsrl.vx v8, v10, a1952; RV32-NEXT: vmv.x.s a1, v8953; RV32-NEXT: addi sp, sp, 16954; RV32-NEXT: .cfi_def_cfa_offset 0955; RV32-NEXT: ret956;957; RV64-LABEL: vpreduce_add_v4i64:958; RV64: # %bb.0:959; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma960; RV64-NEXT: vmv.s.x v10, a0961; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma962; RV64-NEXT: vredsum.vs v10, v8, v10, v0.t963; RV64-NEXT: vmv.x.s a0, v10964; RV64-NEXT: ret965 %r = call i64 @llvm.vp.reduce.add.v4i64(i64 %s, <4 x i64> %v, <4 x i1> %m, i32 %evl)966 ret i64 %r967}968 969define signext i64 @vpreduce_umax_v4i64(i64 signext %s, <4 x i64> %v, <4 x i1> %m, i32 zeroext %evl) {970; RV32-LABEL: vpreduce_umax_v4i64:971; RV32: # %bb.0:972; RV32-NEXT: addi sp, sp, -16973; RV32-NEXT: .cfi_def_cfa_offset 16974; RV32-NEXT: sw a0, 8(sp)975; RV32-NEXT: sw a1, 12(sp)976; RV32-NEXT: addi a0, sp, 8977; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma978; RV32-NEXT: vlse64.v v10, (a0), zero979; RV32-NEXT: li a1, 32980; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma981; RV32-NEXT: vredmaxu.vs v10, v8, v10, v0.t982; RV32-NEXT: vmv.x.s a0, v10983; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma984; RV32-NEXT: vsrl.vx v8, v10, a1985; RV32-NEXT: vmv.x.s a1, v8986; RV32-NEXT: addi sp, sp, 16987; RV32-NEXT: .cfi_def_cfa_offset 0988; RV32-NEXT: ret989;990; RV64-LABEL: vpreduce_umax_v4i64:991; RV64: # %bb.0:992; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma993; RV64-NEXT: vmv.s.x v10, a0994; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma995; RV64-NEXT: vredmaxu.vs v10, v8, v10, v0.t996; RV64-NEXT: vmv.x.s a0, v10997; RV64-NEXT: ret998 %r = call i64 @llvm.vp.reduce.umax.v4i64(i64 %s, <4 x i64> %v, <4 x i1> %m, i32 %evl)999 ret i64 %r1000}1001 1002define signext i64 @vpreduce_smax_v4i64(i64 signext %s, <4 x i64> %v, <4 x i1> %m, i32 zeroext %evl) {1003; RV32-LABEL: vpreduce_smax_v4i64:1004; RV32: # %bb.0:1005; RV32-NEXT: addi sp, sp, -161006; RV32-NEXT: .cfi_def_cfa_offset 161007; RV32-NEXT: sw a0, 8(sp)1008; RV32-NEXT: sw a1, 12(sp)1009; RV32-NEXT: addi a0, sp, 81010; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1011; RV32-NEXT: vlse64.v v10, (a0), zero1012; RV32-NEXT: li a1, 321013; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma1014; RV32-NEXT: vredmax.vs v10, v8, v10, v0.t1015; RV32-NEXT: vmv.x.s a0, v101016; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1017; RV32-NEXT: vsrl.vx v8, v10, a11018; RV32-NEXT: vmv.x.s a1, v81019; RV32-NEXT: addi sp, sp, 161020; RV32-NEXT: .cfi_def_cfa_offset 01021; RV32-NEXT: ret1022;1023; RV64-LABEL: vpreduce_smax_v4i64:1024; RV64: # %bb.0:1025; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma1026; RV64-NEXT: vmv.s.x v10, a01027; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma1028; RV64-NEXT: vredmax.vs v10, v8, v10, v0.t1029; RV64-NEXT: vmv.x.s a0, v101030; RV64-NEXT: ret1031 %r = call i64 @llvm.vp.reduce.smax.v4i64(i64 %s, <4 x i64> %v, <4 x i1> %m, i32 %evl)1032 ret i64 %r1033}1034 1035define signext i64 @vpreduce_umin_v4i64(i64 signext %s, <4 x i64> %v, <4 x i1> %m, i32 zeroext %evl) {1036; RV32-LABEL: vpreduce_umin_v4i64:1037; RV32: # %bb.0:1038; RV32-NEXT: addi sp, sp, -161039; RV32-NEXT: .cfi_def_cfa_offset 161040; RV32-NEXT: sw a0, 8(sp)1041; RV32-NEXT: sw a1, 12(sp)1042; RV32-NEXT: addi a0, sp, 81043; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1044; RV32-NEXT: vlse64.v v10, (a0), zero1045; RV32-NEXT: li a1, 321046; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma1047; RV32-NEXT: vredminu.vs v10, v8, v10, v0.t1048; RV32-NEXT: vmv.x.s a0, v101049; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1050; RV32-NEXT: vsrl.vx v8, v10, a11051; RV32-NEXT: vmv.x.s a1, v81052; RV32-NEXT: addi sp, sp, 161053; RV32-NEXT: .cfi_def_cfa_offset 01054; RV32-NEXT: ret1055;1056; RV64-LABEL: vpreduce_umin_v4i64:1057; RV64: # %bb.0:1058; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma1059; RV64-NEXT: vmv.s.x v10, a01060; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma1061; RV64-NEXT: vredminu.vs v10, v8, v10, v0.t1062; RV64-NEXT: vmv.x.s a0, v101063; RV64-NEXT: ret1064 %r = call i64 @llvm.vp.reduce.umin.v4i64(i64 %s, <4 x i64> %v, <4 x i1> %m, i32 %evl)1065 ret i64 %r1066}1067 1068define signext i64 @vpreduce_smin_v4i64(i64 signext %s, <4 x i64> %v, <4 x i1> %m, i32 zeroext %evl) {1069; RV32-LABEL: vpreduce_smin_v4i64:1070; RV32: # %bb.0:1071; RV32-NEXT: addi sp, sp, -161072; RV32-NEXT: .cfi_def_cfa_offset 161073; RV32-NEXT: sw a0, 8(sp)1074; RV32-NEXT: sw a1, 12(sp)1075; RV32-NEXT: addi a0, sp, 81076; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1077; RV32-NEXT: vlse64.v v10, (a0), zero1078; RV32-NEXT: li a1, 321079; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma1080; RV32-NEXT: vredmin.vs v10, v8, v10, v0.t1081; RV32-NEXT: vmv.x.s a0, v101082; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1083; RV32-NEXT: vsrl.vx v8, v10, a11084; RV32-NEXT: vmv.x.s a1, v81085; RV32-NEXT: addi sp, sp, 161086; RV32-NEXT: .cfi_def_cfa_offset 01087; RV32-NEXT: ret1088;1089; RV64-LABEL: vpreduce_smin_v4i64:1090; RV64: # %bb.0:1091; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma1092; RV64-NEXT: vmv.s.x v10, a01093; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma1094; RV64-NEXT: vredmin.vs v10, v8, v10, v0.t1095; RV64-NEXT: vmv.x.s a0, v101096; RV64-NEXT: ret1097 %r = call i64 @llvm.vp.reduce.smin.v4i64(i64 %s, <4 x i64> %v, <4 x i1> %m, i32 %evl)1098 ret i64 %r1099}1100 1101define signext i64 @vpreduce_and_v4i64(i64 signext %s, <4 x i64> %v, <4 x i1> %m, i32 zeroext %evl) {1102; RV32-LABEL: vpreduce_and_v4i64:1103; RV32: # %bb.0:1104; RV32-NEXT: addi sp, sp, -161105; RV32-NEXT: .cfi_def_cfa_offset 161106; RV32-NEXT: sw a0, 8(sp)1107; RV32-NEXT: sw a1, 12(sp)1108; RV32-NEXT: addi a0, sp, 81109; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1110; RV32-NEXT: vlse64.v v10, (a0), zero1111; RV32-NEXT: li a1, 321112; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma1113; RV32-NEXT: vredand.vs v10, v8, v10, v0.t1114; RV32-NEXT: vmv.x.s a0, v101115; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1116; RV32-NEXT: vsrl.vx v8, v10, a11117; RV32-NEXT: vmv.x.s a1, v81118; RV32-NEXT: addi sp, sp, 161119; RV32-NEXT: .cfi_def_cfa_offset 01120; RV32-NEXT: ret1121;1122; RV64-LABEL: vpreduce_and_v4i64:1123; RV64: # %bb.0:1124; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma1125; RV64-NEXT: vmv.s.x v10, a01126; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma1127; RV64-NEXT: vredand.vs v10, v8, v10, v0.t1128; RV64-NEXT: vmv.x.s a0, v101129; RV64-NEXT: ret1130 %r = call i64 @llvm.vp.reduce.and.v4i64(i64 %s, <4 x i64> %v, <4 x i1> %m, i32 %evl)1131 ret i64 %r1132}1133 1134define signext i64 @vpreduce_or_v4i64(i64 signext %s, <4 x i64> %v, <4 x i1> %m, i32 zeroext %evl) {1135; RV32-LABEL: vpreduce_or_v4i64:1136; RV32: # %bb.0:1137; RV32-NEXT: addi sp, sp, -161138; RV32-NEXT: .cfi_def_cfa_offset 161139; RV32-NEXT: sw a0, 8(sp)1140; RV32-NEXT: sw a1, 12(sp)1141; RV32-NEXT: addi a0, sp, 81142; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1143; RV32-NEXT: vlse64.v v10, (a0), zero1144; RV32-NEXT: li a1, 321145; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma1146; RV32-NEXT: vredor.vs v10, v8, v10, v0.t1147; RV32-NEXT: vmv.x.s a0, v101148; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1149; RV32-NEXT: vsrl.vx v8, v10, a11150; RV32-NEXT: vmv.x.s a1, v81151; RV32-NEXT: addi sp, sp, 161152; RV32-NEXT: .cfi_def_cfa_offset 01153; RV32-NEXT: ret1154;1155; RV64-LABEL: vpreduce_or_v4i64:1156; RV64: # %bb.0:1157; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma1158; RV64-NEXT: vmv.s.x v10, a01159; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma1160; RV64-NEXT: vredor.vs v10, v8, v10, v0.t1161; RV64-NEXT: vmv.x.s a0, v101162; RV64-NEXT: ret1163 %r = call i64 @llvm.vp.reduce.or.v4i64(i64 %s, <4 x i64> %v, <4 x i1> %m, i32 %evl)1164 ret i64 %r1165}1166 1167define signext i64 @vpreduce_xor_v4i64(i64 signext %s, <4 x i64> %v, <4 x i1> %m, i32 zeroext %evl) {1168; RV32-LABEL: vpreduce_xor_v4i64:1169; RV32: # %bb.0:1170; RV32-NEXT: addi sp, sp, -161171; RV32-NEXT: .cfi_def_cfa_offset 161172; RV32-NEXT: sw a0, 8(sp)1173; RV32-NEXT: sw a1, 12(sp)1174; RV32-NEXT: addi a0, sp, 81175; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1176; RV32-NEXT: vlse64.v v10, (a0), zero1177; RV32-NEXT: li a1, 321178; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma1179; RV32-NEXT: vredxor.vs v10, v8, v10, v0.t1180; RV32-NEXT: vmv.x.s a0, v101181; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1182; RV32-NEXT: vsrl.vx v8, v10, a11183; RV32-NEXT: vmv.x.s a1, v81184; RV32-NEXT: addi sp, sp, 161185; RV32-NEXT: .cfi_def_cfa_offset 01186; RV32-NEXT: ret1187;1188; RV64-LABEL: vpreduce_xor_v4i64:1189; RV64: # %bb.0:1190; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma1191; RV64-NEXT: vmv.s.x v10, a01192; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma1193; RV64-NEXT: vredxor.vs v10, v8, v10, v0.t1194; RV64-NEXT: vmv.x.s a0, v101195; RV64-NEXT: ret1196 %r = call i64 @llvm.vp.reduce.xor.v4i64(i64 %s, <4 x i64> %v, <4 x i1> %m, i32 %evl)1197 ret i64 %r1198}1199 1200define i8 @vpreduce_mul_v1i8(i8 %s, <1 x i8> %v, <1 x i1> %m, i32 zeroext %evl) {1201; RV32-LABEL: vpreduce_mul_v1i8:1202; RV32: # %bb.0:1203; RV32-NEXT: addi sp, sp, -161204; RV32-NEXT: .cfi_def_cfa_offset 161205; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1206; RV32-NEXT: .cfi_offset ra, -41207; RV32-NEXT: mv a2, a01208; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma1209; RV32-NEXT: vmv.s.x v9, a11210; RV32-NEXT: vmsne.vi v9, v9, 01211; RV32-NEXT: vmand.mm v0, v9, v01212; RV32-NEXT: vmv.v.i v9, 11213; RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, ma1214; RV32-NEXT: vmerge.vvm v8, v9, v8, v01215; RV32-NEXT: vmv.x.s a0, v81216; RV32-NEXT: mv a1, a21217; RV32-NEXT: call __mulsi31218; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1219; RV32-NEXT: .cfi_restore ra1220; RV32-NEXT: addi sp, sp, 161221; RV32-NEXT: .cfi_def_cfa_offset 01222; RV32-NEXT: ret1223;1224; RV64-LABEL: vpreduce_mul_v1i8:1225; RV64: # %bb.0:1226; RV64-NEXT: addi sp, sp, -161227; RV64-NEXT: .cfi_def_cfa_offset 161228; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1229; RV64-NEXT: .cfi_offset ra, -81230; RV64-NEXT: mv a2, a01231; RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma1232; RV64-NEXT: vmv.s.x v9, a11233; RV64-NEXT: vmsne.vi v9, v9, 01234; RV64-NEXT: vmand.mm v0, v9, v01235; RV64-NEXT: vmv.v.i v9, 11236; RV64-NEXT: vsetvli zero, zero, e8, mf8, ta, ma1237; RV64-NEXT: vmerge.vvm v8, v9, v8, v01238; RV64-NEXT: vmv.x.s a0, v81239; RV64-NEXT: mv a1, a21240; RV64-NEXT: call __muldi31241; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1242; RV64-NEXT: .cfi_restore ra1243; RV64-NEXT: addi sp, sp, 161244; RV64-NEXT: .cfi_def_cfa_offset 01245; RV64-NEXT: ret1246 %r = call i8 @llvm.vp.reduce.mul.v1i8(i8 %s, <1 x i8> %v, <1 x i1> %m, i32 %evl)1247 ret i8 %r1248}1249 1250define signext i8 @vpreduce_mul_v2i8(i8 signext %s, <2 x i8> %v, <2 x i1> %m, i32 zeroext %evl) {1251; RV32-LABEL: vpreduce_mul_v2i8:1252; RV32: # %bb.0:1253; RV32-NEXT: addi sp, sp, -161254; RV32-NEXT: .cfi_def_cfa_offset 161255; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1256; RV32-NEXT: .cfi_offset ra, -41257; RV32-NEXT: mv a2, a01258; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma1259; RV32-NEXT: vid.v v91260; RV32-NEXT: vmsltu.vx v9, v9, a11261; RV32-NEXT: vmand.mm v0, v9, v01262; RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, ma1263; RV32-NEXT: vmv.v.i v9, 11264; RV32-NEXT: vmerge.vvm v8, v9, v8, v01265; RV32-NEXT: vrgather.vi v9, v8, 11266; RV32-NEXT: vmul.vv v8, v8, v91267; RV32-NEXT: vmv.x.s a0, v81268; RV32-NEXT: mv a1, a21269; RV32-NEXT: call __mulsi31270; RV32-NEXT: slli a0, a0, 241271; RV32-NEXT: srai a0, a0, 241272; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1273; RV32-NEXT: .cfi_restore ra1274; RV32-NEXT: addi sp, sp, 161275; RV32-NEXT: .cfi_def_cfa_offset 01276; RV32-NEXT: ret1277;1278; RV64-LABEL: vpreduce_mul_v2i8:1279; RV64: # %bb.0:1280; RV64-NEXT: addi sp, sp, -161281; RV64-NEXT: .cfi_def_cfa_offset 161282; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1283; RV64-NEXT: .cfi_offset ra, -81284; RV64-NEXT: mv a2, a01285; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma1286; RV64-NEXT: vid.v v91287; RV64-NEXT: vmsltu.vx v9, v9, a11288; RV64-NEXT: vmand.mm v0, v9, v01289; RV64-NEXT: vsetvli zero, zero, e8, mf8, ta, ma1290; RV64-NEXT: vmv.v.i v9, 11291; RV64-NEXT: vmerge.vvm v8, v9, v8, v01292; RV64-NEXT: vrgather.vi v9, v8, 11293; RV64-NEXT: vmul.vv v8, v8, v91294; RV64-NEXT: vmv.x.s a0, v81295; RV64-NEXT: mv a1, a21296; RV64-NEXT: call __muldi31297; RV64-NEXT: slli a0, a0, 561298; RV64-NEXT: srai a0, a0, 561299; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1300; RV64-NEXT: .cfi_restore ra1301; RV64-NEXT: addi sp, sp, 161302; RV64-NEXT: .cfi_def_cfa_offset 01303; RV64-NEXT: ret1304 %r = call i8 @llvm.vp.reduce.mul.v2i8(i8 %s, <2 x i8> %v, <2 x i1> %m, i32 %evl)1305 ret i8 %r1306}1307 1308define signext i8 @vpreduce_mul_v4i8(i8 signext %s, <4 x i8> %v, <4 x i1> %m, i32 zeroext %evl) {1309; RV32-LABEL: vpreduce_mul_v4i8:1310; RV32: # %bb.0:1311; RV32-NEXT: addi sp, sp, -161312; RV32-NEXT: .cfi_def_cfa_offset 161313; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1314; RV32-NEXT: .cfi_offset ra, -41315; RV32-NEXT: mv a2, a01316; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma1317; RV32-NEXT: vid.v v91318; RV32-NEXT: vmsltu.vx v9, v9, a11319; RV32-NEXT: vmand.mm v0, v9, v01320; RV32-NEXT: vsetvli zero, zero, e8, mf4, ta, ma1321; RV32-NEXT: vmv.v.i v9, 11322; RV32-NEXT: vmerge.vvm v8, v9, v8, v01323; RV32-NEXT: vslidedown.vi v9, v8, 21324; RV32-NEXT: vmul.vv v8, v8, v91325; RV32-NEXT: vrgather.vi v9, v8, 11326; RV32-NEXT: vmul.vv v8, v8, v91327; RV32-NEXT: vmv.x.s a0, v81328; RV32-NEXT: mv a1, a21329; RV32-NEXT: call __mulsi31330; RV32-NEXT: slli a0, a0, 241331; RV32-NEXT: srai a0, a0, 241332; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1333; RV32-NEXT: .cfi_restore ra1334; RV32-NEXT: addi sp, sp, 161335; RV32-NEXT: .cfi_def_cfa_offset 01336; RV32-NEXT: ret1337;1338; RV64-LABEL: vpreduce_mul_v4i8:1339; RV64: # %bb.0:1340; RV64-NEXT: addi sp, sp, -161341; RV64-NEXT: .cfi_def_cfa_offset 161342; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1343; RV64-NEXT: .cfi_offset ra, -81344; RV64-NEXT: mv a2, a01345; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma1346; RV64-NEXT: vid.v v91347; RV64-NEXT: vmsltu.vx v9, v9, a11348; RV64-NEXT: vmand.mm v0, v9, v01349; RV64-NEXT: vsetvli zero, zero, e8, mf4, ta, ma1350; RV64-NEXT: vmv.v.i v9, 11351; RV64-NEXT: vmerge.vvm v8, v9, v8, v01352; RV64-NEXT: vslidedown.vi v9, v8, 21353; RV64-NEXT: vmul.vv v8, v8, v91354; RV64-NEXT: vrgather.vi v9, v8, 11355; RV64-NEXT: vmul.vv v8, v8, v91356; RV64-NEXT: vmv.x.s a0, v81357; RV64-NEXT: mv a1, a21358; RV64-NEXT: call __muldi31359; RV64-NEXT: slli a0, a0, 561360; RV64-NEXT: srai a0, a0, 561361; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1362; RV64-NEXT: .cfi_restore ra1363; RV64-NEXT: addi sp, sp, 161364; RV64-NEXT: .cfi_def_cfa_offset 01365; RV64-NEXT: ret1366 %r = call i8 @llvm.vp.reduce.mul.v4i8(i8 %s, <4 x i8> %v, <4 x i1> %m, i32 %evl)1367 ret i8 %r1368}1369 1370define signext i8 @vpreduce_mul_v8i8(i8 signext %s, <8 x i8> %v, <8 x i1> %m, i32 zeroext %evl) {1371; RV32-LABEL: vpreduce_mul_v8i8:1372; RV32: # %bb.0:1373; RV32-NEXT: addi sp, sp, -161374; RV32-NEXT: .cfi_def_cfa_offset 161375; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1376; RV32-NEXT: .cfi_offset ra, -41377; RV32-NEXT: mv a2, a01378; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma1379; RV32-NEXT: vid.v v101380; RV32-NEXT: vmsltu.vx v9, v10, a11381; RV32-NEXT: vmand.mm v0, v9, v01382; RV32-NEXT: vsetvli zero, zero, e8, mf2, ta, ma1383; RV32-NEXT: vmv.v.i v9, 11384; RV32-NEXT: vmerge.vvm v8, v9, v8, v01385; RV32-NEXT: vslidedown.vi v9, v8, 41386; RV32-NEXT: vmul.vv v8, v8, v91387; RV32-NEXT: vslidedown.vi v9, v8, 21388; RV32-NEXT: vmul.vv v8, v8, v91389; RV32-NEXT: vrgather.vi v9, v8, 11390; RV32-NEXT: vmul.vv v8, v8, v91391; RV32-NEXT: vmv.x.s a0, v81392; RV32-NEXT: mv a1, a21393; RV32-NEXT: call __mulsi31394; RV32-NEXT: slli a0, a0, 241395; RV32-NEXT: srai a0, a0, 241396; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1397; RV32-NEXT: .cfi_restore ra1398; RV32-NEXT: addi sp, sp, 161399; RV32-NEXT: .cfi_def_cfa_offset 01400; RV32-NEXT: ret1401;1402; RV64-LABEL: vpreduce_mul_v8i8:1403; RV64: # %bb.0:1404; RV64-NEXT: addi sp, sp, -161405; RV64-NEXT: .cfi_def_cfa_offset 161406; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1407; RV64-NEXT: .cfi_offset ra, -81408; RV64-NEXT: mv a2, a01409; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, ma1410; RV64-NEXT: vid.v v101411; RV64-NEXT: vmsltu.vx v9, v10, a11412; RV64-NEXT: vmand.mm v0, v9, v01413; RV64-NEXT: vsetvli zero, zero, e8, mf2, ta, ma1414; RV64-NEXT: vmv.v.i v9, 11415; RV64-NEXT: vmerge.vvm v8, v9, v8, v01416; RV64-NEXT: vslidedown.vi v9, v8, 41417; RV64-NEXT: vmul.vv v8, v8, v91418; RV64-NEXT: vslidedown.vi v9, v8, 21419; RV64-NEXT: vmul.vv v8, v8, v91420; RV64-NEXT: vrgather.vi v9, v8, 11421; RV64-NEXT: vmul.vv v8, v8, v91422; RV64-NEXT: vmv.x.s a0, v81423; RV64-NEXT: mv a1, a21424; RV64-NEXT: call __muldi31425; RV64-NEXT: slli a0, a0, 561426; RV64-NEXT: srai a0, a0, 561427; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1428; RV64-NEXT: .cfi_restore ra1429; RV64-NEXT: addi sp, sp, 161430; RV64-NEXT: .cfi_def_cfa_offset 01431; RV64-NEXT: ret1432 %r = call i8 @llvm.vp.reduce.mul.v8i8(i8 %s, <8 x i8> %v, <8 x i1> %m, i32 %evl)1433 ret i8 %r1434}1435 1436define signext i8 @vpreduce_mul_v16i8(i8 signext %s, <16 x i8> %v, <16 x i1> %m, i32 zeroext %evl) {1437; RV32-LABEL: vpreduce_mul_v16i8:1438; RV32: # %bb.0:1439; RV32-NEXT: addi sp, sp, -161440; RV32-NEXT: .cfi_def_cfa_offset 161441; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1442; RV32-NEXT: .cfi_offset ra, -41443; RV32-NEXT: mv a2, a01444; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma1445; RV32-NEXT: vid.v v121446; RV32-NEXT: vmsltu.vx v9, v12, a11447; RV32-NEXT: vmand.mm v0, v9, v01448; RV32-NEXT: vsetvli zero, zero, e8, m1, ta, ma1449; RV32-NEXT: vmv.v.i v9, 11450; RV32-NEXT: vmerge.vvm v8, v9, v8, v01451; RV32-NEXT: vslidedown.vi v9, v8, 81452; RV32-NEXT: vmul.vv v8, v8, v91453; RV32-NEXT: vslidedown.vi v9, v8, 41454; RV32-NEXT: vmul.vv v8, v8, v91455; RV32-NEXT: vslidedown.vi v9, v8, 21456; RV32-NEXT: vmul.vv v8, v8, v91457; RV32-NEXT: vrgather.vi v9, v8, 11458; RV32-NEXT: vmul.vv v8, v8, v91459; RV32-NEXT: vmv.x.s a0, v81460; RV32-NEXT: mv a1, a21461; RV32-NEXT: call __mulsi31462; RV32-NEXT: slli a0, a0, 241463; RV32-NEXT: srai a0, a0, 241464; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1465; RV32-NEXT: .cfi_restore ra1466; RV32-NEXT: addi sp, sp, 161467; RV32-NEXT: .cfi_def_cfa_offset 01468; RV32-NEXT: ret1469;1470; RV64-LABEL: vpreduce_mul_v16i8:1471; RV64: # %bb.0:1472; RV64-NEXT: addi sp, sp, -161473; RV64-NEXT: .cfi_def_cfa_offset 161474; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1475; RV64-NEXT: .cfi_offset ra, -81476; RV64-NEXT: mv a2, a01477; RV64-NEXT: vsetivli zero, 16, e32, m4, ta, ma1478; RV64-NEXT: vid.v v121479; RV64-NEXT: vmsltu.vx v9, v12, a11480; RV64-NEXT: vmand.mm v0, v9, v01481; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, ma1482; RV64-NEXT: vmv.v.i v9, 11483; RV64-NEXT: vmerge.vvm v8, v9, v8, v01484; RV64-NEXT: vslidedown.vi v9, v8, 81485; RV64-NEXT: vmul.vv v8, v8, v91486; RV64-NEXT: vslidedown.vi v9, v8, 41487; RV64-NEXT: vmul.vv v8, v8, v91488; RV64-NEXT: vslidedown.vi v9, v8, 21489; RV64-NEXT: vmul.vv v8, v8, v91490; RV64-NEXT: vrgather.vi v9, v8, 11491; RV64-NEXT: vmul.vv v8, v8, v91492; RV64-NEXT: vmv.x.s a0, v81493; RV64-NEXT: mv a1, a21494; RV64-NEXT: call __muldi31495; RV64-NEXT: slli a0, a0, 561496; RV64-NEXT: srai a0, a0, 561497; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1498; RV64-NEXT: .cfi_restore ra1499; RV64-NEXT: addi sp, sp, 161500; RV64-NEXT: .cfi_def_cfa_offset 01501; RV64-NEXT: ret1502 %r = call i8 @llvm.vp.reduce.mul.v16i8(i8 %s, <16 x i8> %v, <16 x i1> %m, i32 %evl)1503 ret i8 %r1504}1505 1506define signext i8 @vpreduce_mul_v32i8(i8 signext %s, <32 x i8> %v, <32 x i1> %m, i32 zeroext %evl) {1507; RV32-LABEL: vpreduce_mul_v32i8:1508; RV32: # %bb.0:1509; RV32-NEXT: addi sp, sp, -161510; RV32-NEXT: .cfi_def_cfa_offset 161511; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1512; RV32-NEXT: .cfi_offset ra, -41513; RV32-NEXT: mv a2, a01514; RV32-NEXT: li a0, 321515; RV32-NEXT: vsetvli zero, a0, e32, m8, ta, ma1516; RV32-NEXT: vid.v v161517; RV32-NEXT: vmsltu.vx v10, v16, a11518; RV32-NEXT: vmand.mm v0, v10, v01519; RV32-NEXT: vsetvli zero, zero, e8, m2, ta, ma1520; RV32-NEXT: vmv.v.i v10, 11521; RV32-NEXT: vmerge.vvm v8, v10, v8, v01522; RV32-NEXT: vslidedown.vi v10, v8, 161523; RV32-NEXT: vmul.vv v8, v8, v101524; RV32-NEXT: vslidedown.vi v10, v8, 81525; RV32-NEXT: vmul.vv v8, v8, v101526; RV32-NEXT: vslidedown.vi v10, v8, 41527; RV32-NEXT: vmul.vv v8, v8, v101528; RV32-NEXT: vslidedown.vi v10, v8, 21529; RV32-NEXT: vmul.vv v8, v8, v101530; RV32-NEXT: vrgather.vi v10, v8, 11531; RV32-NEXT: vmul.vv v8, v8, v101532; RV32-NEXT: vmv.x.s a0, v81533; RV32-NEXT: mv a1, a21534; RV32-NEXT: call __mulsi31535; RV32-NEXT: slli a0, a0, 241536; RV32-NEXT: srai a0, a0, 241537; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1538; RV32-NEXT: .cfi_restore ra1539; RV32-NEXT: addi sp, sp, 161540; RV32-NEXT: .cfi_def_cfa_offset 01541; RV32-NEXT: ret1542;1543; RV64-LABEL: vpreduce_mul_v32i8:1544; RV64: # %bb.0:1545; RV64-NEXT: addi sp, sp, -161546; RV64-NEXT: .cfi_def_cfa_offset 161547; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1548; RV64-NEXT: .cfi_offset ra, -81549; RV64-NEXT: mv a2, a01550; RV64-NEXT: li a0, 321551; RV64-NEXT: vsetvli zero, a0, e32, m8, ta, ma1552; RV64-NEXT: vid.v v161553; RV64-NEXT: vmsltu.vx v10, v16, a11554; RV64-NEXT: vmand.mm v0, v10, v01555; RV64-NEXT: vsetvli zero, zero, e8, m2, ta, ma1556; RV64-NEXT: vmv.v.i v10, 11557; RV64-NEXT: vmerge.vvm v8, v10, v8, v01558; RV64-NEXT: vslidedown.vi v10, v8, 161559; RV64-NEXT: vmul.vv v8, v8, v101560; RV64-NEXT: vslidedown.vi v10, v8, 81561; RV64-NEXT: vmul.vv v8, v8, v101562; RV64-NEXT: vslidedown.vi v10, v8, 41563; RV64-NEXT: vmul.vv v8, v8, v101564; RV64-NEXT: vslidedown.vi v10, v8, 21565; RV64-NEXT: vmul.vv v8, v8, v101566; RV64-NEXT: vrgather.vi v10, v8, 11567; RV64-NEXT: vmul.vv v8, v8, v101568; RV64-NEXT: vmv.x.s a0, v81569; RV64-NEXT: mv a1, a21570; RV64-NEXT: call __muldi31571; RV64-NEXT: slli a0, a0, 561572; RV64-NEXT: srai a0, a0, 561573; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1574; RV64-NEXT: .cfi_restore ra1575; RV64-NEXT: addi sp, sp, 161576; RV64-NEXT: .cfi_def_cfa_offset 01577; RV64-NEXT: ret1578 %r = call i8 @llvm.vp.reduce.mul.v32i8(i8 %s, <32 x i8> %v, <32 x i1> %m, i32 %evl)1579 ret i8 %r1580}1581 1582define signext i8 @vpreduce_mul_v64i8(i8 signext %s, <64 x i8> %v, <64 x i1> %m, i32 zeroext %evl) {1583; RV32-LABEL: vpreduce_mul_v64i8:1584; RV32: # %bb.0:1585; RV32-NEXT: addi sp, sp, -161586; RV32-NEXT: .cfi_def_cfa_offset 161587; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1588; RV32-NEXT: .cfi_offset ra, -41589; RV32-NEXT: mv a2, a01590; RV32-NEXT: li a0, 321591; RV32-NEXT: vsetvli zero, a0, e32, m8, ta, ma1592; RV32-NEXT: vid.v v161593; RV32-NEXT: vmsltu.vx v12, v16, a11594; RV32-NEXT: vadd.vx v16, v16, a01595; RV32-NEXT: vmsltu.vx v13, v16, a11596; RV32-NEXT: li a1, 641597; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma1598; RV32-NEXT: vslideup.vi v12, v13, 41599; RV32-NEXT: vsetvli zero, a1, e8, m4, ta, ma1600; RV32-NEXT: vmand.mm v0, v12, v01601; RV32-NEXT: vmv.v.i v12, 11602; RV32-NEXT: vmerge.vvm v8, v12, v8, v01603; RV32-NEXT: vslidedown.vx v12, v8, a01604; RV32-NEXT: vmul.vv v8, v8, v121605; RV32-NEXT: vslidedown.vi v12, v8, 161606; RV32-NEXT: vmul.vv v8, v8, v121607; RV32-NEXT: vslidedown.vi v12, v8, 81608; RV32-NEXT: vmul.vv v8, v8, v121609; RV32-NEXT: vslidedown.vi v12, v8, 41610; RV32-NEXT: vmul.vv v8, v8, v121611; RV32-NEXT: vslidedown.vi v12, v8, 21612; RV32-NEXT: vmul.vv v8, v8, v121613; RV32-NEXT: vrgather.vi v12, v8, 11614; RV32-NEXT: vmul.vv v8, v8, v121615; RV32-NEXT: vmv.x.s a0, v81616; RV32-NEXT: mv a1, a21617; RV32-NEXT: call __mulsi31618; RV32-NEXT: slli a0, a0, 241619; RV32-NEXT: srai a0, a0, 241620; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1621; RV32-NEXT: .cfi_restore ra1622; RV32-NEXT: addi sp, sp, 161623; RV32-NEXT: .cfi_def_cfa_offset 01624; RV32-NEXT: ret1625;1626; RV64-LABEL: vpreduce_mul_v64i8:1627; RV64: # %bb.0:1628; RV64-NEXT: addi sp, sp, -161629; RV64-NEXT: .cfi_def_cfa_offset 161630; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1631; RV64-NEXT: .cfi_offset ra, -81632; RV64-NEXT: mv a2, a01633; RV64-NEXT: li a0, 321634; RV64-NEXT: vsetvli zero, a0, e32, m8, ta, ma1635; RV64-NEXT: vid.v v161636; RV64-NEXT: vmsltu.vx v12, v16, a11637; RV64-NEXT: vadd.vx v16, v16, a01638; RV64-NEXT: vmsltu.vx v13, v16, a11639; RV64-NEXT: li a1, 641640; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, ma1641; RV64-NEXT: vslideup.vi v12, v13, 41642; RV64-NEXT: vsetvli zero, a1, e8, m4, ta, ma1643; RV64-NEXT: vmand.mm v0, v12, v01644; RV64-NEXT: vmv.v.i v12, 11645; RV64-NEXT: vmerge.vvm v8, v12, v8, v01646; RV64-NEXT: vslidedown.vx v12, v8, a01647; RV64-NEXT: vmul.vv v8, v8, v121648; RV64-NEXT: vslidedown.vi v12, v8, 161649; RV64-NEXT: vmul.vv v8, v8, v121650; RV64-NEXT: vslidedown.vi v12, v8, 81651; RV64-NEXT: vmul.vv v8, v8, v121652; RV64-NEXT: vslidedown.vi v12, v8, 41653; RV64-NEXT: vmul.vv v8, v8, v121654; RV64-NEXT: vslidedown.vi v12, v8, 21655; RV64-NEXT: vmul.vv v8, v8, v121656; RV64-NEXT: vrgather.vi v12, v8, 11657; RV64-NEXT: vmul.vv v8, v8, v121658; RV64-NEXT: vmv.x.s a0, v81659; RV64-NEXT: mv a1, a21660; RV64-NEXT: call __muldi31661; RV64-NEXT: slli a0, a0, 561662; RV64-NEXT: srai a0, a0, 561663; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1664; RV64-NEXT: .cfi_restore ra1665; RV64-NEXT: addi sp, sp, 161666; RV64-NEXT: .cfi_def_cfa_offset 01667; RV64-NEXT: ret1668 %r = call i8 @llvm.vp.reduce.mul.v64i8(i8 %s, <64 x i8> %v, <64 x i1> %m, i32 %evl)1669 ret i8 %r1670}1671 1672; Test start value is the first element of a vector.1673define zeroext i8 @front_ele_v4i8(<4 x i8> %v, <4 x i1> %m, i32 zeroext %evl) {1674; CHECK-LABEL: front_ele_v4i8:1675; CHECK: # %bb.0:1676; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma1677; CHECK-NEXT: vredand.vs v8, v8, v8, v0.t1678; CHECK-NEXT: vmv.x.s a0, v81679; CHECK-NEXT: zext.b a0, a01680; CHECK-NEXT: ret1681 %s = extractelement <4 x i8> %v, i64 01682 %r = call i8 @llvm.vp.reduce.and.v4i8(i8 %s, <4 x i8> %v, <4 x i1> %m, i32 %evl)1683 ret i8 %r1684}1685 1686; Test start value is the first element of a vector which longer than M1.1687define zeroext i8 @front_ele_v32i8(<32 x i8> %v, <32 x i1> %m, i32 zeroext %evl) {1688; CHECK-LABEL: front_ele_v32i8:1689; CHECK: # %bb.0:1690; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma1691; CHECK-NEXT: vredand.vs v8, v8, v8, v0.t1692; CHECK-NEXT: vmv.x.s a0, v81693; CHECK-NEXT: zext.b a0, a01694; CHECK-NEXT: ret1695 %s = extractelement <32 x i8> %v, i64 01696 %r = call i8 @llvm.vp.reduce.and.v32i8(i8 %s, <32 x i8> %v, <32 x i1> %m, i32 %evl)1697 ret i8 %r1698}1699