6061 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV323; RUN: llc -mtriple=riscv64 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV644 5define i8 @vreduce_add_v1i8(<1 x i8> %v) {6; CHECK-LABEL: vreduce_add_v1i8:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma9; CHECK-NEXT: vmv.x.s a0, v810; CHECK-NEXT: ret11 %red = call i8 @llvm.vector.reduce.add.v1i8(<1 x i8> %v)12 ret i8 %red13}14 15define i8 @vreduce_add_v2i8(ptr %x) {16; CHECK-LABEL: vreduce_add_v2i8:17; CHECK: # %bb.0:18; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma19; CHECK-NEXT: vle8.v v8, (a0)20; CHECK-NEXT: vmv.s.x v9, zero21; CHECK-NEXT: vredsum.vs v8, v8, v922; CHECK-NEXT: vmv.x.s a0, v823; CHECK-NEXT: ret24 %v = load <2 x i8>, ptr %x25 %red = call i8 @llvm.vector.reduce.add.v2i8(<2 x i8> %v)26 ret i8 %red27}28 29define i8 @vreduce_add_v3i8(ptr %x) {30; CHECK-LABEL: vreduce_add_v3i8:31; CHECK: # %bb.0:32; CHECK-NEXT: vsetivli zero, 3, e8, mf4, ta, ma33; CHECK-NEXT: vle8.v v8, (a0)34; CHECK-NEXT: vmv.s.x v9, zero35; CHECK-NEXT: vredsum.vs v8, v8, v936; CHECK-NEXT: vmv.x.s a0, v837; CHECK-NEXT: ret38 %v = load <3 x i8>, ptr %x39 %red = call i8 @llvm.vector.reduce.add.v3i8(<3 x i8> %v)40 ret i8 %red41}42 43define i8 @vreduce_add_v4i8(ptr %x) {44; CHECK-LABEL: vreduce_add_v4i8:45; CHECK: # %bb.0:46; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma47; CHECK-NEXT: vle8.v v8, (a0)48; CHECK-NEXT: vmv.s.x v9, zero49; CHECK-NEXT: vredsum.vs v8, v8, v950; CHECK-NEXT: vmv.x.s a0, v851; CHECK-NEXT: ret52 %v = load <4 x i8>, ptr %x53 %red = call i8 @llvm.vector.reduce.add.v4i8(<4 x i8> %v)54 ret i8 %red55}56 57define i8 @vreduce_add_v8i8(ptr %x) {58; CHECK-LABEL: vreduce_add_v8i8:59; CHECK: # %bb.0:60; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma61; CHECK-NEXT: vle8.v v8, (a0)62; CHECK-NEXT: vmv.s.x v9, zero63; CHECK-NEXT: vredsum.vs v8, v8, v964; CHECK-NEXT: vmv.x.s a0, v865; CHECK-NEXT: ret66 %v = load <8 x i8>, ptr %x67 %red = call i8 @llvm.vector.reduce.add.v8i8(<8 x i8> %v)68 ret i8 %red69}70 71define i8 @vreduce_add_v16i8(ptr %x) {72; CHECK-LABEL: vreduce_add_v16i8:73; CHECK: # %bb.0:74; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma75; CHECK-NEXT: vle8.v v8, (a0)76; CHECK-NEXT: vmv.s.x v9, zero77; CHECK-NEXT: vredsum.vs v8, v8, v978; CHECK-NEXT: vmv.x.s a0, v879; CHECK-NEXT: ret80 %v = load <16 x i8>, ptr %x81 %red = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %v)82 ret i8 %red83}84 85define i8 @vreduce_add_v32i8(ptr %x) {86; CHECK-LABEL: vreduce_add_v32i8:87; CHECK: # %bb.0:88; CHECK-NEXT: li a1, 3289; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma90; CHECK-NEXT: vle8.v v8, (a0)91; CHECK-NEXT: vmv.s.x v10, zero92; CHECK-NEXT: vredsum.vs v8, v8, v1093; CHECK-NEXT: vmv.x.s a0, v894; CHECK-NEXT: ret95 %v = load <32 x i8>, ptr %x96 %red = call i8 @llvm.vector.reduce.add.v32i8(<32 x i8> %v)97 ret i8 %red98}99 100define i8 @vreduce_add_v64i8(ptr %x) {101; CHECK-LABEL: vreduce_add_v64i8:102; CHECK: # %bb.0:103; CHECK-NEXT: li a1, 64104; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma105; CHECK-NEXT: vle8.v v8, (a0)106; CHECK-NEXT: vmv.s.x v12, zero107; CHECK-NEXT: vredsum.vs v8, v8, v12108; CHECK-NEXT: vmv.x.s a0, v8109; CHECK-NEXT: ret110 %v = load <64 x i8>, ptr %x111 %red = call i8 @llvm.vector.reduce.add.v64i8(<64 x i8> %v)112 ret i8 %red113}114 115define i8 @vreduce_add_v128i8(ptr %x) {116; CHECK-LABEL: vreduce_add_v128i8:117; CHECK: # %bb.0:118; CHECK-NEXT: li a1, 128119; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma120; CHECK-NEXT: vle8.v v8, (a0)121; CHECK-NEXT: vmv.s.x v16, zero122; CHECK-NEXT: vredsum.vs v8, v8, v16123; CHECK-NEXT: vmv.x.s a0, v8124; CHECK-NEXT: ret125 %v = load <128 x i8>, ptr %x126 %red = call i8 @llvm.vector.reduce.add.v128i8(<128 x i8> %v)127 ret i8 %red128}129 130define i8 @vreduce_add_v256i8(ptr %x) {131; CHECK-LABEL: vreduce_add_v256i8:132; CHECK: # %bb.0:133; CHECK-NEXT: li a1, 128134; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma135; CHECK-NEXT: vle8.v v8, (a0)136; CHECK-NEXT: addi a0, a0, 128137; CHECK-NEXT: vle8.v v16, (a0)138; CHECK-NEXT: vadd.vv v8, v8, v16139; CHECK-NEXT: vmv.s.x v16, zero140; CHECK-NEXT: vredsum.vs v8, v8, v16141; CHECK-NEXT: vmv.x.s a0, v8142; CHECK-NEXT: ret143 %v = load <256 x i8>, ptr %x144 %red = call i8 @llvm.vector.reduce.add.v256i8(<256 x i8> %v)145 ret i8 %red146}147 148define i16 @vreduce_add_v1i16(<1 x i16> %v) {149; CHECK-LABEL: vreduce_add_v1i16:150; CHECK: # %bb.0:151; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma152; CHECK-NEXT: vmv.x.s a0, v8153; CHECK-NEXT: ret154 %red = call i16 @llvm.vector.reduce.add.v1i16(<1 x i16> %v)155 ret i16 %red156}157 158define i16 @vwreduce_add_v1i16(<1 x i8> %v) {159; CHECK-LABEL: vwreduce_add_v1i16:160; CHECK: # %bb.0:161; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma162; CHECK-NEXT: vsext.vf2 v9, v8163; CHECK-NEXT: vmv.x.s a0, v9164; CHECK-NEXT: ret165 %e = sext <1 x i8> %v to <1 x i16>166 %red = call i16 @llvm.vector.reduce.add.v1i16(<1 x i16> %e)167 ret i16 %red168}169 170define i16 @vwreduce_uadd_v1i16(<1 x i8> %v) {171; CHECK-LABEL: vwreduce_uadd_v1i16:172; CHECK: # %bb.0:173; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma174; CHECK-NEXT: vzext.vf2 v9, v8175; CHECK-NEXT: vmv.x.s a0, v9176; CHECK-NEXT: ret177 %e = zext <1 x i8> %v to <1 x i16>178 %red = call i16 @llvm.vector.reduce.add.v1i16(<1 x i16> %e)179 ret i16 %red180}181 182define i16 @vreduce_add_v2i16(ptr %x) {183; CHECK-LABEL: vreduce_add_v2i16:184; CHECK: # %bb.0:185; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma186; CHECK-NEXT: vle16.v v8, (a0)187; CHECK-NEXT: vmv.s.x v9, zero188; CHECK-NEXT: vredsum.vs v8, v8, v9189; CHECK-NEXT: vmv.x.s a0, v8190; CHECK-NEXT: ret191 %v = load <2 x i16>, ptr %x192 %red = call i16 @llvm.vector.reduce.add.v2i16(<2 x i16> %v)193 ret i16 %red194}195 196define i16 @vwreduce_add_v2i16(ptr %x) {197; CHECK-LABEL: vwreduce_add_v2i16:198; CHECK: # %bb.0:199; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma200; CHECK-NEXT: vle8.v v8, (a0)201; CHECK-NEXT: vmv.s.x v9, zero202; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma203; CHECK-NEXT: vwredsum.vs v8, v8, v9204; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma205; CHECK-NEXT: vmv.x.s a0, v8206; CHECK-NEXT: ret207 %v = load <2 x i8>, ptr %x208 %e = sext <2 x i8> %v to <2 x i16>209 %red = call i16 @llvm.vector.reduce.add.v2i16(<2 x i16> %e)210 ret i16 %red211}212 213define i16 @vwreduce_uadd_v2i16(ptr %x) {214; CHECK-LABEL: vwreduce_uadd_v2i16:215; CHECK: # %bb.0:216; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma217; CHECK-NEXT: vle8.v v8, (a0)218; CHECK-NEXT: vmv.s.x v9, zero219; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma220; CHECK-NEXT: vwredsumu.vs v8, v8, v9221; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma222; CHECK-NEXT: vmv.x.s a0, v8223; CHECK-NEXT: ret224 %v = load <2 x i8>, ptr %x225 %e = zext <2 x i8> %v to <2 x i16>226 %red = call i16 @llvm.vector.reduce.add.v2i16(<2 x i16> %e)227 ret i16 %red228}229 230define i16 @vreduce_add_v4i16(ptr %x) {231; CHECK-LABEL: vreduce_add_v4i16:232; CHECK: # %bb.0:233; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma234; CHECK-NEXT: vle16.v v8, (a0)235; CHECK-NEXT: vmv.s.x v9, zero236; CHECK-NEXT: vredsum.vs v8, v8, v9237; CHECK-NEXT: vmv.x.s a0, v8238; CHECK-NEXT: ret239 %v = load <4 x i16>, ptr %x240 %red = call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> %v)241 ret i16 %red242}243 244define i16 @vwreduce_add_v4i16(ptr %x) {245; CHECK-LABEL: vwreduce_add_v4i16:246; CHECK: # %bb.0:247; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma248; CHECK-NEXT: vle8.v v8, (a0)249; CHECK-NEXT: vmv.s.x v9, zero250; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma251; CHECK-NEXT: vwredsum.vs v8, v8, v9252; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma253; CHECK-NEXT: vmv.x.s a0, v8254; CHECK-NEXT: ret255 %v = load <4 x i8>, ptr %x256 %e = sext <4 x i8> %v to <4 x i16>257 %red = call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> %e)258 ret i16 %red259}260 261define i16 @vwreduce_uadd_v4i16(ptr %x) {262; CHECK-LABEL: vwreduce_uadd_v4i16:263; CHECK: # %bb.0:264; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma265; CHECK-NEXT: vle8.v v8, (a0)266; CHECK-NEXT: vmv.s.x v9, zero267; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma268; CHECK-NEXT: vwredsumu.vs v8, v8, v9269; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma270; CHECK-NEXT: vmv.x.s a0, v8271; CHECK-NEXT: ret272 %v = load <4 x i8>, ptr %x273 %e = zext <4 x i8> %v to <4 x i16>274 %red = call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> %e)275 ret i16 %red276}277 278define i16 @vreduce_add_v8i16(ptr %x) {279; CHECK-LABEL: vreduce_add_v8i16:280; CHECK: # %bb.0:281; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma282; CHECK-NEXT: vle16.v v8, (a0)283; CHECK-NEXT: vmv.s.x v9, zero284; CHECK-NEXT: vredsum.vs v8, v8, v9285; CHECK-NEXT: vmv.x.s a0, v8286; CHECK-NEXT: ret287 %v = load <8 x i16>, ptr %x288 %red = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %v)289 ret i16 %red290}291 292define i16 @vwreduce_add_v8i16(ptr %x) {293; CHECK-LABEL: vwreduce_add_v8i16:294; CHECK: # %bb.0:295; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma296; CHECK-NEXT: vle8.v v8, (a0)297; CHECK-NEXT: vmv.s.x v9, zero298; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma299; CHECK-NEXT: vwredsum.vs v8, v8, v9300; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma301; CHECK-NEXT: vmv.x.s a0, v8302; CHECK-NEXT: ret303 %v = load <8 x i8>, ptr %x304 %e = sext <8 x i8> %v to <8 x i16>305 %red = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %e)306 ret i16 %red307}308 309define i16 @vwreduce_uadd_v8i16(ptr %x) {310; CHECK-LABEL: vwreduce_uadd_v8i16:311; CHECK: # %bb.0:312; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma313; CHECK-NEXT: vle8.v v8, (a0)314; CHECK-NEXT: vmv.s.x v9, zero315; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma316; CHECK-NEXT: vwredsumu.vs v8, v8, v9317; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma318; CHECK-NEXT: vmv.x.s a0, v8319; CHECK-NEXT: ret320 %v = load <8 x i8>, ptr %x321 %e = zext <8 x i8> %v to <8 x i16>322 %red = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %e)323 ret i16 %red324}325 326define i16 @vreduce_add_v16i16(ptr %x) {327; CHECK-LABEL: vreduce_add_v16i16:328; CHECK: # %bb.0:329; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma330; CHECK-NEXT: vle16.v v8, (a0)331; CHECK-NEXT: vmv.s.x v10, zero332; CHECK-NEXT: vredsum.vs v8, v8, v10333; CHECK-NEXT: vmv.x.s a0, v8334; CHECK-NEXT: ret335 %v = load <16 x i16>, ptr %x336 %red = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %v)337 ret i16 %red338}339 340define i16 @vwreduce_add_v16i16(ptr %x) {341; CHECK-LABEL: vwreduce_add_v16i16:342; CHECK: # %bb.0:343; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma344; CHECK-NEXT: vle8.v v8, (a0)345; CHECK-NEXT: vmv.s.x v9, zero346; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma347; CHECK-NEXT: vwredsum.vs v8, v8, v9348; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma349; CHECK-NEXT: vmv.x.s a0, v8350; CHECK-NEXT: ret351 %v = load <16 x i8>, ptr %x352 %e = sext <16 x i8> %v to <16 x i16>353 %red = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %e)354 ret i16 %red355}356 357define i16 @vwreduce_uadd_v16i16(ptr %x) {358; CHECK-LABEL: vwreduce_uadd_v16i16:359; CHECK: # %bb.0:360; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma361; CHECK-NEXT: vle8.v v8, (a0)362; CHECK-NEXT: vmv.s.x v9, zero363; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma364; CHECK-NEXT: vwredsumu.vs v8, v8, v9365; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma366; CHECK-NEXT: vmv.x.s a0, v8367; CHECK-NEXT: ret368 %v = load <16 x i8>, ptr %x369 %e = zext <16 x i8> %v to <16 x i16>370 %red = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %e)371 ret i16 %red372}373 374define i16 @vreduce_add_v32i16(ptr %x) {375; CHECK-LABEL: vreduce_add_v32i16:376; CHECK: # %bb.0:377; CHECK-NEXT: li a1, 32378; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma379; CHECK-NEXT: vle16.v v8, (a0)380; CHECK-NEXT: vmv.s.x v12, zero381; CHECK-NEXT: vredsum.vs v8, v8, v12382; CHECK-NEXT: vmv.x.s a0, v8383; CHECK-NEXT: ret384 %v = load <32 x i16>, ptr %x385 %red = call i16 @llvm.vector.reduce.add.v32i16(<32 x i16> %v)386 ret i16 %red387}388 389define i16 @vwreduce_add_v32i16(ptr %x) {390; CHECK-LABEL: vwreduce_add_v32i16:391; CHECK: # %bb.0:392; CHECK-NEXT: li a1, 32393; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma394; CHECK-NEXT: vle8.v v8, (a0)395; CHECK-NEXT: vmv.s.x v10, zero396; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma397; CHECK-NEXT: vwredsum.vs v8, v8, v10398; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma399; CHECK-NEXT: vmv.x.s a0, v8400; CHECK-NEXT: ret401 %v = load <32 x i8>, ptr %x402 %e = sext <32 x i8> %v to <32 x i16>403 %red = call i16 @llvm.vector.reduce.add.v32i16(<32 x i16> %e)404 ret i16 %red405}406 407define i16 @vwreduce_uadd_v32i16(ptr %x) {408; CHECK-LABEL: vwreduce_uadd_v32i16:409; CHECK: # %bb.0:410; CHECK-NEXT: li a1, 32411; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma412; CHECK-NEXT: vle8.v v8, (a0)413; CHECK-NEXT: vmv.s.x v10, zero414; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma415; CHECK-NEXT: vwredsumu.vs v8, v8, v10416; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma417; CHECK-NEXT: vmv.x.s a0, v8418; CHECK-NEXT: ret419 %v = load <32 x i8>, ptr %x420 %e = zext <32 x i8> %v to <32 x i16>421 %red = call i16 @llvm.vector.reduce.add.v32i16(<32 x i16> %e)422 ret i16 %red423}424 425define i16 @vreduce_add_v64i16(ptr %x) {426; CHECK-LABEL: vreduce_add_v64i16:427; CHECK: # %bb.0:428; CHECK-NEXT: li a1, 64429; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma430; CHECK-NEXT: vle16.v v8, (a0)431; CHECK-NEXT: vmv.s.x v16, zero432; CHECK-NEXT: vredsum.vs v8, v8, v16433; CHECK-NEXT: vmv.x.s a0, v8434; CHECK-NEXT: ret435 %v = load <64 x i16>, ptr %x436 %red = call i16 @llvm.vector.reduce.add.v64i16(<64 x i16> %v)437 ret i16 %red438}439 440define i16 @vwreduce_add_v64i16(ptr %x) {441; CHECK-LABEL: vwreduce_add_v64i16:442; CHECK: # %bb.0:443; CHECK-NEXT: li a1, 64444; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma445; CHECK-NEXT: vle8.v v8, (a0)446; CHECK-NEXT: vmv.s.x v12, zero447; CHECK-NEXT: vsetvli zero, zero, e8, m4, ta, ma448; CHECK-NEXT: vwredsum.vs v8, v8, v12449; CHECK-NEXT: vsetvli zero, zero, e16, m8, ta, ma450; CHECK-NEXT: vmv.x.s a0, v8451; CHECK-NEXT: ret452 %v = load <64 x i8>, ptr %x453 %e = sext <64 x i8> %v to <64 x i16>454 %red = call i16 @llvm.vector.reduce.add.v64i16(<64 x i16> %e)455 ret i16 %red456}457 458define i16 @vwreduce_uadd_v64i16(ptr %x) {459; CHECK-LABEL: vwreduce_uadd_v64i16:460; CHECK: # %bb.0:461; CHECK-NEXT: li a1, 64462; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma463; CHECK-NEXT: vle8.v v8, (a0)464; CHECK-NEXT: vmv.s.x v12, zero465; CHECK-NEXT: vsetvli zero, zero, e8, m4, ta, ma466; CHECK-NEXT: vwredsumu.vs v8, v8, v12467; CHECK-NEXT: vsetvli zero, zero, e16, m8, ta, ma468; CHECK-NEXT: vmv.x.s a0, v8469; CHECK-NEXT: ret470 %v = load <64 x i8>, ptr %x471 %e = zext <64 x i8> %v to <64 x i16>472 %red = call i16 @llvm.vector.reduce.add.v64i16(<64 x i16> %e)473 ret i16 %red474}475 476define i16 @vreduce_add_v128i16(ptr %x) {477; CHECK-LABEL: vreduce_add_v128i16:478; CHECK: # %bb.0:479; CHECK-NEXT: li a1, 64480; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma481; CHECK-NEXT: vle16.v v8, (a0)482; CHECK-NEXT: addi a0, a0, 128483; CHECK-NEXT: vle16.v v16, (a0)484; CHECK-NEXT: vadd.vv v8, v8, v16485; CHECK-NEXT: vmv.s.x v16, zero486; CHECK-NEXT: vredsum.vs v8, v8, v16487; CHECK-NEXT: vmv.x.s a0, v8488; CHECK-NEXT: ret489 %v = load <128 x i16>, ptr %x490 %red = call i16 @llvm.vector.reduce.add.v128i16(<128 x i16> %v)491 ret i16 %red492}493 494define i16 @vwreduce_add_v128i16(ptr %x) {495; CHECK-LABEL: vwreduce_add_v128i16:496; CHECK: # %bb.0:497; CHECK-NEXT: li a1, 128498; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma499; CHECK-NEXT: vle8.v v8, (a0)500; CHECK-NEXT: li a0, 64501; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma502; CHECK-NEXT: vslidedown.vx v16, v8, a0503; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma504; CHECK-NEXT: vwadd.vv v24, v8, v16505; CHECK-NEXT: vsetvli zero, zero, e16, m8, ta, ma506; CHECK-NEXT: vmv.s.x v8, zero507; CHECK-NEXT: vredsum.vs v8, v24, v8508; CHECK-NEXT: vmv.x.s a0, v8509; CHECK-NEXT: ret510 %v = load <128 x i8>, ptr %x511 %e = sext <128 x i8> %v to <128 x i16>512 %red = call i16 @llvm.vector.reduce.add.v128i16(<128 x i16> %e)513 ret i16 %red514}515 516define i16 @vwreduce_uadd_v128i16(ptr %x) {517; CHECK-LABEL: vwreduce_uadd_v128i16:518; CHECK: # %bb.0:519; CHECK-NEXT: li a1, 128520; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma521; CHECK-NEXT: vle8.v v8, (a0)522; CHECK-NEXT: li a0, 64523; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma524; CHECK-NEXT: vslidedown.vx v16, v8, a0525; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma526; CHECK-NEXT: vwaddu.vv v24, v8, v16527; CHECK-NEXT: vsetvli zero, zero, e16, m8, ta, ma528; CHECK-NEXT: vmv.s.x v8, zero529; CHECK-NEXT: vredsum.vs v8, v24, v8530; CHECK-NEXT: vmv.x.s a0, v8531; CHECK-NEXT: ret532 %v = load <128 x i8>, ptr %x533 %e = zext <128 x i8> %v to <128 x i16>534 %red = call i16 @llvm.vector.reduce.add.v128i16(<128 x i16> %e)535 ret i16 %red536}537 538define i32 @vreduce_add_v1i32(<1 x i32> %v) {539; CHECK-LABEL: vreduce_add_v1i32:540; CHECK: # %bb.0:541; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma542; CHECK-NEXT: vmv.x.s a0, v8543; CHECK-NEXT: ret544 %red = call i32 @llvm.vector.reduce.add.v1i32(<1 x i32> %v)545 ret i32 %red546}547 548define i32 @vwreduce_add_v1i32(<1 x i16> %v) {549; CHECK-LABEL: vwreduce_add_v1i32:550; CHECK: # %bb.0:551; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma552; CHECK-NEXT: vsext.vf2 v9, v8553; CHECK-NEXT: vmv.x.s a0, v9554; CHECK-NEXT: ret555 %e = sext <1 x i16> %v to <1 x i32>556 %red = call i32 @llvm.vector.reduce.add.v1i32(<1 x i32> %e)557 ret i32 %red558}559 560define i32 @vwreduce_uadd_v1i32(<1 x i16> %v) {561; CHECK-LABEL: vwreduce_uadd_v1i32:562; CHECK: # %bb.0:563; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma564; CHECK-NEXT: vzext.vf2 v9, v8565; CHECK-NEXT: vmv.x.s a0, v9566; CHECK-NEXT: ret567 %e = zext <1 x i16> %v to <1 x i32>568 %red = call i32 @llvm.vector.reduce.add.v1i32(<1 x i32> %e)569 ret i32 %red570}571 572define i32 @vreduce_add_v2i32(ptr %x) {573; CHECK-LABEL: vreduce_add_v2i32:574; CHECK: # %bb.0:575; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma576; CHECK-NEXT: vle32.v v8, (a0)577; CHECK-NEXT: vmv.s.x v9, zero578; CHECK-NEXT: vredsum.vs v8, v8, v9579; CHECK-NEXT: vmv.x.s a0, v8580; CHECK-NEXT: ret581 %v = load <2 x i32>, ptr %x582 %red = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> %v)583 ret i32 %red584}585 586define i32 @vwreduce_add_v2i32(ptr %x) {587; CHECK-LABEL: vwreduce_add_v2i32:588; CHECK: # %bb.0:589; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma590; CHECK-NEXT: vle16.v v8, (a0)591; CHECK-NEXT: vmv.s.x v9, zero592; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma593; CHECK-NEXT: vwredsum.vs v8, v8, v9594; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma595; CHECK-NEXT: vmv.x.s a0, v8596; CHECK-NEXT: ret597 %v = load <2 x i16>, ptr %x598 %e = sext <2 x i16> %v to <2 x i32>599 %red = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> %e)600 ret i32 %red601}602 603define i32 @vwreduce_uadd_v2i32(ptr %x) {604; CHECK-LABEL: vwreduce_uadd_v2i32:605; CHECK: # %bb.0:606; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma607; CHECK-NEXT: vle16.v v8, (a0)608; CHECK-NEXT: vmv.s.x v9, zero609; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma610; CHECK-NEXT: vwredsumu.vs v8, v8, v9611; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma612; CHECK-NEXT: vmv.x.s a0, v8613; CHECK-NEXT: ret614 %v = load <2 x i16>, ptr %x615 %e = zext <2 x i16> %v to <2 x i32>616 %red = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> %e)617 ret i32 %red618}619 620define i32 @vreduce_add_v4i32(ptr %x) {621; CHECK-LABEL: vreduce_add_v4i32:622; CHECK: # %bb.0:623; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma624; CHECK-NEXT: vle32.v v8, (a0)625; CHECK-NEXT: vmv.s.x v9, zero626; CHECK-NEXT: vredsum.vs v8, v8, v9627; CHECK-NEXT: vmv.x.s a0, v8628; CHECK-NEXT: ret629 %v = load <4 x i32>, ptr %x630 %red = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %v)631 ret i32 %red632}633 634define i32 @vwreduce_add_v4i32(ptr %x) {635; CHECK-LABEL: vwreduce_add_v4i32:636; CHECK: # %bb.0:637; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma638; CHECK-NEXT: vle16.v v8, (a0)639; CHECK-NEXT: vmv.s.x v9, zero640; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma641; CHECK-NEXT: vwredsum.vs v8, v8, v9642; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma643; CHECK-NEXT: vmv.x.s a0, v8644; CHECK-NEXT: ret645 %v = load <4 x i16>, ptr %x646 %e = sext <4 x i16> %v to <4 x i32>647 %red = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %e)648 ret i32 %red649}650 651define i32 @vwreduce_uadd_v4i32(ptr %x) {652; CHECK-LABEL: vwreduce_uadd_v4i32:653; CHECK: # %bb.0:654; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma655; CHECK-NEXT: vle16.v v8, (a0)656; CHECK-NEXT: vmv.s.x v9, zero657; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma658; CHECK-NEXT: vwredsumu.vs v8, v8, v9659; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma660; CHECK-NEXT: vmv.x.s a0, v8661; CHECK-NEXT: ret662 %v = load <4 x i16>, ptr %x663 %e = zext <4 x i16> %v to <4 x i32>664 %red = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %e)665 ret i32 %red666}667 668define i32 @vreduce_add_v8i32(ptr %x) {669; CHECK-LABEL: vreduce_add_v8i32:670; CHECK: # %bb.0:671; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma672; CHECK-NEXT: vle32.v v8, (a0)673; CHECK-NEXT: vmv.s.x v10, zero674; CHECK-NEXT: vredsum.vs v8, v8, v10675; CHECK-NEXT: vmv.x.s a0, v8676; CHECK-NEXT: ret677 %v = load <8 x i32>, ptr %x678 %red = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %v)679 ret i32 %red680}681 682define i32 @vwreduce_add_v8i32(ptr %x) {683; CHECK-LABEL: vwreduce_add_v8i32:684; CHECK: # %bb.0:685; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma686; CHECK-NEXT: vle16.v v8, (a0)687; CHECK-NEXT: vmv.s.x v9, zero688; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma689; CHECK-NEXT: vwredsum.vs v8, v8, v9690; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma691; CHECK-NEXT: vmv.x.s a0, v8692; CHECK-NEXT: ret693 %v = load <8 x i16>, ptr %x694 %e = sext <8 x i16> %v to <8 x i32>695 %red = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %e)696 ret i32 %red697}698 699define i32 @vwreduce_uadd_v8i32(ptr %x) {700; CHECK-LABEL: vwreduce_uadd_v8i32:701; CHECK: # %bb.0:702; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma703; CHECK-NEXT: vle16.v v8, (a0)704; CHECK-NEXT: vmv.s.x v9, zero705; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma706; CHECK-NEXT: vwredsumu.vs v8, v8, v9707; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma708; CHECK-NEXT: vmv.x.s a0, v8709; CHECK-NEXT: ret710 %v = load <8 x i16>, ptr %x711 %e = zext <8 x i16> %v to <8 x i32>712 %red = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %e)713 ret i32 %red714}715 716define i32 @vreduce_add_v16i32(ptr %x) {717; CHECK-LABEL: vreduce_add_v16i32:718; CHECK: # %bb.0:719; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma720; CHECK-NEXT: vle32.v v8, (a0)721; CHECK-NEXT: vmv.s.x v12, zero722; CHECK-NEXT: vredsum.vs v8, v8, v12723; CHECK-NEXT: vmv.x.s a0, v8724; CHECK-NEXT: ret725 %v = load <16 x i32>, ptr %x726 %red = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %v)727 ret i32 %red728}729 730define i32 @vwreduce_add_v16i32(ptr %x) {731; CHECK-LABEL: vwreduce_add_v16i32:732; CHECK: # %bb.0:733; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma734; CHECK-NEXT: vle16.v v8, (a0)735; CHECK-NEXT: vmv.s.x v10, zero736; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma737; CHECK-NEXT: vwredsum.vs v8, v8, v10738; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma739; CHECK-NEXT: vmv.x.s a0, v8740; CHECK-NEXT: ret741 %v = load <16 x i16>, ptr %x742 %e = sext <16 x i16> %v to <16 x i32>743 %red = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %e)744 ret i32 %red745}746 747define i32 @vwreduce_uadd_v16i32(ptr %x) {748; CHECK-LABEL: vwreduce_uadd_v16i32:749; CHECK: # %bb.0:750; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma751; CHECK-NEXT: vle16.v v8, (a0)752; CHECK-NEXT: vmv.s.x v10, zero753; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma754; CHECK-NEXT: vwredsumu.vs v8, v8, v10755; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma756; CHECK-NEXT: vmv.x.s a0, v8757; CHECK-NEXT: ret758 %v = load <16 x i16>, ptr %x759 %e = zext <16 x i16> %v to <16 x i32>760 %red = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %e)761 ret i32 %red762}763 764define i32 @vreduce_add_v32i32(ptr %x) {765; CHECK-LABEL: vreduce_add_v32i32:766; CHECK: # %bb.0:767; CHECK-NEXT: li a1, 32768; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma769; CHECK-NEXT: vle32.v v8, (a0)770; CHECK-NEXT: vmv.s.x v16, zero771; CHECK-NEXT: vredsum.vs v8, v8, v16772; CHECK-NEXT: vmv.x.s a0, v8773; CHECK-NEXT: ret774 %v = load <32 x i32>, ptr %x775 %red = call i32 @llvm.vector.reduce.add.v32i32(<32 x i32> %v)776 ret i32 %red777}778 779define i32 @vwreduce_add_v32i32(ptr %x) {780; CHECK-LABEL: vwreduce_add_v32i32:781; CHECK: # %bb.0:782; CHECK-NEXT: li a1, 32783; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma784; CHECK-NEXT: vle16.v v8, (a0)785; CHECK-NEXT: vmv.s.x v12, zero786; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma787; CHECK-NEXT: vwredsum.vs v8, v8, v12788; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma789; CHECK-NEXT: vmv.x.s a0, v8790; CHECK-NEXT: ret791 %v = load <32 x i16>, ptr %x792 %e = sext <32 x i16> %v to <32 x i32>793 %red = call i32 @llvm.vector.reduce.add.v32i32(<32 x i32> %e)794 ret i32 %red795}796 797define i32 @vwreduce_uadd_v32i32(ptr %x) {798; CHECK-LABEL: vwreduce_uadd_v32i32:799; CHECK: # %bb.0:800; CHECK-NEXT: li a1, 32801; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma802; CHECK-NEXT: vle16.v v8, (a0)803; CHECK-NEXT: vmv.s.x v12, zero804; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma805; CHECK-NEXT: vwredsumu.vs v8, v8, v12806; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma807; CHECK-NEXT: vmv.x.s a0, v8808; CHECK-NEXT: ret809 %v = load <32 x i16>, ptr %x810 %e = zext <32 x i16> %v to <32 x i32>811 %red = call i32 @llvm.vector.reduce.add.v32i32(<32 x i32> %e)812 ret i32 %red813}814 815define i32 @vreduce_add_v64i32(ptr %x) {816; CHECK-LABEL: vreduce_add_v64i32:817; CHECK: # %bb.0:818; CHECK-NEXT: li a1, 32819; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma820; CHECK-NEXT: vle32.v v8, (a0)821; CHECK-NEXT: addi a0, a0, 128822; CHECK-NEXT: vle32.v v16, (a0)823; CHECK-NEXT: vadd.vv v8, v8, v16824; CHECK-NEXT: vmv.s.x v16, zero825; CHECK-NEXT: vredsum.vs v8, v8, v16826; CHECK-NEXT: vmv.x.s a0, v8827; CHECK-NEXT: ret828 %v = load <64 x i32>, ptr %x829 %red = call i32 @llvm.vector.reduce.add.v64i32(<64 x i32> %v)830 ret i32 %red831}832 833define i32 @vwreduce_add_v64i32(ptr %x) {834; CHECK-LABEL: vwreduce_add_v64i32:835; CHECK: # %bb.0:836; CHECK-NEXT: li a1, 64837; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma838; CHECK-NEXT: vle16.v v8, (a0)839; CHECK-NEXT: li a0, 32840; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma841; CHECK-NEXT: vslidedown.vx v16, v8, a0842; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma843; CHECK-NEXT: vwadd.vv v24, v8, v16844; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma845; CHECK-NEXT: vmv.s.x v8, zero846; CHECK-NEXT: vredsum.vs v8, v24, v8847; CHECK-NEXT: vmv.x.s a0, v8848; CHECK-NEXT: ret849 %v = load <64 x i16>, ptr %x850 %e = sext <64 x i16> %v to <64 x i32>851 %red = call i32 @llvm.vector.reduce.add.v64i32(<64 x i32> %e)852 ret i32 %red853}854 855define i32 @vwreduce_uadd_v64i32(ptr %x) {856; CHECK-LABEL: vwreduce_uadd_v64i32:857; CHECK: # %bb.0:858; CHECK-NEXT: li a1, 64859; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma860; CHECK-NEXT: vle16.v v8, (a0)861; CHECK-NEXT: li a0, 32862; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma863; CHECK-NEXT: vslidedown.vx v16, v8, a0864; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma865; CHECK-NEXT: vwaddu.vv v24, v8, v16866; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma867; CHECK-NEXT: vmv.s.x v8, zero868; CHECK-NEXT: vredsum.vs v8, v24, v8869; CHECK-NEXT: vmv.x.s a0, v8870; CHECK-NEXT: ret871 %v = load <64 x i16>, ptr %x872 %e = zext <64 x i16> %v to <64 x i32>873 %red = call i32 @llvm.vector.reduce.add.v64i32(<64 x i32> %e)874 ret i32 %red875}876 877define i64 @vreduce_add_v1i64(<1 x i64> %v) {878; RV32-LABEL: vreduce_add_v1i64:879; RV32: # %bb.0:880; RV32-NEXT: li a0, 32881; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma882; RV32-NEXT: vsrl.vx v9, v8, a0883; RV32-NEXT: vmv.x.s a1, v9884; RV32-NEXT: vmv.x.s a0, v8885; RV32-NEXT: ret886;887; RV64-LABEL: vreduce_add_v1i64:888; RV64: # %bb.0:889; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma890; RV64-NEXT: vmv.x.s a0, v8891; RV64-NEXT: ret892 %red = call i64 @llvm.vector.reduce.add.v1i64(<1 x i64> %v)893 ret i64 %red894}895 896define i64 @vwreduce_add_v1i64(<1 x i32> %v) {897; RV32-LABEL: vwreduce_add_v1i64:898; RV32: # %bb.0:899; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma900; RV32-NEXT: vsext.vf2 v9, v8901; RV32-NEXT: li a0, 32902; RV32-NEXT: vsrl.vx v8, v9, a0903; RV32-NEXT: vmv.x.s a1, v8904; RV32-NEXT: vmv.x.s a0, v9905; RV32-NEXT: ret906;907; RV64-LABEL: vwreduce_add_v1i64:908; RV64: # %bb.0:909; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma910; RV64-NEXT: vsext.vf2 v9, v8911; RV64-NEXT: vmv.x.s a0, v9912; RV64-NEXT: ret913 %e = sext <1 x i32> %v to <1 x i64>914 %red = call i64 @llvm.vector.reduce.add.v1i64(<1 x i64> %e)915 ret i64 %red916}917 918define i64 @vwreduce_uadd_v1i64(<1 x i32> %v) {919; RV32-LABEL: vwreduce_uadd_v1i64:920; RV32: # %bb.0:921; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma922; RV32-NEXT: vzext.vf2 v9, v8923; RV32-NEXT: li a0, 32924; RV32-NEXT: vsrl.vx v8, v9, a0925; RV32-NEXT: vmv.x.s a1, v8926; RV32-NEXT: vmv.x.s a0, v9927; RV32-NEXT: ret928;929; RV64-LABEL: vwreduce_uadd_v1i64:930; RV64: # %bb.0:931; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma932; RV64-NEXT: vzext.vf2 v9, v8933; RV64-NEXT: vmv.x.s a0, v9934; RV64-NEXT: ret935 %e = zext <1 x i32> %v to <1 x i64>936 %red = call i64 @llvm.vector.reduce.add.v1i64(<1 x i64> %e)937 ret i64 %red938}939 940define i64 @vreduce_add_v2i64(ptr %x) {941; RV32-LABEL: vreduce_add_v2i64:942; RV32: # %bb.0:943; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma944; RV32-NEXT: vle64.v v8, (a0)945; RV32-NEXT: vmv.s.x v9, zero946; RV32-NEXT: li a1, 32947; RV32-NEXT: vredsum.vs v8, v8, v9948; RV32-NEXT: vmv.x.s a0, v8949; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma950; RV32-NEXT: vsrl.vx v8, v8, a1951; RV32-NEXT: vmv.x.s a1, v8952; RV32-NEXT: ret953;954; RV64-LABEL: vreduce_add_v2i64:955; RV64: # %bb.0:956; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma957; RV64-NEXT: vle64.v v8, (a0)958; RV64-NEXT: vmv.s.x v9, zero959; RV64-NEXT: vredsum.vs v8, v8, v9960; RV64-NEXT: vmv.x.s a0, v8961; RV64-NEXT: ret962 %v = load <2 x i64>, ptr %x963 %red = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %v)964 ret i64 %red965}966 967define i64 @vwreduce_add_v2i64(ptr %x) {968; RV32-LABEL: vwreduce_add_v2i64:969; RV32: # %bb.0:970; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma971; RV32-NEXT: vle32.v v8, (a0)972; RV32-NEXT: vmv.s.x v9, zero973; RV32-NEXT: li a1, 32974; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma975; RV32-NEXT: vwredsum.vs v8, v8, v9976; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma977; RV32-NEXT: vmv.x.s a0, v8978; RV32-NEXT: vsrl.vx v8, v8, a1979; RV32-NEXT: vmv.x.s a1, v8980; RV32-NEXT: ret981;982; RV64-LABEL: vwreduce_add_v2i64:983; RV64: # %bb.0:984; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma985; RV64-NEXT: vle32.v v8, (a0)986; RV64-NEXT: vmv.s.x v9, zero987; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma988; RV64-NEXT: vwredsum.vs v8, v8, v9989; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma990; RV64-NEXT: vmv.x.s a0, v8991; RV64-NEXT: ret992 %v = load <2 x i32>, ptr %x993 %e = sext <2 x i32> %v to <2 x i64>994 %red = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %e)995 ret i64 %red996}997 998define i64 @vwreduce_uadd_v2i64(ptr %x) {999; RV32-LABEL: vwreduce_uadd_v2i64:1000; RV32: # %bb.0:1001; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma1002; RV32-NEXT: vle32.v v8, (a0)1003; RV32-NEXT: vmv.s.x v9, zero1004; RV32-NEXT: li a1, 321005; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma1006; RV32-NEXT: vwredsumu.vs v8, v8, v91007; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1008; RV32-NEXT: vmv.x.s a0, v81009; RV32-NEXT: vsrl.vx v8, v8, a11010; RV32-NEXT: vmv.x.s a1, v81011; RV32-NEXT: ret1012;1013; RV64-LABEL: vwreduce_uadd_v2i64:1014; RV64: # %bb.0:1015; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma1016; RV64-NEXT: vle32.v v8, (a0)1017; RV64-NEXT: vmv.s.x v9, zero1018; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma1019; RV64-NEXT: vwredsumu.vs v8, v8, v91020; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma1021; RV64-NEXT: vmv.x.s a0, v81022; RV64-NEXT: ret1023 %v = load <2 x i32>, ptr %x1024 %e = zext <2 x i32> %v to <2 x i64>1025 %red = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %e)1026 ret i64 %red1027}1028 1029define i64 @vreduce_add_v4i64(ptr %x) {1030; RV32-LABEL: vreduce_add_v4i64:1031; RV32: # %bb.0:1032; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma1033; RV32-NEXT: vle64.v v8, (a0)1034; RV32-NEXT: vmv.s.x v10, zero1035; RV32-NEXT: li a1, 321036; RV32-NEXT: vredsum.vs v8, v8, v101037; RV32-NEXT: vmv.x.s a0, v81038; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1039; RV32-NEXT: vsrl.vx v8, v8, a11040; RV32-NEXT: vmv.x.s a1, v81041; RV32-NEXT: ret1042;1043; RV64-LABEL: vreduce_add_v4i64:1044; RV64: # %bb.0:1045; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma1046; RV64-NEXT: vle64.v v8, (a0)1047; RV64-NEXT: vmv.s.x v10, zero1048; RV64-NEXT: vredsum.vs v8, v8, v101049; RV64-NEXT: vmv.x.s a0, v81050; RV64-NEXT: ret1051 %v = load <4 x i64>, ptr %x1052 %red = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %v)1053 ret i64 %red1054}1055 1056define i64 @vwreduce_add_v4i64(ptr %x) {1057; RV32-LABEL: vwreduce_add_v4i64:1058; RV32: # %bb.0:1059; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma1060; RV32-NEXT: vle32.v v8, (a0)1061; RV32-NEXT: vmv.s.x v9, zero1062; RV32-NEXT: li a1, 321063; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma1064; RV32-NEXT: vwredsum.vs v8, v8, v91065; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1066; RV32-NEXT: vmv.x.s a0, v81067; RV32-NEXT: vsrl.vx v8, v8, a11068; RV32-NEXT: vmv.x.s a1, v81069; RV32-NEXT: ret1070;1071; RV64-LABEL: vwreduce_add_v4i64:1072; RV64: # %bb.0:1073; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma1074; RV64-NEXT: vle32.v v8, (a0)1075; RV64-NEXT: vmv.s.x v9, zero1076; RV64-NEXT: vsetvli zero, zero, e32, m1, ta, ma1077; RV64-NEXT: vwredsum.vs v8, v8, v91078; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, ma1079; RV64-NEXT: vmv.x.s a0, v81080; RV64-NEXT: ret1081 %v = load <4 x i32>, ptr %x1082 %e = sext <4 x i32> %v to <4 x i64>1083 %red = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %e)1084 ret i64 %red1085}1086 1087define i64 @vwreduce_uadd_v4i64(ptr %x) {1088; RV32-LABEL: vwreduce_uadd_v4i64:1089; RV32: # %bb.0:1090; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma1091; RV32-NEXT: vle32.v v8, (a0)1092; RV32-NEXT: vmv.s.x v9, zero1093; RV32-NEXT: li a1, 321094; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma1095; RV32-NEXT: vwredsumu.vs v8, v8, v91096; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1097; RV32-NEXT: vmv.x.s a0, v81098; RV32-NEXT: vsrl.vx v8, v8, a11099; RV32-NEXT: vmv.x.s a1, v81100; RV32-NEXT: ret1101;1102; RV64-LABEL: vwreduce_uadd_v4i64:1103; RV64: # %bb.0:1104; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma1105; RV64-NEXT: vle32.v v8, (a0)1106; RV64-NEXT: vmv.s.x v9, zero1107; RV64-NEXT: vsetvli zero, zero, e32, m1, ta, ma1108; RV64-NEXT: vwredsumu.vs v8, v8, v91109; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, ma1110; RV64-NEXT: vmv.x.s a0, v81111; RV64-NEXT: ret1112 %v = load <4 x i32>, ptr %x1113 %e = zext <4 x i32> %v to <4 x i64>1114 %red = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %e)1115 ret i64 %red1116}1117 1118define i64 @vreduce_add_v8i64(ptr %x) {1119; RV32-LABEL: vreduce_add_v8i64:1120; RV32: # %bb.0:1121; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma1122; RV32-NEXT: vle64.v v8, (a0)1123; RV32-NEXT: vmv.s.x v12, zero1124; RV32-NEXT: li a1, 321125; RV32-NEXT: vredsum.vs v8, v8, v121126; RV32-NEXT: vmv.x.s a0, v81127; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1128; RV32-NEXT: vsrl.vx v8, v8, a11129; RV32-NEXT: vmv.x.s a1, v81130; RV32-NEXT: ret1131;1132; RV64-LABEL: vreduce_add_v8i64:1133; RV64: # %bb.0:1134; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma1135; RV64-NEXT: vle64.v v8, (a0)1136; RV64-NEXT: vmv.s.x v12, zero1137; RV64-NEXT: vredsum.vs v8, v8, v121138; RV64-NEXT: vmv.x.s a0, v81139; RV64-NEXT: ret1140 %v = load <8 x i64>, ptr %x1141 %red = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %v)1142 ret i64 %red1143}1144 1145define i64 @vwreduce_add_v8i64(ptr %x) {1146; RV32-LABEL: vwreduce_add_v8i64:1147; RV32: # %bb.0:1148; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma1149; RV32-NEXT: vle32.v v8, (a0)1150; RV32-NEXT: vmv.s.x v10, zero1151; RV32-NEXT: li a1, 321152; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma1153; RV32-NEXT: vwredsum.vs v8, v8, v101154; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1155; RV32-NEXT: vmv.x.s a0, v81156; RV32-NEXT: vsrl.vx v8, v8, a11157; RV32-NEXT: vmv.x.s a1, v81158; RV32-NEXT: ret1159;1160; RV64-LABEL: vwreduce_add_v8i64:1161; RV64: # %bb.0:1162; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma1163; RV64-NEXT: vle32.v v8, (a0)1164; RV64-NEXT: vmv.s.x v10, zero1165; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, ma1166; RV64-NEXT: vwredsum.vs v8, v8, v101167; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, ma1168; RV64-NEXT: vmv.x.s a0, v81169; RV64-NEXT: ret1170 %v = load <8 x i32>, ptr %x1171 %e = sext <8 x i32> %v to <8 x i64>1172 %red = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %e)1173 ret i64 %red1174}1175 1176define i64 @vwreduce_uadd_v8i64(ptr %x) {1177; RV32-LABEL: vwreduce_uadd_v8i64:1178; RV32: # %bb.0:1179; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma1180; RV32-NEXT: vle32.v v8, (a0)1181; RV32-NEXT: vmv.s.x v10, zero1182; RV32-NEXT: li a1, 321183; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma1184; RV32-NEXT: vwredsumu.vs v8, v8, v101185; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1186; RV32-NEXT: vmv.x.s a0, v81187; RV32-NEXT: vsrl.vx v8, v8, a11188; RV32-NEXT: vmv.x.s a1, v81189; RV32-NEXT: ret1190;1191; RV64-LABEL: vwreduce_uadd_v8i64:1192; RV64: # %bb.0:1193; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma1194; RV64-NEXT: vle32.v v8, (a0)1195; RV64-NEXT: vmv.s.x v10, zero1196; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, ma1197; RV64-NEXT: vwredsumu.vs v8, v8, v101198; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, ma1199; RV64-NEXT: vmv.x.s a0, v81200; RV64-NEXT: ret1201 %v = load <8 x i32>, ptr %x1202 %e = zext <8 x i32> %v to <8 x i64>1203 %red = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %e)1204 ret i64 %red1205}1206 1207define i64 @vreduce_add_v16i64(ptr %x) {1208; RV32-LABEL: vreduce_add_v16i64:1209; RV32: # %bb.0:1210; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma1211; RV32-NEXT: vle64.v v8, (a0)1212; RV32-NEXT: vmv.s.x v16, zero1213; RV32-NEXT: li a1, 321214; RV32-NEXT: vredsum.vs v8, v8, v161215; RV32-NEXT: vmv.x.s a0, v81216; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1217; RV32-NEXT: vsrl.vx v8, v8, a11218; RV32-NEXT: vmv.x.s a1, v81219; RV32-NEXT: ret1220;1221; RV64-LABEL: vreduce_add_v16i64:1222; RV64: # %bb.0:1223; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma1224; RV64-NEXT: vle64.v v8, (a0)1225; RV64-NEXT: vmv.s.x v16, zero1226; RV64-NEXT: vredsum.vs v8, v8, v161227; RV64-NEXT: vmv.x.s a0, v81228; RV64-NEXT: ret1229 %v = load <16 x i64>, ptr %x1230 %red = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> %v)1231 ret i64 %red1232}1233 1234define i64 @vwreduce_add_v16i64(ptr %x) {1235; RV32-LABEL: vwreduce_add_v16i64:1236; RV32: # %bb.0:1237; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma1238; RV32-NEXT: vle32.v v8, (a0)1239; RV32-NEXT: vmv.s.x v12, zero1240; RV32-NEXT: li a1, 321241; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, ma1242; RV32-NEXT: vwredsum.vs v8, v8, v121243; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1244; RV32-NEXT: vmv.x.s a0, v81245; RV32-NEXT: vsrl.vx v8, v8, a11246; RV32-NEXT: vmv.x.s a1, v81247; RV32-NEXT: ret1248;1249; RV64-LABEL: vwreduce_add_v16i64:1250; RV64: # %bb.0:1251; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma1252; RV64-NEXT: vle32.v v8, (a0)1253; RV64-NEXT: vmv.s.x v12, zero1254; RV64-NEXT: vsetvli zero, zero, e32, m4, ta, ma1255; RV64-NEXT: vwredsum.vs v8, v8, v121256; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma1257; RV64-NEXT: vmv.x.s a0, v81258; RV64-NEXT: ret1259 %v = load <16 x i32>, ptr %x1260 %e = sext <16 x i32> %v to <16 x i64>1261 %red = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> %e)1262 ret i64 %red1263}1264 1265define i64 @vwreduce_uadd_v16i64(ptr %x) {1266; RV32-LABEL: vwreduce_uadd_v16i64:1267; RV32: # %bb.0:1268; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma1269; RV32-NEXT: vle32.v v8, (a0)1270; RV32-NEXT: vmv.s.x v12, zero1271; RV32-NEXT: li a1, 321272; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, ma1273; RV32-NEXT: vwredsumu.vs v8, v8, v121274; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1275; RV32-NEXT: vmv.x.s a0, v81276; RV32-NEXT: vsrl.vx v8, v8, a11277; RV32-NEXT: vmv.x.s a1, v81278; RV32-NEXT: ret1279;1280; RV64-LABEL: vwreduce_uadd_v16i64:1281; RV64: # %bb.0:1282; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma1283; RV64-NEXT: vle32.v v8, (a0)1284; RV64-NEXT: vmv.s.x v12, zero1285; RV64-NEXT: vsetvli zero, zero, e32, m4, ta, ma1286; RV64-NEXT: vwredsumu.vs v8, v8, v121287; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma1288; RV64-NEXT: vmv.x.s a0, v81289; RV64-NEXT: ret1290 %v = load <16 x i32>, ptr %x1291 %e = zext <16 x i32> %v to <16 x i64>1292 %red = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> %e)1293 ret i64 %red1294}1295 1296define i64 @vreduce_add_v32i64(ptr %x) {1297; RV32-LABEL: vreduce_add_v32i64:1298; RV32: # %bb.0:1299; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma1300; RV32-NEXT: vle64.v v8, (a0)1301; RV32-NEXT: addi a0, a0, 1281302; RV32-NEXT: vle64.v v16, (a0)1303; RV32-NEXT: vadd.vv v8, v8, v161304; RV32-NEXT: vmv.s.x v16, zero1305; RV32-NEXT: li a1, 321306; RV32-NEXT: vredsum.vs v8, v8, v161307; RV32-NEXT: vmv.x.s a0, v81308; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1309; RV32-NEXT: vsrl.vx v8, v8, a11310; RV32-NEXT: vmv.x.s a1, v81311; RV32-NEXT: ret1312;1313; RV64-LABEL: vreduce_add_v32i64:1314; RV64: # %bb.0:1315; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma1316; RV64-NEXT: vle64.v v8, (a0)1317; RV64-NEXT: addi a0, a0, 1281318; RV64-NEXT: vle64.v v16, (a0)1319; RV64-NEXT: vadd.vv v8, v8, v161320; RV64-NEXT: vmv.s.x v16, zero1321; RV64-NEXT: vredsum.vs v8, v8, v161322; RV64-NEXT: vmv.x.s a0, v81323; RV64-NEXT: ret1324 %v = load <32 x i64>, ptr %x1325 %red = call i64 @llvm.vector.reduce.add.v32i64(<32 x i64> %v)1326 ret i64 %red1327}1328 1329define i64 @vwreduce_add_v32i64(ptr %x) {1330; RV32-LABEL: vwreduce_add_v32i64:1331; RV32: # %bb.0:1332; RV32-NEXT: li a1, 321333; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma1334; RV32-NEXT: vle32.v v8, (a0)1335; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma1336; RV32-NEXT: vslidedown.vi v16, v8, 161337; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma1338; RV32-NEXT: vwadd.vv v24, v8, v161339; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma1340; RV32-NEXT: vmv.s.x v8, zero1341; RV32-NEXT: vredsum.vs v8, v24, v81342; RV32-NEXT: vmv.x.s a0, v81343; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1344; RV32-NEXT: vsrl.vx v8, v8, a11345; RV32-NEXT: vmv.x.s a1, v81346; RV32-NEXT: ret1347;1348; RV64-LABEL: vwreduce_add_v32i64:1349; RV64: # %bb.0:1350; RV64-NEXT: li a1, 321351; RV64-NEXT: vsetvli zero, a1, e32, m8, ta, ma1352; RV64-NEXT: vle32.v v8, (a0)1353; RV64-NEXT: vsetivli zero, 16, e32, m8, ta, ma1354; RV64-NEXT: vslidedown.vi v16, v8, 161355; RV64-NEXT: vsetivli zero, 16, e32, m4, ta, ma1356; RV64-NEXT: vwadd.vv v24, v8, v161357; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma1358; RV64-NEXT: vmv.s.x v8, zero1359; RV64-NEXT: vredsum.vs v8, v24, v81360; RV64-NEXT: vmv.x.s a0, v81361; RV64-NEXT: ret1362 %v = load <32 x i32>, ptr %x1363 %e = sext <32 x i32> %v to <32 x i64>1364 %red = call i64 @llvm.vector.reduce.add.v32i64(<32 x i64> %e)1365 ret i64 %red1366}1367 1368define i64 @vwreduce_uadd_v32i64(ptr %x) {1369; RV32-LABEL: vwreduce_uadd_v32i64:1370; RV32: # %bb.0:1371; RV32-NEXT: li a1, 321372; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma1373; RV32-NEXT: vle32.v v8, (a0)1374; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma1375; RV32-NEXT: vslidedown.vi v16, v8, 161376; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma1377; RV32-NEXT: vwaddu.vv v24, v8, v161378; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma1379; RV32-NEXT: vmv.s.x v8, zero1380; RV32-NEXT: vredsum.vs v8, v24, v81381; RV32-NEXT: vmv.x.s a0, v81382; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1383; RV32-NEXT: vsrl.vx v8, v8, a11384; RV32-NEXT: vmv.x.s a1, v81385; RV32-NEXT: ret1386;1387; RV64-LABEL: vwreduce_uadd_v32i64:1388; RV64: # %bb.0:1389; RV64-NEXT: li a1, 321390; RV64-NEXT: vsetvli zero, a1, e32, m8, ta, ma1391; RV64-NEXT: vle32.v v8, (a0)1392; RV64-NEXT: vsetivli zero, 16, e32, m8, ta, ma1393; RV64-NEXT: vslidedown.vi v16, v8, 161394; RV64-NEXT: vsetivli zero, 16, e32, m4, ta, ma1395; RV64-NEXT: vwaddu.vv v24, v8, v161396; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma1397; RV64-NEXT: vmv.s.x v8, zero1398; RV64-NEXT: vredsum.vs v8, v24, v81399; RV64-NEXT: vmv.x.s a0, v81400; RV64-NEXT: ret1401 %v = load <32 x i32>, ptr %x1402 %e = zext <32 x i32> %v to <32 x i64>1403 %red = call i64 @llvm.vector.reduce.add.v32i64(<32 x i64> %e)1404 ret i64 %red1405}1406 1407define i64 @vreduce_add_v64i64(ptr %x) nounwind {1408; RV32-LABEL: vreduce_add_v64i64:1409; RV32: # %bb.0:1410; RV32-NEXT: addi a1, a0, 3841411; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma1412; RV32-NEXT: vle64.v v24, (a1)1413; RV32-NEXT: addi a1, a0, 1281414; RV32-NEXT: vle64.v v0, (a1)1415; RV32-NEXT: vle64.v v8, (a0)1416; RV32-NEXT: addi a0, a0, 2561417; RV32-NEXT: vle64.v v16, (a0)1418; RV32-NEXT: vadd.vv v24, v0, v241419; RV32-NEXT: vmv.s.x v7, zero1420; RV32-NEXT: li a1, 321421; RV32-NEXT: vadd.vv v8, v8, v161422; RV32-NEXT: vadd.vv v8, v8, v241423; RV32-NEXT: vredsum.vs v8, v8, v71424; RV32-NEXT: vmv.x.s a0, v81425; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1426; RV32-NEXT: vsrl.vx v8, v8, a11427; RV32-NEXT: vmv.x.s a1, v81428; RV32-NEXT: ret1429;1430; RV64-LABEL: vreduce_add_v64i64:1431; RV64: # %bb.0:1432; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma1433; RV64-NEXT: vle64.v v8, (a0)1434; RV64-NEXT: addi a1, a0, 3841435; RV64-NEXT: vle64.v v16, (a1)1436; RV64-NEXT: addi a1, a0, 2561437; RV64-NEXT: addi a0, a0, 1281438; RV64-NEXT: vle64.v v24, (a0)1439; RV64-NEXT: vle64.v v0, (a1)1440; RV64-NEXT: vadd.vv v16, v24, v161441; RV64-NEXT: vadd.vv v8, v8, v01442; RV64-NEXT: vadd.vv v8, v8, v161443; RV64-NEXT: vmv.s.x v16, zero1444; RV64-NEXT: vredsum.vs v8, v8, v161445; RV64-NEXT: vmv.x.s a0, v81446; RV64-NEXT: ret1447 %v = load <64 x i64>, ptr %x1448 %red = call i64 @llvm.vector.reduce.add.v64i64(<64 x i64> %v)1449 ret i64 %red1450}1451 1452define i64 @vwreduce_add_v64i64(ptr %x) {1453; RV32-LABEL: vwreduce_add_v64i64:1454; RV32: # %bb.0:1455; RV32-NEXT: li a1, 321456; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma1457; RV32-NEXT: vle32.v v8, (a0)1458; RV32-NEXT: addi a0, a0, 1281459; RV32-NEXT: vle32.v v16, (a0)1460; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma1461; RV32-NEXT: vslidedown.vi v24, v8, 161462; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma1463; RV32-NEXT: vwadd.vv v0, v8, v161464; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma1465; RV32-NEXT: vslidedown.vi v8, v16, 161466; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma1467; RV32-NEXT: vwadd.vv v16, v24, v81468; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma1469; RV32-NEXT: vadd.vv v8, v0, v161470; RV32-NEXT: vmv.s.x v16, zero1471; RV32-NEXT: vredsum.vs v8, v8, v161472; RV32-NEXT: vmv.x.s a0, v81473; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1474; RV32-NEXT: vsrl.vx v8, v8, a11475; RV32-NEXT: vmv.x.s a1, v81476; RV32-NEXT: ret1477;1478; RV64-LABEL: vwreduce_add_v64i64:1479; RV64: # %bb.0:1480; RV64-NEXT: addi sp, sp, -161481; RV64-NEXT: .cfi_def_cfa_offset 161482; RV64-NEXT: csrr a1, vlenb1483; RV64-NEXT: slli a1, a1, 31484; RV64-NEXT: sub sp, sp, a11485; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb1486; RV64-NEXT: li a1, 321487; RV64-NEXT: vsetvli zero, a1, e32, m8, ta, ma1488; RV64-NEXT: vle32.v v8, (a0)1489; RV64-NEXT: addi a0, a0, 1281490; RV64-NEXT: vle32.v v16, (a0)1491; RV64-NEXT: vsetivli zero, 16, e32, m8, ta, ma1492; RV64-NEXT: vslidedown.vi v24, v8, 161493; RV64-NEXT: addi a0, sp, 161494; RV64-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill1495; RV64-NEXT: vslidedown.vi v0, v16, 161496; RV64-NEXT: vsetivli zero, 16, e32, m4, ta, ma1497; RV64-NEXT: vwadd.vv v24, v8, v161498; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload1499; RV64-NEXT: vwadd.vv v8, v16, v01500; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma1501; RV64-NEXT: vadd.vv v8, v24, v81502; RV64-NEXT: vmv.s.x v16, zero1503; RV64-NEXT: vredsum.vs v8, v8, v161504; RV64-NEXT: vmv.x.s a0, v81505; RV64-NEXT: csrr a1, vlenb1506; RV64-NEXT: slli a1, a1, 31507; RV64-NEXT: add sp, sp, a11508; RV64-NEXT: .cfi_def_cfa sp, 161509; RV64-NEXT: addi sp, sp, 161510; RV64-NEXT: .cfi_def_cfa_offset 01511; RV64-NEXT: ret1512 %v = load <64 x i32>, ptr %x1513 %e = sext <64 x i32> %v to <64 x i64>1514 %red = call i64 @llvm.vector.reduce.add.v64i64(<64 x i64> %e)1515 ret i64 %red1516}1517 1518define i64 @vwreduce_uadd_v64i64(ptr %x) {1519; RV32-LABEL: vwreduce_uadd_v64i64:1520; RV32: # %bb.0:1521; RV32-NEXT: li a1, 321522; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma1523; RV32-NEXT: vle32.v v8, (a0)1524; RV32-NEXT: addi a0, a0, 1281525; RV32-NEXT: vle32.v v16, (a0)1526; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma1527; RV32-NEXT: vslidedown.vi v24, v8, 161528; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma1529; RV32-NEXT: vwaddu.vv v0, v8, v161530; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma1531; RV32-NEXT: vslidedown.vi v8, v16, 161532; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma1533; RV32-NEXT: vwaddu.vv v16, v24, v81534; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma1535; RV32-NEXT: vadd.vv v8, v0, v161536; RV32-NEXT: vmv.s.x v16, zero1537; RV32-NEXT: vredsum.vs v8, v8, v161538; RV32-NEXT: vmv.x.s a0, v81539; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1540; RV32-NEXT: vsrl.vx v8, v8, a11541; RV32-NEXT: vmv.x.s a1, v81542; RV32-NEXT: ret1543;1544; RV64-LABEL: vwreduce_uadd_v64i64:1545; RV64: # %bb.0:1546; RV64-NEXT: addi sp, sp, -161547; RV64-NEXT: .cfi_def_cfa_offset 161548; RV64-NEXT: csrr a1, vlenb1549; RV64-NEXT: slli a1, a1, 31550; RV64-NEXT: sub sp, sp, a11551; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb1552; RV64-NEXT: li a1, 321553; RV64-NEXT: vsetvli zero, a1, e32, m8, ta, ma1554; RV64-NEXT: vle32.v v8, (a0)1555; RV64-NEXT: addi a0, a0, 1281556; RV64-NEXT: vle32.v v16, (a0)1557; RV64-NEXT: vsetivli zero, 16, e32, m8, ta, ma1558; RV64-NEXT: vslidedown.vi v24, v8, 161559; RV64-NEXT: addi a0, sp, 161560; RV64-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill1561; RV64-NEXT: vslidedown.vi v0, v16, 161562; RV64-NEXT: vsetivli zero, 16, e32, m4, ta, ma1563; RV64-NEXT: vwaddu.vv v24, v8, v161564; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload1565; RV64-NEXT: vwaddu.vv v8, v16, v01566; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma1567; RV64-NEXT: vadd.vv v8, v24, v81568; RV64-NEXT: vmv.s.x v16, zero1569; RV64-NEXT: vredsum.vs v8, v8, v161570; RV64-NEXT: vmv.x.s a0, v81571; RV64-NEXT: csrr a1, vlenb1572; RV64-NEXT: slli a1, a1, 31573; RV64-NEXT: add sp, sp, a11574; RV64-NEXT: .cfi_def_cfa sp, 161575; RV64-NEXT: addi sp, sp, 161576; RV64-NEXT: .cfi_def_cfa_offset 01577; RV64-NEXT: ret1578 %v = load <64 x i32>, ptr %x1579 %e = zext <64 x i32> %v to <64 x i64>1580 %red = call i64 @llvm.vector.reduce.add.v64i64(<64 x i64> %e)1581 ret i64 %red1582}1583 1584define i8 @vreduce_and_v1i8(<1 x i8> %v) {1585; CHECK-LABEL: vreduce_and_v1i8:1586; CHECK: # %bb.0:1587; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma1588; CHECK-NEXT: vmv.x.s a0, v81589; CHECK-NEXT: ret1590 %red = call i8 @llvm.vector.reduce.and.v1i8(<1 x i8> %v)1591 ret i8 %red1592}1593 1594define i8 @vreduce_and_v2i8(ptr %x) {1595; CHECK-LABEL: vreduce_and_v2i8:1596; CHECK: # %bb.0:1597; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma1598; CHECK-NEXT: vle8.v v8, (a0)1599; CHECK-NEXT: vredand.vs v8, v8, v81600; CHECK-NEXT: vmv.x.s a0, v81601; CHECK-NEXT: ret1602 %v = load <2 x i8>, ptr %x1603 %red = call i8 @llvm.vector.reduce.and.v2i8(<2 x i8> %v)1604 ret i8 %red1605}1606 1607define i8 @vreduce_and_v3i8(ptr %x) {1608; CHECK-LABEL: vreduce_and_v3i8:1609; CHECK: # %bb.0:1610; CHECK-NEXT: vsetivli zero, 3, e8, mf4, ta, ma1611; CHECK-NEXT: vle8.v v8, (a0)1612; CHECK-NEXT: li a0, -11613; CHECK-NEXT: vmv.s.x v9, a01614; CHECK-NEXT: vredand.vs v8, v8, v91615; CHECK-NEXT: vmv.x.s a0, v81616; CHECK-NEXT: ret1617 %v = load <3 x i8>, ptr %x1618 %red = call i8 @llvm.vector.reduce.and.v3i8(<3 x i8> %v)1619 ret i8 %red1620}1621 1622define i8 @vreduce_and_v4i8(ptr %x) {1623; CHECK-LABEL: vreduce_and_v4i8:1624; CHECK: # %bb.0:1625; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma1626; CHECK-NEXT: vle8.v v8, (a0)1627; CHECK-NEXT: vredand.vs v8, v8, v81628; CHECK-NEXT: vmv.x.s a0, v81629; CHECK-NEXT: ret1630 %v = load <4 x i8>, ptr %x1631 %red = call i8 @llvm.vector.reduce.and.v4i8(<4 x i8> %v)1632 ret i8 %red1633}1634 1635define i8 @vreduce_and_v8i8(ptr %x) {1636; CHECK-LABEL: vreduce_and_v8i8:1637; CHECK: # %bb.0:1638; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma1639; CHECK-NEXT: vle8.v v8, (a0)1640; CHECK-NEXT: vredand.vs v8, v8, v81641; CHECK-NEXT: vmv.x.s a0, v81642; CHECK-NEXT: ret1643 %v = load <8 x i8>, ptr %x1644 %red = call i8 @llvm.vector.reduce.and.v8i8(<8 x i8> %v)1645 ret i8 %red1646}1647 1648define i8 @vreduce_and_v16i8(ptr %x) {1649; CHECK-LABEL: vreduce_and_v16i8:1650; CHECK: # %bb.0:1651; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma1652; CHECK-NEXT: vle8.v v8, (a0)1653; CHECK-NEXT: vredand.vs v8, v8, v81654; CHECK-NEXT: vmv.x.s a0, v81655; CHECK-NEXT: ret1656 %v = load <16 x i8>, ptr %x1657 %red = call i8 @llvm.vector.reduce.and.v16i8(<16 x i8> %v)1658 ret i8 %red1659}1660 1661define i8 @vreduce_and_v32i8(ptr %x) {1662; CHECK-LABEL: vreduce_and_v32i8:1663; CHECK: # %bb.0:1664; CHECK-NEXT: li a1, 321665; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma1666; CHECK-NEXT: vle8.v v8, (a0)1667; CHECK-NEXT: vredand.vs v8, v8, v81668; CHECK-NEXT: vmv.x.s a0, v81669; CHECK-NEXT: ret1670 %v = load <32 x i8>, ptr %x1671 %red = call i8 @llvm.vector.reduce.and.v32i8(<32 x i8> %v)1672 ret i8 %red1673}1674 1675define i8 @vreduce_and_v64i8(ptr %x) {1676; CHECK-LABEL: vreduce_and_v64i8:1677; CHECK: # %bb.0:1678; CHECK-NEXT: li a1, 641679; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma1680; CHECK-NEXT: vle8.v v8, (a0)1681; CHECK-NEXT: vredand.vs v8, v8, v81682; CHECK-NEXT: vmv.x.s a0, v81683; CHECK-NEXT: ret1684 %v = load <64 x i8>, ptr %x1685 %red = call i8 @llvm.vector.reduce.and.v64i8(<64 x i8> %v)1686 ret i8 %red1687}1688 1689define i8 @vreduce_and_v128i8(ptr %x) {1690; CHECK-LABEL: vreduce_and_v128i8:1691; CHECK: # %bb.0:1692; CHECK-NEXT: li a1, 1281693; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma1694; CHECK-NEXT: vle8.v v8, (a0)1695; CHECK-NEXT: vredand.vs v8, v8, v81696; CHECK-NEXT: vmv.x.s a0, v81697; CHECK-NEXT: ret1698 %v = load <128 x i8>, ptr %x1699 %red = call i8 @llvm.vector.reduce.and.v128i8(<128 x i8> %v)1700 ret i8 %red1701}1702 1703define i8 @vreduce_and_v256i8(ptr %x) {1704; CHECK-LABEL: vreduce_and_v256i8:1705; CHECK: # %bb.0:1706; CHECK-NEXT: li a1, 1281707; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma1708; CHECK-NEXT: vle8.v v8, (a0)1709; CHECK-NEXT: addi a0, a0, 1281710; CHECK-NEXT: vle8.v v16, (a0)1711; CHECK-NEXT: vand.vv v8, v8, v161712; CHECK-NEXT: vredand.vs v8, v8, v81713; CHECK-NEXT: vmv.x.s a0, v81714; CHECK-NEXT: ret1715 %v = load <256 x i8>, ptr %x1716 %red = call i8 @llvm.vector.reduce.and.v256i8(<256 x i8> %v)1717 ret i8 %red1718}1719 1720define i16 @vreduce_and_v1i16(<1 x i16> %v) {1721; CHECK-LABEL: vreduce_and_v1i16:1722; CHECK: # %bb.0:1723; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma1724; CHECK-NEXT: vmv.x.s a0, v81725; CHECK-NEXT: ret1726 %red = call i16 @llvm.vector.reduce.and.v1i16(<1 x i16> %v)1727 ret i16 %red1728}1729 1730define i16 @vreduce_and_v2i16(ptr %x) {1731; CHECK-LABEL: vreduce_and_v2i16:1732; CHECK: # %bb.0:1733; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma1734; CHECK-NEXT: vle16.v v8, (a0)1735; CHECK-NEXT: vredand.vs v8, v8, v81736; CHECK-NEXT: vmv.x.s a0, v81737; CHECK-NEXT: ret1738 %v = load <2 x i16>, ptr %x1739 %red = call i16 @llvm.vector.reduce.and.v2i16(<2 x i16> %v)1740 ret i16 %red1741}1742 1743define i16 @vreduce_and_v4i16(ptr %x) {1744; CHECK-LABEL: vreduce_and_v4i16:1745; CHECK: # %bb.0:1746; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma1747; CHECK-NEXT: vle16.v v8, (a0)1748; CHECK-NEXT: vredand.vs v8, v8, v81749; CHECK-NEXT: vmv.x.s a0, v81750; CHECK-NEXT: ret1751 %v = load <4 x i16>, ptr %x1752 %red = call i16 @llvm.vector.reduce.and.v4i16(<4 x i16> %v)1753 ret i16 %red1754}1755 1756define i16 @vreduce_and_v8i16(ptr %x) {1757; CHECK-LABEL: vreduce_and_v8i16:1758; CHECK: # %bb.0:1759; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma1760; CHECK-NEXT: vle16.v v8, (a0)1761; CHECK-NEXT: vredand.vs v8, v8, v81762; CHECK-NEXT: vmv.x.s a0, v81763; CHECK-NEXT: ret1764 %v = load <8 x i16>, ptr %x1765 %red = call i16 @llvm.vector.reduce.and.v8i16(<8 x i16> %v)1766 ret i16 %red1767}1768 1769define i16 @vreduce_and_v16i16(ptr %x) {1770; CHECK-LABEL: vreduce_and_v16i16:1771; CHECK: # %bb.0:1772; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma1773; CHECK-NEXT: vle16.v v8, (a0)1774; CHECK-NEXT: vredand.vs v8, v8, v81775; CHECK-NEXT: vmv.x.s a0, v81776; CHECK-NEXT: ret1777 %v = load <16 x i16>, ptr %x1778 %red = call i16 @llvm.vector.reduce.and.v16i16(<16 x i16> %v)1779 ret i16 %red1780}1781 1782define i16 @vreduce_and_v32i16(ptr %x) {1783; CHECK-LABEL: vreduce_and_v32i16:1784; CHECK: # %bb.0:1785; CHECK-NEXT: li a1, 321786; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma1787; CHECK-NEXT: vle16.v v8, (a0)1788; CHECK-NEXT: vredand.vs v8, v8, v81789; CHECK-NEXT: vmv.x.s a0, v81790; CHECK-NEXT: ret1791 %v = load <32 x i16>, ptr %x1792 %red = call i16 @llvm.vector.reduce.and.v32i16(<32 x i16> %v)1793 ret i16 %red1794}1795 1796define i16 @vreduce_and_v64i16(ptr %x) {1797; CHECK-LABEL: vreduce_and_v64i16:1798; CHECK: # %bb.0:1799; CHECK-NEXT: li a1, 641800; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma1801; CHECK-NEXT: vle16.v v8, (a0)1802; CHECK-NEXT: vredand.vs v8, v8, v81803; CHECK-NEXT: vmv.x.s a0, v81804; CHECK-NEXT: ret1805 %v = load <64 x i16>, ptr %x1806 %red = call i16 @llvm.vector.reduce.and.v64i16(<64 x i16> %v)1807 ret i16 %red1808}1809 1810define i16 @vreduce_and_v128i16(ptr %x) {1811; CHECK-LABEL: vreduce_and_v128i16:1812; CHECK: # %bb.0:1813; CHECK-NEXT: li a1, 641814; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma1815; CHECK-NEXT: vle16.v v8, (a0)1816; CHECK-NEXT: addi a0, a0, 1281817; CHECK-NEXT: vle16.v v16, (a0)1818; CHECK-NEXT: vand.vv v8, v8, v161819; CHECK-NEXT: vredand.vs v8, v8, v81820; CHECK-NEXT: vmv.x.s a0, v81821; CHECK-NEXT: ret1822 %v = load <128 x i16>, ptr %x1823 %red = call i16 @llvm.vector.reduce.and.v128i16(<128 x i16> %v)1824 ret i16 %red1825}1826 1827define i32 @vreduce_and_v1i32(<1 x i32> %v) {1828; CHECK-LABEL: vreduce_and_v1i32:1829; CHECK: # %bb.0:1830; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma1831; CHECK-NEXT: vmv.x.s a0, v81832; CHECK-NEXT: ret1833 %red = call i32 @llvm.vector.reduce.and.v1i32(<1 x i32> %v)1834 ret i32 %red1835}1836 1837define i32 @vreduce_and_v2i32(ptr %x) {1838; CHECK-LABEL: vreduce_and_v2i32:1839; CHECK: # %bb.0:1840; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma1841; CHECK-NEXT: vle32.v v8, (a0)1842; CHECK-NEXT: vredand.vs v8, v8, v81843; CHECK-NEXT: vmv.x.s a0, v81844; CHECK-NEXT: ret1845 %v = load <2 x i32>, ptr %x1846 %red = call i32 @llvm.vector.reduce.and.v2i32(<2 x i32> %v)1847 ret i32 %red1848}1849 1850define i32 @vreduce_and_v4i32(ptr %x) {1851; CHECK-LABEL: vreduce_and_v4i32:1852; CHECK: # %bb.0:1853; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma1854; CHECK-NEXT: vle32.v v8, (a0)1855; CHECK-NEXT: vredand.vs v8, v8, v81856; CHECK-NEXT: vmv.x.s a0, v81857; CHECK-NEXT: ret1858 %v = load <4 x i32>, ptr %x1859 %red = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> %v)1860 ret i32 %red1861}1862 1863define i32 @vreduce_and_v8i32(ptr %x) {1864; CHECK-LABEL: vreduce_and_v8i32:1865; CHECK: # %bb.0:1866; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma1867; CHECK-NEXT: vle32.v v8, (a0)1868; CHECK-NEXT: vredand.vs v8, v8, v81869; CHECK-NEXT: vmv.x.s a0, v81870; CHECK-NEXT: ret1871 %v = load <8 x i32>, ptr %x1872 %red = call i32 @llvm.vector.reduce.and.v8i32(<8 x i32> %v)1873 ret i32 %red1874}1875 1876define i32 @vreduce_and_v16i32(ptr %x) {1877; CHECK-LABEL: vreduce_and_v16i32:1878; CHECK: # %bb.0:1879; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma1880; CHECK-NEXT: vle32.v v8, (a0)1881; CHECK-NEXT: vredand.vs v8, v8, v81882; CHECK-NEXT: vmv.x.s a0, v81883; CHECK-NEXT: ret1884 %v = load <16 x i32>, ptr %x1885 %red = call i32 @llvm.vector.reduce.and.v16i32(<16 x i32> %v)1886 ret i32 %red1887}1888 1889define i32 @vreduce_and_v32i32(ptr %x) {1890; CHECK-LABEL: vreduce_and_v32i32:1891; CHECK: # %bb.0:1892; CHECK-NEXT: li a1, 321893; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma1894; CHECK-NEXT: vle32.v v8, (a0)1895; CHECK-NEXT: vredand.vs v8, v8, v81896; CHECK-NEXT: vmv.x.s a0, v81897; CHECK-NEXT: ret1898 %v = load <32 x i32>, ptr %x1899 %red = call i32 @llvm.vector.reduce.and.v32i32(<32 x i32> %v)1900 ret i32 %red1901}1902 1903define i32 @vreduce_and_v64i32(ptr %x) {1904; CHECK-LABEL: vreduce_and_v64i32:1905; CHECK: # %bb.0:1906; CHECK-NEXT: li a1, 321907; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma1908; CHECK-NEXT: vle32.v v8, (a0)1909; CHECK-NEXT: addi a0, a0, 1281910; CHECK-NEXT: vle32.v v16, (a0)1911; CHECK-NEXT: vand.vv v8, v8, v161912; CHECK-NEXT: vredand.vs v8, v8, v81913; CHECK-NEXT: vmv.x.s a0, v81914; CHECK-NEXT: ret1915 %v = load <64 x i32>, ptr %x1916 %red = call i32 @llvm.vector.reduce.and.v64i32(<64 x i32> %v)1917 ret i32 %red1918}1919 1920define i64 @vreduce_and_v1i64(<1 x i64> %v) {1921; RV32-LABEL: vreduce_and_v1i64:1922; RV32: # %bb.0:1923; RV32-NEXT: li a0, 321924; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1925; RV32-NEXT: vsrl.vx v9, v8, a01926; RV32-NEXT: vmv.x.s a1, v91927; RV32-NEXT: vmv.x.s a0, v81928; RV32-NEXT: ret1929;1930; RV64-LABEL: vreduce_and_v1i64:1931; RV64: # %bb.0:1932; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma1933; RV64-NEXT: vmv.x.s a0, v81934; RV64-NEXT: ret1935 %red = call i64 @llvm.vector.reduce.and.v1i64(<1 x i64> %v)1936 ret i64 %red1937}1938 1939define i64 @vreduce_and_v2i64(ptr %x) {1940; RV32-LABEL: vreduce_and_v2i64:1941; RV32: # %bb.0:1942; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma1943; RV32-NEXT: vle64.v v8, (a0)1944; RV32-NEXT: li a0, 321945; RV32-NEXT: vredand.vs v8, v8, v81946; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1947; RV32-NEXT: vsrl.vx v9, v8, a01948; RV32-NEXT: vmv.x.s a1, v91949; RV32-NEXT: vmv.x.s a0, v81950; RV32-NEXT: ret1951;1952; RV64-LABEL: vreduce_and_v2i64:1953; RV64: # %bb.0:1954; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma1955; RV64-NEXT: vle64.v v8, (a0)1956; RV64-NEXT: vredand.vs v8, v8, v81957; RV64-NEXT: vmv.x.s a0, v81958; RV64-NEXT: ret1959 %v = load <2 x i64>, ptr %x1960 %red = call i64 @llvm.vector.reduce.and.v2i64(<2 x i64> %v)1961 ret i64 %red1962}1963 1964define i64 @vreduce_and_v4i64(ptr %x) {1965; RV32-LABEL: vreduce_and_v4i64:1966; RV32: # %bb.0:1967; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma1968; RV32-NEXT: vle64.v v8, (a0)1969; RV32-NEXT: li a1, 321970; RV32-NEXT: vredand.vs v8, v8, v81971; RV32-NEXT: vmv.x.s a0, v81972; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1973; RV32-NEXT: vsrl.vx v8, v8, a11974; RV32-NEXT: vmv.x.s a1, v81975; RV32-NEXT: ret1976;1977; RV64-LABEL: vreduce_and_v4i64:1978; RV64: # %bb.0:1979; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma1980; RV64-NEXT: vle64.v v8, (a0)1981; RV64-NEXT: vredand.vs v8, v8, v81982; RV64-NEXT: vmv.x.s a0, v81983; RV64-NEXT: ret1984 %v = load <4 x i64>, ptr %x1985 %red = call i64 @llvm.vector.reduce.and.v4i64(<4 x i64> %v)1986 ret i64 %red1987}1988 1989define i64 @vreduce_and_v8i64(ptr %x) {1990; RV32-LABEL: vreduce_and_v8i64:1991; RV32: # %bb.0:1992; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma1993; RV32-NEXT: vle64.v v8, (a0)1994; RV32-NEXT: li a1, 321995; RV32-NEXT: vredand.vs v8, v8, v81996; RV32-NEXT: vmv.x.s a0, v81997; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1998; RV32-NEXT: vsrl.vx v8, v8, a11999; RV32-NEXT: vmv.x.s a1, v82000; RV32-NEXT: ret2001;2002; RV64-LABEL: vreduce_and_v8i64:2003; RV64: # %bb.0:2004; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma2005; RV64-NEXT: vle64.v v8, (a0)2006; RV64-NEXT: vredand.vs v8, v8, v82007; RV64-NEXT: vmv.x.s a0, v82008; RV64-NEXT: ret2009 %v = load <8 x i64>, ptr %x2010 %red = call i64 @llvm.vector.reduce.and.v8i64(<8 x i64> %v)2011 ret i64 %red2012}2013 2014define i64 @vreduce_and_v16i64(ptr %x) {2015; RV32-LABEL: vreduce_and_v16i64:2016; RV32: # %bb.0:2017; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma2018; RV32-NEXT: vle64.v v8, (a0)2019; RV32-NEXT: li a1, 322020; RV32-NEXT: vredand.vs v8, v8, v82021; RV32-NEXT: vmv.x.s a0, v82022; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma2023; RV32-NEXT: vsrl.vx v8, v8, a12024; RV32-NEXT: vmv.x.s a1, v82025; RV32-NEXT: ret2026;2027; RV64-LABEL: vreduce_and_v16i64:2028; RV64: # %bb.0:2029; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma2030; RV64-NEXT: vle64.v v8, (a0)2031; RV64-NEXT: vredand.vs v8, v8, v82032; RV64-NEXT: vmv.x.s a0, v82033; RV64-NEXT: ret2034 %v = load <16 x i64>, ptr %x2035 %red = call i64 @llvm.vector.reduce.and.v16i64(<16 x i64> %v)2036 ret i64 %red2037}2038 2039define i64 @vreduce_and_v32i64(ptr %x) {2040; RV32-LABEL: vreduce_and_v32i64:2041; RV32: # %bb.0:2042; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma2043; RV32-NEXT: vle64.v v8, (a0)2044; RV32-NEXT: addi a0, a0, 1282045; RV32-NEXT: vle64.v v16, (a0)2046; RV32-NEXT: li a1, 322047; RV32-NEXT: vand.vv v8, v8, v162048; RV32-NEXT: vredand.vs v8, v8, v82049; RV32-NEXT: vmv.x.s a0, v82050; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma2051; RV32-NEXT: vsrl.vx v8, v8, a12052; RV32-NEXT: vmv.x.s a1, v82053; RV32-NEXT: ret2054;2055; RV64-LABEL: vreduce_and_v32i64:2056; RV64: # %bb.0:2057; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma2058; RV64-NEXT: vle64.v v8, (a0)2059; RV64-NEXT: addi a0, a0, 1282060; RV64-NEXT: vle64.v v16, (a0)2061; RV64-NEXT: vand.vv v8, v8, v162062; RV64-NEXT: vredand.vs v8, v8, v82063; RV64-NEXT: vmv.x.s a0, v82064; RV64-NEXT: ret2065 %v = load <32 x i64>, ptr %x2066 %red = call i64 @llvm.vector.reduce.and.v32i64(<32 x i64> %v)2067 ret i64 %red2068}2069 2070define i64 @vreduce_and_v64i64(ptr %x) nounwind {2071; RV32-LABEL: vreduce_and_v64i64:2072; RV32: # %bb.0:2073; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma2074; RV32-NEXT: vle64.v v8, (a0)2075; RV32-NEXT: addi a1, a0, 3842076; RV32-NEXT: vle64.v v16, (a1)2077; RV32-NEXT: addi a1, a0, 2562078; RV32-NEXT: addi a0, a0, 1282079; RV32-NEXT: vle64.v v0, (a0)2080; RV32-NEXT: vle64.v v24, (a1)2081; RV32-NEXT: li a1, 322082; RV32-NEXT: vand.vv v16, v0, v162083; RV32-NEXT: vand.vv v8, v8, v242084; RV32-NEXT: vand.vv v8, v8, v162085; RV32-NEXT: vredand.vs v8, v8, v82086; RV32-NEXT: vmv.x.s a0, v82087; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma2088; RV32-NEXT: vsrl.vx v8, v8, a12089; RV32-NEXT: vmv.x.s a1, v82090; RV32-NEXT: ret2091;2092; RV64-LABEL: vreduce_and_v64i64:2093; RV64: # %bb.0:2094; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma2095; RV64-NEXT: vle64.v v8, (a0)2096; RV64-NEXT: addi a1, a0, 3842097; RV64-NEXT: vle64.v v16, (a1)2098; RV64-NEXT: addi a1, a0, 2562099; RV64-NEXT: addi a0, a0, 1282100; RV64-NEXT: vle64.v v24, (a0)2101; RV64-NEXT: vle64.v v0, (a1)2102; RV64-NEXT: vand.vv v16, v24, v162103; RV64-NEXT: vand.vv v8, v8, v02104; RV64-NEXT: vand.vv v8, v8, v162105; RV64-NEXT: vredand.vs v8, v8, v82106; RV64-NEXT: vmv.x.s a0, v82107; RV64-NEXT: ret2108 %v = load <64 x i64>, ptr %x2109 %red = call i64 @llvm.vector.reduce.and.v64i64(<64 x i64> %v)2110 ret i64 %red2111}2112 2113define i8 @vreduce_or_v1i8(<1 x i8> %v) {2114; CHECK-LABEL: vreduce_or_v1i8:2115; CHECK: # %bb.0:2116; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma2117; CHECK-NEXT: vmv.x.s a0, v82118; CHECK-NEXT: ret2119 %red = call i8 @llvm.vector.reduce.or.v1i8(<1 x i8> %v)2120 ret i8 %red2121}2122 2123define i8 @vreduce_or_v2i8(ptr %x) {2124; CHECK-LABEL: vreduce_or_v2i8:2125; CHECK: # %bb.0:2126; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma2127; CHECK-NEXT: vle8.v v8, (a0)2128; CHECK-NEXT: vredor.vs v8, v8, v82129; CHECK-NEXT: vmv.x.s a0, v82130; CHECK-NEXT: ret2131 %v = load <2 x i8>, ptr %x2132 %red = call i8 @llvm.vector.reduce.or.v2i8(<2 x i8> %v)2133 ret i8 %red2134}2135 2136define i8 @vreduce_or_v3i8(ptr %x) {2137; CHECK-LABEL: vreduce_or_v3i8:2138; CHECK: # %bb.0:2139; CHECK-NEXT: vsetivli zero, 3, e8, mf4, ta, ma2140; CHECK-NEXT: vle8.v v8, (a0)2141; CHECK-NEXT: vmv.s.x v9, zero2142; CHECK-NEXT: vredor.vs v8, v8, v92143; CHECK-NEXT: vmv.x.s a0, v82144; CHECK-NEXT: ret2145 %v = load <3 x i8>, ptr %x2146 %red = call i8 @llvm.vector.reduce.or.v3i8(<3 x i8> %v)2147 ret i8 %red2148}2149 2150define i8 @vreduce_or_v4i8(ptr %x) {2151; CHECK-LABEL: vreduce_or_v4i8:2152; CHECK: # %bb.0:2153; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma2154; CHECK-NEXT: vle8.v v8, (a0)2155; CHECK-NEXT: vredor.vs v8, v8, v82156; CHECK-NEXT: vmv.x.s a0, v82157; CHECK-NEXT: ret2158 %v = load <4 x i8>, ptr %x2159 %red = call i8 @llvm.vector.reduce.or.v4i8(<4 x i8> %v)2160 ret i8 %red2161}2162 2163define i8 @vreduce_or_v8i8(ptr %x) {2164; CHECK-LABEL: vreduce_or_v8i8:2165; CHECK: # %bb.0:2166; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma2167; CHECK-NEXT: vle8.v v8, (a0)2168; CHECK-NEXT: vredor.vs v8, v8, v82169; CHECK-NEXT: vmv.x.s a0, v82170; CHECK-NEXT: ret2171 %v = load <8 x i8>, ptr %x2172 %red = call i8 @llvm.vector.reduce.or.v8i8(<8 x i8> %v)2173 ret i8 %red2174}2175 2176define i8 @vreduce_or_v16i8(ptr %x) {2177; CHECK-LABEL: vreduce_or_v16i8:2178; CHECK: # %bb.0:2179; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma2180; CHECK-NEXT: vle8.v v8, (a0)2181; CHECK-NEXT: vredor.vs v8, v8, v82182; CHECK-NEXT: vmv.x.s a0, v82183; CHECK-NEXT: ret2184 %v = load <16 x i8>, ptr %x2185 %red = call i8 @llvm.vector.reduce.or.v16i8(<16 x i8> %v)2186 ret i8 %red2187}2188 2189define i8 @vreduce_or_v32i8(ptr %x) {2190; CHECK-LABEL: vreduce_or_v32i8:2191; CHECK: # %bb.0:2192; CHECK-NEXT: li a1, 322193; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma2194; CHECK-NEXT: vle8.v v8, (a0)2195; CHECK-NEXT: vredor.vs v8, v8, v82196; CHECK-NEXT: vmv.x.s a0, v82197; CHECK-NEXT: ret2198 %v = load <32 x i8>, ptr %x2199 %red = call i8 @llvm.vector.reduce.or.v32i8(<32 x i8> %v)2200 ret i8 %red2201}2202 2203define i8 @vreduce_or_v64i8(ptr %x) {2204; CHECK-LABEL: vreduce_or_v64i8:2205; CHECK: # %bb.0:2206; CHECK-NEXT: li a1, 642207; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma2208; CHECK-NEXT: vle8.v v8, (a0)2209; CHECK-NEXT: vredor.vs v8, v8, v82210; CHECK-NEXT: vmv.x.s a0, v82211; CHECK-NEXT: ret2212 %v = load <64 x i8>, ptr %x2213 %red = call i8 @llvm.vector.reduce.or.v64i8(<64 x i8> %v)2214 ret i8 %red2215}2216 2217define i8 @vreduce_or_v128i8(ptr %x) {2218; CHECK-LABEL: vreduce_or_v128i8:2219; CHECK: # %bb.0:2220; CHECK-NEXT: li a1, 1282221; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma2222; CHECK-NEXT: vle8.v v8, (a0)2223; CHECK-NEXT: vredor.vs v8, v8, v82224; CHECK-NEXT: vmv.x.s a0, v82225; CHECK-NEXT: ret2226 %v = load <128 x i8>, ptr %x2227 %red = call i8 @llvm.vector.reduce.or.v128i8(<128 x i8> %v)2228 ret i8 %red2229}2230 2231define i8 @vreduce_or_v256i8(ptr %x) {2232; CHECK-LABEL: vreduce_or_v256i8:2233; CHECK: # %bb.0:2234; CHECK-NEXT: li a1, 1282235; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma2236; CHECK-NEXT: vle8.v v8, (a0)2237; CHECK-NEXT: addi a0, a0, 1282238; CHECK-NEXT: vle8.v v16, (a0)2239; CHECK-NEXT: vor.vv v8, v8, v162240; CHECK-NEXT: vredor.vs v8, v8, v82241; CHECK-NEXT: vmv.x.s a0, v82242; CHECK-NEXT: ret2243 %v = load <256 x i8>, ptr %x2244 %red = call i8 @llvm.vector.reduce.or.v256i8(<256 x i8> %v)2245 ret i8 %red2246}2247 2248define i16 @vreduce_or_v1i16(<1 x i16> %v) {2249; CHECK-LABEL: vreduce_or_v1i16:2250; CHECK: # %bb.0:2251; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma2252; CHECK-NEXT: vmv.x.s a0, v82253; CHECK-NEXT: ret2254 %red = call i16 @llvm.vector.reduce.or.v1i16(<1 x i16> %v)2255 ret i16 %red2256}2257 2258define i16 @vreduce_or_v2i16(ptr %x) {2259; CHECK-LABEL: vreduce_or_v2i16:2260; CHECK: # %bb.0:2261; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma2262; CHECK-NEXT: vle16.v v8, (a0)2263; CHECK-NEXT: vredor.vs v8, v8, v82264; CHECK-NEXT: vmv.x.s a0, v82265; CHECK-NEXT: ret2266 %v = load <2 x i16>, ptr %x2267 %red = call i16 @llvm.vector.reduce.or.v2i16(<2 x i16> %v)2268 ret i16 %red2269}2270 2271define i16 @vreduce_or_v4i16(ptr %x) {2272; CHECK-LABEL: vreduce_or_v4i16:2273; CHECK: # %bb.0:2274; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma2275; CHECK-NEXT: vle16.v v8, (a0)2276; CHECK-NEXT: vredor.vs v8, v8, v82277; CHECK-NEXT: vmv.x.s a0, v82278; CHECK-NEXT: ret2279 %v = load <4 x i16>, ptr %x2280 %red = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> %v)2281 ret i16 %red2282}2283 2284define i16 @vreduce_or_v8i16(ptr %x) {2285; CHECK-LABEL: vreduce_or_v8i16:2286; CHECK: # %bb.0:2287; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma2288; CHECK-NEXT: vle16.v v8, (a0)2289; CHECK-NEXT: vredor.vs v8, v8, v82290; CHECK-NEXT: vmv.x.s a0, v82291; CHECK-NEXT: ret2292 %v = load <8 x i16>, ptr %x2293 %red = call i16 @llvm.vector.reduce.or.v8i16(<8 x i16> %v)2294 ret i16 %red2295}2296 2297define i16 @vreduce_or_v16i16(ptr %x) {2298; CHECK-LABEL: vreduce_or_v16i16:2299; CHECK: # %bb.0:2300; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma2301; CHECK-NEXT: vle16.v v8, (a0)2302; CHECK-NEXT: vredor.vs v8, v8, v82303; CHECK-NEXT: vmv.x.s a0, v82304; CHECK-NEXT: ret2305 %v = load <16 x i16>, ptr %x2306 %red = call i16 @llvm.vector.reduce.or.v16i16(<16 x i16> %v)2307 ret i16 %red2308}2309 2310define i16 @vreduce_or_v32i16(ptr %x) {2311; CHECK-LABEL: vreduce_or_v32i16:2312; CHECK: # %bb.0:2313; CHECK-NEXT: li a1, 322314; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma2315; CHECK-NEXT: vle16.v v8, (a0)2316; CHECK-NEXT: vredor.vs v8, v8, v82317; CHECK-NEXT: vmv.x.s a0, v82318; CHECK-NEXT: ret2319 %v = load <32 x i16>, ptr %x2320 %red = call i16 @llvm.vector.reduce.or.v32i16(<32 x i16> %v)2321 ret i16 %red2322}2323 2324define i16 @vreduce_or_v64i16(ptr %x) {2325; CHECK-LABEL: vreduce_or_v64i16:2326; CHECK: # %bb.0:2327; CHECK-NEXT: li a1, 642328; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma2329; CHECK-NEXT: vle16.v v8, (a0)2330; CHECK-NEXT: vredor.vs v8, v8, v82331; CHECK-NEXT: vmv.x.s a0, v82332; CHECK-NEXT: ret2333 %v = load <64 x i16>, ptr %x2334 %red = call i16 @llvm.vector.reduce.or.v64i16(<64 x i16> %v)2335 ret i16 %red2336}2337 2338define i16 @vreduce_or_v128i16(ptr %x) {2339; CHECK-LABEL: vreduce_or_v128i16:2340; CHECK: # %bb.0:2341; CHECK-NEXT: li a1, 642342; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma2343; CHECK-NEXT: vle16.v v8, (a0)2344; CHECK-NEXT: addi a0, a0, 1282345; CHECK-NEXT: vle16.v v16, (a0)2346; CHECK-NEXT: vor.vv v8, v8, v162347; CHECK-NEXT: vredor.vs v8, v8, v82348; CHECK-NEXT: vmv.x.s a0, v82349; CHECK-NEXT: ret2350 %v = load <128 x i16>, ptr %x2351 %red = call i16 @llvm.vector.reduce.or.v128i16(<128 x i16> %v)2352 ret i16 %red2353}2354 2355define i32 @vreduce_or_v1i32(<1 x i32> %v) {2356; CHECK-LABEL: vreduce_or_v1i32:2357; CHECK: # %bb.0:2358; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma2359; CHECK-NEXT: vmv.x.s a0, v82360; CHECK-NEXT: ret2361 %red = call i32 @llvm.vector.reduce.or.v1i32(<1 x i32> %v)2362 ret i32 %red2363}2364 2365define i32 @vreduce_or_v2i32(ptr %x) {2366; CHECK-LABEL: vreduce_or_v2i32:2367; CHECK: # %bb.0:2368; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma2369; CHECK-NEXT: vle32.v v8, (a0)2370; CHECK-NEXT: vredor.vs v8, v8, v82371; CHECK-NEXT: vmv.x.s a0, v82372; CHECK-NEXT: ret2373 %v = load <2 x i32>, ptr %x2374 %red = call i32 @llvm.vector.reduce.or.v2i32(<2 x i32> %v)2375 ret i32 %red2376}2377 2378define i32 @vreduce_or_v4i32(ptr %x) {2379; CHECK-LABEL: vreduce_or_v4i32:2380; CHECK: # %bb.0:2381; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma2382; CHECK-NEXT: vle32.v v8, (a0)2383; CHECK-NEXT: vredor.vs v8, v8, v82384; CHECK-NEXT: vmv.x.s a0, v82385; CHECK-NEXT: ret2386 %v = load <4 x i32>, ptr %x2387 %red = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> %v)2388 ret i32 %red2389}2390 2391define i32 @vreduce_or_v8i32(ptr %x) {2392; CHECK-LABEL: vreduce_or_v8i32:2393; CHECK: # %bb.0:2394; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma2395; CHECK-NEXT: vle32.v v8, (a0)2396; CHECK-NEXT: vredor.vs v8, v8, v82397; CHECK-NEXT: vmv.x.s a0, v82398; CHECK-NEXT: ret2399 %v = load <8 x i32>, ptr %x2400 %red = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> %v)2401 ret i32 %red2402}2403 2404define i32 @vreduce_or_v16i32(ptr %x) {2405; CHECK-LABEL: vreduce_or_v16i32:2406; CHECK: # %bb.0:2407; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma2408; CHECK-NEXT: vle32.v v8, (a0)2409; CHECK-NEXT: vredor.vs v8, v8, v82410; CHECK-NEXT: vmv.x.s a0, v82411; CHECK-NEXT: ret2412 %v = load <16 x i32>, ptr %x2413 %red = call i32 @llvm.vector.reduce.or.v16i32(<16 x i32> %v)2414 ret i32 %red2415}2416 2417define i32 @vreduce_or_v32i32(ptr %x) {2418; CHECK-LABEL: vreduce_or_v32i32:2419; CHECK: # %bb.0:2420; CHECK-NEXT: li a1, 322421; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma2422; CHECK-NEXT: vle32.v v8, (a0)2423; CHECK-NEXT: vredor.vs v8, v8, v82424; CHECK-NEXT: vmv.x.s a0, v82425; CHECK-NEXT: ret2426 %v = load <32 x i32>, ptr %x2427 %red = call i32 @llvm.vector.reduce.or.v32i32(<32 x i32> %v)2428 ret i32 %red2429}2430 2431define i32 @vreduce_or_v64i32(ptr %x) {2432; CHECK-LABEL: vreduce_or_v64i32:2433; CHECK: # %bb.0:2434; CHECK-NEXT: li a1, 322435; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma2436; CHECK-NEXT: vle32.v v8, (a0)2437; CHECK-NEXT: addi a0, a0, 1282438; CHECK-NEXT: vle32.v v16, (a0)2439; CHECK-NEXT: vor.vv v8, v8, v162440; CHECK-NEXT: vredor.vs v8, v8, v82441; CHECK-NEXT: vmv.x.s a0, v82442; CHECK-NEXT: ret2443 %v = load <64 x i32>, ptr %x2444 %red = call i32 @llvm.vector.reduce.or.v64i32(<64 x i32> %v)2445 ret i32 %red2446}2447 2448define i64 @vreduce_or_v1i64(<1 x i64> %v) {2449; RV32-LABEL: vreduce_or_v1i64:2450; RV32: # %bb.0:2451; RV32-NEXT: li a0, 322452; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma2453; RV32-NEXT: vsrl.vx v9, v8, a02454; RV32-NEXT: vmv.x.s a1, v92455; RV32-NEXT: vmv.x.s a0, v82456; RV32-NEXT: ret2457;2458; RV64-LABEL: vreduce_or_v1i64:2459; RV64: # %bb.0:2460; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma2461; RV64-NEXT: vmv.x.s a0, v82462; RV64-NEXT: ret2463 %red = call i64 @llvm.vector.reduce.or.v1i64(<1 x i64> %v)2464 ret i64 %red2465}2466 2467define i64 @vreduce_or_v2i64(ptr %x) {2468; RV32-LABEL: vreduce_or_v2i64:2469; RV32: # %bb.0:2470; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma2471; RV32-NEXT: vle64.v v8, (a0)2472; RV32-NEXT: li a0, 322473; RV32-NEXT: vredor.vs v8, v8, v82474; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma2475; RV32-NEXT: vsrl.vx v9, v8, a02476; RV32-NEXT: vmv.x.s a1, v92477; RV32-NEXT: vmv.x.s a0, v82478; RV32-NEXT: ret2479;2480; RV64-LABEL: vreduce_or_v2i64:2481; RV64: # %bb.0:2482; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma2483; RV64-NEXT: vle64.v v8, (a0)2484; RV64-NEXT: vredor.vs v8, v8, v82485; RV64-NEXT: vmv.x.s a0, v82486; RV64-NEXT: ret2487 %v = load <2 x i64>, ptr %x2488 %red = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> %v)2489 ret i64 %red2490}2491 2492define i64 @vreduce_or_v4i64(ptr %x) {2493; RV32-LABEL: vreduce_or_v4i64:2494; RV32: # %bb.0:2495; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma2496; RV32-NEXT: vle64.v v8, (a0)2497; RV32-NEXT: li a1, 322498; RV32-NEXT: vredor.vs v8, v8, v82499; RV32-NEXT: vmv.x.s a0, v82500; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma2501; RV32-NEXT: vsrl.vx v8, v8, a12502; RV32-NEXT: vmv.x.s a1, v82503; RV32-NEXT: ret2504;2505; RV64-LABEL: vreduce_or_v4i64:2506; RV64: # %bb.0:2507; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma2508; RV64-NEXT: vle64.v v8, (a0)2509; RV64-NEXT: vredor.vs v8, v8, v82510; RV64-NEXT: vmv.x.s a0, v82511; RV64-NEXT: ret2512 %v = load <4 x i64>, ptr %x2513 %red = call i64 @llvm.vector.reduce.or.v4i64(<4 x i64> %v)2514 ret i64 %red2515}2516 2517define i64 @vreduce_or_v8i64(ptr %x) {2518; RV32-LABEL: vreduce_or_v8i64:2519; RV32: # %bb.0:2520; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma2521; RV32-NEXT: vle64.v v8, (a0)2522; RV32-NEXT: li a1, 322523; RV32-NEXT: vredor.vs v8, v8, v82524; RV32-NEXT: vmv.x.s a0, v82525; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma2526; RV32-NEXT: vsrl.vx v8, v8, a12527; RV32-NEXT: vmv.x.s a1, v82528; RV32-NEXT: ret2529;2530; RV64-LABEL: vreduce_or_v8i64:2531; RV64: # %bb.0:2532; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma2533; RV64-NEXT: vle64.v v8, (a0)2534; RV64-NEXT: vredor.vs v8, v8, v82535; RV64-NEXT: vmv.x.s a0, v82536; RV64-NEXT: ret2537 %v = load <8 x i64>, ptr %x2538 %red = call i64 @llvm.vector.reduce.or.v8i64(<8 x i64> %v)2539 ret i64 %red2540}2541 2542define i64 @vreduce_or_v16i64(ptr %x) {2543; RV32-LABEL: vreduce_or_v16i64:2544; RV32: # %bb.0:2545; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma2546; RV32-NEXT: vle64.v v8, (a0)2547; RV32-NEXT: li a1, 322548; RV32-NEXT: vredor.vs v8, v8, v82549; RV32-NEXT: vmv.x.s a0, v82550; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma2551; RV32-NEXT: vsrl.vx v8, v8, a12552; RV32-NEXT: vmv.x.s a1, v82553; RV32-NEXT: ret2554;2555; RV64-LABEL: vreduce_or_v16i64:2556; RV64: # %bb.0:2557; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma2558; RV64-NEXT: vle64.v v8, (a0)2559; RV64-NEXT: vredor.vs v8, v8, v82560; RV64-NEXT: vmv.x.s a0, v82561; RV64-NEXT: ret2562 %v = load <16 x i64>, ptr %x2563 %red = call i64 @llvm.vector.reduce.or.v16i64(<16 x i64> %v)2564 ret i64 %red2565}2566 2567define i64 @vreduce_or_v32i64(ptr %x) {2568; RV32-LABEL: vreduce_or_v32i64:2569; RV32: # %bb.0:2570; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma2571; RV32-NEXT: vle64.v v8, (a0)2572; RV32-NEXT: addi a0, a0, 1282573; RV32-NEXT: vle64.v v16, (a0)2574; RV32-NEXT: li a1, 322575; RV32-NEXT: vor.vv v8, v8, v162576; RV32-NEXT: vredor.vs v8, v8, v82577; RV32-NEXT: vmv.x.s a0, v82578; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma2579; RV32-NEXT: vsrl.vx v8, v8, a12580; RV32-NEXT: vmv.x.s a1, v82581; RV32-NEXT: ret2582;2583; RV64-LABEL: vreduce_or_v32i64:2584; RV64: # %bb.0:2585; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma2586; RV64-NEXT: vle64.v v8, (a0)2587; RV64-NEXT: addi a0, a0, 1282588; RV64-NEXT: vle64.v v16, (a0)2589; RV64-NEXT: vor.vv v8, v8, v162590; RV64-NEXT: vredor.vs v8, v8, v82591; RV64-NEXT: vmv.x.s a0, v82592; RV64-NEXT: ret2593 %v = load <32 x i64>, ptr %x2594 %red = call i64 @llvm.vector.reduce.or.v32i64(<32 x i64> %v)2595 ret i64 %red2596}2597 2598define i64 @vreduce_or_v64i64(ptr %x) nounwind {2599; RV32-LABEL: vreduce_or_v64i64:2600; RV32: # %bb.0:2601; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma2602; RV32-NEXT: vle64.v v8, (a0)2603; RV32-NEXT: addi a1, a0, 3842604; RV32-NEXT: vle64.v v16, (a1)2605; RV32-NEXT: addi a1, a0, 2562606; RV32-NEXT: addi a0, a0, 1282607; RV32-NEXT: vle64.v v0, (a0)2608; RV32-NEXT: vle64.v v24, (a1)2609; RV32-NEXT: li a1, 322610; RV32-NEXT: vor.vv v16, v0, v162611; RV32-NEXT: vor.vv v8, v8, v242612; RV32-NEXT: vor.vv v8, v8, v162613; RV32-NEXT: vredor.vs v8, v8, v82614; RV32-NEXT: vmv.x.s a0, v82615; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma2616; RV32-NEXT: vsrl.vx v8, v8, a12617; RV32-NEXT: vmv.x.s a1, v82618; RV32-NEXT: ret2619;2620; RV64-LABEL: vreduce_or_v64i64:2621; RV64: # %bb.0:2622; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma2623; RV64-NEXT: vle64.v v8, (a0)2624; RV64-NEXT: addi a1, a0, 3842625; RV64-NEXT: vle64.v v16, (a1)2626; RV64-NEXT: addi a1, a0, 2562627; RV64-NEXT: addi a0, a0, 1282628; RV64-NEXT: vle64.v v24, (a0)2629; RV64-NEXT: vle64.v v0, (a1)2630; RV64-NEXT: vor.vv v16, v24, v162631; RV64-NEXT: vor.vv v8, v8, v02632; RV64-NEXT: vor.vv v8, v8, v162633; RV64-NEXT: vredor.vs v8, v8, v82634; RV64-NEXT: vmv.x.s a0, v82635; RV64-NEXT: ret2636 %v = load <64 x i64>, ptr %x2637 %red = call i64 @llvm.vector.reduce.or.v64i64(<64 x i64> %v)2638 ret i64 %red2639}2640 2641define i8 @vreduce_xor_v1i8(<1 x i8> %v) {2642; CHECK-LABEL: vreduce_xor_v1i8:2643; CHECK: # %bb.0:2644; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma2645; CHECK-NEXT: vmv.x.s a0, v82646; CHECK-NEXT: ret2647 %red = call i8 @llvm.vector.reduce.xor.v1i8(<1 x i8> %v)2648 ret i8 %red2649}2650 2651define i8 @vreduce_xor_v2i8(ptr %x) {2652; CHECK-LABEL: vreduce_xor_v2i8:2653; CHECK: # %bb.0:2654; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma2655; CHECK-NEXT: vle8.v v8, (a0)2656; CHECK-NEXT: vmv.s.x v9, zero2657; CHECK-NEXT: vredxor.vs v8, v8, v92658; CHECK-NEXT: vmv.x.s a0, v82659; CHECK-NEXT: ret2660 %v = load <2 x i8>, ptr %x2661 %red = call i8 @llvm.vector.reduce.xor.v2i8(<2 x i8> %v)2662 ret i8 %red2663}2664 2665define i8 @vreduce_xor_v3i8(ptr %x) {2666; CHECK-LABEL: vreduce_xor_v3i8:2667; CHECK: # %bb.0:2668; CHECK-NEXT: vsetivli zero, 3, e8, mf4, ta, ma2669; CHECK-NEXT: vle8.v v8, (a0)2670; CHECK-NEXT: vmv.s.x v9, zero2671; CHECK-NEXT: vredxor.vs v8, v8, v92672; CHECK-NEXT: vmv.x.s a0, v82673; CHECK-NEXT: ret2674 %v = load <3 x i8>, ptr %x2675 %red = call i8 @llvm.vector.reduce.xor.v3i8(<3 x i8> %v)2676 ret i8 %red2677}2678 2679define i8 @vreduce_xor_v4i8(ptr %x) {2680; CHECK-LABEL: vreduce_xor_v4i8:2681; CHECK: # %bb.0:2682; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma2683; CHECK-NEXT: vle8.v v8, (a0)2684; CHECK-NEXT: vmv.s.x v9, zero2685; CHECK-NEXT: vredxor.vs v8, v8, v92686; CHECK-NEXT: vmv.x.s a0, v82687; CHECK-NEXT: ret2688 %v = load <4 x i8>, ptr %x2689 %red = call i8 @llvm.vector.reduce.xor.v4i8(<4 x i8> %v)2690 ret i8 %red2691}2692 2693define i8 @vreduce_xor_v8i8(ptr %x) {2694; CHECK-LABEL: vreduce_xor_v8i8:2695; CHECK: # %bb.0:2696; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma2697; CHECK-NEXT: vle8.v v8, (a0)2698; CHECK-NEXT: vmv.s.x v9, zero2699; CHECK-NEXT: vredxor.vs v8, v8, v92700; CHECK-NEXT: vmv.x.s a0, v82701; CHECK-NEXT: ret2702 %v = load <8 x i8>, ptr %x2703 %red = call i8 @llvm.vector.reduce.xor.v8i8(<8 x i8> %v)2704 ret i8 %red2705}2706 2707define i8 @vreduce_xor_v16i8(ptr %x) {2708; CHECK-LABEL: vreduce_xor_v16i8:2709; CHECK: # %bb.0:2710; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma2711; CHECK-NEXT: vle8.v v8, (a0)2712; CHECK-NEXT: vmv.s.x v9, zero2713; CHECK-NEXT: vredxor.vs v8, v8, v92714; CHECK-NEXT: vmv.x.s a0, v82715; CHECK-NEXT: ret2716 %v = load <16 x i8>, ptr %x2717 %red = call i8 @llvm.vector.reduce.xor.v16i8(<16 x i8> %v)2718 ret i8 %red2719}2720 2721define i8 @vreduce_xor_v32i8(ptr %x) {2722; CHECK-LABEL: vreduce_xor_v32i8:2723; CHECK: # %bb.0:2724; CHECK-NEXT: li a1, 322725; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma2726; CHECK-NEXT: vle8.v v8, (a0)2727; CHECK-NEXT: vmv.s.x v10, zero2728; CHECK-NEXT: vredxor.vs v8, v8, v102729; CHECK-NEXT: vmv.x.s a0, v82730; CHECK-NEXT: ret2731 %v = load <32 x i8>, ptr %x2732 %red = call i8 @llvm.vector.reduce.xor.v32i8(<32 x i8> %v)2733 ret i8 %red2734}2735 2736define i8 @vreduce_xor_v64i8(ptr %x) {2737; CHECK-LABEL: vreduce_xor_v64i8:2738; CHECK: # %bb.0:2739; CHECK-NEXT: li a1, 642740; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma2741; CHECK-NEXT: vle8.v v8, (a0)2742; CHECK-NEXT: vmv.s.x v12, zero2743; CHECK-NEXT: vredxor.vs v8, v8, v122744; CHECK-NEXT: vmv.x.s a0, v82745; CHECK-NEXT: ret2746 %v = load <64 x i8>, ptr %x2747 %red = call i8 @llvm.vector.reduce.xor.v64i8(<64 x i8> %v)2748 ret i8 %red2749}2750 2751define i8 @vreduce_xor_v128i8(ptr %x) {2752; CHECK-LABEL: vreduce_xor_v128i8:2753; CHECK: # %bb.0:2754; CHECK-NEXT: li a1, 1282755; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma2756; CHECK-NEXT: vle8.v v8, (a0)2757; CHECK-NEXT: vmv.s.x v16, zero2758; CHECK-NEXT: vredxor.vs v8, v8, v162759; CHECK-NEXT: vmv.x.s a0, v82760; CHECK-NEXT: ret2761 %v = load <128 x i8>, ptr %x2762 %red = call i8 @llvm.vector.reduce.xor.v128i8(<128 x i8> %v)2763 ret i8 %red2764}2765 2766define i8 @vreduce_xor_v256i8(ptr %x) {2767; CHECK-LABEL: vreduce_xor_v256i8:2768; CHECK: # %bb.0:2769; CHECK-NEXT: li a1, 1282770; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma2771; CHECK-NEXT: vle8.v v8, (a0)2772; CHECK-NEXT: addi a0, a0, 1282773; CHECK-NEXT: vle8.v v16, (a0)2774; CHECK-NEXT: vxor.vv v8, v8, v162775; CHECK-NEXT: vmv.s.x v16, zero2776; CHECK-NEXT: vredxor.vs v8, v8, v162777; CHECK-NEXT: vmv.x.s a0, v82778; CHECK-NEXT: ret2779 %v = load <256 x i8>, ptr %x2780 %red = call i8 @llvm.vector.reduce.xor.v256i8(<256 x i8> %v)2781 ret i8 %red2782}2783 2784define i16 @vreduce_xor_v1i16(<1 x i16> %v) {2785; CHECK-LABEL: vreduce_xor_v1i16:2786; CHECK: # %bb.0:2787; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma2788; CHECK-NEXT: vmv.x.s a0, v82789; CHECK-NEXT: ret2790 %red = call i16 @llvm.vector.reduce.xor.v1i16(<1 x i16> %v)2791 ret i16 %red2792}2793 2794define i16 @vreduce_xor_v2i16(ptr %x) {2795; CHECK-LABEL: vreduce_xor_v2i16:2796; CHECK: # %bb.0:2797; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma2798; CHECK-NEXT: vle16.v v8, (a0)2799; CHECK-NEXT: vmv.s.x v9, zero2800; CHECK-NEXT: vredxor.vs v8, v8, v92801; CHECK-NEXT: vmv.x.s a0, v82802; CHECK-NEXT: ret2803 %v = load <2 x i16>, ptr %x2804 %red = call i16 @llvm.vector.reduce.xor.v2i16(<2 x i16> %v)2805 ret i16 %red2806}2807 2808define i16 @vreduce_xor_v4i16(ptr %x) {2809; CHECK-LABEL: vreduce_xor_v4i16:2810; CHECK: # %bb.0:2811; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma2812; CHECK-NEXT: vle16.v v8, (a0)2813; CHECK-NEXT: vmv.s.x v9, zero2814; CHECK-NEXT: vredxor.vs v8, v8, v92815; CHECK-NEXT: vmv.x.s a0, v82816; CHECK-NEXT: ret2817 %v = load <4 x i16>, ptr %x2818 %red = call i16 @llvm.vector.reduce.xor.v4i16(<4 x i16> %v)2819 ret i16 %red2820}2821 2822define i16 @vreduce_xor_v8i16(ptr %x) {2823; CHECK-LABEL: vreduce_xor_v8i16:2824; CHECK: # %bb.0:2825; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma2826; CHECK-NEXT: vle16.v v8, (a0)2827; CHECK-NEXT: vmv.s.x v9, zero2828; CHECK-NEXT: vredxor.vs v8, v8, v92829; CHECK-NEXT: vmv.x.s a0, v82830; CHECK-NEXT: ret2831 %v = load <8 x i16>, ptr %x2832 %red = call i16 @llvm.vector.reduce.xor.v8i16(<8 x i16> %v)2833 ret i16 %red2834}2835 2836define i16 @vreduce_xor_v16i16(ptr %x) {2837; CHECK-LABEL: vreduce_xor_v16i16:2838; CHECK: # %bb.0:2839; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma2840; CHECK-NEXT: vle16.v v8, (a0)2841; CHECK-NEXT: vmv.s.x v10, zero2842; CHECK-NEXT: vredxor.vs v8, v8, v102843; CHECK-NEXT: vmv.x.s a0, v82844; CHECK-NEXT: ret2845 %v = load <16 x i16>, ptr %x2846 %red = call i16 @llvm.vector.reduce.xor.v16i16(<16 x i16> %v)2847 ret i16 %red2848}2849 2850define i16 @vreduce_xor_v32i16(ptr %x) {2851; CHECK-LABEL: vreduce_xor_v32i16:2852; CHECK: # %bb.0:2853; CHECK-NEXT: li a1, 322854; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma2855; CHECK-NEXT: vle16.v v8, (a0)2856; CHECK-NEXT: vmv.s.x v12, zero2857; CHECK-NEXT: vredxor.vs v8, v8, v122858; CHECK-NEXT: vmv.x.s a0, v82859; CHECK-NEXT: ret2860 %v = load <32 x i16>, ptr %x2861 %red = call i16 @llvm.vector.reduce.xor.v32i16(<32 x i16> %v)2862 ret i16 %red2863}2864 2865define i16 @vreduce_xor_v64i16(ptr %x) {2866; CHECK-LABEL: vreduce_xor_v64i16:2867; CHECK: # %bb.0:2868; CHECK-NEXT: li a1, 642869; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma2870; CHECK-NEXT: vle16.v v8, (a0)2871; CHECK-NEXT: vmv.s.x v16, zero2872; CHECK-NEXT: vredxor.vs v8, v8, v162873; CHECK-NEXT: vmv.x.s a0, v82874; CHECK-NEXT: ret2875 %v = load <64 x i16>, ptr %x2876 %red = call i16 @llvm.vector.reduce.xor.v64i16(<64 x i16> %v)2877 ret i16 %red2878}2879 2880define i16 @vreduce_xor_v128i16(ptr %x) {2881; CHECK-LABEL: vreduce_xor_v128i16:2882; CHECK: # %bb.0:2883; CHECK-NEXT: li a1, 642884; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma2885; CHECK-NEXT: vle16.v v8, (a0)2886; CHECK-NEXT: addi a0, a0, 1282887; CHECK-NEXT: vle16.v v16, (a0)2888; CHECK-NEXT: vxor.vv v8, v8, v162889; CHECK-NEXT: vmv.s.x v16, zero2890; CHECK-NEXT: vredxor.vs v8, v8, v162891; CHECK-NEXT: vmv.x.s a0, v82892; CHECK-NEXT: ret2893 %v = load <128 x i16>, ptr %x2894 %red = call i16 @llvm.vector.reduce.xor.v128i16(<128 x i16> %v)2895 ret i16 %red2896}2897 2898define i32 @vreduce_xor_v1i32(<1 x i32> %v) {2899; CHECK-LABEL: vreduce_xor_v1i32:2900; CHECK: # %bb.0:2901; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma2902; CHECK-NEXT: vmv.x.s a0, v82903; CHECK-NEXT: ret2904 %red = call i32 @llvm.vector.reduce.xor.v1i32(<1 x i32> %v)2905 ret i32 %red2906}2907 2908define i32 @vreduce_xor_v2i32(ptr %x) {2909; CHECK-LABEL: vreduce_xor_v2i32:2910; CHECK: # %bb.0:2911; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma2912; CHECK-NEXT: vle32.v v8, (a0)2913; CHECK-NEXT: vmv.s.x v9, zero2914; CHECK-NEXT: vredxor.vs v8, v8, v92915; CHECK-NEXT: vmv.x.s a0, v82916; CHECK-NEXT: ret2917 %v = load <2 x i32>, ptr %x2918 %red = call i32 @llvm.vector.reduce.xor.v2i32(<2 x i32> %v)2919 ret i32 %red2920}2921 2922define i32 @vreduce_xor_v4i32(ptr %x) {2923; CHECK-LABEL: vreduce_xor_v4i32:2924; CHECK: # %bb.0:2925; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma2926; CHECK-NEXT: vle32.v v8, (a0)2927; CHECK-NEXT: vmv.s.x v9, zero2928; CHECK-NEXT: vredxor.vs v8, v8, v92929; CHECK-NEXT: vmv.x.s a0, v82930; CHECK-NEXT: ret2931 %v = load <4 x i32>, ptr %x2932 %red = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> %v)2933 ret i32 %red2934}2935 2936define i32 @vreduce_xor_v8i32(ptr %x) {2937; CHECK-LABEL: vreduce_xor_v8i32:2938; CHECK: # %bb.0:2939; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma2940; CHECK-NEXT: vle32.v v8, (a0)2941; CHECK-NEXT: vmv.s.x v10, zero2942; CHECK-NEXT: vredxor.vs v8, v8, v102943; CHECK-NEXT: vmv.x.s a0, v82944; CHECK-NEXT: ret2945 %v = load <8 x i32>, ptr %x2946 %red = call i32 @llvm.vector.reduce.xor.v8i32(<8 x i32> %v)2947 ret i32 %red2948}2949 2950define i32 @vreduce_xor_v16i32(ptr %x) {2951; CHECK-LABEL: vreduce_xor_v16i32:2952; CHECK: # %bb.0:2953; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma2954; CHECK-NEXT: vle32.v v8, (a0)2955; CHECK-NEXT: vmv.s.x v12, zero2956; CHECK-NEXT: vredxor.vs v8, v8, v122957; CHECK-NEXT: vmv.x.s a0, v82958; CHECK-NEXT: ret2959 %v = load <16 x i32>, ptr %x2960 %red = call i32 @llvm.vector.reduce.xor.v16i32(<16 x i32> %v)2961 ret i32 %red2962}2963 2964define i32 @vreduce_xor_v32i32(ptr %x) {2965; CHECK-LABEL: vreduce_xor_v32i32:2966; CHECK: # %bb.0:2967; CHECK-NEXT: li a1, 322968; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma2969; CHECK-NEXT: vle32.v v8, (a0)2970; CHECK-NEXT: vmv.s.x v16, zero2971; CHECK-NEXT: vredxor.vs v8, v8, v162972; CHECK-NEXT: vmv.x.s a0, v82973; CHECK-NEXT: ret2974 %v = load <32 x i32>, ptr %x2975 %red = call i32 @llvm.vector.reduce.xor.v32i32(<32 x i32> %v)2976 ret i32 %red2977}2978 2979define i32 @vreduce_xor_v64i32(ptr %x) {2980; CHECK-LABEL: vreduce_xor_v64i32:2981; CHECK: # %bb.0:2982; CHECK-NEXT: li a1, 322983; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma2984; CHECK-NEXT: vle32.v v8, (a0)2985; CHECK-NEXT: addi a0, a0, 1282986; CHECK-NEXT: vle32.v v16, (a0)2987; CHECK-NEXT: vxor.vv v8, v8, v162988; CHECK-NEXT: vmv.s.x v16, zero2989; CHECK-NEXT: vredxor.vs v8, v8, v162990; CHECK-NEXT: vmv.x.s a0, v82991; CHECK-NEXT: ret2992 %v = load <64 x i32>, ptr %x2993 %red = call i32 @llvm.vector.reduce.xor.v64i32(<64 x i32> %v)2994 ret i32 %red2995}2996 2997define i64 @vreduce_xor_v1i64(<1 x i64> %v) {2998; RV32-LABEL: vreduce_xor_v1i64:2999; RV32: # %bb.0:3000; RV32-NEXT: li a0, 323001; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma3002; RV32-NEXT: vsrl.vx v9, v8, a03003; RV32-NEXT: vmv.x.s a1, v93004; RV32-NEXT: vmv.x.s a0, v83005; RV32-NEXT: ret3006;3007; RV64-LABEL: vreduce_xor_v1i64:3008; RV64: # %bb.0:3009; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma3010; RV64-NEXT: vmv.x.s a0, v83011; RV64-NEXT: ret3012 %red = call i64 @llvm.vector.reduce.xor.v1i64(<1 x i64> %v)3013 ret i64 %red3014}3015 3016define i64 @vreduce_xor_v2i64(ptr %x) {3017; RV32-LABEL: vreduce_xor_v2i64:3018; RV32: # %bb.0:3019; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma3020; RV32-NEXT: vle64.v v8, (a0)3021; RV32-NEXT: vmv.s.x v9, zero3022; RV32-NEXT: li a1, 323023; RV32-NEXT: vredxor.vs v8, v8, v93024; RV32-NEXT: vmv.x.s a0, v83025; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma3026; RV32-NEXT: vsrl.vx v8, v8, a13027; RV32-NEXT: vmv.x.s a1, v83028; RV32-NEXT: ret3029;3030; RV64-LABEL: vreduce_xor_v2i64:3031; RV64: # %bb.0:3032; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma3033; RV64-NEXT: vle64.v v8, (a0)3034; RV64-NEXT: vmv.s.x v9, zero3035; RV64-NEXT: vredxor.vs v8, v8, v93036; RV64-NEXT: vmv.x.s a0, v83037; RV64-NEXT: ret3038 %v = load <2 x i64>, ptr %x3039 %red = call i64 @llvm.vector.reduce.xor.v2i64(<2 x i64> %v)3040 ret i64 %red3041}3042 3043define i64 @vreduce_xor_v4i64(ptr %x) {3044; RV32-LABEL: vreduce_xor_v4i64:3045; RV32: # %bb.0:3046; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma3047; RV32-NEXT: vle64.v v8, (a0)3048; RV32-NEXT: vmv.s.x v10, zero3049; RV32-NEXT: li a1, 323050; RV32-NEXT: vredxor.vs v8, v8, v103051; RV32-NEXT: vmv.x.s a0, v83052; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma3053; RV32-NEXT: vsrl.vx v8, v8, a13054; RV32-NEXT: vmv.x.s a1, v83055; RV32-NEXT: ret3056;3057; RV64-LABEL: vreduce_xor_v4i64:3058; RV64: # %bb.0:3059; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma3060; RV64-NEXT: vle64.v v8, (a0)3061; RV64-NEXT: vmv.s.x v10, zero3062; RV64-NEXT: vredxor.vs v8, v8, v103063; RV64-NEXT: vmv.x.s a0, v83064; RV64-NEXT: ret3065 %v = load <4 x i64>, ptr %x3066 %red = call i64 @llvm.vector.reduce.xor.v4i64(<4 x i64> %v)3067 ret i64 %red3068}3069 3070define i64 @vreduce_xor_v8i64(ptr %x) {3071; RV32-LABEL: vreduce_xor_v8i64:3072; RV32: # %bb.0:3073; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma3074; RV32-NEXT: vle64.v v8, (a0)3075; RV32-NEXT: vmv.s.x v12, zero3076; RV32-NEXT: li a1, 323077; RV32-NEXT: vredxor.vs v8, v8, v123078; RV32-NEXT: vmv.x.s a0, v83079; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma3080; RV32-NEXT: vsrl.vx v8, v8, a13081; RV32-NEXT: vmv.x.s a1, v83082; RV32-NEXT: ret3083;3084; RV64-LABEL: vreduce_xor_v8i64:3085; RV64: # %bb.0:3086; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma3087; RV64-NEXT: vle64.v v8, (a0)3088; RV64-NEXT: vmv.s.x v12, zero3089; RV64-NEXT: vredxor.vs v8, v8, v123090; RV64-NEXT: vmv.x.s a0, v83091; RV64-NEXT: ret3092 %v = load <8 x i64>, ptr %x3093 %red = call i64 @llvm.vector.reduce.xor.v8i64(<8 x i64> %v)3094 ret i64 %red3095}3096 3097define i64 @vreduce_xor_v16i64(ptr %x) {3098; RV32-LABEL: vreduce_xor_v16i64:3099; RV32: # %bb.0:3100; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma3101; RV32-NEXT: vle64.v v8, (a0)3102; RV32-NEXT: vmv.s.x v16, zero3103; RV32-NEXT: li a1, 323104; RV32-NEXT: vredxor.vs v8, v8, v163105; RV32-NEXT: vmv.x.s a0, v83106; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma3107; RV32-NEXT: vsrl.vx v8, v8, a13108; RV32-NEXT: vmv.x.s a1, v83109; RV32-NEXT: ret3110;3111; RV64-LABEL: vreduce_xor_v16i64:3112; RV64: # %bb.0:3113; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma3114; RV64-NEXT: vle64.v v8, (a0)3115; RV64-NEXT: vmv.s.x v16, zero3116; RV64-NEXT: vredxor.vs v8, v8, v163117; RV64-NEXT: vmv.x.s a0, v83118; RV64-NEXT: ret3119 %v = load <16 x i64>, ptr %x3120 %red = call i64 @llvm.vector.reduce.xor.v16i64(<16 x i64> %v)3121 ret i64 %red3122}3123 3124define i64 @vreduce_xor_v32i64(ptr %x) {3125; RV32-LABEL: vreduce_xor_v32i64:3126; RV32: # %bb.0:3127; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma3128; RV32-NEXT: vle64.v v8, (a0)3129; RV32-NEXT: addi a0, a0, 1283130; RV32-NEXT: vle64.v v16, (a0)3131; RV32-NEXT: vxor.vv v8, v8, v163132; RV32-NEXT: vmv.s.x v16, zero3133; RV32-NEXT: li a1, 323134; RV32-NEXT: vredxor.vs v8, v8, v163135; RV32-NEXT: vmv.x.s a0, v83136; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma3137; RV32-NEXT: vsrl.vx v8, v8, a13138; RV32-NEXT: vmv.x.s a1, v83139; RV32-NEXT: ret3140;3141; RV64-LABEL: vreduce_xor_v32i64:3142; RV64: # %bb.0:3143; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma3144; RV64-NEXT: vle64.v v8, (a0)3145; RV64-NEXT: addi a0, a0, 1283146; RV64-NEXT: vle64.v v16, (a0)3147; RV64-NEXT: vxor.vv v8, v8, v163148; RV64-NEXT: vmv.s.x v16, zero3149; RV64-NEXT: vredxor.vs v8, v8, v163150; RV64-NEXT: vmv.x.s a0, v83151; RV64-NEXT: ret3152 %v = load <32 x i64>, ptr %x3153 %red = call i64 @llvm.vector.reduce.xor.v32i64(<32 x i64> %v)3154 ret i64 %red3155}3156 3157define i64 @vreduce_xor_v64i64(ptr %x) nounwind {3158; RV32-LABEL: vreduce_xor_v64i64:3159; RV32: # %bb.0:3160; RV32-NEXT: addi a1, a0, 3843161; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma3162; RV32-NEXT: vle64.v v24, (a1)3163; RV32-NEXT: addi a1, a0, 1283164; RV32-NEXT: vle64.v v0, (a1)3165; RV32-NEXT: vle64.v v8, (a0)3166; RV32-NEXT: addi a0, a0, 2563167; RV32-NEXT: vle64.v v16, (a0)3168; RV32-NEXT: vxor.vv v24, v0, v243169; RV32-NEXT: vmv.s.x v7, zero3170; RV32-NEXT: li a1, 323171; RV32-NEXT: vxor.vv v8, v8, v163172; RV32-NEXT: vxor.vv v8, v8, v243173; RV32-NEXT: vredxor.vs v8, v8, v73174; RV32-NEXT: vmv.x.s a0, v83175; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma3176; RV32-NEXT: vsrl.vx v8, v8, a13177; RV32-NEXT: vmv.x.s a1, v83178; RV32-NEXT: ret3179;3180; RV64-LABEL: vreduce_xor_v64i64:3181; RV64: # %bb.0:3182; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma3183; RV64-NEXT: vle64.v v8, (a0)3184; RV64-NEXT: addi a1, a0, 3843185; RV64-NEXT: vle64.v v16, (a1)3186; RV64-NEXT: addi a1, a0, 2563187; RV64-NEXT: addi a0, a0, 1283188; RV64-NEXT: vle64.v v24, (a0)3189; RV64-NEXT: vle64.v v0, (a1)3190; RV64-NEXT: vxor.vv v16, v24, v163191; RV64-NEXT: vxor.vv v8, v8, v03192; RV64-NEXT: vxor.vv v8, v8, v163193; RV64-NEXT: vmv.s.x v16, zero3194; RV64-NEXT: vredxor.vs v8, v8, v163195; RV64-NEXT: vmv.x.s a0, v83196; RV64-NEXT: ret3197 %v = load <64 x i64>, ptr %x3198 %red = call i64 @llvm.vector.reduce.xor.v64i64(<64 x i64> %v)3199 ret i64 %red3200}3201 3202define i8 @vreduce_smin_v1i8(<1 x i8> %v) {3203; CHECK-LABEL: vreduce_smin_v1i8:3204; CHECK: # %bb.0:3205; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma3206; CHECK-NEXT: vmv.x.s a0, v83207; CHECK-NEXT: ret3208 %red = call i8 @llvm.vector.reduce.smin.v1i8(<1 x i8> %v)3209 ret i8 %red3210}3211 3212define i8 @vreduce_smin_v2i8(ptr %x) {3213; CHECK-LABEL: vreduce_smin_v2i8:3214; CHECK: # %bb.0:3215; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma3216; CHECK-NEXT: vle8.v v8, (a0)3217; CHECK-NEXT: vredmin.vs v8, v8, v83218; CHECK-NEXT: vmv.x.s a0, v83219; CHECK-NEXT: ret3220 %v = load <2 x i8>, ptr %x3221 %red = call i8 @llvm.vector.reduce.smin.v2i8(<2 x i8> %v)3222 ret i8 %red3223}3224 3225define i8 @vreduce_smin_v3i8(ptr %x) {3226; CHECK-LABEL: vreduce_smin_v3i8:3227; CHECK: # %bb.0:3228; CHECK-NEXT: vsetivli zero, 3, e8, mf4, ta, ma3229; CHECK-NEXT: vle8.v v8, (a0)3230; CHECK-NEXT: li a0, 1273231; CHECK-NEXT: vmv.s.x v9, a03232; CHECK-NEXT: vredmin.vs v8, v8, v93233; CHECK-NEXT: vmv.x.s a0, v83234; CHECK-NEXT: ret3235 %v = load <3 x i8>, ptr %x3236 %red = call i8 @llvm.vector.reduce.smin.v3i8(<3 x i8> %v)3237 ret i8 %red3238}3239 3240define i8 @vreduce_smin_v4i8(ptr %x) {3241; CHECK-LABEL: vreduce_smin_v4i8:3242; CHECK: # %bb.0:3243; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma3244; CHECK-NEXT: vle8.v v8, (a0)3245; CHECK-NEXT: vredmin.vs v8, v8, v83246; CHECK-NEXT: vmv.x.s a0, v83247; CHECK-NEXT: ret3248 %v = load <4 x i8>, ptr %x3249 %red = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> %v)3250 ret i8 %red3251}3252 3253define i8 @vreduce_smin_v8i8(ptr %x) {3254; CHECK-LABEL: vreduce_smin_v8i8:3255; CHECK: # %bb.0:3256; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma3257; CHECK-NEXT: vle8.v v8, (a0)3258; CHECK-NEXT: vredmin.vs v8, v8, v83259; CHECK-NEXT: vmv.x.s a0, v83260; CHECK-NEXT: ret3261 %v = load <8 x i8>, ptr %x3262 %red = call i8 @llvm.vector.reduce.smin.v8i8(<8 x i8> %v)3263 ret i8 %red3264}3265 3266define i8 @vreduce_smin_v16i8(ptr %x) {3267; CHECK-LABEL: vreduce_smin_v16i8:3268; CHECK: # %bb.0:3269; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma3270; CHECK-NEXT: vle8.v v8, (a0)3271; CHECK-NEXT: vredmin.vs v8, v8, v83272; CHECK-NEXT: vmv.x.s a0, v83273; CHECK-NEXT: ret3274 %v = load <16 x i8>, ptr %x3275 %red = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> %v)3276 ret i8 %red3277}3278 3279define i8 @vreduce_smin_v32i8(ptr %x) {3280; CHECK-LABEL: vreduce_smin_v32i8:3281; CHECK: # %bb.0:3282; CHECK-NEXT: li a1, 323283; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma3284; CHECK-NEXT: vle8.v v8, (a0)3285; CHECK-NEXT: vredmin.vs v8, v8, v83286; CHECK-NEXT: vmv.x.s a0, v83287; CHECK-NEXT: ret3288 %v = load <32 x i8>, ptr %x3289 %red = call i8 @llvm.vector.reduce.smin.v32i8(<32 x i8> %v)3290 ret i8 %red3291}3292 3293define i8 @vreduce_smin_v64i8(ptr %x) {3294; CHECK-LABEL: vreduce_smin_v64i8:3295; CHECK: # %bb.0:3296; CHECK-NEXT: li a1, 643297; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma3298; CHECK-NEXT: vle8.v v8, (a0)3299; CHECK-NEXT: vredmin.vs v8, v8, v83300; CHECK-NEXT: vmv.x.s a0, v83301; CHECK-NEXT: ret3302 %v = load <64 x i8>, ptr %x3303 %red = call i8 @llvm.vector.reduce.smin.v64i8(<64 x i8> %v)3304 ret i8 %red3305}3306 3307define i8 @vreduce_smin_v128i8(ptr %x) {3308; CHECK-LABEL: vreduce_smin_v128i8:3309; CHECK: # %bb.0:3310; CHECK-NEXT: li a1, 1283311; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma3312; CHECK-NEXT: vle8.v v8, (a0)3313; CHECK-NEXT: vredmin.vs v8, v8, v83314; CHECK-NEXT: vmv.x.s a0, v83315; CHECK-NEXT: ret3316 %v = load <128 x i8>, ptr %x3317 %red = call i8 @llvm.vector.reduce.smin.v128i8(<128 x i8> %v)3318 ret i8 %red3319}3320 3321define i8 @vreduce_smin_v256i8(ptr %x) {3322; CHECK-LABEL: vreduce_smin_v256i8:3323; CHECK: # %bb.0:3324; CHECK-NEXT: li a1, 1283325; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma3326; CHECK-NEXT: vle8.v v8, (a0)3327; CHECK-NEXT: addi a0, a0, 1283328; CHECK-NEXT: vle8.v v16, (a0)3329; CHECK-NEXT: vmin.vv v8, v8, v163330; CHECK-NEXT: vredmin.vs v8, v8, v83331; CHECK-NEXT: vmv.x.s a0, v83332; CHECK-NEXT: ret3333 %v = load <256 x i8>, ptr %x3334 %red = call i8 @llvm.vector.reduce.smin.v256i8(<256 x i8> %v)3335 ret i8 %red3336}3337 3338define i16 @vreduce_smin_v1i16(<1 x i16> %v) {3339; CHECK-LABEL: vreduce_smin_v1i16:3340; CHECK: # %bb.0:3341; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma3342; CHECK-NEXT: vmv.x.s a0, v83343; CHECK-NEXT: ret3344 %red = call i16 @llvm.vector.reduce.smin.v1i16(<1 x i16> %v)3345 ret i16 %red3346}3347 3348define i16 @vreduce_smin_v2i16(ptr %x) {3349; CHECK-LABEL: vreduce_smin_v2i16:3350; CHECK: # %bb.0:3351; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma3352; CHECK-NEXT: vle16.v v8, (a0)3353; CHECK-NEXT: vredmin.vs v8, v8, v83354; CHECK-NEXT: vmv.x.s a0, v83355; CHECK-NEXT: ret3356 %v = load <2 x i16>, ptr %x3357 %red = call i16 @llvm.vector.reduce.smin.v2i16(<2 x i16> %v)3358 ret i16 %red3359}3360 3361define i16 @vreduce_smin_v4i16(ptr %x) {3362; CHECK-LABEL: vreduce_smin_v4i16:3363; CHECK: # %bb.0:3364; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma3365; CHECK-NEXT: vle16.v v8, (a0)3366; CHECK-NEXT: vredmin.vs v8, v8, v83367; CHECK-NEXT: vmv.x.s a0, v83368; CHECK-NEXT: ret3369 %v = load <4 x i16>, ptr %x3370 %red = call i16 @llvm.vector.reduce.smin.v4i16(<4 x i16> %v)3371 ret i16 %red3372}3373 3374define i16 @vreduce_smin_v8i16(ptr %x) {3375; CHECK-LABEL: vreduce_smin_v8i16:3376; CHECK: # %bb.0:3377; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma3378; CHECK-NEXT: vle16.v v8, (a0)3379; CHECK-NEXT: vredmin.vs v8, v8, v83380; CHECK-NEXT: vmv.x.s a0, v83381; CHECK-NEXT: ret3382 %v = load <8 x i16>, ptr %x3383 %red = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> %v)3384 ret i16 %red3385}3386 3387define i16 @vreduce_smin_v16i16(ptr %x) {3388; CHECK-LABEL: vreduce_smin_v16i16:3389; CHECK: # %bb.0:3390; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma3391; CHECK-NEXT: vle16.v v8, (a0)3392; CHECK-NEXT: vredmin.vs v8, v8, v83393; CHECK-NEXT: vmv.x.s a0, v83394; CHECK-NEXT: ret3395 %v = load <16 x i16>, ptr %x3396 %red = call i16 @llvm.vector.reduce.smin.v16i16(<16 x i16> %v)3397 ret i16 %red3398}3399 3400define i16 @vreduce_smin_v32i16(ptr %x) {3401; CHECK-LABEL: vreduce_smin_v32i16:3402; CHECK: # %bb.0:3403; CHECK-NEXT: li a1, 323404; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma3405; CHECK-NEXT: vle16.v v8, (a0)3406; CHECK-NEXT: vredmin.vs v8, v8, v83407; CHECK-NEXT: vmv.x.s a0, v83408; CHECK-NEXT: ret3409 %v = load <32 x i16>, ptr %x3410 %red = call i16 @llvm.vector.reduce.smin.v32i16(<32 x i16> %v)3411 ret i16 %red3412}3413 3414define i16 @vreduce_smin_v64i16(ptr %x) {3415; CHECK-LABEL: vreduce_smin_v64i16:3416; CHECK: # %bb.0:3417; CHECK-NEXT: li a1, 643418; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma3419; CHECK-NEXT: vle16.v v8, (a0)3420; CHECK-NEXT: vredmin.vs v8, v8, v83421; CHECK-NEXT: vmv.x.s a0, v83422; CHECK-NEXT: ret3423 %v = load <64 x i16>, ptr %x3424 %red = call i16 @llvm.vector.reduce.smin.v64i16(<64 x i16> %v)3425 ret i16 %red3426}3427 3428define i16 @vreduce_smin_v128i16(ptr %x) {3429; CHECK-LABEL: vreduce_smin_v128i16:3430; CHECK: # %bb.0:3431; CHECK-NEXT: li a1, 643432; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma3433; CHECK-NEXT: vle16.v v8, (a0)3434; CHECK-NEXT: addi a0, a0, 1283435; CHECK-NEXT: vle16.v v16, (a0)3436; CHECK-NEXT: vmin.vv v8, v8, v163437; CHECK-NEXT: vredmin.vs v8, v8, v83438; CHECK-NEXT: vmv.x.s a0, v83439; CHECK-NEXT: ret3440 %v = load <128 x i16>, ptr %x3441 %red = call i16 @llvm.vector.reduce.smin.v128i16(<128 x i16> %v)3442 ret i16 %red3443}3444 3445define i32 @vreduce_smin_v1i32(<1 x i32> %v) {3446; CHECK-LABEL: vreduce_smin_v1i32:3447; CHECK: # %bb.0:3448; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma3449; CHECK-NEXT: vmv.x.s a0, v83450; CHECK-NEXT: ret3451 %red = call i32 @llvm.vector.reduce.smin.v1i32(<1 x i32> %v)3452 ret i32 %red3453}3454 3455define i32 @vreduce_smin_v2i32(ptr %x) {3456; CHECK-LABEL: vreduce_smin_v2i32:3457; CHECK: # %bb.0:3458; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma3459; CHECK-NEXT: vle32.v v8, (a0)3460; CHECK-NEXT: vredmin.vs v8, v8, v83461; CHECK-NEXT: vmv.x.s a0, v83462; CHECK-NEXT: ret3463 %v = load <2 x i32>, ptr %x3464 %red = call i32 @llvm.vector.reduce.smin.v2i32(<2 x i32> %v)3465 ret i32 %red3466}3467 3468define i32 @vreduce_smin_v4i32(ptr %x) {3469; CHECK-LABEL: vreduce_smin_v4i32:3470; CHECK: # %bb.0:3471; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma3472; CHECK-NEXT: vle32.v v8, (a0)3473; CHECK-NEXT: vredmin.vs v8, v8, v83474; CHECK-NEXT: vmv.x.s a0, v83475; CHECK-NEXT: ret3476 %v = load <4 x i32>, ptr %x3477 %red = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> %v)3478 ret i32 %red3479}3480 3481define i32 @vreduce_smin_v8i32(ptr %x) {3482; CHECK-LABEL: vreduce_smin_v8i32:3483; CHECK: # %bb.0:3484; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma3485; CHECK-NEXT: vle32.v v8, (a0)3486; CHECK-NEXT: vredmin.vs v8, v8, v83487; CHECK-NEXT: vmv.x.s a0, v83488; CHECK-NEXT: ret3489 %v = load <8 x i32>, ptr %x3490 %red = call i32 @llvm.vector.reduce.smin.v8i32(<8 x i32> %v)3491 ret i32 %red3492}3493 3494define i32 @vreduce_smin_v16i32(ptr %x) {3495; CHECK-LABEL: vreduce_smin_v16i32:3496; CHECK: # %bb.0:3497; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma3498; CHECK-NEXT: vle32.v v8, (a0)3499; CHECK-NEXT: vredmin.vs v8, v8, v83500; CHECK-NEXT: vmv.x.s a0, v83501; CHECK-NEXT: ret3502 %v = load <16 x i32>, ptr %x3503 %red = call i32 @llvm.vector.reduce.smin.v16i32(<16 x i32> %v)3504 ret i32 %red3505}3506 3507define i32 @vreduce_smin_v32i32(ptr %x) {3508; CHECK-LABEL: vreduce_smin_v32i32:3509; CHECK: # %bb.0:3510; CHECK-NEXT: li a1, 323511; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma3512; CHECK-NEXT: vle32.v v8, (a0)3513; CHECK-NEXT: vredmin.vs v8, v8, v83514; CHECK-NEXT: vmv.x.s a0, v83515; CHECK-NEXT: ret3516 %v = load <32 x i32>, ptr %x3517 %red = call i32 @llvm.vector.reduce.smin.v32i32(<32 x i32> %v)3518 ret i32 %red3519}3520 3521define i32 @vreduce_smin_v64i32(ptr %x) {3522; CHECK-LABEL: vreduce_smin_v64i32:3523; CHECK: # %bb.0:3524; CHECK-NEXT: li a1, 323525; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma3526; CHECK-NEXT: vle32.v v8, (a0)3527; CHECK-NEXT: addi a0, a0, 1283528; CHECK-NEXT: vle32.v v16, (a0)3529; CHECK-NEXT: vmin.vv v8, v8, v163530; CHECK-NEXT: vredmin.vs v8, v8, v83531; CHECK-NEXT: vmv.x.s a0, v83532; CHECK-NEXT: ret3533 %v = load <64 x i32>, ptr %x3534 %red = call i32 @llvm.vector.reduce.smin.v64i32(<64 x i32> %v)3535 ret i32 %red3536}3537 3538define i64 @vreduce_smin_v1i64(<1 x i64> %v) {3539; RV32-LABEL: vreduce_smin_v1i64:3540; RV32: # %bb.0:3541; RV32-NEXT: li a0, 323542; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma3543; RV32-NEXT: vsrl.vx v9, v8, a03544; RV32-NEXT: vmv.x.s a1, v93545; RV32-NEXT: vmv.x.s a0, v83546; RV32-NEXT: ret3547;3548; RV64-LABEL: vreduce_smin_v1i64:3549; RV64: # %bb.0:3550; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma3551; RV64-NEXT: vmv.x.s a0, v83552; RV64-NEXT: ret3553 %red = call i64 @llvm.vector.reduce.smin.v1i64(<1 x i64> %v)3554 ret i64 %red3555}3556 3557define i64 @vreduce_smin_v2i64(ptr %x) {3558; RV32-LABEL: vreduce_smin_v2i64:3559; RV32: # %bb.0:3560; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma3561; RV32-NEXT: vle64.v v8, (a0)3562; RV32-NEXT: li a0, 323563; RV32-NEXT: vredmin.vs v8, v8, v83564; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma3565; RV32-NEXT: vsrl.vx v9, v8, a03566; RV32-NEXT: vmv.x.s a1, v93567; RV32-NEXT: vmv.x.s a0, v83568; RV32-NEXT: ret3569;3570; RV64-LABEL: vreduce_smin_v2i64:3571; RV64: # %bb.0:3572; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma3573; RV64-NEXT: vle64.v v8, (a0)3574; RV64-NEXT: vredmin.vs v8, v8, v83575; RV64-NEXT: vmv.x.s a0, v83576; RV64-NEXT: ret3577 %v = load <2 x i64>, ptr %x3578 %red = call i64 @llvm.vector.reduce.smin.v2i64(<2 x i64> %v)3579 ret i64 %red3580}3581 3582define i64 @vreduce_smin_v4i64(ptr %x) {3583; RV32-LABEL: vreduce_smin_v4i64:3584; RV32: # %bb.0:3585; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma3586; RV32-NEXT: vle64.v v8, (a0)3587; RV32-NEXT: li a1, 323588; RV32-NEXT: vredmin.vs v8, v8, v83589; RV32-NEXT: vmv.x.s a0, v83590; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma3591; RV32-NEXT: vsrl.vx v8, v8, a13592; RV32-NEXT: vmv.x.s a1, v83593; RV32-NEXT: ret3594;3595; RV64-LABEL: vreduce_smin_v4i64:3596; RV64: # %bb.0:3597; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma3598; RV64-NEXT: vle64.v v8, (a0)3599; RV64-NEXT: vredmin.vs v8, v8, v83600; RV64-NEXT: vmv.x.s a0, v83601; RV64-NEXT: ret3602 %v = load <4 x i64>, ptr %x3603 %red = call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> %v)3604 ret i64 %red3605}3606 3607define i64 @vreduce_smin_v8i64(ptr %x) {3608; RV32-LABEL: vreduce_smin_v8i64:3609; RV32: # %bb.0:3610; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma3611; RV32-NEXT: vle64.v v8, (a0)3612; RV32-NEXT: li a1, 323613; RV32-NEXT: vredmin.vs v8, v8, v83614; RV32-NEXT: vmv.x.s a0, v83615; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma3616; RV32-NEXT: vsrl.vx v8, v8, a13617; RV32-NEXT: vmv.x.s a1, v83618; RV32-NEXT: ret3619;3620; RV64-LABEL: vreduce_smin_v8i64:3621; RV64: # %bb.0:3622; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma3623; RV64-NEXT: vle64.v v8, (a0)3624; RV64-NEXT: vredmin.vs v8, v8, v83625; RV64-NEXT: vmv.x.s a0, v83626; RV64-NEXT: ret3627 %v = load <8 x i64>, ptr %x3628 %red = call i64 @llvm.vector.reduce.smin.v8i64(<8 x i64> %v)3629 ret i64 %red3630}3631 3632define i64 @vreduce_smin_v16i64(ptr %x) {3633; RV32-LABEL: vreduce_smin_v16i64:3634; RV32: # %bb.0:3635; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma3636; RV32-NEXT: vle64.v v8, (a0)3637; RV32-NEXT: li a1, 323638; RV32-NEXT: vredmin.vs v8, v8, v83639; RV32-NEXT: vmv.x.s a0, v83640; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma3641; RV32-NEXT: vsrl.vx v8, v8, a13642; RV32-NEXT: vmv.x.s a1, v83643; RV32-NEXT: ret3644;3645; RV64-LABEL: vreduce_smin_v16i64:3646; RV64: # %bb.0:3647; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma3648; RV64-NEXT: vle64.v v8, (a0)3649; RV64-NEXT: vredmin.vs v8, v8, v83650; RV64-NEXT: vmv.x.s a0, v83651; RV64-NEXT: ret3652 %v = load <16 x i64>, ptr %x3653 %red = call i64 @llvm.vector.reduce.smin.v16i64(<16 x i64> %v)3654 ret i64 %red3655}3656 3657define i64 @vreduce_smin_v32i64(ptr %x) {3658; RV32-LABEL: vreduce_smin_v32i64:3659; RV32: # %bb.0:3660; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma3661; RV32-NEXT: vle64.v v8, (a0)3662; RV32-NEXT: addi a0, a0, 1283663; RV32-NEXT: vle64.v v16, (a0)3664; RV32-NEXT: li a1, 323665; RV32-NEXT: vmin.vv v8, v8, v163666; RV32-NEXT: vredmin.vs v8, v8, v83667; RV32-NEXT: vmv.x.s a0, v83668; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma3669; RV32-NEXT: vsrl.vx v8, v8, a13670; RV32-NEXT: vmv.x.s a1, v83671; RV32-NEXT: ret3672;3673; RV64-LABEL: vreduce_smin_v32i64:3674; RV64: # %bb.0:3675; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma3676; RV64-NEXT: vle64.v v8, (a0)3677; RV64-NEXT: addi a0, a0, 1283678; RV64-NEXT: vle64.v v16, (a0)3679; RV64-NEXT: vmin.vv v8, v8, v163680; RV64-NEXT: vredmin.vs v8, v8, v83681; RV64-NEXT: vmv.x.s a0, v83682; RV64-NEXT: ret3683 %v = load <32 x i64>, ptr %x3684 %red = call i64 @llvm.vector.reduce.smin.v32i64(<32 x i64> %v)3685 ret i64 %red3686}3687 3688define i64 @vreduce_smin_v64i64(ptr %x) nounwind {3689; RV32-LABEL: vreduce_smin_v64i64:3690; RV32: # %bb.0:3691; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma3692; RV32-NEXT: vle64.v v8, (a0)3693; RV32-NEXT: addi a1, a0, 3843694; RV32-NEXT: vle64.v v16, (a1)3695; RV32-NEXT: addi a1, a0, 2563696; RV32-NEXT: addi a0, a0, 1283697; RV32-NEXT: vle64.v v0, (a0)3698; RV32-NEXT: vle64.v v24, (a1)3699; RV32-NEXT: li a1, 323700; RV32-NEXT: vmin.vv v16, v0, v163701; RV32-NEXT: vmin.vv v8, v8, v243702; RV32-NEXT: vmin.vv v8, v8, v163703; RV32-NEXT: vredmin.vs v8, v8, v83704; RV32-NEXT: vmv.x.s a0, v83705; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma3706; RV32-NEXT: vsrl.vx v8, v8, a13707; RV32-NEXT: vmv.x.s a1, v83708; RV32-NEXT: ret3709;3710; RV64-LABEL: vreduce_smin_v64i64:3711; RV64: # %bb.0:3712; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma3713; RV64-NEXT: vle64.v v8, (a0)3714; RV64-NEXT: addi a1, a0, 3843715; RV64-NEXT: vle64.v v16, (a1)3716; RV64-NEXT: addi a1, a0, 2563717; RV64-NEXT: addi a0, a0, 1283718; RV64-NEXT: vle64.v v24, (a0)3719; RV64-NEXT: vle64.v v0, (a1)3720; RV64-NEXT: vmin.vv v16, v24, v163721; RV64-NEXT: vmin.vv v8, v8, v03722; RV64-NEXT: vmin.vv v8, v8, v163723; RV64-NEXT: vredmin.vs v8, v8, v83724; RV64-NEXT: vmv.x.s a0, v83725; RV64-NEXT: ret3726 %v = load <64 x i64>, ptr %x3727 %red = call i64 @llvm.vector.reduce.smin.v64i64(<64 x i64> %v)3728 ret i64 %red3729}3730 3731define i8 @vreduce_smax_v1i8(<1 x i8> %v) {3732; CHECK-LABEL: vreduce_smax_v1i8:3733; CHECK: # %bb.0:3734; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma3735; CHECK-NEXT: vmv.x.s a0, v83736; CHECK-NEXT: ret3737 %red = call i8 @llvm.vector.reduce.smax.v1i8(<1 x i8> %v)3738 ret i8 %red3739}3740 3741define i8 @vreduce_smax_v2i8(ptr %x) {3742; CHECK-LABEL: vreduce_smax_v2i8:3743; CHECK: # %bb.0:3744; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma3745; CHECK-NEXT: vle8.v v8, (a0)3746; CHECK-NEXT: vredmax.vs v8, v8, v83747; CHECK-NEXT: vmv.x.s a0, v83748; CHECK-NEXT: ret3749 %v = load <2 x i8>, ptr %x3750 %red = call i8 @llvm.vector.reduce.smax.v2i8(<2 x i8> %v)3751 ret i8 %red3752}3753 3754define i8 @vreduce_smax_v3i8(ptr %x) {3755; CHECK-LABEL: vreduce_smax_v3i8:3756; CHECK: # %bb.0:3757; CHECK-NEXT: vsetivli zero, 3, e8, mf4, ta, ma3758; CHECK-NEXT: vle8.v v8, (a0)3759; CHECK-NEXT: li a0, -1283760; CHECK-NEXT: vmv.s.x v9, a03761; CHECK-NEXT: vredmax.vs v8, v8, v93762; CHECK-NEXT: vmv.x.s a0, v83763; CHECK-NEXT: ret3764 %v = load <3 x i8>, ptr %x3765 %red = call i8 @llvm.vector.reduce.smax.v3i8(<3 x i8> %v)3766 ret i8 %red3767}3768 3769define i8 @vreduce_smax_v4i8(ptr %x) {3770; CHECK-LABEL: vreduce_smax_v4i8:3771; CHECK: # %bb.0:3772; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma3773; CHECK-NEXT: vle8.v v8, (a0)3774; CHECK-NEXT: vredmax.vs v8, v8, v83775; CHECK-NEXT: vmv.x.s a0, v83776; CHECK-NEXT: ret3777 %v = load <4 x i8>, ptr %x3778 %red = call i8 @llvm.vector.reduce.smax.v4i8(<4 x i8> %v)3779 ret i8 %red3780}3781 3782define i8 @vreduce_smax_v8i8(ptr %x) {3783; CHECK-LABEL: vreduce_smax_v8i8:3784; CHECK: # %bb.0:3785; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma3786; CHECK-NEXT: vle8.v v8, (a0)3787; CHECK-NEXT: vredmax.vs v8, v8, v83788; CHECK-NEXT: vmv.x.s a0, v83789; CHECK-NEXT: ret3790 %v = load <8 x i8>, ptr %x3791 %red = call i8 @llvm.vector.reduce.smax.v8i8(<8 x i8> %v)3792 ret i8 %red3793}3794 3795define i8 @vreduce_smax_v16i8(ptr %x) {3796; CHECK-LABEL: vreduce_smax_v16i8:3797; CHECK: # %bb.0:3798; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma3799; CHECK-NEXT: vle8.v v8, (a0)3800; CHECK-NEXT: vredmax.vs v8, v8, v83801; CHECK-NEXT: vmv.x.s a0, v83802; CHECK-NEXT: ret3803 %v = load <16 x i8>, ptr %x3804 %red = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> %v)3805 ret i8 %red3806}3807 3808define i8 @vreduce_smax_v32i8(ptr %x) {3809; CHECK-LABEL: vreduce_smax_v32i8:3810; CHECK: # %bb.0:3811; CHECK-NEXT: li a1, 323812; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma3813; CHECK-NEXT: vle8.v v8, (a0)3814; CHECK-NEXT: vredmax.vs v8, v8, v83815; CHECK-NEXT: vmv.x.s a0, v83816; CHECK-NEXT: ret3817 %v = load <32 x i8>, ptr %x3818 %red = call i8 @llvm.vector.reduce.smax.v32i8(<32 x i8> %v)3819 ret i8 %red3820}3821 3822define i8 @vreduce_smax_v64i8(ptr %x) {3823; CHECK-LABEL: vreduce_smax_v64i8:3824; CHECK: # %bb.0:3825; CHECK-NEXT: li a1, 643826; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma3827; CHECK-NEXT: vle8.v v8, (a0)3828; CHECK-NEXT: vredmax.vs v8, v8, v83829; CHECK-NEXT: vmv.x.s a0, v83830; CHECK-NEXT: ret3831 %v = load <64 x i8>, ptr %x3832 %red = call i8 @llvm.vector.reduce.smax.v64i8(<64 x i8> %v)3833 ret i8 %red3834}3835 3836define i8 @vreduce_smax_v128i8(ptr %x) {3837; CHECK-LABEL: vreduce_smax_v128i8:3838; CHECK: # %bb.0:3839; CHECK-NEXT: li a1, 1283840; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma3841; CHECK-NEXT: vle8.v v8, (a0)3842; CHECK-NEXT: vredmax.vs v8, v8, v83843; CHECK-NEXT: vmv.x.s a0, v83844; CHECK-NEXT: ret3845 %v = load <128 x i8>, ptr %x3846 %red = call i8 @llvm.vector.reduce.smax.v128i8(<128 x i8> %v)3847 ret i8 %red3848}3849 3850define i8 @vreduce_smax_v256i8(ptr %x) {3851; CHECK-LABEL: vreduce_smax_v256i8:3852; CHECK: # %bb.0:3853; CHECK-NEXT: li a1, 1283854; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma3855; CHECK-NEXT: vle8.v v8, (a0)3856; CHECK-NEXT: addi a0, a0, 1283857; CHECK-NEXT: vle8.v v16, (a0)3858; CHECK-NEXT: vmax.vv v8, v8, v163859; CHECK-NEXT: vredmax.vs v8, v8, v83860; CHECK-NEXT: vmv.x.s a0, v83861; CHECK-NEXT: ret3862 %v = load <256 x i8>, ptr %x3863 %red = call i8 @llvm.vector.reduce.smax.v256i8(<256 x i8> %v)3864 ret i8 %red3865}3866 3867define i16 @vreduce_smax_v1i16(<1 x i16> %v) {3868; CHECK-LABEL: vreduce_smax_v1i16:3869; CHECK: # %bb.0:3870; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma3871; CHECK-NEXT: vmv.x.s a0, v83872; CHECK-NEXT: ret3873 %red = call i16 @llvm.vector.reduce.smax.v1i16(<1 x i16> %v)3874 ret i16 %red3875}3876 3877define i16 @vreduce_smax_v2i16(ptr %x) {3878; CHECK-LABEL: vreduce_smax_v2i16:3879; CHECK: # %bb.0:3880; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma3881; CHECK-NEXT: vle16.v v8, (a0)3882; CHECK-NEXT: vredmax.vs v8, v8, v83883; CHECK-NEXT: vmv.x.s a0, v83884; CHECK-NEXT: ret3885 %v = load <2 x i16>, ptr %x3886 %red = call i16 @llvm.vector.reduce.smax.v2i16(<2 x i16> %v)3887 ret i16 %red3888}3889 3890define i16 @vreduce_smax_v4i16(ptr %x) {3891; CHECK-LABEL: vreduce_smax_v4i16:3892; CHECK: # %bb.0:3893; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma3894; CHECK-NEXT: vle16.v v8, (a0)3895; CHECK-NEXT: vredmax.vs v8, v8, v83896; CHECK-NEXT: vmv.x.s a0, v83897; CHECK-NEXT: ret3898 %v = load <4 x i16>, ptr %x3899 %red = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> %v)3900 ret i16 %red3901}3902 3903define i16 @vreduce_smax_v8i16(ptr %x) {3904; CHECK-LABEL: vreduce_smax_v8i16:3905; CHECK: # %bb.0:3906; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma3907; CHECK-NEXT: vle16.v v8, (a0)3908; CHECK-NEXT: vredmax.vs v8, v8, v83909; CHECK-NEXT: vmv.x.s a0, v83910; CHECK-NEXT: ret3911 %v = load <8 x i16>, ptr %x3912 %red = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> %v)3913 ret i16 %red3914}3915 3916define i16 @vreduce_smax_v16i16(ptr %x) {3917; CHECK-LABEL: vreduce_smax_v16i16:3918; CHECK: # %bb.0:3919; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma3920; CHECK-NEXT: vle16.v v8, (a0)3921; CHECK-NEXT: vredmax.vs v8, v8, v83922; CHECK-NEXT: vmv.x.s a0, v83923; CHECK-NEXT: ret3924 %v = load <16 x i16>, ptr %x3925 %red = call i16 @llvm.vector.reduce.smax.v16i16(<16 x i16> %v)3926 ret i16 %red3927}3928 3929define i16 @vreduce_smax_v32i16(ptr %x) {3930; CHECK-LABEL: vreduce_smax_v32i16:3931; CHECK: # %bb.0:3932; CHECK-NEXT: li a1, 323933; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma3934; CHECK-NEXT: vle16.v v8, (a0)3935; CHECK-NEXT: vredmax.vs v8, v8, v83936; CHECK-NEXT: vmv.x.s a0, v83937; CHECK-NEXT: ret3938 %v = load <32 x i16>, ptr %x3939 %red = call i16 @llvm.vector.reduce.smax.v32i16(<32 x i16> %v)3940 ret i16 %red3941}3942 3943define i16 @vreduce_smax_v64i16(ptr %x) {3944; CHECK-LABEL: vreduce_smax_v64i16:3945; CHECK: # %bb.0:3946; CHECK-NEXT: li a1, 643947; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma3948; CHECK-NEXT: vle16.v v8, (a0)3949; CHECK-NEXT: vredmax.vs v8, v8, v83950; CHECK-NEXT: vmv.x.s a0, v83951; CHECK-NEXT: ret3952 %v = load <64 x i16>, ptr %x3953 %red = call i16 @llvm.vector.reduce.smax.v64i16(<64 x i16> %v)3954 ret i16 %red3955}3956 3957define i16 @vreduce_smax_v128i16(ptr %x) {3958; CHECK-LABEL: vreduce_smax_v128i16:3959; CHECK: # %bb.0:3960; CHECK-NEXT: li a1, 643961; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma3962; CHECK-NEXT: vle16.v v8, (a0)3963; CHECK-NEXT: addi a0, a0, 1283964; CHECK-NEXT: vle16.v v16, (a0)3965; CHECK-NEXT: vmax.vv v8, v8, v163966; CHECK-NEXT: vredmax.vs v8, v8, v83967; CHECK-NEXT: vmv.x.s a0, v83968; CHECK-NEXT: ret3969 %v = load <128 x i16>, ptr %x3970 %red = call i16 @llvm.vector.reduce.smax.v128i16(<128 x i16> %v)3971 ret i16 %red3972}3973 3974define i32 @vreduce_smax_v1i32(<1 x i32> %v) {3975; CHECK-LABEL: vreduce_smax_v1i32:3976; CHECK: # %bb.0:3977; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma3978; CHECK-NEXT: vmv.x.s a0, v83979; CHECK-NEXT: ret3980 %red = call i32 @llvm.vector.reduce.smax.v1i32(<1 x i32> %v)3981 ret i32 %red3982}3983 3984define i32 @vreduce_smax_v2i32(ptr %x) {3985; CHECK-LABEL: vreduce_smax_v2i32:3986; CHECK: # %bb.0:3987; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma3988; CHECK-NEXT: vle32.v v8, (a0)3989; CHECK-NEXT: vredmax.vs v8, v8, v83990; CHECK-NEXT: vmv.x.s a0, v83991; CHECK-NEXT: ret3992 %v = load <2 x i32>, ptr %x3993 %red = call i32 @llvm.vector.reduce.smax.v2i32(<2 x i32> %v)3994 ret i32 %red3995}3996 3997define i32 @vreduce_smax_v4i32(ptr %x) {3998; CHECK-LABEL: vreduce_smax_v4i32:3999; CHECK: # %bb.0:4000; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma4001; CHECK-NEXT: vle32.v v8, (a0)4002; CHECK-NEXT: vredmax.vs v8, v8, v84003; CHECK-NEXT: vmv.x.s a0, v84004; CHECK-NEXT: ret4005 %v = load <4 x i32>, ptr %x4006 %red = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> %v)4007 ret i32 %red4008}4009 4010define i32 @vreduce_smax_v8i32(ptr %x) {4011; CHECK-LABEL: vreduce_smax_v8i32:4012; CHECK: # %bb.0:4013; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma4014; CHECK-NEXT: vle32.v v8, (a0)4015; CHECK-NEXT: vredmax.vs v8, v8, v84016; CHECK-NEXT: vmv.x.s a0, v84017; CHECK-NEXT: ret4018 %v = load <8 x i32>, ptr %x4019 %red = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> %v)4020 ret i32 %red4021}4022 4023define i32 @vreduce_smax_v16i32(ptr %x) {4024; CHECK-LABEL: vreduce_smax_v16i32:4025; CHECK: # %bb.0:4026; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma4027; CHECK-NEXT: vle32.v v8, (a0)4028; CHECK-NEXT: vredmax.vs v8, v8, v84029; CHECK-NEXT: vmv.x.s a0, v84030; CHECK-NEXT: ret4031 %v = load <16 x i32>, ptr %x4032 %red = call i32 @llvm.vector.reduce.smax.v16i32(<16 x i32> %v)4033 ret i32 %red4034}4035 4036define i32 @vreduce_smax_v32i32(ptr %x) {4037; CHECK-LABEL: vreduce_smax_v32i32:4038; CHECK: # %bb.0:4039; CHECK-NEXT: li a1, 324040; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma4041; CHECK-NEXT: vle32.v v8, (a0)4042; CHECK-NEXT: vredmax.vs v8, v8, v84043; CHECK-NEXT: vmv.x.s a0, v84044; CHECK-NEXT: ret4045 %v = load <32 x i32>, ptr %x4046 %red = call i32 @llvm.vector.reduce.smax.v32i32(<32 x i32> %v)4047 ret i32 %red4048}4049 4050define i32 @vreduce_smax_v64i32(ptr %x) {4051; CHECK-LABEL: vreduce_smax_v64i32:4052; CHECK: # %bb.0:4053; CHECK-NEXT: li a1, 324054; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma4055; CHECK-NEXT: vle32.v v8, (a0)4056; CHECK-NEXT: addi a0, a0, 1284057; CHECK-NEXT: vle32.v v16, (a0)4058; CHECK-NEXT: vmax.vv v8, v8, v164059; CHECK-NEXT: vredmax.vs v8, v8, v84060; CHECK-NEXT: vmv.x.s a0, v84061; CHECK-NEXT: ret4062 %v = load <64 x i32>, ptr %x4063 %red = call i32 @llvm.vector.reduce.smax.v64i32(<64 x i32> %v)4064 ret i32 %red4065}4066 4067define i64 @vreduce_smax_v1i64(<1 x i64> %v) {4068; RV32-LABEL: vreduce_smax_v1i64:4069; RV32: # %bb.0:4070; RV32-NEXT: li a0, 324071; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma4072; RV32-NEXT: vsrl.vx v9, v8, a04073; RV32-NEXT: vmv.x.s a1, v94074; RV32-NEXT: vmv.x.s a0, v84075; RV32-NEXT: ret4076;4077; RV64-LABEL: vreduce_smax_v1i64:4078; RV64: # %bb.0:4079; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma4080; RV64-NEXT: vmv.x.s a0, v84081; RV64-NEXT: ret4082 %red = call i64 @llvm.vector.reduce.smax.v1i64(<1 x i64> %v)4083 ret i64 %red4084}4085 4086define i64 @vreduce_smax_v2i64(ptr %x) {4087; RV32-LABEL: vreduce_smax_v2i64:4088; RV32: # %bb.0:4089; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma4090; RV32-NEXT: vle64.v v8, (a0)4091; RV32-NEXT: li a0, 324092; RV32-NEXT: vredmax.vs v8, v8, v84093; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma4094; RV32-NEXT: vsrl.vx v9, v8, a04095; RV32-NEXT: vmv.x.s a1, v94096; RV32-NEXT: vmv.x.s a0, v84097; RV32-NEXT: ret4098;4099; RV64-LABEL: vreduce_smax_v2i64:4100; RV64: # %bb.0:4101; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma4102; RV64-NEXT: vle64.v v8, (a0)4103; RV64-NEXT: vredmax.vs v8, v8, v84104; RV64-NEXT: vmv.x.s a0, v84105; RV64-NEXT: ret4106 %v = load <2 x i64>, ptr %x4107 %red = call i64 @llvm.vector.reduce.smax.v2i64(<2 x i64> %v)4108 ret i64 %red4109}4110 4111define i64 @vreduce_smax_v4i64(ptr %x) {4112; RV32-LABEL: vreduce_smax_v4i64:4113; RV32: # %bb.0:4114; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma4115; RV32-NEXT: vle64.v v8, (a0)4116; RV32-NEXT: li a1, 324117; RV32-NEXT: vredmax.vs v8, v8, v84118; RV32-NEXT: vmv.x.s a0, v84119; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma4120; RV32-NEXT: vsrl.vx v8, v8, a14121; RV32-NEXT: vmv.x.s a1, v84122; RV32-NEXT: ret4123;4124; RV64-LABEL: vreduce_smax_v4i64:4125; RV64: # %bb.0:4126; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma4127; RV64-NEXT: vle64.v v8, (a0)4128; RV64-NEXT: vredmax.vs v8, v8, v84129; RV64-NEXT: vmv.x.s a0, v84130; RV64-NEXT: ret4131 %v = load <4 x i64>, ptr %x4132 %red = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> %v)4133 ret i64 %red4134}4135 4136define i64 @vreduce_smax_v8i64(ptr %x) {4137; RV32-LABEL: vreduce_smax_v8i64:4138; RV32: # %bb.0:4139; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma4140; RV32-NEXT: vle64.v v8, (a0)4141; RV32-NEXT: li a1, 324142; RV32-NEXT: vredmax.vs v8, v8, v84143; RV32-NEXT: vmv.x.s a0, v84144; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma4145; RV32-NEXT: vsrl.vx v8, v8, a14146; RV32-NEXT: vmv.x.s a1, v84147; RV32-NEXT: ret4148;4149; RV64-LABEL: vreduce_smax_v8i64:4150; RV64: # %bb.0:4151; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma4152; RV64-NEXT: vle64.v v8, (a0)4153; RV64-NEXT: vredmax.vs v8, v8, v84154; RV64-NEXT: vmv.x.s a0, v84155; RV64-NEXT: ret4156 %v = load <8 x i64>, ptr %x4157 %red = call i64 @llvm.vector.reduce.smax.v8i64(<8 x i64> %v)4158 ret i64 %red4159}4160 4161define i64 @vreduce_smax_v16i64(ptr %x) {4162; RV32-LABEL: vreduce_smax_v16i64:4163; RV32: # %bb.0:4164; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma4165; RV32-NEXT: vle64.v v8, (a0)4166; RV32-NEXT: li a1, 324167; RV32-NEXT: vredmax.vs v8, v8, v84168; RV32-NEXT: vmv.x.s a0, v84169; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma4170; RV32-NEXT: vsrl.vx v8, v8, a14171; RV32-NEXT: vmv.x.s a1, v84172; RV32-NEXT: ret4173;4174; RV64-LABEL: vreduce_smax_v16i64:4175; RV64: # %bb.0:4176; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma4177; RV64-NEXT: vle64.v v8, (a0)4178; RV64-NEXT: vredmax.vs v8, v8, v84179; RV64-NEXT: vmv.x.s a0, v84180; RV64-NEXT: ret4181 %v = load <16 x i64>, ptr %x4182 %red = call i64 @llvm.vector.reduce.smax.v16i64(<16 x i64> %v)4183 ret i64 %red4184}4185 4186define i64 @vreduce_smax_v32i64(ptr %x) {4187; RV32-LABEL: vreduce_smax_v32i64:4188; RV32: # %bb.0:4189; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma4190; RV32-NEXT: vle64.v v8, (a0)4191; RV32-NEXT: addi a0, a0, 1284192; RV32-NEXT: vle64.v v16, (a0)4193; RV32-NEXT: li a1, 324194; RV32-NEXT: vmax.vv v8, v8, v164195; RV32-NEXT: vredmax.vs v8, v8, v84196; RV32-NEXT: vmv.x.s a0, v84197; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma4198; RV32-NEXT: vsrl.vx v8, v8, a14199; RV32-NEXT: vmv.x.s a1, v84200; RV32-NEXT: ret4201;4202; RV64-LABEL: vreduce_smax_v32i64:4203; RV64: # %bb.0:4204; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma4205; RV64-NEXT: vle64.v v8, (a0)4206; RV64-NEXT: addi a0, a0, 1284207; RV64-NEXT: vle64.v v16, (a0)4208; RV64-NEXT: vmax.vv v8, v8, v164209; RV64-NEXT: vredmax.vs v8, v8, v84210; RV64-NEXT: vmv.x.s a0, v84211; RV64-NEXT: ret4212 %v = load <32 x i64>, ptr %x4213 %red = call i64 @llvm.vector.reduce.smax.v32i64(<32 x i64> %v)4214 ret i64 %red4215}4216 4217define i64 @vreduce_smax_v64i64(ptr %x) nounwind {4218; RV32-LABEL: vreduce_smax_v64i64:4219; RV32: # %bb.0:4220; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma4221; RV32-NEXT: vle64.v v8, (a0)4222; RV32-NEXT: addi a1, a0, 3844223; RV32-NEXT: vle64.v v16, (a1)4224; RV32-NEXT: addi a1, a0, 2564225; RV32-NEXT: addi a0, a0, 1284226; RV32-NEXT: vle64.v v0, (a0)4227; RV32-NEXT: vle64.v v24, (a1)4228; RV32-NEXT: li a1, 324229; RV32-NEXT: vmax.vv v16, v0, v164230; RV32-NEXT: vmax.vv v8, v8, v244231; RV32-NEXT: vmax.vv v8, v8, v164232; RV32-NEXT: vredmax.vs v8, v8, v84233; RV32-NEXT: vmv.x.s a0, v84234; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma4235; RV32-NEXT: vsrl.vx v8, v8, a14236; RV32-NEXT: vmv.x.s a1, v84237; RV32-NEXT: ret4238;4239; RV64-LABEL: vreduce_smax_v64i64:4240; RV64: # %bb.0:4241; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma4242; RV64-NEXT: vle64.v v8, (a0)4243; RV64-NEXT: addi a1, a0, 3844244; RV64-NEXT: vle64.v v16, (a1)4245; RV64-NEXT: addi a1, a0, 2564246; RV64-NEXT: addi a0, a0, 1284247; RV64-NEXT: vle64.v v24, (a0)4248; RV64-NEXT: vle64.v v0, (a1)4249; RV64-NEXT: vmax.vv v16, v24, v164250; RV64-NEXT: vmax.vv v8, v8, v04251; RV64-NEXT: vmax.vv v8, v8, v164252; RV64-NEXT: vredmax.vs v8, v8, v84253; RV64-NEXT: vmv.x.s a0, v84254; RV64-NEXT: ret4255 %v = load <64 x i64>, ptr %x4256 %red = call i64 @llvm.vector.reduce.smax.v64i64(<64 x i64> %v)4257 ret i64 %red4258}4259 4260define i8 @vreduce_umin_v1i8(<1 x i8> %v) {4261; CHECK-LABEL: vreduce_umin_v1i8:4262; CHECK: # %bb.0:4263; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma4264; CHECK-NEXT: vmv.x.s a0, v84265; CHECK-NEXT: ret4266 %red = call i8 @llvm.vector.reduce.umin.v1i8(<1 x i8> %v)4267 ret i8 %red4268}4269 4270define i8 @vreduce_umin_v2i8(ptr %x) {4271; CHECK-LABEL: vreduce_umin_v2i8:4272; CHECK: # %bb.0:4273; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma4274; CHECK-NEXT: vle8.v v8, (a0)4275; CHECK-NEXT: vredminu.vs v8, v8, v84276; CHECK-NEXT: vmv.x.s a0, v84277; CHECK-NEXT: ret4278 %v = load <2 x i8>, ptr %x4279 %red = call i8 @llvm.vector.reduce.umin.v2i8(<2 x i8> %v)4280 ret i8 %red4281}4282 4283define i8 @vreduce_umin_v3i8(ptr %x) {4284; CHECK-LABEL: vreduce_umin_v3i8:4285; CHECK: # %bb.0:4286; CHECK-NEXT: vsetivli zero, 3, e8, mf4, ta, ma4287; CHECK-NEXT: vle8.v v8, (a0)4288; CHECK-NEXT: li a0, -14289; CHECK-NEXT: vmv.s.x v9, a04290; CHECK-NEXT: vredminu.vs v8, v8, v94291; CHECK-NEXT: vmv.x.s a0, v84292; CHECK-NEXT: ret4293 %v = load <3 x i8>, ptr %x4294 %red = call i8 @llvm.vector.reduce.umin.v3i8(<3 x i8> %v)4295 ret i8 %red4296}4297 4298define i8 @vreduce_umin_v4i8(ptr %x) {4299; CHECK-LABEL: vreduce_umin_v4i8:4300; CHECK: # %bb.0:4301; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma4302; CHECK-NEXT: vle8.v v8, (a0)4303; CHECK-NEXT: vredminu.vs v8, v8, v84304; CHECK-NEXT: vmv.x.s a0, v84305; CHECK-NEXT: ret4306 %v = load <4 x i8>, ptr %x4307 %red = call i8 @llvm.vector.reduce.umin.v4i8(<4 x i8> %v)4308 ret i8 %red4309}4310 4311define i8 @vreduce_umin_v8i8(ptr %x) {4312; CHECK-LABEL: vreduce_umin_v8i8:4313; CHECK: # %bb.0:4314; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma4315; CHECK-NEXT: vle8.v v8, (a0)4316; CHECK-NEXT: vredminu.vs v8, v8, v84317; CHECK-NEXT: vmv.x.s a0, v84318; CHECK-NEXT: ret4319 %v = load <8 x i8>, ptr %x4320 %red = call i8 @llvm.vector.reduce.umin.v8i8(<8 x i8> %v)4321 ret i8 %red4322}4323 4324define i8 @vreduce_umin_v16i8(ptr %x) {4325; CHECK-LABEL: vreduce_umin_v16i8:4326; CHECK: # %bb.0:4327; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma4328; CHECK-NEXT: vle8.v v8, (a0)4329; CHECK-NEXT: vredminu.vs v8, v8, v84330; CHECK-NEXT: vmv.x.s a0, v84331; CHECK-NEXT: ret4332 %v = load <16 x i8>, ptr %x4333 %red = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> %v)4334 ret i8 %red4335}4336 4337define i8 @vreduce_umin_v32i8(ptr %x) {4338; CHECK-LABEL: vreduce_umin_v32i8:4339; CHECK: # %bb.0:4340; CHECK-NEXT: li a1, 324341; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma4342; CHECK-NEXT: vle8.v v8, (a0)4343; CHECK-NEXT: vredminu.vs v8, v8, v84344; CHECK-NEXT: vmv.x.s a0, v84345; CHECK-NEXT: ret4346 %v = load <32 x i8>, ptr %x4347 %red = call i8 @llvm.vector.reduce.umin.v32i8(<32 x i8> %v)4348 ret i8 %red4349}4350 4351define i8 @vreduce_umin_v64i8(ptr %x) {4352; CHECK-LABEL: vreduce_umin_v64i8:4353; CHECK: # %bb.0:4354; CHECK-NEXT: li a1, 644355; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma4356; CHECK-NEXT: vle8.v v8, (a0)4357; CHECK-NEXT: vredminu.vs v8, v8, v84358; CHECK-NEXT: vmv.x.s a0, v84359; CHECK-NEXT: ret4360 %v = load <64 x i8>, ptr %x4361 %red = call i8 @llvm.vector.reduce.umin.v64i8(<64 x i8> %v)4362 ret i8 %red4363}4364 4365define i8 @vreduce_umin_v128i8(ptr %x) {4366; CHECK-LABEL: vreduce_umin_v128i8:4367; CHECK: # %bb.0:4368; CHECK-NEXT: li a1, 1284369; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma4370; CHECK-NEXT: vle8.v v8, (a0)4371; CHECK-NEXT: vredminu.vs v8, v8, v84372; CHECK-NEXT: vmv.x.s a0, v84373; CHECK-NEXT: ret4374 %v = load <128 x i8>, ptr %x4375 %red = call i8 @llvm.vector.reduce.umin.v128i8(<128 x i8> %v)4376 ret i8 %red4377}4378 4379define i8 @vreduce_umin_v256i8(ptr %x) {4380; CHECK-LABEL: vreduce_umin_v256i8:4381; CHECK: # %bb.0:4382; CHECK-NEXT: li a1, 1284383; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma4384; CHECK-NEXT: vle8.v v8, (a0)4385; CHECK-NEXT: addi a0, a0, 1284386; CHECK-NEXT: vle8.v v16, (a0)4387; CHECK-NEXT: vminu.vv v8, v8, v164388; CHECK-NEXT: vredminu.vs v8, v8, v84389; CHECK-NEXT: vmv.x.s a0, v84390; CHECK-NEXT: ret4391 %v = load <256 x i8>, ptr %x4392 %red = call i8 @llvm.vector.reduce.umin.v256i8(<256 x i8> %v)4393 ret i8 %red4394}4395 4396define i16 @vreduce_umin_v1i16(<1 x i16> %v) {4397; CHECK-LABEL: vreduce_umin_v1i16:4398; CHECK: # %bb.0:4399; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma4400; CHECK-NEXT: vmv.x.s a0, v84401; CHECK-NEXT: ret4402 %red = call i16 @llvm.vector.reduce.umin.v1i16(<1 x i16> %v)4403 ret i16 %red4404}4405 4406define i16 @vreduce_umin_v2i16(ptr %x) {4407; CHECK-LABEL: vreduce_umin_v2i16:4408; CHECK: # %bb.0:4409; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma4410; CHECK-NEXT: vle16.v v8, (a0)4411; CHECK-NEXT: vredminu.vs v8, v8, v84412; CHECK-NEXT: vmv.x.s a0, v84413; CHECK-NEXT: ret4414 %v = load <2 x i16>, ptr %x4415 %red = call i16 @llvm.vector.reduce.umin.v2i16(<2 x i16> %v)4416 ret i16 %red4417}4418 4419define i16 @vreduce_umin_v4i16(ptr %x) {4420; CHECK-LABEL: vreduce_umin_v4i16:4421; CHECK: # %bb.0:4422; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma4423; CHECK-NEXT: vle16.v v8, (a0)4424; CHECK-NEXT: vredminu.vs v8, v8, v84425; CHECK-NEXT: vmv.x.s a0, v84426; CHECK-NEXT: ret4427 %v = load <4 x i16>, ptr %x4428 %red = call i16 @llvm.vector.reduce.umin.v4i16(<4 x i16> %v)4429 ret i16 %red4430}4431 4432define i16 @vreduce_umin_v8i16(ptr %x) {4433; CHECK-LABEL: vreduce_umin_v8i16:4434; CHECK: # %bb.0:4435; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma4436; CHECK-NEXT: vle16.v v8, (a0)4437; CHECK-NEXT: vredminu.vs v8, v8, v84438; CHECK-NEXT: vmv.x.s a0, v84439; CHECK-NEXT: ret4440 %v = load <8 x i16>, ptr %x4441 %red = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> %v)4442 ret i16 %red4443}4444 4445define i16 @vreduce_umin_v16i16(ptr %x) {4446; CHECK-LABEL: vreduce_umin_v16i16:4447; CHECK: # %bb.0:4448; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma4449; CHECK-NEXT: vle16.v v8, (a0)4450; CHECK-NEXT: vredminu.vs v8, v8, v84451; CHECK-NEXT: vmv.x.s a0, v84452; CHECK-NEXT: ret4453 %v = load <16 x i16>, ptr %x4454 %red = call i16 @llvm.vector.reduce.umin.v16i16(<16 x i16> %v)4455 ret i16 %red4456}4457 4458define i16 @vreduce_umin_v32i16(ptr %x) {4459; CHECK-LABEL: vreduce_umin_v32i16:4460; CHECK: # %bb.0:4461; CHECK-NEXT: li a1, 324462; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma4463; CHECK-NEXT: vle16.v v8, (a0)4464; CHECK-NEXT: vredminu.vs v8, v8, v84465; CHECK-NEXT: vmv.x.s a0, v84466; CHECK-NEXT: ret4467 %v = load <32 x i16>, ptr %x4468 %red = call i16 @llvm.vector.reduce.umin.v32i16(<32 x i16> %v)4469 ret i16 %red4470}4471 4472define i16 @vreduce_umin_v64i16(ptr %x) {4473; CHECK-LABEL: vreduce_umin_v64i16:4474; CHECK: # %bb.0:4475; CHECK-NEXT: li a1, 644476; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma4477; CHECK-NEXT: vle16.v v8, (a0)4478; CHECK-NEXT: vredminu.vs v8, v8, v84479; CHECK-NEXT: vmv.x.s a0, v84480; CHECK-NEXT: ret4481 %v = load <64 x i16>, ptr %x4482 %red = call i16 @llvm.vector.reduce.umin.v64i16(<64 x i16> %v)4483 ret i16 %red4484}4485 4486define i16 @vreduce_umin_v128i16(ptr %x) {4487; CHECK-LABEL: vreduce_umin_v128i16:4488; CHECK: # %bb.0:4489; CHECK-NEXT: li a1, 644490; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma4491; CHECK-NEXT: vle16.v v8, (a0)4492; CHECK-NEXT: addi a0, a0, 1284493; CHECK-NEXT: vle16.v v16, (a0)4494; CHECK-NEXT: vminu.vv v8, v8, v164495; CHECK-NEXT: vredminu.vs v8, v8, v84496; CHECK-NEXT: vmv.x.s a0, v84497; CHECK-NEXT: ret4498 %v = load <128 x i16>, ptr %x4499 %red = call i16 @llvm.vector.reduce.umin.v128i16(<128 x i16> %v)4500 ret i16 %red4501}4502 4503define i32 @vreduce_umin_v1i32(<1 x i32> %v) {4504; CHECK-LABEL: vreduce_umin_v1i32:4505; CHECK: # %bb.0:4506; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma4507; CHECK-NEXT: vmv.x.s a0, v84508; CHECK-NEXT: ret4509 %red = call i32 @llvm.vector.reduce.umin.v1i32(<1 x i32> %v)4510 ret i32 %red4511}4512 4513define i32 @vreduce_umin_v2i32(ptr %x) {4514; CHECK-LABEL: vreduce_umin_v2i32:4515; CHECK: # %bb.0:4516; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma4517; CHECK-NEXT: vle32.v v8, (a0)4518; CHECK-NEXT: vredminu.vs v8, v8, v84519; CHECK-NEXT: vmv.x.s a0, v84520; CHECK-NEXT: ret4521 %v = load <2 x i32>, ptr %x4522 %red = call i32 @llvm.vector.reduce.umin.v2i32(<2 x i32> %v)4523 ret i32 %red4524}4525 4526define i32 @vreduce_umin_v4i32(ptr %x) {4527; CHECK-LABEL: vreduce_umin_v4i32:4528; CHECK: # %bb.0:4529; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma4530; CHECK-NEXT: vle32.v v8, (a0)4531; CHECK-NEXT: vredminu.vs v8, v8, v84532; CHECK-NEXT: vmv.x.s a0, v84533; CHECK-NEXT: ret4534 %v = load <4 x i32>, ptr %x4535 %red = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> %v)4536 ret i32 %red4537}4538 4539define i32 @vreduce_umin_v8i32(ptr %x) {4540; CHECK-LABEL: vreduce_umin_v8i32:4541; CHECK: # %bb.0:4542; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma4543; CHECK-NEXT: vle32.v v8, (a0)4544; CHECK-NEXT: vredminu.vs v8, v8, v84545; CHECK-NEXT: vmv.x.s a0, v84546; CHECK-NEXT: ret4547 %v = load <8 x i32>, ptr %x4548 %red = call i32 @llvm.vector.reduce.umin.v8i32(<8 x i32> %v)4549 ret i32 %red4550}4551 4552define i32 @vreduce_umin_v16i32(ptr %x) {4553; CHECK-LABEL: vreduce_umin_v16i32:4554; CHECK: # %bb.0:4555; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma4556; CHECK-NEXT: vle32.v v8, (a0)4557; CHECK-NEXT: vredminu.vs v8, v8, v84558; CHECK-NEXT: vmv.x.s a0, v84559; CHECK-NEXT: ret4560 %v = load <16 x i32>, ptr %x4561 %red = call i32 @llvm.vector.reduce.umin.v16i32(<16 x i32> %v)4562 ret i32 %red4563}4564 4565define i32 @vreduce_umin_v32i32(ptr %x) {4566; CHECK-LABEL: vreduce_umin_v32i32:4567; CHECK: # %bb.0:4568; CHECK-NEXT: li a1, 324569; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma4570; CHECK-NEXT: vle32.v v8, (a0)4571; CHECK-NEXT: vredminu.vs v8, v8, v84572; CHECK-NEXT: vmv.x.s a0, v84573; CHECK-NEXT: ret4574 %v = load <32 x i32>, ptr %x4575 %red = call i32 @llvm.vector.reduce.umin.v32i32(<32 x i32> %v)4576 ret i32 %red4577}4578 4579define i32 @vreduce_umin_v64i32(ptr %x) {4580; CHECK-LABEL: vreduce_umin_v64i32:4581; CHECK: # %bb.0:4582; CHECK-NEXT: li a1, 324583; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma4584; CHECK-NEXT: vle32.v v8, (a0)4585; CHECK-NEXT: addi a0, a0, 1284586; CHECK-NEXT: vle32.v v16, (a0)4587; CHECK-NEXT: vminu.vv v8, v8, v164588; CHECK-NEXT: vredminu.vs v8, v8, v84589; CHECK-NEXT: vmv.x.s a0, v84590; CHECK-NEXT: ret4591 %v = load <64 x i32>, ptr %x4592 %red = call i32 @llvm.vector.reduce.umin.v64i32(<64 x i32> %v)4593 ret i32 %red4594}4595 4596define i64 @vreduce_umin_v1i64(<1 x i64> %v) {4597; RV32-LABEL: vreduce_umin_v1i64:4598; RV32: # %bb.0:4599; RV32-NEXT: li a0, 324600; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma4601; RV32-NEXT: vsrl.vx v9, v8, a04602; RV32-NEXT: vmv.x.s a1, v94603; RV32-NEXT: vmv.x.s a0, v84604; RV32-NEXT: ret4605;4606; RV64-LABEL: vreduce_umin_v1i64:4607; RV64: # %bb.0:4608; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma4609; RV64-NEXT: vmv.x.s a0, v84610; RV64-NEXT: ret4611 %red = call i64 @llvm.vector.reduce.umin.v1i64(<1 x i64> %v)4612 ret i64 %red4613}4614 4615define i64 @vreduce_umin_v2i64(ptr %x) {4616; RV32-LABEL: vreduce_umin_v2i64:4617; RV32: # %bb.0:4618; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma4619; RV32-NEXT: vle64.v v8, (a0)4620; RV32-NEXT: li a0, 324621; RV32-NEXT: vredminu.vs v8, v8, v84622; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma4623; RV32-NEXT: vsrl.vx v9, v8, a04624; RV32-NEXT: vmv.x.s a1, v94625; RV32-NEXT: vmv.x.s a0, v84626; RV32-NEXT: ret4627;4628; RV64-LABEL: vreduce_umin_v2i64:4629; RV64: # %bb.0:4630; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma4631; RV64-NEXT: vle64.v v8, (a0)4632; RV64-NEXT: vredminu.vs v8, v8, v84633; RV64-NEXT: vmv.x.s a0, v84634; RV64-NEXT: ret4635 %v = load <2 x i64>, ptr %x4636 %red = call i64 @llvm.vector.reduce.umin.v2i64(<2 x i64> %v)4637 ret i64 %red4638}4639 4640define i64 @vreduce_umin_v4i64(ptr %x) {4641; RV32-LABEL: vreduce_umin_v4i64:4642; RV32: # %bb.0:4643; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma4644; RV32-NEXT: vle64.v v8, (a0)4645; RV32-NEXT: li a1, 324646; RV32-NEXT: vredminu.vs v8, v8, v84647; RV32-NEXT: vmv.x.s a0, v84648; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma4649; RV32-NEXT: vsrl.vx v8, v8, a14650; RV32-NEXT: vmv.x.s a1, v84651; RV32-NEXT: ret4652;4653; RV64-LABEL: vreduce_umin_v4i64:4654; RV64: # %bb.0:4655; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma4656; RV64-NEXT: vle64.v v8, (a0)4657; RV64-NEXT: vredminu.vs v8, v8, v84658; RV64-NEXT: vmv.x.s a0, v84659; RV64-NEXT: ret4660 %v = load <4 x i64>, ptr %x4661 %red = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> %v)4662 ret i64 %red4663}4664 4665define i64 @vreduce_umin_v8i64(ptr %x) {4666; RV32-LABEL: vreduce_umin_v8i64:4667; RV32: # %bb.0:4668; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma4669; RV32-NEXT: vle64.v v8, (a0)4670; RV32-NEXT: li a1, 324671; RV32-NEXT: vredminu.vs v8, v8, v84672; RV32-NEXT: vmv.x.s a0, v84673; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma4674; RV32-NEXT: vsrl.vx v8, v8, a14675; RV32-NEXT: vmv.x.s a1, v84676; RV32-NEXT: ret4677;4678; RV64-LABEL: vreduce_umin_v8i64:4679; RV64: # %bb.0:4680; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma4681; RV64-NEXT: vle64.v v8, (a0)4682; RV64-NEXT: vredminu.vs v8, v8, v84683; RV64-NEXT: vmv.x.s a0, v84684; RV64-NEXT: ret4685 %v = load <8 x i64>, ptr %x4686 %red = call i64 @llvm.vector.reduce.umin.v8i64(<8 x i64> %v)4687 ret i64 %red4688}4689 4690define i64 @vreduce_umin_v16i64(ptr %x) {4691; RV32-LABEL: vreduce_umin_v16i64:4692; RV32: # %bb.0:4693; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma4694; RV32-NEXT: vle64.v v8, (a0)4695; RV32-NEXT: li a1, 324696; RV32-NEXT: vredminu.vs v8, v8, v84697; RV32-NEXT: vmv.x.s a0, v84698; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma4699; RV32-NEXT: vsrl.vx v8, v8, a14700; RV32-NEXT: vmv.x.s a1, v84701; RV32-NEXT: ret4702;4703; RV64-LABEL: vreduce_umin_v16i64:4704; RV64: # %bb.0:4705; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma4706; RV64-NEXT: vle64.v v8, (a0)4707; RV64-NEXT: vredminu.vs v8, v8, v84708; RV64-NEXT: vmv.x.s a0, v84709; RV64-NEXT: ret4710 %v = load <16 x i64>, ptr %x4711 %red = call i64 @llvm.vector.reduce.umin.v16i64(<16 x i64> %v)4712 ret i64 %red4713}4714 4715define i64 @vreduce_umin_v32i64(ptr %x) {4716; RV32-LABEL: vreduce_umin_v32i64:4717; RV32: # %bb.0:4718; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma4719; RV32-NEXT: vle64.v v8, (a0)4720; RV32-NEXT: addi a0, a0, 1284721; RV32-NEXT: vle64.v v16, (a0)4722; RV32-NEXT: li a1, 324723; RV32-NEXT: vminu.vv v8, v8, v164724; RV32-NEXT: vredminu.vs v8, v8, v84725; RV32-NEXT: vmv.x.s a0, v84726; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma4727; RV32-NEXT: vsrl.vx v8, v8, a14728; RV32-NEXT: vmv.x.s a1, v84729; RV32-NEXT: ret4730;4731; RV64-LABEL: vreduce_umin_v32i64:4732; RV64: # %bb.0:4733; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma4734; RV64-NEXT: vle64.v v8, (a0)4735; RV64-NEXT: addi a0, a0, 1284736; RV64-NEXT: vle64.v v16, (a0)4737; RV64-NEXT: vminu.vv v8, v8, v164738; RV64-NEXT: vredminu.vs v8, v8, v84739; RV64-NEXT: vmv.x.s a0, v84740; RV64-NEXT: ret4741 %v = load <32 x i64>, ptr %x4742 %red = call i64 @llvm.vector.reduce.umin.v32i64(<32 x i64> %v)4743 ret i64 %red4744}4745 4746define i64 @vreduce_umin_v64i64(ptr %x) nounwind {4747; RV32-LABEL: vreduce_umin_v64i64:4748; RV32: # %bb.0:4749; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma4750; RV32-NEXT: vle64.v v8, (a0)4751; RV32-NEXT: addi a1, a0, 3844752; RV32-NEXT: vle64.v v16, (a1)4753; RV32-NEXT: addi a1, a0, 2564754; RV32-NEXT: addi a0, a0, 1284755; RV32-NEXT: vle64.v v0, (a0)4756; RV32-NEXT: vle64.v v24, (a1)4757; RV32-NEXT: li a1, 324758; RV32-NEXT: vminu.vv v16, v0, v164759; RV32-NEXT: vminu.vv v8, v8, v244760; RV32-NEXT: vminu.vv v8, v8, v164761; RV32-NEXT: vredminu.vs v8, v8, v84762; RV32-NEXT: vmv.x.s a0, v84763; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma4764; RV32-NEXT: vsrl.vx v8, v8, a14765; RV32-NEXT: vmv.x.s a1, v84766; RV32-NEXT: ret4767;4768; RV64-LABEL: vreduce_umin_v64i64:4769; RV64: # %bb.0:4770; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma4771; RV64-NEXT: vle64.v v8, (a0)4772; RV64-NEXT: addi a1, a0, 3844773; RV64-NEXT: vle64.v v16, (a1)4774; RV64-NEXT: addi a1, a0, 2564775; RV64-NEXT: addi a0, a0, 1284776; RV64-NEXT: vle64.v v24, (a0)4777; RV64-NEXT: vle64.v v0, (a1)4778; RV64-NEXT: vminu.vv v16, v24, v164779; RV64-NEXT: vminu.vv v8, v8, v04780; RV64-NEXT: vminu.vv v8, v8, v164781; RV64-NEXT: vredminu.vs v8, v8, v84782; RV64-NEXT: vmv.x.s a0, v84783; RV64-NEXT: ret4784 %v = load <64 x i64>, ptr %x4785 %red = call i64 @llvm.vector.reduce.umin.v64i64(<64 x i64> %v)4786 ret i64 %red4787}4788 4789define i8 @vreduce_umax_v1i8(<1 x i8> %v) {4790; CHECK-LABEL: vreduce_umax_v1i8:4791; CHECK: # %bb.0:4792; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma4793; CHECK-NEXT: vmv.x.s a0, v84794; CHECK-NEXT: ret4795 %red = call i8 @llvm.vector.reduce.umax.v1i8(<1 x i8> %v)4796 ret i8 %red4797}4798 4799define i8 @vreduce_umax_v2i8(ptr %x) {4800; CHECK-LABEL: vreduce_umax_v2i8:4801; CHECK: # %bb.0:4802; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma4803; CHECK-NEXT: vle8.v v8, (a0)4804; CHECK-NEXT: vredmaxu.vs v8, v8, v84805; CHECK-NEXT: vmv.x.s a0, v84806; CHECK-NEXT: ret4807 %v = load <2 x i8>, ptr %x4808 %red = call i8 @llvm.vector.reduce.umax.v2i8(<2 x i8> %v)4809 ret i8 %red4810}4811 4812define i8 @vreduce_umax_v3i8(ptr %x) {4813; CHECK-LABEL: vreduce_umax_v3i8:4814; CHECK: # %bb.0:4815; CHECK-NEXT: vsetivli zero, 3, e8, mf4, ta, ma4816; CHECK-NEXT: vle8.v v8, (a0)4817; CHECK-NEXT: vmv.s.x v9, zero4818; CHECK-NEXT: vredmaxu.vs v8, v8, v94819; CHECK-NEXT: vmv.x.s a0, v84820; CHECK-NEXT: ret4821 %v = load <3 x i8>, ptr %x4822 %red = call i8 @llvm.vector.reduce.umax.v3i8(<3 x i8> %v)4823 ret i8 %red4824}4825 4826define i8 @vreduce_umax_v4i8(ptr %x) {4827; CHECK-LABEL: vreduce_umax_v4i8:4828; CHECK: # %bb.0:4829; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma4830; CHECK-NEXT: vle8.v v8, (a0)4831; CHECK-NEXT: vredmaxu.vs v8, v8, v84832; CHECK-NEXT: vmv.x.s a0, v84833; CHECK-NEXT: ret4834 %v = load <4 x i8>, ptr %x4835 %red = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> %v)4836 ret i8 %red4837}4838 4839define i8 @vreduce_umax_v8i8(ptr %x) {4840; CHECK-LABEL: vreduce_umax_v8i8:4841; CHECK: # %bb.0:4842; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma4843; CHECK-NEXT: vle8.v v8, (a0)4844; CHECK-NEXT: vredmaxu.vs v8, v8, v84845; CHECK-NEXT: vmv.x.s a0, v84846; CHECK-NEXT: ret4847 %v = load <8 x i8>, ptr %x4848 %red = call i8 @llvm.vector.reduce.umax.v8i8(<8 x i8> %v)4849 ret i8 %red4850}4851 4852define i8 @vreduce_umax_v16i8(ptr %x) {4853; CHECK-LABEL: vreduce_umax_v16i8:4854; CHECK: # %bb.0:4855; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma4856; CHECK-NEXT: vle8.v v8, (a0)4857; CHECK-NEXT: vredmaxu.vs v8, v8, v84858; CHECK-NEXT: vmv.x.s a0, v84859; CHECK-NEXT: ret4860 %v = load <16 x i8>, ptr %x4861 %red = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> %v)4862 ret i8 %red4863}4864 4865define i8 @vreduce_umax_v32i8(ptr %x) {4866; CHECK-LABEL: vreduce_umax_v32i8:4867; CHECK: # %bb.0:4868; CHECK-NEXT: li a1, 324869; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma4870; CHECK-NEXT: vle8.v v8, (a0)4871; CHECK-NEXT: vredmaxu.vs v8, v8, v84872; CHECK-NEXT: vmv.x.s a0, v84873; CHECK-NEXT: ret4874 %v = load <32 x i8>, ptr %x4875 %red = call i8 @llvm.vector.reduce.umax.v32i8(<32 x i8> %v)4876 ret i8 %red4877}4878 4879define i8 @vreduce_umax_v64i8(ptr %x) {4880; CHECK-LABEL: vreduce_umax_v64i8:4881; CHECK: # %bb.0:4882; CHECK-NEXT: li a1, 644883; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma4884; CHECK-NEXT: vle8.v v8, (a0)4885; CHECK-NEXT: vredmaxu.vs v8, v8, v84886; CHECK-NEXT: vmv.x.s a0, v84887; CHECK-NEXT: ret4888 %v = load <64 x i8>, ptr %x4889 %red = call i8 @llvm.vector.reduce.umax.v64i8(<64 x i8> %v)4890 ret i8 %red4891}4892 4893define i8 @vreduce_umax_v128i8(ptr %x) {4894; CHECK-LABEL: vreduce_umax_v128i8:4895; CHECK: # %bb.0:4896; CHECK-NEXT: li a1, 1284897; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma4898; CHECK-NEXT: vle8.v v8, (a0)4899; CHECK-NEXT: vredmaxu.vs v8, v8, v84900; CHECK-NEXT: vmv.x.s a0, v84901; CHECK-NEXT: ret4902 %v = load <128 x i8>, ptr %x4903 %red = call i8 @llvm.vector.reduce.umax.v128i8(<128 x i8> %v)4904 ret i8 %red4905}4906 4907define i8 @vreduce_umax_v256i8(ptr %x) {4908; CHECK-LABEL: vreduce_umax_v256i8:4909; CHECK: # %bb.0:4910; CHECK-NEXT: li a1, 1284911; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma4912; CHECK-NEXT: vle8.v v8, (a0)4913; CHECK-NEXT: addi a0, a0, 1284914; CHECK-NEXT: vle8.v v16, (a0)4915; CHECK-NEXT: vmaxu.vv v8, v8, v164916; CHECK-NEXT: vredmaxu.vs v8, v8, v84917; CHECK-NEXT: vmv.x.s a0, v84918; CHECK-NEXT: ret4919 %v = load <256 x i8>, ptr %x4920 %red = call i8 @llvm.vector.reduce.umax.v256i8(<256 x i8> %v)4921 ret i8 %red4922}4923 4924define i16 @vreduce_umax_v1i16(<1 x i16> %v) {4925; CHECK-LABEL: vreduce_umax_v1i16:4926; CHECK: # %bb.0:4927; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma4928; CHECK-NEXT: vmv.x.s a0, v84929; CHECK-NEXT: ret4930 %red = call i16 @llvm.vector.reduce.umax.v1i16(<1 x i16> %v)4931 ret i16 %red4932}4933 4934define i16 @vreduce_umax_v2i16(ptr %x) {4935; CHECK-LABEL: vreduce_umax_v2i16:4936; CHECK: # %bb.0:4937; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma4938; CHECK-NEXT: vle16.v v8, (a0)4939; CHECK-NEXT: vredmaxu.vs v8, v8, v84940; CHECK-NEXT: vmv.x.s a0, v84941; CHECK-NEXT: ret4942 %v = load <2 x i16>, ptr %x4943 %red = call i16 @llvm.vector.reduce.umax.v2i16(<2 x i16> %v)4944 ret i16 %red4945}4946 4947define i16 @vreduce_umax_v4i16(ptr %x) {4948; CHECK-LABEL: vreduce_umax_v4i16:4949; CHECK: # %bb.0:4950; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma4951; CHECK-NEXT: vle16.v v8, (a0)4952; CHECK-NEXT: vredmaxu.vs v8, v8, v84953; CHECK-NEXT: vmv.x.s a0, v84954; CHECK-NEXT: ret4955 %v = load <4 x i16>, ptr %x4956 %red = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> %v)4957 ret i16 %red4958}4959 4960define i16 @vreduce_umax_v8i16(ptr %x) {4961; CHECK-LABEL: vreduce_umax_v8i16:4962; CHECK: # %bb.0:4963; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma4964; CHECK-NEXT: vle16.v v8, (a0)4965; CHECK-NEXT: vredmaxu.vs v8, v8, v84966; CHECK-NEXT: vmv.x.s a0, v84967; CHECK-NEXT: ret4968 %v = load <8 x i16>, ptr %x4969 %red = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> %v)4970 ret i16 %red4971}4972 4973define i16 @vreduce_umax_v16i16(ptr %x) {4974; CHECK-LABEL: vreduce_umax_v16i16:4975; CHECK: # %bb.0:4976; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma4977; CHECK-NEXT: vle16.v v8, (a0)4978; CHECK-NEXT: vredmaxu.vs v8, v8, v84979; CHECK-NEXT: vmv.x.s a0, v84980; CHECK-NEXT: ret4981 %v = load <16 x i16>, ptr %x4982 %red = call i16 @llvm.vector.reduce.umax.v16i16(<16 x i16> %v)4983 ret i16 %red4984}4985 4986define i16 @vreduce_umax_v32i16(ptr %x) {4987; CHECK-LABEL: vreduce_umax_v32i16:4988; CHECK: # %bb.0:4989; CHECK-NEXT: li a1, 324990; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma4991; CHECK-NEXT: vle16.v v8, (a0)4992; CHECK-NEXT: vredmaxu.vs v8, v8, v84993; CHECK-NEXT: vmv.x.s a0, v84994; CHECK-NEXT: ret4995 %v = load <32 x i16>, ptr %x4996 %red = call i16 @llvm.vector.reduce.umax.v32i16(<32 x i16> %v)4997 ret i16 %red4998}4999 5000define i16 @vreduce_umax_v64i16(ptr %x) {5001; CHECK-LABEL: vreduce_umax_v64i16:5002; CHECK: # %bb.0:5003; CHECK-NEXT: li a1, 645004; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma5005; CHECK-NEXT: vle16.v v8, (a0)5006; CHECK-NEXT: vredmaxu.vs v8, v8, v85007; CHECK-NEXT: vmv.x.s a0, v85008; CHECK-NEXT: ret5009 %v = load <64 x i16>, ptr %x5010 %red = call i16 @llvm.vector.reduce.umax.v64i16(<64 x i16> %v)5011 ret i16 %red5012}5013 5014define i16 @vreduce_umax_v128i16(ptr %x) {5015; CHECK-LABEL: vreduce_umax_v128i16:5016; CHECK: # %bb.0:5017; CHECK-NEXT: li a1, 645018; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma5019; CHECK-NEXT: vle16.v v8, (a0)5020; CHECK-NEXT: addi a0, a0, 1285021; CHECK-NEXT: vle16.v v16, (a0)5022; CHECK-NEXT: vmaxu.vv v8, v8, v165023; CHECK-NEXT: vredmaxu.vs v8, v8, v85024; CHECK-NEXT: vmv.x.s a0, v85025; CHECK-NEXT: ret5026 %v = load <128 x i16>, ptr %x5027 %red = call i16 @llvm.vector.reduce.umax.v128i16(<128 x i16> %v)5028 ret i16 %red5029}5030 5031define i32 @vreduce_umax_v1i32(<1 x i32> %v) {5032; CHECK-LABEL: vreduce_umax_v1i32:5033; CHECK: # %bb.0:5034; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma5035; CHECK-NEXT: vmv.x.s a0, v85036; CHECK-NEXT: ret5037 %red = call i32 @llvm.vector.reduce.umax.v1i32(<1 x i32> %v)5038 ret i32 %red5039}5040 5041define i32 @vreduce_umax_v2i32(ptr %x) {5042; CHECK-LABEL: vreduce_umax_v2i32:5043; CHECK: # %bb.0:5044; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma5045; CHECK-NEXT: vle32.v v8, (a0)5046; CHECK-NEXT: vredmaxu.vs v8, v8, v85047; CHECK-NEXT: vmv.x.s a0, v85048; CHECK-NEXT: ret5049 %v = load <2 x i32>, ptr %x5050 %red = call i32 @llvm.vector.reduce.umax.v2i32(<2 x i32> %v)5051 ret i32 %red5052}5053 5054define i32 @vreduce_umax_v4i32(ptr %x) {5055; CHECK-LABEL: vreduce_umax_v4i32:5056; CHECK: # %bb.0:5057; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma5058; CHECK-NEXT: vle32.v v8, (a0)5059; CHECK-NEXT: vredmaxu.vs v8, v8, v85060; CHECK-NEXT: vmv.x.s a0, v85061; CHECK-NEXT: ret5062 %v = load <4 x i32>, ptr %x5063 %red = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> %v)5064 ret i32 %red5065}5066 5067define i32 @vreduce_umax_v8i32(ptr %x) {5068; CHECK-LABEL: vreduce_umax_v8i32:5069; CHECK: # %bb.0:5070; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma5071; CHECK-NEXT: vle32.v v8, (a0)5072; CHECK-NEXT: vredmaxu.vs v8, v8, v85073; CHECK-NEXT: vmv.x.s a0, v85074; CHECK-NEXT: ret5075 %v = load <8 x i32>, ptr %x5076 %red = call i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> %v)5077 ret i32 %red5078}5079 5080define i32 @vreduce_umax_v16i32(ptr %x) {5081; CHECK-LABEL: vreduce_umax_v16i32:5082; CHECK: # %bb.0:5083; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma5084; CHECK-NEXT: vle32.v v8, (a0)5085; CHECK-NEXT: vredmaxu.vs v8, v8, v85086; CHECK-NEXT: vmv.x.s a0, v85087; CHECK-NEXT: ret5088 %v = load <16 x i32>, ptr %x5089 %red = call i32 @llvm.vector.reduce.umax.v16i32(<16 x i32> %v)5090 ret i32 %red5091}5092 5093define i32 @vreduce_umax_v32i32(ptr %x) {5094; CHECK-LABEL: vreduce_umax_v32i32:5095; CHECK: # %bb.0:5096; CHECK-NEXT: li a1, 325097; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma5098; CHECK-NEXT: vle32.v v8, (a0)5099; CHECK-NEXT: vredmaxu.vs v8, v8, v85100; CHECK-NEXT: vmv.x.s a0, v85101; CHECK-NEXT: ret5102 %v = load <32 x i32>, ptr %x5103 %red = call i32 @llvm.vector.reduce.umax.v32i32(<32 x i32> %v)5104 ret i32 %red5105}5106 5107define i32 @vreduce_umax_v64i32(ptr %x) {5108; CHECK-LABEL: vreduce_umax_v64i32:5109; CHECK: # %bb.0:5110; CHECK-NEXT: li a1, 325111; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma5112; CHECK-NEXT: vle32.v v8, (a0)5113; CHECK-NEXT: addi a0, a0, 1285114; CHECK-NEXT: vle32.v v16, (a0)5115; CHECK-NEXT: vmaxu.vv v8, v8, v165116; CHECK-NEXT: vredmaxu.vs v8, v8, v85117; CHECK-NEXT: vmv.x.s a0, v85118; CHECK-NEXT: ret5119 %v = load <64 x i32>, ptr %x5120 %red = call i32 @llvm.vector.reduce.umax.v64i32(<64 x i32> %v)5121 ret i32 %red5122}5123 5124define i64 @vreduce_umax_v1i64(<1 x i64> %v) {5125; RV32-LABEL: vreduce_umax_v1i64:5126; RV32: # %bb.0:5127; RV32-NEXT: li a0, 325128; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma5129; RV32-NEXT: vsrl.vx v9, v8, a05130; RV32-NEXT: vmv.x.s a1, v95131; RV32-NEXT: vmv.x.s a0, v85132; RV32-NEXT: ret5133;5134; RV64-LABEL: vreduce_umax_v1i64:5135; RV64: # %bb.0:5136; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma5137; RV64-NEXT: vmv.x.s a0, v85138; RV64-NEXT: ret5139 %red = call i64 @llvm.vector.reduce.umax.v1i64(<1 x i64> %v)5140 ret i64 %red5141}5142 5143define i64 @vreduce_umax_v2i64(ptr %x) {5144; RV32-LABEL: vreduce_umax_v2i64:5145; RV32: # %bb.0:5146; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma5147; RV32-NEXT: vle64.v v8, (a0)5148; RV32-NEXT: li a0, 325149; RV32-NEXT: vredmaxu.vs v8, v8, v85150; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma5151; RV32-NEXT: vsrl.vx v9, v8, a05152; RV32-NEXT: vmv.x.s a1, v95153; RV32-NEXT: vmv.x.s a0, v85154; RV32-NEXT: ret5155;5156; RV64-LABEL: vreduce_umax_v2i64:5157; RV64: # %bb.0:5158; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma5159; RV64-NEXT: vle64.v v8, (a0)5160; RV64-NEXT: vredmaxu.vs v8, v8, v85161; RV64-NEXT: vmv.x.s a0, v85162; RV64-NEXT: ret5163 %v = load <2 x i64>, ptr %x5164 %red = call i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> %v)5165 ret i64 %red5166}5167 5168define i64 @vreduce_umax_v4i64(ptr %x) {5169; RV32-LABEL: vreduce_umax_v4i64:5170; RV32: # %bb.0:5171; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma5172; RV32-NEXT: vle64.v v8, (a0)5173; RV32-NEXT: li a1, 325174; RV32-NEXT: vredmaxu.vs v8, v8, v85175; RV32-NEXT: vmv.x.s a0, v85176; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma5177; RV32-NEXT: vsrl.vx v8, v8, a15178; RV32-NEXT: vmv.x.s a1, v85179; RV32-NEXT: ret5180;5181; RV64-LABEL: vreduce_umax_v4i64:5182; RV64: # %bb.0:5183; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma5184; RV64-NEXT: vle64.v v8, (a0)5185; RV64-NEXT: vredmaxu.vs v8, v8, v85186; RV64-NEXT: vmv.x.s a0, v85187; RV64-NEXT: ret5188 %v = load <4 x i64>, ptr %x5189 %red = call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> %v)5190 ret i64 %red5191}5192 5193define i64 @vreduce_umax_v8i64(ptr %x) {5194; RV32-LABEL: vreduce_umax_v8i64:5195; RV32: # %bb.0:5196; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma5197; RV32-NEXT: vle64.v v8, (a0)5198; RV32-NEXT: li a1, 325199; RV32-NEXT: vredmaxu.vs v8, v8, v85200; RV32-NEXT: vmv.x.s a0, v85201; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma5202; RV32-NEXT: vsrl.vx v8, v8, a15203; RV32-NEXT: vmv.x.s a1, v85204; RV32-NEXT: ret5205;5206; RV64-LABEL: vreduce_umax_v8i64:5207; RV64: # %bb.0:5208; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma5209; RV64-NEXT: vle64.v v8, (a0)5210; RV64-NEXT: vredmaxu.vs v8, v8, v85211; RV64-NEXT: vmv.x.s a0, v85212; RV64-NEXT: ret5213 %v = load <8 x i64>, ptr %x5214 %red = call i64 @llvm.vector.reduce.umax.v8i64(<8 x i64> %v)5215 ret i64 %red5216}5217 5218define i64 @vreduce_umax_v16i64(ptr %x) {5219; RV32-LABEL: vreduce_umax_v16i64:5220; RV32: # %bb.0:5221; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma5222; RV32-NEXT: vle64.v v8, (a0)5223; RV32-NEXT: li a1, 325224; RV32-NEXT: vredmaxu.vs v8, v8, v85225; RV32-NEXT: vmv.x.s a0, v85226; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma5227; RV32-NEXT: vsrl.vx v8, v8, a15228; RV32-NEXT: vmv.x.s a1, v85229; RV32-NEXT: ret5230;5231; RV64-LABEL: vreduce_umax_v16i64:5232; RV64: # %bb.0:5233; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma5234; RV64-NEXT: vle64.v v8, (a0)5235; RV64-NEXT: vredmaxu.vs v8, v8, v85236; RV64-NEXT: vmv.x.s a0, v85237; RV64-NEXT: ret5238 %v = load <16 x i64>, ptr %x5239 %red = call i64 @llvm.vector.reduce.umax.v16i64(<16 x i64> %v)5240 ret i64 %red5241}5242 5243define i64 @vreduce_umax_v32i64(ptr %x) {5244; RV32-LABEL: vreduce_umax_v32i64:5245; RV32: # %bb.0:5246; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma5247; RV32-NEXT: vle64.v v8, (a0)5248; RV32-NEXT: addi a0, a0, 1285249; RV32-NEXT: vle64.v v16, (a0)5250; RV32-NEXT: li a1, 325251; RV32-NEXT: vmaxu.vv v8, v8, v165252; RV32-NEXT: vredmaxu.vs v8, v8, v85253; RV32-NEXT: vmv.x.s a0, v85254; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma5255; RV32-NEXT: vsrl.vx v8, v8, a15256; RV32-NEXT: vmv.x.s a1, v85257; RV32-NEXT: ret5258;5259; RV64-LABEL: vreduce_umax_v32i64:5260; RV64: # %bb.0:5261; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma5262; RV64-NEXT: vle64.v v8, (a0)5263; RV64-NEXT: addi a0, a0, 1285264; RV64-NEXT: vle64.v v16, (a0)5265; RV64-NEXT: vmaxu.vv v8, v8, v165266; RV64-NEXT: vredmaxu.vs v8, v8, v85267; RV64-NEXT: vmv.x.s a0, v85268; RV64-NEXT: ret5269 %v = load <32 x i64>, ptr %x5270 %red = call i64 @llvm.vector.reduce.umax.v32i64(<32 x i64> %v)5271 ret i64 %red5272}5273 5274define i64 @vreduce_umax_v64i64(ptr %x) nounwind {5275; RV32-LABEL: vreduce_umax_v64i64:5276; RV32: # %bb.0:5277; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma5278; RV32-NEXT: vle64.v v8, (a0)5279; RV32-NEXT: addi a1, a0, 3845280; RV32-NEXT: vle64.v v16, (a1)5281; RV32-NEXT: addi a1, a0, 2565282; RV32-NEXT: addi a0, a0, 1285283; RV32-NEXT: vle64.v v0, (a0)5284; RV32-NEXT: vle64.v v24, (a1)5285; RV32-NEXT: li a1, 325286; RV32-NEXT: vmaxu.vv v16, v0, v165287; RV32-NEXT: vmaxu.vv v8, v8, v245288; RV32-NEXT: vmaxu.vv v8, v8, v165289; RV32-NEXT: vredmaxu.vs v8, v8, v85290; RV32-NEXT: vmv.x.s a0, v85291; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma5292; RV32-NEXT: vsrl.vx v8, v8, a15293; RV32-NEXT: vmv.x.s a1, v85294; RV32-NEXT: ret5295;5296; RV64-LABEL: vreduce_umax_v64i64:5297; RV64: # %bb.0:5298; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma5299; RV64-NEXT: vle64.v v8, (a0)5300; RV64-NEXT: addi a1, a0, 3845301; RV64-NEXT: vle64.v v16, (a1)5302; RV64-NEXT: addi a1, a0, 2565303; RV64-NEXT: addi a0, a0, 1285304; RV64-NEXT: vle64.v v24, (a0)5305; RV64-NEXT: vle64.v v0, (a1)5306; RV64-NEXT: vmaxu.vv v16, v24, v165307; RV64-NEXT: vmaxu.vv v8, v8, v05308; RV64-NEXT: vmaxu.vv v8, v8, v165309; RV64-NEXT: vredmaxu.vs v8, v8, v85310; RV64-NEXT: vmv.x.s a0, v85311; RV64-NEXT: ret5312 %v = load <64 x i64>, ptr %x5313 %red = call i64 @llvm.vector.reduce.umax.v64i64(<64 x i64> %v)5314 ret i64 %red5315}5316 5317define i8 @vreduce_mul_v1i8(<1 x i8> %v) {5318; CHECK-LABEL: vreduce_mul_v1i8:5319; CHECK: # %bb.0:5320; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma5321; CHECK-NEXT: vmv.x.s a0, v85322; CHECK-NEXT: ret5323 %red = call i8 @llvm.vector.reduce.mul.v1i8(<1 x i8> %v)5324 ret i8 %red5325}5326 5327define i8 @vreduce_mul_v2i8(ptr %x) {5328; CHECK-LABEL: vreduce_mul_v2i8:5329; CHECK: # %bb.0:5330; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma5331; CHECK-NEXT: vle8.v v8, (a0)5332; CHECK-NEXT: lbu a0, 1(a0)5333; CHECK-NEXT: vmul.vx v8, v8, a05334; CHECK-NEXT: vmv.x.s a0, v85335; CHECK-NEXT: ret5336 %v = load <2 x i8>, ptr %x5337 %red = call i8 @llvm.vector.reduce.mul.v2i8(<2 x i8> %v)5338 ret i8 %red5339}5340 5341define i8 @vreduce_mul_v3i8(ptr %x) {5342; CHECK-LABEL: vreduce_mul_v3i8:5343; CHECK: # %bb.0:5344; CHECK-NEXT: vsetivli zero, 3, e8, mf4, ta, ma5345; CHECK-NEXT: vle8.v v8, (a0)5346; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma5347; CHECK-NEXT: vmv.v.i v9, 15348; CHECK-NEXT: vslideup.vi v8, v9, 35349; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma5350; CHECK-NEXT: vslidedown.vi v9, v8, 25351; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma5352; CHECK-NEXT: vmul.vv v8, v8, v95353; CHECK-NEXT: vslidedown.vi v9, v8, 15354; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma5355; CHECK-NEXT: vmul.vv v8, v8, v95356; CHECK-NEXT: vmv.x.s a0, v85357; CHECK-NEXT: ret5358 %v = load <3 x i8>, ptr %x5359 %red = call i8 @llvm.vector.reduce.mul.v3i8(<3 x i8> %v)5360 ret i8 %red5361}5362 5363define i8 @vreduce_mul_v4i8(ptr %x) {5364; CHECK-LABEL: vreduce_mul_v4i8:5365; CHECK: # %bb.0:5366; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma5367; CHECK-NEXT: vle8.v v8, (a0)5368; CHECK-NEXT: vslidedown.vi v9, v8, 25369; CHECK-NEXT: vmul.vv v8, v8, v95370; CHECK-NEXT: vrgather.vi v9, v8, 15371; CHECK-NEXT: vmul.vv v8, v8, v95372; CHECK-NEXT: vmv.x.s a0, v85373; CHECK-NEXT: ret5374 %v = load <4 x i8>, ptr %x5375 %red = call i8 @llvm.vector.reduce.mul.v4i8(<4 x i8> %v)5376 ret i8 %red5377}5378 5379define i8 @vreduce_mul_v8i8(ptr %x) {5380; CHECK-LABEL: vreduce_mul_v8i8:5381; CHECK: # %bb.0:5382; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma5383; CHECK-NEXT: vle8.v v8, (a0)5384; CHECK-NEXT: vslidedown.vi v9, v8, 45385; CHECK-NEXT: vmul.vv v8, v8, v95386; CHECK-NEXT: vslidedown.vi v9, v8, 25387; CHECK-NEXT: vmul.vv v8, v8, v95388; CHECK-NEXT: vrgather.vi v9, v8, 15389; CHECK-NEXT: vmul.vv v8, v8, v95390; CHECK-NEXT: vmv.x.s a0, v85391; CHECK-NEXT: ret5392 %v = load <8 x i8>, ptr %x5393 %red = call i8 @llvm.vector.reduce.mul.v8i8(<8 x i8> %v)5394 ret i8 %red5395}5396 5397define i8 @vreduce_mul_v16i8(ptr %x) {5398; CHECK-LABEL: vreduce_mul_v16i8:5399; CHECK: # %bb.0:5400; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma5401; CHECK-NEXT: vle8.v v8, (a0)5402; CHECK-NEXT: vslidedown.vi v9, v8, 85403; CHECK-NEXT: vmul.vv v8, v8, v95404; CHECK-NEXT: vslidedown.vi v9, v8, 45405; CHECK-NEXT: vmul.vv v8, v8, v95406; CHECK-NEXT: vslidedown.vi v9, v8, 25407; CHECK-NEXT: vmul.vv v8, v8, v95408; CHECK-NEXT: vrgather.vi v9, v8, 15409; CHECK-NEXT: vmul.vv v8, v8, v95410; CHECK-NEXT: vmv.x.s a0, v85411; CHECK-NEXT: ret5412 %v = load <16 x i8>, ptr %x5413 %red = call i8 @llvm.vector.reduce.mul.v16i8(<16 x i8> %v)5414 ret i8 %red5415}5416 5417define i8 @vreduce_mul_v32i8(ptr %x) {5418; CHECK-LABEL: vreduce_mul_v32i8:5419; CHECK: # %bb.0:5420; CHECK-NEXT: li a1, 325421; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma5422; CHECK-NEXT: vle8.v v8, (a0)5423; CHECK-NEXT: vslidedown.vi v10, v8, 165424; CHECK-NEXT: vmul.vv v8, v8, v105425; CHECK-NEXT: vslidedown.vi v10, v8, 85426; CHECK-NEXT: vmul.vv v8, v8, v105427; CHECK-NEXT: vslidedown.vi v10, v8, 45428; CHECK-NEXT: vmul.vv v8, v8, v105429; CHECK-NEXT: vslidedown.vi v10, v8, 25430; CHECK-NEXT: vmul.vv v8, v8, v105431; CHECK-NEXT: vrgather.vi v10, v8, 15432; CHECK-NEXT: vmul.vv v8, v8, v105433; CHECK-NEXT: vmv.x.s a0, v85434; CHECK-NEXT: ret5435 %v = load <32 x i8>, ptr %x5436 %red = call i8 @llvm.vector.reduce.mul.v32i8(<32 x i8> %v)5437 ret i8 %red5438}5439 5440define i8 @vreduce_mul_v64i8(ptr %x) {5441; CHECK-LABEL: vreduce_mul_v64i8:5442; CHECK: # %bb.0:5443; CHECK-NEXT: li a1, 645444; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma5445; CHECK-NEXT: vle8.v v8, (a0)5446; CHECK-NEXT: li a0, 325447; CHECK-NEXT: vslidedown.vx v12, v8, a05448; CHECK-NEXT: vmul.vv v8, v8, v125449; CHECK-NEXT: vslidedown.vi v12, v8, 165450; CHECK-NEXT: vmul.vv v8, v8, v125451; CHECK-NEXT: vslidedown.vi v12, v8, 85452; CHECK-NEXT: vmul.vv v8, v8, v125453; CHECK-NEXT: vslidedown.vi v12, v8, 45454; CHECK-NEXT: vmul.vv v8, v8, v125455; CHECK-NEXT: vslidedown.vi v12, v8, 25456; CHECK-NEXT: vmul.vv v8, v8, v125457; CHECK-NEXT: vrgather.vi v12, v8, 15458; CHECK-NEXT: vmul.vv v8, v8, v125459; CHECK-NEXT: vmv.x.s a0, v85460; CHECK-NEXT: ret5461 %v = load <64 x i8>, ptr %x5462 %red = call i8 @llvm.vector.reduce.mul.v64i8(<64 x i8> %v)5463 ret i8 %red5464}5465 5466define i8 @vreduce_mul_v128i8(ptr %x) {5467; CHECK-LABEL: vreduce_mul_v128i8:5468; CHECK: # %bb.0:5469; CHECK-NEXT: li a1, 1285470; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma5471; CHECK-NEXT: vle8.v v8, (a0)5472; CHECK-NEXT: li a0, 645473; CHECK-NEXT: vslidedown.vx v16, v8, a05474; CHECK-NEXT: vmul.vv v8, v8, v165475; CHECK-NEXT: li a0, 325476; CHECK-NEXT: vslidedown.vx v16, v8, a05477; CHECK-NEXT: vmul.vv v8, v8, v165478; CHECK-NEXT: vslidedown.vi v16, v8, 165479; CHECK-NEXT: vmul.vv v8, v8, v165480; CHECK-NEXT: vslidedown.vi v16, v8, 85481; CHECK-NEXT: vmul.vv v8, v8, v165482; CHECK-NEXT: vslidedown.vi v16, v8, 45483; CHECK-NEXT: vmul.vv v8, v8, v165484; CHECK-NEXT: vslidedown.vi v16, v8, 25485; CHECK-NEXT: vmul.vv v8, v8, v165486; CHECK-NEXT: vrgather.vi v16, v8, 15487; CHECK-NEXT: vmul.vv v8, v8, v165488; CHECK-NEXT: vmv.x.s a0, v85489; CHECK-NEXT: ret5490 %v = load <128 x i8>, ptr %x5491 %red = call i8 @llvm.vector.reduce.mul.v128i8(<128 x i8> %v)5492 ret i8 %red5493}5494 5495define i8 @vreduce_mul_v256i8(ptr %x) {5496; CHECK-LABEL: vreduce_mul_v256i8:5497; CHECK: # %bb.0:5498; CHECK-NEXT: li a1, 1285499; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma5500; CHECK-NEXT: vle8.v v8, (a0)5501; CHECK-NEXT: addi a0, a0, 1285502; CHECK-NEXT: vle8.v v16, (a0)5503; CHECK-NEXT: li a0, 645504; CHECK-NEXT: vmul.vv v8, v8, v165505; CHECK-NEXT: vslidedown.vx v16, v8, a05506; CHECK-NEXT: vmul.vv v8, v8, v165507; CHECK-NEXT: li a0, 325508; CHECK-NEXT: vslidedown.vx v16, v8, a05509; CHECK-NEXT: vmul.vv v8, v8, v165510; CHECK-NEXT: vslidedown.vi v16, v8, 165511; CHECK-NEXT: vmul.vv v8, v8, v165512; CHECK-NEXT: vslidedown.vi v16, v8, 85513; CHECK-NEXT: vmul.vv v8, v8, v165514; CHECK-NEXT: vslidedown.vi v16, v8, 45515; CHECK-NEXT: vmul.vv v8, v8, v165516; CHECK-NEXT: vslidedown.vi v16, v8, 25517; CHECK-NEXT: vmul.vv v8, v8, v165518; CHECK-NEXT: vrgather.vi v16, v8, 15519; CHECK-NEXT: vmul.vv v8, v8, v165520; CHECK-NEXT: vmv.x.s a0, v85521; CHECK-NEXT: ret5522 %v = load <256 x i8>, ptr %x5523 %red = call i8 @llvm.vector.reduce.mul.v256i8(<256 x i8> %v)5524 ret i8 %red5525}5526 5527define i16 @vreduce_mul_v1i16(<1 x i16> %v) {5528; CHECK-LABEL: vreduce_mul_v1i16:5529; CHECK: # %bb.0:5530; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma5531; CHECK-NEXT: vmv.x.s a0, v85532; CHECK-NEXT: ret5533 %red = call i16 @llvm.vector.reduce.mul.v1i16(<1 x i16> %v)5534 ret i16 %red5535}5536 5537define i16 @vreduce_mul_v2i16(ptr %x) {5538; CHECK-LABEL: vreduce_mul_v2i16:5539; CHECK: # %bb.0:5540; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma5541; CHECK-NEXT: vle16.v v8, (a0)5542; CHECK-NEXT: lh a0, 2(a0)5543; CHECK-NEXT: vmul.vx v8, v8, a05544; CHECK-NEXT: vmv.x.s a0, v85545; CHECK-NEXT: ret5546 %v = load <2 x i16>, ptr %x5547 %red = call i16 @llvm.vector.reduce.mul.v2i16(<2 x i16> %v)5548 ret i16 %red5549}5550 5551define i16 @vreduce_mul_v4i16(ptr %x) {5552; CHECK-LABEL: vreduce_mul_v4i16:5553; CHECK: # %bb.0:5554; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma5555; CHECK-NEXT: vle16.v v8, (a0)5556; CHECK-NEXT: vslidedown.vi v9, v8, 25557; CHECK-NEXT: vmul.vv v8, v8, v95558; CHECK-NEXT: vrgather.vi v9, v8, 15559; CHECK-NEXT: vmul.vv v8, v8, v95560; CHECK-NEXT: vmv.x.s a0, v85561; CHECK-NEXT: ret5562 %v = load <4 x i16>, ptr %x5563 %red = call i16 @llvm.vector.reduce.mul.v4i16(<4 x i16> %v)5564 ret i16 %red5565}5566 5567define i16 @vreduce_mul_v8i16(ptr %x) {5568; CHECK-LABEL: vreduce_mul_v8i16:5569; CHECK: # %bb.0:5570; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma5571; CHECK-NEXT: vle16.v v8, (a0)5572; CHECK-NEXT: vslidedown.vi v9, v8, 45573; CHECK-NEXT: vmul.vv v8, v8, v95574; CHECK-NEXT: vslidedown.vi v9, v8, 25575; CHECK-NEXT: vmul.vv v8, v8, v95576; CHECK-NEXT: vrgather.vi v9, v8, 15577; CHECK-NEXT: vmul.vv v8, v8, v95578; CHECK-NEXT: vmv.x.s a0, v85579; CHECK-NEXT: ret5580 %v = load <8 x i16>, ptr %x5581 %red = call i16 @llvm.vector.reduce.mul.v8i16(<8 x i16> %v)5582 ret i16 %red5583}5584 5585define i16 @vreduce_mul_v16i16(ptr %x) {5586; CHECK-LABEL: vreduce_mul_v16i16:5587; CHECK: # %bb.0:5588; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma5589; CHECK-NEXT: vle16.v v8, (a0)5590; CHECK-NEXT: vslidedown.vi v10, v8, 85591; CHECK-NEXT: vmul.vv v8, v8, v105592; CHECK-NEXT: vslidedown.vi v10, v8, 45593; CHECK-NEXT: vmul.vv v8, v8, v105594; CHECK-NEXT: vslidedown.vi v10, v8, 25595; CHECK-NEXT: vmul.vv v8, v8, v105596; CHECK-NEXT: vrgather.vi v10, v8, 15597; CHECK-NEXT: vmul.vv v8, v8, v105598; CHECK-NEXT: vmv.x.s a0, v85599; CHECK-NEXT: ret5600 %v = load <16 x i16>, ptr %x5601 %red = call i16 @llvm.vector.reduce.mul.v16i16(<16 x i16> %v)5602 ret i16 %red5603}5604 5605define i16 @vreduce_mul_v32i16(ptr %x) {5606; CHECK-LABEL: vreduce_mul_v32i16:5607; CHECK: # %bb.0:5608; CHECK-NEXT: li a1, 325609; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma5610; CHECK-NEXT: vle16.v v8, (a0)5611; CHECK-NEXT: vslidedown.vi v12, v8, 165612; CHECK-NEXT: vmul.vv v8, v8, v125613; CHECK-NEXT: vslidedown.vi v12, v8, 85614; CHECK-NEXT: vmul.vv v8, v8, v125615; CHECK-NEXT: vslidedown.vi v12, v8, 45616; CHECK-NEXT: vmul.vv v8, v8, v125617; CHECK-NEXT: vslidedown.vi v12, v8, 25618; CHECK-NEXT: vmul.vv v8, v8, v125619; CHECK-NEXT: vrgather.vi v12, v8, 15620; CHECK-NEXT: vmul.vv v8, v8, v125621; CHECK-NEXT: vmv.x.s a0, v85622; CHECK-NEXT: ret5623 %v = load <32 x i16>, ptr %x5624 %red = call i16 @llvm.vector.reduce.mul.v32i16(<32 x i16> %v)5625 ret i16 %red5626}5627 5628define i16 @vreduce_mul_v64i16(ptr %x) {5629; CHECK-LABEL: vreduce_mul_v64i16:5630; CHECK: # %bb.0:5631; CHECK-NEXT: li a1, 645632; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma5633; CHECK-NEXT: vle16.v v8, (a0)5634; CHECK-NEXT: li a0, 325635; CHECK-NEXT: vslidedown.vx v16, v8, a05636; CHECK-NEXT: vmul.vv v8, v8, v165637; CHECK-NEXT: vslidedown.vi v16, v8, 165638; CHECK-NEXT: vmul.vv v8, v8, v165639; CHECK-NEXT: vslidedown.vi v16, v8, 85640; CHECK-NEXT: vmul.vv v8, v8, v165641; CHECK-NEXT: vslidedown.vi v16, v8, 45642; CHECK-NEXT: vmul.vv v8, v8, v165643; CHECK-NEXT: vslidedown.vi v16, v8, 25644; CHECK-NEXT: vmul.vv v8, v8, v165645; CHECK-NEXT: vrgather.vi v16, v8, 15646; CHECK-NEXT: vmul.vv v8, v8, v165647; CHECK-NEXT: vmv.x.s a0, v85648; CHECK-NEXT: ret5649 %v = load <64 x i16>, ptr %x5650 %red = call i16 @llvm.vector.reduce.mul.v64i16(<64 x i16> %v)5651 ret i16 %red5652}5653 5654define i16 @vreduce_mul_v128i16(ptr %x) {5655; CHECK-LABEL: vreduce_mul_v128i16:5656; CHECK: # %bb.0:5657; CHECK-NEXT: li a1, 645658; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma5659; CHECK-NEXT: vle16.v v8, (a0)5660; CHECK-NEXT: addi a0, a0, 1285661; CHECK-NEXT: vle16.v v16, (a0)5662; CHECK-NEXT: vmul.vv v8, v8, v165663; CHECK-NEXT: li a0, 325664; CHECK-NEXT: vslidedown.vx v16, v8, a05665; CHECK-NEXT: vmul.vv v8, v8, v165666; CHECK-NEXT: vslidedown.vi v16, v8, 165667; CHECK-NEXT: vmul.vv v8, v8, v165668; CHECK-NEXT: vslidedown.vi v16, v8, 85669; CHECK-NEXT: vmul.vv v8, v8, v165670; CHECK-NEXT: vslidedown.vi v16, v8, 45671; CHECK-NEXT: vmul.vv v8, v8, v165672; CHECK-NEXT: vslidedown.vi v16, v8, 25673; CHECK-NEXT: vmul.vv v8, v8, v165674; CHECK-NEXT: vrgather.vi v16, v8, 15675; CHECK-NEXT: vmul.vv v8, v8, v165676; CHECK-NEXT: vmv.x.s a0, v85677; CHECK-NEXT: ret5678 %v = load <128 x i16>, ptr %x5679 %red = call i16 @llvm.vector.reduce.mul.v128i16(<128 x i16> %v)5680 ret i16 %red5681}5682 5683define i32 @vreduce_mul_v1i32(<1 x i32> %v) {5684; CHECK-LABEL: vreduce_mul_v1i32:5685; CHECK: # %bb.0:5686; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma5687; CHECK-NEXT: vmv.x.s a0, v85688; CHECK-NEXT: ret5689 %red = call i32 @llvm.vector.reduce.mul.v1i32(<1 x i32> %v)5690 ret i32 %red5691}5692 5693define i32 @vreduce_mul_v2i32(ptr %x) {5694; CHECK-LABEL: vreduce_mul_v2i32:5695; CHECK: # %bb.0:5696; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma5697; CHECK-NEXT: vle32.v v8, (a0)5698; CHECK-NEXT: lw a0, 4(a0)5699; CHECK-NEXT: vmul.vx v8, v8, a05700; CHECK-NEXT: vmv.x.s a0, v85701; CHECK-NEXT: ret5702 %v = load <2 x i32>, ptr %x5703 %red = call i32 @llvm.vector.reduce.mul.v2i32(<2 x i32> %v)5704 ret i32 %red5705}5706 5707define i32 @vreduce_mul_v4i32(ptr %x) {5708; CHECK-LABEL: vreduce_mul_v4i32:5709; CHECK: # %bb.0:5710; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma5711; CHECK-NEXT: vle32.v v8, (a0)5712; CHECK-NEXT: vslidedown.vi v9, v8, 25713; CHECK-NEXT: vmul.vv v8, v8, v95714; CHECK-NEXT: vrgather.vi v9, v8, 15715; CHECK-NEXT: vmul.vv v8, v8, v95716; CHECK-NEXT: vmv.x.s a0, v85717; CHECK-NEXT: ret5718 %v = load <4 x i32>, ptr %x5719 %red = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> %v)5720 ret i32 %red5721}5722 5723define i32 @vreduce_mul_v8i32(ptr %x) {5724; CHECK-LABEL: vreduce_mul_v8i32:5725; CHECK: # %bb.0:5726; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma5727; CHECK-NEXT: vle32.v v8, (a0)5728; CHECK-NEXT: vslidedown.vi v10, v8, 45729; CHECK-NEXT: vmul.vv v8, v8, v105730; CHECK-NEXT: vslidedown.vi v10, v8, 25731; CHECK-NEXT: vmul.vv v8, v8, v105732; CHECK-NEXT: vrgather.vi v10, v8, 15733; CHECK-NEXT: vmul.vv v8, v8, v105734; CHECK-NEXT: vmv.x.s a0, v85735; CHECK-NEXT: ret5736 %v = load <8 x i32>, ptr %x5737 %red = call i32 @llvm.vector.reduce.mul.v8i32(<8 x i32> %v)5738 ret i32 %red5739}5740 5741define i32 @vreduce_mul_v16i32(ptr %x) {5742; CHECK-LABEL: vreduce_mul_v16i32:5743; CHECK: # %bb.0:5744; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma5745; CHECK-NEXT: vle32.v v8, (a0)5746; CHECK-NEXT: vslidedown.vi v12, v8, 85747; CHECK-NEXT: vmul.vv v8, v8, v125748; CHECK-NEXT: vslidedown.vi v12, v8, 45749; CHECK-NEXT: vmul.vv v8, v8, v125750; CHECK-NEXT: vslidedown.vi v12, v8, 25751; CHECK-NEXT: vmul.vv v8, v8, v125752; CHECK-NEXT: vrgather.vi v12, v8, 15753; CHECK-NEXT: vmul.vv v8, v8, v125754; CHECK-NEXT: vmv.x.s a0, v85755; CHECK-NEXT: ret5756 %v = load <16 x i32>, ptr %x5757 %red = call i32 @llvm.vector.reduce.mul.v16i32(<16 x i32> %v)5758 ret i32 %red5759}5760 5761define i32 @vreduce_mul_v32i32(ptr %x) {5762; CHECK-LABEL: vreduce_mul_v32i32:5763; CHECK: # %bb.0:5764; CHECK-NEXT: li a1, 325765; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma5766; CHECK-NEXT: vle32.v v8, (a0)5767; CHECK-NEXT: vslidedown.vi v16, v8, 165768; CHECK-NEXT: vmul.vv v8, v8, v165769; CHECK-NEXT: vslidedown.vi v16, v8, 85770; CHECK-NEXT: vmul.vv v8, v8, v165771; CHECK-NEXT: vslidedown.vi v16, v8, 45772; CHECK-NEXT: vmul.vv v8, v8, v165773; CHECK-NEXT: vslidedown.vi v16, v8, 25774; CHECK-NEXT: vmul.vv v8, v8, v165775; CHECK-NEXT: vrgather.vi v16, v8, 15776; CHECK-NEXT: vmul.vv v8, v8, v165777; CHECK-NEXT: vmv.x.s a0, v85778; CHECK-NEXT: ret5779 %v = load <32 x i32>, ptr %x5780 %red = call i32 @llvm.vector.reduce.mul.v32i32(<32 x i32> %v)5781 ret i32 %red5782}5783 5784define i32 @vreduce_mul_v64i32(ptr %x) {5785; CHECK-LABEL: vreduce_mul_v64i32:5786; CHECK: # %bb.0:5787; CHECK-NEXT: li a1, 325788; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma5789; CHECK-NEXT: vle32.v v8, (a0)5790; CHECK-NEXT: addi a0, a0, 1285791; CHECK-NEXT: vle32.v v16, (a0)5792; CHECK-NEXT: vmul.vv v8, v8, v165793; CHECK-NEXT: vslidedown.vi v16, v8, 165794; CHECK-NEXT: vmul.vv v8, v8, v165795; CHECK-NEXT: vslidedown.vi v16, v8, 85796; CHECK-NEXT: vmul.vv v8, v8, v165797; CHECK-NEXT: vslidedown.vi v16, v8, 45798; CHECK-NEXT: vmul.vv v8, v8, v165799; CHECK-NEXT: vslidedown.vi v16, v8, 25800; CHECK-NEXT: vmul.vv v8, v8, v165801; CHECK-NEXT: vrgather.vi v16, v8, 15802; CHECK-NEXT: vmul.vv v8, v8, v165803; CHECK-NEXT: vmv.x.s a0, v85804; CHECK-NEXT: ret5805 %v = load <64 x i32>, ptr %x5806 %red = call i32 @llvm.vector.reduce.mul.v64i32(<64 x i32> %v)5807 ret i32 %red5808}5809 5810define i64 @vreduce_mul_v1i64(<1 x i64> %v) {5811; RV32-LABEL: vreduce_mul_v1i64:5812; RV32: # %bb.0:5813; RV32-NEXT: li a0, 325814; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma5815; RV32-NEXT: vsrl.vx v9, v8, a05816; RV32-NEXT: vmv.x.s a1, v95817; RV32-NEXT: vmv.x.s a0, v85818; RV32-NEXT: ret5819;5820; RV64-LABEL: vreduce_mul_v1i64:5821; RV64: # %bb.0:5822; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma5823; RV64-NEXT: vmv.x.s a0, v85824; RV64-NEXT: ret5825 %red = call i64 @llvm.vector.reduce.mul.v1i64(<1 x i64> %v)5826 ret i64 %red5827}5828 5829define i64 @vreduce_mul_v2i64(ptr %x) {5830; RV32-LABEL: vreduce_mul_v2i64:5831; RV32: # %bb.0:5832; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma5833; RV32-NEXT: vle64.v v8, (a0)5834; RV32-NEXT: addi a0, a0, 85835; RV32-NEXT: vlse64.v v9, (a0), zero5836; RV32-NEXT: li a1, 325837; RV32-NEXT: vmul.vv v8, v8, v95838; RV32-NEXT: vmv.x.s a0, v85839; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma5840; RV32-NEXT: vsrl.vx v8, v8, a15841; RV32-NEXT: vmv.x.s a1, v85842; RV32-NEXT: ret5843;5844; RV64-LABEL: vreduce_mul_v2i64:5845; RV64: # %bb.0:5846; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma5847; RV64-NEXT: vle64.v v8, (a0)5848; RV64-NEXT: ld a0, 8(a0)5849; RV64-NEXT: vmul.vx v8, v8, a05850; RV64-NEXT: vmv.x.s a0, v85851; RV64-NEXT: ret5852 %v = load <2 x i64>, ptr %x5853 %red = call i64 @llvm.vector.reduce.mul.v2i64(<2 x i64> %v)5854 ret i64 %red5855}5856 5857define i64 @vreduce_mul_v4i64(ptr %x) {5858; RV32-LABEL: vreduce_mul_v4i64:5859; RV32: # %bb.0:5860; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma5861; RV32-NEXT: vle64.v v8, (a0)5862; RV32-NEXT: li a1, 325863; RV32-NEXT: vslidedown.vi v10, v8, 25864; RV32-NEXT: vmul.vv v8, v8, v105865; RV32-NEXT: vrgather.vi v10, v8, 15866; RV32-NEXT: vmul.vv v8, v8, v105867; RV32-NEXT: vmv.x.s a0, v85868; RV32-NEXT: vsetivli zero, 1, e64, m2, ta, ma5869; RV32-NEXT: vsrl.vx v8, v8, a15870; RV32-NEXT: vmv.x.s a1, v85871; RV32-NEXT: ret5872;5873; RV64-LABEL: vreduce_mul_v4i64:5874; RV64: # %bb.0:5875; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma5876; RV64-NEXT: vle64.v v8, (a0)5877; RV64-NEXT: vslidedown.vi v10, v8, 25878; RV64-NEXT: vmul.vv v8, v8, v105879; RV64-NEXT: vrgather.vi v10, v8, 15880; RV64-NEXT: vmul.vv v8, v8, v105881; RV64-NEXT: vmv.x.s a0, v85882; RV64-NEXT: ret5883 %v = load <4 x i64>, ptr %x5884 %red = call i64 @llvm.vector.reduce.mul.v4i64(<4 x i64> %v)5885 ret i64 %red5886}5887 5888define i64 @vreduce_mul_v8i64(ptr %x) {5889; RV32-LABEL: vreduce_mul_v8i64:5890; RV32: # %bb.0:5891; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma5892; RV32-NEXT: vle64.v v8, (a0)5893; RV32-NEXT: li a1, 325894; RV32-NEXT: vslidedown.vi v12, v8, 45895; RV32-NEXT: vmul.vv v8, v8, v125896; RV32-NEXT: vslidedown.vi v12, v8, 25897; RV32-NEXT: vmul.vv v8, v8, v125898; RV32-NEXT: vrgather.vi v12, v8, 15899; RV32-NEXT: vmul.vv v8, v8, v125900; RV32-NEXT: vmv.x.s a0, v85901; RV32-NEXT: vsetivli zero, 1, e64, m4, ta, ma5902; RV32-NEXT: vsrl.vx v8, v8, a15903; RV32-NEXT: vmv.x.s a1, v85904; RV32-NEXT: ret5905;5906; RV64-LABEL: vreduce_mul_v8i64:5907; RV64: # %bb.0:5908; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma5909; RV64-NEXT: vle64.v v8, (a0)5910; RV64-NEXT: vslidedown.vi v12, v8, 45911; RV64-NEXT: vmul.vv v8, v8, v125912; RV64-NEXT: vslidedown.vi v12, v8, 25913; RV64-NEXT: vmul.vv v8, v8, v125914; RV64-NEXT: vrgather.vi v12, v8, 15915; RV64-NEXT: vmul.vv v8, v8, v125916; RV64-NEXT: vmv.x.s a0, v85917; RV64-NEXT: ret5918 %v = load <8 x i64>, ptr %x5919 %red = call i64 @llvm.vector.reduce.mul.v8i64(<8 x i64> %v)5920 ret i64 %red5921}5922 5923define i64 @vreduce_mul_v16i64(ptr %x) {5924; RV32-LABEL: vreduce_mul_v16i64:5925; RV32: # %bb.0:5926; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma5927; RV32-NEXT: vle64.v v8, (a0)5928; RV32-NEXT: li a1, 325929; RV32-NEXT: vslidedown.vi v16, v8, 85930; RV32-NEXT: vmul.vv v8, v8, v165931; RV32-NEXT: vslidedown.vi v16, v8, 45932; RV32-NEXT: vmul.vv v8, v8, v165933; RV32-NEXT: vslidedown.vi v16, v8, 25934; RV32-NEXT: vmul.vv v8, v8, v165935; RV32-NEXT: vrgather.vi v16, v8, 15936; RV32-NEXT: vmul.vv v8, v8, v165937; RV32-NEXT: vmv.x.s a0, v85938; RV32-NEXT: vsetivli zero, 1, e64, m8, ta, ma5939; RV32-NEXT: vsrl.vx v8, v8, a15940; RV32-NEXT: vmv.x.s a1, v85941; RV32-NEXT: ret5942;5943; RV64-LABEL: vreduce_mul_v16i64:5944; RV64: # %bb.0:5945; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma5946; RV64-NEXT: vle64.v v8, (a0)5947; RV64-NEXT: vslidedown.vi v16, v8, 85948; RV64-NEXT: vmul.vv v8, v8, v165949; RV64-NEXT: vslidedown.vi v16, v8, 45950; RV64-NEXT: vmul.vv v8, v8, v165951; RV64-NEXT: vslidedown.vi v16, v8, 25952; RV64-NEXT: vmul.vv v8, v8, v165953; RV64-NEXT: vrgather.vi v16, v8, 15954; RV64-NEXT: vmul.vv v8, v8, v165955; RV64-NEXT: vmv.x.s a0, v85956; RV64-NEXT: ret5957 %v = load <16 x i64>, ptr %x5958 %red = call i64 @llvm.vector.reduce.mul.v16i64(<16 x i64> %v)5959 ret i64 %red5960}5961 5962define i64 @vreduce_mul_v32i64(ptr %x) {5963; RV32-LABEL: vreduce_mul_v32i64:5964; RV32: # %bb.0:5965; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma5966; RV32-NEXT: vle64.v v8, (a0)5967; RV32-NEXT: addi a0, a0, 1285968; RV32-NEXT: vle64.v v16, (a0)5969; RV32-NEXT: vmul.vv v8, v8, v165970; RV32-NEXT: vslidedown.vi v16, v8, 85971; RV32-NEXT: vmul.vv v8, v8, v165972; RV32-NEXT: vslidedown.vi v16, v8, 45973; RV32-NEXT: vmul.vv v8, v8, v165974; RV32-NEXT: vslidedown.vi v16, v8, 25975; RV32-NEXT: vmul.vv v8, v8, v165976; RV32-NEXT: vrgather.vi v16, v8, 15977; RV32-NEXT: vmul.vv v8, v8, v165978; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma5979; RV32-NEXT: vmv.x.s a0, v85980; RV32-NEXT: vslidedown.vi v8, v8, 15981; RV32-NEXT: vmv.x.s a1, v85982; RV32-NEXT: ret5983;5984; RV64-LABEL: vreduce_mul_v32i64:5985; RV64: # %bb.0:5986; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma5987; RV64-NEXT: vle64.v v8, (a0)5988; RV64-NEXT: addi a0, a0, 1285989; RV64-NEXT: vle64.v v16, (a0)5990; RV64-NEXT: vmul.vv v8, v8, v165991; RV64-NEXT: vslidedown.vi v16, v8, 85992; RV64-NEXT: vmul.vv v8, v8, v165993; RV64-NEXT: vslidedown.vi v16, v8, 45994; RV64-NEXT: vmul.vv v8, v8, v165995; RV64-NEXT: vslidedown.vi v16, v8, 25996; RV64-NEXT: vmul.vv v8, v8, v165997; RV64-NEXT: vrgather.vi v16, v8, 15998; RV64-NEXT: vmul.vv v8, v8, v165999; RV64-NEXT: vmv.x.s a0, v86000; RV64-NEXT: ret6001 %v = load <32 x i64>, ptr %x6002 %red = call i64 @llvm.vector.reduce.mul.v32i64(<32 x i64> %v)6003 ret i64 %red6004}6005 6006define i64 @vreduce_mul_v64i64(ptr %x) nounwind {6007; RV32-LABEL: vreduce_mul_v64i64:6008; RV32: # %bb.0:6009; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma6010; RV32-NEXT: vle64.v v8, (a0)6011; RV32-NEXT: addi a1, a0, 3846012; RV32-NEXT: vle64.v v16, (a1)6013; RV32-NEXT: addi a1, a0, 2566014; RV32-NEXT: addi a0, a0, 1286015; RV32-NEXT: vle64.v v24, (a0)6016; RV32-NEXT: vle64.v v0, (a1)6017; RV32-NEXT: vmul.vv v16, v24, v166018; RV32-NEXT: vmul.vv v8, v8, v06019; RV32-NEXT: vmul.vv v8, v8, v166020; RV32-NEXT: vslidedown.vi v16, v8, 86021; RV32-NEXT: vmul.vv v8, v8, v166022; RV32-NEXT: vslidedown.vi v16, v8, 46023; RV32-NEXT: vmul.vv v8, v8, v166024; RV32-NEXT: vslidedown.vi v16, v8, 26025; RV32-NEXT: vmul.vv v8, v8, v166026; RV32-NEXT: vrgather.vi v16, v8, 16027; RV32-NEXT: vmul.vv v8, v8, v166028; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma6029; RV32-NEXT: vmv.x.s a0, v86030; RV32-NEXT: vslidedown.vi v8, v8, 16031; RV32-NEXT: vmv.x.s a1, v86032; RV32-NEXT: ret6033;6034; RV64-LABEL: vreduce_mul_v64i64:6035; RV64: # %bb.0:6036; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma6037; RV64-NEXT: vle64.v v8, (a0)6038; RV64-NEXT: addi a1, a0, 3846039; RV64-NEXT: vle64.v v16, (a1)6040; RV64-NEXT: addi a1, a0, 2566041; RV64-NEXT: addi a0, a0, 1286042; RV64-NEXT: vle64.v v24, (a0)6043; RV64-NEXT: vle64.v v0, (a1)6044; RV64-NEXT: vmul.vv v16, v24, v166045; RV64-NEXT: vmul.vv v8, v8, v06046; RV64-NEXT: vmul.vv v8, v8, v166047; RV64-NEXT: vslidedown.vi v16, v8, 86048; RV64-NEXT: vmul.vv v8, v8, v166049; RV64-NEXT: vslidedown.vi v16, v8, 46050; RV64-NEXT: vmul.vv v8, v8, v166051; RV64-NEXT: vslidedown.vi v16, v8, 26052; RV64-NEXT: vmul.vv v8, v8, v166053; RV64-NEXT: vrgather.vi v16, v8, 16054; RV64-NEXT: vmul.vv v8, v8, v166055; RV64-NEXT: vmv.x.s a0, v86056; RV64-NEXT: ret6057 %v = load <64 x i64>, ptr %x6058 %red = call i64 @llvm.vector.reduce.mul.v64i64(<64 x i64> %v)6059 ret i64 %red6060}6061