812 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,RV32 %s4; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,RV64 %s6 7define <2 x half> @vp_rint_v2f16(<2 x half> %va, <2 x i1> %m, i32 zeroext %evl) {8; CHECK-LABEL: vp_rint_v2f16:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma11; CHECK-NEXT: vfabs.v v9, v8, v0.t12; CHECK-NEXT: li a0, 2513; CHECK-NEXT: slli a0, a0, 1014; CHECK-NEXT: fmv.h.x fa5, a015; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu16; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t17; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma18; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t19; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t20; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu21; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t22; CHECK-NEXT: ret23 %v = call <2 x half> @llvm.vp.rint.v2f16(<2 x half> %va, <2 x i1> %m, i32 %evl)24 ret <2 x half> %v25}26 27define <2 x half> @vp_rint_v2f16_unmasked(<2 x half> %va, i32 zeroext %evl) {28; CHECK-LABEL: vp_rint_v2f16_unmasked:29; CHECK: # %bb.0:30; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma31; CHECK-NEXT: vfabs.v v9, v832; CHECK-NEXT: li a0, 2533; CHECK-NEXT: slli a0, a0, 1034; CHECK-NEXT: fmv.h.x fa5, a035; CHECK-NEXT: vmflt.vf v0, v9, fa536; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t37; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t38; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu39; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t40; CHECK-NEXT: ret41 %v = call <2 x half> @llvm.vp.rint.v2f16(<2 x half> %va, <2 x i1> splat (i1 true), i32 %evl)42 ret <2 x half> %v43}44 45define <4 x half> @vp_rint_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl) {46; CHECK-LABEL: vp_rint_v4f16:47; CHECK: # %bb.0:48; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma49; CHECK-NEXT: vfabs.v v9, v8, v0.t50; CHECK-NEXT: li a0, 2551; CHECK-NEXT: slli a0, a0, 1052; CHECK-NEXT: fmv.h.x fa5, a053; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu54; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t55; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma56; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t57; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t58; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu59; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t60; CHECK-NEXT: ret61 %v = call <4 x half> @llvm.vp.rint.v4f16(<4 x half> %va, <4 x i1> %m, i32 %evl)62 ret <4 x half> %v63}64 65define <4 x half> @vp_rint_v4f16_unmasked(<4 x half> %va, i32 zeroext %evl) {66; CHECK-LABEL: vp_rint_v4f16_unmasked:67; CHECK: # %bb.0:68; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma69; CHECK-NEXT: vfabs.v v9, v870; CHECK-NEXT: li a0, 2571; CHECK-NEXT: slli a0, a0, 1072; CHECK-NEXT: fmv.h.x fa5, a073; CHECK-NEXT: vmflt.vf v0, v9, fa574; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t75; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t76; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu77; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t78; CHECK-NEXT: ret79 %v = call <4 x half> @llvm.vp.rint.v4f16(<4 x half> %va, <4 x i1> splat (i1 true), i32 %evl)80 ret <4 x half> %v81}82 83define <8 x half> @vp_rint_v8f16(<8 x half> %va, <8 x i1> %m, i32 zeroext %evl) {84; CHECK-LABEL: vp_rint_v8f16:85; CHECK: # %bb.0:86; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma87; CHECK-NEXT: vfabs.v v9, v8, v0.t88; CHECK-NEXT: li a0, 2589; CHECK-NEXT: slli a0, a0, 1090; CHECK-NEXT: fmv.h.x fa5, a091; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu92; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t93; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma94; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t95; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t96; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu97; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t98; CHECK-NEXT: ret99 %v = call <8 x half> @llvm.vp.rint.v8f16(<8 x half> %va, <8 x i1> %m, i32 %evl)100 ret <8 x half> %v101}102 103define <8 x half> @vp_rint_v8f16_unmasked(<8 x half> %va, i32 zeroext %evl) {104; CHECK-LABEL: vp_rint_v8f16_unmasked:105; CHECK: # %bb.0:106; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma107; CHECK-NEXT: vfabs.v v9, v8108; CHECK-NEXT: li a0, 25109; CHECK-NEXT: slli a0, a0, 10110; CHECK-NEXT: fmv.h.x fa5, a0111; CHECK-NEXT: vmflt.vf v0, v9, fa5112; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t113; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t114; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu115; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t116; CHECK-NEXT: ret117 %v = call <8 x half> @llvm.vp.rint.v8f16(<8 x half> %va, <8 x i1> splat (i1 true), i32 %evl)118 ret <8 x half> %v119}120 121define <16 x half> @vp_rint_v16f16(<16 x half> %va, <16 x i1> %m, i32 zeroext %evl) {122; CHECK-LABEL: vp_rint_v16f16:123; CHECK: # %bb.0:124; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma125; CHECK-NEXT: vmv1r.v v10, v0126; CHECK-NEXT: vfabs.v v12, v8, v0.t127; CHECK-NEXT: li a0, 25128; CHECK-NEXT: slli a0, a0, 10129; CHECK-NEXT: fmv.h.x fa5, a0130; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu131; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t132; CHECK-NEXT: vmv1r.v v0, v10133; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma134; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t135; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t136; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu137; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t138; CHECK-NEXT: ret139 %v = call <16 x half> @llvm.vp.rint.v16f16(<16 x half> %va, <16 x i1> %m, i32 %evl)140 ret <16 x half> %v141}142 143define <16 x half> @vp_rint_v16f16_unmasked(<16 x half> %va, i32 zeroext %evl) {144; CHECK-LABEL: vp_rint_v16f16_unmasked:145; CHECK: # %bb.0:146; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma147; CHECK-NEXT: vfabs.v v10, v8148; CHECK-NEXT: li a0, 25149; CHECK-NEXT: slli a0, a0, 10150; CHECK-NEXT: fmv.h.x fa5, a0151; CHECK-NEXT: vmflt.vf v0, v10, fa5152; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t153; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t154; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu155; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t156; CHECK-NEXT: ret157 %v = call <16 x half> @llvm.vp.rint.v16f16(<16 x half> %va, <16 x i1> splat (i1 true), i32 %evl)158 ret <16 x half> %v159}160 161define <2 x float> @vp_rint_v2f32(<2 x float> %va, <2 x i1> %m, i32 zeroext %evl) {162; CHECK-LABEL: vp_rint_v2f32:163; CHECK: # %bb.0:164; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma165; CHECK-NEXT: vfabs.v v9, v8, v0.t166; CHECK-NEXT: lui a0, 307200167; CHECK-NEXT: fmv.w.x fa5, a0168; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu169; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t170; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma171; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t172; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t173; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu174; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t175; CHECK-NEXT: ret176 %v = call <2 x float> @llvm.vp.rint.v2f32(<2 x float> %va, <2 x i1> %m, i32 %evl)177 ret <2 x float> %v178}179 180define <2 x float> @vp_rint_v2f32_unmasked(<2 x float> %va, i32 zeroext %evl) {181; CHECK-LABEL: vp_rint_v2f32_unmasked:182; CHECK: # %bb.0:183; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma184; CHECK-NEXT: vfabs.v v9, v8185; CHECK-NEXT: lui a0, 307200186; CHECK-NEXT: fmv.w.x fa5, a0187; CHECK-NEXT: vmflt.vf v0, v9, fa5188; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t189; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t190; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu191; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t192; CHECK-NEXT: ret193 %v = call <2 x float> @llvm.vp.rint.v2f32(<2 x float> %va, <2 x i1> splat (i1 true), i32 %evl)194 ret <2 x float> %v195}196 197define <4 x float> @vp_rint_v4f32(<4 x float> %va, <4 x i1> %m, i32 zeroext %evl) {198; CHECK-LABEL: vp_rint_v4f32:199; CHECK: # %bb.0:200; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma201; CHECK-NEXT: vfabs.v v9, v8, v0.t202; CHECK-NEXT: lui a0, 307200203; CHECK-NEXT: fmv.w.x fa5, a0204; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu205; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t206; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma207; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t208; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t209; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu210; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t211; CHECK-NEXT: ret212 %v = call <4 x float> @llvm.vp.rint.v4f32(<4 x float> %va, <4 x i1> %m, i32 %evl)213 ret <4 x float> %v214}215 216define <4 x float> @vp_rint_v4f32_unmasked(<4 x float> %va, i32 zeroext %evl) {217; CHECK-LABEL: vp_rint_v4f32_unmasked:218; CHECK: # %bb.0:219; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma220; CHECK-NEXT: vfabs.v v9, v8221; CHECK-NEXT: lui a0, 307200222; CHECK-NEXT: fmv.w.x fa5, a0223; CHECK-NEXT: vmflt.vf v0, v9, fa5224; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t225; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t226; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu227; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t228; CHECK-NEXT: ret229 %v = call <4 x float> @llvm.vp.rint.v4f32(<4 x float> %va, <4 x i1> splat (i1 true), i32 %evl)230 ret <4 x float> %v231}232 233define <8 x float> @vp_rint_v8f32(<8 x float> %va, <8 x i1> %m, i32 zeroext %evl) {234; CHECK-LABEL: vp_rint_v8f32:235; CHECK: # %bb.0:236; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma237; CHECK-NEXT: vmv1r.v v10, v0238; CHECK-NEXT: vfabs.v v12, v8, v0.t239; CHECK-NEXT: lui a0, 307200240; CHECK-NEXT: fmv.w.x fa5, a0241; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu242; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t243; CHECK-NEXT: vmv1r.v v0, v10244; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma245; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t246; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t247; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu248; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t249; CHECK-NEXT: ret250 %v = call <8 x float> @llvm.vp.rint.v8f32(<8 x float> %va, <8 x i1> %m, i32 %evl)251 ret <8 x float> %v252}253 254define <8 x float> @vp_rint_v8f32_unmasked(<8 x float> %va, i32 zeroext %evl) {255; CHECK-LABEL: vp_rint_v8f32_unmasked:256; CHECK: # %bb.0:257; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma258; CHECK-NEXT: vfabs.v v10, v8259; CHECK-NEXT: lui a0, 307200260; CHECK-NEXT: fmv.w.x fa5, a0261; CHECK-NEXT: vmflt.vf v0, v10, fa5262; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t263; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t264; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu265; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t266; CHECK-NEXT: ret267 %v = call <8 x float> @llvm.vp.rint.v8f32(<8 x float> %va, <8 x i1> splat (i1 true), i32 %evl)268 ret <8 x float> %v269}270 271define <16 x float> @vp_rint_v16f32(<16 x float> %va, <16 x i1> %m, i32 zeroext %evl) {272; CHECK-LABEL: vp_rint_v16f32:273; CHECK: # %bb.0:274; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma275; CHECK-NEXT: vmv1r.v v12, v0276; CHECK-NEXT: vfabs.v v16, v8, v0.t277; CHECK-NEXT: lui a0, 307200278; CHECK-NEXT: fmv.w.x fa5, a0279; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu280; CHECK-NEXT: vmflt.vf v12, v16, fa5, v0.t281; CHECK-NEXT: vmv1r.v v0, v12282; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma283; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t284; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t285; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu286; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t287; CHECK-NEXT: ret288 %v = call <16 x float> @llvm.vp.rint.v16f32(<16 x float> %va, <16 x i1> %m, i32 %evl)289 ret <16 x float> %v290}291 292define <16 x float> @vp_rint_v16f32_unmasked(<16 x float> %va, i32 zeroext %evl) {293; CHECK-LABEL: vp_rint_v16f32_unmasked:294; CHECK: # %bb.0:295; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma296; CHECK-NEXT: vfabs.v v12, v8297; CHECK-NEXT: lui a0, 307200298; CHECK-NEXT: fmv.w.x fa5, a0299; CHECK-NEXT: vmflt.vf v0, v12, fa5300; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t301; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t302; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu303; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t304; CHECK-NEXT: ret305 %v = call <16 x float> @llvm.vp.rint.v16f32(<16 x float> %va, <16 x i1> splat (i1 true), i32 %evl)306 ret <16 x float> %v307}308 309define <2 x double> @vp_rint_v2f64(<2 x double> %va, <2 x i1> %m, i32 zeroext %evl) {310; RV32-LABEL: vp_rint_v2f64:311; RV32: # %bb.0:312; RV32-NEXT: lui a1, %hi(.LCPI16_0)313; RV32-NEXT: fld fa5, %lo(.LCPI16_0)(a1)314; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma315; RV32-NEXT: vfabs.v v9, v8, v0.t316; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu317; RV32-NEXT: vmflt.vf v0, v9, fa5, v0.t318; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma319; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t320; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t321; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu322; RV32-NEXT: vfsgnj.vv v8, v9, v8, v0.t323; RV32-NEXT: ret324;325; RV64-LABEL: vp_rint_v2f64:326; RV64: # %bb.0:327; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma328; RV64-NEXT: vfabs.v v9, v8, v0.t329; RV64-NEXT: li a0, 1075330; RV64-NEXT: slli a0, a0, 52331; RV64-NEXT: fmv.d.x fa5, a0332; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu333; RV64-NEXT: vmflt.vf v0, v9, fa5, v0.t334; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma335; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t336; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t337; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu338; RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t339; RV64-NEXT: ret340 %v = call <2 x double> @llvm.vp.rint.v2f64(<2 x double> %va, <2 x i1> %m, i32 %evl)341 ret <2 x double> %v342}343 344define <2 x double> @vp_rint_v2f64_unmasked(<2 x double> %va, i32 zeroext %evl) {345; RV32-LABEL: vp_rint_v2f64_unmasked:346; RV32: # %bb.0:347; RV32-NEXT: lui a1, %hi(.LCPI17_0)348; RV32-NEXT: fld fa5, %lo(.LCPI17_0)(a1)349; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma350; RV32-NEXT: vfabs.v v9, v8351; RV32-NEXT: vmflt.vf v0, v9, fa5352; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t353; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t354; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu355; RV32-NEXT: vfsgnj.vv v8, v9, v8, v0.t356; RV32-NEXT: ret357;358; RV64-LABEL: vp_rint_v2f64_unmasked:359; RV64: # %bb.0:360; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma361; RV64-NEXT: vfabs.v v9, v8362; RV64-NEXT: li a0, 1075363; RV64-NEXT: slli a0, a0, 52364; RV64-NEXT: fmv.d.x fa5, a0365; RV64-NEXT: vmflt.vf v0, v9, fa5366; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t367; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t368; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu369; RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t370; RV64-NEXT: ret371 %v = call <2 x double> @llvm.vp.rint.v2f64(<2 x double> %va, <2 x i1> splat (i1 true), i32 %evl)372 ret <2 x double> %v373}374 375define <4 x double> @vp_rint_v4f64(<4 x double> %va, <4 x i1> %m, i32 zeroext %evl) {376; RV32-LABEL: vp_rint_v4f64:377; RV32: # %bb.0:378; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma379; RV32-NEXT: vmv1r.v v10, v0380; RV32-NEXT: lui a0, %hi(.LCPI18_0)381; RV32-NEXT: fld fa5, %lo(.LCPI18_0)(a0)382; RV32-NEXT: vfabs.v v12, v8, v0.t383; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, mu384; RV32-NEXT: vmflt.vf v10, v12, fa5, v0.t385; RV32-NEXT: vmv1r.v v0, v10386; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, ma387; RV32-NEXT: vfcvt.x.f.v v12, v8, v0.t388; RV32-NEXT: vfcvt.f.x.v v12, v12, v0.t389; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, mu390; RV32-NEXT: vfsgnj.vv v8, v12, v8, v0.t391; RV32-NEXT: ret392;393; RV64-LABEL: vp_rint_v4f64:394; RV64: # %bb.0:395; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma396; RV64-NEXT: vmv1r.v v10, v0397; RV64-NEXT: vfabs.v v12, v8, v0.t398; RV64-NEXT: li a0, 1075399; RV64-NEXT: slli a0, a0, 52400; RV64-NEXT: fmv.d.x fa5, a0401; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, mu402; RV64-NEXT: vmflt.vf v10, v12, fa5, v0.t403; RV64-NEXT: vmv1r.v v0, v10404; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, ma405; RV64-NEXT: vfcvt.x.f.v v12, v8, v0.t406; RV64-NEXT: vfcvt.f.x.v v12, v12, v0.t407; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, mu408; RV64-NEXT: vfsgnj.vv v8, v12, v8, v0.t409; RV64-NEXT: ret410 %v = call <4 x double> @llvm.vp.rint.v4f64(<4 x double> %va, <4 x i1> %m, i32 %evl)411 ret <4 x double> %v412}413 414define <4 x double> @vp_rint_v4f64_unmasked(<4 x double> %va, i32 zeroext %evl) {415; RV32-LABEL: vp_rint_v4f64_unmasked:416; RV32: # %bb.0:417; RV32-NEXT: lui a1, %hi(.LCPI19_0)418; RV32-NEXT: fld fa5, %lo(.LCPI19_0)(a1)419; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma420; RV32-NEXT: vfabs.v v10, v8421; RV32-NEXT: vmflt.vf v0, v10, fa5422; RV32-NEXT: vfcvt.x.f.v v10, v8, v0.t423; RV32-NEXT: vfcvt.f.x.v v10, v10, v0.t424; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, mu425; RV32-NEXT: vfsgnj.vv v8, v10, v8, v0.t426; RV32-NEXT: ret427;428; RV64-LABEL: vp_rint_v4f64_unmasked:429; RV64: # %bb.0:430; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma431; RV64-NEXT: vfabs.v v10, v8432; RV64-NEXT: li a0, 1075433; RV64-NEXT: slli a0, a0, 52434; RV64-NEXT: fmv.d.x fa5, a0435; RV64-NEXT: vmflt.vf v0, v10, fa5436; RV64-NEXT: vfcvt.x.f.v v10, v8, v0.t437; RV64-NEXT: vfcvt.f.x.v v10, v10, v0.t438; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, mu439; RV64-NEXT: vfsgnj.vv v8, v10, v8, v0.t440; RV64-NEXT: ret441 %v = call <4 x double> @llvm.vp.rint.v4f64(<4 x double> %va, <4 x i1> splat (i1 true), i32 %evl)442 ret <4 x double> %v443}444 445define <8 x double> @vp_rint_v8f64(<8 x double> %va, <8 x i1> %m, i32 zeroext %evl) {446; RV32-LABEL: vp_rint_v8f64:447; RV32: # %bb.0:448; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma449; RV32-NEXT: vmv1r.v v12, v0450; RV32-NEXT: lui a0, %hi(.LCPI20_0)451; RV32-NEXT: fld fa5, %lo(.LCPI20_0)(a0)452; RV32-NEXT: vfabs.v v16, v8, v0.t453; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu454; RV32-NEXT: vmflt.vf v12, v16, fa5, v0.t455; RV32-NEXT: vmv1r.v v0, v12456; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, ma457; RV32-NEXT: vfcvt.x.f.v v16, v8, v0.t458; RV32-NEXT: vfcvt.f.x.v v16, v16, v0.t459; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu460; RV32-NEXT: vfsgnj.vv v8, v16, v8, v0.t461; RV32-NEXT: ret462;463; RV64-LABEL: vp_rint_v8f64:464; RV64: # %bb.0:465; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma466; RV64-NEXT: vmv1r.v v12, v0467; RV64-NEXT: vfabs.v v16, v8, v0.t468; RV64-NEXT: li a0, 1075469; RV64-NEXT: slli a0, a0, 52470; RV64-NEXT: fmv.d.x fa5, a0471; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, mu472; RV64-NEXT: vmflt.vf v12, v16, fa5, v0.t473; RV64-NEXT: vmv1r.v v0, v12474; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, ma475; RV64-NEXT: vfcvt.x.f.v v16, v8, v0.t476; RV64-NEXT: vfcvt.f.x.v v16, v16, v0.t477; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, mu478; RV64-NEXT: vfsgnj.vv v8, v16, v8, v0.t479; RV64-NEXT: ret480 %v = call <8 x double> @llvm.vp.rint.v8f64(<8 x double> %va, <8 x i1> %m, i32 %evl)481 ret <8 x double> %v482}483 484define <8 x double> @vp_rint_v8f64_unmasked(<8 x double> %va, i32 zeroext %evl) {485; RV32-LABEL: vp_rint_v8f64_unmasked:486; RV32: # %bb.0:487; RV32-NEXT: lui a1, %hi(.LCPI21_0)488; RV32-NEXT: fld fa5, %lo(.LCPI21_0)(a1)489; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma490; RV32-NEXT: vfabs.v v12, v8491; RV32-NEXT: vmflt.vf v0, v12, fa5492; RV32-NEXT: vfcvt.x.f.v v12, v8, v0.t493; RV32-NEXT: vfcvt.f.x.v v12, v12, v0.t494; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu495; RV32-NEXT: vfsgnj.vv v8, v12, v8, v0.t496; RV32-NEXT: ret497;498; RV64-LABEL: vp_rint_v8f64_unmasked:499; RV64: # %bb.0:500; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma501; RV64-NEXT: vfabs.v v12, v8502; RV64-NEXT: li a0, 1075503; RV64-NEXT: slli a0, a0, 52504; RV64-NEXT: fmv.d.x fa5, a0505; RV64-NEXT: vmflt.vf v0, v12, fa5506; RV64-NEXT: vfcvt.x.f.v v12, v8, v0.t507; RV64-NEXT: vfcvt.f.x.v v12, v12, v0.t508; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, mu509; RV64-NEXT: vfsgnj.vv v8, v12, v8, v0.t510; RV64-NEXT: ret511 %v = call <8 x double> @llvm.vp.rint.v8f64(<8 x double> %va, <8 x i1> splat (i1 true), i32 %evl)512 ret <8 x double> %v513}514 515define <15 x double> @vp_rint_v15f64(<15 x double> %va, <15 x i1> %m, i32 zeroext %evl) {516; RV32-LABEL: vp_rint_v15f64:517; RV32: # %bb.0:518; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma519; RV32-NEXT: vmv1r.v v16, v0520; RV32-NEXT: lui a0, %hi(.LCPI22_0)521; RV32-NEXT: fld fa5, %lo(.LCPI22_0)(a0)522; RV32-NEXT: vfabs.v v24, v8, v0.t523; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu524; RV32-NEXT: vmflt.vf v16, v24, fa5, v0.t525; RV32-NEXT: vmv1r.v v0, v16526; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma527; RV32-NEXT: vfcvt.x.f.v v24, v8, v0.t528; RV32-NEXT: vfcvt.f.x.v v24, v24, v0.t529; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu530; RV32-NEXT: vfsgnj.vv v8, v24, v8, v0.t531; RV32-NEXT: ret532;533; RV64-LABEL: vp_rint_v15f64:534; RV64: # %bb.0:535; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma536; RV64-NEXT: vmv1r.v v16, v0537; RV64-NEXT: vfabs.v v24, v8, v0.t538; RV64-NEXT: li a0, 1075539; RV64-NEXT: slli a0, a0, 52540; RV64-NEXT: fmv.d.x fa5, a0541; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu542; RV64-NEXT: vmflt.vf v16, v24, fa5, v0.t543; RV64-NEXT: vmv1r.v v0, v16544; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma545; RV64-NEXT: vfcvt.x.f.v v24, v8, v0.t546; RV64-NEXT: vfcvt.f.x.v v24, v24, v0.t547; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu548; RV64-NEXT: vfsgnj.vv v8, v24, v8, v0.t549; RV64-NEXT: ret550 %v = call <15 x double> @llvm.vp.rint.v15f64(<15 x double> %va, <15 x i1> %m, i32 %evl)551 ret <15 x double> %v552}553 554define <15 x double> @vp_rint_v15f64_unmasked(<15 x double> %va, i32 zeroext %evl) {555; RV32-LABEL: vp_rint_v15f64_unmasked:556; RV32: # %bb.0:557; RV32-NEXT: lui a1, %hi(.LCPI23_0)558; RV32-NEXT: fld fa5, %lo(.LCPI23_0)(a1)559; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma560; RV32-NEXT: vfabs.v v16, v8561; RV32-NEXT: vmflt.vf v0, v16, fa5562; RV32-NEXT: vfcvt.x.f.v v16, v8, v0.t563; RV32-NEXT: vfcvt.f.x.v v16, v16, v0.t564; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu565; RV32-NEXT: vfsgnj.vv v8, v16, v8, v0.t566; RV32-NEXT: ret567;568; RV64-LABEL: vp_rint_v15f64_unmasked:569; RV64: # %bb.0:570; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma571; RV64-NEXT: vfabs.v v16, v8572; RV64-NEXT: li a0, 1075573; RV64-NEXT: slli a0, a0, 52574; RV64-NEXT: fmv.d.x fa5, a0575; RV64-NEXT: vmflt.vf v0, v16, fa5576; RV64-NEXT: vfcvt.x.f.v v16, v8, v0.t577; RV64-NEXT: vfcvt.f.x.v v16, v16, v0.t578; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu579; RV64-NEXT: vfsgnj.vv v8, v16, v8, v0.t580; RV64-NEXT: ret581 %v = call <15 x double> @llvm.vp.rint.v15f64(<15 x double> %va, <15 x i1> splat (i1 true), i32 %evl)582 ret <15 x double> %v583}584 585define <16 x double> @vp_rint_v16f64(<16 x double> %va, <16 x i1> %m, i32 zeroext %evl) {586; RV32-LABEL: vp_rint_v16f64:587; RV32: # %bb.0:588; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma589; RV32-NEXT: vmv1r.v v16, v0590; RV32-NEXT: lui a0, %hi(.LCPI24_0)591; RV32-NEXT: fld fa5, %lo(.LCPI24_0)(a0)592; RV32-NEXT: vfabs.v v24, v8, v0.t593; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu594; RV32-NEXT: vmflt.vf v16, v24, fa5, v0.t595; RV32-NEXT: vmv1r.v v0, v16596; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma597; RV32-NEXT: vfcvt.x.f.v v24, v8, v0.t598; RV32-NEXT: vfcvt.f.x.v v24, v24, v0.t599; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu600; RV32-NEXT: vfsgnj.vv v8, v24, v8, v0.t601; RV32-NEXT: ret602;603; RV64-LABEL: vp_rint_v16f64:604; RV64: # %bb.0:605; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma606; RV64-NEXT: vmv1r.v v16, v0607; RV64-NEXT: vfabs.v v24, v8, v0.t608; RV64-NEXT: li a0, 1075609; RV64-NEXT: slli a0, a0, 52610; RV64-NEXT: fmv.d.x fa5, a0611; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu612; RV64-NEXT: vmflt.vf v16, v24, fa5, v0.t613; RV64-NEXT: vmv1r.v v0, v16614; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma615; RV64-NEXT: vfcvt.x.f.v v24, v8, v0.t616; RV64-NEXT: vfcvt.f.x.v v24, v24, v0.t617; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu618; RV64-NEXT: vfsgnj.vv v8, v24, v8, v0.t619; RV64-NEXT: ret620 %v = call <16 x double> @llvm.vp.rint.v16f64(<16 x double> %va, <16 x i1> %m, i32 %evl)621 ret <16 x double> %v622}623 624define <16 x double> @vp_rint_v16f64_unmasked(<16 x double> %va, i32 zeroext %evl) {625; RV32-LABEL: vp_rint_v16f64_unmasked:626; RV32: # %bb.0:627; RV32-NEXT: lui a1, %hi(.LCPI25_0)628; RV32-NEXT: fld fa5, %lo(.LCPI25_0)(a1)629; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma630; RV32-NEXT: vfabs.v v16, v8631; RV32-NEXT: vmflt.vf v0, v16, fa5632; RV32-NEXT: vfcvt.x.f.v v16, v8, v0.t633; RV32-NEXT: vfcvt.f.x.v v16, v16, v0.t634; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu635; RV32-NEXT: vfsgnj.vv v8, v16, v8, v0.t636; RV32-NEXT: ret637;638; RV64-LABEL: vp_rint_v16f64_unmasked:639; RV64: # %bb.0:640; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma641; RV64-NEXT: vfabs.v v16, v8642; RV64-NEXT: li a0, 1075643; RV64-NEXT: slli a0, a0, 52644; RV64-NEXT: fmv.d.x fa5, a0645; RV64-NEXT: vmflt.vf v0, v16, fa5646; RV64-NEXT: vfcvt.x.f.v v16, v8, v0.t647; RV64-NEXT: vfcvt.f.x.v v16, v16, v0.t648; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu649; RV64-NEXT: vfsgnj.vv v8, v16, v8, v0.t650; RV64-NEXT: ret651 %v = call <16 x double> @llvm.vp.rint.v16f64(<16 x double> %va, <16 x i1> splat (i1 true), i32 %evl)652 ret <16 x double> %v653}654 655define <32 x double> @vp_rint_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroext %evl) {656; RV32-LABEL: vp_rint_v32f64:657; RV32: # %bb.0:658; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma659; RV32-NEXT: vmv1r.v v6, v0660; RV32-NEXT: li a2, 16661; RV32-NEXT: vslidedown.vi v7, v0, 2662; RV32-NEXT: mv a1, a0663; RV32-NEXT: bltu a0, a2, .LBB26_2664; RV32-NEXT: # %bb.1:665; RV32-NEXT: li a1, 16666; RV32-NEXT: .LBB26_2:667; RV32-NEXT: vmv1r.v v0, v6668; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma669; RV32-NEXT: vfabs.v v24, v8, v0.t670; RV32-NEXT: lui a1, %hi(.LCPI26_0)671; RV32-NEXT: fld fa5, %lo(.LCPI26_0)(a1)672; RV32-NEXT: addi a1, a0, -16673; RV32-NEXT: sltu a0, a0, a1674; RV32-NEXT: addi a0, a0, -1675; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu676; RV32-NEXT: vmflt.vf v6, v24, fa5, v0.t677; RV32-NEXT: and a0, a0, a1678; RV32-NEXT: vmv1r.v v0, v6679; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma680; RV32-NEXT: vfcvt.x.f.v v24, v8, v0.t681; RV32-NEXT: vfcvt.f.x.v v24, v24, v0.t682; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu683; RV32-NEXT: vfsgnj.vv v8, v24, v8, v0.t684; RV32-NEXT: vmv1r.v v0, v7685; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma686; RV32-NEXT: vfabs.v v24, v16, v0.t687; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu688; RV32-NEXT: vmflt.vf v7, v24, fa5, v0.t689; RV32-NEXT: vmv1r.v v0, v7690; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma691; RV32-NEXT: vfcvt.x.f.v v24, v16, v0.t692; RV32-NEXT: vfcvt.f.x.v v24, v24, v0.t693; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu694; RV32-NEXT: vfsgnj.vv v16, v24, v16, v0.t695; RV32-NEXT: ret696;697; RV64-LABEL: vp_rint_v32f64:698; RV64: # %bb.0:699; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma700; RV64-NEXT: vmv1r.v v6, v0701; RV64-NEXT: li a2, 16702; RV64-NEXT: vslidedown.vi v7, v0, 2703; RV64-NEXT: mv a1, a0704; RV64-NEXT: bltu a0, a2, .LBB26_2705; RV64-NEXT: # %bb.1:706; RV64-NEXT: li a1, 16707; RV64-NEXT: .LBB26_2:708; RV64-NEXT: vmv1r.v v0, v6709; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma710; RV64-NEXT: vfabs.v v24, v8, v0.t711; RV64-NEXT: li a1, 1075712; RV64-NEXT: slli a1, a1, 52713; RV64-NEXT: fmv.d.x fa5, a1714; RV64-NEXT: addi a1, a0, -16715; RV64-NEXT: sltu a0, a0, a1716; RV64-NEXT: addi a0, a0, -1717; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu718; RV64-NEXT: vmflt.vf v6, v24, fa5, v0.t719; RV64-NEXT: and a0, a0, a1720; RV64-NEXT: vmv1r.v v0, v6721; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma722; RV64-NEXT: vfcvt.x.f.v v24, v8, v0.t723; RV64-NEXT: vfcvt.f.x.v v24, v24, v0.t724; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu725; RV64-NEXT: vfsgnj.vv v8, v24, v8, v0.t726; RV64-NEXT: vmv1r.v v0, v7727; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma728; RV64-NEXT: vfabs.v v24, v16, v0.t729; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu730; RV64-NEXT: vmflt.vf v7, v24, fa5, v0.t731; RV64-NEXT: vmv1r.v v0, v7732; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma733; RV64-NEXT: vfcvt.x.f.v v24, v16, v0.t734; RV64-NEXT: vfcvt.f.x.v v24, v24, v0.t735; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu736; RV64-NEXT: vfsgnj.vv v16, v24, v16, v0.t737; RV64-NEXT: ret738 %v = call <32 x double> @llvm.vp.rint.v32f64(<32 x double> %va, <32 x i1> %m, i32 %evl)739 ret <32 x double> %v740}741 742define <32 x double> @vp_rint_v32f64_unmasked(<32 x double> %va, i32 zeroext %evl) {743; RV32-LABEL: vp_rint_v32f64_unmasked:744; RV32: # %bb.0:745; RV32-NEXT: li a2, 16746; RV32-NEXT: mv a1, a0747; RV32-NEXT: bltu a0, a2, .LBB27_2748; RV32-NEXT: # %bb.1:749; RV32-NEXT: li a1, 16750; RV32-NEXT: .LBB27_2:751; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma752; RV32-NEXT: vfabs.v v24, v8753; RV32-NEXT: lui a2, %hi(.LCPI27_0)754; RV32-NEXT: fld fa5, %lo(.LCPI27_0)(a2)755; RV32-NEXT: addi a2, a0, -16756; RV32-NEXT: sltu a0, a0, a2757; RV32-NEXT: addi a0, a0, -1758; RV32-NEXT: and a0, a0, a2759; RV32-NEXT: vmflt.vf v0, v24, fa5760; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma761; RV32-NEXT: vfabs.v v24, v16762; RV32-NEXT: vmflt.vf v7, v24, fa5763; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma764; RV32-NEXT: vfcvt.x.f.v v24, v8, v0.t765; RV32-NEXT: vfcvt.f.x.v v24, v24, v0.t766; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu767; RV32-NEXT: vfsgnj.vv v8, v24, v8, v0.t768; RV32-NEXT: vmv1r.v v0, v7769; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma770; RV32-NEXT: vfcvt.x.f.v v24, v16, v0.t771; RV32-NEXT: vfcvt.f.x.v v24, v24, v0.t772; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu773; RV32-NEXT: vfsgnj.vv v16, v24, v16, v0.t774; RV32-NEXT: ret775;776; RV64-LABEL: vp_rint_v32f64_unmasked:777; RV64: # %bb.0:778; RV64-NEXT: li a2, 16779; RV64-NEXT: mv a1, a0780; RV64-NEXT: bltu a0, a2, .LBB27_2781; RV64-NEXT: # %bb.1:782; RV64-NEXT: li a1, 16783; RV64-NEXT: .LBB27_2:784; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma785; RV64-NEXT: vfabs.v v24, v8786; RV64-NEXT: li a2, 1075787; RV64-NEXT: slli a2, a2, 52788; RV64-NEXT: fmv.d.x fa5, a2789; RV64-NEXT: addi a2, a0, -16790; RV64-NEXT: sltu a0, a0, a2791; RV64-NEXT: addi a0, a0, -1792; RV64-NEXT: vmflt.vf v0, v24, fa5793; RV64-NEXT: and a0, a0, a2794; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma795; RV64-NEXT: vfabs.v v24, v16796; RV64-NEXT: vmflt.vf v7, v24, fa5797; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma798; RV64-NEXT: vfcvt.x.f.v v24, v8, v0.t799; RV64-NEXT: vfcvt.f.x.v v24, v24, v0.t800; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu801; RV64-NEXT: vfsgnj.vv v8, v24, v8, v0.t802; RV64-NEXT: vmv1r.v v0, v7803; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma804; RV64-NEXT: vfcvt.x.f.v v24, v16, v0.t805; RV64-NEXT: vfcvt.f.x.v v24, v24, v0.t806; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu807; RV64-NEXT: vfsgnj.vv v16, v24, v16, v0.t808; RV64-NEXT: ret809 %v = call <32 x double> @llvm.vp.rint.v32f64(<32 x double> %va, <32 x i1> splat (i1 true), i32 %evl)810 ret <32 x double> %v811}812