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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH,RV32ZVFH4; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH,RV64ZVFH6; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+v -target-abi=ilp32d \7; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,RV32ZVFHMIN8; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+v -target-abi=lp64d \9; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,RV64ZVFHMIN10 11define <2 x half> @vp_roundeven_v2f16(<2 x half> %va, <2 x i1> %m, i32 zeroext %evl) {12; ZVFH-LABEL: vp_roundeven_v2f16:13; ZVFH: # %bb.0:14; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma15; ZVFH-NEXT: vfabs.v v9, v8, v0.t16; ZVFH-NEXT: li a0, 2517; ZVFH-NEXT: slli a0, a0, 1018; ZVFH-NEXT: fmv.h.x fa5, a019; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, mu20; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t21; ZVFH-NEXT: fsrmi a0, 022; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, ma23; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t24; ZVFH-NEXT: fsrm a025; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t26; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, mu27; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t28; ZVFH-NEXT: ret29;30; ZVFHMIN-LABEL: vp_roundeven_v2f16:31; ZVFHMIN: # %bb.0:32; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma33; ZVFHMIN-NEXT: vmv1r.v v9, v034; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t35; ZVFHMIN-NEXT: lui a0, 30720036; ZVFHMIN-NEXT: vmv1r.v v8, v037; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma38; ZVFHMIN-NEXT: vfabs.v v11, v10, v0.t39; ZVFHMIN-NEXT: fmv.w.x fa5, a040; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu41; ZVFHMIN-NEXT: vmflt.vf v8, v11, fa5, v0.t42; ZVFHMIN-NEXT: fsrmi a0, 043; ZVFHMIN-NEXT: vmv1r.v v0, v844; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma45; ZVFHMIN-NEXT: vfcvt.x.f.v v11, v10, v0.t46; ZVFHMIN-NEXT: fsrm a047; ZVFHMIN-NEXT: vfcvt.f.x.v v11, v11, v0.t48; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu49; ZVFHMIN-NEXT: vfsgnj.vv v10, v11, v10, v0.t50; ZVFHMIN-NEXT: vmv1r.v v0, v951; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma52; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t53; ZVFHMIN-NEXT: ret54 %v = call <2 x half> @llvm.vp.roundeven.v2f16(<2 x half> %va, <2 x i1> %m, i32 %evl)55 ret <2 x half> %v56}57 58define <2 x half> @vp_roundeven_v2f16_unmasked(<2 x half> %va, i32 zeroext %evl) {59; ZVFH-LABEL: vp_roundeven_v2f16_unmasked:60; ZVFH: # %bb.0:61; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma62; ZVFH-NEXT: vfabs.v v9, v863; ZVFH-NEXT: li a0, 2564; ZVFH-NEXT: slli a0, a0, 1065; ZVFH-NEXT: fmv.h.x fa5, a066; ZVFH-NEXT: vmflt.vf v0, v9, fa567; ZVFH-NEXT: fsrmi a0, 068; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t69; ZVFH-NEXT: fsrm a070; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t71; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, mu72; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t73; ZVFH-NEXT: ret74;75; ZVFHMIN-LABEL: vp_roundeven_v2f16_unmasked:76; ZVFHMIN: # %bb.0:77; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma78; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v879; ZVFHMIN-NEXT: lui a0, 30720080; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma81; ZVFHMIN-NEXT: vfabs.v v8, v982; ZVFHMIN-NEXT: fmv.w.x fa5, a083; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa584; ZVFHMIN-NEXT: fsrmi a0, 085; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t86; ZVFHMIN-NEXT: fsrm a087; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t88; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu89; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t90; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma91; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v992; ZVFHMIN-NEXT: ret93 %v = call <2 x half> @llvm.vp.roundeven.v2f16(<2 x half> %va, <2 x i1> splat (i1 true), i32 %evl)94 ret <2 x half> %v95}96 97define <4 x half> @vp_roundeven_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl) {98; ZVFH-LABEL: vp_roundeven_v4f16:99; ZVFH: # %bb.0:100; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma101; ZVFH-NEXT: vfabs.v v9, v8, v0.t102; ZVFH-NEXT: li a0, 25103; ZVFH-NEXT: slli a0, a0, 10104; ZVFH-NEXT: fmv.h.x fa5, a0105; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, mu106; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t107; ZVFH-NEXT: fsrmi a0, 0108; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma109; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t110; ZVFH-NEXT: fsrm a0111; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t112; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, mu113; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t114; ZVFH-NEXT: ret115;116; ZVFHMIN-LABEL: vp_roundeven_v4f16:117; ZVFHMIN: # %bb.0:118; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma119; ZVFHMIN-NEXT: vmv1r.v v9, v0120; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t121; ZVFHMIN-NEXT: lui a0, 307200122; ZVFHMIN-NEXT: vmv1r.v v8, v0123; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma124; ZVFHMIN-NEXT: vfabs.v v11, v10, v0.t125; ZVFHMIN-NEXT: fmv.w.x fa5, a0126; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu127; ZVFHMIN-NEXT: vmflt.vf v8, v11, fa5, v0.t128; ZVFHMIN-NEXT: fsrmi a0, 0129; ZVFHMIN-NEXT: vmv.v.v v0, v8130; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma131; ZVFHMIN-NEXT: vfcvt.x.f.v v11, v10, v0.t132; ZVFHMIN-NEXT: fsrm a0133; ZVFHMIN-NEXT: vfcvt.f.x.v v11, v11, v0.t134; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu135; ZVFHMIN-NEXT: vfsgnj.vv v10, v11, v10, v0.t136; ZVFHMIN-NEXT: vmv1r.v v0, v9137; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma138; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t139; ZVFHMIN-NEXT: ret140 %v = call <4 x half> @llvm.vp.roundeven.v4f16(<4 x half> %va, <4 x i1> %m, i32 %evl)141 ret <4 x half> %v142}143 144define <4 x half> @vp_roundeven_v4f16_unmasked(<4 x half> %va, i32 zeroext %evl) {145; ZVFH-LABEL: vp_roundeven_v4f16_unmasked:146; ZVFH: # %bb.0:147; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma148; ZVFH-NEXT: vfabs.v v9, v8149; ZVFH-NEXT: li a0, 25150; ZVFH-NEXT: slli a0, a0, 10151; ZVFH-NEXT: fmv.h.x fa5, a0152; ZVFH-NEXT: vmflt.vf v0, v9, fa5153; ZVFH-NEXT: fsrmi a0, 0154; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t155; ZVFH-NEXT: fsrm a0156; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t157; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, mu158; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t159; ZVFH-NEXT: ret160;161; ZVFHMIN-LABEL: vp_roundeven_v4f16_unmasked:162; ZVFHMIN: # %bb.0:163; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma164; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8165; ZVFHMIN-NEXT: lui a0, 307200166; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma167; ZVFHMIN-NEXT: vfabs.v v8, v9168; ZVFHMIN-NEXT: fmv.w.x fa5, a0169; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5170; ZVFHMIN-NEXT: fsrmi a0, 0171; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t172; ZVFHMIN-NEXT: fsrm a0173; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t174; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu175; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t176; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma177; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9178; ZVFHMIN-NEXT: ret179 %v = call <4 x half> @llvm.vp.roundeven.v4f16(<4 x half> %va, <4 x i1> splat (i1 true), i32 %evl)180 ret <4 x half> %v181}182 183define <8 x half> @vp_roundeven_v8f16(<8 x half> %va, <8 x i1> %m, i32 zeroext %evl) {184; ZVFH-LABEL: vp_roundeven_v8f16:185; ZVFH: # %bb.0:186; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma187; ZVFH-NEXT: vfabs.v v9, v8, v0.t188; ZVFH-NEXT: li a0, 25189; ZVFH-NEXT: slli a0, a0, 10190; ZVFH-NEXT: fmv.h.x fa5, a0191; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu192; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t193; ZVFH-NEXT: fsrmi a0, 0194; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, ma195; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t196; ZVFH-NEXT: fsrm a0197; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t198; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu199; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t200; ZVFH-NEXT: ret201;202; ZVFHMIN-LABEL: vp_roundeven_v8f16:203; ZVFHMIN: # %bb.0:204; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma205; ZVFHMIN-NEXT: vmv1r.v v9, v0206; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t207; ZVFHMIN-NEXT: lui a0, 307200208; ZVFHMIN-NEXT: vmv1r.v v8, v0209; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma210; ZVFHMIN-NEXT: vfabs.v v12, v10, v0.t211; ZVFHMIN-NEXT: fmv.w.x fa5, a0212; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu213; ZVFHMIN-NEXT: vmflt.vf v8, v12, fa5, v0.t214; ZVFHMIN-NEXT: fsrmi a0, 0215; ZVFHMIN-NEXT: vmv1r.v v0, v8216; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma217; ZVFHMIN-NEXT: vfcvt.x.f.v v12, v10, v0.t218; ZVFHMIN-NEXT: fsrm a0219; ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t220; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu221; ZVFHMIN-NEXT: vfsgnj.vv v10, v12, v10, v0.t222; ZVFHMIN-NEXT: vmv1r.v v0, v9223; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma224; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t225; ZVFHMIN-NEXT: ret226 %v = call <8 x half> @llvm.vp.roundeven.v8f16(<8 x half> %va, <8 x i1> %m, i32 %evl)227 ret <8 x half> %v228}229 230define <8 x half> @vp_roundeven_v8f16_unmasked(<8 x half> %va, i32 zeroext %evl) {231; ZVFH-LABEL: vp_roundeven_v8f16_unmasked:232; ZVFH: # %bb.0:233; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma234; ZVFH-NEXT: vfabs.v v9, v8235; ZVFH-NEXT: li a0, 25236; ZVFH-NEXT: slli a0, a0, 10237; ZVFH-NEXT: fmv.h.x fa5, a0238; ZVFH-NEXT: vmflt.vf v0, v9, fa5239; ZVFH-NEXT: fsrmi a0, 0240; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t241; ZVFH-NEXT: fsrm a0242; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t243; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu244; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t245; ZVFH-NEXT: ret246;247; ZVFHMIN-LABEL: vp_roundeven_v8f16_unmasked:248; ZVFHMIN: # %bb.0:249; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma250; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8251; ZVFHMIN-NEXT: lui a0, 307200252; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma253; ZVFHMIN-NEXT: vfabs.v v8, v10254; ZVFHMIN-NEXT: fmv.w.x fa5, a0255; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5256; ZVFHMIN-NEXT: fsrmi a0, 0257; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v10, v0.t258; ZVFHMIN-NEXT: fsrm a0259; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t260; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu261; ZVFHMIN-NEXT: vfsgnj.vv v10, v8, v10, v0.t262; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma263; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10264; ZVFHMIN-NEXT: ret265 %v = call <8 x half> @llvm.vp.roundeven.v8f16(<8 x half> %va, <8 x i1> splat (i1 true), i32 %evl)266 ret <8 x half> %v267}268 269define <16 x half> @vp_roundeven_v16f16(<16 x half> %va, <16 x i1> %m, i32 zeroext %evl) {270; ZVFH-LABEL: vp_roundeven_v16f16:271; ZVFH: # %bb.0:272; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma273; ZVFH-NEXT: vmv1r.v v10, v0274; ZVFH-NEXT: vfabs.v v12, v8, v0.t275; ZVFH-NEXT: li a0, 25276; ZVFH-NEXT: slli a0, a0, 10277; ZVFH-NEXT: fmv.h.x fa5, a0278; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, mu279; ZVFH-NEXT: vmflt.vf v10, v12, fa5, v0.t280; ZVFH-NEXT: fsrmi a0, 0281; ZVFH-NEXT: vmv1r.v v0, v10282; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, ma283; ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t284; ZVFH-NEXT: fsrm a0285; ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t286; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, mu287; ZVFH-NEXT: vfsgnj.vv v8, v12, v8, v0.t288; ZVFH-NEXT: ret289;290; ZVFHMIN-LABEL: vp_roundeven_v16f16:291; ZVFHMIN: # %bb.0:292; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma293; ZVFHMIN-NEXT: vmv1r.v v10, v0294; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8, v0.t295; ZVFHMIN-NEXT: lui a0, 307200296; ZVFHMIN-NEXT: vmv1r.v v8, v0297; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma298; ZVFHMIN-NEXT: vfabs.v v16, v12, v0.t299; ZVFHMIN-NEXT: fmv.w.x fa5, a0300; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu301; ZVFHMIN-NEXT: vmflt.vf v8, v16, fa5, v0.t302; ZVFHMIN-NEXT: fsrmi a0, 0303; ZVFHMIN-NEXT: vmv1r.v v0, v8304; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma305; ZVFHMIN-NEXT: vfcvt.x.f.v v16, v12, v0.t306; ZVFHMIN-NEXT: fsrm a0307; ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t308; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu309; ZVFHMIN-NEXT: vfsgnj.vv v12, v16, v12, v0.t310; ZVFHMIN-NEXT: vmv1r.v v0, v10311; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma312; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12, v0.t313; ZVFHMIN-NEXT: ret314 %v = call <16 x half> @llvm.vp.roundeven.v16f16(<16 x half> %va, <16 x i1> %m, i32 %evl)315 ret <16 x half> %v316}317 318define <16 x half> @vp_roundeven_v16f16_unmasked(<16 x half> %va, i32 zeroext %evl) {319; ZVFH-LABEL: vp_roundeven_v16f16_unmasked:320; ZVFH: # %bb.0:321; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma322; ZVFH-NEXT: vfabs.v v10, v8323; ZVFH-NEXT: li a0, 25324; ZVFH-NEXT: slli a0, a0, 10325; ZVFH-NEXT: fmv.h.x fa5, a0326; ZVFH-NEXT: vmflt.vf v0, v10, fa5327; ZVFH-NEXT: fsrmi a0, 0328; ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t329; ZVFH-NEXT: fsrm a0330; ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t331; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, mu332; ZVFH-NEXT: vfsgnj.vv v8, v10, v8, v0.t333; ZVFH-NEXT: ret334;335; ZVFHMIN-LABEL: vp_roundeven_v16f16_unmasked:336; ZVFHMIN: # %bb.0:337; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma338; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8339; ZVFHMIN-NEXT: lui a0, 307200340; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma341; ZVFHMIN-NEXT: vfabs.v v8, v12342; ZVFHMIN-NEXT: fmv.w.x fa5, a0343; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5344; ZVFHMIN-NEXT: fsrmi a0, 0345; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v12, v0.t346; ZVFHMIN-NEXT: fsrm a0347; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t348; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu349; ZVFHMIN-NEXT: vfsgnj.vv v12, v8, v12, v0.t350; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma351; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12352; ZVFHMIN-NEXT: ret353 %v = call <16 x half> @llvm.vp.roundeven.v16f16(<16 x half> %va, <16 x i1> splat (i1 true), i32 %evl)354 ret <16 x half> %v355}356 357define <2 x float> @vp_roundeven_v2f32(<2 x float> %va, <2 x i1> %m, i32 zeroext %evl) {358; CHECK-LABEL: vp_roundeven_v2f32:359; CHECK: # %bb.0:360; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma361; CHECK-NEXT: vfabs.v v9, v8, v0.t362; CHECK-NEXT: lui a0, 307200363; CHECK-NEXT: fmv.w.x fa5, a0364; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu365; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t366; CHECK-NEXT: fsrmi a0, 0367; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma368; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t369; CHECK-NEXT: fsrm a0370; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t371; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu372; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t373; CHECK-NEXT: ret374 %v = call <2 x float> @llvm.vp.roundeven.v2f32(<2 x float> %va, <2 x i1> %m, i32 %evl)375 ret <2 x float> %v376}377 378define <2 x float> @vp_roundeven_v2f32_unmasked(<2 x float> %va, i32 zeroext %evl) {379; CHECK-LABEL: vp_roundeven_v2f32_unmasked:380; CHECK: # %bb.0:381; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma382; CHECK-NEXT: vfabs.v v9, v8383; CHECK-NEXT: lui a0, 307200384; CHECK-NEXT: fmv.w.x fa5, a0385; CHECK-NEXT: vmflt.vf v0, v9, fa5386; CHECK-NEXT: fsrmi a0, 0387; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t388; CHECK-NEXT: fsrm a0389; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t390; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu391; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t392; CHECK-NEXT: ret393 %v = call <2 x float> @llvm.vp.roundeven.v2f32(<2 x float> %va, <2 x i1> splat (i1 true), i32 %evl)394 ret <2 x float> %v395}396 397define <4 x float> @vp_roundeven_v4f32(<4 x float> %va, <4 x i1> %m, i32 zeroext %evl) {398; CHECK-LABEL: vp_roundeven_v4f32:399; CHECK: # %bb.0:400; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma401; CHECK-NEXT: vfabs.v v9, v8, v0.t402; CHECK-NEXT: lui a0, 307200403; CHECK-NEXT: fmv.w.x fa5, a0404; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu405; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t406; CHECK-NEXT: fsrmi a0, 0407; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma408; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t409; CHECK-NEXT: fsrm a0410; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t411; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu412; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t413; CHECK-NEXT: ret414 %v = call <4 x float> @llvm.vp.roundeven.v4f32(<4 x float> %va, <4 x i1> %m, i32 %evl)415 ret <4 x float> %v416}417 418define <4 x float> @vp_roundeven_v4f32_unmasked(<4 x float> %va, i32 zeroext %evl) {419; CHECK-LABEL: vp_roundeven_v4f32_unmasked:420; CHECK: # %bb.0:421; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma422; CHECK-NEXT: vfabs.v v9, v8423; CHECK-NEXT: lui a0, 307200424; CHECK-NEXT: fmv.w.x fa5, a0425; CHECK-NEXT: vmflt.vf v0, v9, fa5426; CHECK-NEXT: fsrmi a0, 0427; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t428; CHECK-NEXT: fsrm a0429; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t430; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu431; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t432; CHECK-NEXT: ret433 %v = call <4 x float> @llvm.vp.roundeven.v4f32(<4 x float> %va, <4 x i1> splat (i1 true), i32 %evl)434 ret <4 x float> %v435}436 437define <8 x float> @vp_roundeven_v8f32(<8 x float> %va, <8 x i1> %m, i32 zeroext %evl) {438; CHECK-LABEL: vp_roundeven_v8f32:439; CHECK: # %bb.0:440; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma441; CHECK-NEXT: vmv1r.v v10, v0442; CHECK-NEXT: vfabs.v v12, v8, v0.t443; CHECK-NEXT: lui a0, 307200444; CHECK-NEXT: fmv.w.x fa5, a0445; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu446; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t447; CHECK-NEXT: fsrmi a0, 0448; CHECK-NEXT: vmv1r.v v0, v10449; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma450; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t451; CHECK-NEXT: fsrm a0452; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t453; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu454; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t455; CHECK-NEXT: ret456 %v = call <8 x float> @llvm.vp.roundeven.v8f32(<8 x float> %va, <8 x i1> %m, i32 %evl)457 ret <8 x float> %v458}459 460define <8 x float> @vp_roundeven_v8f32_unmasked(<8 x float> %va, i32 zeroext %evl) {461; CHECK-LABEL: vp_roundeven_v8f32_unmasked:462; CHECK: # %bb.0:463; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma464; CHECK-NEXT: vfabs.v v10, v8465; CHECK-NEXT: lui a0, 307200466; CHECK-NEXT: fmv.w.x fa5, a0467; CHECK-NEXT: vmflt.vf v0, v10, fa5468; CHECK-NEXT: fsrmi a0, 0469; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t470; CHECK-NEXT: fsrm a0471; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t472; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu473; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t474; CHECK-NEXT: ret475 %v = call <8 x float> @llvm.vp.roundeven.v8f32(<8 x float> %va, <8 x i1> splat (i1 true), i32 %evl)476 ret <8 x float> %v477}478 479define <16 x float> @vp_roundeven_v16f32(<16 x float> %va, <16 x i1> %m, i32 zeroext %evl) {480; CHECK-LABEL: vp_roundeven_v16f32:481; CHECK: # %bb.0:482; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma483; CHECK-NEXT: vmv1r.v v12, v0484; CHECK-NEXT: vfabs.v v16, v8, v0.t485; CHECK-NEXT: lui a0, 307200486; CHECK-NEXT: fmv.w.x fa5, a0487; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu488; CHECK-NEXT: vmflt.vf v12, v16, fa5, v0.t489; CHECK-NEXT: fsrmi a0, 0490; CHECK-NEXT: vmv1r.v v0, v12491; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma492; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t493; CHECK-NEXT: fsrm a0494; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t495; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu496; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t497; CHECK-NEXT: ret498 %v = call <16 x float> @llvm.vp.roundeven.v16f32(<16 x float> %va, <16 x i1> %m, i32 %evl)499 ret <16 x float> %v500}501 502define <16 x float> @vp_roundeven_v16f32_unmasked(<16 x float> %va, i32 zeroext %evl) {503; CHECK-LABEL: vp_roundeven_v16f32_unmasked:504; CHECK: # %bb.0:505; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma506; CHECK-NEXT: vfabs.v v12, v8507; CHECK-NEXT: lui a0, 307200508; CHECK-NEXT: fmv.w.x fa5, a0509; CHECK-NEXT: vmflt.vf v0, v12, fa5510; CHECK-NEXT: fsrmi a0, 0511; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t512; CHECK-NEXT: fsrm a0513; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t514; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu515; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t516; CHECK-NEXT: ret517 %v = call <16 x float> @llvm.vp.roundeven.v16f32(<16 x float> %va, <16 x i1> splat (i1 true), i32 %evl)518 ret <16 x float> %v519}520 521define <2 x double> @vp_roundeven_v2f64(<2 x double> %va, <2 x i1> %m, i32 zeroext %evl) {522; RV32ZVFH-LABEL: vp_roundeven_v2f64:523; RV32ZVFH: # %bb.0:524; RV32ZVFH-NEXT: lui a1, %hi(.LCPI16_0)525; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI16_0)(a1)526; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m1, ta, ma527; RV32ZVFH-NEXT: vfabs.v v9, v8, v0.t528; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu529; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t530; RV32ZVFH-NEXT: fsrmi a0, 0531; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, ma532; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t533; RV32ZVFH-NEXT: fsrm a0534; RV32ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t535; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu536; RV32ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t537; RV32ZVFH-NEXT: ret538;539; RV64ZVFH-LABEL: vp_roundeven_v2f64:540; RV64ZVFH: # %bb.0:541; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m1, ta, ma542; RV64ZVFH-NEXT: vfabs.v v9, v8, v0.t543; RV64ZVFH-NEXT: li a0, 1075544; RV64ZVFH-NEXT: slli a0, a0, 52545; RV64ZVFH-NEXT: fmv.d.x fa5, a0546; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu547; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t548; RV64ZVFH-NEXT: fsrmi a0, 0549; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, ma550; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t551; RV64ZVFH-NEXT: fsrm a0552; RV64ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t553; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu554; RV64ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t555; RV64ZVFH-NEXT: ret556;557; RV32ZVFHMIN-LABEL: vp_roundeven_v2f64:558; RV32ZVFHMIN: # %bb.0:559; RV32ZVFHMIN-NEXT: lui a1, %hi(.LCPI16_0)560; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI16_0)(a1)561; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m1, ta, ma562; RV32ZVFHMIN-NEXT: vfabs.v v9, v8, v0.t563; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu564; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5, v0.t565; RV32ZVFHMIN-NEXT: fsrmi a0, 0566; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, ma567; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t568; RV32ZVFHMIN-NEXT: fsrm a0569; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t570; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu571; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t572; RV32ZVFHMIN-NEXT: ret573;574; RV64ZVFHMIN-LABEL: vp_roundeven_v2f64:575; RV64ZVFHMIN: # %bb.0:576; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m1, ta, ma577; RV64ZVFHMIN-NEXT: vfabs.v v9, v8, v0.t578; RV64ZVFHMIN-NEXT: li a0, 1075579; RV64ZVFHMIN-NEXT: slli a0, a0, 52580; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0581; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu582; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5, v0.t583; RV64ZVFHMIN-NEXT: fsrmi a0, 0584; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, ma585; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t586; RV64ZVFHMIN-NEXT: fsrm a0587; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t588; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu589; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t590; RV64ZVFHMIN-NEXT: ret591 %v = call <2 x double> @llvm.vp.roundeven.v2f64(<2 x double> %va, <2 x i1> %m, i32 %evl)592 ret <2 x double> %v593}594 595define <2 x double> @vp_roundeven_v2f64_unmasked(<2 x double> %va, i32 zeroext %evl) {596; RV32ZVFH-LABEL: vp_roundeven_v2f64_unmasked:597; RV32ZVFH: # %bb.0:598; RV32ZVFH-NEXT: lui a1, %hi(.LCPI17_0)599; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI17_0)(a1)600; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m1, ta, ma601; RV32ZVFH-NEXT: vfabs.v v9, v8602; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5603; RV32ZVFH-NEXT: fsrmi a0, 0604; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t605; RV32ZVFH-NEXT: fsrm a0606; RV32ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t607; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu608; RV32ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t609; RV32ZVFH-NEXT: ret610;611; RV64ZVFH-LABEL: vp_roundeven_v2f64_unmasked:612; RV64ZVFH: # %bb.0:613; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m1, ta, ma614; RV64ZVFH-NEXT: vfabs.v v9, v8615; RV64ZVFH-NEXT: li a0, 1075616; RV64ZVFH-NEXT: slli a0, a0, 52617; RV64ZVFH-NEXT: fmv.d.x fa5, a0618; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5619; RV64ZVFH-NEXT: fsrmi a0, 0620; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t621; RV64ZVFH-NEXT: fsrm a0622; RV64ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t623; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu624; RV64ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t625; RV64ZVFH-NEXT: ret626;627; RV32ZVFHMIN-LABEL: vp_roundeven_v2f64_unmasked:628; RV32ZVFHMIN: # %bb.0:629; RV32ZVFHMIN-NEXT: lui a1, %hi(.LCPI17_0)630; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI17_0)(a1)631; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m1, ta, ma632; RV32ZVFHMIN-NEXT: vfabs.v v9, v8633; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5634; RV32ZVFHMIN-NEXT: fsrmi a0, 0635; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t636; RV32ZVFHMIN-NEXT: fsrm a0637; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t638; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu639; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t640; RV32ZVFHMIN-NEXT: ret641;642; RV64ZVFHMIN-LABEL: vp_roundeven_v2f64_unmasked:643; RV64ZVFHMIN: # %bb.0:644; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m1, ta, ma645; RV64ZVFHMIN-NEXT: vfabs.v v9, v8646; RV64ZVFHMIN-NEXT: li a0, 1075647; RV64ZVFHMIN-NEXT: slli a0, a0, 52648; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0649; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5650; RV64ZVFHMIN-NEXT: fsrmi a0, 0651; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t652; RV64ZVFHMIN-NEXT: fsrm a0653; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t654; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu655; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t656; RV64ZVFHMIN-NEXT: ret657 %v = call <2 x double> @llvm.vp.roundeven.v2f64(<2 x double> %va, <2 x i1> splat (i1 true), i32 %evl)658 ret <2 x double> %v659}660 661define <4 x double> @vp_roundeven_v4f64(<4 x double> %va, <4 x i1> %m, i32 zeroext %evl) {662; RV32ZVFH-LABEL: vp_roundeven_v4f64:663; RV32ZVFH: # %bb.0:664; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m2, ta, ma665; RV32ZVFH-NEXT: vmv1r.v v10, v0666; RV32ZVFH-NEXT: lui a0, %hi(.LCPI18_0)667; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI18_0)(a0)668; RV32ZVFH-NEXT: vfabs.v v12, v8, v0.t669; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m2, ta, mu670; RV32ZVFH-NEXT: vmflt.vf v10, v12, fa5, v0.t671; RV32ZVFH-NEXT: fsrmi a0, 0672; RV32ZVFH-NEXT: vmv1r.v v0, v10673; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m2, ta, ma674; RV32ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t675; RV32ZVFH-NEXT: fsrm a0676; RV32ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t677; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m2, ta, mu678; RV32ZVFH-NEXT: vfsgnj.vv v8, v12, v8, v0.t679; RV32ZVFH-NEXT: ret680;681; RV64ZVFH-LABEL: vp_roundeven_v4f64:682; RV64ZVFH: # %bb.0:683; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m2, ta, ma684; RV64ZVFH-NEXT: vmv1r.v v10, v0685; RV64ZVFH-NEXT: vfabs.v v12, v8, v0.t686; RV64ZVFH-NEXT: li a0, 1075687; RV64ZVFH-NEXT: slli a0, a0, 52688; RV64ZVFH-NEXT: fmv.d.x fa5, a0689; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m2, ta, mu690; RV64ZVFH-NEXT: vmflt.vf v10, v12, fa5, v0.t691; RV64ZVFH-NEXT: fsrmi a0, 0692; RV64ZVFH-NEXT: vmv1r.v v0, v10693; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m2, ta, ma694; RV64ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t695; RV64ZVFH-NEXT: fsrm a0696; RV64ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t697; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m2, ta, mu698; RV64ZVFH-NEXT: vfsgnj.vv v8, v12, v8, v0.t699; RV64ZVFH-NEXT: ret700;701; RV32ZVFHMIN-LABEL: vp_roundeven_v4f64:702; RV32ZVFHMIN: # %bb.0:703; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m2, ta, ma704; RV32ZVFHMIN-NEXT: vmv1r.v v10, v0705; RV32ZVFHMIN-NEXT: lui a0, %hi(.LCPI18_0)706; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI18_0)(a0)707; RV32ZVFHMIN-NEXT: vfabs.v v12, v8, v0.t708; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m2, ta, mu709; RV32ZVFHMIN-NEXT: vmflt.vf v10, v12, fa5, v0.t710; RV32ZVFHMIN-NEXT: fsrmi a0, 0711; RV32ZVFHMIN-NEXT: vmv1r.v v0, v10712; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m2, ta, ma713; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t714; RV32ZVFHMIN-NEXT: fsrm a0715; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t716; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m2, ta, mu717; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v12, v8, v0.t718; RV32ZVFHMIN-NEXT: ret719;720; RV64ZVFHMIN-LABEL: vp_roundeven_v4f64:721; RV64ZVFHMIN: # %bb.0:722; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m2, ta, ma723; RV64ZVFHMIN-NEXT: vmv1r.v v10, v0724; RV64ZVFHMIN-NEXT: vfabs.v v12, v8, v0.t725; RV64ZVFHMIN-NEXT: li a0, 1075726; RV64ZVFHMIN-NEXT: slli a0, a0, 52727; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0728; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m2, ta, mu729; RV64ZVFHMIN-NEXT: vmflt.vf v10, v12, fa5, v0.t730; RV64ZVFHMIN-NEXT: fsrmi a0, 0731; RV64ZVFHMIN-NEXT: vmv1r.v v0, v10732; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m2, ta, ma733; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t734; RV64ZVFHMIN-NEXT: fsrm a0735; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t736; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m2, ta, mu737; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v12, v8, v0.t738; RV64ZVFHMIN-NEXT: ret739 %v = call <4 x double> @llvm.vp.roundeven.v4f64(<4 x double> %va, <4 x i1> %m, i32 %evl)740 ret <4 x double> %v741}742 743define <4 x double> @vp_roundeven_v4f64_unmasked(<4 x double> %va, i32 zeroext %evl) {744; RV32ZVFH-LABEL: vp_roundeven_v4f64_unmasked:745; RV32ZVFH: # %bb.0:746; RV32ZVFH-NEXT: lui a1, %hi(.LCPI19_0)747; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI19_0)(a1)748; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m2, ta, ma749; RV32ZVFH-NEXT: vfabs.v v10, v8750; RV32ZVFH-NEXT: vmflt.vf v0, v10, fa5751; RV32ZVFH-NEXT: fsrmi a0, 0752; RV32ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t753; RV32ZVFH-NEXT: fsrm a0754; RV32ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t755; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m2, ta, mu756; RV32ZVFH-NEXT: vfsgnj.vv v8, v10, v8, v0.t757; RV32ZVFH-NEXT: ret758;759; RV64ZVFH-LABEL: vp_roundeven_v4f64_unmasked:760; RV64ZVFH: # %bb.0:761; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m2, ta, ma762; RV64ZVFH-NEXT: vfabs.v v10, v8763; RV64ZVFH-NEXT: li a0, 1075764; RV64ZVFH-NEXT: slli a0, a0, 52765; RV64ZVFH-NEXT: fmv.d.x fa5, a0766; RV64ZVFH-NEXT: vmflt.vf v0, v10, fa5767; RV64ZVFH-NEXT: fsrmi a0, 0768; RV64ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t769; RV64ZVFH-NEXT: fsrm a0770; RV64ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t771; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m2, ta, mu772; RV64ZVFH-NEXT: vfsgnj.vv v8, v10, v8, v0.t773; RV64ZVFH-NEXT: ret774;775; RV32ZVFHMIN-LABEL: vp_roundeven_v4f64_unmasked:776; RV32ZVFHMIN: # %bb.0:777; RV32ZVFHMIN-NEXT: lui a1, %hi(.LCPI19_0)778; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI19_0)(a1)779; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m2, ta, ma780; RV32ZVFHMIN-NEXT: vfabs.v v10, v8781; RV32ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5782; RV32ZVFHMIN-NEXT: fsrmi a0, 0783; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t784; RV32ZVFHMIN-NEXT: fsrm a0785; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t786; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m2, ta, mu787; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v10, v8, v0.t788; RV32ZVFHMIN-NEXT: ret789;790; RV64ZVFHMIN-LABEL: vp_roundeven_v4f64_unmasked:791; RV64ZVFHMIN: # %bb.0:792; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m2, ta, ma793; RV64ZVFHMIN-NEXT: vfabs.v v10, v8794; RV64ZVFHMIN-NEXT: li a0, 1075795; RV64ZVFHMIN-NEXT: slli a0, a0, 52796; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0797; RV64ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5798; RV64ZVFHMIN-NEXT: fsrmi a0, 0799; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t800; RV64ZVFHMIN-NEXT: fsrm a0801; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t802; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m2, ta, mu803; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v10, v8, v0.t804; RV64ZVFHMIN-NEXT: ret805 %v = call <4 x double> @llvm.vp.roundeven.v4f64(<4 x double> %va, <4 x i1> splat (i1 true), i32 %evl)806 ret <4 x double> %v807}808 809define <8 x double> @vp_roundeven_v8f64(<8 x double> %va, <8 x i1> %m, i32 zeroext %evl) {810; RV32ZVFH-LABEL: vp_roundeven_v8f64:811; RV32ZVFH: # %bb.0:812; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m4, ta, ma813; RV32ZVFH-NEXT: vmv1r.v v12, v0814; RV32ZVFH-NEXT: lui a0, %hi(.LCPI20_0)815; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI20_0)(a0)816; RV32ZVFH-NEXT: vfabs.v v16, v8, v0.t817; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m4, ta, mu818; RV32ZVFH-NEXT: vmflt.vf v12, v16, fa5, v0.t819; RV32ZVFH-NEXT: fsrmi a0, 0820; RV32ZVFH-NEXT: vmv1r.v v0, v12821; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m4, ta, ma822; RV32ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t823; RV32ZVFH-NEXT: fsrm a0824; RV32ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t825; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m4, ta, mu826; RV32ZVFH-NEXT: vfsgnj.vv v8, v16, v8, v0.t827; RV32ZVFH-NEXT: ret828;829; RV64ZVFH-LABEL: vp_roundeven_v8f64:830; RV64ZVFH: # %bb.0:831; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m4, ta, ma832; RV64ZVFH-NEXT: vmv1r.v v12, v0833; RV64ZVFH-NEXT: vfabs.v v16, v8, v0.t834; RV64ZVFH-NEXT: li a0, 1075835; RV64ZVFH-NEXT: slli a0, a0, 52836; RV64ZVFH-NEXT: fmv.d.x fa5, a0837; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m4, ta, mu838; RV64ZVFH-NEXT: vmflt.vf v12, v16, fa5, v0.t839; RV64ZVFH-NEXT: fsrmi a0, 0840; RV64ZVFH-NEXT: vmv1r.v v0, v12841; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m4, ta, ma842; RV64ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t843; RV64ZVFH-NEXT: fsrm a0844; RV64ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t845; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m4, ta, mu846; RV64ZVFH-NEXT: vfsgnj.vv v8, v16, v8, v0.t847; RV64ZVFH-NEXT: ret848;849; RV32ZVFHMIN-LABEL: vp_roundeven_v8f64:850; RV32ZVFHMIN: # %bb.0:851; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m4, ta, ma852; RV32ZVFHMIN-NEXT: vmv1r.v v12, v0853; RV32ZVFHMIN-NEXT: lui a0, %hi(.LCPI20_0)854; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI20_0)(a0)855; RV32ZVFHMIN-NEXT: vfabs.v v16, v8, v0.t856; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m4, ta, mu857; RV32ZVFHMIN-NEXT: vmflt.vf v12, v16, fa5, v0.t858; RV32ZVFHMIN-NEXT: fsrmi a0, 0859; RV32ZVFHMIN-NEXT: vmv1r.v v0, v12860; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m4, ta, ma861; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t862; RV32ZVFHMIN-NEXT: fsrm a0863; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t864; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m4, ta, mu865; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v16, v8, v0.t866; RV32ZVFHMIN-NEXT: ret867;868; RV64ZVFHMIN-LABEL: vp_roundeven_v8f64:869; RV64ZVFHMIN: # %bb.0:870; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m4, ta, ma871; RV64ZVFHMIN-NEXT: vmv1r.v v12, v0872; RV64ZVFHMIN-NEXT: vfabs.v v16, v8, v0.t873; RV64ZVFHMIN-NEXT: li a0, 1075874; RV64ZVFHMIN-NEXT: slli a0, a0, 52875; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0876; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m4, ta, mu877; RV64ZVFHMIN-NEXT: vmflt.vf v12, v16, fa5, v0.t878; RV64ZVFHMIN-NEXT: fsrmi a0, 0879; RV64ZVFHMIN-NEXT: vmv1r.v v0, v12880; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m4, ta, ma881; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t882; RV64ZVFHMIN-NEXT: fsrm a0883; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t884; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m4, ta, mu885; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v16, v8, v0.t886; RV64ZVFHMIN-NEXT: ret887 %v = call <8 x double> @llvm.vp.roundeven.v8f64(<8 x double> %va, <8 x i1> %m, i32 %evl)888 ret <8 x double> %v889}890 891define <8 x double> @vp_roundeven_v8f64_unmasked(<8 x double> %va, i32 zeroext %evl) {892; RV32ZVFH-LABEL: vp_roundeven_v8f64_unmasked:893; RV32ZVFH: # %bb.0:894; RV32ZVFH-NEXT: lui a1, %hi(.LCPI21_0)895; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI21_0)(a1)896; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m4, ta, ma897; RV32ZVFH-NEXT: vfabs.v v12, v8898; RV32ZVFH-NEXT: vmflt.vf v0, v12, fa5899; RV32ZVFH-NEXT: fsrmi a0, 0900; RV32ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t901; RV32ZVFH-NEXT: fsrm a0902; RV32ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t903; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m4, ta, mu904; RV32ZVFH-NEXT: vfsgnj.vv v8, v12, v8, v0.t905; RV32ZVFH-NEXT: ret906;907; RV64ZVFH-LABEL: vp_roundeven_v8f64_unmasked:908; RV64ZVFH: # %bb.0:909; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m4, ta, ma910; RV64ZVFH-NEXT: vfabs.v v12, v8911; RV64ZVFH-NEXT: li a0, 1075912; RV64ZVFH-NEXT: slli a0, a0, 52913; RV64ZVFH-NEXT: fmv.d.x fa5, a0914; RV64ZVFH-NEXT: vmflt.vf v0, v12, fa5915; RV64ZVFH-NEXT: fsrmi a0, 0916; RV64ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t917; RV64ZVFH-NEXT: fsrm a0918; RV64ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t919; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m4, ta, mu920; RV64ZVFH-NEXT: vfsgnj.vv v8, v12, v8, v0.t921; RV64ZVFH-NEXT: ret922;923; RV32ZVFHMIN-LABEL: vp_roundeven_v8f64_unmasked:924; RV32ZVFHMIN: # %bb.0:925; RV32ZVFHMIN-NEXT: lui a1, %hi(.LCPI21_0)926; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI21_0)(a1)927; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m4, ta, ma928; RV32ZVFHMIN-NEXT: vfabs.v v12, v8929; RV32ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5930; RV32ZVFHMIN-NEXT: fsrmi a0, 0931; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t932; RV32ZVFHMIN-NEXT: fsrm a0933; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t934; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m4, ta, mu935; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v12, v8, v0.t936; RV32ZVFHMIN-NEXT: ret937;938; RV64ZVFHMIN-LABEL: vp_roundeven_v8f64_unmasked:939; RV64ZVFHMIN: # %bb.0:940; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m4, ta, ma941; RV64ZVFHMIN-NEXT: vfabs.v v12, v8942; RV64ZVFHMIN-NEXT: li a0, 1075943; RV64ZVFHMIN-NEXT: slli a0, a0, 52944; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0945; RV64ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5946; RV64ZVFHMIN-NEXT: fsrmi a0, 0947; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t948; RV64ZVFHMIN-NEXT: fsrm a0949; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t950; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m4, ta, mu951; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v12, v8, v0.t952; RV64ZVFHMIN-NEXT: ret953 %v = call <8 x double> @llvm.vp.roundeven.v8f64(<8 x double> %va, <8 x i1> splat (i1 true), i32 %evl)954 ret <8 x double> %v955}956 957define <15 x double> @vp_roundeven_v15f64(<15 x double> %va, <15 x i1> %m, i32 zeroext %evl) {958; RV32ZVFH-LABEL: vp_roundeven_v15f64:959; RV32ZVFH: # %bb.0:960; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma961; RV32ZVFH-NEXT: vmv1r.v v16, v0962; RV32ZVFH-NEXT: lui a0, %hi(.LCPI22_0)963; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI22_0)(a0)964; RV32ZVFH-NEXT: vfabs.v v24, v8, v0.t965; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu966; RV32ZVFH-NEXT: vmflt.vf v16, v24, fa5, v0.t967; RV32ZVFH-NEXT: fsrmi a0, 0968; RV32ZVFH-NEXT: vmv1r.v v0, v16969; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma970; RV32ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t971; RV32ZVFH-NEXT: fsrm a0972; RV32ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t973; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu974; RV32ZVFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t975; RV32ZVFH-NEXT: ret976;977; RV64ZVFH-LABEL: vp_roundeven_v15f64:978; RV64ZVFH: # %bb.0:979; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma980; RV64ZVFH-NEXT: vmv1r.v v16, v0981; RV64ZVFH-NEXT: vfabs.v v24, v8, v0.t982; RV64ZVFH-NEXT: li a0, 1075983; RV64ZVFH-NEXT: slli a0, a0, 52984; RV64ZVFH-NEXT: fmv.d.x fa5, a0985; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu986; RV64ZVFH-NEXT: vmflt.vf v16, v24, fa5, v0.t987; RV64ZVFH-NEXT: fsrmi a0, 0988; RV64ZVFH-NEXT: vmv1r.v v0, v16989; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma990; RV64ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t991; RV64ZVFH-NEXT: fsrm a0992; RV64ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t993; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu994; RV64ZVFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t995; RV64ZVFH-NEXT: ret996;997; RV32ZVFHMIN-LABEL: vp_roundeven_v15f64:998; RV32ZVFHMIN: # %bb.0:999; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma1000; RV32ZVFHMIN-NEXT: vmv1r.v v16, v01001; RV32ZVFHMIN-NEXT: lui a0, %hi(.LCPI22_0)1002; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI22_0)(a0)1003; RV32ZVFHMIN-NEXT: vfabs.v v24, v8, v0.t1004; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1005; RV32ZVFHMIN-NEXT: vmflt.vf v16, v24, fa5, v0.t1006; RV32ZVFHMIN-NEXT: fsrmi a0, 01007; RV32ZVFHMIN-NEXT: vmv1r.v v0, v161008; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, ma1009; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t1010; RV32ZVFHMIN-NEXT: fsrm a01011; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t1012; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1013; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v24, v8, v0.t1014; RV32ZVFHMIN-NEXT: ret1015;1016; RV64ZVFHMIN-LABEL: vp_roundeven_v15f64:1017; RV64ZVFHMIN: # %bb.0:1018; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma1019; RV64ZVFHMIN-NEXT: vmv1r.v v16, v01020; RV64ZVFHMIN-NEXT: vfabs.v v24, v8, v0.t1021; RV64ZVFHMIN-NEXT: li a0, 10751022; RV64ZVFHMIN-NEXT: slli a0, a0, 521023; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a01024; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1025; RV64ZVFHMIN-NEXT: vmflt.vf v16, v24, fa5, v0.t1026; RV64ZVFHMIN-NEXT: fsrmi a0, 01027; RV64ZVFHMIN-NEXT: vmv1r.v v0, v161028; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, ma1029; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t1030; RV64ZVFHMIN-NEXT: fsrm a01031; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t1032; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1033; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v24, v8, v0.t1034; RV64ZVFHMIN-NEXT: ret1035 %v = call <15 x double> @llvm.vp.roundeven.v15f64(<15 x double> %va, <15 x i1> %m, i32 %evl)1036 ret <15 x double> %v1037}1038 1039define <15 x double> @vp_roundeven_v15f64_unmasked(<15 x double> %va, i32 zeroext %evl) {1040; RV32ZVFH-LABEL: vp_roundeven_v15f64_unmasked:1041; RV32ZVFH: # %bb.0:1042; RV32ZVFH-NEXT: lui a1, %hi(.LCPI23_0)1043; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI23_0)(a1)1044; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma1045; RV32ZVFH-NEXT: vfabs.v v16, v81046; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa51047; RV32ZVFH-NEXT: fsrmi a0, 01048; RV32ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t1049; RV32ZVFH-NEXT: fsrm a01050; RV32ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t1051; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1052; RV32ZVFH-NEXT: vfsgnj.vv v8, v16, v8, v0.t1053; RV32ZVFH-NEXT: ret1054;1055; RV64ZVFH-LABEL: vp_roundeven_v15f64_unmasked:1056; RV64ZVFH: # %bb.0:1057; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma1058; RV64ZVFH-NEXT: vfabs.v v16, v81059; RV64ZVFH-NEXT: li a0, 10751060; RV64ZVFH-NEXT: slli a0, a0, 521061; RV64ZVFH-NEXT: fmv.d.x fa5, a01062; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa51063; RV64ZVFH-NEXT: fsrmi a0, 01064; RV64ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t1065; RV64ZVFH-NEXT: fsrm a01066; RV64ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t1067; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1068; RV64ZVFH-NEXT: vfsgnj.vv v8, v16, v8, v0.t1069; RV64ZVFH-NEXT: ret1070;1071; RV32ZVFHMIN-LABEL: vp_roundeven_v15f64_unmasked:1072; RV32ZVFHMIN: # %bb.0:1073; RV32ZVFHMIN-NEXT: lui a1, %hi(.LCPI23_0)1074; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI23_0)(a1)1075; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma1076; RV32ZVFHMIN-NEXT: vfabs.v v16, v81077; RV32ZVFHMIN-NEXT: vmflt.vf v0, v16, fa51078; RV32ZVFHMIN-NEXT: fsrmi a0, 01079; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t1080; RV32ZVFHMIN-NEXT: fsrm a01081; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t1082; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1083; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v16, v8, v0.t1084; RV32ZVFHMIN-NEXT: ret1085;1086; RV64ZVFHMIN-LABEL: vp_roundeven_v15f64_unmasked:1087; RV64ZVFHMIN: # %bb.0:1088; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma1089; RV64ZVFHMIN-NEXT: vfabs.v v16, v81090; RV64ZVFHMIN-NEXT: li a0, 10751091; RV64ZVFHMIN-NEXT: slli a0, a0, 521092; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a01093; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa51094; RV64ZVFHMIN-NEXT: fsrmi a0, 01095; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t1096; RV64ZVFHMIN-NEXT: fsrm a01097; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t1098; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1099; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v16, v8, v0.t1100; RV64ZVFHMIN-NEXT: ret1101 %v = call <15 x double> @llvm.vp.roundeven.v15f64(<15 x double> %va, <15 x i1> splat (i1 true), i32 %evl)1102 ret <15 x double> %v1103}1104 1105define <16 x double> @vp_roundeven_v16f64(<16 x double> %va, <16 x i1> %m, i32 zeroext %evl) {1106; RV32ZVFH-LABEL: vp_roundeven_v16f64:1107; RV32ZVFH: # %bb.0:1108; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma1109; RV32ZVFH-NEXT: vmv1r.v v16, v01110; RV32ZVFH-NEXT: lui a0, %hi(.LCPI24_0)1111; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI24_0)(a0)1112; RV32ZVFH-NEXT: vfabs.v v24, v8, v0.t1113; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1114; RV32ZVFH-NEXT: vmflt.vf v16, v24, fa5, v0.t1115; RV32ZVFH-NEXT: fsrmi a0, 01116; RV32ZVFH-NEXT: vmv1r.v v0, v161117; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma1118; RV32ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t1119; RV32ZVFH-NEXT: fsrm a01120; RV32ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t1121; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1122; RV32ZVFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t1123; RV32ZVFH-NEXT: ret1124;1125; RV64ZVFH-LABEL: vp_roundeven_v16f64:1126; RV64ZVFH: # %bb.0:1127; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma1128; RV64ZVFH-NEXT: vmv1r.v v16, v01129; RV64ZVFH-NEXT: vfabs.v v24, v8, v0.t1130; RV64ZVFH-NEXT: li a0, 10751131; RV64ZVFH-NEXT: slli a0, a0, 521132; RV64ZVFH-NEXT: fmv.d.x fa5, a01133; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1134; RV64ZVFH-NEXT: vmflt.vf v16, v24, fa5, v0.t1135; RV64ZVFH-NEXT: fsrmi a0, 01136; RV64ZVFH-NEXT: vmv1r.v v0, v161137; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma1138; RV64ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t1139; RV64ZVFH-NEXT: fsrm a01140; RV64ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t1141; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1142; RV64ZVFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t1143; RV64ZVFH-NEXT: ret1144;1145; RV32ZVFHMIN-LABEL: vp_roundeven_v16f64:1146; RV32ZVFHMIN: # %bb.0:1147; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma1148; RV32ZVFHMIN-NEXT: vmv1r.v v16, v01149; RV32ZVFHMIN-NEXT: lui a0, %hi(.LCPI24_0)1150; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI24_0)(a0)1151; RV32ZVFHMIN-NEXT: vfabs.v v24, v8, v0.t1152; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1153; RV32ZVFHMIN-NEXT: vmflt.vf v16, v24, fa5, v0.t1154; RV32ZVFHMIN-NEXT: fsrmi a0, 01155; RV32ZVFHMIN-NEXT: vmv1r.v v0, v161156; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, ma1157; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t1158; RV32ZVFHMIN-NEXT: fsrm a01159; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t1160; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1161; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v24, v8, v0.t1162; RV32ZVFHMIN-NEXT: ret1163;1164; RV64ZVFHMIN-LABEL: vp_roundeven_v16f64:1165; RV64ZVFHMIN: # %bb.0:1166; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma1167; RV64ZVFHMIN-NEXT: vmv1r.v v16, v01168; RV64ZVFHMIN-NEXT: vfabs.v v24, v8, v0.t1169; RV64ZVFHMIN-NEXT: li a0, 10751170; RV64ZVFHMIN-NEXT: slli a0, a0, 521171; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a01172; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1173; RV64ZVFHMIN-NEXT: vmflt.vf v16, v24, fa5, v0.t1174; RV64ZVFHMIN-NEXT: fsrmi a0, 01175; RV64ZVFHMIN-NEXT: vmv1r.v v0, v161176; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, ma1177; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t1178; RV64ZVFHMIN-NEXT: fsrm a01179; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t1180; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1181; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v24, v8, v0.t1182; RV64ZVFHMIN-NEXT: ret1183 %v = call <16 x double> @llvm.vp.roundeven.v16f64(<16 x double> %va, <16 x i1> %m, i32 %evl)1184 ret <16 x double> %v1185}1186 1187define <16 x double> @vp_roundeven_v16f64_unmasked(<16 x double> %va, i32 zeroext %evl) {1188; RV32ZVFH-LABEL: vp_roundeven_v16f64_unmasked:1189; RV32ZVFH: # %bb.0:1190; RV32ZVFH-NEXT: lui a1, %hi(.LCPI25_0)1191; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI25_0)(a1)1192; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma1193; RV32ZVFH-NEXT: vfabs.v v16, v81194; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa51195; RV32ZVFH-NEXT: fsrmi a0, 01196; RV32ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t1197; RV32ZVFH-NEXT: fsrm a01198; RV32ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t1199; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1200; RV32ZVFH-NEXT: vfsgnj.vv v8, v16, v8, v0.t1201; RV32ZVFH-NEXT: ret1202;1203; RV64ZVFH-LABEL: vp_roundeven_v16f64_unmasked:1204; RV64ZVFH: # %bb.0:1205; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma1206; RV64ZVFH-NEXT: vfabs.v v16, v81207; RV64ZVFH-NEXT: li a0, 10751208; RV64ZVFH-NEXT: slli a0, a0, 521209; RV64ZVFH-NEXT: fmv.d.x fa5, a01210; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa51211; RV64ZVFH-NEXT: fsrmi a0, 01212; RV64ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t1213; RV64ZVFH-NEXT: fsrm a01214; RV64ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t1215; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1216; RV64ZVFH-NEXT: vfsgnj.vv v8, v16, v8, v0.t1217; RV64ZVFH-NEXT: ret1218;1219; RV32ZVFHMIN-LABEL: vp_roundeven_v16f64_unmasked:1220; RV32ZVFHMIN: # %bb.0:1221; RV32ZVFHMIN-NEXT: lui a1, %hi(.LCPI25_0)1222; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI25_0)(a1)1223; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma1224; RV32ZVFHMIN-NEXT: vfabs.v v16, v81225; RV32ZVFHMIN-NEXT: vmflt.vf v0, v16, fa51226; RV32ZVFHMIN-NEXT: fsrmi a0, 01227; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t1228; RV32ZVFHMIN-NEXT: fsrm a01229; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t1230; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1231; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v16, v8, v0.t1232; RV32ZVFHMIN-NEXT: ret1233;1234; RV64ZVFHMIN-LABEL: vp_roundeven_v16f64_unmasked:1235; RV64ZVFHMIN: # %bb.0:1236; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma1237; RV64ZVFHMIN-NEXT: vfabs.v v16, v81238; RV64ZVFHMIN-NEXT: li a0, 10751239; RV64ZVFHMIN-NEXT: slli a0, a0, 521240; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a01241; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa51242; RV64ZVFHMIN-NEXT: fsrmi a0, 01243; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t1244; RV64ZVFHMIN-NEXT: fsrm a01245; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t1246; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1247; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v16, v8, v0.t1248; RV64ZVFHMIN-NEXT: ret1249 %v = call <16 x double> @llvm.vp.roundeven.v16f64(<16 x double> %va, <16 x i1> splat (i1 true), i32 %evl)1250 ret <16 x double> %v1251}1252 1253define <32 x double> @vp_roundeven_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroext %evl) {1254; RV32ZVFH-LABEL: vp_roundeven_v32f64:1255; RV32ZVFH: # %bb.0:1256; RV32ZVFH-NEXT: vsetivli zero, 2, e8, mf4, ta, ma1257; RV32ZVFH-NEXT: vmv1r.v v6, v01258; RV32ZVFH-NEXT: li a2, 161259; RV32ZVFH-NEXT: vslidedown.vi v7, v0, 21260; RV32ZVFH-NEXT: mv a1, a01261; RV32ZVFH-NEXT: bltu a0, a2, .LBB26_21262; RV32ZVFH-NEXT: # %bb.1:1263; RV32ZVFH-NEXT: li a1, 161264; RV32ZVFH-NEXT: .LBB26_2:1265; RV32ZVFH-NEXT: vmv1r.v v0, v61266; RV32ZVFH-NEXT: vsetvli zero, a1, e64, m8, ta, ma1267; RV32ZVFH-NEXT: vfabs.v v24, v8, v0.t1268; RV32ZVFH-NEXT: lui a1, %hi(.LCPI26_0)1269; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI26_0)(a1)1270; RV32ZVFH-NEXT: addi a1, a0, -161271; RV32ZVFH-NEXT: sltu a0, a0, a11272; RV32ZVFH-NEXT: addi a0, a0, -11273; RV32ZVFH-NEXT: and a0, a0, a11274; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1275; RV32ZVFH-NEXT: vmflt.vf v6, v24, fa5, v0.t1276; RV32ZVFH-NEXT: fsrmi a1, 01277; RV32ZVFH-NEXT: vmv1r.v v0, v61278; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma1279; RV32ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t1280; RV32ZVFH-NEXT: fsrm a11281; RV32ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t1282; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1283; RV32ZVFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t1284; RV32ZVFH-NEXT: vmv1r.v v0, v71285; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma1286; RV32ZVFH-NEXT: vfabs.v v24, v16, v0.t1287; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1288; RV32ZVFH-NEXT: vmflt.vf v7, v24, fa5, v0.t1289; RV32ZVFH-NEXT: fsrmi a0, 01290; RV32ZVFH-NEXT: vmv1r.v v0, v71291; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma1292; RV32ZVFH-NEXT: vfcvt.x.f.v v24, v16, v0.t1293; RV32ZVFH-NEXT: fsrm a01294; RV32ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t1295; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1296; RV32ZVFH-NEXT: vfsgnj.vv v16, v24, v16, v0.t1297; RV32ZVFH-NEXT: ret1298;1299; RV64ZVFH-LABEL: vp_roundeven_v32f64:1300; RV64ZVFH: # %bb.0:1301; RV64ZVFH-NEXT: vsetivli zero, 2, e8, mf4, ta, ma1302; RV64ZVFH-NEXT: vmv1r.v v6, v01303; RV64ZVFH-NEXT: li a2, 161304; RV64ZVFH-NEXT: vslidedown.vi v7, v0, 21305; RV64ZVFH-NEXT: mv a1, a01306; RV64ZVFH-NEXT: bltu a0, a2, .LBB26_21307; RV64ZVFH-NEXT: # %bb.1:1308; RV64ZVFH-NEXT: li a1, 161309; RV64ZVFH-NEXT: .LBB26_2:1310; RV64ZVFH-NEXT: vmv1r.v v0, v61311; RV64ZVFH-NEXT: vsetvli zero, a1, e64, m8, ta, ma1312; RV64ZVFH-NEXT: vfabs.v v24, v8, v0.t1313; RV64ZVFH-NEXT: li a1, 10751314; RV64ZVFH-NEXT: slli a1, a1, 521315; RV64ZVFH-NEXT: fmv.d.x fa5, a11316; RV64ZVFH-NEXT: addi a1, a0, -161317; RV64ZVFH-NEXT: sltu a0, a0, a11318; RV64ZVFH-NEXT: addi a0, a0, -11319; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1320; RV64ZVFH-NEXT: vmflt.vf v6, v24, fa5, v0.t1321; RV64ZVFH-NEXT: and a0, a0, a11322; RV64ZVFH-NEXT: fsrmi a1, 01323; RV64ZVFH-NEXT: vmv1r.v v0, v61324; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma1325; RV64ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t1326; RV64ZVFH-NEXT: fsrm a11327; RV64ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t1328; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1329; RV64ZVFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t1330; RV64ZVFH-NEXT: vmv1r.v v0, v71331; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma1332; RV64ZVFH-NEXT: vfabs.v v24, v16, v0.t1333; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1334; RV64ZVFH-NEXT: vmflt.vf v7, v24, fa5, v0.t1335; RV64ZVFH-NEXT: fsrmi a0, 01336; RV64ZVFH-NEXT: vmv1r.v v0, v71337; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma1338; RV64ZVFH-NEXT: vfcvt.x.f.v v24, v16, v0.t1339; RV64ZVFH-NEXT: fsrm a01340; RV64ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t1341; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1342; RV64ZVFH-NEXT: vfsgnj.vv v16, v24, v16, v0.t1343; RV64ZVFH-NEXT: ret1344;1345; RV32ZVFHMIN-LABEL: vp_roundeven_v32f64:1346; RV32ZVFHMIN: # %bb.0:1347; RV32ZVFHMIN-NEXT: vsetivli zero, 2, e8, mf4, ta, ma1348; RV32ZVFHMIN-NEXT: vmv1r.v v6, v01349; RV32ZVFHMIN-NEXT: li a2, 161350; RV32ZVFHMIN-NEXT: vslidedown.vi v7, v0, 21351; RV32ZVFHMIN-NEXT: mv a1, a01352; RV32ZVFHMIN-NEXT: bltu a0, a2, .LBB26_21353; RV32ZVFHMIN-NEXT: # %bb.1:1354; RV32ZVFHMIN-NEXT: li a1, 161355; RV32ZVFHMIN-NEXT: .LBB26_2:1356; RV32ZVFHMIN-NEXT: vmv1r.v v0, v61357; RV32ZVFHMIN-NEXT: vsetvli zero, a1, e64, m8, ta, ma1358; RV32ZVFHMIN-NEXT: vfabs.v v24, v8, v0.t1359; RV32ZVFHMIN-NEXT: lui a1, %hi(.LCPI26_0)1360; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI26_0)(a1)1361; RV32ZVFHMIN-NEXT: addi a1, a0, -161362; RV32ZVFHMIN-NEXT: sltu a0, a0, a11363; RV32ZVFHMIN-NEXT: addi a0, a0, -11364; RV32ZVFHMIN-NEXT: and a0, a0, a11365; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1366; RV32ZVFHMIN-NEXT: vmflt.vf v6, v24, fa5, v0.t1367; RV32ZVFHMIN-NEXT: fsrmi a1, 01368; RV32ZVFHMIN-NEXT: vmv1r.v v0, v61369; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, ma1370; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t1371; RV32ZVFHMIN-NEXT: fsrm a11372; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t1373; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1374; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v24, v8, v0.t1375; RV32ZVFHMIN-NEXT: vmv1r.v v0, v71376; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma1377; RV32ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t1378; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1379; RV32ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5, v0.t1380; RV32ZVFHMIN-NEXT: fsrmi a0, 01381; RV32ZVFHMIN-NEXT: vmv1r.v v0, v71382; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, ma1383; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t1384; RV32ZVFHMIN-NEXT: fsrm a01385; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t1386; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1387; RV32ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t1388; RV32ZVFHMIN-NEXT: ret1389;1390; RV64ZVFHMIN-LABEL: vp_roundeven_v32f64:1391; RV64ZVFHMIN: # %bb.0:1392; RV64ZVFHMIN-NEXT: vsetivli zero, 2, e8, mf4, ta, ma1393; RV64ZVFHMIN-NEXT: vmv1r.v v6, v01394; RV64ZVFHMIN-NEXT: li a2, 161395; RV64ZVFHMIN-NEXT: vslidedown.vi v7, v0, 21396; RV64ZVFHMIN-NEXT: mv a1, a01397; RV64ZVFHMIN-NEXT: bltu a0, a2, .LBB26_21398; RV64ZVFHMIN-NEXT: # %bb.1:1399; RV64ZVFHMIN-NEXT: li a1, 161400; RV64ZVFHMIN-NEXT: .LBB26_2:1401; RV64ZVFHMIN-NEXT: vmv1r.v v0, v61402; RV64ZVFHMIN-NEXT: vsetvli zero, a1, e64, m8, ta, ma1403; RV64ZVFHMIN-NEXT: vfabs.v v24, v8, v0.t1404; RV64ZVFHMIN-NEXT: li a1, 10751405; RV64ZVFHMIN-NEXT: slli a1, a1, 521406; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a11407; RV64ZVFHMIN-NEXT: addi a1, a0, -161408; RV64ZVFHMIN-NEXT: sltu a0, a0, a11409; RV64ZVFHMIN-NEXT: addi a0, a0, -11410; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1411; RV64ZVFHMIN-NEXT: vmflt.vf v6, v24, fa5, v0.t1412; RV64ZVFHMIN-NEXT: and a0, a0, a11413; RV64ZVFHMIN-NEXT: fsrmi a1, 01414; RV64ZVFHMIN-NEXT: vmv1r.v v0, v61415; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, ma1416; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t1417; RV64ZVFHMIN-NEXT: fsrm a11418; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t1419; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1420; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v24, v8, v0.t1421; RV64ZVFHMIN-NEXT: vmv1r.v v0, v71422; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma1423; RV64ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t1424; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1425; RV64ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5, v0.t1426; RV64ZVFHMIN-NEXT: fsrmi a0, 01427; RV64ZVFHMIN-NEXT: vmv1r.v v0, v71428; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, ma1429; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t1430; RV64ZVFHMIN-NEXT: fsrm a01431; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t1432; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1433; RV64ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t1434; RV64ZVFHMIN-NEXT: ret1435 %v = call <32 x double> @llvm.vp.roundeven.v32f64(<32 x double> %va, <32 x i1> %m, i32 %evl)1436 ret <32 x double> %v1437}1438 1439define <32 x double> @vp_roundeven_v32f64_unmasked(<32 x double> %va, i32 zeroext %evl) {1440; RV32ZVFH-LABEL: vp_roundeven_v32f64_unmasked:1441; RV32ZVFH: # %bb.0:1442; RV32ZVFH-NEXT: li a2, 161443; RV32ZVFH-NEXT: mv a1, a01444; RV32ZVFH-NEXT: bltu a0, a2, .LBB27_21445; RV32ZVFH-NEXT: # %bb.1:1446; RV32ZVFH-NEXT: li a1, 161447; RV32ZVFH-NEXT: .LBB27_2:1448; RV32ZVFH-NEXT: vsetvli zero, a1, e64, m8, ta, ma1449; RV32ZVFH-NEXT: vfabs.v v24, v81450; RV32ZVFH-NEXT: lui a2, %hi(.LCPI27_0)1451; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI27_0)(a2)1452; RV32ZVFH-NEXT: addi a2, a0, -161453; RV32ZVFH-NEXT: sltu a0, a0, a21454; RV32ZVFH-NEXT: addi a0, a0, -11455; RV32ZVFH-NEXT: and a0, a0, a21456; RV32ZVFH-NEXT: fsrmi a2, 01457; RV32ZVFH-NEXT: vmflt.vf v0, v24, fa51458; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma1459; RV32ZVFH-NEXT: vfabs.v v24, v161460; RV32ZVFH-NEXT: vmflt.vf v7, v24, fa51461; RV32ZVFH-NEXT: vsetvli zero, a1, e64, m8, ta, ma1462; RV32ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t1463; RV32ZVFH-NEXT: fsrm a21464; RV32ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t1465; RV32ZVFH-NEXT: fsrmi a1, 01466; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1467; RV32ZVFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t1468; RV32ZVFH-NEXT: vmv1r.v v0, v71469; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma1470; RV32ZVFH-NEXT: vfcvt.x.f.v v24, v16, v0.t1471; RV32ZVFH-NEXT: fsrm a11472; RV32ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t1473; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1474; RV32ZVFH-NEXT: vfsgnj.vv v16, v24, v16, v0.t1475; RV32ZVFH-NEXT: ret1476;1477; RV64ZVFH-LABEL: vp_roundeven_v32f64_unmasked:1478; RV64ZVFH: # %bb.0:1479; RV64ZVFH-NEXT: li a2, 161480; RV64ZVFH-NEXT: mv a1, a01481; RV64ZVFH-NEXT: bltu a0, a2, .LBB27_21482; RV64ZVFH-NEXT: # %bb.1:1483; RV64ZVFH-NEXT: li a1, 161484; RV64ZVFH-NEXT: .LBB27_2:1485; RV64ZVFH-NEXT: vsetvli zero, a1, e64, m8, ta, ma1486; RV64ZVFH-NEXT: vfabs.v v24, v81487; RV64ZVFH-NEXT: li a2, 10751488; RV64ZVFH-NEXT: slli a2, a2, 521489; RV64ZVFH-NEXT: fmv.d.x fa5, a21490; RV64ZVFH-NEXT: addi a2, a0, -161491; RV64ZVFH-NEXT: sltu a0, a0, a21492; RV64ZVFH-NEXT: addi a0, a0, -11493; RV64ZVFH-NEXT: and a0, a0, a21494; RV64ZVFH-NEXT: fsrmi a2, 01495; RV64ZVFH-NEXT: vmflt.vf v0, v24, fa51496; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma1497; RV64ZVFH-NEXT: vfabs.v v24, v161498; RV64ZVFH-NEXT: vmflt.vf v7, v24, fa51499; RV64ZVFH-NEXT: vsetvli zero, a1, e64, m8, ta, ma1500; RV64ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t1501; RV64ZVFH-NEXT: fsrm a21502; RV64ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t1503; RV64ZVFH-NEXT: fsrmi a1, 01504; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1505; RV64ZVFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t1506; RV64ZVFH-NEXT: vmv1r.v v0, v71507; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma1508; RV64ZVFH-NEXT: vfcvt.x.f.v v24, v16, v0.t1509; RV64ZVFH-NEXT: fsrm a11510; RV64ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t1511; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1512; RV64ZVFH-NEXT: vfsgnj.vv v16, v24, v16, v0.t1513; RV64ZVFH-NEXT: ret1514;1515; RV32ZVFHMIN-LABEL: vp_roundeven_v32f64_unmasked:1516; RV32ZVFHMIN: # %bb.0:1517; RV32ZVFHMIN-NEXT: li a2, 161518; RV32ZVFHMIN-NEXT: mv a1, a01519; RV32ZVFHMIN-NEXT: bltu a0, a2, .LBB27_21520; RV32ZVFHMIN-NEXT: # %bb.1:1521; RV32ZVFHMIN-NEXT: li a1, 161522; RV32ZVFHMIN-NEXT: .LBB27_2:1523; RV32ZVFHMIN-NEXT: vsetvli zero, a1, e64, m8, ta, ma1524; RV32ZVFHMIN-NEXT: vfabs.v v24, v81525; RV32ZVFHMIN-NEXT: lui a2, %hi(.LCPI27_0)1526; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI27_0)(a2)1527; RV32ZVFHMIN-NEXT: addi a2, a0, -161528; RV32ZVFHMIN-NEXT: sltu a0, a0, a21529; RV32ZVFHMIN-NEXT: addi a0, a0, -11530; RV32ZVFHMIN-NEXT: and a0, a0, a21531; RV32ZVFHMIN-NEXT: fsrmi a2, 01532; RV32ZVFHMIN-NEXT: vmflt.vf v0, v24, fa51533; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma1534; RV32ZVFHMIN-NEXT: vfabs.v v24, v161535; RV32ZVFHMIN-NEXT: vmflt.vf v7, v24, fa51536; RV32ZVFHMIN-NEXT: vsetvli zero, a1, e64, m8, ta, ma1537; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t1538; RV32ZVFHMIN-NEXT: fsrm a21539; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t1540; RV32ZVFHMIN-NEXT: fsrmi a1, 01541; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1542; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v24, v8, v0.t1543; RV32ZVFHMIN-NEXT: vmv1r.v v0, v71544; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma1545; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t1546; RV32ZVFHMIN-NEXT: fsrm a11547; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t1548; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1549; RV32ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t1550; RV32ZVFHMIN-NEXT: ret1551;1552; RV64ZVFHMIN-LABEL: vp_roundeven_v32f64_unmasked:1553; RV64ZVFHMIN: # %bb.0:1554; RV64ZVFHMIN-NEXT: li a2, 161555; RV64ZVFHMIN-NEXT: mv a1, a01556; RV64ZVFHMIN-NEXT: bltu a0, a2, .LBB27_21557; RV64ZVFHMIN-NEXT: # %bb.1:1558; RV64ZVFHMIN-NEXT: li a1, 161559; RV64ZVFHMIN-NEXT: .LBB27_2:1560; RV64ZVFHMIN-NEXT: vsetvli zero, a1, e64, m8, ta, ma1561; RV64ZVFHMIN-NEXT: vfabs.v v24, v81562; RV64ZVFHMIN-NEXT: li a2, 10751563; RV64ZVFHMIN-NEXT: slli a2, a2, 521564; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a21565; RV64ZVFHMIN-NEXT: addi a2, a0, -161566; RV64ZVFHMIN-NEXT: sltu a0, a0, a21567; RV64ZVFHMIN-NEXT: addi a0, a0, -11568; RV64ZVFHMIN-NEXT: and a0, a0, a21569; RV64ZVFHMIN-NEXT: fsrmi a2, 01570; RV64ZVFHMIN-NEXT: vmflt.vf v0, v24, fa51571; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma1572; RV64ZVFHMIN-NEXT: vfabs.v v24, v161573; RV64ZVFHMIN-NEXT: vmflt.vf v7, v24, fa51574; RV64ZVFHMIN-NEXT: vsetvli zero, a1, e64, m8, ta, ma1575; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t1576; RV64ZVFHMIN-NEXT: fsrm a21577; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t1578; RV64ZVFHMIN-NEXT: fsrmi a1, 01579; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1580; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v24, v8, v0.t1581; RV64ZVFHMIN-NEXT: vmv1r.v v0, v71582; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma1583; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t1584; RV64ZVFHMIN-NEXT: fsrm a11585; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t1586; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1587; RV64ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t1588; RV64ZVFHMIN-NEXT: ret1589 %v = call <32 x double> @llvm.vp.roundeven.v32f64(<32 x double> %va, <32 x i1> splat (i1 true), i32 %evl)1590 ret <32 x double> %v1591}1592