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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc < %s -mtriple=riscv32 -mattr=+v | FileCheck %s3; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s4 5define signext i16 @sad_4x8_as_i16(<4 x i8> %a, <4 x i8> %b) {6; CHECK-LABEL: sad_4x8_as_i16:7; CHECK: # %bb.0: # %entry8; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma9; CHECK-NEXT: vminu.vv v10, v8, v910; CHECK-NEXT: vmaxu.vv v8, v8, v911; CHECK-NEXT: vsub.vv v8, v8, v1012; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma13; CHECK-NEXT: vmv.s.x v9, zero14; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma15; CHECK-NEXT: vwredsumu.vs v8, v8, v916; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma17; CHECK-NEXT: vmv.x.s a0, v818; CHECK-NEXT: ret19entry:20 %1 = zext <4 x i8> %a to <4 x i16>21 %3 = zext <4 x i8> %b to <4 x i16>22 %4 = sub nsw <4 x i16> %1, %323 %5 = tail call <4 x i16> @llvm.abs.v4i16(<4 x i16> %4, i1 true)24 %6 = tail call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> %5)25 ret i16 %626}27 28define signext i32 @sad_4x8_as_i32(<4 x i8> %a, <4 x i8> %b) {29; CHECK-LABEL: sad_4x8_as_i32:30; CHECK: # %bb.0: # %entry31; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma32; CHECK-NEXT: vminu.vv v10, v8, v933; CHECK-NEXT: vmaxu.vv v8, v8, v934; CHECK-NEXT: vsub.vv v8, v8, v1035; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma36; CHECK-NEXT: vzext.vf4 v9, v837; CHECK-NEXT: vmv.s.x v8, zero38; CHECK-NEXT: vredsum.vs v8, v9, v839; CHECK-NEXT: vmv.x.s a0, v840; CHECK-NEXT: ret41entry:42 %1 = zext <4 x i8> %a to <4 x i32>43 %3 = zext <4 x i8> %b to <4 x i32>44 %4 = sub nsw <4 x i32> %1, %345 %5 = tail call <4 x i32> @llvm.abs.v4i32(<4 x i32> %4, i1 true)46 %6 = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %5)47 ret i32 %648}49 50define signext i16 @sad_16x8_as_i16(<16 x i8> %a, <16 x i8> %b) {51; CHECK-LABEL: sad_16x8_as_i16:52; CHECK: # %bb.0: # %entry53; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma54; CHECK-NEXT: vminu.vv v10, v8, v955; CHECK-NEXT: vmaxu.vv v8, v8, v956; CHECK-NEXT: vsub.vv v8, v8, v1057; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma58; CHECK-NEXT: vmv.s.x v9, zero59; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma60; CHECK-NEXT: vwredsumu.vs v8, v8, v961; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma62; CHECK-NEXT: vmv.x.s a0, v863; CHECK-NEXT: ret64entry:65 %1 = zext <16 x i8> %a to <16 x i16>66 %3 = zext <16 x i8> %b to <16 x i16>67 %4 = sub nsw <16 x i16> %1, %368 %5 = tail call <16 x i16> @llvm.abs.v16i16(<16 x i16> %4, i1 true)69 %6 = tail call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %5)70 ret i16 %671}72 73define signext i32 @sad_16x8_as_i32(<16 x i8> %a, <16 x i8> %b) {74; CHECK-LABEL: sad_16x8_as_i32:75; CHECK: # %bb.0: # %entry76; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma77; CHECK-NEXT: vminu.vv v10, v8, v978; CHECK-NEXT: vmaxu.vv v8, v8, v979; CHECK-NEXT: vsub.vv v12, v8, v1080; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma81; CHECK-NEXT: vzext.vf4 v8, v1282; CHECK-NEXT: vmv.s.x v12, zero83; CHECK-NEXT: vredsum.vs v8, v8, v1284; CHECK-NEXT: vmv.x.s a0, v885; CHECK-NEXT: ret86entry:87 %1 = zext <16 x i8> %a to <16 x i32>88 %3 = zext <16 x i8> %b to <16 x i32>89 %4 = sub nsw <16 x i32> %1, %390 %5 = tail call <16 x i32> @llvm.abs.v16i32(<16 x i32> %4, i1 true)91 %6 = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %5)92 ret i32 %693}94 95define signext i32 @sad_2block_16xi8_as_i32(ptr %a, ptr %b, i32 signext %stridea, i32 signext %strideb) {96; CHECK-LABEL: sad_2block_16xi8_as_i32:97; CHECK: # %bb.0: # %entry98; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma99; CHECK-NEXT: vle8.v v8, (a0)100; CHECK-NEXT: vle8.v v9, (a1)101; CHECK-NEXT: add a0, a0, a2102; CHECK-NEXT: add a1, a1, a3103; CHECK-NEXT: vle8.v v10, (a0)104; CHECK-NEXT: vle8.v v11, (a1)105; CHECK-NEXT: add a0, a0, a2106; CHECK-NEXT: add a1, a1, a3107; CHECK-NEXT: vle8.v v12, (a0)108; CHECK-NEXT: vle8.v v13, (a1)109; CHECK-NEXT: add a0, a0, a2110; CHECK-NEXT: add a1, a1, a3111; CHECK-NEXT: vminu.vv v14, v8, v9112; CHECK-NEXT: vmaxu.vv v8, v8, v9113; CHECK-NEXT: vle8.v v9, (a0)114; CHECK-NEXT: vsub.vv v8, v8, v14115; CHECK-NEXT: vminu.vv v14, v10, v11116; CHECK-NEXT: vmaxu.vv v10, v10, v11117; CHECK-NEXT: vle8.v v11, (a1)118; CHECK-NEXT: vsub.vv v10, v10, v14119; CHECK-NEXT: vminu.vv v14, v12, v13120; CHECK-NEXT: vmaxu.vv v15, v12, v13121; CHECK-NEXT: vwaddu.vv v12, v10, v8122; CHECK-NEXT: vsub.vv v8, v15, v14123; CHECK-NEXT: vminu.vv v10, v9, v11124; CHECK-NEXT: vmaxu.vv v9, v9, v11125; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma126; CHECK-NEXT: vzext.vf2 v14, v8127; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma128; CHECK-NEXT: vsub.vv v16, v9, v10129; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma130; CHECK-NEXT: vwaddu.vv v8, v14, v12131; CHECK-NEXT: vzext.vf2 v12, v16132; CHECK-NEXT: vwaddu.wv v8, v8, v12133; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma134; CHECK-NEXT: vmv.s.x v12, zero135; CHECK-NEXT: vredsum.vs v8, v8, v12136; CHECK-NEXT: vmv.x.s a0, v8137; CHECK-NEXT: ret138entry:139 %idx.ext8 = sext i32 %strideb to i64140 %idx.ext = sext i32 %stridea to i64141 %0 = load <16 x i8>, ptr %a, align 1142 %1 = zext <16 x i8> %0 to <16 x i32>143 %2 = load <16 x i8>, ptr %b, align 1144 %3 = zext <16 x i8> %2 to <16 x i32>145 %4 = sub nsw <16 x i32> %1, %3146 %5 = tail call <16 x i32> @llvm.abs.v16i32(<16 x i32> %4, i1 true)147 %6 = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %5)148 %add.ptr = getelementptr inbounds i8, ptr %a, i64 %idx.ext149 %add.ptr9 = getelementptr inbounds i8, ptr %b, i64 %idx.ext8150 %7 = load <16 x i8>, ptr %add.ptr, align 1151 %8 = zext <16 x i8> %7 to <16 x i32>152 %9 = load <16 x i8>, ptr %add.ptr9, align 1153 %10 = zext <16 x i8> %9 to <16 x i32>154 %11 = sub nsw <16 x i32> %8, %10155 %12 = tail call <16 x i32> @llvm.abs.v16i32(<16 x i32> %11, i1 true)156 %13 = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %12)157 %op.rdx.1 = add i32 %13, %6158 %add.ptr.1 = getelementptr inbounds i8, ptr %add.ptr, i64 %idx.ext159 %add.ptr9.1 = getelementptr inbounds i8, ptr %add.ptr9, i64 %idx.ext8160 %14 = load <16 x i8>, ptr %add.ptr.1, align 1161 %15 = zext <16 x i8> %14 to <16 x i32>162 %16 = load <16 x i8>, ptr %add.ptr9.1, align 1163 %17 = zext <16 x i8> %16 to <16 x i32>164 %18 = sub nsw <16 x i32> %15, %17165 %19 = tail call <16 x i32> @llvm.abs.v16i32(<16 x i32> %18, i1 true)166 %20 = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %19)167 %op.rdx.2 = add i32 %20, %op.rdx.1168 %add.ptr.2 = getelementptr inbounds i8, ptr %add.ptr.1, i64 %idx.ext169 %add.ptr9.2 = getelementptr inbounds i8, ptr %add.ptr9.1, i64 %idx.ext8170 %21 = load <16 x i8>, ptr %add.ptr.2, align 1171 %22 = zext <16 x i8> %21 to <16 x i32>172 %23 = load <16 x i8>, ptr %add.ptr9.2, align 1173 %24 = zext <16 x i8> %23 to <16 x i32>174 %25 = sub nsw <16 x i32> %22, %24175 %26 = tail call <16 x i32> @llvm.abs.v16i32(<16 x i32> %25, i1 true)176 %27 = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %26)177 %op.rdx.3 = add i32 %27, %op.rdx.2178 ret i32 %op.rdx.3179}180 181