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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \3; RUN: | FileCheck %s4; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \5; RUN: | FileCheck %s6 7 8define <1 x i32> @select_addsub_v1i32(<1 x i1> %cc, <1 x i32> %a, <1 x i32> %b) {9; CHECK-LABEL: select_addsub_v1i32:10; CHECK: # %bb.0:11; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu12; CHECK-NEXT: vrsub.vi v9, v9, 0, v0.t13; CHECK-NEXT: vadd.vv v8, v8, v914; CHECK-NEXT: ret15 %sub = sub <1 x i32> %a, %b16 %add = add <1 x i32> %a, %b17 %res = select <1 x i1> %cc, <1 x i32> %sub, <1 x i32> %add18 ret <1 x i32> %res19}20 21define <2 x i32> @select_addsub_v2i32(<2 x i1> %cc, <2 x i32> %a, <2 x i32> %b) {22; CHECK-LABEL: select_addsub_v2i32:23; CHECK: # %bb.0:24; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu25; CHECK-NEXT: vrsub.vi v9, v9, 0, v0.t26; CHECK-NEXT: vadd.vv v8, v8, v927; CHECK-NEXT: ret28 %sub = sub <2 x i32> %a, %b29 %add = add <2 x i32> %a, %b30 %res = select <2 x i1> %cc, <2 x i32> %sub, <2 x i32> %add31 ret <2 x i32> %res32}33 34define <4 x i32> @select_addsub_v4i32(<4 x i1> %cc, <4 x i32> %a, <4 x i32> %b) {35; CHECK-LABEL: select_addsub_v4i32:36; CHECK: # %bb.0:37; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu38; CHECK-NEXT: vrsub.vi v9, v9, 0, v0.t39; CHECK-NEXT: vadd.vv v8, v8, v940; CHECK-NEXT: ret41 %sub = sub <4 x i32> %a, %b42 %add = add <4 x i32> %a, %b43 %res = select <4 x i1> %cc, <4 x i32> %sub, <4 x i32> %add44 ret <4 x i32> %res45}46 47define <4 x i32> @select_addsub_v4i32_select_swapped(<4 x i1> %cc, <4 x i32> %a, <4 x i32> %b) {48; CHECK-LABEL: select_addsub_v4i32_select_swapped:49; CHECK: # %bb.0:50; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma51; CHECK-NEXT: vrsub.vi v10, v9, 052; CHECK-NEXT: vmerge.vvm v9, v10, v9, v053; CHECK-NEXT: vadd.vv v8, v8, v954; CHECK-NEXT: ret55 %sub = sub <4 x i32> %a, %b56 %add = add <4 x i32> %a, %b57 %res = select <4 x i1> %cc, <4 x i32> %add, <4 x i32> %sub58 ret <4 x i32> %res59}60 61define <4 x i32> @select_addsub_v4i32_add_swapped(<4 x i1> %cc, <4 x i32> %a, <4 x i32> %b) {62; CHECK-LABEL: select_addsub_v4i32_add_swapped:63; CHECK: # %bb.0:64; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu65; CHECK-NEXT: vrsub.vi v9, v9, 0, v0.t66; CHECK-NEXT: vadd.vv v8, v8, v967; CHECK-NEXT: ret68 %sub = sub <4 x i32> %a, %b69 %add = add <4 x i32> %b, %a70 %res = select <4 x i1> %cc, <4 x i32> %sub, <4 x i32> %add71 ret <4 x i32> %res72}73 74define <4 x i32> @select_addsub_v4i32_both_swapped(<4 x i1> %cc, <4 x i32> %a, <4 x i32> %b) {75; CHECK-LABEL: select_addsub_v4i32_both_swapped:76; CHECK: # %bb.0:77; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma78; CHECK-NEXT: vrsub.vi v10, v9, 079; CHECK-NEXT: vmerge.vvm v9, v10, v9, v080; CHECK-NEXT: vadd.vv v8, v8, v981; CHECK-NEXT: ret82 %sub = sub <4 x i32> %a, %b83 %add = add <4 x i32> %b, %a84 %res = select <4 x i1> %cc, <4 x i32> %add, <4 x i32> %sub85 ret <4 x i32> %res86}87 88define <4 x i32> @select_addsub_v4i32_sub_swapped(<4 x i1> %cc, <4 x i32> %a, <4 x i32> %b) {89; CHECK-LABEL: select_addsub_v4i32_sub_swapped:90; CHECK: # %bb.0:91; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu92; CHECK-NEXT: vrsub.vi v8, v8, 0, v0.t93; CHECK-NEXT: vadd.vv v8, v9, v894; CHECK-NEXT: ret95 %sub = sub <4 x i32> %b, %a96 %add = add <4 x i32> %a, %b97 %res = select <4 x i1> %cc, <4 x i32> %sub, <4 x i32> %add98 ret <4 x i32> %res99}100 101define <8 x i32> @select_addsub_v8i32(<8 x i1> %cc, <8 x i32> %a, <8 x i32> %b) {102; CHECK-LABEL: select_addsub_v8i32:103; CHECK: # %bb.0:104; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu105; CHECK-NEXT: vrsub.vi v10, v10, 0, v0.t106; CHECK-NEXT: vadd.vv v8, v8, v10107; CHECK-NEXT: ret108 %sub = sub <8 x i32> %a, %b109 %add = add <8 x i32> %a, %b110 %res = select <8 x i1> %cc, <8 x i32> %sub, <8 x i32> %add111 ret <8 x i32> %res112}113 114define <16 x i32> @select_addsub_v16i32(<16 x i1> %cc, <16 x i32> %a, <16 x i32> %b) {115; CHECK-LABEL: select_addsub_v16i32:116; CHECK: # %bb.0:117; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu118; CHECK-NEXT: vrsub.vi v12, v12, 0, v0.t119; CHECK-NEXT: vadd.vv v8, v8, v12120; CHECK-NEXT: ret121 %sub = sub <16 x i32> %a, %b122 %add = add <16 x i32> %a, %b123 %res = select <16 x i1> %cc, <16 x i32> %sub, <16 x i32> %add124 ret <16 x i32> %res125}126 127define <32 x i32> @select_addsub_v32i32(<32 x i1> %cc, <32 x i32> %a, <32 x i32> %b) {128; CHECK-LABEL: select_addsub_v32i32:129; CHECK: # %bb.0:130; CHECK-NEXT: li a0, 32131; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu132; CHECK-NEXT: vrsub.vi v16, v16, 0, v0.t133; CHECK-NEXT: vadd.vv v8, v8, v16134; CHECK-NEXT: ret135 %sub = sub <32 x i32> %a, %b136 %add = add <32 x i32> %a, %b137 %res = select <32 x i1> %cc, <32 x i32> %sub, <32 x i32> %add138 ret <32 x i32> %res139}140 141define <64 x i32> @select_addsub_v64i32(<64 x i1> %cc, <64 x i32> %a, <64 x i32> %b) {142; CHECK-LABEL: select_addsub_v64i32:143; CHECK: # %bb.0:144; CHECK-NEXT: addi sp, sp, -16145; CHECK-NEXT: .cfi_def_cfa_offset 16146; CHECK-NEXT: csrr a1, vlenb147; CHECK-NEXT: slli a1, a1, 3148; CHECK-NEXT: sub sp, sp, a1149; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb150; CHECK-NEXT: addi a1, sp, 16151; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill152; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma153; CHECK-NEXT: vmv8r.v v16, v8154; CHECK-NEXT: li a1, 32155; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu156; CHECK-NEXT: vle32.v v8, (a0)157; CHECK-NEXT: addi a0, a0, 128158; CHECK-NEXT: vle32.v v24, (a0)159; CHECK-NEXT: vrsub.vi v8, v8, 0, v0.t160; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma161; CHECK-NEXT: vslidedown.vi v0, v0, 4162; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu163; CHECK-NEXT: vadd.vv v8, v16, v8164; CHECK-NEXT: vrsub.vi v24, v24, 0, v0.t165; CHECK-NEXT: addi a0, sp, 16166; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload167; CHECK-NEXT: vadd.vv v16, v16, v24168; CHECK-NEXT: csrr a0, vlenb169; CHECK-NEXT: slli a0, a0, 3170; CHECK-NEXT: add sp, sp, a0171; CHECK-NEXT: .cfi_def_cfa sp, 16172; CHECK-NEXT: addi sp, sp, 16173; CHECK-NEXT: .cfi_def_cfa_offset 0174; CHECK-NEXT: ret175 %sub = sub <64 x i32> %a, %b176 %add = add <64 x i32> %a, %b177 %res = select <64 x i1> %cc, <64 x i32> %sub, <64 x i32> %add178 ret <64 x i32> %res179}180 181define <8 x i64> @select_addsub_v8i64(<8 x i1> %cc, <8 x i64> %a, <8 x i64> %b) {182; CHECK-LABEL: select_addsub_v8i64:183; CHECK: # %bb.0:184; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu185; CHECK-NEXT: vrsub.vi v12, v12, 0, v0.t186; CHECK-NEXT: vadd.vv v8, v8, v12187; CHECK-NEXT: ret188 %sub = sub <8 x i64> %a, %b189 %add = add <8 x i64> %a, %b190 %res = select <8 x i1> %cc, <8 x i64> %sub, <8 x i64> %add191 ret <8 x i64> %res192}193 194define <8 x i16> @select_addsub_v8i16(<8 x i1> %cc, <8 x i16> %a, <8 x i16> %b) {195; CHECK-LABEL: select_addsub_v8i16:196; CHECK: # %bb.0:197; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu198; CHECK-NEXT: vrsub.vi v9, v9, 0, v0.t199; CHECK-NEXT: vadd.vv v8, v8, v9200; CHECK-NEXT: ret201 %sub = sub <8 x i16> %a, %b202 %add = add <8 x i16> %a, %b203 %res = select <8 x i1> %cc, <8 x i16> %sub, <8 x i16> %add204 ret <8 x i16> %res205}206 207define <8 x i8> @select_addsub_v8i8(<8 x i1> %cc, <8 x i8> %a, <8 x i8> %b) {208; CHECK-LABEL: select_addsub_v8i8:209; CHECK: # %bb.0:210; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu211; CHECK-NEXT: vrsub.vi v9, v9, 0, v0.t212; CHECK-NEXT: vadd.vv v8, v8, v9213; CHECK-NEXT: ret214 %sub = sub <8 x i8> %a, %b215 %add = add <8 x i8> %a, %b216 %res = select <8 x i1> %cc, <8 x i8> %sub, <8 x i8> %add217 ret <8 x i8> %res218}219 220define <8 x i1> @select_addsub_v8i1(<8 x i1> %cc, <8 x i1> %a, <8 x i1> %b) {221; CHECK-LABEL: select_addsub_v8i1:222; CHECK: # %bb.0:223; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma224; CHECK-NEXT: vmxor.mm v0, v8, v9225; CHECK-NEXT: ret226 %sub = sub <8 x i1> %a, %b227 %add = add <8 x i1> %a, %b228 %res = select <8 x i1> %cc, <8 x i1> %sub, <8 x i1> %add229 ret <8 x i1> %res230}231 232define <8 x i2> @select_addsub_v8i2(<8 x i1> %cc, <8 x i2> %a, <8 x i2> %b) {233; CHECK-LABEL: select_addsub_v8i2:234; CHECK: # %bb.0:235; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu236; CHECK-NEXT: vrsub.vi v9, v9, 0, v0.t237; CHECK-NEXT: vadd.vv v8, v8, v9238; CHECK-NEXT: ret239 %sub = sub <8 x i2> %a, %b240 %add = add <8 x i2> %a, %b241 %res = select <8 x i1> %cc, <8 x i2> %sub, <8 x i2> %add242 ret <8 x i2> %res243}244 245define <4 x i32> @select_addsub_v4i32_constmask(<4 x i32> %a, <4 x i32> %b) {246; CHECK-LABEL: select_addsub_v4i32_constmask:247; CHECK: # %bb.0:248; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu249; CHECK-NEXT: vmv.v.i v0, 5250; CHECK-NEXT: vrsub.vi v9, v9, 0, v0.t251; CHECK-NEXT: vadd.vv v8, v8, v9252; CHECK-NEXT: ret253 %sub = sub <4 x i32> %a, %b254 %add = add <4 x i32> %a, %b255 %res = select <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x i32> %sub, <4 x i32> %add256 ret <4 x i32> %res257}258 259define <4 x i32> @select_addsub_v4i32_constmask2(<4 x i32> %a, <4 x i32> %b) {260; CHECK-LABEL: select_addsub_v4i32_constmask2:261; CHECK: # %bb.0:262; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu263; CHECK-NEXT: vmv.v.i v0, 10264; CHECK-NEXT: vrsub.vi v8, v8, 0, v0.t265; CHECK-NEXT: vadd.vv v8, v9, v8266; CHECK-NEXT: ret267 %sub = sub <4 x i32> %b, %a268 %add = add <4 x i32> %a, %b269 %res = select <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x i32> %add, <4 x i32> %sub270 ret <4 x i32> %res271}272 273; Same pattern as above, but the select is disguised as a shuffle274define <4 x i32> @select_addsub_v4i32_as_shuffle(<4 x i32> %a, <4 x i32> %b) {275; CHECK-LABEL: select_addsub_v4i32_as_shuffle:276; CHECK: # %bb.0:277; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu278; CHECK-NEXT: vmv.v.i v0, 5279; CHECK-NEXT: vrsub.vi v9, v9, 0, v0.t280; CHECK-NEXT: vadd.vv v8, v8, v9281; CHECK-NEXT: ret282 %sub = sub <4 x i32> %a, %b283 %add = add <4 x i32> %a, %b284 %res = shufflevector <4 x i32> %sub, <4 x i32> %add, <4 x i32> <i32 0, i32 5, i32 2, i32 7>285 ret <4 x i32> %res286}287 288; Same pattern as above, but the select is disguised as a shuffle289define <4 x i32> @select_addsub_v4i32_as_shuffle2(<4 x i32> %a, <4 x i32> %b) {290; CHECK-LABEL: select_addsub_v4i32_as_shuffle2:291; CHECK: # %bb.0:292; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu293; CHECK-NEXT: vmv.v.i v0, 10294; CHECK-NEXT: vrsub.vi v8, v8, 0, v0.t295; CHECK-NEXT: vadd.vv v8, v9, v8296; CHECK-NEXT: ret297 %sub = sub <4 x i32> %b, %a298 %add = add <4 x i32> %a, %b299 %res = shufflevector <4 x i32> %add, <4 x i32> %sub, <4 x i32> <i32 0, i32 5, i32 2, i32 7>300 ret <4 x i32> %res301}302