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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+v,+zfbfmin,+zvfbfmin -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s4; RUN: llc -mtriple=riscv64 -mattr=+d,+v,+zfbfmin,+zvfbfmin -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck %s6 7define <2 x bfloat> @select_v2bf16(i1 zeroext %c, <2 x bfloat> %a, <2 x bfloat> %b) {8; CHECK-LABEL: select_v2bf16:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma11; CHECK-NEXT: vmv.v.x v10, a012; CHECK-NEXT: vmsne.vi v0, v10, 013; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma14; CHECK-NEXT: vmerge.vvm v8, v9, v8, v015; CHECK-NEXT: ret16 %v = select i1 %c, <2 x bfloat> %a, <2 x bfloat> %b17 ret <2 x bfloat> %v18}19 20define <2 x bfloat> @selectcc_v2bf16(bfloat %a, bfloat %b, <2 x bfloat> %c, <2 x bfloat> %d) {21; CHECK-LABEL: selectcc_v2bf16:22; CHECK: # %bb.0:23; CHECK-NEXT: fcvt.s.bf16 fa5, fa124; CHECK-NEXT: fcvt.s.bf16 fa4, fa025; CHECK-NEXT: feq.s a0, fa4, fa526; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma27; CHECK-NEXT: vmv.v.x v10, a028; CHECK-NEXT: vmsne.vi v0, v10, 029; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma30; CHECK-NEXT: vmerge.vvm v8, v9, v8, v031; CHECK-NEXT: ret32 %cmp = fcmp oeq bfloat %a, %b33 %v = select i1 %cmp, <2 x bfloat> %c, <2 x bfloat> %d34 ret <2 x bfloat> %v35}36 37define <4 x bfloat> @select_v4bf16(i1 zeroext %c, <4 x bfloat> %a, <4 x bfloat> %b) {38; CHECK-LABEL: select_v4bf16:39; CHECK: # %bb.0:40; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma41; CHECK-NEXT: vmv.v.x v10, a042; CHECK-NEXT: vmsne.vi v0, v10, 043; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma44; CHECK-NEXT: vmerge.vvm v8, v9, v8, v045; CHECK-NEXT: ret46 %v = select i1 %c, <4 x bfloat> %a, <4 x bfloat> %b47 ret <4 x bfloat> %v48}49 50define <4 x bfloat> @selectcc_v4bf16(bfloat %a, bfloat %b, <4 x bfloat> %c, <4 x bfloat> %d) {51; CHECK-LABEL: selectcc_v4bf16:52; CHECK: # %bb.0:53; CHECK-NEXT: fcvt.s.bf16 fa5, fa154; CHECK-NEXT: fcvt.s.bf16 fa4, fa055; CHECK-NEXT: feq.s a0, fa4, fa556; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma57; CHECK-NEXT: vmv.v.x v10, a058; CHECK-NEXT: vmsne.vi v0, v10, 059; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma60; CHECK-NEXT: vmerge.vvm v8, v9, v8, v061; CHECK-NEXT: ret62 %cmp = fcmp oeq bfloat %a, %b63 %v = select i1 %cmp, <4 x bfloat> %c, <4 x bfloat> %d64 ret <4 x bfloat> %v65}66 67define <8 x bfloat> @select_v8bf16(i1 zeroext %c, <8 x bfloat> %a, <8 x bfloat> %b) {68; CHECK-LABEL: select_v8bf16:69; CHECK: # %bb.0:70; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma71; CHECK-NEXT: vmv.v.x v10, a072; CHECK-NEXT: vmsne.vi v0, v10, 073; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma74; CHECK-NEXT: vmerge.vvm v8, v9, v8, v075; CHECK-NEXT: ret76 %v = select i1 %c, <8 x bfloat> %a, <8 x bfloat> %b77 ret <8 x bfloat> %v78}79 80define <8 x bfloat> @selectcc_v8bf16(bfloat %a, bfloat %b, <8 x bfloat> %c, <8 x bfloat> %d) {81; CHECK-LABEL: selectcc_v8bf16:82; CHECK: # %bb.0:83; CHECK-NEXT: fcvt.s.bf16 fa5, fa184; CHECK-NEXT: fcvt.s.bf16 fa4, fa085; CHECK-NEXT: feq.s a0, fa4, fa586; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma87; CHECK-NEXT: vmv.v.x v10, a088; CHECK-NEXT: vmsne.vi v0, v10, 089; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma90; CHECK-NEXT: vmerge.vvm v8, v9, v8, v091; CHECK-NEXT: ret92 %cmp = fcmp oeq bfloat %a, %b93 %v = select i1 %cmp, <8 x bfloat> %c, <8 x bfloat> %d94 ret <8 x bfloat> %v95}96 97define <16 x bfloat> @select_v16bf16(i1 zeroext %c, <16 x bfloat> %a, <16 x bfloat> %b) {98; CHECK-LABEL: select_v16bf16:99; CHECK: # %bb.0:100; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma101; CHECK-NEXT: vmv.v.x v12, a0102; CHECK-NEXT: vmsne.vi v0, v12, 0103; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma104; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0105; CHECK-NEXT: ret106 %v = select i1 %c, <16 x bfloat> %a, <16 x bfloat> %b107 ret <16 x bfloat> %v108}109 110define <16 x bfloat> @selectcc_v16bf16(bfloat %a, bfloat %b, <16 x bfloat> %c, <16 x bfloat> %d) {111; CHECK-LABEL: selectcc_v16bf16:112; CHECK: # %bb.0:113; CHECK-NEXT: fcvt.s.bf16 fa5, fa1114; CHECK-NEXT: fcvt.s.bf16 fa4, fa0115; CHECK-NEXT: feq.s a0, fa4, fa5116; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma117; CHECK-NEXT: vmv.v.x v12, a0118; CHECK-NEXT: vmsne.vi v0, v12, 0119; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma120; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0121; CHECK-NEXT: ret122 %cmp = fcmp oeq bfloat %a, %b123 %v = select i1 %cmp, <16 x bfloat> %c, <16 x bfloat> %d124 ret <16 x bfloat> %v125}126