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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \3; RUN: | FileCheck %s --check-prefixes=CHECK,RV324; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \5; RUN: | FileCheck %s --check-prefixes=CHECK,RV646 7define <1 x i1> @select_v1i1(i1 zeroext %c, <1 x i1> %a, <1 x i1> %b) {8; CHECK-LABEL: select_v1i1:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma11; CHECK-NEXT: vmv.s.x v9, a012; CHECK-NEXT: vmsne.vi v9, v9, 013; CHECK-NEXT: vmandn.mm v8, v8, v914; CHECK-NEXT: vmand.mm v9, v0, v915; CHECK-NEXT: vmor.mm v0, v9, v816; CHECK-NEXT: ret17 %v = select i1 %c, <1 x i1> %a, <1 x i1> %b18 ret <1 x i1> %v19}20 21define <1 x i1> @selectcc_v1i1(i1 signext %a, i1 signext %b, <1 x i1> %c, <1 x i1> %d) {22; CHECK-LABEL: selectcc_v1i1:23; CHECK: # %bb.0:24; CHECK-NEXT: xor a0, a0, a125; CHECK-NEXT: andi a0, a0, 126; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma27; CHECK-NEXT: vmv.s.x v9, a028; CHECK-NEXT: vmsne.vi v9, v9, 029; CHECK-NEXT: vmandn.mm v8, v8, v930; CHECK-NEXT: vmand.mm v9, v0, v931; CHECK-NEXT: vmor.mm v0, v9, v832; CHECK-NEXT: ret33 %cmp = icmp ne i1 %a, %b34 %v = select i1 %cmp, <1 x i1> %c, <1 x i1> %d35 ret <1 x i1> %v36}37 38define <2 x i1> @select_v2i1(i1 zeroext %c, <2 x i1> %a, <2 x i1> %b) {39; CHECK-LABEL: select_v2i1:40; CHECK: # %bb.0:41; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma42; CHECK-NEXT: vmv.v.x v9, a043; CHECK-NEXT: vmsne.vi v9, v9, 044; CHECK-NEXT: vmandn.mm v8, v8, v945; CHECK-NEXT: vmand.mm v9, v0, v946; CHECK-NEXT: vmor.mm v0, v9, v847; CHECK-NEXT: ret48 %v = select i1 %c, <2 x i1> %a, <2 x i1> %b49 ret <2 x i1> %v50}51 52define <2 x i1> @selectcc_v2i1(i1 signext %a, i1 signext %b, <2 x i1> %c, <2 x i1> %d) {53; CHECK-LABEL: selectcc_v2i1:54; CHECK: # %bb.0:55; CHECK-NEXT: xor a0, a0, a156; CHECK-NEXT: andi a0, a0, 157; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma58; CHECK-NEXT: vmv.v.x v9, a059; CHECK-NEXT: vmsne.vi v9, v9, 060; CHECK-NEXT: vmandn.mm v8, v8, v961; CHECK-NEXT: vmand.mm v9, v0, v962; CHECK-NEXT: vmor.mm v0, v9, v863; CHECK-NEXT: ret64 %cmp = icmp ne i1 %a, %b65 %v = select i1 %cmp, <2 x i1> %c, <2 x i1> %d66 ret <2 x i1> %v67}68 69define <4 x i1> @select_v4i1(i1 zeroext %c, <4 x i1> %a, <4 x i1> %b) {70; CHECK-LABEL: select_v4i1:71; CHECK: # %bb.0:72; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma73; CHECK-NEXT: vmv.v.x v9, a074; CHECK-NEXT: vmsne.vi v9, v9, 075; CHECK-NEXT: vmandn.mm v8, v8, v976; CHECK-NEXT: vmand.mm v9, v0, v977; CHECK-NEXT: vmor.mm v0, v9, v878; CHECK-NEXT: ret79 %v = select i1 %c, <4 x i1> %a, <4 x i1> %b80 ret <4 x i1> %v81}82 83define <4 x i1> @selectcc_v4i1(i1 signext %a, i1 signext %b, <4 x i1> %c, <4 x i1> %d) {84; CHECK-LABEL: selectcc_v4i1:85; CHECK: # %bb.0:86; CHECK-NEXT: xor a0, a0, a187; CHECK-NEXT: andi a0, a0, 188; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma89; CHECK-NEXT: vmv.v.x v9, a090; CHECK-NEXT: vmsne.vi v9, v9, 091; CHECK-NEXT: vmandn.mm v8, v8, v992; CHECK-NEXT: vmand.mm v9, v0, v993; CHECK-NEXT: vmor.mm v0, v9, v894; CHECK-NEXT: ret95 %cmp = icmp ne i1 %a, %b96 %v = select i1 %cmp, <4 x i1> %c, <4 x i1> %d97 ret <4 x i1> %v98}99 100define <8 x i1> @select_v8i1(i1 zeroext %c, <8 x i1> %a, <8 x i1> %b) {101; CHECK-LABEL: select_v8i1:102; CHECK: # %bb.0:103; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma104; CHECK-NEXT: vmv.v.x v9, a0105; CHECK-NEXT: vmsne.vi v9, v9, 0106; CHECK-NEXT: vmandn.mm v8, v8, v9107; CHECK-NEXT: vmand.mm v9, v0, v9108; CHECK-NEXT: vmor.mm v0, v9, v8109; CHECK-NEXT: ret110 %v = select i1 %c, <8 x i1> %a, <8 x i1> %b111 ret <8 x i1> %v112}113 114define <8 x i1> @selectcc_v8i1(i1 signext %a, i1 signext %b, <8 x i1> %c, <8 x i1> %d) {115; CHECK-LABEL: selectcc_v8i1:116; CHECK: # %bb.0:117; CHECK-NEXT: xor a0, a0, a1118; CHECK-NEXT: andi a0, a0, 1119; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma120; CHECK-NEXT: vmv.v.x v9, a0121; CHECK-NEXT: vmsne.vi v9, v9, 0122; CHECK-NEXT: vmandn.mm v8, v8, v9123; CHECK-NEXT: vmand.mm v9, v0, v9124; CHECK-NEXT: vmor.mm v0, v9, v8125; CHECK-NEXT: ret126 %cmp = icmp ne i1 %a, %b127 %v = select i1 %cmp, <8 x i1> %c, <8 x i1> %d128 ret <8 x i1> %v129}130 131define <16 x i1> @select_v16i1(i1 zeroext %c, <16 x i1> %a, <16 x i1> %b) {132; CHECK-LABEL: select_v16i1:133; CHECK: # %bb.0:134; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma135; CHECK-NEXT: vmv.v.x v9, a0136; CHECK-NEXT: vmsne.vi v9, v9, 0137; CHECK-NEXT: vmandn.mm v8, v8, v9138; CHECK-NEXT: vmand.mm v9, v0, v9139; CHECK-NEXT: vmor.mm v0, v9, v8140; CHECK-NEXT: ret141 %v = select i1 %c, <16 x i1> %a, <16 x i1> %b142 ret <16 x i1> %v143}144 145define <16 x i1> @selectcc_v16i1(i1 signext %a, i1 signext %b, <16 x i1> %c, <16 x i1> %d) {146; CHECK-LABEL: selectcc_v16i1:147; CHECK: # %bb.0:148; CHECK-NEXT: xor a0, a0, a1149; CHECK-NEXT: andi a0, a0, 1150; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma151; CHECK-NEXT: vmv.v.x v9, a0152; CHECK-NEXT: vmsne.vi v9, v9, 0153; CHECK-NEXT: vmandn.mm v8, v8, v9154; CHECK-NEXT: vmand.mm v9, v0, v9155; CHECK-NEXT: vmor.mm v0, v9, v8156; CHECK-NEXT: ret157 %cmp = icmp ne i1 %a, %b158 %v = select i1 %cmp, <16 x i1> %c, <16 x i1> %d159 ret <16 x i1> %v160}161 162define <2 x i8> @select_v2i8(i1 zeroext %c, <2 x i8> %a, <2 x i8> %b) {163; CHECK-LABEL: select_v2i8:164; CHECK: # %bb.0:165; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma166; CHECK-NEXT: vmv.v.x v10, a0167; CHECK-NEXT: vmsne.vi v0, v10, 0168; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0169; CHECK-NEXT: ret170 %v = select i1 %c, <2 x i8> %a, <2 x i8> %b171 ret <2 x i8> %v172}173 174define <2 x i8> @selectcc_v2i8(i8 signext %a, i8 signext %b, <2 x i8> %c, <2 x i8> %d) {175; CHECK-LABEL: selectcc_v2i8:176; CHECK: # %bb.0:177; CHECK-NEXT: xor a0, a0, a1178; CHECK-NEXT: snez a0, a0179; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma180; CHECK-NEXT: vmv.v.x v10, a0181; CHECK-NEXT: vmsne.vi v0, v10, 0182; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0183; CHECK-NEXT: ret184 %cmp = icmp ne i8 %a, %b185 %v = select i1 %cmp, <2 x i8> %c, <2 x i8> %d186 ret <2 x i8> %v187}188 189define <4 x i8> @select_v4i8(i1 zeroext %c, <4 x i8> %a, <4 x i8> %b) {190; CHECK-LABEL: select_v4i8:191; CHECK: # %bb.0:192; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma193; CHECK-NEXT: vmv.v.x v10, a0194; CHECK-NEXT: vmsne.vi v0, v10, 0195; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0196; CHECK-NEXT: ret197 %v = select i1 %c, <4 x i8> %a, <4 x i8> %b198 ret <4 x i8> %v199}200 201define <4 x i8> @selectcc_v4i8(i8 signext %a, i8 signext %b, <4 x i8> %c, <4 x i8> %d) {202; CHECK-LABEL: selectcc_v4i8:203; CHECK: # %bb.0:204; CHECK-NEXT: xor a0, a0, a1205; CHECK-NEXT: snez a0, a0206; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma207; CHECK-NEXT: vmv.v.x v10, a0208; CHECK-NEXT: vmsne.vi v0, v10, 0209; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0210; CHECK-NEXT: ret211 %cmp = icmp ne i8 %a, %b212 %v = select i1 %cmp, <4 x i8> %c, <4 x i8> %d213 ret <4 x i8> %v214}215 216define <8 x i8> @select_v8i8(i1 zeroext %c, <8 x i8> %a, <8 x i8> %b) {217; CHECK-LABEL: select_v8i8:218; CHECK: # %bb.0:219; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma220; CHECK-NEXT: vmv.v.x v10, a0221; CHECK-NEXT: vmsne.vi v0, v10, 0222; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0223; CHECK-NEXT: ret224 %v = select i1 %c, <8 x i8> %a, <8 x i8> %b225 ret <8 x i8> %v226}227 228define <8 x i8> @selectcc_v8i8(i8 signext %a, i8 signext %b, <8 x i8> %c, <8 x i8> %d) {229; CHECK-LABEL: selectcc_v8i8:230; CHECK: # %bb.0:231; CHECK-NEXT: xor a0, a0, a1232; CHECK-NEXT: snez a0, a0233; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma234; CHECK-NEXT: vmv.v.x v10, a0235; CHECK-NEXT: vmsne.vi v0, v10, 0236; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0237; CHECK-NEXT: ret238 %cmp = icmp ne i8 %a, %b239 %v = select i1 %cmp, <8 x i8> %c, <8 x i8> %d240 ret <8 x i8> %v241}242 243define <16 x i8> @select_v16i8(i1 zeroext %c, <16 x i8> %a, <16 x i8> %b) {244; CHECK-LABEL: select_v16i8:245; CHECK: # %bb.0:246; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma247; CHECK-NEXT: vmv.v.x v10, a0248; CHECK-NEXT: vmsne.vi v0, v10, 0249; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0250; CHECK-NEXT: ret251 %v = select i1 %c, <16 x i8> %a, <16 x i8> %b252 ret <16 x i8> %v253}254 255define <16 x i8> @selectcc_v16i8(i8 signext %a, i8 signext %b, <16 x i8> %c, <16 x i8> %d) {256; CHECK-LABEL: selectcc_v16i8:257; CHECK: # %bb.0:258; CHECK-NEXT: xor a0, a0, a1259; CHECK-NEXT: snez a0, a0260; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma261; CHECK-NEXT: vmv.v.x v10, a0262; CHECK-NEXT: vmsne.vi v0, v10, 0263; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0264; CHECK-NEXT: ret265 %cmp = icmp ne i8 %a, %b266 %v = select i1 %cmp, <16 x i8> %c, <16 x i8> %d267 ret <16 x i8> %v268}269 270define <2 x i16> @select_v2i16(i1 zeroext %c, <2 x i16> %a, <2 x i16> %b) {271; CHECK-LABEL: select_v2i16:272; CHECK: # %bb.0:273; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma274; CHECK-NEXT: vmv.v.x v10, a0275; CHECK-NEXT: vmsne.vi v0, v10, 0276; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma277; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0278; CHECK-NEXT: ret279 %v = select i1 %c, <2 x i16> %a, <2 x i16> %b280 ret <2 x i16> %v281}282 283define <2 x i16> @selectcc_v2i16(i16 signext %a, i16 signext %b, <2 x i16> %c, <2 x i16> %d) {284; CHECK-LABEL: selectcc_v2i16:285; CHECK: # %bb.0:286; CHECK-NEXT: xor a0, a0, a1287; CHECK-NEXT: snez a0, a0288; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma289; CHECK-NEXT: vmv.v.x v10, a0290; CHECK-NEXT: vmsne.vi v0, v10, 0291; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma292; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0293; CHECK-NEXT: ret294 %cmp = icmp ne i16 %a, %b295 %v = select i1 %cmp, <2 x i16> %c, <2 x i16> %d296 ret <2 x i16> %v297}298 299define <4 x i16> @select_v4i16(i1 zeroext %c, <4 x i16> %a, <4 x i16> %b) {300; CHECK-LABEL: select_v4i16:301; CHECK: # %bb.0:302; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma303; CHECK-NEXT: vmv.v.x v10, a0304; CHECK-NEXT: vmsne.vi v0, v10, 0305; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma306; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0307; CHECK-NEXT: ret308 %v = select i1 %c, <4 x i16> %a, <4 x i16> %b309 ret <4 x i16> %v310}311 312define <4 x i16> @selectcc_v4i16(i16 signext %a, i16 signext %b, <4 x i16> %c, <4 x i16> %d) {313; CHECK-LABEL: selectcc_v4i16:314; CHECK: # %bb.0:315; CHECK-NEXT: xor a0, a0, a1316; CHECK-NEXT: snez a0, a0317; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma318; CHECK-NEXT: vmv.v.x v10, a0319; CHECK-NEXT: vmsne.vi v0, v10, 0320; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma321; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0322; CHECK-NEXT: ret323 %cmp = icmp ne i16 %a, %b324 %v = select i1 %cmp, <4 x i16> %c, <4 x i16> %d325 ret <4 x i16> %v326}327 328define <8 x i16> @select_v8i16(i1 zeroext %c, <8 x i16> %a, <8 x i16> %b) {329; CHECK-LABEL: select_v8i16:330; CHECK: # %bb.0:331; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma332; CHECK-NEXT: vmv.v.x v10, a0333; CHECK-NEXT: vmsne.vi v0, v10, 0334; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma335; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0336; CHECK-NEXT: ret337 %v = select i1 %c, <8 x i16> %a, <8 x i16> %b338 ret <8 x i16> %v339}340 341define <8 x i16> @selectcc_v8i16(i16 signext %a, i16 signext %b, <8 x i16> %c, <8 x i16> %d) {342; CHECK-LABEL: selectcc_v8i16:343; CHECK: # %bb.0:344; CHECK-NEXT: xor a0, a0, a1345; CHECK-NEXT: snez a0, a0346; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma347; CHECK-NEXT: vmv.v.x v10, a0348; CHECK-NEXT: vmsne.vi v0, v10, 0349; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma350; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0351; CHECK-NEXT: ret352 %cmp = icmp ne i16 %a, %b353 %v = select i1 %cmp, <8 x i16> %c, <8 x i16> %d354 ret <8 x i16> %v355}356 357define <16 x i16> @select_v16i16(i1 zeroext %c, <16 x i16> %a, <16 x i16> %b) {358; CHECK-LABEL: select_v16i16:359; CHECK: # %bb.0:360; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma361; CHECK-NEXT: vmv.v.x v12, a0362; CHECK-NEXT: vmsne.vi v0, v12, 0363; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma364; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0365; CHECK-NEXT: ret366 %v = select i1 %c, <16 x i16> %a, <16 x i16> %b367 ret <16 x i16> %v368}369 370define <16 x i16> @selectcc_v16i16(i16 signext %a, i16 signext %b, <16 x i16> %c, <16 x i16> %d) {371; CHECK-LABEL: selectcc_v16i16:372; CHECK: # %bb.0:373; CHECK-NEXT: xor a0, a0, a1374; CHECK-NEXT: snez a0, a0375; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma376; CHECK-NEXT: vmv.v.x v12, a0377; CHECK-NEXT: vmsne.vi v0, v12, 0378; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma379; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0380; CHECK-NEXT: ret381 %cmp = icmp ne i16 %a, %b382 %v = select i1 %cmp, <16 x i16> %c, <16 x i16> %d383 ret <16 x i16> %v384}385 386define <2 x i32> @select_v2i32(i1 zeroext %c, <2 x i32> %a, <2 x i32> %b) {387; CHECK-LABEL: select_v2i32:388; CHECK: # %bb.0:389; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma390; CHECK-NEXT: vmv.v.x v10, a0391; CHECK-NEXT: vmsne.vi v0, v10, 0392; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma393; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0394; CHECK-NEXT: ret395 %v = select i1 %c, <2 x i32> %a, <2 x i32> %b396 ret <2 x i32> %v397}398 399define <2 x i32> @selectcc_v2i32(i32 signext %a, i32 signext %b, <2 x i32> %c, <2 x i32> %d) {400; CHECK-LABEL: selectcc_v2i32:401; CHECK: # %bb.0:402; CHECK-NEXT: xor a0, a0, a1403; CHECK-NEXT: snez a0, a0404; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma405; CHECK-NEXT: vmv.v.x v10, a0406; CHECK-NEXT: vmsne.vi v0, v10, 0407; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma408; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0409; CHECK-NEXT: ret410 %cmp = icmp ne i32 %a, %b411 %v = select i1 %cmp, <2 x i32> %c, <2 x i32> %d412 ret <2 x i32> %v413}414 415define <4 x i32> @select_v4i32(i1 zeroext %c, <4 x i32> %a, <4 x i32> %b) {416; CHECK-LABEL: select_v4i32:417; CHECK: # %bb.0:418; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma419; CHECK-NEXT: vmv.v.x v10, a0420; CHECK-NEXT: vmsne.vi v0, v10, 0421; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma422; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0423; CHECK-NEXT: ret424 %v = select i1 %c, <4 x i32> %a, <4 x i32> %b425 ret <4 x i32> %v426}427 428define <4 x i32> @selectcc_v4i32(i32 signext %a, i32 signext %b, <4 x i32> %c, <4 x i32> %d) {429; CHECK-LABEL: selectcc_v4i32:430; CHECK: # %bb.0:431; CHECK-NEXT: xor a0, a0, a1432; CHECK-NEXT: snez a0, a0433; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma434; CHECK-NEXT: vmv.v.x v10, a0435; CHECK-NEXT: vmsne.vi v0, v10, 0436; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma437; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0438; CHECK-NEXT: ret439 %cmp = icmp ne i32 %a, %b440 %v = select i1 %cmp, <4 x i32> %c, <4 x i32> %d441 ret <4 x i32> %v442}443 444define <8 x i32> @select_v8i32(i1 zeroext %c, <8 x i32> %a, <8 x i32> %b) {445; CHECK-LABEL: select_v8i32:446; CHECK: # %bb.0:447; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma448; CHECK-NEXT: vmv.v.x v12, a0449; CHECK-NEXT: vmsne.vi v0, v12, 0450; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma451; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0452; CHECK-NEXT: ret453 %v = select i1 %c, <8 x i32> %a, <8 x i32> %b454 ret <8 x i32> %v455}456 457define <8 x i32> @selectcc_v8i32(i32 signext %a, i32 signext %b, <8 x i32> %c, <8 x i32> %d) {458; CHECK-LABEL: selectcc_v8i32:459; CHECK: # %bb.0:460; CHECK-NEXT: xor a0, a0, a1461; CHECK-NEXT: snez a0, a0462; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma463; CHECK-NEXT: vmv.v.x v12, a0464; CHECK-NEXT: vmsne.vi v0, v12, 0465; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma466; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0467; CHECK-NEXT: ret468 %cmp = icmp ne i32 %a, %b469 %v = select i1 %cmp, <8 x i32> %c, <8 x i32> %d470 ret <8 x i32> %v471}472 473define <16 x i32> @select_v16i32(i1 zeroext %c, <16 x i32> %a, <16 x i32> %b) {474; CHECK-LABEL: select_v16i32:475; CHECK: # %bb.0:476; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma477; CHECK-NEXT: vmv.v.x v16, a0478; CHECK-NEXT: vmsne.vi v0, v16, 0479; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma480; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0481; CHECK-NEXT: ret482 %v = select i1 %c, <16 x i32> %a, <16 x i32> %b483 ret <16 x i32> %v484}485 486define <16 x i32> @selectcc_v16i32(i32 signext %a, i32 signext %b, <16 x i32> %c, <16 x i32> %d) {487; CHECK-LABEL: selectcc_v16i32:488; CHECK: # %bb.0:489; CHECK-NEXT: xor a0, a0, a1490; CHECK-NEXT: snez a0, a0491; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma492; CHECK-NEXT: vmv.v.x v16, a0493; CHECK-NEXT: vmsne.vi v0, v16, 0494; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma495; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0496; CHECK-NEXT: ret497 %cmp = icmp ne i32 %a, %b498 %v = select i1 %cmp, <16 x i32> %c, <16 x i32> %d499 ret <16 x i32> %v500}501 502define <2 x i64> @select_v2i64(i1 zeroext %c, <2 x i64> %a, <2 x i64> %b) {503; CHECK-LABEL: select_v2i64:504; CHECK: # %bb.0:505; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma506; CHECK-NEXT: vmv.v.x v10, a0507; CHECK-NEXT: vmsne.vi v0, v10, 0508; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma509; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0510; CHECK-NEXT: ret511 %v = select i1 %c, <2 x i64> %a, <2 x i64> %b512 ret <2 x i64> %v513}514 515define <2 x i64> @selectcc_v2i64(i64 signext %a, i64 signext %b, <2 x i64> %c, <2 x i64> %d) {516; RV32-LABEL: selectcc_v2i64:517; RV32: # %bb.0:518; RV32-NEXT: xor a1, a1, a3519; RV32-NEXT: xor a0, a0, a2520; RV32-NEXT: or a0, a0, a1521; RV32-NEXT: snez a0, a0522; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, ma523; RV32-NEXT: vmv.v.x v10, a0524; RV32-NEXT: vmsne.vi v0, v10, 0525; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma526; RV32-NEXT: vmerge.vvm v8, v9, v8, v0527; RV32-NEXT: ret528;529; RV64-LABEL: selectcc_v2i64:530; RV64: # %bb.0:531; RV64-NEXT: xor a0, a0, a1532; RV64-NEXT: snez a0, a0533; RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, ma534; RV64-NEXT: vmv.v.x v10, a0535; RV64-NEXT: vmsne.vi v0, v10, 0536; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma537; RV64-NEXT: vmerge.vvm v8, v9, v8, v0538; RV64-NEXT: ret539 %cmp = icmp ne i64 %a, %b540 %v = select i1 %cmp, <2 x i64> %c, <2 x i64> %d541 ret <2 x i64> %v542}543 544define <4 x i64> @select_v4i64(i1 zeroext %c, <4 x i64> %a, <4 x i64> %b) {545; CHECK-LABEL: select_v4i64:546; CHECK: # %bb.0:547; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma548; CHECK-NEXT: vmv.v.x v12, a0549; CHECK-NEXT: vmsne.vi v0, v12, 0550; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma551; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0552; CHECK-NEXT: ret553 %v = select i1 %c, <4 x i64> %a, <4 x i64> %b554 ret <4 x i64> %v555}556 557define <4 x i64> @selectcc_v4i64(i64 signext %a, i64 signext %b, <4 x i64> %c, <4 x i64> %d) {558; RV32-LABEL: selectcc_v4i64:559; RV32: # %bb.0:560; RV32-NEXT: xor a1, a1, a3561; RV32-NEXT: xor a0, a0, a2562; RV32-NEXT: or a0, a0, a1563; RV32-NEXT: snez a0, a0564; RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, ma565; RV32-NEXT: vmv.v.x v12, a0566; RV32-NEXT: vmsne.vi v0, v12, 0567; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, ma568; RV32-NEXT: vmerge.vvm v8, v10, v8, v0569; RV32-NEXT: ret570;571; RV64-LABEL: selectcc_v4i64:572; RV64: # %bb.0:573; RV64-NEXT: xor a0, a0, a1574; RV64-NEXT: snez a0, a0575; RV64-NEXT: vsetivli zero, 4, e8, mf4, ta, ma576; RV64-NEXT: vmv.v.x v12, a0577; RV64-NEXT: vmsne.vi v0, v12, 0578; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, ma579; RV64-NEXT: vmerge.vvm v8, v10, v8, v0580; RV64-NEXT: ret581 %cmp = icmp ne i64 %a, %b582 %v = select i1 %cmp, <4 x i64> %c, <4 x i64> %d583 ret <4 x i64> %v584}585 586define <8 x i64> @select_v8i64(i1 zeroext %c, <8 x i64> %a, <8 x i64> %b) {587; CHECK-LABEL: select_v8i64:588; CHECK: # %bb.0:589; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma590; CHECK-NEXT: vmv.v.x v16, a0591; CHECK-NEXT: vmsne.vi v0, v16, 0592; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma593; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0594; CHECK-NEXT: ret595 %v = select i1 %c, <8 x i64> %a, <8 x i64> %b596 ret <8 x i64> %v597}598 599define <8 x i64> @selectcc_v8i64(i64 signext %a, i64 signext %b, <8 x i64> %c, <8 x i64> %d) {600; RV32-LABEL: selectcc_v8i64:601; RV32: # %bb.0:602; RV32-NEXT: xor a1, a1, a3603; RV32-NEXT: xor a0, a0, a2604; RV32-NEXT: or a0, a0, a1605; RV32-NEXT: snez a0, a0606; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma607; RV32-NEXT: vmv.v.x v16, a0608; RV32-NEXT: vmsne.vi v0, v16, 0609; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, ma610; RV32-NEXT: vmerge.vvm v8, v12, v8, v0611; RV32-NEXT: ret612;613; RV64-LABEL: selectcc_v8i64:614; RV64: # %bb.0:615; RV64-NEXT: xor a0, a0, a1616; RV64-NEXT: snez a0, a0617; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, ma618; RV64-NEXT: vmv.v.x v16, a0619; RV64-NEXT: vmsne.vi v0, v16, 0620; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, ma621; RV64-NEXT: vmerge.vvm v8, v12, v8, v0622; RV64-NEXT: ret623 %cmp = icmp ne i64 %a, %b624 %v = select i1 %cmp, <8 x i64> %c, <8 x i64> %d625 ret <8 x i64> %v626}627 628define <16 x i64> @select_v16i64(i1 zeroext %c, <16 x i64> %a, <16 x i64> %b) {629; CHECK-LABEL: select_v16i64:630; CHECK: # %bb.0:631; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma632; CHECK-NEXT: vmv.v.x v24, a0633; CHECK-NEXT: vmsne.vi v0, v24, 0634; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma635; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0636; CHECK-NEXT: ret637 %v = select i1 %c, <16 x i64> %a, <16 x i64> %b638 ret <16 x i64> %v639}640 641define <16 x i64> @selectcc_v16i64(i64 signext %a, i64 signext %b, <16 x i64> %c, <16 x i64> %d) {642; RV32-LABEL: selectcc_v16i64:643; RV32: # %bb.0:644; RV32-NEXT: xor a1, a1, a3645; RV32-NEXT: xor a0, a0, a2646; RV32-NEXT: or a0, a0, a1647; RV32-NEXT: snez a0, a0648; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma649; RV32-NEXT: vmv.v.x v24, a0650; RV32-NEXT: vmsne.vi v0, v24, 0651; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma652; RV32-NEXT: vmerge.vvm v8, v16, v8, v0653; RV32-NEXT: ret654;655; RV64-LABEL: selectcc_v16i64:656; RV64: # %bb.0:657; RV64-NEXT: xor a0, a0, a1658; RV64-NEXT: snez a0, a0659; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma660; RV64-NEXT: vmv.v.x v24, a0661; RV64-NEXT: vmsne.vi v0, v24, 0662; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma663; RV64-NEXT: vmerge.vvm v8, v16, v8, v0664; RV64-NEXT: ret665 %cmp = icmp ne i64 %a, %b666 %v = select i1 %cmp, <16 x i64> %c, <16 x i64> %d667 ret <16 x i64> %v668}669