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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc < %s -mtriple=riscv32 -mattr=+v -verify-machineinstrs | FileCheck -check-prefixes=CHECK,RV32 %s3; RUN: llc < %s -mtriple=riscv64 -mattr=+v -verify-machineinstrs | FileCheck -check-prefixes=CHECK,RV64 %s4 5 6define <8 x i1> @v8i1_v16i1(<16 x i1>) {7; RV32-LABEL: v8i1_v16i1:8; RV32: # %bb.0:9; RV32-NEXT: vsetivli zero, 1, e16, m1, ta, ma10; RV32-NEXT: vmv.x.s a0, v011; RV32-NEXT: slli a1, a0, 1812; RV32-NEXT: srli a2, a0, 3113; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu14; RV32-NEXT: vmv.v.x v8, a215; RV32-NEXT: slli a2, a0, 2716; RV32-NEXT: srli a1, a1, 3117; RV32-NEXT: vslide1down.vx v8, v8, a118; RV32-NEXT: slli a1, a0, 2619; RV32-NEXT: srli a1, a1, 3120; RV32-NEXT: vmv.v.x v9, a121; RV32-NEXT: slli a1, a0, 2822; RV32-NEXT: srli a2, a2, 3123; RV32-NEXT: vslide1down.vx v8, v8, a224; RV32-NEXT: slli a2, a0, 1925; RV32-NEXT: srli a2, a2, 3126; RV32-NEXT: vslide1down.vx v9, v9, a227; RV32-NEXT: slli a2, a0, 2428; RV32-NEXT: slli a0, a0, 2929; RV32-NEXT: srli a1, a1, 3130; RV32-NEXT: srli a2, a2, 3131; RV32-NEXT: srli a0, a0, 3132; RV32-NEXT: vslide1down.vx v8, v8, a133; RV32-NEXT: vslide1down.vx v9, v9, a234; RV32-NEXT: vmv.v.i v0, 1535; RV32-NEXT: vslide1down.vx v9, v9, a036; RV32-NEXT: vslidedown.vi v8, v9, 4, v0.t37; RV32-NEXT: vand.vi v8, v8, 138; RV32-NEXT: vmsne.vi v0, v8, 039; RV32-NEXT: ret40;41; RV64-LABEL: v8i1_v16i1:42; RV64: # %bb.0:43; RV64-NEXT: vsetivli zero, 1, e16, m1, ta, ma44; RV64-NEXT: vmv.x.s a0, v045; RV64-NEXT: slli a1, a0, 5046; RV64-NEXT: srli a2, a0, 6347; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu48; RV64-NEXT: vmv.v.x v8, a249; RV64-NEXT: slli a2, a0, 5950; RV64-NEXT: srli a1, a1, 6351; RV64-NEXT: vslide1down.vx v8, v8, a152; RV64-NEXT: slli a1, a0, 5853; RV64-NEXT: srli a1, a1, 6354; RV64-NEXT: vmv.v.x v9, a155; RV64-NEXT: slli a1, a0, 6056; RV64-NEXT: srli a2, a2, 6357; RV64-NEXT: vslide1down.vx v8, v8, a258; RV64-NEXT: slli a2, a0, 5159; RV64-NEXT: srli a2, a2, 6360; RV64-NEXT: vslide1down.vx v9, v9, a261; RV64-NEXT: slli a2, a0, 5662; RV64-NEXT: slli a0, a0, 6163; RV64-NEXT: srli a1, a1, 6364; RV64-NEXT: srli a2, a2, 6365; RV64-NEXT: srli a0, a0, 6366; RV64-NEXT: vslide1down.vx v8, v8, a167; RV64-NEXT: vslide1down.vx v9, v9, a268; RV64-NEXT: vmv.v.i v0, 1569; RV64-NEXT: vslide1down.vx v9, v9, a070; RV64-NEXT: vslidedown.vi v8, v9, 4, v0.t71; RV64-NEXT: vand.vi v8, v8, 172; RV64-NEXT: vmsne.vi v0, v8, 073; RV64-NEXT: ret74 %2 = shufflevector <16 x i1> %0, <16 x i1> poison, <8 x i32> <i32 5, i32 12, i32 7, i32 2, i32 15, i32 13, i32 4, i32 3>75 ret <8 x i1> %276}77 78define <4 x i32> @v4i32_v8i32(<8 x i32>) {79; CHECK-LABEL: v4i32_v8i32:80; CHECK: # %bb.0:81; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu82; CHECK-NEXT: vmv.v.i v0, 883; CHECK-NEXT: vslidedown.vi v10, v8, 284; CHECK-NEXT: vslideup.vi v10, v8, 1, v0.t85; CHECK-NEXT: vmv.v.i v0, 586; CHECK-NEXT: vsetivli zero, 4, e32, m2, ta, ma87; CHECK-NEXT: vslidedown.vi v8, v8, 488; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu89; CHECK-NEXT: vslidedown.vi v10, v8, 1, v0.t90; CHECK-NEXT: vmv.v.v v8, v1091; CHECK-NEXT: ret92 %2 = shufflevector <8 x i32> %0, <8 x i32> poison, <4 x i32> <i32 5, i32 3, i32 7, i32 2>93 ret <4 x i32> %294}95 96define <4 x i32> @v4i32_v16i32(<16 x i32>) {97; CHECK-LABEL: v4i32_v16i32:98; CHECK: # %bb.0:99; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma100; CHECK-NEXT: vmv.v.i v0, 8101; CHECK-NEXT: vsetivli zero, 8, e32, m4, ta, ma102; CHECK-NEXT: vslidedown.vi v12, v8, 8103; CHECK-NEXT: li a0, 32104; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu105; CHECK-NEXT: vslidedown.vi v12, v12, 3, v0.t106; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma107; CHECK-NEXT: vmv.v.i v0, 10108; CHECK-NEXT: vnsrl.wx v10, v8, a0109; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma110; CHECK-NEXT: vmerge.vvm v8, v10, v12, v0111; CHECK-NEXT: ret112 %2 = shufflevector <16 x i32> %0, <16 x i32> poison, <4 x i32> <i32 1, i32 9, i32 5, i32 14>113 ret <4 x i32> %2114}115 116define <4 x i32> @v4i32_v32i32(<32 x i32>) {117; RV32-LABEL: v4i32_v32i32:118; RV32: # %bb.0:119; RV32-NEXT: addi sp, sp, -256120; RV32-NEXT: .cfi_def_cfa_offset 256121; RV32-NEXT: sw ra, 252(sp) # 4-byte Folded Spill122; RV32-NEXT: sw s0, 248(sp) # 4-byte Folded Spill123; RV32-NEXT: .cfi_offset ra, -4124; RV32-NEXT: .cfi_offset s0, -8125; RV32-NEXT: addi s0, sp, 256126; RV32-NEXT: .cfi_def_cfa s0, 0127; RV32-NEXT: andi sp, sp, -128128; RV32-NEXT: li a0, 32129; RV32-NEXT: mv a1, sp130; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma131; RV32-NEXT: vslidedown.vi v16, v8, 1132; RV32-NEXT: vsetvli zero, a0, e32, m8, ta, ma133; RV32-NEXT: vse32.v v8, (a1)134; RV32-NEXT: vsetivli zero, 1, e32, m2, ta, ma135; RV32-NEXT: vslidedown.vi v8, v8, 4136; RV32-NEXT: lw a0, 36(sp)137; RV32-NEXT: vmv.x.s a1, v16138; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma139; RV32-NEXT: vmv.v.x v9, a1140; RV32-NEXT: lw a1, 120(sp)141; RV32-NEXT: vslide1down.vx v9, v9, a0142; RV32-NEXT: vmv.x.s a0, v8143; RV32-NEXT: vslide1down.vx v8, v9, a0144; RV32-NEXT: vslide1down.vx v8, v8, a1145; RV32-NEXT: addi sp, s0, -256146; RV32-NEXT: .cfi_def_cfa sp, 256147; RV32-NEXT: lw ra, 252(sp) # 4-byte Folded Reload148; RV32-NEXT: lw s0, 248(sp) # 4-byte Folded Reload149; RV32-NEXT: .cfi_restore ra150; RV32-NEXT: .cfi_restore s0151; RV32-NEXT: addi sp, sp, 256152; RV32-NEXT: .cfi_def_cfa_offset 0153; RV32-NEXT: ret154;155; RV64-LABEL: v4i32_v32i32:156; RV64: # %bb.0:157; RV64-NEXT: addi sp, sp, -256158; RV64-NEXT: .cfi_def_cfa_offset 256159; RV64-NEXT: sd ra, 248(sp) # 8-byte Folded Spill160; RV64-NEXT: sd s0, 240(sp) # 8-byte Folded Spill161; RV64-NEXT: .cfi_offset ra, -8162; RV64-NEXT: .cfi_offset s0, -16163; RV64-NEXT: addi s0, sp, 256164; RV64-NEXT: .cfi_def_cfa s0, 0165; RV64-NEXT: andi sp, sp, -128166; RV64-NEXT: li a0, 32167; RV64-NEXT: mv a1, sp168; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma169; RV64-NEXT: vslidedown.vi v16, v8, 1170; RV64-NEXT: vsetvli zero, a0, e32, m8, ta, ma171; RV64-NEXT: vse32.v v8, (a1)172; RV64-NEXT: vsetivli zero, 1, e32, m2, ta, ma173; RV64-NEXT: vslidedown.vi v8, v8, 4174; RV64-NEXT: lw a0, 36(sp)175; RV64-NEXT: vmv.x.s a1, v16176; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma177; RV64-NEXT: vmv.v.x v9, a1178; RV64-NEXT: lw a1, 120(sp)179; RV64-NEXT: vslide1down.vx v9, v9, a0180; RV64-NEXT: vmv.x.s a0, v8181; RV64-NEXT: vslide1down.vx v8, v9, a0182; RV64-NEXT: vslide1down.vx v8, v8, a1183; RV64-NEXT: addi sp, s0, -256184; RV64-NEXT: .cfi_def_cfa sp, 256185; RV64-NEXT: ld ra, 248(sp) # 8-byte Folded Reload186; RV64-NEXT: ld s0, 240(sp) # 8-byte Folded Reload187; RV64-NEXT: .cfi_restore ra188; RV64-NEXT: .cfi_restore s0189; RV64-NEXT: addi sp, sp, 256190; RV64-NEXT: .cfi_def_cfa_offset 0191; RV64-NEXT: ret192 %2 = shufflevector <32 x i32> %0, <32 x i32> poison, <4 x i32> <i32 1, i32 9, i32 4, i32 30>193 ret <4 x i32> %2194}195 196define <16 x i1> @v16i1_v8i1(<8 x i1>) {197; CHECK-LABEL: v16i1_v8i1:198; CHECK: # %bb.0:199; CHECK-NEXT: lui a0, %hi(.LCPI4_0)200; CHECK-NEXT: addi a0, a0, %lo(.LCPI4_0)201; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma202; CHECK-NEXT: vle8.v v8, (a0)203; CHECK-NEXT: vmv.v.i v9, 0204; CHECK-NEXT: vmerge.vim v9, v9, 1, v0205; CHECK-NEXT: vrgather.vv v10, v9, v8206; CHECK-NEXT: vmsne.vi v0, v10, 0207; CHECK-NEXT: ret208 %2 = shufflevector <8 x i1> %0, <8 x i1> poison, <16 x i32> <i32 2, i32 3, i32 0, i32 5, i32 1, i32 2, i32 0, i32 6, i32 2, i32 3, i32 0, i32 7, i32 1, i32 2, i32 0, i32 4>209 ret <16 x i1> %2210}211 212define <8 x i32> @v8i32_v4i32(<4 x i32>) {213; CHECK-LABEL: v8i32_v4i32:214; CHECK: # %bb.0:215; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma216; CHECK-NEXT: vmv1r.v v10, v8217; CHECK-NEXT: lui a0, %hi(.LCPI5_0)218; CHECK-NEXT: addi a0, a0, %lo(.LCPI5_0)219; CHECK-NEXT: vle16.v v11, (a0)220; CHECK-NEXT: csrr a0, vlenb221; CHECK-NEXT: srli a0, a0, 2222; CHECK-NEXT: vslidedown.vx v8, v11, a0223; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma224; CHECK-NEXT: vrgatherei16.vv v9, v10, v8225; CHECK-NEXT: vrgatherei16.vv v8, v10, v11226; CHECK-NEXT: ret227 %2 = shufflevector <4 x i32> %0, <4 x i32> poison, <8 x i32> <i32 2, i32 3, i32 0, i32 1, i32 1, i32 2, i32 0, i32 3>228 ret <8 x i32> %2229}230 231define <16 x i32> @v16i32_v4i32(<4 x i32>) {232; CHECK-LABEL: v16i32_v4i32:233; CHECK: # %bb.0:234; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma235; CHECK-NEXT: vmv1r.v v12, v8236; CHECK-NEXT: lui a0, 2237; CHECK-NEXT: vmv.v.i v8, 3238; CHECK-NEXT: addi a1, a0, 265239; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma240; CHECK-NEXT: vmv.s.x v0, a1241; CHECK-NEXT: lui a1, 4242; CHECK-NEXT: addi a1, a1, 548243; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma244; CHECK-NEXT: vmerge.vim v8, v8, 2, v0245; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma246; CHECK-NEXT: vmv.s.x v0, a1247; CHECK-NEXT: csrr a1, vlenb248; CHECK-NEXT: addi a0, a0, -1856249; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma250; CHECK-NEXT: vmerge.vim v8, v8, 0, v0251; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma252; CHECK-NEXT: vmv.s.x v0, a0253; CHECK-NEXT: srli a1, a1, 2254; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma255; CHECK-NEXT: vmerge.vim v8, v8, 1, v0256; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma257; CHECK-NEXT: vsext.vf2 v10, v8258; CHECK-NEXT: vslidedown.vx v14, v10, a1259; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma260; CHECK-NEXT: vrgatherei16.vv v9, v12, v14261; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma262; CHECK-NEXT: vslidedown.vx v14, v14, a1263; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma264; CHECK-NEXT: vrgatherei16.vv v8, v12, v10265; CHECK-NEXT: vrgatherei16.vv v10, v12, v14266; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma267; CHECK-NEXT: vslidedown.vx v14, v14, a1268; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma269; CHECK-NEXT: vrgatherei16.vv v11, v12, v14270; CHECK-NEXT: ret271 %2 = shufflevector <4 x i32> %0, <4 x i32> poison, <16 x i32> <i32 2, i32 3, i32 0, i32 2, i32 3, i32 0, i32 1, i32 1, i32 2, i32 0, i32 3, i32 1, i32 1, i32 2, i32 0, i32 3>272 ret <16 x i32> %2273}274 275define <32 x i32> @v32i32_v4i32(<4 x i32>) {276; CHECK-LABEL: v32i32_v4i32:277; CHECK: # %bb.0:278; CHECK-NEXT: vsetivli zero, 1, e32, m4, ta, ma279; CHECK-NEXT: vmv1r.v v16, v8280; CHECK-NEXT: li a0, 32281; CHECK-NEXT: lui a1, 135432282; CHECK-NEXT: addi a1, a1, 1161283; CHECK-NEXT: vmv.s.x v0, a1284; CHECK-NEXT: lui a1, 270865285; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma286; CHECK-NEXT: vmv.v.i v8, 3287; CHECK-NEXT: addi a1, a1, 548288; CHECK-NEXT: vmerge.vim v8, v8, 2, v0289; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma290; CHECK-NEXT: vmv.s.x v0, a1291; CHECK-NEXT: lui a1, 100550292; CHECK-NEXT: addi a1, a1, 64293; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma294; CHECK-NEXT: vmerge.vim v8, v8, 0, v0295; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma296; CHECK-NEXT: vmv.s.x v0, a1297; CHECK-NEXT: csrr a1, vlenb298; CHECK-NEXT: srli a1, a1, 2299; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma300; CHECK-NEXT: vmerge.vim v8, v8, 1, v0301; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma302; CHECK-NEXT: vsext.vf2 v12, v8303; CHECK-NEXT: vslidedown.vx v20, v12, a1304; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, ma305; CHECK-NEXT: vrgatherei16.vv v9, v16, v20306; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma307; CHECK-NEXT: vslidedown.vx v20, v20, a1308; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, ma309; CHECK-NEXT: vrgatherei16.vv v8, v16, v12310; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma311; CHECK-NEXT: vslidedown.vx v12, v20, a1312; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, ma313; CHECK-NEXT: vrgatherei16.vv v10, v16, v20314; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma315; CHECK-NEXT: vslidedown.vx v20, v12, a1316; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, ma317; CHECK-NEXT: vrgatherei16.vv v11, v16, v12318; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma319; CHECK-NEXT: vslidedown.vx v24, v20, a1320; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, ma321; CHECK-NEXT: vrgatherei16.vv v12, v16, v20322; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma323; CHECK-NEXT: vslidedown.vx v20, v24, a1324; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, ma325; CHECK-NEXT: vrgatherei16.vv v13, v16, v24326; CHECK-NEXT: vrgatherei16.vv v14, v16, v20327; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma328; CHECK-NEXT: vslidedown.vx v20, v20, a1329; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma330; CHECK-NEXT: vrgatherei16.vv v15, v16, v20331; CHECK-NEXT: ret332 %2 = shufflevector <4 x i32> %0, <4 x i32> poison, <32 x i32> <i32 2, i32 3, i32 0, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 2, i32 3, i32 0, i32 1, i32 1, i32 2, i32 0, i32 3, i32 1, i32 1, i32 2, i32 0, i32 3, i32 1, i32 2, i32 0, i32 3, i32 1, i32 1, i32 2, i32 0, i32 3>333 ret <32 x i32> %2334}335 336define <32 x i8> @vnsrl_v32i8_v64i8(<64 x i8> %in) {337; CHECK-LABEL: vnsrl_v32i8_v64i8:338; CHECK: # %bb.0:339; CHECK-NEXT: li a0, 32340; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma341; CHECK-NEXT: vnsrl.wi v12, v8, 8342; CHECK-NEXT: vmv.v.v v8, v12343; CHECK-NEXT: ret344 %res = shufflevector <64 x i8> %in, <64 x i8> poison, <32 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31, i32 33, i32 35, i32 37, i32 39, i32 41, i32 43, i32 45, i32 47, i32 49, i32 51, i32 53, i32 55, i32 57, i32 59, i32 61, i32 63>345 ret <32 x i8> %res346}347