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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc < %s -mtriple=riscv32 -mattr=+v -verify-machineinstrs | FileCheck -check-prefix=VLA %s3; RUN: llc < %s -mtriple=riscv64 -mattr=+v -verify-machineinstrs | FileCheck -check-prefix=VLA %s4 5; RUN: llc < %s -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-max=128 -verify-machineinstrs | FileCheck -check-prefix=VLS %s6; RUN: llc < %s -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-max=128 -verify-machineinstrs | FileCheck -check-prefix=VLS %s7 8define <8 x i32> @concat_2xv4i32(<4 x i32> %a, <4 x i32> %b) {9; VLA-LABEL: concat_2xv4i32:10; VLA: # %bb.0:11; VLA-NEXT: vsetivli zero, 8, e32, m2, ta, ma12; VLA-NEXT: vmv1r.v v10, v913; VLA-NEXT: vslideup.vi v8, v10, 414; VLA-NEXT: ret15;16; VLS-LABEL: concat_2xv4i32:17; VLS: # %bb.0:18; VLS-NEXT: ret19 %ab = shufflevector <4 x i32> %a, <4 x i32> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>20 ret <8 x i32> %ab21}22 23define <8 x i32> @concat_4xv2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c, <2 x i32> %d) {24; VLA-LABEL: concat_4xv2i32:25; VLA: # %bb.0:26; VLA-NEXT: vsetivli zero, 4, e32, m1, ta, ma27; VLA-NEXT: vslideup.vi v10, v11, 228; VLA-NEXT: vslideup.vi v8, v9, 229; VLA-NEXT: vsetivli zero, 8, e32, m2, ta, ma30; VLA-NEXT: vslideup.vi v8, v10, 431; VLA-NEXT: ret32;33; VLS-LABEL: concat_4xv2i32:34; VLS: # %bb.0:35; VLS-NEXT: vsetivli zero, 4, e32, m1, ta, ma36; VLS-NEXT: vmv1r.v v13, v1037; VLS-NEXT: vmv1r.v v12, v838; VLS-NEXT: vslideup.vi v13, v11, 239; VLS-NEXT: vslideup.vi v12, v9, 240; VLS-NEXT: vmv2r.v v8, v1241; VLS-NEXT: ret42 %ab = shufflevector <2 x i32> %a, <2 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 3>43 %cd = shufflevector <2 x i32> %c, <2 x i32> %d, <4 x i32> <i32 0, i32 1, i32 2, i32 3>44 %abcd = shufflevector <4 x i32> %ab, <4 x i32> %cd, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>45 ret <8 x i32> %abcd46}47 48define <8 x i32> @concat_8xv1i32(<1 x i32> %a, <1 x i32> %b, <1 x i32> %c, <1 x i32> %d, <1 x i32> %e, <1 x i32> %f, <1 x i32> %g, <1 x i32> %h) {49; VLA-LABEL: concat_8xv1i32:50; VLA: # %bb.0:51; VLA-NEXT: vsetivli zero, 2, e32, mf2, ta, ma52; VLA-NEXT: vslideup.vi v14, v15, 153; VLA-NEXT: vslideup.vi v12, v13, 154; VLA-NEXT: vslideup.vi v10, v11, 155; VLA-NEXT: vslideup.vi v8, v9, 156; VLA-NEXT: vsetivli zero, 4, e32, m1, ta, ma57; VLA-NEXT: vslideup.vi v12, v14, 258; VLA-NEXT: vslideup.vi v8, v10, 259; VLA-NEXT: vsetivli zero, 8, e32, m2, ta, ma60; VLA-NEXT: vslideup.vi v8, v12, 461; VLA-NEXT: ret62;63; VLS-LABEL: concat_8xv1i32:64; VLS: # %bb.0:65; VLS-NEXT: vsetivli zero, 2, e32, mf2, ta, ma66; VLS-NEXT: vmv1r.v v17, v1267; VLS-NEXT: vmv1r.v v16, v868; VLS-NEXT: vslideup.vi v14, v15, 169; VLS-NEXT: vslideup.vi v17, v13, 170; VLS-NEXT: vsetivli zero, 4, e32, m1, ta, ma71; VLS-NEXT: vslideup.vi v17, v14, 272; VLS-NEXT: vsetivli zero, 2, e32, mf2, ta, ma73; VLS-NEXT: vslideup.vi v10, v11, 174; VLS-NEXT: vslideup.vi v16, v9, 175; VLS-NEXT: vsetivli zero, 4, e32, m1, ta, ma76; VLS-NEXT: vslideup.vi v16, v10, 277; VLS-NEXT: vmv2r.v v8, v1678; VLS-NEXT: ret79 %ab = shufflevector <1 x i32> %a, <1 x i32> %b, <2 x i32> <i32 0, i32 1>80 %cd = shufflevector <1 x i32> %c, <1 x i32> %d, <2 x i32> <i32 0, i32 1>81 %abcd = shufflevector <2 x i32> %ab, <2 x i32> %cd, <4 x i32> <i32 0, i32 1, i32 2, i32 3>82 %ef = shufflevector <1 x i32> %e, <1 x i32> %f, <2 x i32> <i32 0, i32 1>83 %gh = shufflevector <1 x i32> %g, <1 x i32> %h, <2 x i32> <i32 0, i32 1>84 %efgh = shufflevector <2 x i32> %ef, <2 x i32> %gh, <4 x i32> <i32 0, i32 1, i32 2, i32 3>85 %abcdefgh = shufflevector <4 x i32> %abcd, <4 x i32> %efgh, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>86 ret <8 x i32> %abcdefgh87}88 89define <16 x i32> @concat_2xv8i32(<8 x i32> %a, <8 x i32> %b) {90; VLA-LABEL: concat_2xv8i32:91; VLA: # %bb.0:92; VLA-NEXT: vsetivli zero, 16, e32, m4, ta, ma93; VLA-NEXT: vmv2r.v v12, v1094; VLA-NEXT: vslideup.vi v8, v12, 895; VLA-NEXT: ret96;97; VLS-LABEL: concat_2xv8i32:98; VLS: # %bb.0:99; VLS-NEXT: ret100 %v = shufflevector <8 x i32> %a, <8 x i32> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>101 ret <16 x i32> %v102}103 104define <16 x i32> @concat_4xv4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) {105; VLA-LABEL: concat_4xv4i32:106; VLA: # %bb.0:107; VLA-NEXT: vsetivli zero, 8, e32, m2, ta, ma108; VLA-NEXT: vmv1r.v v14, v11109; VLA-NEXT: vmv1r.v v12, v10110; VLA-NEXT: vmv1r.v v10, v9111; VLA-NEXT: vslideup.vi v12, v14, 4112; VLA-NEXT: vslideup.vi v8, v10, 4113; VLA-NEXT: vsetivli zero, 16, e32, m4, ta, ma114; VLA-NEXT: vslideup.vi v8, v12, 8115; VLA-NEXT: ret116;117; VLS-LABEL: concat_4xv4i32:118; VLS: # %bb.0:119; VLS-NEXT: ret120 %ab = shufflevector <4 x i32> %a, <4 x i32> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>121 %cd = shufflevector <4 x i32> %c, <4 x i32> %d, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>122 %abcd = shufflevector <8 x i32> %ab, <8 x i32> %cd, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>123 ret <16 x i32> %abcd124}125 126define <16 x i32> @concat_8xv2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c, <2 x i32> %d, <2 x i32> %e, <2 x i32> %f, <2 x i32> %g, <2 x i32> %h) {127; VLA-LABEL: concat_8xv2i32:128; VLA: # %bb.0:129; VLA-NEXT: vsetivli zero, 4, e32, m1, ta, ma130; VLA-NEXT: vslideup.vi v14, v15, 2131; VLA-NEXT: vslideup.vi v12, v13, 2132; VLA-NEXT: vslideup.vi v10, v11, 2133; VLA-NEXT: vslideup.vi v8, v9, 2134; VLA-NEXT: vsetivli zero, 8, e32, m2, ta, ma135; VLA-NEXT: vslideup.vi v12, v14, 4136; VLA-NEXT: vslideup.vi v8, v10, 4137; VLA-NEXT: vsetivli zero, 16, e32, m4, ta, ma138; VLA-NEXT: vslideup.vi v8, v12, 8139; VLA-NEXT: ret140;141; VLS-LABEL: concat_8xv2i32:142; VLS: # %bb.0:143; VLS-NEXT: vsetivli zero, 4, e32, m1, ta, ma144; VLS-NEXT: vmv1r.v v19, v14145; VLS-NEXT: vmv1r.v v18, v12146; VLS-NEXT: vmv1r.v v17, v10147; VLS-NEXT: vmv1r.v v16, v8148; VLS-NEXT: vslideup.vi v19, v15, 2149; VLS-NEXT: vslideup.vi v18, v13, 2150; VLS-NEXT: vslideup.vi v17, v11, 2151; VLS-NEXT: vslideup.vi v16, v9, 2152; VLS-NEXT: vmv4r.v v8, v16153; VLS-NEXT: ret154 %ab = shufflevector <2 x i32> %a, <2 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 3>155 %cd = shufflevector <2 x i32> %c, <2 x i32> %d, <4 x i32> <i32 0, i32 1, i32 2, i32 3>156 %abcd = shufflevector <4 x i32> %ab, <4 x i32> %cd, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>157 %ef = shufflevector <2 x i32> %e, <2 x i32> %f, <4 x i32> <i32 0, i32 1, i32 2, i32 3>158 %gh = shufflevector <2 x i32> %g, <2 x i32> %h, <4 x i32> <i32 0, i32 1, i32 2, i32 3>159 %efgh = shufflevector <4 x i32> %ef, <4 x i32> %gh, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>160 %abcdefgh = shufflevector <8 x i32> %abcd, <8 x i32> %efgh, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>161 ret <16 x i32> %abcdefgh162}163 164define <32 x i32> @concat_2xv16i32(<16 x i32> %a, <16 x i32> %b) {165; VLA-LABEL: concat_2xv16i32:166; VLA: # %bb.0:167; VLA-NEXT: vsetivli zero, 1, e8, m1, ta, ma168; VLA-NEXT: vmv4r.v v16, v12169; VLA-NEXT: li a0, 32170; VLA-NEXT: vsetvli zero, a0, e32, m8, ta, ma171; VLA-NEXT: vslideup.vi v8, v16, 16172; VLA-NEXT: ret173;174; VLS-LABEL: concat_2xv16i32:175; VLS: # %bb.0:176; VLS-NEXT: ret177 %ab = shufflevector <16 x i32> %a, <16 x i32> %b, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>178 ret <32 x i32> %ab179}180 181define <32 x i32> @concat_4xv8i32(<8 x i32> %a, <8 x i32> %b, <8 x i32> %c, <8 x i32> %d) {182; VLA-LABEL: concat_4xv8i32:183; VLA: # %bb.0:184; VLA-NEXT: vsetivli zero, 16, e32, m4, ta, ma185; VLA-NEXT: vmv2r.v v20, v14186; VLA-NEXT: vmv2r.v v16, v12187; VLA-NEXT: vmv2r.v v12, v10188; VLA-NEXT: li a0, 32189; VLA-NEXT: vslideup.vi v16, v20, 8190; VLA-NEXT: vslideup.vi v8, v12, 8191; VLA-NEXT: vsetvli zero, a0, e32, m8, ta, ma192; VLA-NEXT: vslideup.vi v8, v16, 16193; VLA-NEXT: ret194;195; VLS-LABEL: concat_4xv8i32:196; VLS: # %bb.0:197; VLS-NEXT: ret198 %ab = shufflevector <8 x i32> %a, <8 x i32> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>199 %cd = shufflevector <8 x i32> %c, <8 x i32> %d, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>200 %abcd = shufflevector <16 x i32> %ab, <16 x i32> %cd, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>201 ret <32 x i32> %abcd202}203 204define <32 x i32> @concat_8xv4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d, <4 x i32> %e, <4 x i32> %f, <4 x i32> %g, <4 x i32> %h) {205; VLA-LABEL: concat_8xv4i32:206; VLA: # %bb.0:207; VLA-NEXT: vsetivli zero, 8, e32, m2, ta, ma208; VLA-NEXT: vmv1r.v v18, v15209; VLA-NEXT: vmv1r.v v20, v14210; VLA-NEXT: vmv1r.v v14, v13211; VLA-NEXT: vmv1r.v v16, v12212; VLA-NEXT: vmv1r.v v22, v11213; VLA-NEXT: vmv1r.v v12, v10214; VLA-NEXT: vmv1r.v v10, v9215; VLA-NEXT: li a0, 32216; VLA-NEXT: vslideup.vi v20, v18, 4217; VLA-NEXT: vslideup.vi v16, v14, 4218; VLA-NEXT: vslideup.vi v12, v22, 4219; VLA-NEXT: vslideup.vi v8, v10, 4220; VLA-NEXT: vsetivli zero, 16, e32, m4, ta, ma221; VLA-NEXT: vslideup.vi v16, v20, 8222; VLA-NEXT: vslideup.vi v8, v12, 8223; VLA-NEXT: vsetvli zero, a0, e32, m8, ta, ma224; VLA-NEXT: vslideup.vi v8, v16, 16225; VLA-NEXT: ret226;227; VLS-LABEL: concat_8xv4i32:228; VLS: # %bb.0:229; VLS-NEXT: ret230 %ab = shufflevector <4 x i32> %a, <4 x i32> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>231 %cd = shufflevector <4 x i32> %c, <4 x i32> %d, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>232 %abcd = shufflevector <8 x i32> %ab, <8 x i32> %cd, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>233 %ef = shufflevector <4 x i32> %e, <4 x i32> %f, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>234 %gh = shufflevector <4 x i32> %g, <4 x i32> %h, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>235 %efgh = shufflevector <8 x i32> %ef, <8 x i32> %gh, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>236 %abcdefgh = shufflevector <16 x i32> %abcd, <16 x i32> %efgh, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>237 ret <32 x i32> %abcdefgh238}239