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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfh,+zvl256b \3; RUN: -lower-interleaved-accesses=false -verify-machineinstrs \4; RUN: | FileCheck %s --check-prefixes=CHECK,V5; RUN: llc < %s -mtriple=riscv64 -mattr=+f,+zve32f,+zvfh,+zvl256b \6; RUN: -lower-interleaved-accesses=false -verify-machineinstrs \7; RUN: | FileCheck %s --check-prefixes=CHECK,ZVE32F8; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfh,+zvl256b,+experimental-xrivosvizip \9; RUN: -lower-interleaved-accesses=false -verify-machineinstrs \10; RUN: | FileCheck %s --check-prefixes=CHECK,ZIP11 12define void @vnsrl_0_i8(ptr %in, ptr %out) {13; CHECK-LABEL: vnsrl_0_i8:14; CHECK: # %bb.0: # %entry15; CHECK-NEXT: vsetivli zero, 16, e8, mf2, ta, ma16; CHECK-NEXT: vle8.v v8, (a0)17; CHECK-NEXT: vsetivli zero, 8, e8, mf4, ta, ma18; CHECK-NEXT: vnsrl.wi v8, v8, 019; CHECK-NEXT: vse8.v v8, (a1)20; CHECK-NEXT: ret21entry:22 %0 = load <16 x i8>, ptr %in, align 123 %shuffle.i5 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>24 store <8 x i8> %shuffle.i5, ptr %out, align 125 ret void26}27 28define void @vnsrl_8_i8(ptr %in, ptr %out) {29; CHECK-LABEL: vnsrl_8_i8:30; CHECK: # %bb.0: # %entry31; CHECK-NEXT: vsetivli zero, 16, e8, mf2, ta, ma32; CHECK-NEXT: vle8.v v8, (a0)33; CHECK-NEXT: vsetivli zero, 8, e8, mf4, ta, ma34; CHECK-NEXT: vnsrl.wi v8, v8, 835; CHECK-NEXT: vse8.v v8, (a1)36; CHECK-NEXT: ret37entry:38 %0 = load <16 x i8>, ptr %in, align 139 %shuffle.i5 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>40 store <8 x i8> %shuffle.i5, ptr %out, align 141 ret void42}43 44define void @vnsrl_0_i16(ptr %in, ptr %out) {45; V-LABEL: vnsrl_0_i16:46; V: # %bb.0: # %entry47; V-NEXT: vsetivli zero, 8, e16, mf2, ta, ma48; V-NEXT: vle16.v v8, (a0)49; V-NEXT: vsetivli zero, 4, e16, mf4, ta, ma50; V-NEXT: vnsrl.wi v8, v8, 051; V-NEXT: vse16.v v8, (a1)52; V-NEXT: ret53;54; ZVE32F-LABEL: vnsrl_0_i16:55; ZVE32F: # %bb.0: # %entry56; ZVE32F-NEXT: vsetivli zero, 8, e16, mf2, ta, ma57; ZVE32F-NEXT: vle16.v v8, (a0)58; ZVE32F-NEXT: vsetivli zero, 4, e16, mf2, ta, ma59; ZVE32F-NEXT: vnsrl.wi v8, v8, 060; ZVE32F-NEXT: vse16.v v8, (a1)61; ZVE32F-NEXT: ret62;63; ZIP-LABEL: vnsrl_0_i16:64; ZIP: # %bb.0: # %entry65; ZIP-NEXT: vsetivli zero, 8, e16, mf2, ta, ma66; ZIP-NEXT: vle16.v v8, (a0)67; ZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma68; ZIP-NEXT: vnsrl.wi v8, v8, 069; ZIP-NEXT: vse16.v v8, (a1)70; ZIP-NEXT: ret71entry:72 %0 = load <8 x i16>, ptr %in, align 273 %shuffle.i5 = shufflevector <8 x i16> %0, <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>74 store <4 x i16> %shuffle.i5, ptr %out, align 275 ret void76}77 78define void @vnsrl_16_i16(ptr %in, ptr %out) {79; V-LABEL: vnsrl_16_i16:80; V: # %bb.0: # %entry81; V-NEXT: vsetivli zero, 8, e16, mf2, ta, ma82; V-NEXT: vle16.v v8, (a0)83; V-NEXT: vsetivli zero, 4, e16, mf4, ta, ma84; V-NEXT: vnsrl.wi v8, v8, 1685; V-NEXT: vse16.v v8, (a1)86; V-NEXT: ret87;88; ZVE32F-LABEL: vnsrl_16_i16:89; ZVE32F: # %bb.0: # %entry90; ZVE32F-NEXT: vsetivli zero, 8, e16, mf2, ta, ma91; ZVE32F-NEXT: vle16.v v8, (a0)92; ZVE32F-NEXT: vsetivli zero, 4, e16, mf2, ta, ma93; ZVE32F-NEXT: vnsrl.wi v8, v8, 1694; ZVE32F-NEXT: vse16.v v8, (a1)95; ZVE32F-NEXT: ret96;97; ZIP-LABEL: vnsrl_16_i16:98; ZIP: # %bb.0: # %entry99; ZIP-NEXT: vsetivli zero, 8, e16, mf2, ta, ma100; ZIP-NEXT: vle16.v v8, (a0)101; ZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma102; ZIP-NEXT: vnsrl.wi v8, v8, 16103; ZIP-NEXT: vse16.v v8, (a1)104; ZIP-NEXT: ret105entry:106 %0 = load <8 x i16>, ptr %in, align 2107 %shuffle.i5 = shufflevector <8 x i16> %0, <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>108 store <4 x i16> %shuffle.i5, ptr %out, align 2109 ret void110}111 112define void @vnsrl_0_half(ptr %in, ptr %out) {113; V-LABEL: vnsrl_0_half:114; V: # %bb.0: # %entry115; V-NEXT: vsetivli zero, 8, e16, mf2, ta, ma116; V-NEXT: vle16.v v8, (a0)117; V-NEXT: vsetivli zero, 4, e16, mf4, ta, ma118; V-NEXT: vnsrl.wi v8, v8, 0119; V-NEXT: vse16.v v8, (a1)120; V-NEXT: ret121;122; ZVE32F-LABEL: vnsrl_0_half:123; ZVE32F: # %bb.0: # %entry124; ZVE32F-NEXT: vsetivli zero, 8, e16, mf2, ta, ma125; ZVE32F-NEXT: vle16.v v8, (a0)126; ZVE32F-NEXT: vsetivli zero, 4, e16, mf2, ta, ma127; ZVE32F-NEXT: vnsrl.wi v8, v8, 0128; ZVE32F-NEXT: vse16.v v8, (a1)129; ZVE32F-NEXT: ret130;131; ZIP-LABEL: vnsrl_0_half:132; ZIP: # %bb.0: # %entry133; ZIP-NEXT: vsetivli zero, 8, e16, mf2, ta, ma134; ZIP-NEXT: vle16.v v8, (a0)135; ZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma136; ZIP-NEXT: vnsrl.wi v8, v8, 0137; ZIP-NEXT: vse16.v v8, (a1)138; ZIP-NEXT: ret139entry:140 %0 = load <8 x half>, ptr %in, align 2141 %shuffle.i5 = shufflevector <8 x half> %0, <8 x half> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>142 store <4 x half> %shuffle.i5, ptr %out, align 2143 ret void144}145 146define void @vnsrl_16_half(ptr %in, ptr %out) {147; V-LABEL: vnsrl_16_half:148; V: # %bb.0: # %entry149; V-NEXT: vsetivli zero, 8, e16, mf2, ta, ma150; V-NEXT: vle16.v v8, (a0)151; V-NEXT: vsetivli zero, 4, e16, mf4, ta, ma152; V-NEXT: vnsrl.wi v8, v8, 16153; V-NEXT: vse16.v v8, (a1)154; V-NEXT: ret155;156; ZVE32F-LABEL: vnsrl_16_half:157; ZVE32F: # %bb.0: # %entry158; ZVE32F-NEXT: vsetivli zero, 8, e16, mf2, ta, ma159; ZVE32F-NEXT: vle16.v v8, (a0)160; ZVE32F-NEXT: vsetivli zero, 4, e16, mf2, ta, ma161; ZVE32F-NEXT: vnsrl.wi v8, v8, 16162; ZVE32F-NEXT: vse16.v v8, (a1)163; ZVE32F-NEXT: ret164;165; ZIP-LABEL: vnsrl_16_half:166; ZIP: # %bb.0: # %entry167; ZIP-NEXT: vsetivli zero, 8, e16, mf2, ta, ma168; ZIP-NEXT: vle16.v v8, (a0)169; ZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma170; ZIP-NEXT: vnsrl.wi v8, v8, 16171; ZIP-NEXT: vse16.v v8, (a1)172; ZIP-NEXT: ret173entry:174 %0 = load <8 x half>, ptr %in, align 2175 %shuffle.i5 = shufflevector <8 x half> %0, <8 x half> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>176 store <4 x half> %shuffle.i5, ptr %out, align 2177 ret void178}179 180define void @vnsrl_0_i32(ptr %in, ptr %out) {181; V-LABEL: vnsrl_0_i32:182; V: # %bb.0: # %entry183; V-NEXT: vsetivli zero, 4, e32, mf2, ta, ma184; V-NEXT: vle32.v v8, (a0)185; V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma186; V-NEXT: vnsrl.wi v8, v8, 0187; V-NEXT: vse32.v v8, (a1)188; V-NEXT: ret189;190; ZVE32F-LABEL: vnsrl_0_i32:191; ZVE32F: # %bb.0: # %entry192; ZVE32F-NEXT: vsetivli zero, 4, e32, m1, ta, ma193; ZVE32F-NEXT: vle32.v v8, (a0)194; ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma195; ZVE32F-NEXT: vslidedown.vi v9, v8, 2196; ZVE32F-NEXT: vslideup.vi v8, v9, 1197; ZVE32F-NEXT: vse32.v v8, (a1)198; ZVE32F-NEXT: ret199;200; ZIP-LABEL: vnsrl_0_i32:201; ZIP: # %bb.0: # %entry202; ZIP-NEXT: vsetivli zero, 4, e32, mf2, ta, ma203; ZIP-NEXT: vle32.v v8, (a0)204; ZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma205; ZIP-NEXT: vnsrl.wi v8, v8, 0206; ZIP-NEXT: vse32.v v8, (a1)207; ZIP-NEXT: ret208entry:209 %0 = load <4 x i32>, ptr %in, align 4210 %shuffle.i5 = shufflevector <4 x i32> %0, <4 x i32> poison, <2 x i32> <i32 0, i32 2>211 store <2 x i32> %shuffle.i5, ptr %out, align 4212 ret void213}214 215define void @vnsrl_32_i32(ptr %in, ptr %out) {216; V-LABEL: vnsrl_32_i32:217; V: # %bb.0: # %entry218; V-NEXT: vsetivli zero, 4, e32, mf2, ta, ma219; V-NEXT: vle32.v v8, (a0)220; V-NEXT: li a0, 32221; V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma222; V-NEXT: vnsrl.wx v8, v8, a0223; V-NEXT: vse32.v v8, (a1)224; V-NEXT: ret225;226; ZVE32F-LABEL: vnsrl_32_i32:227; ZVE32F: # %bb.0: # %entry228; ZVE32F-NEXT: vsetivli zero, 4, e32, m1, ta, ma229; ZVE32F-NEXT: vle32.v v8, (a0)230; ZVE32F-NEXT: vmv.v.i v0, 1231; ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, mu232; ZVE32F-NEXT: vslidedown.vi v9, v8, 2233; ZVE32F-NEXT: vslidedown.vi v9, v8, 1, v0.t234; ZVE32F-NEXT: vse32.v v9, (a1)235; ZVE32F-NEXT: ret236;237; ZIP-LABEL: vnsrl_32_i32:238; ZIP: # %bb.0: # %entry239; ZIP-NEXT: vsetivli zero, 4, e32, mf2, ta, ma240; ZIP-NEXT: vle32.v v8, (a0)241; ZIP-NEXT: li a0, 32242; ZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma243; ZIP-NEXT: vnsrl.wx v8, v8, a0244; ZIP-NEXT: vse32.v v8, (a1)245; ZIP-NEXT: ret246entry:247 %0 = load <4 x i32>, ptr %in, align 4248 %shuffle.i5 = shufflevector <4 x i32> %0, <4 x i32> poison, <2 x i32> <i32 1, i32 3>249 store <2 x i32> %shuffle.i5, ptr %out, align 4250 ret void251}252 253define void @vnsrl_0_float(ptr %in, ptr %out) {254; V-LABEL: vnsrl_0_float:255; V: # %bb.0: # %entry256; V-NEXT: vsetivli zero, 4, e32, mf2, ta, ma257; V-NEXT: vle32.v v8, (a0)258; V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma259; V-NEXT: vnsrl.wi v8, v8, 0260; V-NEXT: vse32.v v8, (a1)261; V-NEXT: ret262;263; ZVE32F-LABEL: vnsrl_0_float:264; ZVE32F: # %bb.0: # %entry265; ZVE32F-NEXT: vsetivli zero, 4, e32, m1, ta, ma266; ZVE32F-NEXT: vle32.v v8, (a0)267; ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma268; ZVE32F-NEXT: vslidedown.vi v9, v8, 2269; ZVE32F-NEXT: vslideup.vi v8, v9, 1270; ZVE32F-NEXT: vse32.v v8, (a1)271; ZVE32F-NEXT: ret272;273; ZIP-LABEL: vnsrl_0_float:274; ZIP: # %bb.0: # %entry275; ZIP-NEXT: vsetivli zero, 4, e32, mf2, ta, ma276; ZIP-NEXT: vle32.v v8, (a0)277; ZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma278; ZIP-NEXT: vnsrl.wi v8, v8, 0279; ZIP-NEXT: vse32.v v8, (a1)280; ZIP-NEXT: ret281entry:282 %0 = load <4 x float>, ptr %in, align 4283 %shuffle.i5 = shufflevector <4 x float> %0, <4 x float> poison, <2 x i32> <i32 0, i32 2>284 store <2 x float> %shuffle.i5, ptr %out, align 4285 ret void286}287 288define void @vnsrl_32_float(ptr %in, ptr %out) {289; V-LABEL: vnsrl_32_float:290; V: # %bb.0: # %entry291; V-NEXT: vsetivli zero, 4, e32, mf2, ta, ma292; V-NEXT: vle32.v v8, (a0)293; V-NEXT: li a0, 32294; V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma295; V-NEXT: vnsrl.wx v8, v8, a0296; V-NEXT: vse32.v v8, (a1)297; V-NEXT: ret298;299; ZVE32F-LABEL: vnsrl_32_float:300; ZVE32F: # %bb.0: # %entry301; ZVE32F-NEXT: vsetivli zero, 4, e32, m1, ta, ma302; ZVE32F-NEXT: vle32.v v8, (a0)303; ZVE32F-NEXT: vmv.v.i v0, 1304; ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, mu305; ZVE32F-NEXT: vslidedown.vi v9, v8, 2306; ZVE32F-NEXT: vslidedown.vi v9, v8, 1, v0.t307; ZVE32F-NEXT: vse32.v v9, (a1)308; ZVE32F-NEXT: ret309;310; ZIP-LABEL: vnsrl_32_float:311; ZIP: # %bb.0: # %entry312; ZIP-NEXT: vsetivli zero, 4, e32, mf2, ta, ma313; ZIP-NEXT: vle32.v v8, (a0)314; ZIP-NEXT: li a0, 32315; ZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma316; ZIP-NEXT: vnsrl.wx v8, v8, a0317; ZIP-NEXT: vse32.v v8, (a1)318; ZIP-NEXT: ret319entry:320 %0 = load <4 x float>, ptr %in, align 4321 %shuffle.i5 = shufflevector <4 x float> %0, <4 x float> poison, <2 x i32> <i32 1, i32 3>322 store <2 x float> %shuffle.i5, ptr %out, align 4323 ret void324}325 326define void @vnsrl_0_i64(ptr %in, ptr %out) {327; V-LABEL: vnsrl_0_i64:328; V: # %bb.0: # %entry329; V-NEXT: vsetivli zero, 4, e64, m1, ta, ma330; V-NEXT: vle64.v v8, (a0)331; V-NEXT: vsetivli zero, 2, e64, m1, ta, ma332; V-NEXT: vslidedown.vi v9, v8, 2333; V-NEXT: vslideup.vi v8, v9, 1334; V-NEXT: vse64.v v8, (a1)335; V-NEXT: ret336;337; ZVE32F-LABEL: vnsrl_0_i64:338; ZVE32F: # %bb.0: # %entry339; ZVE32F-NEXT: ld a2, 0(a0)340; ZVE32F-NEXT: ld a0, 16(a0)341; ZVE32F-NEXT: sd a2, 0(a1)342; ZVE32F-NEXT: sd a0, 8(a1)343; ZVE32F-NEXT: ret344;345; ZIP-LABEL: vnsrl_0_i64:346; ZIP: # %bb.0: # %entry347; ZIP-NEXT: vsetivli zero, 4, e64, m1, ta, ma348; ZIP-NEXT: vle64.v v8, (a0)349; ZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma350; ZIP-NEXT: ri.vunzip2a.vv v10, v8, v9351; ZIP-NEXT: vse64.v v10, (a1)352; ZIP-NEXT: ret353entry:354 %0 = load <4 x i64>, ptr %in, align 8355 %shuffle.i5 = shufflevector <4 x i64> %0, <4 x i64> poison, <2 x i32> <i32 0, i32 2>356 store <2 x i64> %shuffle.i5, ptr %out, align 8357 ret void358}359 360define void @vnsrl_64_i64(ptr %in, ptr %out) {361; V-LABEL: vnsrl_64_i64:362; V: # %bb.0: # %entry363; V-NEXT: vsetivli zero, 4, e64, m1, ta, ma364; V-NEXT: vle64.v v8, (a0)365; V-NEXT: vmv.v.i v0, 1366; V-NEXT: vsetivli zero, 2, e64, m1, ta, mu367; V-NEXT: vslidedown.vi v9, v8, 2368; V-NEXT: vslidedown.vi v9, v8, 1, v0.t369; V-NEXT: vse64.v v9, (a1)370; V-NEXT: ret371;372; ZVE32F-LABEL: vnsrl_64_i64:373; ZVE32F: # %bb.0: # %entry374; ZVE32F-NEXT: ld a2, 8(a0)375; ZVE32F-NEXT: ld a0, 24(a0)376; ZVE32F-NEXT: sd a2, 0(a1)377; ZVE32F-NEXT: sd a0, 8(a1)378; ZVE32F-NEXT: ret379;380; ZIP-LABEL: vnsrl_64_i64:381; ZIP: # %bb.0: # %entry382; ZIP-NEXT: vsetivli zero, 4, e64, m1, ta, ma383; ZIP-NEXT: vle64.v v8, (a0)384; ZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma385; ZIP-NEXT: ri.vunzip2b.vv v10, v8, v9386; ZIP-NEXT: vse64.v v10, (a1)387; ZIP-NEXT: ret388entry:389 %0 = load <4 x i64>, ptr %in, align 8390 %shuffle.i5 = shufflevector <4 x i64> %0, <4 x i64> poison, <2 x i32> <i32 1, i32 3>391 store <2 x i64> %shuffle.i5, ptr %out, align 8392 ret void393}394 395define void @vnsrl_0_double(ptr %in, ptr %out) {396; V-LABEL: vnsrl_0_double:397; V: # %bb.0: # %entry398; V-NEXT: vsetivli zero, 4, e64, m1, ta, ma399; V-NEXT: vle64.v v8, (a0)400; V-NEXT: vsetivli zero, 2, e64, m1, ta, ma401; V-NEXT: vslidedown.vi v9, v8, 2402; V-NEXT: vslideup.vi v8, v9, 1403; V-NEXT: vse64.v v8, (a1)404; V-NEXT: ret405;406; ZVE32F-LABEL: vnsrl_0_double:407; ZVE32F: # %bb.0: # %entry408; ZVE32F-NEXT: ld a2, 0(a0)409; ZVE32F-NEXT: ld a0, 16(a0)410; ZVE32F-NEXT: sd a2, 0(a1)411; ZVE32F-NEXT: sd a0, 8(a1)412; ZVE32F-NEXT: ret413;414; ZIP-LABEL: vnsrl_0_double:415; ZIP: # %bb.0: # %entry416; ZIP-NEXT: vsetivli zero, 4, e64, m1, ta, ma417; ZIP-NEXT: vle64.v v8, (a0)418; ZIP-NEXT: ri.vunzip2a.vv v10, v8, v9419; ZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma420; ZIP-NEXT: vse64.v v10, (a1)421; ZIP-NEXT: ret422entry:423 %0 = load <4 x double>, ptr %in, align 8424 %shuffle.i5 = shufflevector <4 x double> %0, <4 x double> poison, <2 x i32> <i32 0, i32 2>425 store <2 x double> %shuffle.i5, ptr %out, align 8426 ret void427}428 429define void @vnsrl_64_double(ptr %in, ptr %out) {430; V-LABEL: vnsrl_64_double:431; V: # %bb.0: # %entry432; V-NEXT: vsetivli zero, 4, e64, m1, ta, ma433; V-NEXT: vle64.v v8, (a0)434; V-NEXT: vmv.v.i v0, 1435; V-NEXT: vsetivli zero, 2, e64, m1, ta, mu436; V-NEXT: vslidedown.vi v9, v8, 2437; V-NEXT: vslidedown.vi v9, v8, 1, v0.t438; V-NEXT: vse64.v v9, (a1)439; V-NEXT: ret440;441; ZVE32F-LABEL: vnsrl_64_double:442; ZVE32F: # %bb.0: # %entry443; ZVE32F-NEXT: ld a2, 8(a0)444; ZVE32F-NEXT: ld a0, 24(a0)445; ZVE32F-NEXT: sd a2, 0(a1)446; ZVE32F-NEXT: sd a0, 8(a1)447; ZVE32F-NEXT: ret448;449; ZIP-LABEL: vnsrl_64_double:450; ZIP: # %bb.0: # %entry451; ZIP-NEXT: vsetivli zero, 4, e64, m1, ta, ma452; ZIP-NEXT: vle64.v v8, (a0)453; ZIP-NEXT: ri.vunzip2b.vv v10, v8, v9454; ZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma455; ZIP-NEXT: vse64.v v10, (a1)456; ZIP-NEXT: ret457entry:458 %0 = load <4 x double>, ptr %in, align 8459 %shuffle.i5 = shufflevector <4 x double> %0, <4 x double> poison, <2 x i32> <i32 1, i32 3>460 store <2 x double> %shuffle.i5, ptr %out, align 8461 ret void462}463 464define void @vnsrl_0_i8_undef(ptr %in, ptr %out) {465; CHECK-LABEL: vnsrl_0_i8_undef:466; CHECK: # %bb.0: # %entry467; CHECK-NEXT: vsetivli zero, 16, e8, mf2, ta, ma468; CHECK-NEXT: vle8.v v8, (a0)469; CHECK-NEXT: vsetivli zero, 8, e8, mf4, ta, ma470; CHECK-NEXT: vnsrl.wi v8, v8, 0471; CHECK-NEXT: vse8.v v8, (a1)472; CHECK-NEXT: ret473entry:474 %0 = load <16 x i8>, ptr %in, align 1475 %shuffle.i5 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 poison, i32 poison>476 store <8 x i8> %shuffle.i5, ptr %out, align 1477 ret void478}479 480define void @vnsrl_0_i8_undef2(ptr %in, ptr %out) {481; CHECK-LABEL: vnsrl_0_i8_undef2:482; CHECK: # %bb.0: # %entry483; CHECK-NEXT: vsetivli zero, 16, e8, mf2, ta, ma484; CHECK-NEXT: vle8.v v8, (a0)485; CHECK-NEXT: vsetivli zero, 8, e8, mf4, ta, ma486; CHECK-NEXT: vnsrl.wi v8, v8, 0487; CHECK-NEXT: vse8.v v8, (a1)488; CHECK-NEXT: ret489entry:490 %0 = load <16 x i8>, ptr %in, align 1491 %shuffle.i5 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> <i32 0, i32 2, i32 poison, i32 6, i32 poison, i32 10, i32 12, i32 14>492 store <8 x i8> %shuffle.i5, ptr %out, align 1493 ret void494}495 496define void @vnsrl_0_i8_undef3(ptr %in, ptr %out) {497; CHECK-LABEL: vnsrl_0_i8_undef3:498; CHECK: # %bb.0: # %entry499; CHECK-NEXT: vsetivli zero, 16, e8, mf2, ta, ma500; CHECK-NEXT: vle8.v v8, (a0)501; CHECK-NEXT: vsetivli zero, 8, e8, mf4, ta, ma502; CHECK-NEXT: vnsrl.wi v8, v8, 0503; CHECK-NEXT: vse8.v v8, (a1)504; CHECK-NEXT: ret505entry:506 %0 = load <16 x i8>, ptr %in, align 1507 %shuffle.i5 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> <i32 poison, i32 poison, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>508 store <8 x i8> %shuffle.i5, ptr %out, align 1509 ret void510}511 512; Not a vnsrl (checking for a prior pattern matching bug)513define void @vnsrl_0_i8_undef_negative(ptr %in, ptr %out) {514; CHECK-LABEL: vnsrl_0_i8_undef_negative:515; CHECK: # %bb.0: # %entry516; CHECK-NEXT: vsetivli zero, 16, e8, mf2, ta, ma517; CHECK-NEXT: vle8.v v8, (a0)518; CHECK-NEXT: li a0, 32519; CHECK-NEXT: vmv.s.x v0, a0520; CHECK-NEXT: lui a0, %hi(.LCPI17_0)521; CHECK-NEXT: addi a0, a0, %lo(.LCPI17_0)522; CHECK-NEXT: vsetivli zero, 8, e8, mf4, ta, ma523; CHECK-NEXT: vle8.v v9, (a0)524; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma525; CHECK-NEXT: vslidedown.vi v10, v8, 8526; CHECK-NEXT: vsetivli zero, 8, e8, mf4, ta, mu527; CHECK-NEXT: vslideup.vi v11, v10, 4528; CHECK-NEXT: vslideup.vi v11, v10, 3, v0.t529; CHECK-NEXT: li a0, 48530; CHECK-NEXT: vmv.s.x v0, a0531; CHECK-NEXT: vrgather.vv v10, v8, v9532; CHECK-NEXT: vmerge.vvm v8, v10, v11, v0533; CHECK-NEXT: vse8.v v8, (a1)534; CHECK-NEXT: ret535entry:536 %0 = load <16 x i8>, ptr %in, align 1537 %shuffle.i5 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 poison, i32 1>538 store <8 x i8> %shuffle.i5, ptr %out, align 1539 ret void540}541 542define void @vnsrl_0_i8_single_src(ptr %in, ptr %out) {543; V-LABEL: vnsrl_0_i8_single_src:544; V: # %bb.0: # %entry545; V-NEXT: vsetivli zero, 8, e8, mf4, ta, ma546; V-NEXT: vle8.v v8, (a0)547; V-NEXT: vsetivli zero, 4, e8, mf8, ta, ma548; V-NEXT: vnsrl.wi v8, v8, 0549; V-NEXT: vse8.v v8, (a1)550; V-NEXT: ret551;552; ZVE32F-LABEL: vnsrl_0_i8_single_src:553; ZVE32F: # %bb.0: # %entry554; ZVE32F-NEXT: vsetivli zero, 8, e8, mf4, ta, ma555; ZVE32F-NEXT: vle8.v v8, (a0)556; ZVE32F-NEXT: vsetivli zero, 4, e8, mf4, ta, ma557; ZVE32F-NEXT: vnsrl.wi v8, v8, 0558; ZVE32F-NEXT: vse8.v v8, (a1)559; ZVE32F-NEXT: ret560;561; ZIP-LABEL: vnsrl_0_i8_single_src:562; ZIP: # %bb.0: # %entry563; ZIP-NEXT: vsetivli zero, 8, e8, mf4, ta, ma564; ZIP-NEXT: vle8.v v8, (a0)565; ZIP-NEXT: vsetivli zero, 4, e8, mf8, ta, ma566; ZIP-NEXT: vnsrl.wi v8, v8, 0567; ZIP-NEXT: vse8.v v8, (a1)568; ZIP-NEXT: ret569entry:570 %0 = load <8 x i8>, ptr %in, align 1571 %shuffle.i5 = shufflevector <8 x i8> %0, <8 x i8> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>572 store <4 x i8> %shuffle.i5, ptr %out, align 1573 ret void574}575 576define void @vnsrl_8_i8_single_src(ptr %in, ptr %out) {577; V-LABEL: vnsrl_8_i8_single_src:578; V: # %bb.0: # %entry579; V-NEXT: vsetivli zero, 8, e8, mf4, ta, ma580; V-NEXT: vle8.v v8, (a0)581; V-NEXT: vsetivli zero, 4, e8, mf8, ta, ma582; V-NEXT: vnsrl.wi v8, v8, 8583; V-NEXT: vse8.v v8, (a1)584; V-NEXT: ret585;586; ZVE32F-LABEL: vnsrl_8_i8_single_src:587; ZVE32F: # %bb.0: # %entry588; ZVE32F-NEXT: vsetivli zero, 8, e8, mf4, ta, ma589; ZVE32F-NEXT: vle8.v v8, (a0)590; ZVE32F-NEXT: vsetivli zero, 4, e8, mf4, ta, ma591; ZVE32F-NEXT: vnsrl.wi v8, v8, 8592; ZVE32F-NEXT: vse8.v v8, (a1)593; ZVE32F-NEXT: ret594;595; ZIP-LABEL: vnsrl_8_i8_single_src:596; ZIP: # %bb.0: # %entry597; ZIP-NEXT: vsetivli zero, 8, e8, mf4, ta, ma598; ZIP-NEXT: vle8.v v8, (a0)599; ZIP-NEXT: vsetivli zero, 4, e8, mf8, ta, ma600; ZIP-NEXT: vnsrl.wi v8, v8, 8601; ZIP-NEXT: vse8.v v8, (a1)602; ZIP-NEXT: ret603entry:604 %0 = load <8 x i8>, ptr %in, align 1605 %shuffle.i5 = shufflevector <8 x i8> %0, <8 x i8> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>606 store <4 x i8> %shuffle.i5, ptr %out, align 1607 ret void608}609 610define void @vnsrl_0_i8_single_wideuse(ptr %in, ptr %out) {611; V-LABEL: vnsrl_0_i8_single_wideuse:612; V: # %bb.0: # %entry613; V-NEXT: vsetivli zero, 8, e8, mf4, ta, ma614; V-NEXT: vle8.v v8, (a0)615; V-NEXT: vsetivli zero, 4, e8, mf8, ta, ma616; V-NEXT: vnsrl.wi v8, v8, 0617; V-NEXT: vsetivli zero, 8, e8, mf4, ta, ma618; V-NEXT: vse8.v v8, (a1)619; V-NEXT: ret620;621; ZVE32F-LABEL: vnsrl_0_i8_single_wideuse:622; ZVE32F: # %bb.0: # %entry623; ZVE32F-NEXT: vsetivli zero, 8, e8, mf4, ta, ma624; ZVE32F-NEXT: vle8.v v8, (a0)625; ZVE32F-NEXT: vsetivli zero, 4, e8, mf4, ta, ma626; ZVE32F-NEXT: vnsrl.wi v8, v8, 0627; ZVE32F-NEXT: vsetivli zero, 8, e8, mf4, ta, ma628; ZVE32F-NEXT: vse8.v v8, (a1)629; ZVE32F-NEXT: ret630;631; ZIP-LABEL: vnsrl_0_i8_single_wideuse:632; ZIP: # %bb.0: # %entry633; ZIP-NEXT: vsetivli zero, 8, e8, mf4, ta, ma634; ZIP-NEXT: vle8.v v8, (a0)635; ZIP-NEXT: vsetivli zero, 4, e8, mf8, ta, ma636; ZIP-NEXT: vnsrl.wi v8, v8, 0637; ZIP-NEXT: vsetivli zero, 8, e8, mf4, ta, ma638; ZIP-NEXT: vse8.v v8, (a1)639; ZIP-NEXT: ret640entry:641 %0 = load <8 x i8>, ptr %in, align 1642 %shuffle.i5 = shufflevector <8 x i8> %0, <8 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 poison, i32 poison, i32 poison, i32 poison>643 store <8 x i8> %shuffle.i5, ptr %out, align 1644 ret void645}646 647; FIXME: We could use a smaller vl for the vnsrl since some elts are undefined.648define void @vnsrl_0_i32_single_src_m8(ptr %in, ptr %out) {649; V-LABEL: vnsrl_0_i32_single_src_m8:650; V: # %bb.0: # %entry651; V-NEXT: li a2, 64652; V-NEXT: vsetvli zero, a2, e32, m8, ta, ma653; V-NEXT: vle32.v v8, (a0)654; V-NEXT: li a0, 32655; V-NEXT: vsetvli zero, a0, e32, m4, ta, ma656; V-NEXT: vnsrl.wi v16, v8, 0657; V-NEXT: vsetvli zero, a2, e32, m8, ta, ma658; V-NEXT: vse32.v v16, (a1)659; V-NEXT: ret660;661; ZVE32F-LABEL: vnsrl_0_i32_single_src_m8:662; ZVE32F: # %bb.0: # %entry663; ZVE32F-NEXT: li a2, 64664; ZVE32F-NEXT: vsetvli zero, a2, e32, m8, ta, ma665; ZVE32F-NEXT: vle32.v v8, (a0)666; ZVE32F-NEXT: lui a0, 341667; ZVE32F-NEXT: addi a0, a0, 1365668; ZVE32F-NEXT: vmv.s.x v12, a0669; ZVE32F-NEXT: li a0, 32670; ZVE32F-NEXT: vsetvli zero, a0, e32, m4, ta, ma671; ZVE32F-NEXT: vcompress.vm v16, v8, v12672; ZVE32F-NEXT: vsetvli zero, a2, e32, m8, ta, ma673; ZVE32F-NEXT: vse32.v v16, (a1)674; ZVE32F-NEXT: ret675;676; ZIP-LABEL: vnsrl_0_i32_single_src_m8:677; ZIP: # %bb.0: # %entry678; ZIP-NEXT: li a2, 64679; ZIP-NEXT: vsetvli zero, a2, e32, m8, ta, ma680; ZIP-NEXT: vle32.v v8, (a0)681; ZIP-NEXT: li a0, 32682; ZIP-NEXT: vsetvli zero, a0, e32, m4, ta, ma683; ZIP-NEXT: vnsrl.wi v16, v8, 0684; ZIP-NEXT: vsetvli zero, a2, e32, m8, ta, ma685; ZIP-NEXT: vse32.v v16, (a1)686; ZIP-NEXT: ret687entry:688 %0 = load <64 x i32>, ptr %in, align 4689 %shuffle.i5 = shufflevector <64 x i32> %0, <64 x i32> poison, <64 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>690 store <64 x i32> %shuffle.i5, ptr %out, align 4691 ret void692}693 694define void @vnsrl_0_i32_single_src_m8_2(ptr %in, ptr %out) {695; V-LABEL: vnsrl_0_i32_single_src_m8_2:696; V: # %bb.0: # %entry697; V-NEXT: li a2, 64698; V-NEXT: vsetvli zero, a2, e32, m8, ta, ma699; V-NEXT: vle32.v v8, (a0)700; V-NEXT: li a0, 32701; V-NEXT: vsetvli zero, a0, e32, m4, ta, ma702; V-NEXT: vnsrl.wi v16, v8, 0703; V-NEXT: vsetvli zero, a2, e32, m8, ta, ma704; V-NEXT: vse32.v v16, (a1)705; V-NEXT: ret706;707; ZVE32F-LABEL: vnsrl_0_i32_single_src_m8_2:708; ZVE32F: # %bb.0: # %entry709; ZVE32F-NEXT: li a2, 64710; ZVE32F-NEXT: vsetvli zero, a2, e32, m8, ta, ma711; ZVE32F-NEXT: vle32.v v8, (a0)712; ZVE32F-NEXT: lui a0, 349525713; ZVE32F-NEXT: addi a0, a0, 1365714; ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma715; ZVE32F-NEXT: vmv.v.x v24, a0716; ZVE32F-NEXT: vsetvli zero, a2, e32, m8, ta, ma717; ZVE32F-NEXT: vcompress.vm v16, v8, v24718; ZVE32F-NEXT: vse32.v v16, (a1)719; ZVE32F-NEXT: ret720;721; ZIP-LABEL: vnsrl_0_i32_single_src_m8_2:722; ZIP: # %bb.0: # %entry723; ZIP-NEXT: li a2, 64724; ZIP-NEXT: vsetvli zero, a2, e32, m8, ta, ma725; ZIP-NEXT: vle32.v v8, (a0)726; ZIP-NEXT: li a0, 32727; ZIP-NEXT: vsetvli zero, a0, e32, m4, ta, ma728; ZIP-NEXT: vnsrl.wi v16, v8, 0729; ZIP-NEXT: vsetvli zero, a2, e32, m8, ta, ma730; ZIP-NEXT: vse32.v v16, (a1)731; ZIP-NEXT: ret732entry:733 %0 = load <64 x i32>, ptr %in, align 4734 %shuffle.i5 = shufflevector <64 x i32> %0, <64 x i32> poison, <64 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30, i32 32, i32 34, i32 36, i32 38, i32 40, i32 42, i32 44, i32 46, i32 48, i32 50, i32 52, i32 54, i32 56, i32 58, i32 60, i32 62, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>735 store <64 x i32> %shuffle.i5, ptr %out, align 4736 ret void737}738 739define void @vnsrl_0_i8_two_source(ptr %in0, ptr %in1, ptr %out) {740; V-LABEL: vnsrl_0_i8_two_source:741; V: # %bb.0: # %entry742; V-NEXT: vsetivli zero, 8, e8, mf4, ta, ma743; V-NEXT: vle8.v v8, (a1)744; V-NEXT: vle8.v v9, (a0)745; V-NEXT: vsetivli zero, 4, e8, mf8, ta, ma746; V-NEXT: vnsrl.wi v8, v8, 0747; V-NEXT: vnsrl.wi v9, v9, 0748; V-NEXT: vsetivli zero, 8, e8, mf4, ta, ma749; V-NEXT: vslideup.vi v9, v8, 4750; V-NEXT: vse8.v v9, (a2)751; V-NEXT: ret752;753; ZVE32F-LABEL: vnsrl_0_i8_two_source:754; ZVE32F: # %bb.0: # %entry755; ZVE32F-NEXT: vsetivli zero, 8, e8, mf4, ta, ma756; ZVE32F-NEXT: vle8.v v8, (a1)757; ZVE32F-NEXT: vle8.v v9, (a0)758; ZVE32F-NEXT: vsetivli zero, 4, e8, mf4, ta, ma759; ZVE32F-NEXT: vnsrl.wi v8, v8, 0760; ZVE32F-NEXT: vnsrl.wi v9, v9, 0761; ZVE32F-NEXT: vsetivli zero, 8, e8, mf4, ta, ma762; ZVE32F-NEXT: vslideup.vi v9, v8, 4763; ZVE32F-NEXT: vse8.v v9, (a2)764; ZVE32F-NEXT: ret765;766; ZIP-LABEL: vnsrl_0_i8_two_source:767; ZIP: # %bb.0: # %entry768; ZIP-NEXT: vsetivli zero, 8, e8, mf4, ta, ma769; ZIP-NEXT: vle8.v v8, (a1)770; ZIP-NEXT: vle8.v v9, (a0)771; ZIP-NEXT: vsetivli zero, 4, e8, mf8, ta, ma772; ZIP-NEXT: vnsrl.wi v8, v8, 0773; ZIP-NEXT: vnsrl.wi v9, v9, 0774; ZIP-NEXT: vsetivli zero, 8, e8, mf4, ta, ma775; ZIP-NEXT: vslideup.vi v9, v8, 4776; ZIP-NEXT: vse8.v v9, (a2)777; ZIP-NEXT: ret778entry:779 %0 = load <8 x i8>, ptr %in0, align 1780 %1 = load <8 x i8>, ptr %in1, align 1781 %shuffle.i5 = shufflevector <8 x i8> %0, <8 x i8> %1, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>782 store <8 x i8> %shuffle.i5, ptr %out, align 1783 ret void784}785 786define void @vnsrl_8_8_two_source(ptr %in0, ptr %in1, ptr %out) {787; V-LABEL: vnsrl_8_8_two_source:788; V: # %bb.0: # %entry789; V-NEXT: vsetivli zero, 8, e8, mf4, ta, ma790; V-NEXT: vle8.v v8, (a1)791; V-NEXT: vle8.v v9, (a0)792; V-NEXT: vsetivli zero, 4, e8, mf8, ta, ma793; V-NEXT: vnsrl.wi v8, v8, 8794; V-NEXT: vnsrl.wi v9, v9, 8795; V-NEXT: vsetivli zero, 8, e8, mf4, ta, ma796; V-NEXT: vslideup.vi v9, v8, 4797; V-NEXT: vse8.v v9, (a2)798; V-NEXT: ret799;800; ZVE32F-LABEL: vnsrl_8_8_two_source:801; ZVE32F: # %bb.0: # %entry802; ZVE32F-NEXT: vsetivli zero, 8, e8, mf4, ta, ma803; ZVE32F-NEXT: vle8.v v8, (a1)804; ZVE32F-NEXT: vle8.v v9, (a0)805; ZVE32F-NEXT: vsetivli zero, 4, e8, mf4, ta, ma806; ZVE32F-NEXT: vnsrl.wi v8, v8, 8807; ZVE32F-NEXT: vnsrl.wi v9, v9, 8808; ZVE32F-NEXT: vsetivli zero, 8, e8, mf4, ta, ma809; ZVE32F-NEXT: vslideup.vi v9, v8, 4810; ZVE32F-NEXT: vse8.v v9, (a2)811; ZVE32F-NEXT: ret812;813; ZIP-LABEL: vnsrl_8_8_two_source:814; ZIP: # %bb.0: # %entry815; ZIP-NEXT: vsetivli zero, 8, e8, mf4, ta, ma816; ZIP-NEXT: vle8.v v8, (a1)817; ZIP-NEXT: vle8.v v9, (a0)818; ZIP-NEXT: vsetivli zero, 4, e8, mf8, ta, ma819; ZIP-NEXT: vnsrl.wi v8, v8, 8820; ZIP-NEXT: vnsrl.wi v9, v9, 8821; ZIP-NEXT: vsetivli zero, 8, e8, mf4, ta, ma822; ZIP-NEXT: vslideup.vi v9, v8, 4823; ZIP-NEXT: vse8.v v9, (a2)824; ZIP-NEXT: ret825entry:826 %0 = load <8 x i8>, ptr %in0, align 1827 %1 = load <8 x i8>, ptr %in1, align 1828 %shuffle.i5 = shufflevector <8 x i8> %0, <8 x i8> %1, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>829 store <8 x i8> %shuffle.i5, ptr %out, align 1830 ret void831}832 833define void @vnsrl_0_i16_two_source(ptr %in0, ptr %in1, ptr %out) {834; V-LABEL: vnsrl_0_i16_two_source:835; V: # %bb.0: # %entry836; V-NEXT: vsetivli zero, 4, e16, mf4, ta, ma837; V-NEXT: vle16.v v8, (a1)838; V-NEXT: vle16.v v9, (a0)839; V-NEXT: vsetivli zero, 2, e16, mf4, ta, ma840; V-NEXT: vnsrl.wi v8, v8, 0841; V-NEXT: vnsrl.wi v9, v9, 0842; V-NEXT: vsetivli zero, 4, e16, mf4, ta, ma843; V-NEXT: vslideup.vi v9, v8, 2844; V-NEXT: vse16.v v9, (a2)845; V-NEXT: ret846;847; ZVE32F-LABEL: vnsrl_0_i16_two_source:848; ZVE32F: # %bb.0: # %entry849; ZVE32F-NEXT: vsetivli zero, 4, e16, mf2, ta, ma850; ZVE32F-NEXT: vle16.v v8, (a1)851; ZVE32F-NEXT: vle16.v v9, (a0)852; ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma853; ZVE32F-NEXT: vnsrl.wi v8, v8, 0854; ZVE32F-NEXT: vnsrl.wi v9, v9, 0855; ZVE32F-NEXT: vsetivli zero, 4, e16, mf2, ta, ma856; ZVE32F-NEXT: vslideup.vi v9, v8, 2857; ZVE32F-NEXT: vse16.v v9, (a2)858; ZVE32F-NEXT: ret859;860; ZIP-LABEL: vnsrl_0_i16_two_source:861; ZIP: # %bb.0: # %entry862; ZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma863; ZIP-NEXT: vle16.v v8, (a1)864; ZIP-NEXT: vle16.v v9, (a0)865; ZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma866; ZIP-NEXT: vnsrl.wi v8, v8, 0867; ZIP-NEXT: vnsrl.wi v9, v9, 0868; ZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma869; ZIP-NEXT: vslideup.vi v9, v8, 2870; ZIP-NEXT: vse16.v v9, (a2)871; ZIP-NEXT: ret872entry:873 %0 = load <4 x i16>, ptr %in0, align 2874 %1 = load <4 x i16>, ptr %in1, align 2875 %shuffle.i5 = shufflevector <4 x i16> %0, <4 x i16> %1, <4 x i32> <i32 0, i32 2, i32 4, i32 6>876 store <4 x i16> %shuffle.i5, ptr %out, align 2877 ret void878}879 880define void @vnsrl_16_i16_two_source(ptr %in0, ptr %in1, ptr %out) {881; V-LABEL: vnsrl_16_i16_two_source:882; V: # %bb.0: # %entry883; V-NEXT: vsetivli zero, 4, e16, mf4, ta, ma884; V-NEXT: vle16.v v8, (a1)885; V-NEXT: vle16.v v9, (a0)886; V-NEXT: vsetivli zero, 2, e16, mf4, ta, ma887; V-NEXT: vnsrl.wi v8, v8, 16888; V-NEXT: vnsrl.wi v9, v9, 16889; V-NEXT: vsetivli zero, 4, e16, mf4, ta, ma890; V-NEXT: vslideup.vi v9, v8, 2891; V-NEXT: vse16.v v9, (a2)892; V-NEXT: ret893;894; ZVE32F-LABEL: vnsrl_16_i16_two_source:895; ZVE32F: # %bb.0: # %entry896; ZVE32F-NEXT: vsetivli zero, 4, e16, mf2, ta, ma897; ZVE32F-NEXT: vle16.v v8, (a1)898; ZVE32F-NEXT: vle16.v v9, (a0)899; ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma900; ZVE32F-NEXT: vnsrl.wi v8, v8, 16901; ZVE32F-NEXT: vnsrl.wi v9, v9, 16902; ZVE32F-NEXT: vsetivli zero, 4, e16, mf2, ta, ma903; ZVE32F-NEXT: vslideup.vi v9, v8, 2904; ZVE32F-NEXT: vse16.v v9, (a2)905; ZVE32F-NEXT: ret906;907; ZIP-LABEL: vnsrl_16_i16_two_source:908; ZIP: # %bb.0: # %entry909; ZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma910; ZIP-NEXT: vle16.v v8, (a1)911; ZIP-NEXT: vle16.v v9, (a0)912; ZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma913; ZIP-NEXT: vnsrl.wi v8, v8, 16914; ZIP-NEXT: vnsrl.wi v9, v9, 16915; ZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma916; ZIP-NEXT: vslideup.vi v9, v8, 2917; ZIP-NEXT: vse16.v v9, (a2)918; ZIP-NEXT: ret919entry:920 %0 = load <4 x i16>, ptr %in0, align 2921 %1 = load <4 x i16>, ptr %in1, align 2922 %shuffle.i5 = shufflevector <4 x i16> %0, <4 x i16> %1, <4 x i32> <i32 1, i32 3, i32 5, i32 7>923 store <4 x i16> %shuffle.i5, ptr %out, align 2924 ret void925}926 927define void @vnsrl_0_half_two_source(ptr %in0, ptr %in1, ptr %out) {928; V-LABEL: vnsrl_0_half_two_source:929; V: # %bb.0: # %entry930; V-NEXT: vsetivli zero, 4, e16, mf4, ta, ma931; V-NEXT: vle16.v v8, (a1)932; V-NEXT: vle16.v v9, (a0)933; V-NEXT: vsetivli zero, 2, e16, mf4, ta, ma934; V-NEXT: vnsrl.wi v8, v8, 0935; V-NEXT: vnsrl.wi v9, v9, 0936; V-NEXT: vsetivli zero, 4, e16, mf4, ta, ma937; V-NEXT: vslideup.vi v9, v8, 2938; V-NEXT: vse16.v v9, (a2)939; V-NEXT: ret940;941; ZVE32F-LABEL: vnsrl_0_half_two_source:942; ZVE32F: # %bb.0: # %entry943; ZVE32F-NEXT: vsetivli zero, 4, e16, mf2, ta, ma944; ZVE32F-NEXT: vle16.v v8, (a1)945; ZVE32F-NEXT: vle16.v v9, (a0)946; ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma947; ZVE32F-NEXT: vnsrl.wi v8, v8, 0948; ZVE32F-NEXT: vnsrl.wi v9, v9, 0949; ZVE32F-NEXT: vsetivli zero, 4, e16, mf2, ta, ma950; ZVE32F-NEXT: vslideup.vi v9, v8, 2951; ZVE32F-NEXT: vse16.v v9, (a2)952; ZVE32F-NEXT: ret953;954; ZIP-LABEL: vnsrl_0_half_two_source:955; ZIP: # %bb.0: # %entry956; ZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma957; ZIP-NEXT: vle16.v v8, (a1)958; ZIP-NEXT: vle16.v v9, (a0)959; ZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma960; ZIP-NEXT: vnsrl.wi v8, v8, 0961; ZIP-NEXT: vnsrl.wi v9, v9, 0962; ZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma963; ZIP-NEXT: vslideup.vi v9, v8, 2964; ZIP-NEXT: vse16.v v9, (a2)965; ZIP-NEXT: ret966entry:967 %0 = load <4 x half>, ptr %in0, align 2968 %1 = load <4 x half>, ptr %in1, align 2969 %shuffle.i5 = shufflevector <4 x half> %0, <4 x half> %1, <4 x i32> <i32 0, i32 2, i32 4, i32 6>970 store <4 x half> %shuffle.i5, ptr %out, align 2971 ret void972}973 974define void @vnsrl_16_half_two_source(ptr %in0, ptr %in1, ptr %out) {975; V-LABEL: vnsrl_16_half_two_source:976; V: # %bb.0: # %entry977; V-NEXT: vsetivli zero, 4, e16, mf4, ta, ma978; V-NEXT: vle16.v v8, (a1)979; V-NEXT: vle16.v v9, (a0)980; V-NEXT: vsetivli zero, 2, e16, mf4, ta, ma981; V-NEXT: vnsrl.wi v8, v8, 16982; V-NEXT: vnsrl.wi v9, v9, 16983; V-NEXT: vsetivli zero, 4, e16, mf4, ta, ma984; V-NEXT: vslideup.vi v9, v8, 2985; V-NEXT: vse16.v v9, (a2)986; V-NEXT: ret987;988; ZVE32F-LABEL: vnsrl_16_half_two_source:989; ZVE32F: # %bb.0: # %entry990; ZVE32F-NEXT: vsetivli zero, 4, e16, mf2, ta, ma991; ZVE32F-NEXT: vle16.v v8, (a1)992; ZVE32F-NEXT: vle16.v v9, (a0)993; ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma994; ZVE32F-NEXT: vnsrl.wi v8, v8, 16995; ZVE32F-NEXT: vnsrl.wi v9, v9, 16996; ZVE32F-NEXT: vsetivli zero, 4, e16, mf2, ta, ma997; ZVE32F-NEXT: vslideup.vi v9, v8, 2998; ZVE32F-NEXT: vse16.v v9, (a2)999; ZVE32F-NEXT: ret1000;1001; ZIP-LABEL: vnsrl_16_half_two_source:1002; ZIP: # %bb.0: # %entry1003; ZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma1004; ZIP-NEXT: vle16.v v8, (a1)1005; ZIP-NEXT: vle16.v v9, (a0)1006; ZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma1007; ZIP-NEXT: vnsrl.wi v8, v8, 161008; ZIP-NEXT: vnsrl.wi v9, v9, 161009; ZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma1010; ZIP-NEXT: vslideup.vi v9, v8, 21011; ZIP-NEXT: vse16.v v9, (a2)1012; ZIP-NEXT: ret1013entry:1014 %0 = load <4 x half>, ptr %in0, align 21015 %1 = load <4 x half>, ptr %in1, align 21016 %shuffle.i5 = shufflevector <4 x half> %0, <4 x half> %1, <4 x i32> <i32 1, i32 3, i32 5, i32 7>1017 store <4 x half> %shuffle.i5, ptr %out, align 21018 ret void1019}1020 1021define void @vnsrl_0_i32_two_source(ptr %in0, ptr %in1, ptr %out) {1022; V-LABEL: vnsrl_0_i32_two_source:1023; V: # %bb.0: # %entry1024; V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma1025; V-NEXT: vle32.v v8, (a0)1026; V-NEXT: vle32.v v9, (a1)1027; V-NEXT: vslideup.vi v8, v9, 11028; V-NEXT: vse32.v v8, (a2)1029; V-NEXT: ret1030;1031; ZVE32F-LABEL: vnsrl_0_i32_two_source:1032; ZVE32F: # %bb.0: # %entry1033; ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma1034; ZVE32F-NEXT: vle32.v v8, (a0)1035; ZVE32F-NEXT: vle32.v v9, (a1)1036; ZVE32F-NEXT: vslideup.vi v8, v9, 11037; ZVE32F-NEXT: vse32.v v8, (a2)1038; ZVE32F-NEXT: ret1039;1040; ZIP-LABEL: vnsrl_0_i32_two_source:1041; ZIP: # %bb.0: # %entry1042; ZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma1043; ZIP-NEXT: vle32.v v8, (a0)1044; ZIP-NEXT: vle32.v v9, (a1)1045; ZIP-NEXT: vslideup.vi v8, v9, 11046; ZIP-NEXT: vse32.v v8, (a2)1047; ZIP-NEXT: ret1048entry:1049 %0 = load <2 x i32>, ptr %in0, align 41050 %1 = load <2 x i32>, ptr %in1, align 41051 %shuffle.i5 = shufflevector <2 x i32> %0, <2 x i32> %1, <2 x i32> <i32 0, i32 2>1052 store <2 x i32> %shuffle.i5, ptr %out, align 41053 ret void1054}1055 1056define void @vnsrl_32_i32_two_source(ptr %in0, ptr %in1, ptr %out) {1057; V-LABEL: vnsrl_32_i32_two_source:1058; V: # %bb.0: # %entry1059; V-NEXT: vsetivli zero, 2, e32, mf2, ta, mu1060; V-NEXT: vle32.v v8, (a0)1061; V-NEXT: vle32.v v9, (a1)1062; V-NEXT: vmv.v.i v0, 11063; V-NEXT: vslidedown.vi v9, v8, 1, v0.t1064; V-NEXT: vse32.v v9, (a2)1065; V-NEXT: ret1066;1067; ZVE32F-LABEL: vnsrl_32_i32_two_source:1068; ZVE32F: # %bb.0: # %entry1069; ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, mu1070; ZVE32F-NEXT: vle32.v v8, (a0)1071; ZVE32F-NEXT: vle32.v v9, (a1)1072; ZVE32F-NEXT: vmv.v.i v0, 11073; ZVE32F-NEXT: vslidedown.vi v9, v8, 1, v0.t1074; ZVE32F-NEXT: vse32.v v9, (a2)1075; ZVE32F-NEXT: ret1076;1077; ZIP-LABEL: vnsrl_32_i32_two_source:1078; ZIP: # %bb.0: # %entry1079; ZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma1080; ZIP-NEXT: vle32.v v8, (a0)1081; ZIP-NEXT: vle32.v v9, (a1)1082; ZIP-NEXT: ri.vzipodd.vv v10, v8, v91083; ZIP-NEXT: vse32.v v10, (a2)1084; ZIP-NEXT: ret1085entry:1086 %0 = load <2 x i32>, ptr %in0, align 41087 %1 = load <2 x i32>, ptr %in1, align 41088 %shuffle.i5 = shufflevector <2 x i32> %0, <2 x i32> %1, <2 x i32> <i32 1, i32 3>1089 store <2 x i32> %shuffle.i5, ptr %out, align 41090 ret void1091}1092 1093define void @vnsrl_0_float_two_source(ptr %in0, ptr %in1, ptr %out) {1094; V-LABEL: vnsrl_0_float_two_source:1095; V: # %bb.0: # %entry1096; V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma1097; V-NEXT: vle32.v v8, (a0)1098; V-NEXT: vle32.v v9, (a1)1099; V-NEXT: vslideup.vi v8, v9, 11100; V-NEXT: vse32.v v8, (a2)1101; V-NEXT: ret1102;1103; ZVE32F-LABEL: vnsrl_0_float_two_source:1104; ZVE32F: # %bb.0: # %entry1105; ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma1106; ZVE32F-NEXT: vle32.v v8, (a0)1107; ZVE32F-NEXT: vle32.v v9, (a1)1108; ZVE32F-NEXT: vslideup.vi v8, v9, 11109; ZVE32F-NEXT: vse32.v v8, (a2)1110; ZVE32F-NEXT: ret1111;1112; ZIP-LABEL: vnsrl_0_float_two_source:1113; ZIP: # %bb.0: # %entry1114; ZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma1115; ZIP-NEXT: vle32.v v8, (a0)1116; ZIP-NEXT: vle32.v v9, (a1)1117; ZIP-NEXT: vslideup.vi v8, v9, 11118; ZIP-NEXT: vse32.v v8, (a2)1119; ZIP-NEXT: ret1120entry:1121 %0 = load <2 x float>, ptr %in0, align 41122 %1 = load <2 x float>, ptr %in1, align 41123 %shuffle.i5 = shufflevector <2 x float> %0, <2 x float> %1, <2 x i32> <i32 0, i32 2>1124 store <2 x float> %shuffle.i5, ptr %out, align 41125 ret void1126}1127 1128define void @vnsrl_32_float_two_source(ptr %in0, ptr %in1, ptr %out) {1129; V-LABEL: vnsrl_32_float_two_source:1130; V: # %bb.0: # %entry1131; V-NEXT: vsetivli zero, 2, e32, mf2, ta, mu1132; V-NEXT: vle32.v v8, (a0)1133; V-NEXT: vle32.v v9, (a1)1134; V-NEXT: vmv.v.i v0, 11135; V-NEXT: vslidedown.vi v9, v8, 1, v0.t1136; V-NEXT: vse32.v v9, (a2)1137; V-NEXT: ret1138;1139; ZVE32F-LABEL: vnsrl_32_float_two_source:1140; ZVE32F: # %bb.0: # %entry1141; ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, mu1142; ZVE32F-NEXT: vle32.v v8, (a0)1143; ZVE32F-NEXT: vle32.v v9, (a1)1144; ZVE32F-NEXT: vmv.v.i v0, 11145; ZVE32F-NEXT: vslidedown.vi v9, v8, 1, v0.t1146; ZVE32F-NEXT: vse32.v v9, (a2)1147; ZVE32F-NEXT: ret1148;1149; ZIP-LABEL: vnsrl_32_float_two_source:1150; ZIP: # %bb.0: # %entry1151; ZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma1152; ZIP-NEXT: vle32.v v8, (a0)1153; ZIP-NEXT: vle32.v v9, (a1)1154; ZIP-NEXT: ri.vzipodd.vv v10, v8, v91155; ZIP-NEXT: vse32.v v10, (a2)1156; ZIP-NEXT: ret1157entry:1158 %0 = load <2 x float>, ptr %in0, align 41159 %1 = load <2 x float>, ptr %in1, align 41160 %shuffle.i5 = shufflevector <2 x float> %0, <2 x float> %1, <2 x i32> <i32 1, i32 3>1161 store <2 x float> %shuffle.i5, ptr %out, align 41162 ret void1163}1164 1165define void @vnsrl_0_i64_two_source(ptr %in0, ptr %in1, ptr %out) {1166; V-LABEL: vnsrl_0_i64_two_source:1167; V: # %bb.0: # %entry1168; V-NEXT: vsetivli zero, 2, e64, m1, ta, ma1169; V-NEXT: vle64.v v8, (a0)1170; V-NEXT: vle64.v v9, (a1)1171; V-NEXT: vslideup.vi v8, v9, 11172; V-NEXT: vse64.v v8, (a2)1173; V-NEXT: ret1174;1175; ZVE32F-LABEL: vnsrl_0_i64_two_source:1176; ZVE32F: # %bb.0: # %entry1177; ZVE32F-NEXT: vsetivli zero, 4, e32, m1, ta, ma1178; ZVE32F-NEXT: vle32.v v8, (a0)1179; ZVE32F-NEXT: vle32.v v9, (a1)1180; ZVE32F-NEXT: vslideup.vi v8, v9, 21181; ZVE32F-NEXT: vse32.v v8, (a2)1182; ZVE32F-NEXT: ret1183;1184; ZIP-LABEL: vnsrl_0_i64_two_source:1185; ZIP: # %bb.0: # %entry1186; ZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma1187; ZIP-NEXT: vle64.v v8, (a0)1188; ZIP-NEXT: vle64.v v9, (a1)1189; ZIP-NEXT: vslideup.vi v8, v9, 11190; ZIP-NEXT: vse64.v v8, (a2)1191; ZIP-NEXT: ret1192entry:1193 %0 = load <2 x i64>, ptr %in0, align 81194 %1 = load <2 x i64>, ptr %in1, align 81195 %shuffle.i5 = shufflevector <2 x i64> %0, <2 x i64> %1, <2 x i32> <i32 0, i32 2>1196 store <2 x i64> %shuffle.i5, ptr %out, align 81197 ret void1198}1199 1200define void @vnsrl_64_i64_two_source(ptr %in0, ptr %in1, ptr %out) {1201; V-LABEL: vnsrl_64_i64_two_source:1202; V: # %bb.0: # %entry1203; V-NEXT: vsetivli zero, 2, e64, m1, ta, mu1204; V-NEXT: vle64.v v8, (a0)1205; V-NEXT: vle64.v v9, (a1)1206; V-NEXT: vmv.v.i v0, 11207; V-NEXT: vslidedown.vi v9, v8, 1, v0.t1208; V-NEXT: vse64.v v9, (a2)1209; V-NEXT: ret1210;1211; ZVE32F-LABEL: vnsrl_64_i64_two_source:1212; ZVE32F: # %bb.0: # %entry1213; ZVE32F-NEXT: vsetivli zero, 4, e32, m1, ta, mu1214; ZVE32F-NEXT: vle32.v v8, (a0)1215; ZVE32F-NEXT: vle32.v v9, (a1)1216; ZVE32F-NEXT: vmv.v.i v0, 31217; ZVE32F-NEXT: vslidedown.vi v9, v8, 2, v0.t1218; ZVE32F-NEXT: vse32.v v9, (a2)1219; ZVE32F-NEXT: ret1220;1221; ZIP-LABEL: vnsrl_64_i64_two_source:1222; ZIP: # %bb.0: # %entry1223; ZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma1224; ZIP-NEXT: vle64.v v8, (a0)1225; ZIP-NEXT: vle64.v v9, (a1)1226; ZIP-NEXT: ri.vzipodd.vv v10, v8, v91227; ZIP-NEXT: vse64.v v10, (a2)1228; ZIP-NEXT: ret1229entry:1230 %0 = load <2 x i64>, ptr %in0, align 81231 %1 = load <2 x i64>, ptr %in1, align 81232 %shuffle.i5 = shufflevector <2 x i64> %0, <2 x i64> %1, <2 x i32> <i32 1, i32 3>1233 store <2 x i64> %shuffle.i5, ptr %out, align 81234 ret void1235}1236 1237define void @vnsrl_0_double_two_source(ptr %in0, ptr %in1, ptr %out) {1238; V-LABEL: vnsrl_0_double_two_source:1239; V: # %bb.0: # %entry1240; V-NEXT: vsetivli zero, 2, e64, m1, ta, ma1241; V-NEXT: vle64.v v8, (a0)1242; V-NEXT: vle64.v v9, (a1)1243; V-NEXT: vslideup.vi v8, v9, 11244; V-NEXT: vse64.v v8, (a2)1245; V-NEXT: ret1246;1247; ZVE32F-LABEL: vnsrl_0_double_two_source:1248; ZVE32F: # %bb.0: # %entry1249; ZVE32F-NEXT: ld a0, 0(a0)1250; ZVE32F-NEXT: ld a1, 0(a1)1251; ZVE32F-NEXT: sd a0, 0(a2)1252; ZVE32F-NEXT: sd a1, 8(a2)1253; ZVE32F-NEXT: ret1254;1255; ZIP-LABEL: vnsrl_0_double_two_source:1256; ZIP: # %bb.0: # %entry1257; ZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma1258; ZIP-NEXT: vle64.v v8, (a0)1259; ZIP-NEXT: vle64.v v9, (a1)1260; ZIP-NEXT: vslideup.vi v8, v9, 11261; ZIP-NEXT: vse64.v v8, (a2)1262; ZIP-NEXT: ret1263entry:1264 %0 = load <2 x double>, ptr %in0, align 81265 %1 = load <2 x double>, ptr %in1, align 81266 %shuffle.i5 = shufflevector <2 x double> %0, <2 x double> %1, <2 x i32> <i32 0, i32 2>1267 store <2 x double> %shuffle.i5, ptr %out, align 81268 ret void1269}1270 1271define void @vnsrl_64_double_two_source(ptr %in0, ptr %in1, ptr %out) {1272; V-LABEL: vnsrl_64_double_two_source:1273; V: # %bb.0: # %entry1274; V-NEXT: vsetivli zero, 2, e64, m1, ta, mu1275; V-NEXT: vle64.v v8, (a0)1276; V-NEXT: vle64.v v9, (a1)1277; V-NEXT: vmv.v.i v0, 11278; V-NEXT: vslidedown.vi v9, v8, 1, v0.t1279; V-NEXT: vse64.v v9, (a2)1280; V-NEXT: ret1281;1282; ZVE32F-LABEL: vnsrl_64_double_two_source:1283; ZVE32F: # %bb.0: # %entry1284; ZVE32F-NEXT: ld a0, 8(a0)1285; ZVE32F-NEXT: ld a1, 8(a1)1286; ZVE32F-NEXT: sd a0, 0(a2)1287; ZVE32F-NEXT: sd a1, 8(a2)1288; ZVE32F-NEXT: ret1289;1290; ZIP-LABEL: vnsrl_64_double_two_source:1291; ZIP: # %bb.0: # %entry1292; ZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma1293; ZIP-NEXT: vle64.v v8, (a0)1294; ZIP-NEXT: vle64.v v9, (a1)1295; ZIP-NEXT: ri.vzipodd.vv v10, v8, v91296; ZIP-NEXT: vse64.v v10, (a2)1297; ZIP-NEXT: ret1298entry:1299 %0 = load <2 x double>, ptr %in0, align 81300 %1 = load <2 x double>, ptr %in1, align 81301 %shuffle.i5 = shufflevector <2 x double> %0, <2 x double> %1, <2 x i32> <i32 1, i32 3>1302 store <2 x double> %shuffle.i5, ptr %out, align 81303 ret void1304}1305 1306define <2 x i64> @unzip2a_dual_v2i64(<2 x i64> %a, <2 x i64> %b) {1307; V-LABEL: unzip2a_dual_v2i64:1308; V: # %bb.0: # %entry1309; V-NEXT: vsetivli zero, 2, e64, m1, ta, ma1310; V-NEXT: vslideup.vi v8, v9, 11311; V-NEXT: ret1312;1313; ZVE32F-LABEL: unzip2a_dual_v2i64:1314; ZVE32F: # %bb.0: # %entry1315; ZVE32F-NEXT: mv a1, a21316; ZVE32F-NEXT: ret1317;1318; ZIP-LABEL: unzip2a_dual_v2i64:1319; ZIP: # %bb.0: # %entry1320; ZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma1321; ZIP-NEXT: vslideup.vi v8, v9, 11322; ZIP-NEXT: ret1323entry:1324 %c = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 0, i32 2>1325 ret <2 x i64> %c1326}1327 1328define <4 x i64> @unzip2a_dual_v4i64(<4 x i64> %a, <4 x i64> %b) {1329; V-LABEL: unzip2a_dual_v4i64:1330; V: # %bb.0: # %entry1331; V-NEXT: vsetivli zero, 4, e64, m1, ta, mu1332; V-NEXT: vmv.v.i v0, 81333; V-NEXT: vslideup.vi v10, v9, 21334; V-NEXT: vslideup.vi v10, v9, 1, v0.t1335; V-NEXT: vmv.v.i v0, 21336; V-NEXT: vslidedown.vi v8, v8, 1, v0.t1337; V-NEXT: vmv.v.i v0, 121338; V-NEXT: vmerge.vvm v8, v8, v10, v01339; V-NEXT: ret1340;1341; ZVE32F-LABEL: unzip2a_dual_v4i64:1342; ZVE32F: # %bb.0: # %entry1343; ZVE32F-NEXT: ld a3, 0(a1)1344; ZVE32F-NEXT: ld a1, 16(a1)1345; ZVE32F-NEXT: ld a4, 0(a2)1346; ZVE32F-NEXT: ld a2, 16(a2)1347; ZVE32F-NEXT: vsetivli zero, 8, e32, m1, ta, mu1348; ZVE32F-NEXT: vmv.v.i v0, 151349; ZVE32F-NEXT: srli a5, a1, 321350; ZVE32F-NEXT: srli a6, a3, 321351; ZVE32F-NEXT: srli a7, a2, 321352; ZVE32F-NEXT: srli t0, a4, 321353; ZVE32F-NEXT: vmv.v.x v8, a41354; ZVE32F-NEXT: vmv.v.x v9, a31355; ZVE32F-NEXT: vslide1down.vx v8, v8, t01356; ZVE32F-NEXT: vslide1down.vx v9, v9, a61357; ZVE32F-NEXT: vslide1down.vx v8, v8, a21358; ZVE32F-NEXT: vslide1down.vx v9, v9, a11359; ZVE32F-NEXT: vslide1down.vx v8, v8, a71360; ZVE32F-NEXT: vslide1down.vx v9, v9, a51361; ZVE32F-NEXT: vslidedown.vi v8, v9, 4, v0.t1362; ZVE32F-NEXT: vse32.v v8, (a0)1363; ZVE32F-NEXT: ret1364;1365; ZIP-LABEL: unzip2a_dual_v4i64:1366; ZIP: # %bb.0: # %entry1367; ZIP-NEXT: vsetivli zero, 4, e64, m1, ta, ma1368; ZIP-NEXT: ri.vunzip2a.vv v11, v9, v101369; ZIP-NEXT: ri.vunzip2a.vv v9, v8, v101370; ZIP-NEXT: vslideup.vi v9, v11, 21371; ZIP-NEXT: vmv.v.v v8, v91372; ZIP-NEXT: ret1373entry:1374 %c = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 6>1375 ret <4 x i64> %c1376}1377 1378define <16 x i64> @unzip2a_dual_v16i64(<16 x i64> %a, <16 x i64> %b) {1379; V-LABEL: unzip2a_dual_v16i64:1380; V: # %bb.0: # %entry1381; V-NEXT: vsetivli zero, 16, e16, m1, ta, ma1382; V-NEXT: vid.v v161383; V-NEXT: lui a0, 51384; V-NEXT: addi a0, a0, 13651385; V-NEXT: vmv.s.x v20, a01386; V-NEXT: li a0, -2561387; V-NEXT: vadd.vv v21, v16, v161388; V-NEXT: vsetvli zero, zero, e64, m4, ta, ma1389; V-NEXT: vcompress.vm v16, v8, v201390; V-NEXT: vmv.s.x v0, a01391; V-NEXT: vsetvli zero, zero, e16, m1, ta, ma1392; V-NEXT: vadd.vi v8, v21, -161393; V-NEXT: vsetvli zero, zero, e64, m4, ta, mu1394; V-NEXT: vrgatherei16.vv v16, v12, v8, v0.t1395; V-NEXT: vmv.v.v v8, v161396; V-NEXT: ret1397;1398; ZVE32F-LABEL: unzip2a_dual_v16i64:1399; ZVE32F: # %bb.0: # %entry1400; ZVE32F-NEXT: addi sp, sp, -2561401; ZVE32F-NEXT: .cfi_def_cfa_offset 2561402; ZVE32F-NEXT: sd ra, 248(sp) # 8-byte Folded Spill1403; ZVE32F-NEXT: sd s0, 240(sp) # 8-byte Folded Spill1404; ZVE32F-NEXT: sd s2, 232(sp) # 8-byte Folded Spill1405; ZVE32F-NEXT: sd s3, 224(sp) # 8-byte Folded Spill1406; ZVE32F-NEXT: sd s4, 216(sp) # 8-byte Folded Spill1407; ZVE32F-NEXT: .cfi_offset ra, -81408; ZVE32F-NEXT: .cfi_offset s0, -161409; ZVE32F-NEXT: .cfi_offset s2, -241410; ZVE32F-NEXT: .cfi_offset s3, -321411; ZVE32F-NEXT: .cfi_offset s4, -401412; ZVE32F-NEXT: addi s0, sp, 2561413; ZVE32F-NEXT: .cfi_def_cfa s0, 01414; ZVE32F-NEXT: andi sp, sp, -1281415; ZVE32F-NEXT: ld t5, 0(a1)1416; ZVE32F-NEXT: ld t2, 16(a1)1417; ZVE32F-NEXT: ld a4, 32(a1)1418; ZVE32F-NEXT: ld a3, 48(a1)1419; ZVE32F-NEXT: ld a6, 64(a1)1420; ZVE32F-NEXT: ld a5, 80(a1)1421; ZVE32F-NEXT: ld a7, 96(a1)1422; ZVE32F-NEXT: ld a1, 112(a1)1423; ZVE32F-NEXT: ld t1, 0(a2)1424; ZVE32F-NEXT: ld t0, 16(a2)1425; ZVE32F-NEXT: ld t4, 32(a2)1426; ZVE32F-NEXT: ld t3, 48(a2)1427; ZVE32F-NEXT: ld t6, 64(a2)1428; ZVE32F-NEXT: ld s2, 80(a2)1429; ZVE32F-NEXT: ld s3, 96(a2)1430; ZVE32F-NEXT: ld a2, 112(a2)1431; ZVE32F-NEXT: srli s4, t5, 321432; ZVE32F-NEXT: sw t5, 0(sp)1433; ZVE32F-NEXT: sw s4, 4(sp)1434; ZVE32F-NEXT: srli t5, t2, 321435; ZVE32F-NEXT: sw t2, 8(sp)1436; ZVE32F-NEXT: srli t2, s3, 321437; ZVE32F-NEXT: sw s3, 112(sp)1438; ZVE32F-NEXT: sw t2, 116(sp)1439; ZVE32F-NEXT: srli t2, a2, 321440; ZVE32F-NEXT: sw a2, 120(sp)1441; ZVE32F-NEXT: sw t2, 124(sp)1442; ZVE32F-NEXT: srli a2, t6, 321443; ZVE32F-NEXT: sw t6, 96(sp)1444; ZVE32F-NEXT: sw a2, 100(sp)1445; ZVE32F-NEXT: srli a2, s2, 321446; ZVE32F-NEXT: sw s2, 104(sp)1447; ZVE32F-NEXT: sw a2, 108(sp)1448; ZVE32F-NEXT: srli a2, t4, 321449; ZVE32F-NEXT: sw t4, 80(sp)1450; ZVE32F-NEXT: sw a2, 84(sp)1451; ZVE32F-NEXT: srli a2, t3, 321452; ZVE32F-NEXT: sw t3, 88(sp)1453; ZVE32F-NEXT: sw a2, 92(sp)1454; ZVE32F-NEXT: srli a2, t1, 321455; ZVE32F-NEXT: sw t1, 64(sp)1456; ZVE32F-NEXT: sw a2, 68(sp)1457; ZVE32F-NEXT: srli a2, t0, 321458; ZVE32F-NEXT: sw t0, 72(sp)1459; ZVE32F-NEXT: sw a2, 76(sp)1460; ZVE32F-NEXT: srli a2, a7, 321461; ZVE32F-NEXT: sw a7, 48(sp)1462; ZVE32F-NEXT: sw a2, 52(sp)1463; ZVE32F-NEXT: srli a2, a1, 321464; ZVE32F-NEXT: sw a1, 56(sp)1465; ZVE32F-NEXT: sw a2, 60(sp)1466; ZVE32F-NEXT: srli a1, a6, 321467; ZVE32F-NEXT: sw a6, 32(sp)1468; ZVE32F-NEXT: sw a1, 36(sp)1469; ZVE32F-NEXT: srli a1, a5, 321470; ZVE32F-NEXT: sw a5, 40(sp)1471; ZVE32F-NEXT: sw a1, 44(sp)1472; ZVE32F-NEXT: srli a1, a4, 321473; ZVE32F-NEXT: sw a4, 16(sp)1474; ZVE32F-NEXT: sw a1, 20(sp)1475; ZVE32F-NEXT: srli a1, a3, 321476; ZVE32F-NEXT: sw a3, 24(sp)1477; ZVE32F-NEXT: sw a1, 28(sp)1478; ZVE32F-NEXT: li a1, 321479; ZVE32F-NEXT: sw t5, 12(sp)1480; ZVE32F-NEXT: mv a2, sp1481; ZVE32F-NEXT: vsetvli zero, a1, e32, m4, ta, ma1482; ZVE32F-NEXT: vle32.v v8, (a2)1483; ZVE32F-NEXT: vse32.v v8, (a0)1484; ZVE32F-NEXT: addi sp, s0, -2561485; ZVE32F-NEXT: .cfi_def_cfa sp, 2561486; ZVE32F-NEXT: ld ra, 248(sp) # 8-byte Folded Reload1487; ZVE32F-NEXT: ld s0, 240(sp) # 8-byte Folded Reload1488; ZVE32F-NEXT: ld s2, 232(sp) # 8-byte Folded Reload1489; ZVE32F-NEXT: ld s3, 224(sp) # 8-byte Folded Reload1490; ZVE32F-NEXT: ld s4, 216(sp) # 8-byte Folded Reload1491; ZVE32F-NEXT: .cfi_restore ra1492; ZVE32F-NEXT: .cfi_restore s01493; ZVE32F-NEXT: .cfi_restore s21494; ZVE32F-NEXT: .cfi_restore s31495; ZVE32F-NEXT: .cfi_restore s41496; ZVE32F-NEXT: addi sp, sp, 2561497; ZVE32F-NEXT: .cfi_def_cfa_offset 01498; ZVE32F-NEXT: ret1499;1500; ZIP-LABEL: unzip2a_dual_v16i64:1501; ZIP: # %bb.0: # %entry1502; ZIP-NEXT: vsetivli zero, 8, e64, m2, ta, ma1503; ZIP-NEXT: ri.vunzip2a.vv v16, v12, v141504; ZIP-NEXT: ri.vunzip2a.vv v12, v8, v101505; ZIP-NEXT: vsetivli zero, 16, e64, m4, ta, ma1506; ZIP-NEXT: vslideup.vi v12, v16, 81507; ZIP-NEXT: vmv.v.v v8, v121508; ZIP-NEXT: ret1509entry:1510 %c = shufflevector <16 x i64> %a, <16 x i64> %b, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>1511 ret <16 x i64> %c1512}1513 1514define <4 x i64> @unzip2a_dual_v4i64_exact(<4 x i64> %a, <4 x i64> %b) vscale_range(4,4) {1515; V-LABEL: unzip2a_dual_v4i64_exact:1516; V: # %bb.0: # %entry1517; V-NEXT: vsetivli zero, 4, e64, m1, ta, mu1518; V-NEXT: vmv.v.i v0, 81519; V-NEXT: vslideup.vi v10, v9, 21520; V-NEXT: vslideup.vi v10, v9, 1, v0.t1521; V-NEXT: vmv.v.i v0, 21522; V-NEXT: vslidedown.vi v8, v8, 1, v0.t1523; V-NEXT: vmv.v.i v0, 121524; V-NEXT: vmerge.vvm v8, v8, v10, v01525; V-NEXT: ret1526;1527; ZVE32F-LABEL: unzip2a_dual_v4i64_exact:1528; ZVE32F: # %bb.0: # %entry1529; ZVE32F-NEXT: ld a3, 0(a1)1530; ZVE32F-NEXT: ld a1, 16(a1)1531; ZVE32F-NEXT: ld a4, 0(a2)1532; ZVE32F-NEXT: ld a2, 16(a2)1533; ZVE32F-NEXT: vsetivli zero, 8, e32, m1, ta, mu1534; ZVE32F-NEXT: vmv.v.i v0, 151535; ZVE32F-NEXT: srli a5, a1, 321536; ZVE32F-NEXT: srli a6, a3, 321537; ZVE32F-NEXT: srli a7, a2, 321538; ZVE32F-NEXT: srli t0, a4, 321539; ZVE32F-NEXT: vmv.v.x v8, a41540; ZVE32F-NEXT: vmv.v.x v9, a31541; ZVE32F-NEXT: vslide1down.vx v8, v8, t01542; ZVE32F-NEXT: vslide1down.vx v9, v9, a61543; ZVE32F-NEXT: vslide1down.vx v8, v8, a21544; ZVE32F-NEXT: vslide1down.vx v9, v9, a11545; ZVE32F-NEXT: vslide1down.vx v8, v8, a71546; ZVE32F-NEXT: vslide1down.vx v9, v9, a51547; ZVE32F-NEXT: vslidedown.vi v8, v9, 4, v0.t1548; ZVE32F-NEXT: vs1r.v v8, (a0)1549; ZVE32F-NEXT: ret1550;1551; ZIP-LABEL: unzip2a_dual_v4i64_exact:1552; ZIP: # %bb.0: # %entry1553; ZIP-NEXT: vsetivli zero, 4, e64, m1, ta, ma1554; ZIP-NEXT: ri.vunzip2a.vv v10, v8, v91555; ZIP-NEXT: vmv.v.v v8, v101556; ZIP-NEXT: ret1557entry:1558 %c = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 6>1559 ret <4 x i64> %c1560}1561 1562define <4 x i64> @unzip2a_dual_v4i64_exact_nf2(<4 x i64> %a, <4 x i64> %b) vscale_range(8,8) {1563; V-LABEL: unzip2a_dual_v4i64_exact_nf2:1564; V: # %bb.0: # %entry1565; V-NEXT: vsetivli zero, 4, e64, m1, ta, mu1566; V-NEXT: vmv.v.i v0, 81567; V-NEXT: vslideup.vi v10, v9, 21568; V-NEXT: vslideup.vi v10, v9, 1, v0.t1569; V-NEXT: vmv.v.i v0, 21570; V-NEXT: vslidedown.vi v8, v8, 1, v0.t1571; V-NEXT: vmv.v.i v0, 121572; V-NEXT: vmerge.vvm v8, v8, v10, v01573; V-NEXT: ret1574;1575; ZVE32F-LABEL: unzip2a_dual_v4i64_exact_nf2:1576; ZVE32F: # %bb.0: # %entry1577; ZVE32F-NEXT: ld a3, 0(a1)1578; ZVE32F-NEXT: ld a1, 16(a1)1579; ZVE32F-NEXT: ld a4, 0(a2)1580; ZVE32F-NEXT: ld a2, 16(a2)1581; ZVE32F-NEXT: vsetivli zero, 8, e32, m1, ta, mu1582; ZVE32F-NEXT: vmv.v.i v0, 151583; ZVE32F-NEXT: srli a5, a1, 321584; ZVE32F-NEXT: srli a6, a3, 321585; ZVE32F-NEXT: srli a7, a2, 321586; ZVE32F-NEXT: srli t0, a4, 321587; ZVE32F-NEXT: vmv.v.x v8, a41588; ZVE32F-NEXT: vmv.v.x v9, a31589; ZVE32F-NEXT: vslide1down.vx v8, v8, t01590; ZVE32F-NEXT: vslide1down.vx v9, v9, a61591; ZVE32F-NEXT: vslide1down.vx v8, v8, a21592; ZVE32F-NEXT: vslide1down.vx v9, v9, a11593; ZVE32F-NEXT: vslide1down.vx v8, v8, a71594; ZVE32F-NEXT: vslide1down.vx v9, v9, a51595; ZVE32F-NEXT: vslidedown.vi v8, v9, 4, v0.t1596; ZVE32F-NEXT: vse32.v v8, (a0)1597; ZVE32F-NEXT: ret1598;1599; ZIP-LABEL: unzip2a_dual_v4i64_exact_nf2:1600; ZIP: # %bb.0: # %entry1601; ZIP-NEXT: vsetivli zero, 8, e64, m1, ta, ma1602; ZIP-NEXT: vslideup.vi v8, v9, 41603; ZIP-NEXT: ri.vunzip2a.vv v9, v8, v101604; ZIP-NEXT: vmv.v.v v8, v91605; ZIP-NEXT: ret1606entry:1607 %c = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 6>1608 ret <4 x i64> %c1609}1610 1611define <16 x i64> @unzip2a_dual_v16i64_exact(<16 x i64> %a, <16 x i64> %b) vscale_range(4,4) {1612; V-LABEL: unzip2a_dual_v16i64_exact:1613; V: # %bb.0: # %entry1614; V-NEXT: vsetivli zero, 4, e64, m1, ta, mu1615; V-NEXT: vslideup.vi v19, v15, 21616; V-NEXT: vmv.v.i v16, 81617; V-NEXT: vmv.v.i v17, 21618; V-NEXT: vmv.v.i v18, 121619; V-NEXT: vmv.v.v v0, v161620; V-NEXT: vslideup.vi v19, v15, 1, v0.t1621; V-NEXT: vmv.v.v v0, v171622; V-NEXT: vslidedown.vi v14, v14, 1, v0.t1623; V-NEXT: vmv.v.v v0, v181624; V-NEXT: vmerge.vvm v15, v14, v19, v01625; V-NEXT: vslideup.vi v14, v13, 21626; V-NEXT: vmv.v.v v0, v161627; V-NEXT: vslideup.vi v14, v13, 1, v0.t1628; V-NEXT: vmv.v.v v0, v171629; V-NEXT: vslidedown.vi v12, v12, 1, v0.t1630; V-NEXT: vmv.v.v v0, v181631; V-NEXT: vmerge.vvm v14, v12, v14, v01632; V-NEXT: vslideup.vi v12, v11, 21633; V-NEXT: li a0, -2561634; V-NEXT: vmv.v.v v0, v161635; V-NEXT: vslideup.vi v12, v11, 1, v0.t1636; V-NEXT: vmv.v.v v0, v171637; V-NEXT: vslidedown.vi v10, v10, 1, v0.t1638; V-NEXT: vmv.v.v v0, v181639; V-NEXT: vmerge.vvm v13, v10, v12, v01640; V-NEXT: vslideup.vi v10, v9, 21641; V-NEXT: vmv.v.v v0, v161642; V-NEXT: vslideup.vi v10, v9, 1, v0.t1643; V-NEXT: vmv.v.v v0, v171644; V-NEXT: vslidedown.vi v8, v8, 1, v0.t1645; V-NEXT: vmv.v.v v0, v181646; V-NEXT: vmerge.vvm v12, v8, v10, v01647; V-NEXT: vmv.s.x v0, a01648; V-NEXT: vsetivli zero, 16, e64, m4, ta, ma1649; V-NEXT: vmerge.vvm v8, v12, v12, v01650; V-NEXT: ret1651;1652; ZVE32F-LABEL: unzip2a_dual_v16i64_exact:1653; ZVE32F: # %bb.0: # %entry1654; ZVE32F-NEXT: ld a5, 96(a2)1655; ZVE32F-NEXT: ld a7, 0(a1)1656; ZVE32F-NEXT: ld a4, 16(a1)1657; ZVE32F-NEXT: ld t0, 32(a1)1658; ZVE32F-NEXT: ld a3, 48(a1)1659; ZVE32F-NEXT: ld t1, 64(a1)1660; ZVE32F-NEXT: ld a6, 80(a1)1661; ZVE32F-NEXT: ld t2, 96(a1)1662; ZVE32F-NEXT: ld a1, 112(a1)1663; ZVE32F-NEXT: vsetivli zero, 8, e32, m1, ta, mu1664; ZVE32F-NEXT: vmv.v.x v8, a71665; ZVE32F-NEXT: srli a7, a7, 321666; ZVE32F-NEXT: vmv.v.x v9, t01667; ZVE32F-NEXT: srli t0, t0, 321668; ZVE32F-NEXT: vmv.v.x v10, t11669; ZVE32F-NEXT: srli t1, t1, 321670; ZVE32F-NEXT: vmv.v.x v11, t21671; ZVE32F-NEXT: srli t2, t2, 321672; ZVE32F-NEXT: vslide1down.vx v11, v11, t21673; ZVE32F-NEXT: vslide1down.vx v10, v10, t11674; ZVE32F-NEXT: vslide1down.vx v12, v9, t01675; ZVE32F-NEXT: vslide1down.vx v8, v8, a71676; ZVE32F-NEXT: ld t0, 0(a2)1677; ZVE32F-NEXT: ld t1, 16(a2)1678; ZVE32F-NEXT: ld t2, 32(a2)1679; ZVE32F-NEXT: ld a7, 48(a2)1680; ZVE32F-NEXT: vmv.v.x v9, t01681; ZVE32F-NEXT: srli t0, t0, 321682; ZVE32F-NEXT: vmv.v.x v13, t21683; ZVE32F-NEXT: srli t2, t2, 321684; ZVE32F-NEXT: vslide1down.vx v13, v13, t21685; ZVE32F-NEXT: vslide1down.vx v14, v9, t01686; ZVE32F-NEXT: ld t0, 64(a2)1687; ZVE32F-NEXT: ld t2, 112(a2)1688; ZVE32F-NEXT: vmv.v.x v9, a51689; ZVE32F-NEXT: srli a5, a5, 321690; ZVE32F-NEXT: vslide1down.vx v15, v9, a51691; ZVE32F-NEXT: ld a2, 80(a2)1692; ZVE32F-NEXT: vmv.v.x v9, t01693; ZVE32F-NEXT: srli a5, t0, 321694; ZVE32F-NEXT: vslide1down.vx v16, v9, a51695; ZVE32F-NEXT: vslide1down.vx v9, v11, a11696; ZVE32F-NEXT: srli a1, a1, 321697; ZVE32F-NEXT: vslide1down.vx v9, v9, a11698; ZVE32F-NEXT: vslide1down.vx v10, v10, a61699; ZVE32F-NEXT: srli a1, a6, 321700; ZVE32F-NEXT: vslide1down.vx v10, v10, a11701; ZVE32F-NEXT: vslide1down.vx v8, v8, a41702; ZVE32F-NEXT: srli a4, a4, 321703; ZVE32F-NEXT: vslide1down.vx v11, v8, a41704; ZVE32F-NEXT: vmv.v.i v0, 151705; ZVE32F-NEXT: vslide1down.vx v8, v14, t11706; ZVE32F-NEXT: srli a1, t1, 321707; ZVE32F-NEXT: vslide1down.vx v14, v8, a11708; ZVE32F-NEXT: vslidedown.vi v9, v10, 4, v0.t1709; ZVE32F-NEXT: vslide1down.vx v8, v12, a31710; ZVE32F-NEXT: srli a3, a3, 321711; ZVE32F-NEXT: vslide1down.vx v8, v8, a31712; ZVE32F-NEXT: vslidedown.vi v8, v11, 4, v0.t1713; ZVE32F-NEXT: vslide1down.vx v10, v13, a71714; ZVE32F-NEXT: srli a1, a7, 321715; ZVE32F-NEXT: vslide1down.vx v10, v10, a11716; ZVE32F-NEXT: vslidedown.vi v10, v14, 4, v0.t1717; ZVE32F-NEXT: vslide1down.vx v11, v15, t21718; ZVE32F-NEXT: srli a1, t2, 321719; ZVE32F-NEXT: vslide1down.vx v11, v11, a11720; ZVE32F-NEXT: vslide1down.vx v12, v16, a21721; ZVE32F-NEXT: srli a2, a2, 321722; ZVE32F-NEXT: vslide1down.vx v12, v12, a21723; ZVE32F-NEXT: vslidedown.vi v11, v12, 4, v0.t1724; ZVE32F-NEXT: vs4r.v v8, (a0)1725; ZVE32F-NEXT: ret1726;1727; ZIP-LABEL: unzip2a_dual_v16i64_exact:1728; ZIP: # %bb.0: # %entry1729; ZIP-NEXT: vsetivli zero, 16, e64, m4, ta, ma1730; ZIP-NEXT: ri.vunzip2a.vv v16, v8, v121731; ZIP-NEXT: vmv.v.v v8, v161732; ZIP-NEXT: ret1733entry:1734 %c = shufflevector <16 x i64> %a, <16 x i64> %b, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>1735 ret <16 x i64> %c1736}1737 1738define <4 x i64> @unzip2b_dual_v4i64(<4 x i64> %a, <4 x i64> %b) {1739; V-LABEL: unzip2b_dual_v4i64:1740; V: # %bb.0: # %entry1741; V-NEXT: vsetivli zero, 4, e64, m1, ta, mu1742; V-NEXT: vmv.v.i v0, 21743; V-NEXT: vslidedown.vi v10, v8, 11744; V-NEXT: vslidedown.vi v10, v8, 2, v0.t1745; V-NEXT: vmv.v.i v0, 41746; V-NEXT: vmv1r.v v8, v91747; V-NEXT: vslideup.vi v8, v9, 1, v0.t1748; V-NEXT: vmv.v.i v0, 121749; V-NEXT: vmerge.vvm v8, v10, v8, v01750; V-NEXT: ret1751;1752; ZVE32F-LABEL: unzip2b_dual_v4i64:1753; ZVE32F: # %bb.0: # %entry1754; ZVE32F-NEXT: ld a3, 8(a1)1755; ZVE32F-NEXT: ld a1, 24(a1)1756; ZVE32F-NEXT: ld a4, 8(a2)1757; ZVE32F-NEXT: ld a2, 24(a2)1758; ZVE32F-NEXT: vsetivli zero, 8, e32, m1, ta, mu1759; ZVE32F-NEXT: vmv.v.i v0, 151760; ZVE32F-NEXT: srli a5, a1, 321761; ZVE32F-NEXT: srli a6, a3, 321762; ZVE32F-NEXT: srli a7, a2, 321763; ZVE32F-NEXT: srli t0, a4, 321764; ZVE32F-NEXT: vmv.v.x v8, a41765; ZVE32F-NEXT: vmv.v.x v9, a31766; ZVE32F-NEXT: vslide1down.vx v8, v8, t01767; ZVE32F-NEXT: vslide1down.vx v9, v9, a61768; ZVE32F-NEXT: vslide1down.vx v8, v8, a21769; ZVE32F-NEXT: vslide1down.vx v9, v9, a11770; ZVE32F-NEXT: vslide1down.vx v8, v8, a71771; ZVE32F-NEXT: vslide1down.vx v9, v9, a51772; ZVE32F-NEXT: vslidedown.vi v8, v9, 4, v0.t1773; ZVE32F-NEXT: vse32.v v8, (a0)1774; ZVE32F-NEXT: ret1775;1776; ZIP-LABEL: unzip2b_dual_v4i64:1777; ZIP: # %bb.0: # %entry1778; ZIP-NEXT: vsetivli zero, 4, e64, m1, ta, ma1779; ZIP-NEXT: ri.vunzip2b.vv v11, v9, v101780; ZIP-NEXT: ri.vunzip2b.vv v9, v8, v101781; ZIP-NEXT: vslideup.vi v9, v11, 21782; ZIP-NEXT: vmv.v.v v8, v91783; ZIP-NEXT: ret1784entry:1785 %c = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 1, i32 3, i32 5, i32 7>1786 ret <4 x i64> %c1787}1788 1789define <4 x i64> @unzip2b_dual_v4i64_exact(<4 x i64> %a, <4 x i64> %b) vscale_range(4,4) {1790; V-LABEL: unzip2b_dual_v4i64_exact:1791; V: # %bb.0: # %entry1792; V-NEXT: vsetivli zero, 4, e64, m1, ta, mu1793; V-NEXT: vmv.v.i v0, 21794; V-NEXT: vslidedown.vi v10, v8, 11795; V-NEXT: vslidedown.vi v10, v8, 2, v0.t1796; V-NEXT: vmv.v.i v0, 41797; V-NEXT: vmv1r.v v8, v91798; V-NEXT: vslideup.vi v8, v9, 1, v0.t1799; V-NEXT: vmv.v.i v0, 121800; V-NEXT: vmerge.vvm v8, v10, v8, v01801; V-NEXT: ret1802;1803; ZVE32F-LABEL: unzip2b_dual_v4i64_exact:1804; ZVE32F: # %bb.0: # %entry1805; ZVE32F-NEXT: ld a3, 8(a1)1806; ZVE32F-NEXT: ld a1, 24(a1)1807; ZVE32F-NEXT: ld a4, 8(a2)1808; ZVE32F-NEXT: ld a2, 24(a2)1809; ZVE32F-NEXT: vsetivli zero, 8, e32, m1, ta, mu1810; ZVE32F-NEXT: vmv.v.i v0, 151811; ZVE32F-NEXT: srli a5, a1, 321812; ZVE32F-NEXT: srli a6, a3, 321813; ZVE32F-NEXT: srli a7, a2, 321814; ZVE32F-NEXT: srli t0, a4, 321815; ZVE32F-NEXT: vmv.v.x v8, a41816; ZVE32F-NEXT: vmv.v.x v9, a31817; ZVE32F-NEXT: vslide1down.vx v8, v8, t01818; ZVE32F-NEXT: vslide1down.vx v9, v9, a61819; ZVE32F-NEXT: vslide1down.vx v8, v8, a21820; ZVE32F-NEXT: vslide1down.vx v9, v9, a11821; ZVE32F-NEXT: vslide1down.vx v8, v8, a71822; ZVE32F-NEXT: vslide1down.vx v9, v9, a51823; ZVE32F-NEXT: vslidedown.vi v8, v9, 4, v0.t1824; ZVE32F-NEXT: vs1r.v v8, (a0)1825; ZVE32F-NEXT: ret1826;1827; ZIP-LABEL: unzip2b_dual_v4i64_exact:1828; ZIP: # %bb.0: # %entry1829; ZIP-NEXT: vsetivli zero, 4, e64, m1, ta, ma1830; ZIP-NEXT: ri.vunzip2b.vv v10, v8, v91831; ZIP-NEXT: vmv.v.v v8, v101832; ZIP-NEXT: ret1833entry:1834 %c = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 1, i32 3, i32 5, i32 7>1835 ret <4 x i64> %c1836}1837