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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV323; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV644 5define <4 x i64> @m2_splat_0(<4 x i64> %v1) vscale_range(2,2) {6; CHECK-LABEL: m2_splat_0:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma9; CHECK-NEXT: vrgather.vi v10, v8, 010; CHECK-NEXT: vmv.v.v v8, v1011; CHECK-NEXT: ret12 %res = shufflevector <4 x i64> %v1, <4 x i64> poison, <4 x i32> <i32 0, i32 0, i32 0, i32 0>13 ret <4 x i64> %res14}15 16define <4 x i64> @m2_splat_in_chunks(<4 x i64> %v1) vscale_range(2,2) {17; CHECK-LABEL: m2_splat_in_chunks:18; CHECK: # %bb.0:19; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma20; CHECK-NEXT: vrgather.vi v10, v8, 021; CHECK-NEXT: vrgather.vi v11, v9, 022; CHECK-NEXT: vmv2r.v v8, v1023; CHECK-NEXT: ret24 %res = shufflevector <4 x i64> %v1, <4 x i64> poison, <4 x i32> <i32 0, i32 0, i32 2, i32 2>25 ret <4 x i64> %res26}27 28define <8 x i64> @m4_splat_in_chunks(<8 x i64> %v1) vscale_range(2,2) {29; CHECK-LABEL: m4_splat_in_chunks:30; CHECK: # %bb.0:31; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma32; CHECK-NEXT: vrgather.vi v12, v8, 033; CHECK-NEXT: vrgather.vi v13, v9, 034; CHECK-NEXT: vrgather.vi v14, v10, 035; CHECK-NEXT: vrgather.vi v15, v11, 136; CHECK-NEXT: vmv4r.v v8, v1237; CHECK-NEXT: ret38 %res = shufflevector <8 x i64> %v1, <8 x i64> poison, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 7, i32 7>39 ret <8 x i64> %res40}41 42 43define <4 x i64> @m2_splat_with_tail(<4 x i64> %v1) vscale_range(2,2) {44; CHECK-LABEL: m2_splat_with_tail:45; CHECK: # %bb.0:46; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma47; CHECK-NEXT: vrgather.vi v10, v8, 048; CHECK-NEXT: vmv1r.v v11, v949; CHECK-NEXT: vmv2r.v v8, v1050; CHECK-NEXT: ret51 %res = shufflevector <4 x i64> %v1, <4 x i64> poison, <4 x i32> <i32 0, i32 0, i32 2, i32 3>52 ret <4 x i64> %res53}54 55define <4 x i64> @m2_pair_swap_vl4(<4 x i64> %v1) vscale_range(2,2) {56; CHECK-LABEL: m2_pair_swap_vl4:57; CHECK: # %bb.0:58; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma59; CHECK-NEXT: vslidedown.vi v11, v9, 160; CHECK-NEXT: vslideup.vi v11, v9, 161; CHECK-NEXT: vslidedown.vi v10, v8, 162; CHECK-NEXT: vslideup.vi v10, v8, 163; CHECK-NEXT: vmv2r.v v8, v1064; CHECK-NEXT: ret65 %res = shufflevector <4 x i64> %v1, <4 x i64> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>66 ret <4 x i64> %res67}68 69define <8 x i32> @m2_pair_swap_vl8(<8 x i32> %v1) vscale_range(2,2) {70; RV32-LABEL: m2_pair_swap_vl8:71; RV32: # %bb.0:72; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma73; RV32-NEXT: vmv.v.i v12, 074; RV32-NEXT: li a0, 3275; RV32-NEXT: li a1, 6376; RV32-NEXT: vwsubu.vx v10, v12, a077; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, ma78; RV32-NEXT: vmv.v.x v12, a079; RV32-NEXT: vand.vx v10, v10, a180; RV32-NEXT: vand.vx v12, v12, a181; RV32-NEXT: vsrl.vv v10, v8, v1082; RV32-NEXT: vsll.vv v8, v8, v1283; RV32-NEXT: vor.vv v8, v8, v1084; RV32-NEXT: ret85;86; RV64-LABEL: m2_pair_swap_vl8:87; RV64: # %bb.0:88; RV64-NEXT: li a0, 3289; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma90; RV64-NEXT: vsrl.vx v10, v8, a091; RV64-NEXT: vsll.vx v8, v8, a092; RV64-NEXT: vor.vv v8, v8, v1093; RV64-NEXT: ret94 %res = shufflevector <8 x i32> %v1, <8 x i32> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>95 ret <8 x i32> %res96}97 98define <4 x i64> @m2_splat_into_identity(<4 x i64> %v1) vscale_range(2,2) {99; CHECK-LABEL: m2_splat_into_identity:100; CHECK: # %bb.0:101; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma102; CHECK-NEXT: vrgather.vi v10, v8, 0103; CHECK-NEXT: vmv1r.v v11, v9104; CHECK-NEXT: vmv2r.v v8, v10105; CHECK-NEXT: ret106 %res = shufflevector <4 x i64> %v1, <4 x i64> poison, <4 x i32> <i32 0, i32 0, i32 2, i32 3>107 ret <4 x i64> %res108}109 110define <4 x i64> @m2_broadcast_i128(<4 x i64> %v1) vscale_range(2,2) {111; CHECK-LABEL: m2_broadcast_i128:112; CHECK: # %bb.0:113; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma114; CHECK-NEXT: vmv1r.v v9, v8115; CHECK-NEXT: ret116 %res = shufflevector <4 x i64> %v1, <4 x i64> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 1>117 ret <4 x i64> %res118}119 120define <8 x i64> @m4_broadcast_i128(<8 x i64> %v1) vscale_range(2,2) {121; CHECK-LABEL: m4_broadcast_i128:122; CHECK: # %bb.0:123; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma124; CHECK-NEXT: vmv1r.v v9, v8125; CHECK-NEXT: vmv1r.v v10, v8126; CHECK-NEXT: vmv1r.v v11, v8127; CHECK-NEXT: ret128 %res = shufflevector <8 x i64> %v1, <8 x i64> poison, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1>129 ret <8 x i64> %res130}131 132 133define <4 x i64> @m2_splat_two_source(<4 x i64> %v1, <4 x i64> %v2) vscale_range(2,2) {134; CHECK-LABEL: m2_splat_two_source:135; CHECK: # %bb.0:136; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma137; CHECK-NEXT: vrgather.vi v12, v8, 0138; CHECK-NEXT: vrgather.vi v13, v11, 1139; CHECK-NEXT: vmv2r.v v8, v12140; CHECK-NEXT: ret141 %res = shufflevector <4 x i64> %v1, <4 x i64> %v2, <4 x i32> <i32 0, i32 0, i32 7, i32 7>142 ret <4 x i64> %res143}144 145define <4 x i64> @m2_splat_into_identity_two_source_v2_hi(<4 x i64> %v1, <4 x i64> %v2) vscale_range(2,2) {146; CHECK-LABEL: m2_splat_into_identity_two_source_v2_hi:147; CHECK: # %bb.0:148; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma149; CHECK-NEXT: vrgather.vi v10, v8, 0150; CHECK-NEXT: vmv2r.v v8, v10151; CHECK-NEXT: ret152 %res = shufflevector <4 x i64> %v1, <4 x i64> %v2, <4 x i32> <i32 0, i32 0, i32 6, i32 7>153 ret <4 x i64> %res154}155 156define <4 x i64> @m2_splat_into_slide_two_source_v2_lo(<4 x i64> %v1, <4 x i64> %v2) vscale_range(2,2) {157; CHECK-LABEL: m2_splat_into_slide_two_source_v2_lo:158; CHECK: # %bb.0:159; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma160; CHECK-NEXT: vrgather.vi v12, v8, 0161; CHECK-NEXT: vmv1r.v v13, v10162; CHECK-NEXT: vmv2r.v v8, v12163; CHECK-NEXT: ret164 %res = shufflevector <4 x i64> %v1, <4 x i64> %v2, <4 x i32> <i32 0, i32 0, i32 4, i32 5>165 ret <4 x i64> %res166}167 168define <4 x i64> @m2_splat_into_slide_two_source(<4 x i64> %v1, <4 x i64> %v2) vscale_range(2,2) {169; CHECK-LABEL: m2_splat_into_slide_two_source:170; CHECK: # %bb.0:171; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma172; CHECK-NEXT: vslidedown.vi v13, v10, 1173; CHECK-NEXT: vslideup.vi v13, v11, 1174; CHECK-NEXT: vrgather.vi v12, v8, 0175; CHECK-NEXT: vmv2r.v v8, v12176; CHECK-NEXT: ret177 %res = shufflevector <4 x i64> %v1, <4 x i64> %v2, <4 x i32> <i32 0, i32 0, i32 5, i32 6>178 ret <4 x i64> %res179}180 181define void @shuffle1(ptr %explicit_0, ptr %explicit_1) vscale_range(2,2) {182; CHECK-LABEL: shuffle1:183; CHECK: # %bb.0:184; CHECK-NEXT: addi a0, a0, 252185; CHECK-NEXT: vsetivli zero, 12, e8, m1, ta, ma186; CHECK-NEXT: vle8.v v10, (a0)187; CHECK-NEXT: vmv.v.i v0, 1188; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu189; CHECK-NEXT: vslidedown.vi v10, v10, 1, v0.t190; CHECK-NEXT: vmv.v.i v0, 5191; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma192; CHECK-NEXT: vmv.v.i v8, 0193; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma194; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0195; CHECK-NEXT: addi a0, a1, 672196; CHECK-NEXT: vs2r.v v8, (a0)197; CHECK-NEXT: ret198 %1 = getelementptr i32, ptr %explicit_0, i64 63199 %2 = load <3 x i32>, ptr %1, align 1200 %3 = shufflevector <3 x i32> %2, <3 x i32> poison, <2 x i32> <i32 1, i32 2>201 %4 = shufflevector <2 x i32> %3, <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>202 %5 = shufflevector <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 poison, i32 0, i32 poison, i32 0>, <8 x i32> %4, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 5, i32 9, i32 7>203 %6 = getelementptr inbounds <8 x i32>, ptr %explicit_1, i64 21204 store <8 x i32> %5, ptr %6, align 32205 ret void206}207 208define <16 x float> @shuffle2(<4 x float> %a) vscale_range(2,2) {209; CHECK-LABEL: shuffle2:210; CHECK: # %bb.0:211; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma212; CHECK-NEXT: vslidedown.vi v12, v8, 1213; CHECK-NEXT: vmv.v.i v0, 6214; CHECK-NEXT: vslideup.vi v12, v8, 2215; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma216; CHECK-NEXT: vmv.v.i v8, 0217; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma218; CHECK-NEXT: vmerge.vvm v9, v9, v12, v0219; CHECK-NEXT: ret220 %b = extractelement <4 x float> %a, i32 2221 %c = insertelement <16 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float poison, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float %b, i32 5222 %b1 = extractelement <4 x float> %a, i32 0223 %c1 = insertelement <16 x float> %c, float %b1, i32 6224 ret <16 x float>%c1225}226 227define i64 @extract_any_extend_vector_inreg_v16i64(<16 x i64> %a0, i32 %a1) vscale_range(2,2) {228; RV32-LABEL: extract_any_extend_vector_inreg_v16i64:229; RV32: # %bb.0:230; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma231; RV32-NEXT: vmv.v.i v16, 0232; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu233; RV32-NEXT: vmv.v.i v0, 1234; RV32-NEXT: li a1, 32235; RV32-NEXT: vslidedown.vi v18, v15, 1, v0.t236; RV32-NEXT: vsetivli zero, 1, e64, m8, ta, ma237; RV32-NEXT: vslidedown.vx v8, v16, a0238; RV32-NEXT: vmv.x.s a0, v8239; RV32-NEXT: vsrl.vx v8, v8, a1240; RV32-NEXT: vmv.x.s a1, v8241; RV32-NEXT: ret242;243; RV64-LABEL: extract_any_extend_vector_inreg_v16i64:244; RV64: # %bb.0:245; RV64-NEXT: addi sp, sp, -256246; RV64-NEXT: .cfi_def_cfa_offset 256247; RV64-NEXT: sd ra, 248(sp) # 8-byte Folded Spill248; RV64-NEXT: sd s0, 240(sp) # 8-byte Folded Spill249; RV64-NEXT: sd s2, 232(sp) # 8-byte Folded Spill250; RV64-NEXT: .cfi_offset ra, -8251; RV64-NEXT: .cfi_offset s0, -16252; RV64-NEXT: .cfi_offset s2, -24253; RV64-NEXT: addi s0, sp, 256254; RV64-NEXT: .cfi_def_cfa s0, 0255; RV64-NEXT: andi sp, sp, -128256; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, ma257; RV64-NEXT: vmv.v.i v0, 1258; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma259; RV64-NEXT: vmv.v.i v16, 0260; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu261; RV64-NEXT: vslidedown.vi v18, v15, 1, v0.t262; RV64-NEXT: mv s2, sp263; RV64-NEXT: vs8r.v v16, (s2)264; RV64-NEXT: andi a0, a0, 15265; RV64-NEXT: li a1, 8266; RV64-NEXT: call __muldi3267; RV64-NEXT: add a0, s2, a0268; RV64-NEXT: ld a0, 0(a0)269; RV64-NEXT: addi sp, s0, -256270; RV64-NEXT: .cfi_def_cfa sp, 256271; RV64-NEXT: ld ra, 248(sp) # 8-byte Folded Reload272; RV64-NEXT: ld s0, 240(sp) # 8-byte Folded Reload273; RV64-NEXT: ld s2, 232(sp) # 8-byte Folded Reload274; RV64-NEXT: .cfi_restore ra275; RV64-NEXT: .cfi_restore s0276; RV64-NEXT: .cfi_restore s2277; RV64-NEXT: addi sp, sp, 256278; RV64-NEXT: .cfi_def_cfa_offset 0279; RV64-NEXT: ret280 %1 = extractelement <16 x i64> %a0, i32 15281 %2 = insertelement <16 x i64> zeroinitializer, i64 %1, i32 4282 %3 = extractelement <16 x i64> %2, i32 %a1283 ret i64 %3284}285 286define <4 x double> @shuffles_add(<4 x double> %0, <4 x double> %1) vscale_range(2,2) {287; CHECK-LABEL: shuffles_add:288; CHECK: # %bb.0:289; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu290; CHECK-NEXT: vmv1r.v v13, v10291; CHECK-NEXT: vmv.v.i v0, 1292; CHECK-NEXT: vslideup.vi v13, v11, 1293; CHECK-NEXT: vslidedown.vi v11, v10, 1, v0.t294; CHECK-NEXT: vmv1r.v v10, v9295; CHECK-NEXT: vrgather.vi v12, v9, 0296; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma297; CHECK-NEXT: vfadd.vv v8, v12, v10298; CHECK-NEXT: ret299 %3 = shufflevector <4 x double> %0, <4 x double> %1, <4 x i32> <i32 poison, i32 2, i32 4, i32 6>300 %4 = shufflevector <4 x double> %0, <4 x double> %1, <4 x i32> <i32 poison, i32 3, i32 5, i32 7>301 %5 = fadd <4 x double> %3, %4302 ret <4 x double> %5303}304 305define <16 x i32> @m4_square_num_of_shuffles_in_chunks(<16 x i32> %0) vscale_range(2,2) {306; CHECK-LABEL: m4_square_num_of_shuffles_in_chunks:307; CHECK: # %bb.0: # %entry308; CHECK-NEXT: lui a0, %hi(.LCPI17_0)309; CHECK-NEXT: addi a0, a0, %lo(.LCPI17_0)310; CHECK-NEXT: vl1r.v v12, (a0)311; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma312; CHECK-NEXT: vsext.vf2 v16, v12313; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma314; CHECK-NEXT: vrgatherei16.vv v12, v8, v16315; CHECK-NEXT: vmv.v.v v8, v12316; CHECK-NEXT: ret317entry:318 %1 = shufflevector <16 x i32> %0, <16 x i32> poison, <16 x i32> <i32 0, i32 5, i32 8, i32 12, i32 1, i32 4, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15>319 ret <16 x i32> %1320}321 322define <16 x i32> @m4_linear_num_of_shuffles_in_chunks(<16 x i32> %0) vscale_range(2,2) {323; CHECK-LABEL: m4_linear_num_of_shuffles_in_chunks:324; CHECK: # %bb.0: # %entry325; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma326; CHECK-NEXT: vslideup.vi v12, v10, 2327; CHECK-NEXT: vslideup.vi v12, v11, 3328; CHECK-NEXT: vrgather.vi v14, v8, 2329; CHECK-NEXT: vrgather.vi v15, v10, 3330; CHECK-NEXT: vmv4r.v v8, v12331; CHECK-NEXT: ret332entry:333 %1 = shufflevector <16 x i32> %0, <16 x i32> poison, <16 x i32> <i32 poison, i32 poison, i32 8, i32 12, i32 poison, i32 poison, i32 poison, i32 poison, i32 2, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 11, i32 poison>334 ret <16 x i32> %1335}336 337define i64 @multi_chunks_shuffle(<32 x i32> %0) vscale_range(8,8) {338; RV32-LABEL: multi_chunks_shuffle:339; RV32: # %bb.0: # %entry340; RV32-NEXT: vsetivli zero, 16, e32, m1, ta, ma341; RV32-NEXT: vmv.v.i v12, 0342; RV32-NEXT: li a0, 32343; RV32-NEXT: li a1, 63344; RV32-NEXT: vwsubu.vx v10, v12, a0345; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, ma346; RV32-NEXT: vmv.v.x v12, a0347; RV32-NEXT: lui a0, 61681348; RV32-NEXT: addi a0, a0, -241349; RV32-NEXT: vand.vx v10, v10, a1350; RV32-NEXT: vand.vx v12, v12, a1351; RV32-NEXT: vsrl.vv v10, v8, v10352; RV32-NEXT: vsll.vv v8, v8, v12353; RV32-NEXT: vmv.s.x v0, a0354; RV32-NEXT: vor.vv v8, v8, v10355; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma356; RV32-NEXT: vmv.v.i v10, 0357; RV32-NEXT: vmerge.vvm v8, v10, v8, v0358; RV32-NEXT: vrgather.vi v10, v8, 2359; RV32-NEXT: vor.vv v8, v8, v10360; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma361; RV32-NEXT: vslidedown.vi v8, v8, 1362; RV32-NEXT: vmv.x.s a0, v8363; RV32-NEXT: srai a1, a0, 31364; RV32-NEXT: ret365;366; RV64-LABEL: multi_chunks_shuffle:367; RV64: # %bb.0: # %entry368; RV64-NEXT: li a0, 32369; RV64-NEXT: vsetivli zero, 16, e64, m2, ta, ma370; RV64-NEXT: vsrl.vx v10, v8, a0371; RV64-NEXT: vsll.vx v8, v8, a0372; RV64-NEXT: lui a0, 61681373; RV64-NEXT: addi a0, a0, -241374; RV64-NEXT: vor.vv v8, v8, v10375; RV64-NEXT: vmv.s.x v0, a0376; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma377; RV64-NEXT: vmv.v.i v10, 0378; RV64-NEXT: vmerge.vvm v8, v10, v8, v0379; RV64-NEXT: vrgather.vi v10, v8, 2380; RV64-NEXT: vor.vv v8, v8, v10381; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma382; RV64-NEXT: vslidedown.vi v8, v8, 1383; RV64-NEXT: vmv.x.s a0, v8384; RV64-NEXT: ret385entry:386 %1 = shufflevector <32 x i32> %0, <32 x i32> zeroinitializer, <32 x i32> <i32 1, i32 0, i32 3, i32 2, i32 37, i32 36, i32 39, i32 38, i32 9, i32 8, i32 11, i32 10, i32 45, i32 44, i32 47, i32 46, i32 17, i32 16, i32 19, i32 18, i32 53, i32 52, i32 55, i32 54, i32 25, i32 24, i32 27, i32 26, i32 61, i32 60, i32 63, i32 62>387 %2 = shufflevector <32 x i32> zeroinitializer, <32 x i32> %1, <32 x i32> <i32 3, i32 34, i32 33, i32 0, i32 7, i32 38, i32 37, i32 4, i32 11, i32 42, i32 41, i32 8, i32 15, i32 46, i32 45, i32 12, i32 19, i32 50, i32 49, i32 16, i32 23, i32 54, i32 53, i32 20, i32 27, i32 58, i32 57, i32 24, i32 31, i32 62, i32 61, i32 28>388 %3 = or <32 x i32> %1, %2389 %4 = extractelement <32 x i32> %3, i64 1390 %conv199 = sext i32 %4 to i64391 ret i64 %conv199392}393 394define void @shuffle_i128_ldst(ptr %p) vscale_range(2,2) {395; CHECK-LABEL: shuffle_i128_ldst:396; CHECK: # %bb.0:397; CHECK-NEXT: vl4re64.v v8, (a0)398; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma399; CHECK-NEXT: vmv1r.v v9, v8400; CHECK-NEXT: vmv4r.v v12, v8401; CHECK-NEXT: vmv1r.v v14, v11402; CHECK-NEXT: vmv1r.v v15, v10403; CHECK-NEXT: vs4r.v v12, (a0)404; CHECK-NEXT: ret405 %a = load <4 x i128>, ptr %p406 %res = shufflevector <4 x i128> %a, <4 x i128> poison, <4 x i32> <i32 0, i32 0, i32 3, i32 2>407 store <4 x i128> %res, ptr %p408 ret void409}410 411define void @shuffle_i256_ldst(ptr %p) vscale_range(2,2) {412; CHECK-LABEL: shuffle_i256_ldst:413; CHECK: # %bb.0:414; CHECK-NEXT: vl8re64.v v8, (a0)415; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma416; CHECK-NEXT: vmv1r.v v10, v8417; CHECK-NEXT: vmv1r.v v11, v9418; CHECK-NEXT: vmv8r.v v16, v8419; CHECK-NEXT: vmv1r.v v20, v14420; CHECK-NEXT: vmv1r.v v21, v15421; CHECK-NEXT: vmv1r.v v22, v12422; CHECK-NEXT: vmv1r.v v23, v13423; CHECK-NEXT: vs8r.v v16, (a0)424; CHECK-NEXT: ret425 %a = load <4 x i256>, ptr %p426 %res = shufflevector <4 x i256> %a, <4 x i256> poison, <4 x i32> <i32 0, i32 0, i32 3, i32 2>427 store <4 x i256> %res, ptr %p428 ret void429}430 431define void @shuffle_3_input_vectors() vscale_range(4,4) {432; CHECK-LABEL: shuffle_3_input_vectors:433; CHECK: # %bb.0:434; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma435; CHECK-NEXT: vmv.v.i v8, 1436; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma437; CHECK-NEXT: vmv.v.i v0, 6438; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma439; CHECK-NEXT: vmv.v.i v16, 0440; CHECK-NEXT: vsetivli zero, 4, e64, m1, ta, mu441; CHECK-NEXT: vslidedown.vi v20, v8, 1, v0.t442; CHECK-NEXT: vslideup.vi v20, v9, 3443; CHECK-NEXT: vslidedown.vi v21, v9, 1444; CHECK-NEXT: vmv1r.v v22, v8445; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma446; CHECK-NEXT: vmsgt.vi v8, v16, 0447; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma448; CHECK-NEXT: vmv.x.s a0, v8449; CHECK-NEXT: sb a0, 0(zero)450; CHECK-NEXT: ret451 %1 = shufflevector <32 x i64> zeroinitializer, <32 x i64> splat (i64 1), <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 poison, i32 poison, i32 33, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>452 %2 = icmp slt <32 x i64> zeroinitializer, %1453 %3 = bitcast <32 x i1> %2 to i32454 %4 = trunc i32 %3 to i8455 store i8 %4, ptr null, align 1456 ret void457}458