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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v,+m,+zvl128b -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,V128,RV32-V1283; RUN: llc -mtriple=riscv64 -mattr=+v,+m,+zvl128b -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,V128,RV64-V1284; RUN: llc -mtriple=riscv32 -mattr=+v,+m,+zvl512b -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,V512,RV32-V5125; RUN: llc -mtriple=riscv64 -mattr=+v,+m,+zvl512b -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,V512,RV64-V5126; RUN: llc -mtriple=riscv32 -mattr=+v,+m,+experimental-xrivosvizip -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZIP,RV32-ZIP7; RUN: llc -mtriple=riscv64 -mattr=+v,+m,+experimental-xrivosvizip -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZIP,RV64-ZIP8 9; Test optimizing interleaves to widening arithmetic.10 11define <4 x i8> @interleave_v2i8(<2 x i8> %x, <2 x i8> %y) {12; CHECK-LABEL: interleave_v2i8:13; CHECK: # %bb.0:14; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma15; CHECK-NEXT: vwaddu.vv v10, v8, v916; CHECK-NEXT: li a0, -117; CHECK-NEXT: vwmaccu.vx v10, a0, v918; CHECK-NEXT: vmv1r.v v8, v1019; CHECK-NEXT: ret20;21; ZIP-LABEL: interleave_v2i8:22; ZIP: # %bb.0:23; ZIP-NEXT: vsetivli zero, 4, e8, mf4, ta, ma24; ZIP-NEXT: ri.vzip2a.vv v10, v8, v925; ZIP-NEXT: vmv1r.v v8, v1026; ZIP-NEXT: ret27 %a = shufflevector <2 x i8> %x, <2 x i8> %y, <4 x i32> <i32 0, i32 2, i32 1, i32 3>28 ret <4 x i8> %a29}30 31define <4 x i16> @interleave_v2i16(<2 x i16> %x, <2 x i16> %y) {32; CHECK-LABEL: interleave_v2i16:33; CHECK: # %bb.0:34; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma35; CHECK-NEXT: vwaddu.vv v10, v8, v936; CHECK-NEXT: li a0, -137; CHECK-NEXT: vwmaccu.vx v10, a0, v938; CHECK-NEXT: vmv1r.v v8, v1039; CHECK-NEXT: ret40;41; ZIP-LABEL: interleave_v2i16:42; ZIP: # %bb.0:43; ZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma44; ZIP-NEXT: ri.vzip2a.vv v10, v8, v945; ZIP-NEXT: vmv1r.v v8, v1046; ZIP-NEXT: ret47 %a = shufflevector <2 x i16> %x, <2 x i16> %y, <4 x i32> <i32 0, i32 2, i32 1, i32 3>48 ret <4 x i16> %a49}50 51; Vector order switched for coverage.52define <4 x i32> @interleave_v2i32(<2 x i32> %x, <2 x i32> %y) {53; CHECK-LABEL: interleave_v2i32:54; CHECK: # %bb.0:55; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma56; CHECK-NEXT: vwaddu.vv v10, v9, v857; CHECK-NEXT: li a0, -158; CHECK-NEXT: vwmaccu.vx v10, a0, v859; CHECK-NEXT: vmv1r.v v8, v1060; CHECK-NEXT: ret61;62; ZIP-LABEL: interleave_v2i32:63; ZIP: # %bb.0:64; ZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma65; ZIP-NEXT: ri.vzip2a.vv v10, v9, v866; ZIP-NEXT: vmv.v.v v8, v1067; ZIP-NEXT: ret68 %a = shufflevector <2 x i32> %x, <2 x i32> %y, <4 x i32> <i32 2, i32 0, i32 3, i32 1>69 ret <4 x i32> %a70}71 72; One vXi64 test case to very that we don't optimize it.73; FIXME: Is there better codegen we can do here?74define <4 x i64> @interleave_v2i64(<2 x i64> %x, <2 x i64> %y) {75; V128-LABEL: interleave_v2i64:76; V128: # %bb.0:77; V128-NEXT: vsetivli zero, 1, e8, m1, ta, ma78; V128-NEXT: vmv1r.v v10, v979; V128-NEXT: vmv.v.i v0, 1080; V128-NEXT: vsetivli zero, 4, e64, m2, ta, ma81; V128-NEXT: vslideup.vi v12, v10, 182; V128-NEXT: vslideup.vi v12, v10, 283; V128-NEXT: vmv2r.v v10, v884; V128-NEXT: vslideup.vi v10, v8, 185; V128-NEXT: vmerge.vvm v8, v10, v12, v086; V128-NEXT: ret87;88; V512-LABEL: interleave_v2i64:89; V512: # %bb.0:90; V512-NEXT: vsetivli zero, 4, e64, m1, ta, ma91; V512-NEXT: vslideup.vi v10, v9, 192; V512-NEXT: vmv1r.v v11, v893; V512-NEXT: vslideup.vi v10, v9, 294; V512-NEXT: vmv.v.i v0, 1095; V512-NEXT: vslideup.vi v11, v8, 196; V512-NEXT: vmerge.vvm v8, v11, v10, v097; V512-NEXT: ret98;99; ZIP-LABEL: interleave_v2i64:100; ZIP: # %bb.0:101; ZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma102; ZIP-NEXT: vmv1r.v v12, v9103; ZIP-NEXT: ri.vzip2a.vv v10, v8, v12104; ZIP-NEXT: vmv.v.v v8, v10105; ZIP-NEXT: ret106 %a = shufflevector <2 x i64> %x, <2 x i64> %y, <4 x i32> <i32 0, i32 2, i32 1, i32 3>107 ret <4 x i64> %a108}109 110; Vector order switched for coverage.111define <8 x i8> @interleave_v4i8(<4 x i8> %x, <4 x i8> %y) {112; V128-LABEL: interleave_v4i8:113; V128: # %bb.0:114; V128-NEXT: vsetivli zero, 4, e8, mf4, ta, ma115; V128-NEXT: vwaddu.vv v10, v9, v8116; V128-NEXT: li a0, -1117; V128-NEXT: vwmaccu.vx v10, a0, v8118; V128-NEXT: vmv1r.v v8, v10119; V128-NEXT: ret120;121; V512-LABEL: interleave_v4i8:122; V512: # %bb.0:123; V512-NEXT: vsetivli zero, 4, e8, mf8, ta, ma124; V512-NEXT: vwaddu.vv v10, v9, v8125; V512-NEXT: li a0, -1126; V512-NEXT: vwmaccu.vx v10, a0, v8127; V512-NEXT: vmv1r.v v8, v10128; V512-NEXT: ret129;130; ZIP-LABEL: interleave_v4i8:131; ZIP: # %bb.0:132; ZIP-NEXT: vsetivli zero, 8, e8, mf2, ta, ma133; ZIP-NEXT: ri.vzip2a.vv v10, v9, v8134; ZIP-NEXT: vmv1r.v v8, v10135; ZIP-NEXT: ret136 %a = shufflevector <4 x i8> %x, <4 x i8> %y, <8 x i32> <i32 4, i32 0, i32 5, i32 1, i32 6, i32 2, i32 7, i32 3>137 ret <8 x i8> %a138}139 140; Undef elements for coverage141define <8 x i16> @interleave_v4i16(<4 x i16> %x, <4 x i16> %y) {142; V128-LABEL: interleave_v4i16:143; V128: # %bb.0:144; V128-NEXT: vsetivli zero, 4, e16, mf2, ta, ma145; V128-NEXT: vwaddu.vv v10, v8, v9146; V128-NEXT: li a0, -1147; V128-NEXT: vwmaccu.vx v10, a0, v9148; V128-NEXT: vmv1r.v v8, v10149; V128-NEXT: ret150;151; V512-LABEL: interleave_v4i16:152; V512: # %bb.0:153; V512-NEXT: vsetivli zero, 4, e16, mf4, ta, ma154; V512-NEXT: vwaddu.vv v10, v8, v9155; V512-NEXT: li a0, -1156; V512-NEXT: vwmaccu.vx v10, a0, v9157; V512-NEXT: vmv1r.v v8, v10158; V512-NEXT: ret159;160; ZIP-LABEL: interleave_v4i16:161; ZIP: # %bb.0:162; ZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma163; ZIP-NEXT: ri.vzip2a.vv v10, v8, v9164; ZIP-NEXT: vmv.v.v v8, v10165; ZIP-NEXT: ret166 %a = shufflevector <4 x i16> %x, <4 x i16> %y, <8 x i32> <i32 0, i32 4, i32 poison, i32 5, i32 2, i32 poison, i32 3, i32 7>167 ret <8 x i16> %a168}169 170define <8 x i32> @interleave_v4i32(<4 x i32> %x, <4 x i32> %y) {171; V128-LABEL: interleave_v4i32:172; V128: # %bb.0:173; V128-NEXT: vsetivli zero, 4, e32, m1, ta, ma174; V128-NEXT: vmv1r.v v10, v9175; V128-NEXT: vmv1r.v v11, v8176; V128-NEXT: vwaddu.vv v8, v11, v10177; V128-NEXT: li a0, -1178; V128-NEXT: vwmaccu.vx v8, a0, v10179; V128-NEXT: ret180;181; V512-LABEL: interleave_v4i32:182; V512: # %bb.0:183; V512-NEXT: vsetivli zero, 4, e32, mf2, ta, ma184; V512-NEXT: vwaddu.vv v10, v8, v9185; V512-NEXT: li a0, -1186; V512-NEXT: vwmaccu.vx v10, a0, v9187; V512-NEXT: vmv1r.v v8, v10188; V512-NEXT: ret189;190; ZIP-LABEL: interleave_v4i32:191; ZIP: # %bb.0:192; ZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma193; ZIP-NEXT: vmv1r.v v12, v9194; ZIP-NEXT: ri.vzip2a.vv v10, v8, v12195; ZIP-NEXT: vmv.v.v v8, v10196; ZIP-NEXT: ret197 %a = shufflevector <4 x i32> %x, <4 x i32> %y, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>198 ret <8 x i32> %a199}200 201; %y should be slid down by 2202define <4 x i32> @interleave_v4i32_offset_2(<4 x i32> %x, <4 x i32> %y) {203; V128-LABEL: interleave_v4i32_offset_2:204; V128: # %bb.0:205; V128-NEXT: vsetivli zero, 2, e32, m1, ta, ma206; V128-NEXT: vslidedown.vi v10, v9, 2207; V128-NEXT: vsetivli zero, 2, e32, mf2, ta, ma208; V128-NEXT: vwaddu.vv v9, v8, v10209; V128-NEXT: li a0, -1210; V128-NEXT: vwmaccu.vx v9, a0, v10211; V128-NEXT: vmv1r.v v8, v9212; V128-NEXT: ret213;214; V512-LABEL: interleave_v4i32_offset_2:215; V512: # %bb.0:216; V512-NEXT: vsetivli zero, 2, e32, mf2, ta, ma217; V512-NEXT: vslidedown.vi v10, v9, 2218; V512-NEXT: vwaddu.vv v9, v8, v10219; V512-NEXT: li a0, -1220; V512-NEXT: vwmaccu.vx v9, a0, v10221; V512-NEXT: vmv1r.v v8, v9222; V512-NEXT: ret223;224; ZIP-LABEL: interleave_v4i32_offset_2:225; ZIP: # %bb.0:226; ZIP-NEXT: vsetivli zero, 2, e32, m1, ta, ma227; ZIP-NEXT: vslidedown.vi v10, v9, 2228; ZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma229; ZIP-NEXT: ri.vzip2a.vv v9, v8, v10230; ZIP-NEXT: vmv.v.v v8, v9231; ZIP-NEXT: ret232 %a = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 0, i32 6, i32 1, i32 7>233 ret <4 x i32> %a234}235 236; %y should be slid down by 1237define <4 x i32> @interleave_v4i32_offset_1(<4 x i32> %x, <4 x i32> %y) {238; V128-LABEL: interleave_v4i32_offset_1:239; V128: # %bb.0:240; V128-NEXT: vsetivli zero, 4, e32, m1, ta, mu241; V128-NEXT: vmv.v.i v0, 8242; V128-NEXT: vmv1r.v v10, v9243; V128-NEXT: vslideup.vi v10, v9, 1, v0.t244; V128-NEXT: vmv.v.i v0, 10245; V128-NEXT: vsetivli zero, 2, e64, m1, ta, ma246; V128-NEXT: vzext.vf2 v9, v8247; V128-NEXT: vsetivli zero, 4, e32, m1, ta, ma248; V128-NEXT: vmerge.vvm v8, v9, v10, v0249; V128-NEXT: ret250;251; V512-LABEL: interleave_v4i32_offset_1:252; V512: # %bb.0:253; V512-NEXT: vsetivli zero, 4, e32, mf2, ta, mu254; V512-NEXT: vmv.v.i v0, 8255; V512-NEXT: vmv1r.v v10, v9256; V512-NEXT: vslideup.vi v10, v9, 1, v0.t257; V512-NEXT: vmv.v.i v0, 10258; V512-NEXT: vsetivli zero, 2, e64, m1, ta, ma259; V512-NEXT: vzext.vf2 v9, v8260; V512-NEXT: vsetivli zero, 4, e32, mf2, ta, ma261; V512-NEXT: vmerge.vvm v8, v9, v10, v0262; V512-NEXT: ret263;264; ZIP-LABEL: interleave_v4i32_offset_1:265; ZIP: # %bb.0:266; ZIP-NEXT: vsetivli zero, 4, e32, m1, ta, mu267; ZIP-NEXT: vmv.v.i v0, 8268; ZIP-NEXT: vmv1r.v v10, v9269; ZIP-NEXT: vslideup.vi v10, v9, 1, v0.t270; ZIP-NEXT: vmv.v.i v0, 10271; ZIP-NEXT: ri.vzip2a.vv v11, v8, v9272; ZIP-NEXT: vmerge.vvm v8, v11, v10, v0273; ZIP-NEXT: ret274 %a = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 0, i32 5, i32 1, i32 6>275 ret <4 x i32> %a276}277 278define <16 x i8> @interleave_v8i8(<8 x i8> %x, <8 x i8> %y) {279; V128-LABEL: interleave_v8i8:280; V128: # %bb.0:281; V128-NEXT: vsetivli zero, 8, e8, mf2, ta, ma282; V128-NEXT: vwaddu.vv v10, v8, v9283; V128-NEXT: li a0, -1284; V128-NEXT: vwmaccu.vx v10, a0, v9285; V128-NEXT: vmv1r.v v8, v10286; V128-NEXT: ret287;288; V512-LABEL: interleave_v8i8:289; V512: # %bb.0:290; V512-NEXT: vsetivli zero, 8, e8, mf8, ta, ma291; V512-NEXT: vwaddu.vv v10, v8, v9292; V512-NEXT: li a0, -1293; V512-NEXT: vwmaccu.vx v10, a0, v9294; V512-NEXT: vmv1r.v v8, v10295; V512-NEXT: ret296;297; ZIP-LABEL: interleave_v8i8:298; ZIP: # %bb.0:299; ZIP-NEXT: vsetivli zero, 16, e8, m1, ta, ma300; ZIP-NEXT: ri.vzip2a.vv v10, v8, v9301; ZIP-NEXT: vmv.v.v v8, v10302; ZIP-NEXT: ret303 %a = shufflevector <8 x i8> %x, <8 x i8> %y, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>304 ret <16 x i8> %a305}306 307; Vector order switched for coverage.308define <16 x i16> @interleave_v8i16(<8 x i16> %x, <8 x i16> %y) {309; V128-LABEL: interleave_v8i16:310; V128: # %bb.0:311; V128-NEXT: vsetivli zero, 8, e16, m1, ta, ma312; V128-NEXT: vmv1r.v v10, v9313; V128-NEXT: vmv1r.v v11, v8314; V128-NEXT: vwaddu.vv v8, v10, v11315; V128-NEXT: li a0, -1316; V128-NEXT: vwmaccu.vx v8, a0, v11317; V128-NEXT: ret318;319; V512-LABEL: interleave_v8i16:320; V512: # %bb.0:321; V512-NEXT: vsetivli zero, 8, e16, mf4, ta, ma322; V512-NEXT: vwaddu.vv v10, v9, v8323; V512-NEXT: li a0, -1324; V512-NEXT: vwmaccu.vx v10, a0, v8325; V512-NEXT: vmv1r.v v8, v10326; V512-NEXT: ret327;328; ZIP-LABEL: interleave_v8i16:329; ZIP: # %bb.0:330; ZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma331; ZIP-NEXT: vmv1r.v v12, v9332; ZIP-NEXT: ri.vzip2a.vv v10, v12, v8333; ZIP-NEXT: vmv.v.v v8, v10334; ZIP-NEXT: ret335 %a = shufflevector <8 x i16> %x, <8 x i16> %y, <16 x i32> <i32 8, i32 0, i32 9, i32 1, i32 10, i32 2, i32 11, i32 3, i32 12, i32 4, i32 13, i32 5, i32 14, i32 6, i32 15, i32 7>336 ret <16 x i16> %a337}338 339define <16 x i32> @interleave_v8i32(<8 x i32> %x, <8 x i32> %y) {340; V128-LABEL: interleave_v8i32:341; V128: # %bb.0:342; V128-NEXT: vsetivli zero, 8, e32, m2, ta, ma343; V128-NEXT: vmv2r.v v12, v10344; V128-NEXT: vmv2r.v v14, v8345; V128-NEXT: vwaddu.vv v8, v14, v12346; V128-NEXT: li a0, -1347; V128-NEXT: vwmaccu.vx v8, a0, v12348; V128-NEXT: ret349;350; V512-LABEL: interleave_v8i32:351; V512: # %bb.0:352; V512-NEXT: vsetivli zero, 8, e32, mf2, ta, ma353; V512-NEXT: vwaddu.vv v10, v8, v9354; V512-NEXT: li a0, -1355; V512-NEXT: vwmaccu.vx v10, a0, v9356; V512-NEXT: vmv1r.v v8, v10357; V512-NEXT: ret358;359; ZIP-LABEL: interleave_v8i32:360; ZIP: # %bb.0:361; ZIP-NEXT: vsetivli zero, 16, e32, m4, ta, ma362; ZIP-NEXT: vmv2r.v v16, v10363; ZIP-NEXT: ri.vzip2a.vv v12, v8, v16364; ZIP-NEXT: vmv.v.v v8, v12365; ZIP-NEXT: ret366 %a = shufflevector <8 x i32> %x, <8 x i32> %y, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>367 ret <16 x i32> %a368}369 370define <32 x i8> @interleave_v16i8(<16 x i8> %x, <16 x i8> %y) {371; V128-LABEL: interleave_v16i8:372; V128: # %bb.0:373; V128-NEXT: vsetivli zero, 16, e8, m1, ta, ma374; V128-NEXT: vmv1r.v v10, v9375; V128-NEXT: vmv1r.v v11, v8376; V128-NEXT: vwaddu.vv v8, v11, v10377; V128-NEXT: li a0, -1378; V128-NEXT: vwmaccu.vx v8, a0, v10379; V128-NEXT: ret380;381; V512-LABEL: interleave_v16i8:382; V512: # %bb.0:383; V512-NEXT: vsetivli zero, 16, e8, mf4, ta, ma384; V512-NEXT: vwaddu.vv v10, v8, v9385; V512-NEXT: li a0, -1386; V512-NEXT: vwmaccu.vx v10, a0, v9387; V512-NEXT: vmv1r.v v8, v10388; V512-NEXT: ret389;390; ZIP-LABEL: interleave_v16i8:391; ZIP: # %bb.0:392; ZIP-NEXT: vsetivli zero, 1, e8, m1, ta, ma393; ZIP-NEXT: vmv1r.v v12, v9394; ZIP-NEXT: li a0, 32395; ZIP-NEXT: vsetvli zero, a0, e8, m2, ta, ma396; ZIP-NEXT: ri.vzip2a.vv v10, v8, v12397; ZIP-NEXT: vmv.v.v v8, v10398; ZIP-NEXT: ret399 %a = shufflevector <16 x i8> %x, <16 x i8> %y, <32 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23, i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>400 ret <32 x i8> %a401}402 403define <32 x i16> @interleave_v16i16(<16 x i16> %x, <16 x i16> %y) {404; V128-LABEL: interleave_v16i16:405; V128: # %bb.0:406; V128-NEXT: vsetivli zero, 16, e16, m2, ta, ma407; V128-NEXT: vmv2r.v v12, v10408; V128-NEXT: vmv2r.v v14, v8409; V128-NEXT: vwaddu.vv v8, v14, v12410; V128-NEXT: li a0, -1411; V128-NEXT: vwmaccu.vx v8, a0, v12412; V128-NEXT: ret413;414; V512-LABEL: interleave_v16i16:415; V512: # %bb.0:416; V512-NEXT: vsetivli zero, 16, e16, mf2, ta, ma417; V512-NEXT: vwaddu.vv v10, v8, v9418; V512-NEXT: li a0, -1419; V512-NEXT: vwmaccu.vx v10, a0, v9420; V512-NEXT: vmv1r.v v8, v10421; V512-NEXT: ret422;423; ZIP-LABEL: interleave_v16i16:424; ZIP: # %bb.0:425; ZIP-NEXT: vsetivli zero, 1, e8, m1, ta, ma426; ZIP-NEXT: vmv2r.v v16, v10427; ZIP-NEXT: li a0, 32428; ZIP-NEXT: vsetvli zero, a0, e16, m4, ta, ma429; ZIP-NEXT: ri.vzip2a.vv v12, v8, v16430; ZIP-NEXT: vmv.v.v v8, v12431; ZIP-NEXT: ret432 %a = shufflevector <16 x i16> %x, <16 x i16> %y, <32 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23, i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>433 ret <32 x i16> %a434}435 436define <32 x i32> @interleave_v16i32(<16 x i32> %x, <16 x i32> %y) {437; V128-LABEL: interleave_v16i32:438; V128: # %bb.0:439; V128-NEXT: vsetivli zero, 16, e32, m4, ta, ma440; V128-NEXT: vmv4r.v v16, v12441; V128-NEXT: vmv4r.v v20, v8442; V128-NEXT: vwaddu.vv v8, v20, v16443; V128-NEXT: li a0, -1444; V128-NEXT: vwmaccu.vx v8, a0, v16445; V128-NEXT: ret446;447; V512-LABEL: interleave_v16i32:448; V512: # %bb.0:449; V512-NEXT: vsetivli zero, 16, e32, m1, ta, ma450; V512-NEXT: vmv1r.v v10, v9451; V512-NEXT: vmv1r.v v11, v8452; V512-NEXT: vwaddu.vv v8, v11, v10453; V512-NEXT: li a0, -1454; V512-NEXT: vwmaccu.vx v8, a0, v10455; V512-NEXT: ret456;457; ZIP-LABEL: interleave_v16i32:458; ZIP: # %bb.0:459; ZIP-NEXT: vsetivli zero, 1, e8, m1, ta, ma460; ZIP-NEXT: vmv4r.v v24, v12461; ZIP-NEXT: li a0, 32462; ZIP-NEXT: vsetvli zero, a0, e32, m8, ta, ma463; ZIP-NEXT: ri.vzip2a.vv v16, v8, v24464; ZIP-NEXT: vmv.v.v v8, v16465; ZIP-NEXT: ret466 %a = shufflevector <16 x i32> %x, <16 x i32> %y, <32 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23, i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>467 ret <32 x i32> %a468}469 470define <64 x i8> @interleave_v32i8(<32 x i8> %x, <32 x i8> %y) {471; V128-LABEL: interleave_v32i8:472; V128: # %bb.0:473; V128-NEXT: vsetivli zero, 1, e8, m1, ta, ma474; V128-NEXT: vmv2r.v v12, v10475; V128-NEXT: vmv2r.v v14, v8476; V128-NEXT: li a0, 32477; V128-NEXT: vsetvli zero, a0, e8, m2, ta, ma478; V128-NEXT: vwaddu.vv v8, v14, v12479; V128-NEXT: li a0, -1480; V128-NEXT: vwmaccu.vx v8, a0, v12481; V128-NEXT: ret482;483; V512-LABEL: interleave_v32i8:484; V512: # %bb.0:485; V512-NEXT: li a0, 32486; V512-NEXT: vsetvli zero, a0, e8, mf2, ta, ma487; V512-NEXT: vwaddu.vv v10, v8, v9488; V512-NEXT: li a0, -1489; V512-NEXT: vwmaccu.vx v10, a0, v9490; V512-NEXT: vmv1r.v v8, v10491; V512-NEXT: ret492;493; ZIP-LABEL: interleave_v32i8:494; ZIP: # %bb.0:495; ZIP-NEXT: vsetivli zero, 1, e8, m1, ta, ma496; ZIP-NEXT: vmv2r.v v16, v10497; ZIP-NEXT: li a0, 64498; ZIP-NEXT: vsetvli zero, a0, e8, m4, ta, ma499; ZIP-NEXT: ri.vzip2a.vv v12, v8, v16500; ZIP-NEXT: vmv.v.v v8, v12501; ZIP-NEXT: ret502 %a = shufflevector <32 x i8> %x, <32 x i8> %y, <64 x i32> <i32 0, i32 32, i32 1, i32 33, i32 2, i32 34, i32 3, i32 35, i32 4, i32 36, i32 5, i32 37, i32 6, i32 38, i32 7, i32 39, i32 8, i32 40, i32 9, i32 41, i32 10, i32 42, i32 11, i32 43, i32 12, i32 44, i32 13, i32 45, i32 14, i32 46, i32 15, i32 47, i32 16, i32 48, i32 17, i32 49, i32 18, i32 50, i32 19, i32 51, i32 20, i32 52, i32 21, i32 53, i32 22, i32 54, i32 23, i32 55, i32 24, i32 56, i32 25, i32 57, i32 26, i32 58, i32 27, i32 59, i32 28, i32 60, i32 29, i32 61, i32 30, i32 62, i32 31, i32 63>503 ret <64 x i8> %a504}505 506define <64 x i16> @interleave_v32i16(<32 x i16> %x, <32 x i16> %y) {507; V128-LABEL: interleave_v32i16:508; V128: # %bb.0:509; V128-NEXT: vsetivli zero, 1, e8, m1, ta, ma510; V128-NEXT: vmv4r.v v16, v12511; V128-NEXT: vmv4r.v v20, v8512; V128-NEXT: li a0, 32513; V128-NEXT: vsetvli zero, a0, e16, m4, ta, ma514; V128-NEXT: vwaddu.vv v8, v20, v16515; V128-NEXT: li a0, -1516; V128-NEXT: vwmaccu.vx v8, a0, v16517; V128-NEXT: ret518;519; V512-LABEL: interleave_v32i16:520; V512: # %bb.0:521; V512-NEXT: vsetivli zero, 1, e8, m1, ta, ma522; V512-NEXT: vmv1r.v v10, v9523; V512-NEXT: vmv1r.v v11, v8524; V512-NEXT: li a0, 32525; V512-NEXT: vsetvli zero, a0, e16, m1, ta, ma526; V512-NEXT: vwaddu.vv v8, v11, v10527; V512-NEXT: li a0, -1528; V512-NEXT: vwmaccu.vx v8, a0, v10529; V512-NEXT: ret530;531; ZIP-LABEL: interleave_v32i16:532; ZIP: # %bb.0:533; ZIP-NEXT: vsetivli zero, 1, e8, m1, ta, ma534; ZIP-NEXT: vmv4r.v v24, v12535; ZIP-NEXT: li a0, 64536; ZIP-NEXT: vsetvli zero, a0, e16, m8, ta, ma537; ZIP-NEXT: ri.vzip2a.vv v16, v8, v24538; ZIP-NEXT: vmv.v.v v8, v16539; ZIP-NEXT: ret540 %a = shufflevector <32 x i16> %x, <32 x i16> %y, <64 x i32> <i32 0, i32 32, i32 1, i32 33, i32 2, i32 34, i32 3, i32 35, i32 4, i32 36, i32 5, i32 37, i32 6, i32 38, i32 7, i32 39, i32 8, i32 40, i32 9, i32 41, i32 10, i32 42, i32 11, i32 43, i32 12, i32 44, i32 13, i32 45, i32 14, i32 46, i32 15, i32 47, i32 16, i32 48, i32 17, i32 49, i32 18, i32 50, i32 19, i32 51, i32 20, i32 52, i32 21, i32 53, i32 22, i32 54, i32 23, i32 55, i32 24, i32 56, i32 25, i32 57, i32 26, i32 58, i32 27, i32 59, i32 28, i32 60, i32 29, i32 61, i32 30, i32 62, i32 31, i32 63>541 ret <64 x i16> %a542}543 544define <64 x i32> @interleave_v32i32(<32 x i32> %x, <32 x i32> %y) {545; V128-LABEL: interleave_v32i32:546; V128: # %bb.0:547; V128-NEXT: addi sp, sp, -16548; V128-NEXT: .cfi_def_cfa_offset 16549; V128-NEXT: csrr a0, vlenb550; V128-NEXT: slli a0, a0, 3551; V128-NEXT: sub sp, sp, a0552; V128-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb553; V128-NEXT: addi a0, sp, 16554; V128-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill555; V128-NEXT: vsetivli zero, 16, e32, m8, ta, ma556; V128-NEXT: vslidedown.vi v24, v16, 16557; V128-NEXT: li a0, 32558; V128-NEXT: lui a1, 699051559; V128-NEXT: vslidedown.vi v0, v8, 16560; V128-NEXT: vsetivli zero, 16, e64, m8, ta, ma561; V128-NEXT: vzext.vf2 v8, v24562; V128-NEXT: addi a1, a1, -1366563; V128-NEXT: vzext.vf2 v24, v0564; V128-NEXT: vmv.s.x v0, a1565; V128-NEXT: vsll.vx v8, v8, a0566; V128-NEXT: vsetvli zero, a0, e32, m8, ta, ma567; V128-NEXT: vmerge.vvm v24, v24, v8, v0568; V128-NEXT: addi a0, sp, 16569; V128-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload570; V128-NEXT: vsetivli zero, 16, e32, m4, ta, ma571; V128-NEXT: vwaddu.vv v0, v8, v16572; V128-NEXT: li a0, -1573; V128-NEXT: vwmaccu.vx v0, a0, v16574; V128-NEXT: vmv8r.v v8, v0575; V128-NEXT: vmv8r.v v16, v24576; V128-NEXT: csrr a0, vlenb577; V128-NEXT: slli a0, a0, 3578; V128-NEXT: add sp, sp, a0579; V128-NEXT: .cfi_def_cfa sp, 16580; V128-NEXT: addi sp, sp, 16581; V128-NEXT: .cfi_def_cfa_offset 0582; V128-NEXT: ret583;584; V512-LABEL: interleave_v32i32:585; V512: # %bb.0:586; V512-NEXT: vsetivli zero, 1, e8, m1, ta, ma587; V512-NEXT: vmv2r.v v12, v10588; V512-NEXT: vmv2r.v v14, v8589; V512-NEXT: li a0, 32590; V512-NEXT: vsetvli zero, a0, e32, m2, ta, ma591; V512-NEXT: vwaddu.vv v8, v14, v12592; V512-NEXT: li a0, -1593; V512-NEXT: vwmaccu.vx v8, a0, v12594; V512-NEXT: ret595;596; ZIP-LABEL: interleave_v32i32:597; ZIP: # %bb.0:598; ZIP-NEXT: addi sp, sp, -16599; ZIP-NEXT: .cfi_def_cfa_offset 16600; ZIP-NEXT: csrr a0, vlenb601; ZIP-NEXT: li a1, 40602; ZIP-NEXT: mul a0, a0, a1603; ZIP-NEXT: sub sp, sp, a0604; ZIP-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x28, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 40 * vlenb605; ZIP-NEXT: csrr a0, vlenb606; ZIP-NEXT: slli a0, a0, 5607; ZIP-NEXT: add a0, sp, a0608; ZIP-NEXT: addi a0, a0, 16609; ZIP-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill610; ZIP-NEXT: addi a0, sp, 16611; ZIP-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill612; ZIP-NEXT: li a0, 32613; ZIP-NEXT: vsetivli zero, 16, e32, m8, ta, ma614; ZIP-NEXT: vslidedown.vi v16, v8, 16615; ZIP-NEXT: vsetvli zero, a0, e32, m8, ta, ma616; ZIP-NEXT: ri.vzip2a.vv v8, v16, v0617; ZIP-NEXT: csrr a1, vlenb618; ZIP-NEXT: slli a1, a1, 3619; ZIP-NEXT: add a1, sp, a1620; ZIP-NEXT: addi a1, a1, 16621; ZIP-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill622; ZIP-NEXT: csrr a1, vlenb623; ZIP-NEXT: slli a1, a1, 5624; ZIP-NEXT: add a1, sp, a1625; ZIP-NEXT: addi a1, a1, 16626; ZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload627; ZIP-NEXT: vsetivli zero, 16, e32, m8, ta, ma628; ZIP-NEXT: vslidedown.vi v16, v16, 16629; ZIP-NEXT: csrr a1, vlenb630; ZIP-NEXT: li a2, 24631; ZIP-NEXT: mul a1, a1, a2632; ZIP-NEXT: add a1, sp, a1633; ZIP-NEXT: addi a1, a1, 16634; ZIP-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill635; ZIP-NEXT: lui a1, 699051636; ZIP-NEXT: addi a1, a1, -1366637; ZIP-NEXT: vmv.s.x v0, a1638; ZIP-NEXT: csrr a1, vlenb639; ZIP-NEXT: slli a1, a1, 4640; ZIP-NEXT: add a1, sp, a1641; ZIP-NEXT: addi a1, a1, 16642; ZIP-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill643; ZIP-NEXT: csrr a1, vlenb644; ZIP-NEXT: li a2, 24645; ZIP-NEXT: mul a1, a1, a2646; ZIP-NEXT: add a1, sp, a1647; ZIP-NEXT: addi a1, a1, 16648; ZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload649; ZIP-NEXT: csrr a1, vlenb650; ZIP-NEXT: slli a1, a1, 4651; ZIP-NEXT: add a1, sp, a1652; ZIP-NEXT: addi a1, a1, 16653; ZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload654; ZIP-NEXT: csrr a1, vlenb655; ZIP-NEXT: slli a1, a1, 3656; ZIP-NEXT: add a1, sp, a1657; ZIP-NEXT: addi a1, a1, 16658; ZIP-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload659; ZIP-NEXT: vsetvli zero, a0, e32, m8, ta, mu660; ZIP-NEXT: ri.vzip2a.vv v8, v24, v16, v0.t661; ZIP-NEXT: vmv.v.v v24, v8662; ZIP-NEXT: csrr a0, vlenb663; ZIP-NEXT: slli a0, a0, 5664; ZIP-NEXT: add a0, sp, a0665; ZIP-NEXT: addi a0, a0, 16666; ZIP-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload667; ZIP-NEXT: addi a0, sp, 16668; ZIP-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload669; ZIP-NEXT: ri.vzip2a.vv v0, v8, v16670; ZIP-NEXT: vmv.v.v v8, v0671; ZIP-NEXT: vmv.v.v v16, v24672; ZIP-NEXT: csrr a0, vlenb673; ZIP-NEXT: li a1, 40674; ZIP-NEXT: mul a0, a0, a1675; ZIP-NEXT: add sp, sp, a0676; ZIP-NEXT: .cfi_def_cfa sp, 16677; ZIP-NEXT: addi sp, sp, 16678; ZIP-NEXT: .cfi_def_cfa_offset 0679; ZIP-NEXT: ret680 %a = shufflevector <32 x i32> %x, <32 x i32> %y, <64 x i32> <i32 0, i32 32, i32 1, i32 33, i32 2, i32 34, i32 3, i32 35, i32 4, i32 36, i32 5, i32 37, i32 6, i32 38, i32 7, i32 39, i32 8, i32 40, i32 9, i32 41, i32 10, i32 42, i32 11, i32 43, i32 12, i32 44, i32 13, i32 45, i32 14, i32 46, i32 15, i32 47, i32 16, i32 48, i32 17, i32 49, i32 18, i32 50, i32 19, i32 51, i32 20, i32 52, i32 21, i32 53, i32 22, i32 54, i32 23, i32 55, i32 24, i32 56, i32 25, i32 57, i32 26, i32 58, i32 27, i32 59, i32 28, i32 60, i32 29, i32 61, i32 30, i32 62, i32 31, i32 63>681 ret <64 x i32> %a682}683 684define <4 x i8> @unary_interleave_v4i8(<4 x i8> %x) {685; V128-LABEL: unary_interleave_v4i8:686; V128: # %bb.0:687; V128-NEXT: vsetivli zero, 2, e8, mf4, ta, ma688; V128-NEXT: vslidedown.vi v10, v8, 2689; V128-NEXT: vsetivli zero, 2, e8, mf8, ta, ma690; V128-NEXT: vwaddu.vv v9, v8, v10691; V128-NEXT: li a0, -1692; V128-NEXT: vwmaccu.vx v9, a0, v10693; V128-NEXT: vmv1r.v v8, v9694; V128-NEXT: ret695;696; V512-LABEL: unary_interleave_v4i8:697; V512: # %bb.0:698; V512-NEXT: vsetivli zero, 2, e8, mf8, ta, ma699; V512-NEXT: vslidedown.vi v10, v8, 2700; V512-NEXT: vwaddu.vv v9, v8, v10701; V512-NEXT: li a0, -1702; V512-NEXT: vwmaccu.vx v9, a0, v10703; V512-NEXT: vmv1r.v v8, v9704; V512-NEXT: ret705;706; ZIP-LABEL: unary_interleave_v4i8:707; ZIP: # %bb.0:708; ZIP-NEXT: vsetivli zero, 2, e8, mf4, ta, ma709; ZIP-NEXT: vslidedown.vi v10, v8, 2710; ZIP-NEXT: vsetivli zero, 4, e8, mf4, ta, ma711; ZIP-NEXT: ri.vzip2a.vv v9, v8, v10712; ZIP-NEXT: vmv1r.v v8, v9713; ZIP-NEXT: ret714 %a = shufflevector <4 x i8> %x, <4 x i8> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>715 ret <4 x i8> %a716}717 718; This shouldn't be interleaved719define <4 x i8> @unary_interleave_v4i8_invalid(<4 x i8> %x) {720; V128-LABEL: unary_interleave_v4i8_invalid:721; V128: # %bb.0:722; V128-NEXT: lui a0, 16723; V128-NEXT: addi a0, a0, 768724; V128-NEXT: vsetivli zero, 4, e32, m1, ta, ma725; V128-NEXT: vmv.s.x v10, a0726; V128-NEXT: vsetvli zero, zero, e8, mf4, ta, ma727; V128-NEXT: vrgather.vv v9, v8, v10728; V128-NEXT: vmv1r.v v8, v9729; V128-NEXT: ret730;731; V512-LABEL: unary_interleave_v4i8_invalid:732; V512: # %bb.0:733; V512-NEXT: lui a0, 16734; V512-NEXT: addi a0, a0, 768735; V512-NEXT: vsetivli zero, 4, e32, m1, ta, ma736; V512-NEXT: vmv.s.x v10, a0737; V512-NEXT: vsetivli zero, 4, e8, mf8, ta, ma738; V512-NEXT: vrgather.vv v9, v8, v10739; V512-NEXT: vmv1r.v v8, v9740; V512-NEXT: ret741;742; ZIP-LABEL: unary_interleave_v4i8_invalid:743; ZIP: # %bb.0:744; ZIP-NEXT: lui a0, 16745; ZIP-NEXT: addi a0, a0, 768746; ZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma747; ZIP-NEXT: vmv.s.x v10, a0748; ZIP-NEXT: vsetvli zero, zero, e8, mf4, ta, ma749; ZIP-NEXT: vrgather.vv v9, v8, v10750; ZIP-NEXT: vmv1r.v v8, v9751; ZIP-NEXT: ret752 %a = shufflevector <4 x i8> %x, <4 x i8> poison, <4 x i32> <i32 0, i32 3, i32 1, i32 4>753 ret <4 x i8> %a754}755 756define <4 x i16> @unary_interleave_v4i16(<4 x i16> %x) {757; V128-LABEL: unary_interleave_v4i16:758; V128: # %bb.0:759; V128-NEXT: vsetivli zero, 2, e16, mf2, ta, ma760; V128-NEXT: vslidedown.vi v10, v8, 2761; V128-NEXT: vsetivli zero, 2, e16, mf4, ta, ma762; V128-NEXT: vwaddu.vv v9, v8, v10763; V128-NEXT: li a0, -1764; V128-NEXT: vwmaccu.vx v9, a0, v10765; V128-NEXT: vmv1r.v v8, v9766; V128-NEXT: ret767;768; V512-LABEL: unary_interleave_v4i16:769; V512: # %bb.0:770; V512-NEXT: vsetivli zero, 2, e16, mf4, ta, ma771; V512-NEXT: vslidedown.vi v10, v8, 2772; V512-NEXT: vwaddu.vv v9, v8, v10773; V512-NEXT: li a0, -1774; V512-NEXT: vwmaccu.vx v9, a0, v10775; V512-NEXT: vmv1r.v v8, v9776; V512-NEXT: ret777;778; ZIP-LABEL: unary_interleave_v4i16:779; ZIP: # %bb.0:780; ZIP-NEXT: vsetivli zero, 2, e16, mf2, ta, ma781; ZIP-NEXT: vslidedown.vi v10, v8, 2782; ZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma783; ZIP-NEXT: ri.vzip2a.vv v9, v8, v10784; ZIP-NEXT: vmv1r.v v8, v9785; ZIP-NEXT: ret786 %a = shufflevector <4 x i16> %x, <4 x i16> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>787 ret <4 x i16> %a788}789 790define <4 x i32> @unary_interleave_v4i32(<4 x i32> %x) {791; V128-LABEL: unary_interleave_v4i32:792; V128: # %bb.0:793; V128-NEXT: vsetivli zero, 2, e32, m1, ta, ma794; V128-NEXT: vslidedown.vi v10, v8, 2795; V128-NEXT: vsetivli zero, 2, e32, mf2, ta, ma796; V128-NEXT: vwaddu.vv v9, v8, v10797; V128-NEXT: li a0, -1798; V128-NEXT: vwmaccu.vx v9, a0, v10799; V128-NEXT: vmv1r.v v8, v9800; V128-NEXT: ret801;802; V512-LABEL: unary_interleave_v4i32:803; V512: # %bb.0:804; V512-NEXT: vsetivli zero, 2, e32, mf2, ta, ma805; V512-NEXT: vslidedown.vi v10, v8, 2806; V512-NEXT: vwaddu.vv v9, v8, v10807; V512-NEXT: li a0, -1808; V512-NEXT: vwmaccu.vx v9, a0, v10809; V512-NEXT: vmv1r.v v8, v9810; V512-NEXT: ret811;812; ZIP-LABEL: unary_interleave_v4i32:813; ZIP: # %bb.0:814; ZIP-NEXT: vsetivli zero, 2, e32, m1, ta, ma815; ZIP-NEXT: vslidedown.vi v10, v8, 2816; ZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma817; ZIP-NEXT: ri.vzip2a.vv v9, v8, v10818; ZIP-NEXT: vmv.v.v v8, v9819; ZIP-NEXT: ret820 %a = shufflevector <4 x i32> %x, <4 x i32> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>821 ret <4 x i32> %a822}823 824; FIXME: Is there better codegen we can do here?825define <4 x i64> @unary_interleave_v4i64(<4 x i64> %x) {826; V128-LABEL: unary_interleave_v4i64:827; V128: # %bb.0:828; V128-NEXT: lui a0, 12304829; V128-NEXT: addi a0, a0, 512830; V128-NEXT: vsetivli zero, 4, e32, m1, ta, ma831; V128-NEXT: vmv.s.x v10, a0832; V128-NEXT: vsetvli zero, zero, e16, mf2, ta, ma833; V128-NEXT: vsext.vf2 v12, v10834; V128-NEXT: vsetvli zero, zero, e64, m2, ta, ma835; V128-NEXT: vrgatherei16.vv v10, v8, v12836; V128-NEXT: vmv.v.v v8, v10837; V128-NEXT: ret838;839; RV32-V512-LABEL: unary_interleave_v4i64:840; RV32-V512: # %bb.0:841; RV32-V512-NEXT: lui a0, 12304842; RV32-V512-NEXT: addi a0, a0, 512843; RV32-V512-NEXT: vsetivli zero, 4, e32, m1, ta, ma844; RV32-V512-NEXT: vmv.s.x v9, a0845; RV32-V512-NEXT: vsetivli zero, 4, e16, mf4, ta, ma846; RV32-V512-NEXT: vsext.vf2 v10, v9847; RV32-V512-NEXT: vsetvli zero, zero, e64, m1, ta, ma848; RV32-V512-NEXT: vrgatherei16.vv v9, v8, v10849; RV32-V512-NEXT: vmv.v.v v8, v9850; RV32-V512-NEXT: ret851;852; RV64-V512-LABEL: unary_interleave_v4i64:853; RV64-V512: # %bb.0:854; RV64-V512-NEXT: lui a0, 12304855; RV64-V512-NEXT: addi a0, a0, 512856; RV64-V512-NEXT: vsetivli zero, 4, e64, m1, ta, ma857; RV64-V512-NEXT: vmv.s.x v9, a0858; RV64-V512-NEXT: vsext.vf8 v10, v9859; RV64-V512-NEXT: vrgather.vv v9, v8, v10860; RV64-V512-NEXT: vmv.v.v v8, v9861; RV64-V512-NEXT: ret862;863; ZIP-LABEL: unary_interleave_v4i64:864; ZIP: # %bb.0:865; ZIP-NEXT: vsetivli zero, 2, e64, m2, ta, ma866; ZIP-NEXT: vslidedown.vi v12, v8, 2867; ZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma868; ZIP-NEXT: ri.vzip2a.vv v10, v8, v12869; ZIP-NEXT: vmv.v.v v8, v10870; ZIP-NEXT: ret871 %a = shufflevector <4 x i64> %x, <4 x i64> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>872 ret <4 x i64> %a873}874 875define <8 x i8> @unary_interleave_v8i8(<8 x i8> %x) {876; V128-LABEL: unary_interleave_v8i8:877; V128: # %bb.0:878; V128-NEXT: vsetivli zero, 4, e8, mf2, ta, ma879; V128-NEXT: vslidedown.vi v10, v8, 4880; V128-NEXT: vsetivli zero, 4, e8, mf4, ta, ma881; V128-NEXT: vwaddu.vv v9, v8, v10882; V128-NEXT: li a0, -1883; V128-NEXT: vwmaccu.vx v9, a0, v10884; V128-NEXT: vmv1r.v v8, v9885; V128-NEXT: ret886;887; V512-LABEL: unary_interleave_v8i8:888; V512: # %bb.0:889; V512-NEXT: vsetivli zero, 4, e8, mf8, ta, ma890; V512-NEXT: vslidedown.vi v10, v8, 4891; V512-NEXT: vwaddu.vv v9, v8, v10892; V512-NEXT: li a0, -1893; V512-NEXT: vwmaccu.vx v9, a0, v10894; V512-NEXT: vmv1r.v v8, v9895; V512-NEXT: ret896;897; ZIP-LABEL: unary_interleave_v8i8:898; ZIP: # %bb.0:899; ZIP-NEXT: vsetivli zero, 4, e8, mf2, ta, ma900; ZIP-NEXT: vslidedown.vi v10, v8, 4901; ZIP-NEXT: vsetivli zero, 8, e8, mf2, ta, ma902; ZIP-NEXT: ri.vzip2a.vv v9, v8, v10903; ZIP-NEXT: vmv1r.v v8, v9904; ZIP-NEXT: ret905 %a = shufflevector <8 x i8> %x, <8 x i8> poison, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 poison, i32 6, i32 3, i32 7>906 ret <8 x i8> %a907}908 909define <8 x i16> @unary_interleave_v8i16(<8 x i16> %x) {910; V128-LABEL: unary_interleave_v8i16:911; V128: # %bb.0:912; V128-NEXT: vsetivli zero, 4, e16, m1, ta, ma913; V128-NEXT: vslidedown.vi v10, v8, 4914; V128-NEXT: vsetivli zero, 4, e16, mf2, ta, ma915; V128-NEXT: vwaddu.vv v9, v10, v8916; V128-NEXT: li a0, -1917; V128-NEXT: vwmaccu.vx v9, a0, v8918; V128-NEXT: vmv1r.v v8, v9919; V128-NEXT: ret920;921; V512-LABEL: unary_interleave_v8i16:922; V512: # %bb.0:923; V512-NEXT: vsetivli zero, 4, e16, mf4, ta, ma924; V512-NEXT: vslidedown.vi v10, v8, 4925; V512-NEXT: vwaddu.vv v9, v10, v8926; V512-NEXT: li a0, -1927; V512-NEXT: vwmaccu.vx v9, a0, v8928; V512-NEXT: vmv1r.v v8, v9929; V512-NEXT: ret930;931; ZIP-LABEL: unary_interleave_v8i16:932; ZIP: # %bb.0:933; ZIP-NEXT: vsetivli zero, 4, e16, m1, ta, ma934; ZIP-NEXT: vslidedown.vi v10, v8, 4935; ZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma936; ZIP-NEXT: ri.vzip2a.vv v9, v10, v8937; ZIP-NEXT: vmv.v.v v8, v9938; ZIP-NEXT: ret939 %a = shufflevector <8 x i16> %x, <8 x i16> poison, <8 x i32> <i32 4, i32 poison, i32 5, i32 1, i32 6, i32 2, i32 7, i32 3>940 ret <8 x i16> %a941}942 943define <8 x i32> @unary_interleave_v8i32(<8 x i32> %x) {944; V128-LABEL: unary_interleave_v8i32:945; V128: # %bb.0:946; V128-NEXT: vsetivli zero, 4, e32, m2, ta, ma947; V128-NEXT: vslidedown.vi v12, v8, 4948; V128-NEXT: vsetivli zero, 4, e32, m1, ta, ma949; V128-NEXT: vwaddu.vv v10, v8, v12950; V128-NEXT: li a0, -1951; V128-NEXT: vwmaccu.vx v10, a0, v12952; V128-NEXT: vmv2r.v v8, v10953; V128-NEXT: ret954;955; V512-LABEL: unary_interleave_v8i32:956; V512: # %bb.0:957; V512-NEXT: vsetivli zero, 4, e32, mf2, ta, ma958; V512-NEXT: vslidedown.vi v10, v8, 4959; V512-NEXT: vwaddu.vv v9, v8, v10960; V512-NEXT: li a0, -1961; V512-NEXT: vwmaccu.vx v9, a0, v10962; V512-NEXT: vmv1r.v v8, v9963; V512-NEXT: ret964;965; ZIP-LABEL: unary_interleave_v8i32:966; ZIP: # %bb.0:967; ZIP-NEXT: vsetivli zero, 4, e32, m2, ta, ma968; ZIP-NEXT: vslidedown.vi v12, v8, 4969; ZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma970; ZIP-NEXT: ri.vzip2a.vv v10, v8, v12971; ZIP-NEXT: vmv.v.v v8, v10972; ZIP-NEXT: ret973 %a = shufflevector <8 x i32> %x, <8 x i32> poison, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>974 ret <8 x i32> %a975}976 977; This interleaves the first 2 elements of a vector in opposite order. With978; undefs for the remaining elements. We use to miscompile this.979define <4 x i8> @unary_interleave_10uu_v4i8(<4 x i8> %x) {980; CHECK-LABEL: unary_interleave_10uu_v4i8:981; CHECK: # %bb.0:982; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma983; CHECK-NEXT: vsrl.vi v9, v8, 8984; CHECK-NEXT: vsll.vi v8, v8, 8985; CHECK-NEXT: vor.vv v8, v8, v9986; CHECK-NEXT: ret987;988; ZIP-LABEL: unary_interleave_10uu_v4i8:989; ZIP: # %bb.0:990; ZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma991; ZIP-NEXT: vsrl.vi v9, v8, 8992; ZIP-NEXT: vsll.vi v8, v8, 8993; ZIP-NEXT: vor.vv v8, v8, v9994; ZIP-NEXT: ret995 %a = shufflevector <4 x i8> %x, <4 x i8> poison, <4 x i32> <i32 1, i32 0, i32 poison, i32 poison>996 ret <4 x i8> %a997}998 999define <16 x i16> @interleave_slp(<8 x i16> %v0, <8 x i16> %v1) {1000; V128-LABEL: interleave_slp:1001; V128: # %bb.0: # %entry1002; V128-NEXT: vsetivli zero, 8, e16, m1, ta, ma1003; V128-NEXT: vmv1r.v v10, v91004; V128-NEXT: vmv1r.v v11, v81005; V128-NEXT: vwaddu.vv v8, v11, v101006; V128-NEXT: li a0, -11007; V128-NEXT: vwmaccu.vx v8, a0, v101008; V128-NEXT: ret1009;1010; V512-LABEL: interleave_slp:1011; V512: # %bb.0: # %entry1012; V512-NEXT: vsetivli zero, 8, e16, mf4, ta, ma1013; V512-NEXT: vwaddu.vv v10, v8, v91014; V512-NEXT: li a0, -11015; V512-NEXT: vwmaccu.vx v10, a0, v91016; V512-NEXT: vmv1r.v v8, v101017; V512-NEXT: ret1018;1019; ZIP-LABEL: interleave_slp:1020; ZIP: # %bb.0: # %entry1021; ZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma1022; ZIP-NEXT: vmv1r.v v12, v91023; ZIP-NEXT: ri.vzip2a.vv v10, v8, v121024; ZIP-NEXT: vmv.v.v v8, v101025; ZIP-NEXT: ret1026entry:1027 %v2 = shufflevector <8 x i16> %v0, <8 x i16> poison, <16 x i32> <i32 0, i32 poison, i32 1, i32 poison, i32 2, i32 poison, i32 3, i32 poison, i32 4, i32 poison, i32 5, i32 poison, i32 6, i32 poison, i32 7, i32 poison>1028 %v3 = shufflevector <8 x i16> %v1, <8 x i16> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>1029 %v4 = shufflevector <16 x i16> %v2, <16 x i16> %v3, <16 x i32> <i32 0, i32 16, i32 2, i32 17, i32 4, i32 18, i32 6, i32 19, i32 8, i32 20, i32 10, i32 21, i32 12, i32 22, i32 14, i32 23>1030 ret <16 x i16> %v41031}1032 1033;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:1034; RV32-V128: {{.*}}1035; RV32-ZIP: {{.*}}1036; RV64-V128: {{.*}}1037; RV64-ZIP: {{.*}}1038