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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,NO-ZVBB,RV323; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,NO-ZVBB,RV644; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zvfh,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVBB,RV32-ZVBB5; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zvfh,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVBB,RV64-ZVBB6 7define <2 x i1> @reverse_v2i1(<2 x i1> %a) {8; NO-ZVBB-LABEL: reverse_v2i1:9; NO-ZVBB: # %bb.0:10; NO-ZVBB-NEXT: vsetivli zero, 2, e8, mf8, ta, ma11; NO-ZVBB-NEXT: vmv.v.i v8, 012; NO-ZVBB-NEXT: vmerge.vim v8, v8, 1, v013; NO-ZVBB-NEXT: vslidedown.vi v9, v8, 114; NO-ZVBB-NEXT: vslideup.vi v9, v8, 115; NO-ZVBB-NEXT: vmsne.vi v0, v9, 016; NO-ZVBB-NEXT: ret17;18; ZVBB-LABEL: reverse_v2i1:19; ZVBB: # %bb.0:20; ZVBB-NEXT: vsetivli zero, 1, e8, mf8, ta, ma21; ZVBB-NEXT: vbrev.v v8, v022; ZVBB-NEXT: vsrl.vi v0, v8, 623; ZVBB-NEXT: ret24 %res = shufflevector <2 x i1> %a, <2 x i1> poison, <2 x i32> <i32 1, i32 0>25 ret <2 x i1> %res26}27 28define <4 x i1> @reverse_v4i1(<4 x i1> %a) {29; NO-ZVBB-LABEL: reverse_v4i1:30; NO-ZVBB: # %bb.0:31; NO-ZVBB-NEXT: vsetivli zero, 4, e8, mf4, ta, ma32; NO-ZVBB-NEXT: vmv.v.i v8, 033; NO-ZVBB-NEXT: vmerge.vim v8, v8, 1, v034; NO-ZVBB-NEXT: vid.v v935; NO-ZVBB-NEXT: vrsub.vi v9, v9, 336; NO-ZVBB-NEXT: vrgather.vv v10, v8, v937; NO-ZVBB-NEXT: vmsne.vi v0, v10, 038; NO-ZVBB-NEXT: ret39;40; ZVBB-LABEL: reverse_v4i1:41; ZVBB: # %bb.0:42; ZVBB-NEXT: vsetivli zero, 1, e8, mf8, ta, ma43; ZVBB-NEXT: vbrev.v v8, v044; ZVBB-NEXT: vsrl.vi v0, v8, 445; ZVBB-NEXT: ret46 %res = shufflevector <4 x i1> %a, <4 x i1> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>47 ret <4 x i1> %res48}49 50define <8 x i1> @reverse_v8i1(<8 x i1> %a) {51; NO-ZVBB-LABEL: reverse_v8i1:52; NO-ZVBB: # %bb.0:53; NO-ZVBB-NEXT: vsetivli zero, 8, e8, mf2, ta, ma54; NO-ZVBB-NEXT: vmv.v.i v8, 055; NO-ZVBB-NEXT: vmerge.vim v8, v8, 1, v056; NO-ZVBB-NEXT: vid.v v957; NO-ZVBB-NEXT: vrsub.vi v9, v9, 758; NO-ZVBB-NEXT: vrgather.vv v10, v8, v959; NO-ZVBB-NEXT: vmsne.vi v0, v10, 060; NO-ZVBB-NEXT: ret61;62; ZVBB-LABEL: reverse_v8i1:63; ZVBB: # %bb.0:64; ZVBB-NEXT: vsetivli zero, 1, e8, mf8, ta, ma65; ZVBB-NEXT: vbrev.v v0, v066; ZVBB-NEXT: ret67 %res = shufflevector <8 x i1> %a, <8 x i1> poison, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>68 ret <8 x i1> %res69}70 71define <16 x i1> @reverse_v16i1(<16 x i1> %a) {72; NO-ZVBB-LABEL: reverse_v16i1:73; NO-ZVBB: # %bb.0:74; NO-ZVBB-NEXT: vsetivli zero, 16, e8, m1, ta, ma75; NO-ZVBB-NEXT: vmv.v.i v8, 076; NO-ZVBB-NEXT: vmerge.vim v8, v8, 1, v077; NO-ZVBB-NEXT: vid.v v978; NO-ZVBB-NEXT: vrsub.vi v9, v9, 1579; NO-ZVBB-NEXT: vrgather.vv v10, v8, v980; NO-ZVBB-NEXT: vmsne.vi v0, v10, 081; NO-ZVBB-NEXT: ret82;83; ZVBB-LABEL: reverse_v16i1:84; ZVBB: # %bb.0:85; ZVBB-NEXT: vsetivli zero, 1, e16, mf4, ta, ma86; ZVBB-NEXT: vbrev.v v0, v087; ZVBB-NEXT: ret88 %res = shufflevector <16 x i1> %a, <16 x i1> poison, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>89 ret <16 x i1> %res90}91 92define <32 x i1> @reverse_v32i1(<32 x i1> %a) {93; NO-ZVBB-LABEL: reverse_v32i1:94; NO-ZVBB: # %bb.0:95; NO-ZVBB-NEXT: li a0, 3296; NO-ZVBB-NEXT: csrr a1, vlenb97; NO-ZVBB-NEXT: vsetvli a2, zero, e16, m2, ta, ma98; NO-ZVBB-NEXT: vid.v v899; NO-ZVBB-NEXT: vsetvli zero, a0, e8, m2, ta, ma100; NO-ZVBB-NEXT: vmv.v.i v10, 0101; NO-ZVBB-NEXT: addi a2, a1, -1102; NO-ZVBB-NEXT: slli a1, a1, 1103; NO-ZVBB-NEXT: vmerge.vim v10, v10, 1, v0104; NO-ZVBB-NEXT: vsetvli a3, zero, e16, m2, ta, ma105; NO-ZVBB-NEXT: vrsub.vx v8, v8, a2106; NO-ZVBB-NEXT: vsetvli zero, zero, e8, m1, ta, ma107; NO-ZVBB-NEXT: vrgatherei16.vv v13, v10, v8108; NO-ZVBB-NEXT: vrgatherei16.vv v12, v11, v8109; NO-ZVBB-NEXT: addi a1, a1, -32110; NO-ZVBB-NEXT: vsetvli zero, a0, e8, m2, ta, ma111; NO-ZVBB-NEXT: vslidedown.vx v8, v12, a1112; NO-ZVBB-NEXT: vmsne.vi v0, v8, 0113; NO-ZVBB-NEXT: ret114;115; ZVBB-LABEL: reverse_v32i1:116; ZVBB: # %bb.0:117; ZVBB-NEXT: vsetivli zero, 1, e32, mf2, ta, ma118; ZVBB-NEXT: vbrev.v v0, v0119; ZVBB-NEXT: ret120 %res = shufflevector <32 x i1> %a, <32 x i1> poison, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>121 ret <32 x i1> %res122}123 124define <64 x i1> @reverse_v64i1(<64 x i1> %a) {125; NO-ZVBB-LABEL: reverse_v64i1:126; NO-ZVBB: # %bb.0:127; NO-ZVBB-NEXT: li a0, 64128; NO-ZVBB-NEXT: csrr a1, vlenb129; NO-ZVBB-NEXT: vsetvli a2, zero, e16, m2, ta, ma130; NO-ZVBB-NEXT: vid.v v12131; NO-ZVBB-NEXT: vsetvli zero, a0, e8, m4, ta, ma132; NO-ZVBB-NEXT: vmv.v.i v8, 0133; NO-ZVBB-NEXT: addi a2, a1, -1134; NO-ZVBB-NEXT: slli a1, a1, 2135; NO-ZVBB-NEXT: vmerge.vim v8, v8, 1, v0136; NO-ZVBB-NEXT: vsetvli a3, zero, e16, m2, ta, ma137; NO-ZVBB-NEXT: vrsub.vx v16, v12, a2138; NO-ZVBB-NEXT: vsetvli zero, zero, e8, m1, ta, ma139; NO-ZVBB-NEXT: vrgatherei16.vv v15, v8, v16140; NO-ZVBB-NEXT: vrgatherei16.vv v14, v9, v16141; NO-ZVBB-NEXT: vrgatherei16.vv v13, v10, v16142; NO-ZVBB-NEXT: vrgatherei16.vv v12, v11, v16143; NO-ZVBB-NEXT: addi a1, a1, -64144; NO-ZVBB-NEXT: vsetvli zero, a0, e8, m4, ta, ma145; NO-ZVBB-NEXT: vslidedown.vx v8, v12, a1146; NO-ZVBB-NEXT: vmsne.vi v0, v8, 0147; NO-ZVBB-NEXT: ret148;149; ZVBB-LABEL: reverse_v64i1:150; ZVBB: # %bb.0:151; ZVBB-NEXT: vsetivli zero, 1, e64, m1, ta, ma152; ZVBB-NEXT: vbrev.v v0, v0153; ZVBB-NEXT: ret154 %res = shufflevector <64 x i1> %a, <64 x i1> poison, <64 x i32> <i32 63, i32 62, i32 61, i32 60, i32 59, i32 58, i32 57, i32 56, i32 55, i32 54, i32 53, i32 52, i32 51, i32 50, i32 49, i32 48, i32 47, i32 46, i32 45, i32 44, i32 43, i32 42, i32 41, i32 40, i32 39, i32 38, i32 37, i32 36, i32 35, i32 34, i32 33, i32 32, i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>155 ret <64 x i1> %res156}157 158define <128 x i1> @reverse_v128i1(<128 x i1> %a) {159; CHECK-LABEL: reverse_v128i1:160; CHECK: # %bb.0:161; CHECK-NEXT: li a0, 128162; CHECK-NEXT: csrr a1, vlenb163; CHECK-NEXT: vsetvli a2, zero, e16, m2, ta, ma164; CHECK-NEXT: vid.v v24165; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma166; CHECK-NEXT: vmv.v.i v8, 0167; CHECK-NEXT: addi a2, a1, -1168; CHECK-NEXT: slli a1, a1, 3169; CHECK-NEXT: vmerge.vim v16, v8, 1, v0170; CHECK-NEXT: vsetvli a3, zero, e16, m2, ta, ma171; CHECK-NEXT: vrsub.vx v24, v24, a2172; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma173; CHECK-NEXT: vrgatherei16.vv v15, v16, v24174; CHECK-NEXT: vrgatherei16.vv v14, v17, v24175; CHECK-NEXT: vrgatherei16.vv v13, v18, v24176; CHECK-NEXT: vrgatherei16.vv v12, v19, v24177; CHECK-NEXT: vrgatherei16.vv v11, v20, v24178; CHECK-NEXT: vrgatherei16.vv v10, v21, v24179; CHECK-NEXT: vrgatherei16.vv v9, v22, v24180; CHECK-NEXT: vrgatherei16.vv v8, v23, v24181; CHECK-NEXT: addi a1, a1, -128182; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma183; CHECK-NEXT: vslidedown.vx v8, v8, a1184; CHECK-NEXT: vmsne.vi v0, v8, 0185; CHECK-NEXT: ret186 %res = shufflevector <128 x i1> %a, <128 x i1> poison, <128 x i32> <i32 127, i32 126, i32 125, i32 124, i32 123, i32 122, i32 121, i32 120, i32 119, i32 118, i32 117, i32 116, i32 115, i32 114, i32 113, i32 112, i32 111, i32 110, i32 109, i32 108, i32 107, i32 106, i32 105, i32 104, i32 103, i32 102, i32 101, i32 100, i32 99, i32 98, i32 97, i32 96, i32 95, i32 94, i32 93, i32 92, i32 91, i32 90, i32 89, i32 88, i32 87, i32 86, i32 85, i32 84, i32 83, i32 82, i32 81, i32 80, i32 79, i32 78, i32 77, i32 76, i32 75, i32 74, i32 73, i32 72, i32 71, i32 70, i32 69, i32 68, i32 67, i32 66, i32 65, i32 64, i32 63, i32 62, i32 61, i32 60, i32 59, i32 58, i32 57, i32 56, i32 55, i32 54, i32 53, i32 52, i32 51, i32 50, i32 49, i32 48, i32 47, i32 46, i32 45, i32 44, i32 43, i32 42, i32 41, i32 40, i32 39, i32 38, i32 37, i32 36, i32 35, i32 34, i32 33, i32 32, i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>187 ret <128 x i1> %res188}189 190define <1 x i8> @reverse_v1i8(<1 x i8> %a) {191; CHECK-LABEL: reverse_v1i8:192; CHECK: # %bb.0:193; CHECK-NEXT: ret194 %res = shufflevector <1 x i8> %a, <1 x i8> poison, <1 x i32> <i32 0>195 ret <1 x i8> %res196}197 198define <2 x i8> @reverse_v2i8(<2 x i8> %a) {199; NO-ZVBB-LABEL: reverse_v2i8:200; NO-ZVBB: # %bb.0:201; NO-ZVBB-NEXT: vsetivli zero, 2, e8, mf8, ta, ma202; NO-ZVBB-NEXT: vslidedown.vi v9, v8, 1203; NO-ZVBB-NEXT: vslideup.vi v9, v8, 1204; NO-ZVBB-NEXT: vmv1r.v v8, v9205; NO-ZVBB-NEXT: ret206;207; ZVBB-LABEL: reverse_v2i8:208; ZVBB: # %bb.0:209; ZVBB-NEXT: vsetivli zero, 1, e16, mf4, ta, ma210; ZVBB-NEXT: vrev8.v v8, v8211; ZVBB-NEXT: ret212 %res = shufflevector <2 x i8> %a, <2 x i8> poison, <2 x i32> <i32 1, i32 0>213 ret <2 x i8> %res214}215 216define <4 x i8> @reverse_v4i8(<4 x i8> %a) {217; CHECK-LABEL: reverse_v4i8:218; CHECK: # %bb.0:219; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma220; CHECK-NEXT: vid.v v9221; CHECK-NEXT: vrsub.vi v10, v9, 3222; CHECK-NEXT: vrgather.vv v9, v8, v10223; CHECK-NEXT: vmv1r.v v8, v9224; CHECK-NEXT: ret225 %res = shufflevector <4 x i8> %a, <4 x i8> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>226 ret <4 x i8> %res227}228 229define <8 x i8> @reverse_v8i8(<8 x i8> %a) {230; CHECK-LABEL: reverse_v8i8:231; CHECK: # %bb.0:232; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma233; CHECK-NEXT: vid.v v9234; CHECK-NEXT: vrsub.vi v10, v9, 7235; CHECK-NEXT: vrgather.vv v9, v8, v10236; CHECK-NEXT: vmv1r.v v8, v9237; CHECK-NEXT: ret238 %res = shufflevector <8 x i8> %a, <8 x i8> poison, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>239 ret <8 x i8> %res240}241 242define <16 x i8> @reverse_v16i8(<16 x i8> %a) {243; CHECK-LABEL: reverse_v16i8:244; CHECK: # %bb.0:245; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma246; CHECK-NEXT: vid.v v9247; CHECK-NEXT: vrsub.vi v10, v9, 15248; CHECK-NEXT: vrgather.vv v9, v8, v10249; CHECK-NEXT: vmv.v.v v8, v9250; CHECK-NEXT: ret251 %res = shufflevector <16 x i8> %a, <16 x i8> poison, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>252 ret <16 x i8> %res253}254 255define <32 x i8> @reverse_v32i8(<32 x i8> %a) {256; CHECK-LABEL: reverse_v32i8:257; CHECK: # %bb.0:258; CHECK-NEXT: csrr a0, vlenb259; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma260; CHECK-NEXT: vid.v v10261; CHECK-NEXT: addi a1, a0, -1262; CHECK-NEXT: slli a0, a0, 1263; CHECK-NEXT: vrsub.vx v10, v10, a1264; CHECK-NEXT: addi a0, a0, -32265; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma266; CHECK-NEXT: vrgatherei16.vv v13, v8, v10267; CHECK-NEXT: vrgatherei16.vv v12, v9, v10268; CHECK-NEXT: li a1, 32269; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma270; CHECK-NEXT: vslidedown.vx v8, v12, a0271; CHECK-NEXT: ret272 %res = shufflevector <32 x i8> %a, <32 x i8> poison, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>273 ret <32 x i8> %res274}275 276define <64 x i8> @reverse_v64i8(<64 x i8> %a) {277; CHECK-LABEL: reverse_v64i8:278; CHECK: # %bb.0:279; CHECK-NEXT: csrr a0, vlenb280; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma281; CHECK-NEXT: vid.v v12282; CHECK-NEXT: addi a1, a0, -1283; CHECK-NEXT: slli a0, a0, 2284; CHECK-NEXT: vrsub.vx v16, v12, a1285; CHECK-NEXT: addi a0, a0, -64286; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma287; CHECK-NEXT: vrgatherei16.vv v15, v8, v16288; CHECK-NEXT: vrgatherei16.vv v14, v9, v16289; CHECK-NEXT: vrgatherei16.vv v13, v10, v16290; CHECK-NEXT: vrgatherei16.vv v12, v11, v16291; CHECK-NEXT: li a1, 64292; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma293; CHECK-NEXT: vslidedown.vx v8, v12, a0294; CHECK-NEXT: ret295 %res = shufflevector <64 x i8> %a, <64 x i8> poison, <64 x i32> <i32 63, i32 62, i32 61, i32 60, i32 59, i32 58, i32 57, i32 56, i32 55, i32 54, i32 53, i32 52, i32 51, i32 50, i32 49, i32 48, i32 47, i32 46, i32 45, i32 44, i32 43, i32 42, i32 41, i32 40, i32 39, i32 38, i32 37, i32 36, i32 35, i32 34, i32 33, i32 32, i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>296 ret <64 x i8> %res297}298 299define <1 x i16> @reverse_v1i16(<1 x i16> %a) {300; CHECK-LABEL: reverse_v1i16:301; CHECK: # %bb.0:302; CHECK-NEXT: ret303 %res = shufflevector <1 x i16> %a, <1 x i16> poison, <1 x i32> <i32 0>304 ret <1 x i16> %res305}306 307define <2 x i16> @reverse_v2i16(<2 x i16> %a) {308; NO-ZVBB-LABEL: reverse_v2i16:309; NO-ZVBB: # %bb.0:310; NO-ZVBB-NEXT: vsetivli zero, 2, e16, mf4, ta, ma311; NO-ZVBB-NEXT: vslidedown.vi v9, v8, 1312; NO-ZVBB-NEXT: vslideup.vi v9, v8, 1313; NO-ZVBB-NEXT: vmv1r.v v8, v9314; NO-ZVBB-NEXT: ret315;316; ZVBB-LABEL: reverse_v2i16:317; ZVBB: # %bb.0:318; ZVBB-NEXT: vsetivli zero, 1, e32, mf2, ta, ma319; ZVBB-NEXT: vror.vi v8, v8, 16320; ZVBB-NEXT: ret321 %res = shufflevector <2 x i16> %a, <2 x i16> poison, <2 x i32> <i32 1, i32 0>322 ret <2 x i16> %res323}324 325define <4 x i16> @reverse_v4i16(<4 x i16> %a) {326; CHECK-LABEL: reverse_v4i16:327; CHECK: # %bb.0:328; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma329; CHECK-NEXT: vid.v v9330; CHECK-NEXT: vrsub.vi v10, v9, 3331; CHECK-NEXT: vrgather.vv v9, v8, v10332; CHECK-NEXT: vmv1r.v v8, v9333; CHECK-NEXT: ret334 %res = shufflevector <4 x i16> %a, <4 x i16> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>335 ret <4 x i16> %res336}337 338define <8 x i16> @reverse_v8i16(<8 x i16> %a) {339; CHECK-LABEL: reverse_v8i16:340; CHECK: # %bb.0:341; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma342; CHECK-NEXT: vid.v v9343; CHECK-NEXT: vrsub.vi v10, v9, 7344; CHECK-NEXT: vrgather.vv v9, v8, v10345; CHECK-NEXT: vmv.v.v v8, v9346; CHECK-NEXT: ret347 %res = shufflevector <8 x i16> %a, <8 x i16> poison, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>348 ret <8 x i16> %res349}350 351define <16 x i16> @reverse_v16i16(<16 x i16> %a) {352; CHECK-LABEL: reverse_v16i16:353; CHECK: # %bb.0:354; CHECK-NEXT: csrr a0, vlenb355; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma356; CHECK-NEXT: vid.v v10357; CHECK-NEXT: srli a1, a0, 1358; CHECK-NEXT: addi a1, a1, -1359; CHECK-NEXT: vrsub.vx v12, v10, a1360; CHECK-NEXT: vrgather.vv v11, v8, v12361; CHECK-NEXT: vrgather.vv v10, v9, v12362; CHECK-NEXT: addi a0, a0, -16363; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma364; CHECK-NEXT: vslidedown.vx v8, v10, a0365; CHECK-NEXT: ret366 %res = shufflevector <16 x i16> %a, <16 x i16> poison, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>367 ret <16 x i16> %res368}369 370define <32 x i16> @reverse_v32i16(<32 x i16> %a) {371; CHECK-LABEL: reverse_v32i16:372; CHECK: # %bb.0:373; CHECK-NEXT: csrr a0, vlenb374; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma375; CHECK-NEXT: vid.v v12376; CHECK-NEXT: srli a1, a0, 1377; CHECK-NEXT: slli a0, a0, 1378; CHECK-NEXT: addi a1, a1, -1379; CHECK-NEXT: addi a0, a0, -32380; CHECK-NEXT: vrsub.vx v16, v12, a1381; CHECK-NEXT: vrgather.vv v15, v8, v16382; CHECK-NEXT: vrgather.vv v14, v9, v16383; CHECK-NEXT: vrgather.vv v13, v10, v16384; CHECK-NEXT: vrgather.vv v12, v11, v16385; CHECK-NEXT: li a1, 32386; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma387; CHECK-NEXT: vslidedown.vx v8, v12, a0388; CHECK-NEXT: ret389 %res = shufflevector <32 x i16> %a, <32 x i16> poison, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>390 ret <32 x i16> %res391}392 393define <1 x i32> @reverse_v1i32(<1 x i32> %a) {394; CHECK-LABEL: reverse_v1i32:395; CHECK: # %bb.0:396; CHECK-NEXT: ret397 %res = shufflevector <1 x i32> %a, <1 x i32> poison, <1 x i32> <i32 0>398 ret <1 x i32> %res399}400 401define <2 x i32> @reverse_v2i32(<2 x i32> %a) {402; NO-ZVBB-LABEL: reverse_v2i32:403; NO-ZVBB: # %bb.0:404; NO-ZVBB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma405; NO-ZVBB-NEXT: vslidedown.vi v9, v8, 1406; NO-ZVBB-NEXT: vslideup.vi v9, v8, 1407; NO-ZVBB-NEXT: vmv1r.v v8, v9408; NO-ZVBB-NEXT: ret409;410; ZVBB-LABEL: reverse_v2i32:411; ZVBB: # %bb.0:412; ZVBB-NEXT: vsetivli zero, 1, e64, m1, ta, ma413; ZVBB-NEXT: vror.vi v8, v8, 32414; ZVBB-NEXT: ret415 %res = shufflevector <2 x i32> %a, <2 x i32> poison, <2 x i32> <i32 1, i32 0>416 ret <2 x i32> %res417}418 419define <4 x i32> @reverse_v4i32(<4 x i32> %a) {420; CHECK-LABEL: reverse_v4i32:421; CHECK: # %bb.0:422; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma423; CHECK-NEXT: vid.v v9424; CHECK-NEXT: vrsub.vi v10, v9, 3425; CHECK-NEXT: vrgather.vv v9, v8, v10426; CHECK-NEXT: vmv.v.v v8, v9427; CHECK-NEXT: ret428 %res = shufflevector <4 x i32> %a, <4 x i32> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>429 ret <4 x i32> %res430}431 432define <8 x i32> @reverse_v8i32(<8 x i32> %a) {433; CHECK-LABEL: reverse_v8i32:434; CHECK: # %bb.0:435; CHECK-NEXT: csrr a0, vlenb436; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma437; CHECK-NEXT: vid.v v10438; CHECK-NEXT: srli a1, a0, 2439; CHECK-NEXT: srli a0, a0, 1440; CHECK-NEXT: addi a1, a1, -1441; CHECK-NEXT: vrsub.vx v12, v10, a1442; CHECK-NEXT: vrgather.vv v11, v8, v12443; CHECK-NEXT: vrgather.vv v10, v9, v12444; CHECK-NEXT: addi a0, a0, -8445; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma446; CHECK-NEXT: vslidedown.vx v8, v10, a0447; CHECK-NEXT: ret448 %res = shufflevector <8 x i32> %a, <8 x i32> poison, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>449 ret <8 x i32> %res450}451 452define <16 x i32> @reverse_v16i32(<16 x i32> %a) {453; CHECK-LABEL: reverse_v16i32:454; CHECK: # %bb.0:455; CHECK-NEXT: csrr a0, vlenb456; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma457; CHECK-NEXT: vid.v v12458; CHECK-NEXT: srli a1, a0, 2459; CHECK-NEXT: addi a1, a1, -1460; CHECK-NEXT: vrsub.vx v16, v12, a1461; CHECK-NEXT: vrgather.vv v15, v8, v16462; CHECK-NEXT: vrgather.vv v14, v9, v16463; CHECK-NEXT: vrgather.vv v13, v10, v16464; CHECK-NEXT: vrgather.vv v12, v11, v16465; CHECK-NEXT: addi a0, a0, -16466; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma467; CHECK-NEXT: vslidedown.vx v8, v12, a0468; CHECK-NEXT: ret469 %res = shufflevector <16 x i32> %a, <16 x i32> poison, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>470 ret <16 x i32> %res471}472 473define <1 x i64> @reverse_v1i64(<1 x i64> %a) {474; CHECK-LABEL: reverse_v1i64:475; CHECK: # %bb.0:476; CHECK-NEXT: ret477 %res = shufflevector <1 x i64> %a, <1 x i64> poison, <1 x i32> <i32 0>478 ret <1 x i64> %res479}480 481define <2 x i64> @reverse_v2i64(<2 x i64> %a) {482; CHECK-LABEL: reverse_v2i64:483; CHECK: # %bb.0:484; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma485; CHECK-NEXT: vslidedown.vi v9, v8, 1486; CHECK-NEXT: vslideup.vi v9, v8, 1487; CHECK-NEXT: vmv.v.v v8, v9488; CHECK-NEXT: ret489 %res = shufflevector <2 x i64> %a, <2 x i64> poison, <2 x i32> <i32 1, i32 0>490 ret <2 x i64> %res491}492 493define <4 x i64> @reverse_v4i64(<4 x i64> %a) {494; CHECK-LABEL: reverse_v4i64:495; CHECK: # %bb.0:496; CHECK-NEXT: csrr a0, vlenb497; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma498; CHECK-NEXT: vid.v v10499; CHECK-NEXT: srli a1, a0, 3500; CHECK-NEXT: srli a0, a0, 2501; CHECK-NEXT: addi a1, a1, -1502; CHECK-NEXT: vrsub.vx v12, v10, a1503; CHECK-NEXT: vrgather.vv v11, v8, v12504; CHECK-NEXT: vrgather.vv v10, v9, v12505; CHECK-NEXT: addi a0, a0, -4506; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma507; CHECK-NEXT: vslidedown.vx v8, v10, a0508; CHECK-NEXT: ret509 %res = shufflevector <4 x i64> %a, <4 x i64> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>510 ret <4 x i64> %res511}512 513define <8 x i64> @reverse_v8i64(<8 x i64> %a) {514; CHECK-LABEL: reverse_v8i64:515; CHECK: # %bb.0:516; CHECK-NEXT: csrr a0, vlenb517; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma518; CHECK-NEXT: vid.v v12519; CHECK-NEXT: srli a1, a0, 3520; CHECK-NEXT: srli a0, a0, 1521; CHECK-NEXT: addi a1, a1, -1522; CHECK-NEXT: vrsub.vx v16, v12, a1523; CHECK-NEXT: vrgather.vv v15, v8, v16524; CHECK-NEXT: vrgather.vv v14, v9, v16525; CHECK-NEXT: vrgather.vv v13, v10, v16526; CHECK-NEXT: vrgather.vv v12, v11, v16527; CHECK-NEXT: addi a0, a0, -8528; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma529; CHECK-NEXT: vslidedown.vx v8, v12, a0530; CHECK-NEXT: ret531 %res = shufflevector <8 x i64> %a, <8 x i64> poison, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>532 ret <8 x i64> %res533}534 535 536define <1 x half> @reverse_v1f16(<1 x half> %a) {537; CHECK-LABEL: reverse_v1f16:538; CHECK: # %bb.0:539; CHECK-NEXT: ret540 %res = shufflevector <1 x half> %a, <1 x half> poison, <1 x i32> <i32 0>541 ret <1 x half> %res542}543 544define <2 x half> @reverse_v2f16(<2 x half> %a) {545; NO-ZVBB-LABEL: reverse_v2f16:546; NO-ZVBB: # %bb.0:547; NO-ZVBB-NEXT: vsetivli zero, 2, e16, mf4, ta, ma548; NO-ZVBB-NEXT: vslidedown.vi v9, v8, 1549; NO-ZVBB-NEXT: vslideup.vi v9, v8, 1550; NO-ZVBB-NEXT: vmv1r.v v8, v9551; NO-ZVBB-NEXT: ret552;553; ZVBB-LABEL: reverse_v2f16:554; ZVBB: # %bb.0:555; ZVBB-NEXT: vsetivli zero, 1, e32, mf2, ta, ma556; ZVBB-NEXT: vror.vi v8, v8, 16557; ZVBB-NEXT: ret558 %res = shufflevector <2 x half> %a, <2 x half> poison, <2 x i32> <i32 1, i32 0>559 ret <2 x half> %res560}561 562define <4 x half> @reverse_v4f16(<4 x half> %a) {563; CHECK-LABEL: reverse_v4f16:564; CHECK: # %bb.0:565; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma566; CHECK-NEXT: vid.v v9567; CHECK-NEXT: vrsub.vi v10, v9, 3568; CHECK-NEXT: vrgather.vv v9, v8, v10569; CHECK-NEXT: vmv1r.v v8, v9570; CHECK-NEXT: ret571 %res = shufflevector <4 x half> %a, <4 x half> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>572 ret <4 x half> %res573}574 575define <8 x half> @reverse_v8f16(<8 x half> %a) {576; CHECK-LABEL: reverse_v8f16:577; CHECK: # %bb.0:578; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma579; CHECK-NEXT: vid.v v9580; CHECK-NEXT: vrsub.vi v10, v9, 7581; CHECK-NEXT: vrgather.vv v9, v8, v10582; CHECK-NEXT: vmv.v.v v8, v9583; CHECK-NEXT: ret584 %res = shufflevector <8 x half> %a, <8 x half> poison, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>585 ret <8 x half> %res586}587 588define <16 x half> @reverse_v16f16(<16 x half> %a) {589; CHECK-LABEL: reverse_v16f16:590; CHECK: # %bb.0:591; CHECK-NEXT: csrr a0, vlenb592; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma593; CHECK-NEXT: vid.v v10594; CHECK-NEXT: srli a1, a0, 1595; CHECK-NEXT: addi a1, a1, -1596; CHECK-NEXT: vrsub.vx v12, v10, a1597; CHECK-NEXT: vrgather.vv v11, v8, v12598; CHECK-NEXT: vrgather.vv v10, v9, v12599; CHECK-NEXT: addi a0, a0, -16600; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma601; CHECK-NEXT: vslidedown.vx v8, v10, a0602; CHECK-NEXT: ret603 %res = shufflevector <16 x half> %a, <16 x half> poison, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>604 ret <16 x half> %res605}606 607define <32 x half> @reverse_v32f16(<32 x half> %a) {608; CHECK-LABEL: reverse_v32f16:609; CHECK: # %bb.0:610; CHECK-NEXT: csrr a0, vlenb611; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma612; CHECK-NEXT: vid.v v12613; CHECK-NEXT: srli a1, a0, 1614; CHECK-NEXT: slli a0, a0, 1615; CHECK-NEXT: addi a1, a1, -1616; CHECK-NEXT: addi a0, a0, -32617; CHECK-NEXT: vrsub.vx v16, v12, a1618; CHECK-NEXT: vrgather.vv v15, v8, v16619; CHECK-NEXT: vrgather.vv v14, v9, v16620; CHECK-NEXT: vrgather.vv v13, v10, v16621; CHECK-NEXT: vrgather.vv v12, v11, v16622; CHECK-NEXT: li a1, 32623; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma624; CHECK-NEXT: vslidedown.vx v8, v12, a0625; CHECK-NEXT: ret626 %res = shufflevector <32 x half> %a, <32 x half> poison, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>627 ret <32 x half> %res628}629 630define <1 x float> @reverse_v1f32(<1 x float> %a) {631; CHECK-LABEL: reverse_v1f32:632; CHECK: # %bb.0:633; CHECK-NEXT: ret634 %res = shufflevector <1 x float> %a, <1 x float> poison, <1 x i32> <i32 0>635 ret <1 x float> %res636}637 638define <2 x float> @reverse_v2f32(<2 x float> %a) {639; NO-ZVBB-LABEL: reverse_v2f32:640; NO-ZVBB: # %bb.0:641; NO-ZVBB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma642; NO-ZVBB-NEXT: vslidedown.vi v9, v8, 1643; NO-ZVBB-NEXT: vslideup.vi v9, v8, 1644; NO-ZVBB-NEXT: vmv1r.v v8, v9645; NO-ZVBB-NEXT: ret646;647; ZVBB-LABEL: reverse_v2f32:648; ZVBB: # %bb.0:649; ZVBB-NEXT: vsetivli zero, 1, e64, m1, ta, ma650; ZVBB-NEXT: vror.vi v8, v8, 32651; ZVBB-NEXT: ret652 %res = shufflevector <2 x float> %a, <2 x float> poison, <2 x i32> <i32 1, i32 0>653 ret <2 x float> %res654}655 656define <4 x float> @reverse_v4f32(<4 x float> %a) {657; CHECK-LABEL: reverse_v4f32:658; CHECK: # %bb.0:659; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma660; CHECK-NEXT: vid.v v9661; CHECK-NEXT: vrsub.vi v10, v9, 3662; CHECK-NEXT: vrgather.vv v9, v8, v10663; CHECK-NEXT: vmv.v.v v8, v9664; CHECK-NEXT: ret665 %res = shufflevector <4 x float> %a, <4 x float> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>666 ret <4 x float> %res667}668 669define <8 x float> @reverse_v8f32(<8 x float> %a) {670; CHECK-LABEL: reverse_v8f32:671; CHECK: # %bb.0:672; CHECK-NEXT: csrr a0, vlenb673; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma674; CHECK-NEXT: vid.v v10675; CHECK-NEXT: srli a1, a0, 2676; CHECK-NEXT: srli a0, a0, 1677; CHECK-NEXT: addi a1, a1, -1678; CHECK-NEXT: vrsub.vx v12, v10, a1679; CHECK-NEXT: vrgather.vv v11, v8, v12680; CHECK-NEXT: vrgather.vv v10, v9, v12681; CHECK-NEXT: addi a0, a0, -8682; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma683; CHECK-NEXT: vslidedown.vx v8, v10, a0684; CHECK-NEXT: ret685 %res = shufflevector <8 x float> %a, <8 x float> poison, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>686 ret <8 x float> %res687}688 689define <16 x float> @reverse_v16f32(<16 x float> %a) {690; CHECK-LABEL: reverse_v16f32:691; CHECK: # %bb.0:692; CHECK-NEXT: csrr a0, vlenb693; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma694; CHECK-NEXT: vid.v v12695; CHECK-NEXT: srli a1, a0, 2696; CHECK-NEXT: addi a1, a1, -1697; CHECK-NEXT: vrsub.vx v16, v12, a1698; CHECK-NEXT: vrgather.vv v15, v8, v16699; CHECK-NEXT: vrgather.vv v14, v9, v16700; CHECK-NEXT: vrgather.vv v13, v10, v16701; CHECK-NEXT: vrgather.vv v12, v11, v16702; CHECK-NEXT: addi a0, a0, -16703; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma704; CHECK-NEXT: vslidedown.vx v8, v12, a0705; CHECK-NEXT: ret706 %res = shufflevector <16 x float> %a, <16 x float> poison, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>707 ret <16 x float> %res708}709 710define <1 x double> @reverse_v1f64(<1 x double> %a) {711; CHECK-LABEL: reverse_v1f64:712; CHECK: # %bb.0:713; CHECK-NEXT: ret714 %res = shufflevector <1 x double> %a, <1 x double> poison, <1 x i32> <i32 0>715 ret <1 x double> %res716}717 718define <2 x double> @reverse_v2f64(<2 x double> %a) {719; CHECK-LABEL: reverse_v2f64:720; CHECK: # %bb.0:721; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma722; CHECK-NEXT: vslidedown.vi v9, v8, 1723; CHECK-NEXT: vslideup.vi v9, v8, 1724; CHECK-NEXT: vmv.v.v v8, v9725; CHECK-NEXT: ret726 %res = shufflevector <2 x double> %a, <2 x double> poison, <2 x i32> <i32 1, i32 0>727 ret <2 x double> %res728}729 730define <4 x double> @reverse_v4f64(<4 x double> %a) {731; CHECK-LABEL: reverse_v4f64:732; CHECK: # %bb.0:733; CHECK-NEXT: csrr a0, vlenb734; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma735; CHECK-NEXT: vid.v v10736; CHECK-NEXT: srli a1, a0, 3737; CHECK-NEXT: srli a0, a0, 2738; CHECK-NEXT: addi a1, a1, -1739; CHECK-NEXT: vrsub.vx v12, v10, a1740; CHECK-NEXT: vrgather.vv v11, v8, v12741; CHECK-NEXT: vrgather.vv v10, v9, v12742; CHECK-NEXT: addi a0, a0, -4743; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma744; CHECK-NEXT: vslidedown.vx v8, v10, a0745; CHECK-NEXT: ret746 %res = shufflevector <4 x double> %a, <4 x double> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>747 ret <4 x double> %res748}749 750define <8 x double> @reverse_v8f64(<8 x double> %a) {751; CHECK-LABEL: reverse_v8f64:752; CHECK: # %bb.0:753; CHECK-NEXT: csrr a0, vlenb754; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma755; CHECK-NEXT: vid.v v12756; CHECK-NEXT: srli a1, a0, 3757; CHECK-NEXT: srli a0, a0, 1758; CHECK-NEXT: addi a1, a1, -1759; CHECK-NEXT: vrsub.vx v16, v12, a1760; CHECK-NEXT: vrgather.vv v15, v8, v16761; CHECK-NEXT: vrgather.vv v14, v9, v16762; CHECK-NEXT: vrgather.vv v13, v10, v16763; CHECK-NEXT: vrgather.vv v12, v11, v16764; CHECK-NEXT: addi a0, a0, -8765; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma766; CHECK-NEXT: vslidedown.vx v8, v12, a0767; CHECK-NEXT: ret768 %res = shufflevector <8 x double> %a, <8 x double> poison, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>769 ret <8 x double> %res770}771 772 773define <3 x i64> @reverse_v3i64(<3 x i64> %a) {774; CHECK-LABEL: reverse_v3i64:775; CHECK: # %bb.0:776; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma777; CHECK-NEXT: vid.v v10778; CHECK-NEXT: vrsub.vi v12, v10, 2779; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma780; CHECK-NEXT: vrgatherei16.vv v10, v8, v12781; CHECK-NEXT: vmv.v.v v8, v10782; CHECK-NEXT: ret783 %res = shufflevector <3 x i64> %a, <3 x i64> poison, <3 x i32> <i32 2, i32 1, i32 0>784 ret <3 x i64> %res785}786 787define <6 x i64> @reverse_v6i64(<6 x i64> %a) {788; CHECK-LABEL: reverse_v6i64:789; CHECK: # %bb.0:790; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma791; CHECK-NEXT: vid.v v12792; CHECK-NEXT: vrsub.vi v16, v12, 5793; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma794; CHECK-NEXT: vrgatherei16.vv v12, v8, v16795; CHECK-NEXT: vmv.v.v v8, v12796; CHECK-NEXT: ret797 %res = shufflevector <6 x i64> %a, <6 x i64> poison, <6 x i32> <i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>798 ret <6 x i64> %res799}800 801define <12 x i64> @reverse_v12i64(<12 x i64> %a) {802; CHECK-LABEL: reverse_v12i64:803; CHECK: # %bb.0:804; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma805; CHECK-NEXT: vid.v v16806; CHECK-NEXT: vrsub.vi v24, v16, 11807; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma808; CHECK-NEXT: vrgatherei16.vv v16, v8, v24809; CHECK-NEXT: vmv.v.v v8, v16810; CHECK-NEXT: ret811 %res = shufflevector <12 x i64> %a, <12 x i64> poison, <12 x i32> <i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>812 ret <12 x i64> %res813}814 815define <4 x i8> @reverse_v4i8_2(<2 x i8> %a, <2 x i8> %b) {816; NO-ZVBB-LABEL: reverse_v4i8_2:817; NO-ZVBB: # %bb.0:818; NO-ZVBB-NEXT: vsetivli zero, 2, e8, mf8, ta, ma819; NO-ZVBB-NEXT: vslidedown.vi v10, v8, 1820; NO-ZVBB-NEXT: vslideup.vi v10, v8, 1821; NO-ZVBB-NEXT: vslidedown.vi v8, v9, 1822; NO-ZVBB-NEXT: vslideup.vi v8, v9, 1823; NO-ZVBB-NEXT: vsetivli zero, 4, e8, mf4, ta, ma824; NO-ZVBB-NEXT: vslideup.vi v8, v10, 2825; NO-ZVBB-NEXT: ret826;827; ZVBB-LABEL: reverse_v4i8_2:828; ZVBB: # %bb.0:829; ZVBB-NEXT: vsetivli zero, 1, e16, mf4, ta, ma830; ZVBB-NEXT: vrev8.v v10, v8831; ZVBB-NEXT: vrev8.v v8, v9832; ZVBB-NEXT: vsetivli zero, 4, e8, mf4, ta, ma833; ZVBB-NEXT: vslideup.vi v8, v10, 2834; ZVBB-NEXT: ret835 %res = shufflevector <2 x i8> %a, <2 x i8> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0>836 ret <4 x i8> %res837}838 839define <8 x i8> @reverse_v8i8_2(<4 x i8> %a, <4 x i8> %b) {840; CHECK-LABEL: reverse_v8i8_2:841; CHECK: # %bb.0:842; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma843; CHECK-NEXT: vid.v v10844; CHECK-NEXT: vrsub.vi v10, v10, 3845; CHECK-NEXT: vrgather.vv v11, v8, v10846; CHECK-NEXT: vrgather.vv v8, v9, v10847; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma848; CHECK-NEXT: vslideup.vi v8, v11, 4849; CHECK-NEXT: ret850 %res = shufflevector <4 x i8> %a, <4 x i8> %b, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>851 ret <8 x i8> %res852}853 854define <16 x i8> @reverse_v16i8_2(<8 x i8> %a, <8 x i8> %b) {855; CHECK-LABEL: reverse_v16i8_2:856; CHECK: # %bb.0:857; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma858; CHECK-NEXT: vid.v v10859; CHECK-NEXT: vrsub.vi v10, v10, 7860; CHECK-NEXT: vrgather.vv v11, v8, v10861; CHECK-NEXT: vrgather.vv v8, v9, v10862; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma863; CHECK-NEXT: vslideup.vi v8, v11, 8864; CHECK-NEXT: ret865 %res = shufflevector <8 x i8> %a, <8 x i8> %b, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>866 ret <16 x i8> %res867}868 869define <32 x i8> @reverse_v32i8_2(<16 x i8> %a, <16 x i8> %b) {870; CHECK-LABEL: reverse_v32i8_2:871; CHECK: # %bb.0:872; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma873; CHECK-NEXT: vid.v v10874; CHECK-NEXT: vrsub.vi v11, v10, 15875; CHECK-NEXT: vrgather.vv v10, v8, v11876; CHECK-NEXT: vrgather.vv v8, v9, v11877; CHECK-NEXT: li a0, 32878; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma879; CHECK-NEXT: vslideup.vi v8, v10, 16880; CHECK-NEXT: ret881 %res = shufflevector <16 x i8> %a, <16 x i8> %b, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>882 ret <32 x i8> %res883}884 885define <4 x i16> @reverse_v4i16_2(<2 x i16> %a, <2 x i16> %b) {886; NO-ZVBB-LABEL: reverse_v4i16_2:887; NO-ZVBB: # %bb.0:888; NO-ZVBB-NEXT: vsetivli zero, 2, e16, mf4, ta, ma889; NO-ZVBB-NEXT: vslidedown.vi v10, v8, 1890; NO-ZVBB-NEXT: vslideup.vi v10, v8, 1891; NO-ZVBB-NEXT: vslidedown.vi v8, v9, 1892; NO-ZVBB-NEXT: vslideup.vi v8, v9, 1893; NO-ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma894; NO-ZVBB-NEXT: vslideup.vi v8, v10, 2895; NO-ZVBB-NEXT: ret896;897; ZVBB-LABEL: reverse_v4i16_2:898; ZVBB: # %bb.0:899; ZVBB-NEXT: vsetivli zero, 1, e32, mf2, ta, ma900; ZVBB-NEXT: vror.vi v10, v8, 16901; ZVBB-NEXT: vror.vi v8, v9, 16902; ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma903; ZVBB-NEXT: vslideup.vi v8, v10, 2904; ZVBB-NEXT: ret905 %res = shufflevector <2 x i16> %a, <2 x i16> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0>906 ret <4 x i16> %res907}908 909define <8 x i16> @reverse_v8i16_2(<4 x i16> %a, <4 x i16> %b) {910; CHECK-LABEL: reverse_v8i16_2:911; CHECK: # %bb.0:912; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma913; CHECK-NEXT: vid.v v10914; CHECK-NEXT: vrsub.vi v10, v10, 3915; CHECK-NEXT: vrgather.vv v11, v8, v10916; CHECK-NEXT: vrgather.vv v8, v9, v10917; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma918; CHECK-NEXT: vslideup.vi v8, v11, 4919; CHECK-NEXT: ret920 %res = shufflevector <4 x i16> %a, <4 x i16> %b, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>921 ret <8 x i16> %res922}923 924define <16 x i16> @reverse_v16i16_2(<8 x i16> %a, <8 x i16> %b) {925; CHECK-LABEL: reverse_v16i16_2:926; CHECK: # %bb.0:927; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma928; CHECK-NEXT: vid.v v10929; CHECK-NEXT: vrsub.vi v11, v10, 7930; CHECK-NEXT: vrgather.vv v10, v8, v11931; CHECK-NEXT: vrgather.vv v8, v9, v11932; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma933; CHECK-NEXT: vslideup.vi v8, v10, 8934; CHECK-NEXT: ret935 %res = shufflevector <8 x i16> %a, <8 x i16> %b, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>936 ret <16 x i16> %res937}938 939define <32 x i16> @reverse_v32i16_2(<16 x i16> %a, <16 x i16> %b) {940; CHECK-LABEL: reverse_v32i16_2:941; CHECK: # %bb.0:942; CHECK-NEXT: csrr a0, vlenb943; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma944; CHECK-NEXT: vid.v v12945; CHECK-NEXT: srli a1, a0, 1946; CHECK-NEXT: addi a0, a0, -16947; CHECK-NEXT: addi a1, a1, -1948; CHECK-NEXT: vrsub.vx v16, v12, a1949; CHECK-NEXT: vrgather.vv v13, v8, v16950; CHECK-NEXT: vrgather.vv v15, v10, v16951; CHECK-NEXT: vrgather.vv v12, v9, v16952; CHECK-NEXT: vrgather.vv v14, v11, v16953; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma954; CHECK-NEXT: vslidedown.vx v12, v12, a0955; CHECK-NEXT: vslidedown.vx v8, v14, a0956; CHECK-NEXT: li a0, 32957; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma958; CHECK-NEXT: vslideup.vi v8, v12, 16959; CHECK-NEXT: ret960 %res = shufflevector <16 x i16> %a, <16 x i16> %b, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>961 ret <32 x i16> %res962}963 964define <4 x i32> @reverse_v4i32_2(<2 x i32> %a, < 2 x i32> %b) {965; NO-ZVBB-LABEL: reverse_v4i32_2:966; NO-ZVBB: # %bb.0:967; NO-ZVBB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma968; NO-ZVBB-NEXT: vslidedown.vi v10, v8, 1969; NO-ZVBB-NEXT: vslideup.vi v10, v8, 1970; NO-ZVBB-NEXT: vslidedown.vi v8, v9, 1971; NO-ZVBB-NEXT: vslideup.vi v8, v9, 1972; NO-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma973; NO-ZVBB-NEXT: vslideup.vi v8, v10, 2974; NO-ZVBB-NEXT: ret975;976; ZVBB-LABEL: reverse_v4i32_2:977; ZVBB: # %bb.0:978; ZVBB-NEXT: vsetivli zero, 1, e64, m1, ta, ma979; ZVBB-NEXT: vror.vi v10, v8, 32980; ZVBB-NEXT: vror.vi v8, v9, 32981; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma982; ZVBB-NEXT: vslideup.vi v8, v10, 2983; ZVBB-NEXT: ret984 %res = shufflevector <2 x i32> %a, <2 x i32> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0>985 ret <4 x i32> %res986}987 988define <8 x i32> @reverse_v8i32_2(<4 x i32> %a, <4 x i32> %b) {989; CHECK-LABEL: reverse_v8i32_2:990; CHECK: # %bb.0:991; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma992; CHECK-NEXT: vid.v v10993; CHECK-NEXT: vrsub.vi v11, v10, 3994; CHECK-NEXT: vrgather.vv v10, v8, v11995; CHECK-NEXT: vrgather.vv v8, v9, v11996; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma997; CHECK-NEXT: vslideup.vi v8, v10, 4998; CHECK-NEXT: ret999 %res = shufflevector <4 x i32> %a, <4 x i32> %b, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>1000 ret <8 x i32> %res1001}1002 1003define <16 x i32> @reverse_v16i32_2(<8 x i32> %a, <8 x i32> %b) {1004; CHECK-LABEL: reverse_v16i32_2:1005; CHECK: # %bb.0:1006; CHECK-NEXT: csrr a0, vlenb1007; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma1008; CHECK-NEXT: vid.v v121009; CHECK-NEXT: srli a1, a0, 21010; CHECK-NEXT: srli a0, a0, 11011; CHECK-NEXT: addi a1, a1, -11012; CHECK-NEXT: addi a0, a0, -81013; CHECK-NEXT: vrsub.vx v16, v12, a11014; CHECK-NEXT: vrgather.vv v13, v8, v161015; CHECK-NEXT: vrgather.vv v15, v10, v161016; CHECK-NEXT: vrgather.vv v12, v9, v161017; CHECK-NEXT: vrgather.vv v14, v11, v161018; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma1019; CHECK-NEXT: vslidedown.vx v12, v12, a01020; CHECK-NEXT: vslidedown.vx v8, v14, a01021; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma1022; CHECK-NEXT: vslideup.vi v8, v12, 81023; CHECK-NEXT: ret1024 %res = shufflevector <8 x i32> %a, <8 x i32> %b, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>1025 ret <16 x i32> %res1026}1027 1028define <32 x i32> @reverse_v32i32_2(<16 x i32> %a, <16 x i32> %b) {1029; CHECK-LABEL: reverse_v32i32_2:1030; CHECK: # %bb.0:1031; CHECK-NEXT: csrr a0, vlenb1032; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma1033; CHECK-NEXT: vid.v v161034; CHECK-NEXT: srli a1, a0, 21035; CHECK-NEXT: addi a0, a0, -161036; CHECK-NEXT: addi a1, a1, -11037; CHECK-NEXT: vrsub.vx v24, v16, a11038; CHECK-NEXT: vrgather.vv v19, v8, v241039; CHECK-NEXT: vrgather.vv v23, v12, v241040; CHECK-NEXT: vrgather.vv v18, v9, v241041; CHECK-NEXT: vrgather.vv v22, v13, v241042; CHECK-NEXT: vrgather.vv v17, v10, v241043; CHECK-NEXT: vrgather.vv v21, v14, v241044; CHECK-NEXT: vrgather.vv v16, v11, v241045; CHECK-NEXT: vrgather.vv v20, v15, v241046; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma1047; CHECK-NEXT: vslidedown.vx v16, v16, a01048; CHECK-NEXT: vslidedown.vx v8, v20, a01049; CHECK-NEXT: li a0, 321050; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma1051; CHECK-NEXT: vslideup.vi v8, v16, 161052; CHECK-NEXT: ret1053 %res = shufflevector <16 x i32> %a, <16 x i32> %b, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>1054 ret <32 x i32> %res1055}1056 1057define <4 x i64> @reverse_v4i64_2(<2 x i64> %a, < 2 x i64> %b) {1058; CHECK-LABEL: reverse_v4i64_2:1059; CHECK: # %bb.0:1060; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma1061; CHECK-NEXT: vslidedown.vi v10, v8, 11062; CHECK-NEXT: vslideup.vi v10, v8, 11063; CHECK-NEXT: vslidedown.vi v8, v9, 11064; CHECK-NEXT: vslideup.vi v8, v9, 11065; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma1066; CHECK-NEXT: vslideup.vi v8, v10, 21067; CHECK-NEXT: ret1068 %res = shufflevector <2 x i64> %a, <2 x i64> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0>1069 ret <4 x i64> %res1070}1071 1072define <8 x i64> @reverse_v8i64_2(<4 x i64> %a, <4 x i64> %b) {1073; CHECK-LABEL: reverse_v8i64_2:1074; CHECK: # %bb.0:1075; CHECK-NEXT: csrr a0, vlenb1076; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma1077; CHECK-NEXT: vid.v v121078; CHECK-NEXT: srli a1, a0, 31079; CHECK-NEXT: srli a0, a0, 21080; CHECK-NEXT: addi a1, a1, -11081; CHECK-NEXT: addi a0, a0, -41082; CHECK-NEXT: vrsub.vx v16, v12, a11083; CHECK-NEXT: vrgather.vv v13, v8, v161084; CHECK-NEXT: vrgather.vv v15, v10, v161085; CHECK-NEXT: vrgather.vv v12, v9, v161086; CHECK-NEXT: vrgather.vv v14, v11, v161087; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma1088; CHECK-NEXT: vslidedown.vx v12, v12, a01089; CHECK-NEXT: vslidedown.vx v8, v14, a01090; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma1091; CHECK-NEXT: vslideup.vi v8, v12, 41092; CHECK-NEXT: ret1093 %res = shufflevector <4 x i64> %a, <4 x i64> %b, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>1094 ret <8 x i64> %res1095}1096 1097define <4 x half> @reverse_v4f16_2(<2 x half> %a, <2 x half> %b) {1098; NO-ZVBB-LABEL: reverse_v4f16_2:1099; NO-ZVBB: # %bb.0:1100; NO-ZVBB-NEXT: vsetivli zero, 2, e16, mf4, ta, ma1101; NO-ZVBB-NEXT: vslidedown.vi v10, v8, 11102; NO-ZVBB-NEXT: vslideup.vi v10, v8, 11103; NO-ZVBB-NEXT: vslidedown.vi v8, v9, 11104; NO-ZVBB-NEXT: vslideup.vi v8, v9, 11105; NO-ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma1106; NO-ZVBB-NEXT: vslideup.vi v8, v10, 21107; NO-ZVBB-NEXT: ret1108;1109; ZVBB-LABEL: reverse_v4f16_2:1110; ZVBB: # %bb.0:1111; ZVBB-NEXT: vsetivli zero, 1, e32, mf2, ta, ma1112; ZVBB-NEXT: vror.vi v10, v8, 161113; ZVBB-NEXT: vror.vi v8, v9, 161114; ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma1115; ZVBB-NEXT: vslideup.vi v8, v10, 21116; ZVBB-NEXT: ret1117 %res = shufflevector <2 x half> %a, <2 x half> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0>1118 ret <4 x half> %res1119}1120 1121define <8 x half> @reverse_v8f16_2(<4 x half> %a, <4 x half> %b) {1122; CHECK-LABEL: reverse_v8f16_2:1123; CHECK: # %bb.0:1124; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma1125; CHECK-NEXT: vid.v v101126; CHECK-NEXT: vrsub.vi v10, v10, 31127; CHECK-NEXT: vrgather.vv v11, v8, v101128; CHECK-NEXT: vrgather.vv v8, v9, v101129; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma1130; CHECK-NEXT: vslideup.vi v8, v11, 41131; CHECK-NEXT: ret1132 %res = shufflevector <4 x half> %a, <4 x half> %b, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>1133 ret <8 x half> %res1134}1135 1136define <16 x half> @reverse_v16f16_2(<8 x half> %a, <8 x half> %b) {1137; CHECK-LABEL: reverse_v16f16_2:1138; CHECK: # %bb.0:1139; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma1140; CHECK-NEXT: vid.v v101141; CHECK-NEXT: vrsub.vi v11, v10, 71142; CHECK-NEXT: vrgather.vv v10, v8, v111143; CHECK-NEXT: vrgather.vv v8, v9, v111144; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma1145; CHECK-NEXT: vslideup.vi v8, v10, 81146; CHECK-NEXT: ret1147 %res = shufflevector <8 x half> %a, <8 x half> %b, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>1148 ret <16 x half> %res1149}1150 1151define <32 x half> @reverse_v32f16_2(<16 x half> %a) {1152; CHECK-LABEL: reverse_v32f16_2:1153; CHECK: # %bb.0:1154; CHECK-NEXT: csrr a0, vlenb1155; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma1156; CHECK-NEXT: vid.v v101157; CHECK-NEXT: srli a1, a0, 11158; CHECK-NEXT: addi a1, a1, -11159; CHECK-NEXT: vrsub.vx v12, v10, a11160; CHECK-NEXT: vrgather.vv v11, v8, v121161; CHECK-NEXT: vrgather.vv v10, v9, v121162; CHECK-NEXT: li a1, 321163; CHECK-NEXT: slli a0, a0, 11164; CHECK-NEXT: vrgather.vv v8, v9, v121165; CHECK-NEXT: addi a0, a0, -321166; CHECK-NEXT: vmv.v.v v9, v81167; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma1168; CHECK-NEXT: vslidedown.vx v8, v8, a01169; CHECK-NEXT: ret1170 %res = shufflevector <16 x half> %a, <16 x half> poison, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>1171 ret <32 x half> %res1172}1173 1174define <4 x float> @reverse_v4f32_2(<2 x float> %a, <2 x float> %b) {1175; NO-ZVBB-LABEL: reverse_v4f32_2:1176; NO-ZVBB: # %bb.0:1177; NO-ZVBB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma1178; NO-ZVBB-NEXT: vslidedown.vi v10, v8, 11179; NO-ZVBB-NEXT: vslideup.vi v10, v8, 11180; NO-ZVBB-NEXT: vslidedown.vi v8, v9, 11181; NO-ZVBB-NEXT: vslideup.vi v8, v9, 11182; NO-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma1183; NO-ZVBB-NEXT: vslideup.vi v8, v10, 21184; NO-ZVBB-NEXT: ret1185;1186; ZVBB-LABEL: reverse_v4f32_2:1187; ZVBB: # %bb.0:1188; ZVBB-NEXT: vsetivli zero, 1, e64, m1, ta, ma1189; ZVBB-NEXT: vror.vi v10, v8, 321190; ZVBB-NEXT: vror.vi v8, v9, 321191; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma1192; ZVBB-NEXT: vslideup.vi v8, v10, 21193; ZVBB-NEXT: ret1194 %res = shufflevector <2 x float> %a, <2 x float> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0>1195 ret <4 x float> %res1196}1197 1198define <8 x float> @reverse_v8f32_2(<4 x float> %a, <4 x float> %b) {1199; CHECK-LABEL: reverse_v8f32_2:1200; CHECK: # %bb.0:1201; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma1202; CHECK-NEXT: vid.v v101203; CHECK-NEXT: vrsub.vi v11, v10, 31204; CHECK-NEXT: vrgather.vv v10, v8, v111205; CHECK-NEXT: vrgather.vv v8, v9, v111206; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma1207; CHECK-NEXT: vslideup.vi v8, v10, 41208; CHECK-NEXT: ret1209 %res = shufflevector <4 x float> %a, <4 x float> %b, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>1210 ret <8 x float> %res1211}1212 1213define <16 x float> @reverse_v16f32_2(<8 x float> %a, <8 x float> %b) {1214; CHECK-LABEL: reverse_v16f32_2:1215; CHECK: # %bb.0:1216; CHECK-NEXT: csrr a0, vlenb1217; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma1218; CHECK-NEXT: vid.v v121219; CHECK-NEXT: srli a1, a0, 21220; CHECK-NEXT: srli a0, a0, 11221; CHECK-NEXT: addi a1, a1, -11222; CHECK-NEXT: addi a0, a0, -81223; CHECK-NEXT: vrsub.vx v16, v12, a11224; CHECK-NEXT: vrgather.vv v13, v8, v161225; CHECK-NEXT: vrgather.vv v15, v10, v161226; CHECK-NEXT: vrgather.vv v12, v9, v161227; CHECK-NEXT: vrgather.vv v14, v11, v161228; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma1229; CHECK-NEXT: vslidedown.vx v12, v12, a01230; CHECK-NEXT: vslidedown.vx v8, v14, a01231; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma1232; CHECK-NEXT: vslideup.vi v8, v12, 81233; CHECK-NEXT: ret1234 %res = shufflevector <8 x float> %a, <8 x float> %b, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>1235 ret <16 x float> %res1236}1237 1238define <4 x double> @reverse_v4f64_2(<2 x double> %a, < 2 x double> %b) {1239; CHECK-LABEL: reverse_v4f64_2:1240; CHECK: # %bb.0:1241; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma1242; CHECK-NEXT: vslidedown.vi v10, v8, 11243; CHECK-NEXT: vslideup.vi v10, v8, 11244; CHECK-NEXT: vslidedown.vi v8, v9, 11245; CHECK-NEXT: vslideup.vi v8, v9, 11246; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma1247; CHECK-NEXT: vslideup.vi v8, v10, 21248; CHECK-NEXT: ret1249 %res = shufflevector <2 x double> %a, <2 x double> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0>1250 ret <4 x double> %res1251}1252 1253define <8 x double> @reverse_v8f64_2(<4 x double> %a, <4 x double> %b) {1254; CHECK-LABEL: reverse_v8f64_2:1255; CHECK: # %bb.0:1256; CHECK-NEXT: csrr a0, vlenb1257; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma1258; CHECK-NEXT: vid.v v121259; CHECK-NEXT: srli a1, a0, 31260; CHECK-NEXT: srli a0, a0, 21261; CHECK-NEXT: addi a1, a1, -11262; CHECK-NEXT: addi a0, a0, -41263; CHECK-NEXT: vrsub.vx v16, v12, a11264; CHECK-NEXT: vrgather.vv v13, v8, v161265; CHECK-NEXT: vrgather.vv v15, v10, v161266; CHECK-NEXT: vrgather.vv v12, v9, v161267; CHECK-NEXT: vrgather.vv v14, v11, v161268; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma1269; CHECK-NEXT: vslidedown.vx v12, v12, a01270; CHECK-NEXT: vslidedown.vx v8, v14, a01271; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma1272; CHECK-NEXT: vslideup.vi v8, v12, 41273; CHECK-NEXT: ret1274 %res = shufflevector <4 x double> %a, <4 x double> %b, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>1275 ret <8 x double> %res1276}1277 1278; There is no corresponding v1i256 type, so make sure we don't crash if we try1279; to lower via lowerBitreverseShuffle.1280define <256 x i1> @reverse_v256i1(<256 x i1> %a) vscale_range(16, 1024) {1281; CHECK-LABEL: reverse_v256i1:1282; CHECK: # %bb.0:1283; CHECK-NEXT: li a0, 2561284; CHECK-NEXT: csrr a1, vlenb1285; CHECK-NEXT: vsetvli a2, zero, e16, m2, ta, ma1286; CHECK-NEXT: vid.v v81287; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma1288; CHECK-NEXT: vmv.v.i v10, 01289; CHECK-NEXT: addi a2, a1, -11290; CHECK-NEXT: slli a1, a1, 11291; CHECK-NEXT: vmerge.vim v10, v10, 1, v01292; CHECK-NEXT: vsetvli a3, zero, e16, m2, ta, ma1293; CHECK-NEXT: vrsub.vx v8, v8, a21294; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma1295; CHECK-NEXT: vrgatherei16.vv v13, v10, v81296; CHECK-NEXT: vrgatherei16.vv v12, v11, v81297; CHECK-NEXT: addi a1, a1, -2561298; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma1299; CHECK-NEXT: vslidedown.vx v8, v12, a11300; CHECK-NEXT: vmsne.vi v0, v8, 01301; CHECK-NEXT: ret1302 %res = shufflevector <256 x i1> %a, <256 x i1> poison, <256 x i32> <i32 255, i32 254, i32 253, i32 252, i32 251, i32 250, i32 249, i32 248, i32 247, i32 246, i32 245, i32 244, i32 243, i32 242, i32 241, i32 240, i32 239, i32 238, i32 237, i32 236, i32 235, i32 234, i32 233, i32 232, i32 231, i32 230, i32 229, i32 228, i32 227, i32 226, i32 225, i32 224, i32 223, i32 222, i32 221, i32 220, i32 219, i32 218, i32 217, i32 216, i32 215, i32 214, i32 213, i32 212, i32 211, i32 210, i32 209, i32 208, i32 207, i32 206, i32 205, i32 204, i32 203, i32 202, i32 201, i32 200, i32 199, i32 198, i32 197, i32 196, i32 195, i32 194, i32 193, i32 192, i32 191, i32 190, i32 189, i32 188, i32 187, i32 186, i32 185, i32 184, i32 183, i32 182, i32 181, i32 180, i32 179, i32 178, i32 177, i32 176, i32 175, i32 174, i32 173, i32 172, i32 171, i32 170, i32 169, i32 168, i32 167, i32 166, i32 165, i32 164, i32 163, i32 162, i32 161, i32 160, i32 159, i32 158, i32 157, i32 156, i32 155, i32 154, i32 153, i32 152, i32 151, i32 150, i32 149, i32 148, i32 147, i32 146, i32 145, i32 144, i32 143, i32 142, i32 141, i32 140, i32 139, i32 138, i32 137, i32 136, i32 135, i32 134, i32 133, i32 132, i32 131, i32 130, i32 129, i32 128, i32 127, i32 126, i32 125, i32 124, i32 123, i32 122, i32 121, i32 120, i32 119, i32 118, i32 117, i32 116, i32 115, i32 114, i32 113, i32 112, i32 111, i32 110, i32 109, i32 108, i32 107, i32 106, i32 105, i32 104, i32 103, i32 102, i32 101, i32 100, i32 99, i32 98, i32 97, i32 96, i32 95, i32 94, i32 93, i32 92, i32 91, i32 90, i32 89, i32 88, i32 87, i32 86, i32 85, i32 84, i32 83, i32 82, i32 81, i32 80, i32 79, i32 78, i32 77, i32 76, i32 75, i32 74, i32 73, i32 72, i32 71, i32 70, i32 69, i32 68, i32 67, i32 66, i32 65, i32 64, i32 63, i32 62, i32 61, i32 60, i32 59, i32 58, i32 57, i32 56, i32 55, i32 54, i32 53, i32 52, i32 51, i32 50, i32 49, i32 48, i32 47, i32 46, i32 45, i32 44, i32 43, i32 42, i32 41, i32 40, i32 39, i32 38, i32 37, i32 36, i32 35, i32 34, i32 33, i32 32, i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>1303 ret <256 x i1> %res1304}1305 1306define <8 x i32> @reverse_v8i32_exact_vlen_128(<8 x i32> %a) vscale_range(2, 2) {1307; CHECK-LABEL: reverse_v8i32_exact_vlen_128:1308; CHECK: # %bb.0:1309; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma1310; CHECK-NEXT: vid.v v101311; CHECK-NEXT: vrsub.vi v12, v10, 31312; CHECK-NEXT: vrgather.vv v11, v8, v121313; CHECK-NEXT: vrgather.vv v10, v9, v121314; CHECK-NEXT: vmv2r.v v8, v101315; CHECK-NEXT: ret1316 %res = shufflevector <8 x i32> %a, <8 x i32> poison, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>1317 ret <8 x i32> %res1318}1319 1320define <16 x i32> @reverse_v16i32_exact_vlen_256(<16 x i32> %a) vscale_range(4, 4) {1321; CHECK-LABEL: reverse_v16i32_exact_vlen_256:1322; CHECK: # %bb.0:1323; CHECK-NEXT: vsetivli zero, 8, e32, m1, ta, ma1324; CHECK-NEXT: vid.v v101325; CHECK-NEXT: vrsub.vi v12, v10, 71326; CHECK-NEXT: vrgather.vv v11, v8, v121327; CHECK-NEXT: vrgather.vv v10, v9, v121328; CHECK-NEXT: vmv2r.v v8, v101329; CHECK-NEXT: ret1330 %res = shufflevector <16 x i32> %a, <16 x i32> poison, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>1331 ret <16 x i32> %res1332}1333 1334define <8 x i32> @reverse_v8i32_undef_suffix(<8 x i32> %a) {1335; CHECK-LABEL: reverse_v8i32_undef_suffix:1336; CHECK: # %bb.0:1337; CHECK-NEXT: csrr a0, vlenb1338; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma1339; CHECK-NEXT: vid.v v101340; CHECK-NEXT: srli a1, a0, 21341; CHECK-NEXT: srli a0, a0, 11342; CHECK-NEXT: addi a1, a1, -11343; CHECK-NEXT: vrsub.vx v12, v10, a11344; CHECK-NEXT: vrgather.vv v11, v8, v121345; CHECK-NEXT: vrgather.vv v10, v9, v121346; CHECK-NEXT: addi a0, a0, -81347; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma1348; CHECK-NEXT: vslidedown.vx v8, v10, a01349; CHECK-NEXT: ret1350 %res = shufflevector <8 x i32> %a, <8 x i32> poison, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 poison, i32 poison, i32 poison, i32 poison>1351 ret <8 x i32> %res1352}1353 1354define <8 x i32> @reverse_v8i32_undef_prefix(<8 x i32> %a) {1355; CHECK-LABEL: reverse_v8i32_undef_prefix:1356; CHECK: # %bb.0:1357; CHECK-NEXT: csrr a0, vlenb1358; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma1359; CHECK-NEXT: vid.v v101360; CHECK-NEXT: srli a1, a0, 21361; CHECK-NEXT: srli a0, a0, 11362; CHECK-NEXT: addi a1, a1, -11363; CHECK-NEXT: vrsub.vx v12, v10, a11364; CHECK-NEXT: vrgather.vv v11, v8, v121365; CHECK-NEXT: vrgather.vv v10, v9, v121366; CHECK-NEXT: addi a0, a0, -81367; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma1368; CHECK-NEXT: vslidedown.vx v8, v10, a01369; CHECK-NEXT: ret1370 %res = shufflevector <8 x i32> %a, <8 x i32> poison, <8 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 3, i32 2, i32 1, i32 0>1371 ret <8 x i32> %res1372}1373 1374 1375;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:1376; RV32: {{.*}}1377; RV32-ZVBB: {{.*}}1378; RV64: {{.*}}1379; RV64-ZVBB: {{.*}}1380