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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zvfh,+zfbfmin,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH,RV323; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zvfh,+zfbfmin,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH,RV644; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,RV325; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,RV646 7target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"8 9define <2 x i8> @vslide1up_2xi8(<2 x i8> %v, i8 %b) {10; CHECK-LABEL: vslide1up_2xi8:11; CHECK: # %bb.0:12; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma13; CHECK-NEXT: vslide1up.vx v9, v8, a014; CHECK-NEXT: vmv1r.v v8, v915; CHECK-NEXT: ret16 %vb = insertelement <2 x i8> poison, i8 %b, i64 017 %v1 = shufflevector <2 x i8> %v, <2 x i8> %vb, <2 x i32> <i32 2, i32 0>18 ret <2 x i8> %v119}20 21define <4 x i8> @vslide1up_4xi8(<4 x i8> %v, i8 %b) {22; CHECK-LABEL: vslide1up_4xi8:23; CHECK: # %bb.0:24; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma25; CHECK-NEXT: vslide1up.vx v9, v8, a026; CHECK-NEXT: vmv1r.v v8, v927; CHECK-NEXT: ret28 %vb = insertelement <4 x i8> poison, i8 %b, i64 029 %v1 = shufflevector <4 x i8> %v, <4 x i8> %vb, <4 x i32> <i32 4, i32 0, i32 1, i32 2>30 ret <4 x i8> %v131}32 33define <4 x i8> @vslide1up_4xi8_swapped(<4 x i8> %v, i8 %b) {34; CHECK-LABEL: vslide1up_4xi8_swapped:35; CHECK: # %bb.0:36; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma37; CHECK-NEXT: vslide1up.vx v9, v8, a038; CHECK-NEXT: vmv1r.v v8, v939; CHECK-NEXT: ret40 %vb = insertelement <4 x i8> poison, i8 %b, i64 041 %v1 = shufflevector <4 x i8> %vb, <4 x i8> %v, <4 x i32> <i32 0, i32 4, i32 5, i32 6>42 ret <4 x i8> %v143}44 45define <2 x i16> @vslide1up_2xi16(<2 x i16> %v, i16 %b) {46; CHECK-LABEL: vslide1up_2xi16:47; CHECK: # %bb.0:48; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma49; CHECK-NEXT: vslide1up.vx v9, v8, a050; CHECK-NEXT: vmv1r.v v8, v951; CHECK-NEXT: ret52 %vb = insertelement <2 x i16> poison, i16 %b, i64 053 %v1 = shufflevector <2 x i16> %v, <2 x i16> %vb, <2 x i32> <i32 2, i32 0>54 ret <2 x i16> %v155}56 57define <4 x i16> @vslide1up_4xi16(<4 x i16> %v, i16 %b) {58; CHECK-LABEL: vslide1up_4xi16:59; CHECK: # %bb.0:60; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma61; CHECK-NEXT: vslide1up.vx v9, v8, a062; CHECK-NEXT: vmv1r.v v8, v963; CHECK-NEXT: ret64 %vb = insertelement <4 x i16> poison, i16 %b, i64 065 %v1 = shufflevector <4 x i16> %v, <4 x i16> %vb, <4 x i32> <i32 4, i32 0, i32 1, i32 2>66 ret <4 x i16> %v167}68 69define <2 x i32> @vslide1up_2xi32(<2 x i32> %v, i32 %b) {70; CHECK-LABEL: vslide1up_2xi32:71; CHECK: # %bb.0:72; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma73; CHECK-NEXT: vslide1up.vx v9, v8, a074; CHECK-NEXT: vmv1r.v v8, v975; CHECK-NEXT: ret76 %vb = insertelement <2 x i32> poison, i32 %b, i64 077 %v1 = shufflevector <2 x i32> %v, <2 x i32> %vb, <2 x i32> <i32 2, i32 0>78 ret <2 x i32> %v179}80 81define <4 x i32> @vslide1up_4xi32(<4 x i32> %v, i32 %b) {82; CHECK-LABEL: vslide1up_4xi32:83; CHECK: # %bb.0:84; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma85; CHECK-NEXT: vslide1up.vx v9, v8, a086; CHECK-NEXT: vmv.v.v v8, v987; CHECK-NEXT: ret88 %vb = insertelement <4 x i32> poison, i32 %b, i64 089 %v1 = shufflevector <4 x i32> %v, <4 x i32> %vb, <4 x i32> <i32 4, i32 0, i32 1, i32 2>90 ret <4 x i32> %v191}92 93define <2 x i64> @vslide1up_2xi64(<2 x i64> %v, i64 %b) {94; RV32-LABEL: vslide1up_2xi64:95; RV32: # %bb.0:96; RV32-NEXT: addi sp, sp, -1697; RV32-NEXT: .cfi_def_cfa_offset 1698; RV32-NEXT: sw a0, 8(sp)99; RV32-NEXT: sw a1, 12(sp)100; RV32-NEXT: addi a0, sp, 8101; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma102; RV32-NEXT: vlse64.v v9, (a0), zero103; RV32-NEXT: vslideup.vi v9, v8, 1104; RV32-NEXT: vmv.v.v v8, v9105; RV32-NEXT: addi sp, sp, 16106; RV32-NEXT: .cfi_def_cfa_offset 0107; RV32-NEXT: ret108;109; RV64-LABEL: vslide1up_2xi64:110; RV64: # %bb.0:111; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma112; RV64-NEXT: vslide1up.vx v9, v8, a0113; RV64-NEXT: vmv.v.v v8, v9114; RV64-NEXT: ret115 %vb = insertelement <2 x i64> poison, i64 %b, i64 0116 %v1 = shufflevector <2 x i64> %v, <2 x i64> %vb, <2 x i32> <i32 2, i32 0>117 ret <2 x i64> %v1118}119 120define <4 x i64> @vslide1up_4xi64(<4 x i64> %v, i64 %b) {121; RV32-LABEL: vslide1up_4xi64:122; RV32: # %bb.0:123; RV32-NEXT: addi sp, sp, -16124; RV32-NEXT: .cfi_def_cfa_offset 16125; RV32-NEXT: sw a0, 8(sp)126; RV32-NEXT: sw a1, 12(sp)127; RV32-NEXT: addi a0, sp, 8128; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma129; RV32-NEXT: vlse64.v v10, (a0), zero130; RV32-NEXT: vslideup.vi v10, v8, 1131; RV32-NEXT: vmv.v.v v8, v10132; RV32-NEXT: addi sp, sp, 16133; RV32-NEXT: .cfi_def_cfa_offset 0134; RV32-NEXT: ret135;136; RV64-LABEL: vslide1up_4xi64:137; RV64: # %bb.0:138; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma139; RV64-NEXT: vslide1up.vx v10, v8, a0140; RV64-NEXT: vmv.v.v v8, v10141; RV64-NEXT: ret142 %vb = insertelement <4 x i64> poison, i64 %b, i64 0143 %v1 = shufflevector <4 x i64> %v, <4 x i64> %vb, <4 x i32> <i32 4, i32 0, i32 1, i32 2>144 ret <4 x i64> %v1145}146 147define <2 x bfloat> @vslide1up_2xbf16(<2 x bfloat> %v, bfloat %b) {148; CHECK-LABEL: vslide1up_2xbf16:149; CHECK: # %bb.0:150; CHECK-NEXT: fmv.x.h a0, fa0151; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma152; CHECK-NEXT: vslide1up.vx v9, v8, a0153; CHECK-NEXT: vmv1r.v v8, v9154; CHECK-NEXT: ret155 %vb = insertelement <2 x bfloat> poison, bfloat %b, i64 0156 %v1 = shufflevector <2 x bfloat> %v, <2 x bfloat> %vb, <2 x i32> <i32 2, i32 0>157 ret <2 x bfloat> %v1158}159 160define <4 x bfloat> @vslide1up_4xbf16(<4 x bfloat> %v, bfloat %b) {161; CHECK-LABEL: vslide1up_4xbf16:162; CHECK: # %bb.0:163; CHECK-NEXT: fmv.x.h a0, fa0164; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma165; CHECK-NEXT: vslide1up.vx v9, v8, a0166; CHECK-NEXT: vmv1r.v v8, v9167; CHECK-NEXT: ret168 %vb = insertelement <4 x bfloat> poison, bfloat %b, i64 0169 %v1 = shufflevector <4 x bfloat> %v, <4 x bfloat> %vb, <4 x i32> <i32 4, i32 0, i32 1, i32 2>170 ret <4 x bfloat> %v1171}172 173define <2 x half> @vslide1up_2xf16(<2 x half> %v, half %b) {174; ZVFH-LABEL: vslide1up_2xf16:175; ZVFH: # %bb.0:176; ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma177; ZVFH-NEXT: vfslide1up.vf v9, v8, fa0178; ZVFH-NEXT: vmv1r.v v8, v9179; ZVFH-NEXT: ret180;181; ZVFHMIN-LABEL: vslide1up_2xf16:182; ZVFHMIN: # %bb.0:183; ZVFHMIN-NEXT: fmv.x.h a0, fa0184; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma185; ZVFHMIN-NEXT: vslide1up.vx v9, v8, a0186; ZVFHMIN-NEXT: vmv1r.v v8, v9187; ZVFHMIN-NEXT: ret188 %vb = insertelement <2 x half> poison, half %b, i64 0189 %v1 = shufflevector <2 x half> %v, <2 x half> %vb, <2 x i32> <i32 2, i32 0>190 ret <2 x half> %v1191}192 193define <4 x half> @vslide1up_4xf16(<4 x half> %v, half %b) {194; ZVFH-LABEL: vslide1up_4xf16:195; ZVFH: # %bb.0:196; ZVFH-NEXT: vsetivli zero, 4, e16, mf2, ta, ma197; ZVFH-NEXT: vfslide1up.vf v9, v8, fa0198; ZVFH-NEXT: vmv1r.v v8, v9199; ZVFH-NEXT: ret200;201; ZVFHMIN-LABEL: vslide1up_4xf16:202; ZVFHMIN: # %bb.0:203; ZVFHMIN-NEXT: fmv.x.h a0, fa0204; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma205; ZVFHMIN-NEXT: vslide1up.vx v9, v8, a0206; ZVFHMIN-NEXT: vmv1r.v v8, v9207; ZVFHMIN-NEXT: ret208 %vb = insertelement <4 x half> poison, half %b, i64 0209 %v1 = shufflevector <4 x half> %v, <4 x half> %vb, <4 x i32> <i32 4, i32 0, i32 1, i32 2>210 ret <4 x half> %v1211}212 213define <2 x float> @vslide1up_2xf32(<2 x float> %v, float %b) {214; CHECK-LABEL: vslide1up_2xf32:215; CHECK: # %bb.0:216; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma217; CHECK-NEXT: vfslide1up.vf v9, v8, fa0218; CHECK-NEXT: vmv1r.v v8, v9219; CHECK-NEXT: ret220 %vb = insertelement <2 x float> poison, float %b, i64 0221 %v1 = shufflevector <2 x float> %v, <2 x float> %vb, <2 x i32> <i32 2, i32 0>222 ret <2 x float> %v1223}224 225define <4 x float> @vslide1up_4xf32(<4 x float> %v, float %b) {226; CHECK-LABEL: vslide1up_4xf32:227; CHECK: # %bb.0:228; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma229; CHECK-NEXT: vfslide1up.vf v9, v8, fa0230; CHECK-NEXT: vmv.v.v v8, v9231; CHECK-NEXT: ret232 %vb = insertelement <4 x float> poison, float %b, i64 0233 %v1 = shufflevector <4 x float> %v, <4 x float> %vb, <4 x i32> <i32 4, i32 0, i32 1, i32 2>234 ret <4 x float> %v1235}236 237define <2 x double> @vslide1up_2xf64(<2 x double> %v, double %b) {238; CHECK-LABEL: vslide1up_2xf64:239; CHECK: # %bb.0:240; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma241; CHECK-NEXT: vfslide1up.vf v9, v8, fa0242; CHECK-NEXT: vmv.v.v v8, v9243; CHECK-NEXT: ret244 %vb = insertelement <2 x double> poison, double %b, i64 0245 %v1 = shufflevector <2 x double> %v, <2 x double> %vb, <2 x i32> <i32 2, i32 0>246 ret <2 x double> %v1247}248 249define <4 x double> @vslide1up_4xf64(<4 x double> %v, double %b) {250; CHECK-LABEL: vslide1up_4xf64:251; CHECK: # %bb.0:252; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma253; CHECK-NEXT: vfmv.s.f v10, fa0254; CHECK-NEXT: vslideup.vi v10, v8, 3255; CHECK-NEXT: vmv.v.v v8, v10256; CHECK-NEXT: ret257 %vb = insertelement <4 x double> poison, double %b, i64 0258 %v1 = shufflevector <4 x double> %v, <4 x double> %vb, <4 x i32> <i32 4, i32 5, i32 6, i32 0>259 ret <4 x double> %v1260}261 262define <4 x i8> @vslide1up_4xi8_with_splat(<4 x i8> %v, i8 %b) {263; CHECK-LABEL: vslide1up_4xi8_with_splat:264; CHECK: # %bb.0:265; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma266; CHECK-NEXT: vslide1up.vx v9, v8, a0267; CHECK-NEXT: vmv1r.v v8, v9268; CHECK-NEXT: ret269 %vb = insertelement <4 x i8> poison, i8 %b, i64 0270 %v1 = shufflevector <4 x i8> %vb, <4 x i8> poison, <4 x i32> zeroinitializer271 %v2 = shufflevector <4 x i8> %v1, <4 x i8> %v, <4 x i32> <i32 1, i32 4, i32 5, i32 6>272 ret <4 x i8> %v2273}274 275define <2 x double> @vslide1up_v2f64_inverted(<2 x double> %v, double %b) {276; CHECK-LABEL: vslide1up_v2f64_inverted:277; CHECK: # %bb.0:278; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma279; CHECK-NEXT: vrgather.vi v9, v8, 0280; CHECK-NEXT: vsetvli zero, zero, e64, m1, tu, ma281; CHECK-NEXT: vfmv.s.f v9, fa0282; CHECK-NEXT: vmv1r.v v8, v9283; CHECK-NEXT: ret284 %v1 = shufflevector <2 x double> %v, <2 x double> poison, <2 x i32> <i32 0, i32 0>285 %v2 = insertelement <2 x double> %v1, double %b, i64 0286 ret <2 x double> %v2287}288 289define <4 x i8> @vslide1up_4xi8_inverted(<4 x i8> %v, i8 %b) {290; CHECK-LABEL: vslide1up_4xi8_inverted:291; CHECK: # %bb.0:292; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma293; CHECK-NEXT: vslideup.vi v9, v8, 1294; CHECK-NEXT: vsetvli zero, zero, e8, mf4, tu, ma295; CHECK-NEXT: vmv.s.x v9, a0296; CHECK-NEXT: vmv1r.v v8, v9297; CHECK-NEXT: ret298 %v1 = shufflevector <4 x i8> %v, <4 x i8> poison, <4 x i32> <i32 poison, i32 0, i32 1, i32 2>299 %v2 = insertelement <4 x i8> %v1, i8 %b, i64 0300 ret <4 x i8> %v2301}302 303define <2 x double> @vslide1up_2xf64_as_rotate(<2 x double> %v, double %b) {304; CHECK-LABEL: vslide1up_2xf64_as_rotate:305; CHECK: # %bb.0:306; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma307; CHECK-NEXT: vfmv.s.f v9, fa0308; CHECK-NEXT: vslideup.vi v8, v9, 1309; CHECK-NEXT: vslidedown.vi v9, v8, 1310; CHECK-NEXT: vslideup.vi v9, v8, 1311; CHECK-NEXT: vmv.v.v v8, v9312; CHECK-NEXT: ret313 %v1 = insertelement <2 x double> %v, double %b, i64 1314 %v2 = shufflevector <2 x double> %v1, <2 x double> poison, <2 x i32> <i32 1, i32 0>315 ret <2 x double> %v2316}317 318define <4 x i8> @vslide1up_4xi8_as_rotate(<4 x i8> %v, i8 %b) {319; CHECK-LABEL: vslide1up_4xi8_as_rotate:320; CHECK: # %bb.0:321; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma322; CHECK-NEXT: vmv.s.x v9, a0323; CHECK-NEXT: vslideup.vi v8, v9, 3324; CHECK-NEXT: vslidedown.vi v9, v8, 3325; CHECK-NEXT: vslideup.vi v9, v8, 1326; CHECK-NEXT: vmv1r.v v8, v9327; CHECK-NEXT: ret328 %v1 = insertelement <4 x i8> %v, i8 %b, i64 3329 %v2 = shufflevector <4 x i8> %v1, <4 x i8> poison, <4 x i32> <i32 3, i32 0, i32 1, i32 2>330 ret <4 x i8> %v2331}332 333; The length of the shift is less than the suffix, since we'd have to334; materailize the splat, using the vslide1up doesn't help us.335define <4 x i32> @vslide1up_4xi32_neg1(<4 x i32> %v, i32 %b) {336; CHECK-LABEL: vslide1up_4xi32_neg1:337; CHECK: # %bb.0:338; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma339; CHECK-NEXT: vmv.v.x v9, a0340; CHECK-NEXT: vsetivli zero, 3, e32, m1, tu, ma341; CHECK-NEXT: vslideup.vi v9, v8, 1342; CHECK-NEXT: vmv1r.v v8, v9343; CHECK-NEXT: ret344 %vb = insertelement <4 x i32> poison, i32 %b, i64 0345 %vb2 = insertelement <4 x i32> %vb, i32 %b, i64 3346 %v1 = shufflevector <4 x i32> %v, <4 x i32> %vb2, <4 x i32> <i32 4, i32 0, i32 1, i32 7>347 ret <4 x i32> %v1348}349 350; We don't know the scalar to do the vslide1up351define <4 x i32> @vslide1up_4xi32_neg2(<4 x i32> %v1, <4 x i32> %v2) {352; CHECK-LABEL: vslide1up_4xi32_neg2:353; CHECK: # %bb.0:354; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma355; CHECK-NEXT: vslideup.vi v9, v8, 1356; CHECK-NEXT: vmv.v.v v8, v9357; CHECK-NEXT: ret358 %res = shufflevector <4 x i32> %v1, <4 x i32> %v2, <4 x i32> <i32 4, i32 0, i32 1, i32 2>359 ret <4 x i32> %res360}361 362; Not profitable - can just use a slideup instead363define <4 x i8> @vslide1up_4xi8_neg_undef_insert(<4 x i8> %v, i8 %b) {364; CHECK-LABEL: vslide1up_4xi8_neg_undef_insert:365; CHECK: # %bb.0:366; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma367; CHECK-NEXT: vslideup.vi v9, v8, 1368; CHECK-NEXT: vmv1r.v v8, v9369; CHECK-NEXT: ret370 %v2 = shufflevector <4 x i8> poison, <4 x i8> %v, <4 x i32> <i32 0, i32 4, i32 5, i32 6>371 ret <4 x i8> %v2372}373 374define <4 x i8> @vslide1up_4xi8_neg_incorrect_insert(<4 x i8> %v, i8 %b) {375; CHECK-LABEL: vslide1up_4xi8_neg_incorrect_insert:376; CHECK: # %bb.0:377; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma378; CHECK-NEXT: vmv1r.v v9, v8379; CHECK-NEXT: vslideup.vi v9, v8, 1380; CHECK-NEXT: vmv1r.v v8, v9381; CHECK-NEXT: ret382 %v2 = shufflevector <4 x i8> poison, <4 x i8> %v, <4 x i32> <i32 4, i32 4, i32 5, i32 6>383 ret <4 x i8> %v2384}385 386define <4 x i8> @vslide1up_4xi8_neg_incorrect_insert2(<4 x i8> %v, i8 %b) {387; CHECK-LABEL: vslide1up_4xi8_neg_incorrect_insert2:388; CHECK: # %bb.0:389; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma390; CHECK-NEXT: vslidedown.vi v9, v8, 3391; CHECK-NEXT: vslideup.vi v9, v8, 1392; CHECK-NEXT: vmv1r.v v8, v9393; CHECK-NEXT: ret394 %v2 = shufflevector <4 x i8> poison, <4 x i8> %v, <4 x i32> <i32 7, i32 4, i32 5, i32 6>395 ret <4 x i8> %v2396}397 398define <4 x i8> @vslide1up_4xi8_neg_incorrect_insert3(<4 x i8> %v, i8 %b) {399; CHECK-LABEL: vslide1up_4xi8_neg_incorrect_insert3:400; CHECK: # %bb.0:401; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma402; CHECK-NEXT: vslidedown.vi v9, v8, 1403; CHECK-NEXT: vslideup.vi v9, v8, 1404; CHECK-NEXT: vmv1r.v v8, v9405; CHECK-NEXT: ret406 %v2 = shufflevector <4 x i8> poison, <4 x i8> %v, <4 x i32> <i32 5, i32 4, i32 5, i32 6>407 ret <4 x i8> %v2408}409 410define <2 x i8> @vslide1up_4xi8_neg_length_changing(<4 x i8> %v, i8 %b) {411; CHECK-LABEL: vslide1up_4xi8_neg_length_changing:412; CHECK: # %bb.0:413; CHECK-NEXT: vsetivli zero, 1, e8, m1, tu, ma414; CHECK-NEXT: vmv1r.v v9, v8415; CHECK-NEXT: vmv.s.x v9, a0416; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma417; CHECK-NEXT: vslideup.vi v9, v8, 1418; CHECK-NEXT: vmv1r.v v8, v9419; CHECK-NEXT: ret420 %v1 = insertelement <4 x i8> %v, i8 %b, i64 0421 %v2 = shufflevector <4 x i8> %v1, <4 x i8> %v, <2 x i32> <i32 0, i32 4>422 ret <2 x i8> %v2423}424