401 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfhmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV323; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfhmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV644; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfhmin,+experimental-xrivosvizip -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZIP,ZIP-RV325; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfhmin,+experimental-xrivosvizip -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZIP,ZIP-RV646 7define <4 x i32> @zipeven_v4i32(<4 x i32> %a, <4 x i32> %b) {8; CHECK-LABEL: zipeven_v4i32:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu11; CHECK-NEXT: vmv.v.i v0, 1012; CHECK-NEXT: vslideup.vi v8, v9, 1, v0.t13; CHECK-NEXT: ret14;15; ZIP-LABEL: zipeven_v4i32:16; ZIP: # %bb.0: # %entry17; ZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma18; ZIP-NEXT: ri.vzipeven.vv v10, v8, v919; ZIP-NEXT: vmv.v.v v8, v1020; ZIP-NEXT: ret21entry:22 %c = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 6>23 ret <4 x i32> %c24}25 26define <4 x i32> @zipeven_v4i32_swapped(<4 x i32> %a, <4 x i32> %b) {27; CHECK-LABEL: zipeven_v4i32_swapped:28; CHECK: # %bb.0: # %entry29; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu30; CHECK-NEXT: vmv.v.i v0, 1031; CHECK-NEXT: vslideup.vi v9, v8, 1, v0.t32; CHECK-NEXT: vmv.v.v v8, v933; CHECK-NEXT: ret34;35; ZIP-LABEL: zipeven_v4i32_swapped:36; ZIP: # %bb.0: # %entry37; ZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma38; ZIP-NEXT: ri.vzipeven.vv v10, v9, v839; ZIP-NEXT: vmv.v.v v8, v1040; ZIP-NEXT: ret41entry:42 %c = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 0, i32 6, i32 2>43 ret <4 x i32> %c44}45 46define <4 x i64> @zipeven_v4i64(<4 x i64> %a, <4 x i64> %b) {47; CHECK-LABEL: zipeven_v4i64:48; CHECK: # %bb.0: # %entry49; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma50; CHECK-NEXT: vmv.v.i v0, 1051; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu52; CHECK-NEXT: vslideup.vi v8, v10, 1, v0.t53; CHECK-NEXT: ret54;55; ZIP-LABEL: zipeven_v4i64:56; ZIP: # %bb.0: # %entry57; ZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma58; ZIP-NEXT: ri.vzipeven.vv v12, v8, v1059; ZIP-NEXT: vmv.v.v v8, v1260; ZIP-NEXT: ret61entry:62 %c = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 6>63 ret <4 x i64> %c64}65 66define <4 x half> @zipeven_v4f16(<4 x half> %a, <4 x half> %b) {67; CHECK-LABEL: zipeven_v4f16:68; CHECK: # %bb.0: # %entry69; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu70; CHECK-NEXT: vmv.v.i v0, 1071; CHECK-NEXT: vslideup.vi v8, v9, 1, v0.t72; CHECK-NEXT: ret73;74; ZIP-LABEL: zipeven_v4f16:75; ZIP: # %bb.0: # %entry76; ZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma77; ZIP-NEXT: ri.vzipeven.vv v10, v8, v978; ZIP-NEXT: vmv1r.v v8, v1079; ZIP-NEXT: ret80entry:81 %c = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 6>82 ret <4 x half> %c83}84 85define <4 x float> @zipeven_v4f32(<4 x float> %a, <4 x float> %b) {86; CHECK-LABEL: zipeven_v4f32:87; CHECK: # %bb.0: # %entry88; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu89; CHECK-NEXT: vmv.v.i v0, 1090; CHECK-NEXT: vslideup.vi v8, v9, 1, v0.t91; CHECK-NEXT: ret92;93; ZIP-LABEL: zipeven_v4f32:94; ZIP: # %bb.0: # %entry95; ZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma96; ZIP-NEXT: ri.vzipeven.vv v10, v8, v997; ZIP-NEXT: vmv.v.v v8, v1098; ZIP-NEXT: ret99entry:100 %c = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 6>101 ret <4 x float> %c102}103 104define <4 x double> @zipeven_v4f64(<4 x double> %a, <4 x double> %b) {105; CHECK-LABEL: zipeven_v4f64:106; CHECK: # %bb.0: # %entry107; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma108; CHECK-NEXT: vmv.v.i v0, 10109; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu110; CHECK-NEXT: vslideup.vi v8, v10, 1, v0.t111; CHECK-NEXT: ret112;113; ZIP-LABEL: zipeven_v4f64:114; ZIP: # %bb.0: # %entry115; ZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma116; ZIP-NEXT: ri.vzipeven.vv v12, v8, v10117; ZIP-NEXT: vmv.v.v v8, v12118; ZIP-NEXT: ret119entry:120 %c = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 6>121 ret <4 x double> %c122}123 124 125define <4 x i32> @zipodd_v4i32(<4 x i32> %a, <4 x i32> %b) {126; CHECK-LABEL: zipodd_v4i32:127; CHECK: # %bb.0: # %entry128; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu129; CHECK-NEXT: vmv.v.i v0, 5130; CHECK-NEXT: vslidedown.vi v9, v8, 1, v0.t131; CHECK-NEXT: vmv.v.v v8, v9132; CHECK-NEXT: ret133;134; ZIP-LABEL: zipodd_v4i32:135; ZIP: # %bb.0: # %entry136; ZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma137; ZIP-NEXT: ri.vzipodd.vv v10, v8, v9138; ZIP-NEXT: vmv.v.v v8, v10139; ZIP-NEXT: ret140entry:141 %c = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 1, i32 5, i32 3, i32 7>142 ret <4 x i32> %c143}144 145define <4 x i32> @zipodd_v4i32_swapped(<4 x i32> %a, <4 x i32> %b) {146; CHECK-LABEL: zipodd_v4i32_swapped:147; CHECK: # %bb.0: # %entry148; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu149; CHECK-NEXT: vmv.v.i v0, 5150; CHECK-NEXT: vslidedown.vi v8, v9, 1, v0.t151; CHECK-NEXT: ret152;153; ZIP-LABEL: zipodd_v4i32_swapped:154; ZIP: # %bb.0: # %entry155; ZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma156; ZIP-NEXT: ri.vzipodd.vv v10, v9, v8157; ZIP-NEXT: vmv.v.v v8, v10158; ZIP-NEXT: ret159entry:160 %c = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 5, i32 1, i32 7, i32 3>161 ret <4 x i32> %c162}163 164; This is the zipeven pattern with a poison second operand. That happens165; to also be described as an identity shuffle, so this is testing that we166; don't emit the zipeven instruction.167define <4 x i32> @zipeven_v4i32_single(<4 x i32> %a) {168; CHECK-LABEL: zipeven_v4i32_single:169; CHECK: # %bb.0: # %entry170; CHECK-NEXT: ret171;172; ZIP-LABEL: zipeven_v4i32_single:173; ZIP: # %bb.0: # %entry174; ZIP-NEXT: ret175entry:176 %c = shufflevector <4 x i32> %a, <4 x i32> poison, <4 x i32> <i32 0, i32 poison, i32 2, i32 poison>177 ret <4 x i32> %c178}179 180; This is the zipodd pattern with a poison second operand. That happens181; to also be described as a single slide, so this is testing that we182; don't emit the zipodd instruction.183define <4 x i32> @zipodd_v4i32_single(<4 x i32> %a) {184; CHECK-LABEL: zipodd_v4i32_single:185; CHECK: # %bb.0: # %entry186; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma187; CHECK-NEXT: vslidedown.vi v8, v8, 1188; CHECK-NEXT: ret189;190; ZIP-LABEL: zipodd_v4i32_single:191; ZIP: # %bb.0: # %entry192; ZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma193; ZIP-NEXT: vslidedown.vi v8, v8, 1194; ZIP-NEXT: ret195entry:196 %c = shufflevector <4 x i32> %a, <4 x i32> poison, <4 x i32> <i32 1, i32 poison, i32 3, i32 poison>197 ret <4 x i32> %c198}199 200define <4 x i32> @zipodd_v4i32_both(<4 x i32> %a) {201; CHECK-LABEL: zipodd_v4i32_both:202; CHECK: # %bb.0: # %entry203; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu204; CHECK-NEXT: vmv.v.i v0, 5205; CHECK-NEXT: vslidedown.vi v8, v8, 1, v0.t206; CHECK-NEXT: ret207;208; ZIP-LABEL: zipodd_v4i32_both:209; ZIP: # %bb.0: # %entry210; ZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma211; ZIP-NEXT: ri.vzipodd.vv v9, v8, v8212; ZIP-NEXT: vmv.v.v v8, v9213; ZIP-NEXT: ret214entry:215 %c = shufflevector <4 x i32> %a, <4 x i32> poison, <4 x i32> <i32 1, i32 1, i32 3, i32 3>216 ret <4 x i32> %c217}218 219define <4 x i32> @zipeven_v4i32_both(<4 x i32> %a) {220; CHECK-LABEL: zipeven_v4i32_both:221; CHECK: # %bb.0: # %entry222; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu223; CHECK-NEXT: vmv.v.i v0, 10224; CHECK-NEXT: vmv1r.v v9, v8225; CHECK-NEXT: vslideup.vi v9, v8, 1, v0.t226; CHECK-NEXT: vmv.v.v v8, v9227; CHECK-NEXT: ret228;229; ZIP-LABEL: zipeven_v4i32_both:230; ZIP: # %bb.0: # %entry231; ZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma232; ZIP-NEXT: ri.vzipeven.vv v9, v8, v8233; ZIP-NEXT: vmv.v.v v8, v9234; ZIP-NEXT: ret235entry:236 %c = shufflevector <4 x i32> %a, <4 x i32> poison, <4 x i32> <i32 0, i32 0, i32 2, i32 2>237 ret <4 x i32> %c238}239 240define <4 x i32> @zipeven_v4i32_partial(<4 x i32> %a, <4 x i32> %b) {241; CHECK-LABEL: zipeven_v4i32_partial:242; CHECK: # %bb.0: # %entry243; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, ma244; CHECK-NEXT: vslideup.vi v8, v9, 1245; CHECK-NEXT: ret246;247; ZIP-LABEL: zipeven_v4i32_partial:248; ZIP: # %bb.0: # %entry249; ZIP-NEXT: vsetivli zero, 2, e32, m1, tu, ma250; ZIP-NEXT: vslideup.vi v8, v9, 1251; ZIP-NEXT: ret252entry:253 %c = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 poison>254 ret <4 x i32> %c255}256 257define <4 x i32> @zipodd_v4i32_partial(<4 x i32> %a, <4 x i32> %b) {258; CHECK-LABEL: zipodd_v4i32_partial:259; CHECK: # %bb.0: # %entry260; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu261; CHECK-NEXT: vmv.v.i v0, 5262; CHECK-NEXT: vslidedown.vi v9, v8, 1, v0.t263; CHECK-NEXT: vmv.v.v v8, v9264; CHECK-NEXT: ret265;266; ZIP-LABEL: zipodd_v4i32_partial:267; ZIP: # %bb.0: # %entry268; ZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma269; ZIP-NEXT: ri.vzipodd.vv v10, v8, v9270; ZIP-NEXT: vmv.v.v v8, v10271; ZIP-NEXT: ret272entry:273 %c = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 1, i32 5, i32 3, i32 poison>274 ret <4 x i32> %c275}276 277define <8 x i32> @zipeven_v8i32(<8 x i32> %v1, <8 x i32> %v2) {278; CHECK-LABEL: zipeven_v8i32:279; CHECK: # %bb.0:280; CHECK-NEXT: li a0, 170281; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu282; CHECK-NEXT: vmv.s.x v0, a0283; CHECK-NEXT: vslideup.vi v8, v10, 1, v0.t284; CHECK-NEXT: ret285;286; ZIP-LABEL: zipeven_v8i32:287; ZIP: # %bb.0:288; ZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma289; ZIP-NEXT: ri.vzipeven.vv v12, v8, v10290; ZIP-NEXT: vmv.v.v v8, v12291; ZIP-NEXT: ret292 %out = shufflevector <8 x i32> %v1, <8 x i32> %v2, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>293 ret <8 x i32> %out294}295 296define <8 x i32> @zipodd_v8i32(<8 x i32> %v1, <8 x i32> %v2) {297; CHECK-LABEL: zipodd_v8i32:298; CHECK: # %bb.0:299; CHECK-NEXT: li a0, 85300; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu301; CHECK-NEXT: vmv.s.x v0, a0302; CHECK-NEXT: vslidedown.vi v10, v8, 1, v0.t303; CHECK-NEXT: vmv.v.v v8, v10304; CHECK-NEXT: ret305;306; ZIP-LABEL: zipodd_v8i32:307; ZIP: # %bb.0:308; ZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma309; ZIP-NEXT: ri.vzipodd.vv v12, v8, v10310; ZIP-NEXT: vmv.v.v v8, v12311; ZIP-NEXT: ret312 %out = shufflevector <8 x i32> %v1, <8 x i32> %v2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>313 ret <8 x i32> %out314}315 316define <16 x i64> @zipeven_v16i64(<16 x i64> %v1, <16 x i64> %v2) {317; CHECK-LABEL: zipeven_v16i64:318; CHECK: # %bb.0:319; CHECK-NEXT: lui a0, 11320; CHECK-NEXT: addi a0, a0, -1366321; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu322; CHECK-NEXT: vmv.s.x v0, a0323; CHECK-NEXT: vslideup.vi v8, v16, 1, v0.t324; CHECK-NEXT: ret325;326; ZIP-LABEL: zipeven_v16i64:327; ZIP: # %bb.0:328; ZIP-NEXT: vsetivli zero, 16, e64, m8, ta, ma329; ZIP-NEXT: ri.vzipeven.vv v24, v8, v16330; ZIP-NEXT: vmv.v.v v8, v24331; ZIP-NEXT: ret332 %out = shufflevector <16 x i64> %v1, <16 x i64> %v2, <16 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30>333 ret <16 x i64> %out334}335 336define <16 x i64> @zipodd_v16i64(<16 x i64> %v1, <16 x i64> %v2) {337; CHECK-LABEL: zipodd_v16i64:338; CHECK: # %bb.0:339; CHECK-NEXT: lui a0, 5340; CHECK-NEXT: addi a0, a0, 1365341; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu342; CHECK-NEXT: vmv.s.x v0, a0343; CHECK-NEXT: vslidedown.vi v16, v8, 1, v0.t344; CHECK-NEXT: vmv.v.v v8, v16345; CHECK-NEXT: ret346;347; ZIP-LABEL: zipodd_v16i64:348; ZIP: # %bb.0:349; ZIP-NEXT: vsetivli zero, 16, e64, m8, ta, ma350; ZIP-NEXT: ri.vzipodd.vv v24, v8, v16351; ZIP-NEXT: vmv.v.v v8, v24352; ZIP-NEXT: ret353 %out = shufflevector <16 x i64> %v1, <16 x i64> %v2, <16 x i32> <i32 1, i32 17, i32 3, i32 19, i32 5, i32 21, i32 7, i32 23, i32 9, i32 25, i32 11, i32 27, i32 13, i32 29, i32 15, i32 31>354 ret <16 x i64> %out355}356 357define <8 x i32> @zipeven_v8i32_as_v4i64(<8 x i32> %v1, <8 x i32> %v2) {358; CHECK-LABEL: zipeven_v8i32_as_v4i64:359; CHECK: # %bb.0:360; CHECK-NEXT: li a0, 204361; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu362; CHECK-NEXT: vmv.s.x v0, a0363; CHECK-NEXT: vslideup.vi v8, v10, 2, v0.t364; CHECK-NEXT: ret365;366; ZIP-LABEL: zipeven_v8i32_as_v4i64:367; ZIP: # %bb.0:368; ZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma369; ZIP-NEXT: ri.vzipeven.vv v12, v8, v10370; ZIP-NEXT: vmv.v.v v8, v12371; ZIP-NEXT: ret372 %out = shufflevector <8 x i32> %v1, <8 x i32> %v2, <8 x i32> <i32 0, i32 1, i32 8, i32 9, i32 4, i32 5, i32 12, i32 13>373 ret <8 x i32> %out374}375 376define <8 x i32> @zipodd_v8i32_as_v4i64(<8 x i32> %v1, <8 x i32> %v2) {377; CHECK-LABEL: zipodd_v8i32_as_v4i64:378; CHECK: # %bb.0:379; CHECK-NEXT: li a0, 51380; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu381; CHECK-NEXT: vmv.s.x v0, a0382; CHECK-NEXT: vslidedown.vi v10, v8, 2, v0.t383; CHECK-NEXT: vmv.v.v v8, v10384; CHECK-NEXT: ret385;386; ZIP-LABEL: zipodd_v8i32_as_v4i64:387; ZIP: # %bb.0:388; ZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma389; ZIP-NEXT: ri.vzipodd.vv v12, v8, v10390; ZIP-NEXT: vmv.v.v v8, v12391; ZIP-NEXT: ret392 %out = shufflevector <8 x i32> %v1, <8 x i32> %v2, <8 x i32> <i32 2, i32 3, i32 10, i32 11, i32 6, i32 7, i32 14, i32 15>393 ret <8 x i32> %out394}395 396;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:397; RV32: {{.*}}398; RV64: {{.*}}399; ZIP-RV32: {{.*}}400; ZIP-RV64: {{.*}}401