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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfh < %s | FileCheck %s \3; RUN: --check-prefixes=CHECK,ZVFH4; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfh < %s | FileCheck %s \5; RUN: --check-prefixes=CHECK,ZVFH6; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfhmin < %s | FileCheck %s \7; RUN: --check-prefixes=CHECK,ZVFHMIN8; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfhmin < %s | FileCheck %s \9; RUN: --check-prefixes=CHECK,ZVFHMIN10 11define <4 x half> @vsitofp_v4f16_v4i7(<4 x i7> %va, <4 x i1> %m, i32 zeroext %evl) {12; ZVFH-LABEL: vsitofp_v4f16_v4i7:13; ZVFH: # %bb.0:14; ZVFH-NEXT: vsetivli zero, 4, e8, mf4, ta, ma15; ZVFH-NEXT: vadd.vv v8, v8, v816; ZVFH-NEXT: vsra.vi v9, v8, 117; ZVFH-NEXT: vsetvli zero, a0, e8, mf4, ta, ma18; ZVFH-NEXT: vfwcvt.f.x.v v8, v9, v0.t19; ZVFH-NEXT: ret20;21; ZVFHMIN-LABEL: vsitofp_v4f16_v4i7:22; ZVFHMIN: # %bb.0:23; ZVFHMIN-NEXT: vsetivli zero, 4, e8, mf4, ta, ma24; ZVFHMIN-NEXT: vadd.vv v8, v8, v825; ZVFHMIN-NEXT: vsra.vi v8, v8, 126; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma27; ZVFHMIN-NEXT: vsext.vf2 v9, v8, v0.t28; ZVFHMIN-NEXT: vfwcvt.f.x.v v10, v9, v0.t29; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma30; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v1031; ZVFHMIN-NEXT: ret32 %v = call <4 x half> @llvm.vp.sitofp.v4f16.v4i7(<4 x i7> %va, <4 x i1> %m, i32 %evl)33 ret <4 x half> %v34}35 36define <4 x half> @vsitofp_v4f16_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {37; ZVFH-LABEL: vsitofp_v4f16_v4i8:38; ZVFH: # %bb.0:39; ZVFH-NEXT: vsetvli zero, a0, e8, mf4, ta, ma40; ZVFH-NEXT: vfwcvt.f.x.v v9, v8, v0.t41; ZVFH-NEXT: vmv1r.v v8, v942; ZVFH-NEXT: ret43;44; ZVFHMIN-LABEL: vsitofp_v4f16_v4i8:45; ZVFHMIN: # %bb.0:46; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma47; ZVFHMIN-NEXT: vsext.vf2 v9, v8, v0.t48; ZVFHMIN-NEXT: vfwcvt.f.x.v v10, v9, v0.t49; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma50; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v1051; ZVFHMIN-NEXT: ret52 %v = call <4 x half> @llvm.vp.sitofp.v4f16.v4i8(<4 x i8> %va, <4 x i1> %m, i32 %evl)53 ret <4 x half> %v54}55 56define <4 x half> @vsitofp_v4f16_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {57; ZVFH-LABEL: vsitofp_v4f16_v4i8_unmasked:58; ZVFH: # %bb.0:59; ZVFH-NEXT: vsetvli zero, a0, e8, mf4, ta, ma60; ZVFH-NEXT: vfwcvt.f.x.v v9, v861; ZVFH-NEXT: vmv1r.v v8, v962; ZVFH-NEXT: ret63;64; ZVFHMIN-LABEL: vsitofp_v4f16_v4i8_unmasked:65; ZVFHMIN: # %bb.0:66; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma67; ZVFHMIN-NEXT: vsext.vf2 v9, v868; ZVFHMIN-NEXT: vfwcvt.f.x.v v10, v969; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma70; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v1071; ZVFHMIN-NEXT: ret72 %v = call <4 x half> @llvm.vp.sitofp.v4f16.v4i8(<4 x i8> %va, <4 x i1> splat (i1 true), i32 %evl)73 ret <4 x half> %v74}75 76define <4 x half> @vsitofp_v4f16_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {77; ZVFH-LABEL: vsitofp_v4f16_v4i16:78; ZVFH: # %bb.0:79; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma80; ZVFH-NEXT: vfcvt.f.x.v v8, v8, v0.t81; ZVFH-NEXT: ret82;83; ZVFHMIN-LABEL: vsitofp_v4f16_v4i16:84; ZVFHMIN: # %bb.0:85; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma86; ZVFHMIN-NEXT: vfwcvt.f.x.v v9, v8, v0.t87; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma88; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v989; ZVFHMIN-NEXT: ret90 %v = call <4 x half> @llvm.vp.sitofp.v4f16.v4i16(<4 x i16> %va, <4 x i1> %m, i32 %evl)91 ret <4 x half> %v92}93 94define <4 x half> @vsitofp_v4f16_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {95; ZVFH-LABEL: vsitofp_v4f16_v4i16_unmasked:96; ZVFH: # %bb.0:97; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma98; ZVFH-NEXT: vfcvt.f.x.v v8, v899; ZVFH-NEXT: ret100;101; ZVFHMIN-LABEL: vsitofp_v4f16_v4i16_unmasked:102; ZVFHMIN: # %bb.0:103; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma104; ZVFHMIN-NEXT: vfwcvt.f.x.v v9, v8105; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma106; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9107; ZVFHMIN-NEXT: ret108 %v = call <4 x half> @llvm.vp.sitofp.v4f16.v4i16(<4 x i16> %va, <4 x i1> splat (i1 true), i32 %evl)109 ret <4 x half> %v110}111 112define <4 x half> @vsitofp_v4f16_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {113; ZVFH-LABEL: vsitofp_v4f16_v4i32:114; ZVFH: # %bb.0:115; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma116; ZVFH-NEXT: vfncvt.f.x.w v9, v8, v0.t117; ZVFH-NEXT: vmv1r.v v8, v9118; ZVFH-NEXT: ret119;120; ZVFHMIN-LABEL: vsitofp_v4f16_v4i32:121; ZVFHMIN: # %bb.0:122; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma123; ZVFHMIN-NEXT: vfcvt.f.x.v v9, v8, v0.t124; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma125; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9126; ZVFHMIN-NEXT: ret127 %v = call <4 x half> @llvm.vp.sitofp.v4f16.v4i32(<4 x i32> %va, <4 x i1> %m, i32 %evl)128 ret <4 x half> %v129}130 131define <4 x half> @vsitofp_v4f16_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {132; ZVFH-LABEL: vsitofp_v4f16_v4i32_unmasked:133; ZVFH: # %bb.0:134; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma135; ZVFH-NEXT: vfncvt.f.x.w v9, v8136; ZVFH-NEXT: vmv1r.v v8, v9137; ZVFH-NEXT: ret138;139; ZVFHMIN-LABEL: vsitofp_v4f16_v4i32_unmasked:140; ZVFHMIN: # %bb.0:141; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma142; ZVFHMIN-NEXT: vfcvt.f.x.v v9, v8143; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma144; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9145; ZVFHMIN-NEXT: ret146 %v = call <4 x half> @llvm.vp.sitofp.v4f16.v4i32(<4 x i32> %va, <4 x i1> splat (i1 true), i32 %evl)147 ret <4 x half> %v148}149 150define <4 x half> @vsitofp_v4f16_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {151; ZVFH-LABEL: vsitofp_v4f16_v4i64:152; ZVFH: # %bb.0:153; ZVFH-NEXT: vsetvli zero, a0, e32, m1, ta, ma154; ZVFH-NEXT: vfncvt.f.x.w v10, v8, v0.t155; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma156; ZVFH-NEXT: vfncvt.f.f.w v8, v10, v0.t157; ZVFH-NEXT: ret158;159; ZVFHMIN-LABEL: vsitofp_v4f16_v4i64:160; ZVFHMIN: # %bb.0:161; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma162; ZVFHMIN-NEXT: vfncvt.f.x.w v10, v8, v0.t163; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma164; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10165; ZVFHMIN-NEXT: ret166 %v = call <4 x half> @llvm.vp.sitofp.v4f16.v4i64(<4 x i64> %va, <4 x i1> %m, i32 %evl)167 ret <4 x half> %v168}169 170define <4 x half> @vsitofp_v4f16_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {171; ZVFH-LABEL: vsitofp_v4f16_v4i64_unmasked:172; ZVFH: # %bb.0:173; ZVFH-NEXT: vsetvli zero, a0, e32, m1, ta, ma174; ZVFH-NEXT: vfncvt.f.x.w v10, v8175; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma176; ZVFH-NEXT: vfncvt.f.f.w v8, v10177; ZVFH-NEXT: ret178;179; ZVFHMIN-LABEL: vsitofp_v4f16_v4i64_unmasked:180; ZVFHMIN: # %bb.0:181; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma182; ZVFHMIN-NEXT: vfncvt.f.x.w v10, v8183; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma184; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10185; ZVFHMIN-NEXT: ret186 %v = call <4 x half> @llvm.vp.sitofp.v4f16.v4i64(<4 x i64> %va, <4 x i1> splat (i1 true), i32 %evl)187 ret <4 x half> %v188}189 190define <4 x float> @vsitofp_v4f32_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {191; CHECK-LABEL: vsitofp_v4f32_v4i8:192; CHECK: # %bb.0:193; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma194; CHECK-NEXT: vsext.vf2 v9, v8, v0.t195; CHECK-NEXT: vfwcvt.f.x.v v8, v9, v0.t196; CHECK-NEXT: ret197 %v = call <4 x float> @llvm.vp.sitofp.v4f32.v4i8(<4 x i8> %va, <4 x i1> %m, i32 %evl)198 ret <4 x float> %v199}200 201define <4 x float> @vsitofp_v4f32_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {202; CHECK-LABEL: vsitofp_v4f32_v4i8_unmasked:203; CHECK: # %bb.0:204; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma205; CHECK-NEXT: vsext.vf2 v9, v8206; CHECK-NEXT: vfwcvt.f.x.v v8, v9207; CHECK-NEXT: ret208 %v = call <4 x float> @llvm.vp.sitofp.v4f32.v4i8(<4 x i8> %va, <4 x i1> splat (i1 true), i32 %evl)209 ret <4 x float> %v210}211 212define <4 x float> @vsitofp_v4f32_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {213; CHECK-LABEL: vsitofp_v4f32_v4i16:214; CHECK: # %bb.0:215; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma216; CHECK-NEXT: vfwcvt.f.x.v v9, v8, v0.t217; CHECK-NEXT: vmv1r.v v8, v9218; CHECK-NEXT: ret219 %v = call <4 x float> @llvm.vp.sitofp.v4f32.v4i16(<4 x i16> %va, <4 x i1> %m, i32 %evl)220 ret <4 x float> %v221}222 223define <4 x float> @vsitofp_v4f32_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {224; CHECK-LABEL: vsitofp_v4f32_v4i16_unmasked:225; CHECK: # %bb.0:226; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma227; CHECK-NEXT: vfwcvt.f.x.v v9, v8228; CHECK-NEXT: vmv1r.v v8, v9229; CHECK-NEXT: ret230 %v = call <4 x float> @llvm.vp.sitofp.v4f32.v4i16(<4 x i16> %va, <4 x i1> splat (i1 true), i32 %evl)231 ret <4 x float> %v232}233 234define <4 x float> @vsitofp_v4f32_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {235; CHECK-LABEL: vsitofp_v4f32_v4i32:236; CHECK: # %bb.0:237; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma238; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t239; CHECK-NEXT: ret240 %v = call <4 x float> @llvm.vp.sitofp.v4f32.v4i32(<4 x i32> %va, <4 x i1> %m, i32 %evl)241 ret <4 x float> %v242}243 244define <4 x float> @vsitofp_v4f32_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {245; CHECK-LABEL: vsitofp_v4f32_v4i32_unmasked:246; CHECK: # %bb.0:247; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma248; CHECK-NEXT: vfcvt.f.x.v v8, v8249; CHECK-NEXT: ret250 %v = call <4 x float> @llvm.vp.sitofp.v4f32.v4i32(<4 x i32> %va, <4 x i1> splat (i1 true), i32 %evl)251 ret <4 x float> %v252}253 254define <4 x float> @vsitofp_v4f32_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {255; CHECK-LABEL: vsitofp_v4f32_v4i64:256; CHECK: # %bb.0:257; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma258; CHECK-NEXT: vfncvt.f.x.w v10, v8, v0.t259; CHECK-NEXT: vmv.v.v v8, v10260; CHECK-NEXT: ret261 %v = call <4 x float> @llvm.vp.sitofp.v4f32.v4i64(<4 x i64> %va, <4 x i1> %m, i32 %evl)262 ret <4 x float> %v263}264 265define <4 x float> @vsitofp_v4f32_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {266; CHECK-LABEL: vsitofp_v4f32_v4i64_unmasked:267; CHECK: # %bb.0:268; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma269; CHECK-NEXT: vfncvt.f.x.w v10, v8270; CHECK-NEXT: vmv.v.v v8, v10271; CHECK-NEXT: ret272 %v = call <4 x float> @llvm.vp.sitofp.v4f32.v4i64(<4 x i64> %va, <4 x i1> splat (i1 true), i32 %evl)273 ret <4 x float> %v274}275 276define <4 x double> @vsitofp_v4f64_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {277; CHECK-LABEL: vsitofp_v4f64_v4i8:278; CHECK: # %bb.0:279; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma280; CHECK-NEXT: vsext.vf4 v10, v8, v0.t281; CHECK-NEXT: vfwcvt.f.x.v v8, v10, v0.t282; CHECK-NEXT: ret283 %v = call <4 x double> @llvm.vp.sitofp.v4f64.v4i8(<4 x i8> %va, <4 x i1> %m, i32 %evl)284 ret <4 x double> %v285}286 287define <4 x double> @vsitofp_v4f64_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {288; CHECK-LABEL: vsitofp_v4f64_v4i8_unmasked:289; CHECK: # %bb.0:290; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma291; CHECK-NEXT: vsext.vf4 v10, v8292; CHECK-NEXT: vfwcvt.f.x.v v8, v10293; CHECK-NEXT: ret294 %v = call <4 x double> @llvm.vp.sitofp.v4f64.v4i8(<4 x i8> %va, <4 x i1> splat (i1 true), i32 %evl)295 ret <4 x double> %v296}297 298define <4 x double> @vsitofp_v4f64_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {299; CHECK-LABEL: vsitofp_v4f64_v4i16:300; CHECK: # %bb.0:301; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma302; CHECK-NEXT: vsext.vf2 v10, v8, v0.t303; CHECK-NEXT: vfwcvt.f.x.v v8, v10, v0.t304; CHECK-NEXT: ret305 %v = call <4 x double> @llvm.vp.sitofp.v4f64.v4i16(<4 x i16> %va, <4 x i1> %m, i32 %evl)306 ret <4 x double> %v307}308 309define <4 x double> @vsitofp_v4f64_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {310; CHECK-LABEL: vsitofp_v4f64_v4i16_unmasked:311; CHECK: # %bb.0:312; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma313; CHECK-NEXT: vsext.vf2 v10, v8314; CHECK-NEXT: vfwcvt.f.x.v v8, v10315; CHECK-NEXT: ret316 %v = call <4 x double> @llvm.vp.sitofp.v4f64.v4i16(<4 x i16> %va, <4 x i1> splat (i1 true), i32 %evl)317 ret <4 x double> %v318}319 320define <4 x double> @vsitofp_v4f64_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {321; CHECK-LABEL: vsitofp_v4f64_v4i32:322; CHECK: # %bb.0:323; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma324; CHECK-NEXT: vmv1r.v v10, v8325; CHECK-NEXT: vfwcvt.f.x.v v8, v10, v0.t326; CHECK-NEXT: ret327 %v = call <4 x double> @llvm.vp.sitofp.v4f64.v4i32(<4 x i32> %va, <4 x i1> %m, i32 %evl)328 ret <4 x double> %v329}330 331define <4 x double> @vsitofp_v4f64_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {332; CHECK-LABEL: vsitofp_v4f64_v4i32_unmasked:333; CHECK: # %bb.0:334; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma335; CHECK-NEXT: vmv1r.v v10, v8336; CHECK-NEXT: vfwcvt.f.x.v v8, v10337; CHECK-NEXT: ret338 %v = call <4 x double> @llvm.vp.sitofp.v4f64.v4i32(<4 x i32> %va, <4 x i1> splat (i1 true), i32 %evl)339 ret <4 x double> %v340}341 342define <4 x double> @vsitofp_v4f64_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {343; CHECK-LABEL: vsitofp_v4f64_v4i64:344; CHECK: # %bb.0:345; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma346; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t347; CHECK-NEXT: ret348 %v = call <4 x double> @llvm.vp.sitofp.v4f64.v4i64(<4 x i64> %va, <4 x i1> %m, i32 %evl)349 ret <4 x double> %v350}351 352define <4 x double> @vsitofp_v4f64_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {353; CHECK-LABEL: vsitofp_v4f64_v4i64_unmasked:354; CHECK: # %bb.0:355; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma356; CHECK-NEXT: vfcvt.f.x.v v8, v8357; CHECK-NEXT: ret358 %v = call <4 x double> @llvm.vp.sitofp.v4f64.v4i64(<4 x i64> %va, <4 x i1> splat (i1 true), i32 %evl)359 ret <4 x double> %v360}361 362define <32 x double> @vsitofp_v32f64_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) {363; CHECK-LABEL: vsitofp_v32f64_v32i64:364; CHECK: # %bb.0:365; CHECK-NEXT: li a2, 16366; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma367; CHECK-NEXT: vslidedown.vi v24, v0, 2368; CHECK-NEXT: mv a1, a0369; CHECK-NEXT: bltu a0, a2, .LBB25_2370; CHECK-NEXT: # %bb.1:371; CHECK-NEXT: li a1, 16372; CHECK-NEXT: .LBB25_2:373; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma374; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t375; CHECK-NEXT: addi a1, a0, -16376; CHECK-NEXT: sltu a0, a0, a1377; CHECK-NEXT: addi a0, a0, -1378; CHECK-NEXT: and a0, a0, a1379; CHECK-NEXT: vmv1r.v v0, v24380; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma381; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t382; CHECK-NEXT: ret383 %v = call <32 x double> @llvm.vp.sitofp.v32f64.v32i64(<32 x i64> %va, <32 x i1> %m, i32 %evl)384 ret <32 x double> %v385}386 387define <32 x double> @vsitofp_v32f64_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {388; CHECK-LABEL: vsitofp_v32f64_v32i64_unmasked:389; CHECK: # %bb.0:390; CHECK-NEXT: li a2, 16391; CHECK-NEXT: mv a1, a0392; CHECK-NEXT: bltu a0, a2, .LBB26_2393; CHECK-NEXT: # %bb.1:394; CHECK-NEXT: li a1, 16395; CHECK-NEXT: .LBB26_2:396; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma397; CHECK-NEXT: vfcvt.f.x.v v8, v8398; CHECK-NEXT: addi a1, a0, -16399; CHECK-NEXT: sltu a0, a0, a1400; CHECK-NEXT: addi a0, a0, -1401; CHECK-NEXT: and a0, a0, a1402; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma403; CHECK-NEXT: vfcvt.f.x.v v16, v16404; CHECK-NEXT: ret405 %v = call <32 x double> @llvm.vp.sitofp.v32f64.v32i64(<32 x i64> %va, <32 x i1> splat (i1 true), i32 %evl)406 ret <32 x double> %v407}408