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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s4 5define <2 x i8> @stepvector_v2i8() {6; CHECK-LABEL: stepvector_v2i8:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma9; CHECK-NEXT: vid.v v810; CHECK-NEXT: ret11 %v = call <2 x i8> @llvm.stepvector.v2i8()12 ret <2 x i8> %v13}14 15define <3 x i8> @stepvector_v3i8() {16; CHECK-LABEL: stepvector_v3i8:17; CHECK: # %bb.0:18; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma19; CHECK-NEXT: vid.v v820; CHECK-NEXT: ret21 %v = call <3 x i8> @llvm.stepvector.v3i8()22 ret <3 x i8> %v23}24 25define <4 x i8> @stepvector_v4i8() {26; CHECK-LABEL: stepvector_v4i8:27; CHECK: # %bb.0:28; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma29; CHECK-NEXT: vid.v v830; CHECK-NEXT: ret31 %v = call <4 x i8> @llvm.stepvector.v4i8()32 ret <4 x i8> %v33}34 35define <8 x i8> @stepvector_v8i8() {36; CHECK-LABEL: stepvector_v8i8:37; CHECK: # %bb.0:38; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma39; CHECK-NEXT: vid.v v840; CHECK-NEXT: ret41 %v = call <8 x i8> @llvm.stepvector.v8i8()42 ret <8 x i8> %v43}44 45define <16 x i8> @stepvector_v16i8() {46; CHECK-LABEL: stepvector_v16i8:47; CHECK: # %bb.0:48; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma49; CHECK-NEXT: vid.v v850; CHECK-NEXT: ret51 %v = call <16 x i8> @llvm.stepvector.v16i8()52 ret <16 x i8> %v53}54 55define <2 x i16> @stepvector_v2i16() {56; CHECK-LABEL: stepvector_v2i16:57; CHECK: # %bb.0:58; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma59; CHECK-NEXT: vid.v v860; CHECK-NEXT: ret61 %v = call <2 x i16> @llvm.stepvector.v2i16()62 ret <2 x i16> %v63}64 65define <4 x i16> @stepvector_v4i16() {66; CHECK-LABEL: stepvector_v4i16:67; CHECK: # %bb.0:68; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma69; CHECK-NEXT: vid.v v870; CHECK-NEXT: ret71 %v = call <4 x i16> @llvm.stepvector.v4i16()72 ret <4 x i16> %v73}74 75define <8 x i16> @stepvector_v8i16() {76; CHECK-LABEL: stepvector_v8i16:77; CHECK: # %bb.0:78; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma79; CHECK-NEXT: vid.v v880; CHECK-NEXT: ret81 %v = call <8 x i16> @llvm.stepvector.v8i16()82 ret <8 x i16> %v83}84 85define <16 x i16> @stepvector_v16i16() {86; CHECK-LABEL: stepvector_v16i16:87; CHECK: # %bb.0:88; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma89; CHECK-NEXT: vid.v v890; CHECK-NEXT: ret91 %v = call <16 x i16> @llvm.stepvector.v16i16()92 ret <16 x i16> %v93}94 95define <2 x i32> @stepvector_v2i32() {96; CHECK-LABEL: stepvector_v2i32:97; CHECK: # %bb.0:98; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma99; CHECK-NEXT: vid.v v8100; CHECK-NEXT: ret101 %v = call <2 x i32> @llvm.stepvector.v2i32()102 ret <2 x i32> %v103}104 105define <4 x i32> @stepvector_v4i32() {106; CHECK-LABEL: stepvector_v4i32:107; CHECK: # %bb.0:108; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma109; CHECK-NEXT: vid.v v8110; CHECK-NEXT: ret111 %v = call <4 x i32> @llvm.stepvector.v4i32()112 ret <4 x i32> %v113}114 115define <8 x i32> @stepvector_v8i32() {116; CHECK-LABEL: stepvector_v8i32:117; CHECK: # %bb.0:118; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma119; CHECK-NEXT: vid.v v8120; CHECK-NEXT: ret121 %v = call <8 x i32> @llvm.stepvector.v8i32()122 ret <8 x i32> %v123}124 125define <16 x i32> @stepvector_v16i32() {126; CHECK-LABEL: stepvector_v16i32:127; CHECK: # %bb.0:128; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma129; CHECK-NEXT: vid.v v8130; CHECK-NEXT: ret131 %v = call <16 x i32> @llvm.stepvector.v16i32()132 ret <16 x i32> %v133}134 135define <2 x i64> @stepvector_v2i64() {136; CHECK-LABEL: stepvector_v2i64:137; CHECK: # %bb.0:138; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma139; CHECK-NEXT: vid.v v8140; CHECK-NEXT: ret141 %v = call <2 x i64> @llvm.stepvector.v2i64()142 ret <2 x i64> %v143}144 145define <4 x i64> @stepvector_v4i64() {146; CHECK-LABEL: stepvector_v4i64:147; CHECK: # %bb.0:148; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma149; CHECK-NEXT: vid.v v8150; CHECK-NEXT: ret151 %v = call <4 x i64> @llvm.stepvector.v4i64()152 ret <4 x i64> %v153}154 155define <8 x i64> @stepvector_v8i64() {156; CHECK-LABEL: stepvector_v8i64:157; CHECK: # %bb.0:158; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma159; CHECK-NEXT: vid.v v8160; CHECK-NEXT: ret161 %v = call <8 x i64> @llvm.stepvector.v8i64()162 ret <8 x i64> %v163}164 165define <16 x i64> @stepvector_v16i64() {166; CHECK-LABEL: stepvector_v16i64:167; CHECK: # %bb.0:168; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma169; CHECK-NEXT: vid.v v8170; CHECK-NEXT: ret171 %v = call <16 x i64> @llvm.stepvector.v16i64()172 ret <16 x i64> %v173}174