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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+v,+zvfh,+zvfbfmin,+optimized-zero-stride-load \3; RUN: -verify-machineinstrs < %s \4; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,CHECK-OPT5; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+v,+zvfh,+zvfbfmin,+optimized-zero-stride-load \6; RUN: -verify-machineinstrs < %s \7; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,CHECK-OPT8; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+v,+zvfh,+zvfbfmin \9; RUN: -verify-machineinstrs < %s \10; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,CHECK-NO-OPT,CHECK-NO-OPT-ZVFH11; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+v,+zvfh,+zvfbfmin \12; RUN: -verify-machineinstrs < %s \13; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,CHECK-NO-OPT,CHECK-NO-OPT-ZVFH14; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+v,+zvfhmin,+zvfbfmin,+optimized-zero-stride-load \15; RUN: -verify-machineinstrs < %s \16; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,CHECK-OPT17; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+v,+zvfhmin,+zvfbfmin,+optimized-zero-stride-load \18; RUN: -verify-machineinstrs < %s \19; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,CHECK-OPT20; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+v,+zvfhmin,+zvfbfmin \21; RUN: -verify-machineinstrs < %s \22; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,CHECK-NO-OPT,CHECK-NO-OPT-ZVFHMIN23; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+v,+zvfhmin,+zvfbfmin \24; RUN: -verify-machineinstrs < %s \25; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,CHECK-NO-OPT,CHECK-NO-OPT-ZVFHMIN26 27define <2 x i8> @strided_vpload_v2i8_i8(ptr %ptr, i8 signext %stride, <2 x i1> %m, i32 zeroext %evl) {28; CHECK-LABEL: strided_vpload_v2i8_i8:29; CHECK: # %bb.0:30; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, ma31; CHECK-NEXT: vlse8.v v8, (a0), a1, v0.t32; CHECK-NEXT: ret33 %load = call <2 x i8> @llvm.experimental.vp.strided.load.v2i8.p0.i8(ptr %ptr, i8 %stride, <2 x i1> %m, i32 %evl)34 ret <2 x i8> %load35}36 37define <2 x i8> @strided_vpload_v2i8_i16(ptr %ptr, i16 signext %stride, <2 x i1> %m, i32 zeroext %evl) {38; CHECK-LABEL: strided_vpload_v2i8_i16:39; CHECK: # %bb.0:40; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, ma41; CHECK-NEXT: vlse8.v v8, (a0), a1, v0.t42; CHECK-NEXT: ret43 %load = call <2 x i8> @llvm.experimental.vp.strided.load.v2i8.p0.i16(ptr %ptr, i16 %stride, <2 x i1> %m, i32 %evl)44 ret <2 x i8> %load45}46 47define <2 x i8> @strided_vpload_v2i8_i64(ptr %ptr, i64 signext %stride, <2 x i1> %m, i32 zeroext %evl) {48; CHECK-RV32-LABEL: strided_vpload_v2i8_i64:49; CHECK-RV32: # %bb.0:50; CHECK-RV32-NEXT: vsetvli zero, a3, e8, mf8, ta, ma51; CHECK-RV32-NEXT: vlse8.v v8, (a0), a1, v0.t52; CHECK-RV32-NEXT: ret53;54; CHECK-RV64-LABEL: strided_vpload_v2i8_i64:55; CHECK-RV64: # %bb.0:56; CHECK-RV64-NEXT: vsetvli zero, a2, e8, mf8, ta, ma57; CHECK-RV64-NEXT: vlse8.v v8, (a0), a1, v0.t58; CHECK-RV64-NEXT: ret59 %load = call <2 x i8> @llvm.experimental.vp.strided.load.v2i8.p0.i64(ptr %ptr, i64 %stride, <2 x i1> %m, i32 %evl)60 ret <2 x i8> %load61}62 63define <2 x i8> @strided_vpload_v2i8(ptr %ptr, i32 signext %stride, <2 x i1> %m, i32 zeroext %evl) {64; CHECK-LABEL: strided_vpload_v2i8:65; CHECK: # %bb.0:66; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, ma67; CHECK-NEXT: vlse8.v v8, (a0), a1, v0.t68; CHECK-NEXT: ret69 %load = call <2 x i8> @llvm.experimental.vp.strided.load.v2i8.p0.i32(ptr %ptr, i32 %stride, <2 x i1> %m, i32 %evl)70 ret <2 x i8> %load71}72 73define <4 x i8> @strided_vpload_v4i8(ptr %ptr, i32 signext %stride, <4 x i1> %m, i32 zeroext %evl) {74; CHECK-LABEL: strided_vpload_v4i8:75; CHECK: # %bb.0:76; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, ma77; CHECK-NEXT: vlse8.v v8, (a0), a1, v0.t78; CHECK-NEXT: ret79 %load = call <4 x i8> @llvm.experimental.vp.strided.load.v4i8.p0.i32(ptr %ptr, i32 %stride, <4 x i1> %m, i32 %evl)80 ret <4 x i8> %load81}82 83define <4 x i8> @strided_vpload_v4i8_allones_mask(ptr %ptr, i32 signext %stride, i32 zeroext %evl) {84; CHECK-LABEL: strided_vpload_v4i8_allones_mask:85; CHECK: # %bb.0:86; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, ma87; CHECK-NEXT: vlse8.v v8, (a0), a188; CHECK-NEXT: ret89 %load = call <4 x i8> @llvm.experimental.vp.strided.load.v4i8.p0.i32(ptr %ptr, i32 %stride, <4 x i1> splat (i1 true), i32 %evl)90 ret <4 x i8> %load91}92 93define <8 x i8> @strided_vpload_v8i8(ptr %ptr, i32 signext %stride, <8 x i1> %m, i32 zeroext %evl) {94; CHECK-LABEL: strided_vpload_v8i8:95; CHECK: # %bb.0:96; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, ma97; CHECK-NEXT: vlse8.v v8, (a0), a1, v0.t98; CHECK-NEXT: ret99 %load = call <8 x i8> @llvm.experimental.vp.strided.load.v8i8.p0.i32(ptr %ptr, i32 %stride, <8 x i1> %m, i32 %evl)100 ret <8 x i8> %load101}102 103define <8 x i8> @strided_vpload_v8i8_unit_stride(ptr %ptr, <8 x i1> %m, i32 zeroext %evl) {104; CHECK-LABEL: strided_vpload_v8i8_unit_stride:105; CHECK: # %bb.0:106; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma107; CHECK-NEXT: vle8.v v8, (a0), v0.t108; CHECK-NEXT: ret109 %load = call <8 x i8> @llvm.experimental.vp.strided.load.v8i8.p0.i32(ptr %ptr, i32 1, <8 x i1> %m, i32 %evl)110 ret <8 x i8> %load111}112 113define <2 x i16> @strided_vpload_v2i16(ptr %ptr, i32 signext %stride, <2 x i1> %m, i32 zeroext %evl) {114; CHECK-LABEL: strided_vpload_v2i16:115; CHECK: # %bb.0:116; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, ma117; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t118; CHECK-NEXT: ret119 %load = call <2 x i16> @llvm.experimental.vp.strided.load.v2i16.p0.i32(ptr %ptr, i32 %stride, <2 x i1> %m, i32 %evl)120 ret <2 x i16> %load121}122 123define <4 x i16> @strided_vpload_v4i16(ptr %ptr, i32 signext %stride, <4 x i1> %m, i32 zeroext %evl) {124; CHECK-LABEL: strided_vpload_v4i16:125; CHECK: # %bb.0:126; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, ma127; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t128; CHECK-NEXT: ret129 %load = call <4 x i16> @llvm.experimental.vp.strided.load.v4i16.p0.i32(ptr %ptr, i32 %stride, <4 x i1> %m, i32 %evl)130 ret <4 x i16> %load131}132 133define <8 x i16> @strided_vpload_v8i16(ptr %ptr, i32 signext %stride, <8 x i1> %m, i32 zeroext %evl) {134; CHECK-LABEL: strided_vpload_v8i16:135; CHECK: # %bb.0:136; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, ma137; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t138; CHECK-NEXT: ret139 %load = call <8 x i16> @llvm.experimental.vp.strided.load.v8i16.p0.i32(ptr %ptr, i32 %stride, <8 x i1> %m, i32 %evl)140 ret <8 x i16> %load141}142 143define <8 x i16> @strided_vpload_v8i16_unit_stride(ptr %ptr, <8 x i1> %m, i32 zeroext %evl) {144; CHECK-LABEL: strided_vpload_v8i16_unit_stride:145; CHECK: # %bb.0:146; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma147; CHECK-NEXT: vle16.v v8, (a0), v0.t148; CHECK-NEXT: ret149 %load = call <8 x i16> @llvm.experimental.vp.strided.load.v8i16.p0.i32(ptr %ptr, i32 2, <8 x i1> %m, i32 %evl)150 ret <8 x i16> %load151}152 153define <8 x i16> @strided_vpload_v8i16_allones_mask(ptr %ptr, i32 signext %stride, i32 zeroext %evl) {154; CHECK-LABEL: strided_vpload_v8i16_allones_mask:155; CHECK: # %bb.0:156; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, ma157; CHECK-NEXT: vlse16.v v8, (a0), a1158; CHECK-NEXT: ret159 %load = call <8 x i16> @llvm.experimental.vp.strided.load.v8i16.p0.i32(ptr %ptr, i32 %stride, <8 x i1> splat (i1 true), i32 %evl)160 ret <8 x i16> %load161}162 163define <2 x i32> @strided_vpload_v2i32(ptr %ptr, i32 signext %stride, <2 x i1> %m, i32 zeroext %evl) {164; CHECK-LABEL: strided_vpload_v2i32:165; CHECK: # %bb.0:166; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, ma167; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t168; CHECK-NEXT: ret169 %load = call <2 x i32> @llvm.experimental.vp.strided.load.v2i32.p0.i32(ptr %ptr, i32 %stride, <2 x i1> %m, i32 %evl)170 ret <2 x i32> %load171}172 173define <4 x i32> @strided_vpload_v4i32(ptr %ptr, i32 signext %stride, <4 x i1> %m, i32 zeroext %evl) {174; CHECK-LABEL: strided_vpload_v4i32:175; CHECK: # %bb.0:176; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, ma177; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t178; CHECK-NEXT: ret179 %load = call <4 x i32> @llvm.experimental.vp.strided.load.v4i32.p0.i32(ptr %ptr, i32 %stride, <4 x i1> %m, i32 %evl)180 ret <4 x i32> %load181}182 183define <4 x i32> @strided_vpload_v4i32_unit_stride(ptr %ptr, <4 x i1> %m, i32 zeroext %evl) {184; CHECK-LABEL: strided_vpload_v4i32_unit_stride:185; CHECK: # %bb.0:186; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma187; CHECK-NEXT: vle32.v v8, (a0), v0.t188; CHECK-NEXT: ret189 %load = call <4 x i32> @llvm.experimental.vp.strided.load.v4i32.p0.i32(ptr %ptr, i32 4, <4 x i1> %m, i32 %evl)190 ret <4 x i32> %load191}192 193define <8 x i32> @strided_vpload_v8i32(ptr %ptr, i32 signext %stride, <8 x i1> %m, i32 zeroext %evl) {194; CHECK-LABEL: strided_vpload_v8i32:195; CHECK: # %bb.0:196; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, ma197; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t198; CHECK-NEXT: ret199 %load = call <8 x i32> @llvm.experimental.vp.strided.load.v8i32.p0.i32(ptr %ptr, i32 %stride, <8 x i1> %m, i32 %evl)200 ret <8 x i32> %load201}202 203define <8 x i32> @strided_vpload_v8i32_allones_mask(ptr %ptr, i32 signext %stride, i32 zeroext %evl) {204; CHECK-LABEL: strided_vpload_v8i32_allones_mask:205; CHECK: # %bb.0:206; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, ma207; CHECK-NEXT: vlse32.v v8, (a0), a1208; CHECK-NEXT: ret209 %load = call <8 x i32> @llvm.experimental.vp.strided.load.v8i32.p0.i32(ptr %ptr, i32 %stride, <8 x i1> splat (i1 true), i32 %evl)210 ret <8 x i32> %load211}212 213define <2 x i64> @strided_vpload_v2i64(ptr %ptr, i32 signext %stride, <2 x i1> %m, i32 zeroext %evl) {214; CHECK-LABEL: strided_vpload_v2i64:215; CHECK: # %bb.0:216; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, ma217; CHECK-NEXT: vlse64.v v8, (a0), a1, v0.t218; CHECK-NEXT: ret219 %load = call <2 x i64> @llvm.experimental.vp.strided.load.v2i64.p0.i32(ptr %ptr, i32 %stride, <2 x i1> %m, i32 %evl)220 ret <2 x i64> %load221}222 223define <2 x i64> @strided_vpload_v2i64_unit_stride(ptr %ptr, <2 x i1> %m, i32 zeroext %evl) {224; CHECK-LABEL: strided_vpload_v2i64_unit_stride:225; CHECK: # %bb.0:226; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma227; CHECK-NEXT: vle64.v v8, (a0), v0.t228; CHECK-NEXT: ret229 %load = call <2 x i64> @llvm.experimental.vp.strided.load.v2i64.p0.i32(ptr %ptr, i32 8, <2 x i1> %m, i32 %evl)230 ret <2 x i64> %load231}232 233define <4 x i64> @strided_vpload_v4i64(ptr %ptr, i32 signext %stride, <4 x i1> %m, i32 zeroext %evl) {234; CHECK-LABEL: strided_vpload_v4i64:235; CHECK: # %bb.0:236; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, ma237; CHECK-NEXT: vlse64.v v8, (a0), a1, v0.t238; CHECK-NEXT: ret239 %load = call <4 x i64> @llvm.experimental.vp.strided.load.v4i64.p0.i32(ptr %ptr, i32 %stride, <4 x i1> %m, i32 %evl)240 ret <4 x i64> %load241}242 243define <4 x i64> @strided_vpload_v4i64_allones_mask(ptr %ptr, i32 signext %stride, i32 zeroext %evl) {244; CHECK-LABEL: strided_vpload_v4i64_allones_mask:245; CHECK: # %bb.0:246; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, ma247; CHECK-NEXT: vlse64.v v8, (a0), a1248; CHECK-NEXT: ret249 %load = call <4 x i64> @llvm.experimental.vp.strided.load.v4i64.p0.i32(ptr %ptr, i32 %stride, <4 x i1> splat (i1 true), i32 %evl)250 ret <4 x i64> %load251}252 253define <8 x i64> @strided_vpload_v8i64(ptr %ptr, i32 signext %stride, <8 x i1> %m, i32 zeroext %evl) {254; CHECK-LABEL: strided_vpload_v8i64:255; CHECK: # %bb.0:256; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, ma257; CHECK-NEXT: vlse64.v v8, (a0), a1, v0.t258; CHECK-NEXT: ret259 %load = call <8 x i64> @llvm.experimental.vp.strided.load.v8i64.p0.i32(ptr %ptr, i32 %stride, <8 x i1> %m, i32 %evl)260 ret <8 x i64> %load261}262 263define <2 x bfloat> @strided_vpload_v2bf16(ptr %ptr, i32 signext %stride, <2 x i1> %m, i32 zeroext %evl) {264; CHECK-LABEL: strided_vpload_v2bf16:265; CHECK: # %bb.0:266; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, ma267; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t268; CHECK-NEXT: ret269 %load = call <2 x bfloat> @llvm.experimental.vp.strided.load.v2bf16.p0.i32(ptr %ptr, i32 %stride, <2 x i1> %m, i32 %evl)270 ret <2 x bfloat> %load271}272 273define <2 x bfloat> @strided_vpload_v2bf16_allones_mask(ptr %ptr, i32 signext %stride, i32 zeroext %evl) {274; CHECK-LABEL: strided_vpload_v2bf16_allones_mask:275; CHECK: # %bb.0:276; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, ma277; CHECK-NEXT: vlse16.v v8, (a0), a1278; CHECK-NEXT: ret279 %load = call <2 x bfloat> @llvm.experimental.vp.strided.load.v2bf16.p0.i32(ptr %ptr, i32 %stride, <2 x i1> splat (i1 true), i32 %evl)280 ret <2 x bfloat> %load281}282 283define <4 x bfloat> @strided_vpload_v4bf16(ptr %ptr, i32 signext %stride, <4 x i1> %m, i32 zeroext %evl) {284; CHECK-LABEL: strided_vpload_v4bf16:285; CHECK: # %bb.0:286; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, ma287; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t288; CHECK-NEXT: ret289 %load = call <4 x bfloat> @llvm.experimental.vp.strided.load.v4bf16.p0.i32(ptr %ptr, i32 %stride, <4 x i1> %m, i32 %evl)290 ret <4 x bfloat> %load291}292 293define <8 x bfloat> @strided_vpload_v8bf16(ptr %ptr, i32 signext %stride, <8 x i1> %m, i32 zeroext %evl) {294; CHECK-LABEL: strided_vpload_v8bf16:295; CHECK: # %bb.0:296; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, ma297; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t298; CHECK-NEXT: ret299 %load = call <8 x bfloat> @llvm.experimental.vp.strided.load.v8bf16.p0.i32(ptr %ptr, i32 %stride, <8 x i1> %m, i32 %evl)300 ret <8 x bfloat> %load301}302 303define <8 x bfloat> @strided_vpload_v8bf16_unit_stride(ptr %ptr, <8 x i1> %m, i32 zeroext %evl) {304; CHECK-LABEL: strided_vpload_v8bf16_unit_stride:305; CHECK: # %bb.0:306; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma307; CHECK-NEXT: vle16.v v8, (a0), v0.t308; CHECK-NEXT: ret309 %load = call <8 x bfloat> @llvm.experimental.vp.strided.load.v8bf16.p0.i32(ptr %ptr, i32 2, <8 x i1> %m, i32 %evl)310 ret <8 x bfloat> %load311}312 313define <2 x half> @strided_vpload_v2f16(ptr %ptr, i32 signext %stride, <2 x i1> %m, i32 zeroext %evl) {314; CHECK-LABEL: strided_vpload_v2f16:315; CHECK: # %bb.0:316; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, ma317; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t318; CHECK-NEXT: ret319 %load = call <2 x half> @llvm.experimental.vp.strided.load.v2f16.p0.i32(ptr %ptr, i32 %stride, <2 x i1> %m, i32 %evl)320 ret <2 x half> %load321}322 323define <2 x half> @strided_vpload_v2f16_allones_mask(ptr %ptr, i32 signext %stride, i32 zeroext %evl) {324; CHECK-LABEL: strided_vpload_v2f16_allones_mask:325; CHECK: # %bb.0:326; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, ma327; CHECK-NEXT: vlse16.v v8, (a0), a1328; CHECK-NEXT: ret329 %load = call <2 x half> @llvm.experimental.vp.strided.load.v2f16.p0.i32(ptr %ptr, i32 %stride, <2 x i1> splat (i1 true), i32 %evl)330 ret <2 x half> %load331}332 333define <4 x half> @strided_vpload_v4f16(ptr %ptr, i32 signext %stride, <4 x i1> %m, i32 zeroext %evl) {334; CHECK-LABEL: strided_vpload_v4f16:335; CHECK: # %bb.0:336; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, ma337; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t338; CHECK-NEXT: ret339 %load = call <4 x half> @llvm.experimental.vp.strided.load.v4f16.p0.i32(ptr %ptr, i32 %stride, <4 x i1> %m, i32 %evl)340 ret <4 x half> %load341}342 343define <8 x half> @strided_vpload_v8f16(ptr %ptr, i32 signext %stride, <8 x i1> %m, i32 zeroext %evl) {344; CHECK-LABEL: strided_vpload_v8f16:345; CHECK: # %bb.0:346; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, ma347; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t348; CHECK-NEXT: ret349 %load = call <8 x half> @llvm.experimental.vp.strided.load.v8f16.p0.i32(ptr %ptr, i32 %stride, <8 x i1> %m, i32 %evl)350 ret <8 x half> %load351}352 353define <8 x half> @strided_vpload_v8f16_unit_stride(ptr %ptr, <8 x i1> %m, i32 zeroext %evl) {354; CHECK-LABEL: strided_vpload_v8f16_unit_stride:355; CHECK: # %bb.0:356; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma357; CHECK-NEXT: vle16.v v8, (a0), v0.t358; CHECK-NEXT: ret359 %load = call <8 x half> @llvm.experimental.vp.strided.load.v8f16.p0.i32(ptr %ptr, i32 2, <8 x i1> %m, i32 %evl)360 ret <8 x half> %load361}362 363define <2 x float> @strided_vpload_v2f32(ptr %ptr, i32 signext %stride, <2 x i1> %m, i32 zeroext %evl) {364; CHECK-LABEL: strided_vpload_v2f32:365; CHECK: # %bb.0:366; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, ma367; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t368; CHECK-NEXT: ret369 %load = call <2 x float> @llvm.experimental.vp.strided.load.v2f32.p0.i32(ptr %ptr, i32 %stride, <2 x i1> %m, i32 %evl)370 ret <2 x float> %load371}372 373define <4 x float> @strided_vpload_v4f32(ptr %ptr, i32 signext %stride, <4 x i1> %m, i32 zeroext %evl) {374; CHECK-LABEL: strided_vpload_v4f32:375; CHECK: # %bb.0:376; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, ma377; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t378; CHECK-NEXT: ret379 %load = call <4 x float> @llvm.experimental.vp.strided.load.v4f32.p0.i32(ptr %ptr, i32 %stride, <4 x i1> %m, i32 %evl)380 ret <4 x float> %load381}382 383define <4 x float> @strided_vpload_v4f32_unit_stride(ptr %ptr, <4 x i1> %m, i32 zeroext %evl) {384; CHECK-LABEL: strided_vpload_v4f32_unit_stride:385; CHECK: # %bb.0:386; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma387; CHECK-NEXT: vle32.v v8, (a0), v0.t388; CHECK-NEXT: ret389 %load = call <4 x float> @llvm.experimental.vp.strided.load.v4f32.p0.i32(ptr %ptr, i32 4, <4 x i1> %m, i32 %evl)390 ret <4 x float> %load391}392 393define <8 x float> @strided_vpload_v8f32(ptr %ptr, i32 signext %stride, <8 x i1> %m, i32 zeroext %evl) {394; CHECK-LABEL: strided_vpload_v8f32:395; CHECK: # %bb.0:396; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, ma397; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t398; CHECK-NEXT: ret399 %load = call <8 x float> @llvm.experimental.vp.strided.load.v8f32.p0.i32(ptr %ptr, i32 %stride, <8 x i1> %m, i32 %evl)400 ret <8 x float> %load401}402 403define <8 x float> @strided_vpload_v8f32_allones_mask(ptr %ptr, i32 signext %stride, i32 zeroext %evl) {404; CHECK-LABEL: strided_vpload_v8f32_allones_mask:405; CHECK: # %bb.0:406; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, ma407; CHECK-NEXT: vlse32.v v8, (a0), a1408; CHECK-NEXT: ret409 %load = call <8 x float> @llvm.experimental.vp.strided.load.v8f32.p0.i32(ptr %ptr, i32 %stride, <8 x i1> splat (i1 true), i32 %evl)410 ret <8 x float> %load411}412 413define <2 x double> @strided_vpload_v2f64(ptr %ptr, i32 signext %stride, <2 x i1> %m, i32 zeroext %evl) {414; CHECK-LABEL: strided_vpload_v2f64:415; CHECK: # %bb.0:416; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, ma417; CHECK-NEXT: vlse64.v v8, (a0), a1, v0.t418; CHECK-NEXT: ret419 %load = call <2 x double> @llvm.experimental.vp.strided.load.v2f64.p0.i32(ptr %ptr, i32 %stride, <2 x i1> %m, i32 %evl)420 ret <2 x double> %load421}422 423define <2 x double> @strided_vpload_v2f64_unit_stride(ptr %ptr, <2 x i1> %m, i32 zeroext %evl) {424; CHECK-LABEL: strided_vpload_v2f64_unit_stride:425; CHECK: # %bb.0:426; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma427; CHECK-NEXT: vle64.v v8, (a0), v0.t428; CHECK-NEXT: ret429 %load = call <2 x double> @llvm.experimental.vp.strided.load.v2f64.p0.i32(ptr %ptr, i32 8, <2 x i1> %m, i32 %evl)430 ret <2 x double> %load431}432 433define <4 x double> @strided_vpload_v4f64(ptr %ptr, i32 signext %stride, <4 x i1> %m, i32 zeroext %evl) {434; CHECK-LABEL: strided_vpload_v4f64:435; CHECK: # %bb.0:436; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, ma437; CHECK-NEXT: vlse64.v v8, (a0), a1, v0.t438; CHECK-NEXT: ret439 %load = call <4 x double> @llvm.experimental.vp.strided.load.v4f64.p0.i32(ptr %ptr, i32 %stride, <4 x i1> %m, i32 %evl)440 ret <4 x double> %load441}442 443define <4 x double> @strided_vpload_v4f64_allones_mask(ptr %ptr, i32 signext %stride, i32 zeroext %evl) {444; CHECK-LABEL: strided_vpload_v4f64_allones_mask:445; CHECK: # %bb.0:446; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, ma447; CHECK-NEXT: vlse64.v v8, (a0), a1448; CHECK-NEXT: ret449 %load = call <4 x double> @llvm.experimental.vp.strided.load.v4f64.p0.i32(ptr %ptr, i32 %stride, <4 x i1> splat (i1 true), i32 %evl)450 ret <4 x double> %load451}452 453define <8 x double> @strided_vpload_v8f64(ptr %ptr, i32 signext %stride, <8 x i1> %m, i32 zeroext %evl) {454; CHECK-LABEL: strided_vpload_v8f64:455; CHECK: # %bb.0:456; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, ma457; CHECK-NEXT: vlse64.v v8, (a0), a1, v0.t458; CHECK-NEXT: ret459 %load = call <8 x double> @llvm.experimental.vp.strided.load.v8f64.p0.i32(ptr %ptr, i32 %stride, <8 x i1> %m, i32 %evl)460 ret <8 x double> %load461}462 463; Widening464define <3 x double> @strided_vpload_v3f64(ptr %ptr, i32 signext %stride, <3 x i1> %mask, i32 zeroext %evl) {465; CHECK-LABEL: strided_vpload_v3f64:466; CHECK: # %bb.0:467; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, ma468; CHECK-NEXT: vlse64.v v8, (a0), a1, v0.t469; CHECK-NEXT: ret470 %v = call <3 x double> @llvm.experimental.vp.strided.load.v3f64.p0.i32(ptr %ptr, i32 %stride, <3 x i1> %mask, i32 %evl)471 ret <3 x double> %v472}473 474define <3 x double> @strided_vpload_v3f64_allones_mask(ptr %ptr, i32 signext %stride, i32 zeroext %evl) {475; CHECK-LABEL: strided_vpload_v3f64_allones_mask:476; CHECK: # %bb.0:477; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, ma478; CHECK-NEXT: vlse64.v v8, (a0), a1479; CHECK-NEXT: ret480 %v = call <3 x double> @llvm.experimental.vp.strided.load.v3f64.p0.i32(ptr %ptr, i32 %stride, <3 x i1> splat (i1 true), i32 %evl)481 ret <3 x double> %v482}483 484; Splitting485define <32 x double> @strided_vpload_v32f64(ptr %ptr, i32 signext %stride, <32 x i1> %m, i32 zeroext %evl) nounwind {486; CHECK-LABEL: strided_vpload_v32f64:487; CHECK: # %bb.0:488; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma489; CHECK-NEXT: vmv1r.v v9, v0490; CHECK-NEXT: li a4, 16491; CHECK-NEXT: mv a3, a2492; CHECK-NEXT: bltu a2, a4, .LBB45_2493; CHECK-NEXT: # %bb.1:494; CHECK-NEXT: li a3, 16495; CHECK-NEXT: .LBB45_2:496; CHECK-NEXT: mul a4, a3, a1497; CHECK-NEXT: addi a5, a2, -16498; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma499; CHECK-NEXT: vslidedown.vi v8, v9, 2500; CHECK-NEXT: add a4, a0, a4501; CHECK-NEXT: sltu a2, a2, a5502; CHECK-NEXT: addi a2, a2, -1503; CHECK-NEXT: and a2, a2, a5504; CHECK-NEXT: vmv1r.v v0, v8505; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma506; CHECK-NEXT: vlse64.v v16, (a4), a1, v0.t507; CHECK-NEXT: vmv1r.v v0, v9508; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, ma509; CHECK-NEXT: vlse64.v v8, (a0), a1, v0.t510; CHECK-NEXT: ret511 %load = call <32 x double> @llvm.experimental.vp.strided.load.v32f64.p0.i32(ptr %ptr, i32 %stride, <32 x i1> %m, i32 %evl)512 ret <32 x double> %load513}514 515define <32 x double> @strided_vpload_v32f64_allones_mask(ptr %ptr, i32 signext %stride, i32 zeroext %evl) nounwind {516; CHECK-LABEL: strided_vpload_v32f64_allones_mask:517; CHECK: # %bb.0:518; CHECK-NEXT: li a4, 16519; CHECK-NEXT: mv a3, a2520; CHECK-NEXT: bltu a2, a4, .LBB46_2521; CHECK-NEXT: # %bb.1:522; CHECK-NEXT: li a3, 16523; CHECK-NEXT: .LBB46_2:524; CHECK-NEXT: mul a4, a3, a1525; CHECK-NEXT: addi a5, a2, -16526; CHECK-NEXT: add a4, a0, a4527; CHECK-NEXT: sltu a2, a2, a5528; CHECK-NEXT: addi a2, a2, -1529; CHECK-NEXT: and a2, a2, a5530; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma531; CHECK-NEXT: vlse64.v v16, (a4), a1532; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, ma533; CHECK-NEXT: vlse64.v v8, (a0), a1534; CHECK-NEXT: ret535 %load = call <32 x double> @llvm.experimental.vp.strided.load.v32f64.p0.i32(ptr %ptr, i32 %stride, <32 x i1> splat (i1 true), i32 %evl)536 ret <32 x double> %load537}538 539; Widening + splitting (with HiIsEmpty == true)540define <33 x double> @strided_load_v33f64(ptr %ptr, i64 %stride, <33 x i1> %mask, i32 zeroext %evl) {541; CHECK-RV32-LABEL: strided_load_v33f64:542; CHECK-RV32: # %bb.0:543; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma544; CHECK-RV32-NEXT: vmv1r.v v8, v0545; CHECK-RV32-NEXT: li a5, 32546; CHECK-RV32-NEXT: mv a3, a4547; CHECK-RV32-NEXT: bltu a4, a5, .LBB47_2548; CHECK-RV32-NEXT: # %bb.1:549; CHECK-RV32-NEXT: li a3, 32550; CHECK-RV32-NEXT: .LBB47_2:551; CHECK-RV32-NEXT: mul a6, a3, a2552; CHECK-RV32-NEXT: addi a5, a4, -32553; CHECK-RV32-NEXT: sltu a7, a4, a5554; CHECK-RV32-NEXT: addi a7, a7, -1555; CHECK-RV32-NEXT: and a7, a7, a5556; CHECK-RV32-NEXT: li a5, 16557; CHECK-RV32-NEXT: add a6, a1, a6558; CHECK-RV32-NEXT: bltu a7, a5, .LBB47_4559; CHECK-RV32-NEXT: # %bb.3:560; CHECK-RV32-NEXT: li a7, 16561; CHECK-RV32-NEXT: .LBB47_4:562; CHECK-RV32-NEXT: vsetivli zero, 4, e8, mf2, ta, ma563; CHECK-RV32-NEXT: vslidedown.vi v0, v8, 4564; CHECK-RV32-NEXT: vsetvli zero, a7, e64, m8, ta, ma565; CHECK-RV32-NEXT: vlse64.v v16, (a6), a2, v0.t566; CHECK-RV32-NEXT: addi a6, a3, -16567; CHECK-RV32-NEXT: sltu a3, a3, a6568; CHECK-RV32-NEXT: addi a3, a3, -1569; CHECK-RV32-NEXT: and a3, a3, a6570; CHECK-RV32-NEXT: bltu a4, a5, .LBB47_6571; CHECK-RV32-NEXT: # %bb.5:572; CHECK-RV32-NEXT: li a4, 16573; CHECK-RV32-NEXT: .LBB47_6:574; CHECK-RV32-NEXT: mul a5, a4, a2575; CHECK-RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma576; CHECK-RV32-NEXT: vslidedown.vi v0, v8, 2577; CHECK-RV32-NEXT: add a5, a1, a5578; CHECK-RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma579; CHECK-RV32-NEXT: vlse64.v v24, (a5), a2, v0.t580; CHECK-RV32-NEXT: vmv1r.v v0, v8581; CHECK-RV32-NEXT: vsetvli zero, a4, e64, m8, ta, ma582; CHECK-RV32-NEXT: vlse64.v v8, (a1), a2, v0.t583; CHECK-RV32-NEXT: addi a1, a0, 128584; CHECK-RV32-NEXT: addi a2, a0, 256585; CHECK-RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma586; CHECK-RV32-NEXT: vse64.v v8, (a0)587; CHECK-RV32-NEXT: vse64.v v24, (a1)588; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma589; CHECK-RV32-NEXT: vse64.v v16, (a2)590; CHECK-RV32-NEXT: ret591;592; CHECK-RV64-LABEL: strided_load_v33f64:593; CHECK-RV64: # %bb.0:594; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma595; CHECK-RV64-NEXT: vmv1r.v v8, v0596; CHECK-RV64-NEXT: li a5, 32597; CHECK-RV64-NEXT: mv a4, a3598; CHECK-RV64-NEXT: bltu a3, a5, .LBB47_2599; CHECK-RV64-NEXT: # %bb.1:600; CHECK-RV64-NEXT: li a4, 32601; CHECK-RV64-NEXT: .LBB47_2:602; CHECK-RV64-NEXT: mul a6, a4, a2603; CHECK-RV64-NEXT: addi a5, a3, -32604; CHECK-RV64-NEXT: sltu a7, a3, a5605; CHECK-RV64-NEXT: addi a7, a7, -1606; CHECK-RV64-NEXT: and a7, a7, a5607; CHECK-RV64-NEXT: li a5, 16608; CHECK-RV64-NEXT: add a6, a1, a6609; CHECK-RV64-NEXT: bltu a7, a5, .LBB47_4610; CHECK-RV64-NEXT: # %bb.3:611; CHECK-RV64-NEXT: li a7, 16612; CHECK-RV64-NEXT: .LBB47_4:613; CHECK-RV64-NEXT: vsetivli zero, 4, e8, mf2, ta, ma614; CHECK-RV64-NEXT: vslidedown.vi v0, v8, 4615; CHECK-RV64-NEXT: vsetvli zero, a7, e64, m8, ta, ma616; CHECK-RV64-NEXT: vlse64.v v16, (a6), a2, v0.t617; CHECK-RV64-NEXT: addi a6, a4, -16618; CHECK-RV64-NEXT: sltu a4, a4, a6619; CHECK-RV64-NEXT: addi a4, a4, -1620; CHECK-RV64-NEXT: and a4, a4, a6621; CHECK-RV64-NEXT: bltu a3, a5, .LBB47_6622; CHECK-RV64-NEXT: # %bb.5:623; CHECK-RV64-NEXT: li a3, 16624; CHECK-RV64-NEXT: .LBB47_6:625; CHECK-RV64-NEXT: mul a5, a3, a2626; CHECK-RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma627; CHECK-RV64-NEXT: vslidedown.vi v0, v8, 2628; CHECK-RV64-NEXT: add a5, a1, a5629; CHECK-RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma630; CHECK-RV64-NEXT: vlse64.v v24, (a5), a2, v0.t631; CHECK-RV64-NEXT: vmv1r.v v0, v8632; CHECK-RV64-NEXT: vsetvli zero, a3, e64, m8, ta, ma633; CHECK-RV64-NEXT: vlse64.v v8, (a1), a2, v0.t634; CHECK-RV64-NEXT: addi a1, a0, 128635; CHECK-RV64-NEXT: addi a2, a0, 256636; CHECK-RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma637; CHECK-RV64-NEXT: vse64.v v8, (a0)638; CHECK-RV64-NEXT: vse64.v v24, (a1)639; CHECK-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma640; CHECK-RV64-NEXT: vse64.v v16, (a2)641; CHECK-RV64-NEXT: ret642 %v = call <33 x double> @llvm.experimental.vp.strided.load.v33f64.p0.i64(ptr %ptr, i64 %stride, <33 x i1> %mask, i32 %evl)643 ret <33 x double> %v644}645 646; Test unmasked integer zero strided647define <4 x i8> @zero_strided_unmasked_vpload_4i8_i8(ptr %ptr) {648; CHECK-OPT-LABEL: zero_strided_unmasked_vpload_4i8_i8:649; CHECK-OPT: # %bb.0:650; CHECK-OPT-NEXT: vsetivli zero, 3, e8, mf4, ta, ma651; CHECK-OPT-NEXT: vlse8.v v8, (a0), zero652; CHECK-OPT-NEXT: ret653;654; CHECK-NO-OPT-LABEL: zero_strided_unmasked_vpload_4i8_i8:655; CHECK-NO-OPT: # %bb.0:656; CHECK-NO-OPT-NEXT: lbu a0, 0(a0)657; CHECK-NO-OPT-NEXT: vsetivli zero, 3, e8, mf4, ta, ma658; CHECK-NO-OPT-NEXT: vmv.v.x v8, a0659; CHECK-NO-OPT-NEXT: ret660 %load = call <4 x i8> @llvm.experimental.vp.strided.load.4i8.p0.i8(ptr %ptr, i8 0, <4 x i1> splat (i1 true), i32 3)661 ret <4 x i8> %load662}663 664; Test unmasked float zero strided665define <4 x half> @zero_strided_unmasked_vpload_4f16(ptr %ptr) {666; CHECK-OPT-LABEL: zero_strided_unmasked_vpload_4f16:667; CHECK-OPT: # %bb.0:668; CHECK-OPT-NEXT: vsetivli zero, 3, e16, mf2, ta, ma669; CHECK-OPT-NEXT: vlse16.v v8, (a0), zero670; CHECK-OPT-NEXT: ret671;672; CHECK-NO-OPT-ZVFH-LABEL: zero_strided_unmasked_vpload_4f16:673; CHECK-NO-OPT-ZVFH: # %bb.0:674; CHECK-NO-OPT-ZVFH-NEXT: flh fa5, 0(a0)675; CHECK-NO-OPT-ZVFH-NEXT: vsetivli zero, 3, e16, mf2, ta, ma676; CHECK-NO-OPT-ZVFH-NEXT: vfmv.v.f v8, fa5677; CHECK-NO-OPT-ZVFH-NEXT: ret678;679; CHECK-NO-OPT-ZVFHMIN-LABEL: zero_strided_unmasked_vpload_4f16:680; CHECK-NO-OPT-ZVFHMIN: # %bb.0:681; CHECK-NO-OPT-ZVFHMIN-NEXT: lh a0, 0(a0)682; CHECK-NO-OPT-ZVFHMIN-NEXT: vsetivli zero, 3, e16, mf2, ta, ma683; CHECK-NO-OPT-ZVFHMIN-NEXT: vmv.v.x v8, a0684; CHECK-NO-OPT-ZVFHMIN-NEXT: ret685 %load = call <4 x half> @llvm.experimental.vp.strided.load.4f16.p0.i32(ptr %ptr, i32 0, <4 x i1> splat (i1 true), i32 3)686 ret <4 x half> %load687}688 689define <4 x i64> @zero_strided_vadd.vx(<4 x i64> %v, ptr %ptr) {690; CHECK-RV32-LABEL: zero_strided_vadd.vx:691; CHECK-RV32: # %bb.0:692; CHECK-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma693; CHECK-RV32-NEXT: vlse64.v v10, (a0), zero694; CHECK-RV32-NEXT: vadd.vv v8, v8, v10695; CHECK-RV32-NEXT: ret696;697; CHECK-RV64-LABEL: zero_strided_vadd.vx:698; CHECK-RV64: # %bb.0:699; CHECK-RV64-NEXT: ld a0, 0(a0)700; CHECK-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma701; CHECK-RV64-NEXT: vadd.vx v8, v8, a0702; CHECK-RV64-NEXT: ret703 %load = call <4 x i64> @llvm.experimental.vp.strided.load.v4i64.p0.i32(ptr %ptr, i32 0, <4 x i1> splat (i1 true), i32 4)704 %w = add <4 x i64> %v, %load705 ret <4 x i64> %w706}707