862 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV323; RUN: llc -mtriple=riscv64 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV644 5define <2 x i7> @vtrunc_v2i7_v2i16(<2 x i16> %a, <2 x i1> %m, i32 zeroext %vl) {6; CHECK-LABEL: vtrunc_v2i7_v2i16:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma9; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t10; CHECK-NEXT: ret11 %v = call <2 x i7> @llvm.vp.trunc.v2i7.v2i16(<2 x i16> %a, <2 x i1> %m, i32 %vl)12 ret <2 x i7> %v13}14 15define <2 x i8> @vtrunc_v2i8_v2i15(<2 x i15> %a, <2 x i1> %m, i32 zeroext %vl) {16; CHECK-LABEL: vtrunc_v2i8_v2i15:17; CHECK: # %bb.0:18; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma19; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t20; CHECK-NEXT: ret21 %v = call <2 x i8> @llvm.vp.trunc.v2i8.v2i15(<2 x i15> %a, <2 x i1> %m, i32 %vl)22 ret <2 x i8> %v23}24 25define <2 x i8> @vtrunc_v2i8_v2i16(<2 x i16> %a, <2 x i1> %m, i32 zeroext %vl) {26; CHECK-LABEL: vtrunc_v2i8_v2i16:27; CHECK: # %bb.0:28; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma29; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t30; CHECK-NEXT: ret31 %v = call <2 x i8> @llvm.vp.trunc.v2i8.v2i16(<2 x i16> %a, <2 x i1> %m, i32 %vl)32 ret <2 x i8> %v33}34 35define <2 x i8> @vtrunc_v2i8_v2i16_unmasked(<2 x i16> %a, i32 zeroext %vl) {36; CHECK-LABEL: vtrunc_v2i8_v2i16_unmasked:37; CHECK: # %bb.0:38; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma39; CHECK-NEXT: vnsrl.wi v8, v8, 040; CHECK-NEXT: ret41 %v = call <2 x i8> @llvm.vp.trunc.v2i8.v2i16(<2 x i16> %a, <2 x i1> <i1 true, i1 true>, i32 %vl)42 ret <2 x i8> %v43}44 45define <128 x i7> @vtrunc_v128i7_v128i16(<128 x i16> %a, <128 x i1> %m, i32 zeroext %vl) {46; CHECK-LABEL: vtrunc_v128i7_v128i16:47; CHECK: # %bb.0:48; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma49; CHECK-NEXT: vmv8r.v v24, v850; CHECK-NEXT: li a1, 6451; CHECK-NEXT: vslidedown.vi v12, v0, 852; CHECK-NEXT: mv a2, a053; CHECK-NEXT: bltu a0, a1, .LBB4_254; CHECK-NEXT: # %bb.1:55; CHECK-NEXT: li a2, 6456; CHECK-NEXT: .LBB4_2:57; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, ma58; CHECK-NEXT: vnsrl.wi v8, v24, 0, v0.t59; CHECK-NEXT: addi a2, a0, -6460; CHECK-NEXT: sltu a0, a0, a261; CHECK-NEXT: addi a0, a0, -162; CHECK-NEXT: and a0, a0, a263; CHECK-NEXT: vmv1r.v v0, v1264; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma65; CHECK-NEXT: vnsrl.wi v24, v16, 0, v0.t66; CHECK-NEXT: li a0, 12867; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma68; CHECK-NEXT: vslideup.vx v8, v24, a169; CHECK-NEXT: ret70 %v = call <128 x i7> @llvm.vp.trunc.v128i7.v128i16(<128 x i16> %a, <128 x i1> %m, i32 %vl)71 ret <128 x i7> %v72}73 74define <2 x i8> @vtrunc_v2i8_v2i32(<2 x i32> %a, <2 x i1> %m, i32 zeroext %vl) {75; CHECK-LABEL: vtrunc_v2i8_v2i32:76; CHECK: # %bb.0:77; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma78; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t79; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma80; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t81; CHECK-NEXT: ret82 %v = call <2 x i8> @llvm.vp.trunc.v2i8.v2i32(<2 x i32> %a, <2 x i1> %m, i32 %vl)83 ret <2 x i8> %v84}85 86define <2 x i8> @vtrunc_v2i8_v2i32_unmasked(<2 x i32> %a, i32 zeroext %vl) {87; CHECK-LABEL: vtrunc_v2i8_v2i32_unmasked:88; CHECK: # %bb.0:89; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma90; CHECK-NEXT: vnsrl.wi v8, v8, 091; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma92; CHECK-NEXT: vnsrl.wi v8, v8, 093; CHECK-NEXT: ret94 %v = call <2 x i8> @llvm.vp.trunc.v2i8.v2i32(<2 x i32> %a, <2 x i1> <i1 true, i1 true>, i32 %vl)95 ret <2 x i8> %v96}97 98define <2 x i8> @vtrunc_v2i8_v2i64(<2 x i64> %a, <2 x i1> %m, i32 zeroext %vl) {99; CHECK-LABEL: vtrunc_v2i8_v2i64:100; CHECK: # %bb.0:101; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma102; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t103; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma104; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t105; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma106; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t107; CHECK-NEXT: ret108 %v = call <2 x i8> @llvm.vp.trunc.v2i8.v2i64(<2 x i64> %a, <2 x i1> %m, i32 %vl)109 ret <2 x i8> %v110}111 112define <2 x i8> @vtrunc_v2i8_v2i64_unmasked(<2 x i64> %a, i32 zeroext %vl) {113; CHECK-LABEL: vtrunc_v2i8_v2i64_unmasked:114; CHECK: # %bb.0:115; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma116; CHECK-NEXT: vnsrl.wi v8, v8, 0117; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma118; CHECK-NEXT: vnsrl.wi v8, v8, 0119; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma120; CHECK-NEXT: vnsrl.wi v8, v8, 0121; CHECK-NEXT: ret122 %v = call <2 x i8> @llvm.vp.trunc.v2i8.v2i64(<2 x i64> %a, <2 x i1> <i1 true, i1 true>, i32 %vl)123 ret <2 x i8> %v124}125 126define <2 x i16> @vtrunc_v2i16_v2i32(<2 x i32> %a, <2 x i1> %m, i32 zeroext %vl) {127; CHECK-LABEL: vtrunc_v2i16_v2i32:128; CHECK: # %bb.0:129; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma130; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t131; CHECK-NEXT: ret132 %v = call <2 x i16> @llvm.vp.trunc.v2i16.v2i32(<2 x i32> %a, <2 x i1> %m, i32 %vl)133 ret <2 x i16> %v134}135 136define <2 x i16> @vtrunc_v2i16_v2i32_unmasked(<2 x i32> %a, i32 zeroext %vl) {137; CHECK-LABEL: vtrunc_v2i16_v2i32_unmasked:138; CHECK: # %bb.0:139; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma140; CHECK-NEXT: vnsrl.wi v8, v8, 0141; CHECK-NEXT: ret142 %v = call <2 x i16> @llvm.vp.trunc.v2i16.v2i32(<2 x i32> %a, <2 x i1> <i1 true, i1 true>, i32 %vl)143 ret <2 x i16> %v144}145 146define <2 x i16> @vtrunc_v2i16_v2i64(<2 x i64> %a, <2 x i1> %m, i32 zeroext %vl) {147; CHECK-LABEL: vtrunc_v2i16_v2i64:148; CHECK: # %bb.0:149; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma150; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t151; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma152; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t153; CHECK-NEXT: ret154 %v = call <2 x i16> @llvm.vp.trunc.v2i16.v2i64(<2 x i64> %a, <2 x i1> %m, i32 %vl)155 ret <2 x i16> %v156}157 158define <2 x i16> @vtrunc_v2i16_v2i64_unmasked(<2 x i64> %a, i32 zeroext %vl) {159; CHECK-LABEL: vtrunc_v2i16_v2i64_unmasked:160; CHECK: # %bb.0:161; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma162; CHECK-NEXT: vnsrl.wi v8, v8, 0163; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma164; CHECK-NEXT: vnsrl.wi v8, v8, 0165; CHECK-NEXT: ret166 %v = call <2 x i16> @llvm.vp.trunc.v2i16.v2i64(<2 x i64> %a, <2 x i1> <i1 true, i1 true>, i32 %vl)167 ret <2 x i16> %v168}169 170define <15 x i16> @vtrunc_v15i16_v15i64(<15 x i64> %a, <15 x i1> %m, i32 zeroext %vl) {171; CHECK-LABEL: vtrunc_v15i16_v15i64:172; CHECK: # %bb.0:173; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma174; CHECK-NEXT: vnsrl.wi v16, v8, 0, v0.t175; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma176; CHECK-NEXT: vnsrl.wi v8, v16, 0, v0.t177; CHECK-NEXT: ret178 %v = call <15 x i16> @llvm.vp.trunc.v15i16.v15i64(<15 x i64> %a, <15 x i1> %m, i32 %vl)179 ret <15 x i16> %v180}181 182define <2 x i32> @vtrunc_v2i32_v2i64(<2 x i64> %a, <2 x i1> %m, i32 zeroext %vl) {183; CHECK-LABEL: vtrunc_v2i32_v2i64:184; CHECK: # %bb.0:185; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma186; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t187; CHECK-NEXT: ret188 %v = call <2 x i32> @llvm.vp.trunc.v2i32.v2i64(<2 x i64> %a, <2 x i1> %m, i32 %vl)189 ret <2 x i32> %v190}191 192define <2 x i32> @vtrunc_v2i32_v2i64_unmasked(<2 x i64> %a, i32 zeroext %vl) {193; CHECK-LABEL: vtrunc_v2i32_v2i64_unmasked:194; CHECK: # %bb.0:195; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma196; CHECK-NEXT: vnsrl.wi v8, v8, 0197; CHECK-NEXT: ret198 %v = call <2 x i32> @llvm.vp.trunc.v2i32.v2i64(<2 x i64> %a, <2 x i1> <i1 true, i1 true>, i32 %vl)199 ret <2 x i32> %v200}201 202define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 zeroext %vl) {203; RV32-LABEL: vtrunc_v128i32_v128i64:204; RV32: # %bb.0:205; RV32-NEXT: addi sp, sp, -32206; RV32-NEXT: .cfi_def_cfa_offset 32207; RV32-NEXT: sw s0, 28(sp) # 4-byte Folded Spill208; RV32-NEXT: .cfi_offset s0, -4209; RV32-NEXT: csrr a2, vlenb210; RV32-NEXT: li a3, 72211; RV32-NEXT: mul a2, a2, a3212; RV32-NEXT: sub sp, sp, a2213; RV32-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x20, 0x22, 0x11, 0xc8, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 32 + 72 * vlenb214; RV32-NEXT: vsetivli zero, 8, e8, m1, ta, ma215; RV32-NEXT: vmv1r.v v7, v0216; RV32-NEXT: csrr a2, vlenb217; RV32-NEXT: slli a2, a2, 5218; RV32-NEXT: add a2, sp, a2219; RV32-NEXT: addi a2, a2, 16220; RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill221; RV32-NEXT: csrr a2, vlenb222; RV32-NEXT: li a3, 40223; RV32-NEXT: mul a2, a2, a3224; RV32-NEXT: add a2, sp, a2225; RV32-NEXT: addi a2, a2, 16226; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill227; RV32-NEXT: vslidedown.vi v5, v0, 8228; RV32-NEXT: vsetivli zero, 4, e8, mf2, ta, ma229; RV32-NEXT: vslidedown.vi v4, v0, 4230; RV32-NEXT: addi a2, a7, -64231; RV32-NEXT: vslidedown.vi v3, v5, 4232; RV32-NEXT: sltu a3, a7, a2233; RV32-NEXT: addi a3, a3, -1234; RV32-NEXT: and a4, a3, a2235; RV32-NEXT: addi a2, a4, -32236; RV32-NEXT: sltu a3, a4, a2237; RV32-NEXT: addi a3, a3, -1238; RV32-NEXT: and a3, a3, a2239; RV32-NEXT: li a2, 16240; RV32-NEXT: addi t0, a3, -16241; RV32-NEXT: mv a5, a3242; RV32-NEXT: bltu a3, a2, .LBB16_2243; RV32-NEXT: # %bb.1:244; RV32-NEXT: li a5, 16245; RV32-NEXT: .LBB16_2:246; RV32-NEXT: li t2, 64247; RV32-NEXT: sltu t1, a3, t0248; RV32-NEXT: mv a6, a7249; RV32-NEXT: bltu a7, t2, .LBB16_4250; RV32-NEXT: # %bb.3:251; RV32-NEXT: li a6, 64252; RV32-NEXT: .LBB16_4:253; RV32-NEXT: addi t2, a1, 128254; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma255; RV32-NEXT: vslidedown.vi v6, v4, 2256; RV32-NEXT: addi t6, a1, 512257; RV32-NEXT: addi t5, a1, 640258; RV32-NEXT: vslidedown.vi v0, v3, 2259; RV32-NEXT: addi t1, t1, -1260; RV32-NEXT: addi t3, a1, 384261; RV32-NEXT: vslidedown.vi v2, v5, 2262; RV32-NEXT: li a3, 32263; RV32-NEXT: addi t4, a6, -32264; RV32-NEXT: sltu a6, a6, t4265; RV32-NEXT: addi a6, a6, -1266; RV32-NEXT: and a6, a6, t4267; RV32-NEXT: addi t4, a6, -16268; RV32-NEXT: sltu s0, a6, t4269; RV32-NEXT: addi s0, s0, -1270; RV32-NEXT: bltu a6, a2, .LBB16_6271; RV32-NEXT: # %bb.5:272; RV32-NEXT: li a6, 16273; RV32-NEXT: .LBB16_6:274; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma275; RV32-NEXT: vle64.v v8, (t6)276; RV32-NEXT: csrr t6, vlenb277; RV32-NEXT: sw a0, 4(sp) # 4-byte Folded Spill278; RV32-NEXT: li a0, 56279; RV32-NEXT: mul t6, t6, a0280; RV32-NEXT: lw a0, 4(sp) # 4-byte Folded Reload281; RV32-NEXT: add t6, sp, t6282; RV32-NEXT: addi t6, t6, 16283; RV32-NEXT: vs8r.v v8, (t6) # vscale x 64-byte Folded Spill284; RV32-NEXT: vle64.v v8, (t5)285; RV32-NEXT: vle64.v v16, (t2)286; RV32-NEXT: vle64.v v24, (a1)287; RV32-NEXT: csrr t2, vlenb288; RV32-NEXT: li t5, 48289; RV32-NEXT: mul t2, t2, t5290; RV32-NEXT: add t2, sp, t2291; RV32-NEXT: addi t2, t2, 16292; RV32-NEXT: vs8r.v v24, (t2) # vscale x 64-byte Folded Spill293; RV32-NEXT: vle64.v v24, (t3)294; RV32-NEXT: csrr t2, vlenb295; RV32-NEXT: slli t2, t2, 3296; RV32-NEXT: add t2, sp, t2297; RV32-NEXT: addi t2, t2, 16298; RV32-NEXT: vs8r.v v24, (t2) # vscale x 64-byte Folded Spill299; RV32-NEXT: and t2, t1, t0300; RV32-NEXT: and t1, s0, t4301; RV32-NEXT: addi a1, a1, 256302; RV32-NEXT: mv t0, a4303; RV32-NEXT: bltu a4, a3, .LBB16_8304; RV32-NEXT: # %bb.7:305; RV32-NEXT: li t0, 32306; RV32-NEXT: .LBB16_8:307; RV32-NEXT: vsetvli zero, t2, e32, m4, ta, ma308; RV32-NEXT: vnsrl.wi v24, v8, 0, v0.t309; RV32-NEXT: csrr t2, vlenb310; RV32-NEXT: li t3, 24311; RV32-NEXT: mul t2, t2, t3312; RV32-NEXT: add t2, sp, t2313; RV32-NEXT: addi t2, t2, 16314; RV32-NEXT: vs8r.v v24, (t2) # vscale x 64-byte Folded Spill315; RV32-NEXT: vmv1r.v v0, v3316; RV32-NEXT: csrr t2, vlenb317; RV32-NEXT: li t3, 56318; RV32-NEXT: mul t2, t2, t3319; RV32-NEXT: add t2, sp, t2320; RV32-NEXT: addi t2, t2, 16321; RV32-NEXT: vl8r.v v24, (t2) # vscale x 64-byte Folded Reload322; RV32-NEXT: vsetvli zero, a5, e32, m4, ta, ma323; RV32-NEXT: vnsrl.wi v8, v24, 0, v0.t324; RV32-NEXT: csrr a5, vlenb325; RV32-NEXT: slli a5, a5, 6326; RV32-NEXT: add a5, sp, a5327; RV32-NEXT: addi a5, a5, 16328; RV32-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill329; RV32-NEXT: vmv1r.v v0, v6330; RV32-NEXT: vsetvli zero, t1, e32, m4, ta, ma331; RV32-NEXT: vnsrl.wi v8, v16, 0, v0.t332; RV32-NEXT: csrr a5, vlenb333; RV32-NEXT: slli a5, a5, 4334; RV32-NEXT: add a5, sp, a5335; RV32-NEXT: addi a5, a5, 16336; RV32-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill337; RV32-NEXT: addi a5, t0, -16338; RV32-NEXT: sltu t0, t0, a5339; RV32-NEXT: addi t0, t0, -1340; RV32-NEXT: and a5, t0, a5341; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma342; RV32-NEXT: vle64.v v8, (a1)343; RV32-NEXT: addi a1, sp, 16344; RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill345; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma346; RV32-NEXT: vslidedown.vi v30, v7, 2347; RV32-NEXT: vmv1r.v v0, v4348; RV32-NEXT: csrr a1, vlenb349; RV32-NEXT: li t0, 48350; RV32-NEXT: mul a1, a1, t0351; RV32-NEXT: add a1, sp, a1352; RV32-NEXT: addi a1, a1, 16353; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload354; RV32-NEXT: vsetvli zero, a6, e32, m4, ta, ma355; RV32-NEXT: vnsrl.wi v8, v16, 0, v0.t356; RV32-NEXT: csrr a1, vlenb357; RV32-NEXT: li a6, 56358; RV32-NEXT: mul a1, a1, a6359; RV32-NEXT: add a1, sp, a1360; RV32-NEXT: addi a1, a1, 16361; RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill362; RV32-NEXT: vmv1r.v v0, v2363; RV32-NEXT: csrr a1, vlenb364; RV32-NEXT: slli a1, a1, 3365; RV32-NEXT: add a1, sp, a1366; RV32-NEXT: addi a1, a1, 16367; RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload368; RV32-NEXT: vsetvli zero, a5, e32, m4, ta, ma369; RV32-NEXT: vnsrl.wi v16, v8, 0, v0.t370; RV32-NEXT: bltu a4, a2, .LBB16_10371; RV32-NEXT: # %bb.9:372; RV32-NEXT: li a4, 16373; RV32-NEXT: .LBB16_10:374; RV32-NEXT: vmv1r.v v0, v5375; RV32-NEXT: addi a1, sp, 16376; RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload377; RV32-NEXT: vsetvli zero, a4, e32, m4, ta, ma378; RV32-NEXT: vnsrl.wi v24, v8, 0, v0.t379; RV32-NEXT: csrr a1, vlenb380; RV32-NEXT: li a4, 48381; RV32-NEXT: mul a1, a1, a4382; RV32-NEXT: add a1, sp, a1383; RV32-NEXT: addi a1, a1, 16384; RV32-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill385; RV32-NEXT: mv a1, a7386; RV32-NEXT: bltu a7, a3, .LBB16_12387; RV32-NEXT: # %bb.11:388; RV32-NEXT: li a1, 32389; RV32-NEXT: .LBB16_12:390; RV32-NEXT: vmv1r.v v0, v30391; RV32-NEXT: csrr a4, vlenb392; RV32-NEXT: li a5, 24393; RV32-NEXT: mul a4, a4, a5394; RV32-NEXT: add a4, sp, a4395; RV32-NEXT: addi a4, a4, 16396; RV32-NEXT: vl8r.v v8, (a4) # vscale x 64-byte Folded Reload397; RV32-NEXT: csrr a4, vlenb398; RV32-NEXT: slli a4, a4, 4399; RV32-NEXT: add a4, sp, a4400; RV32-NEXT: addi a4, a4, 16401; RV32-NEXT: vl8r.v v24, (a4) # vscale x 64-byte Folded Reload402; RV32-NEXT: csrr a4, vlenb403; RV32-NEXT: li a5, 24404; RV32-NEXT: mul a4, a4, a5405; RV32-NEXT: add a4, sp, a4406; RV32-NEXT: addi a4, a4, 16407; RV32-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill408; RV32-NEXT: csrr a4, vlenb409; RV32-NEXT: slli a4, a4, 6410; RV32-NEXT: add a4, sp, a4411; RV32-NEXT: addi a4, a4, 16412; RV32-NEXT: vl8r.v v16, (a4) # vscale x 64-byte Folded Reload413; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma414; RV32-NEXT: vslideup.vi v16, v8, 16415; RV32-NEXT: csrr a4, vlenb416; RV32-NEXT: slli a4, a4, 6417; RV32-NEXT: add a4, sp, a4418; RV32-NEXT: addi a4, a4, 16419; RV32-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill420; RV32-NEXT: addi a4, a1, -16421; RV32-NEXT: csrr a5, vlenb422; RV32-NEXT: li a6, 56423; RV32-NEXT: mul a5, a5, a6424; RV32-NEXT: add a5, sp, a5425; RV32-NEXT: addi a5, a5, 16426; RV32-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload427; RV32-NEXT: vslideup.vi v16, v24, 16428; RV32-NEXT: csrr a5, vlenb429; RV32-NEXT: li a6, 56430; RV32-NEXT: mul a5, a5, a6431; RV32-NEXT: add a5, sp, a5432; RV32-NEXT: addi a5, a5, 16433; RV32-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill434; RV32-NEXT: csrr a5, vlenb435; RV32-NEXT: li a6, 48436; RV32-NEXT: mul a5, a5, a6437; RV32-NEXT: add a5, sp, a5438; RV32-NEXT: addi a5, a5, 16439; RV32-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload440; RV32-NEXT: csrr a5, vlenb441; RV32-NEXT: li a6, 24442; RV32-NEXT: mul a5, a5, a6443; RV32-NEXT: add a5, sp, a5444; RV32-NEXT: addi a5, a5, 16445; RV32-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload446; RV32-NEXT: vslideup.vi v16, v8, 16447; RV32-NEXT: csrr a5, vlenb448; RV32-NEXT: li a6, 48449; RV32-NEXT: mul a5, a5, a6450; RV32-NEXT: add a5, sp, a5451; RV32-NEXT: addi a5, a5, 16452; RV32-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill453; RV32-NEXT: sltu a1, a1, a4454; RV32-NEXT: addi a1, a1, -1455; RV32-NEXT: and a1, a1, a4456; RV32-NEXT: csrr a4, vlenb457; RV32-NEXT: slli a4, a4, 5458; RV32-NEXT: add a4, sp, a4459; RV32-NEXT: addi a4, a4, 16460; RV32-NEXT: vl8r.v v16, (a4) # vscale x 64-byte Folded Reload461; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, ma462; RV32-NEXT: vnsrl.wi v8, v16, 0, v0.t463; RV32-NEXT: bltu a7, a2, .LBB16_14464; RV32-NEXT: # %bb.13:465; RV32-NEXT: li a7, 16466; RV32-NEXT: .LBB16_14:467; RV32-NEXT: vmv1r.v v0, v7468; RV32-NEXT: csrr a1, vlenb469; RV32-NEXT: li a2, 40470; RV32-NEXT: mul a1, a1, a2471; RV32-NEXT: add a1, sp, a1472; RV32-NEXT: addi a1, a1, 16473; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload474; RV32-NEXT: vsetvli zero, a7, e32, m4, ta, ma475; RV32-NEXT: vnsrl.wi v24, v16, 0, v0.t476; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma477; RV32-NEXT: vslideup.vi v24, v8, 16478; RV32-NEXT: vse32.v v24, (a0)479; RV32-NEXT: addi a1, a0, 256480; RV32-NEXT: csrr a2, vlenb481; RV32-NEXT: li a3, 48482; RV32-NEXT: mul a2, a2, a3483; RV32-NEXT: add a2, sp, a2484; RV32-NEXT: addi a2, a2, 16485; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload486; RV32-NEXT: vse32.v v8, (a1)487; RV32-NEXT: addi a1, a0, 128488; RV32-NEXT: csrr a2, vlenb489; RV32-NEXT: li a3, 56490; RV32-NEXT: mul a2, a2, a3491; RV32-NEXT: add a2, sp, a2492; RV32-NEXT: addi a2, a2, 16493; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload494; RV32-NEXT: vse32.v v8, (a1)495; RV32-NEXT: addi a0, a0, 384496; RV32-NEXT: csrr a1, vlenb497; RV32-NEXT: slli a1, a1, 6498; RV32-NEXT: add a1, sp, a1499; RV32-NEXT: addi a1, a1, 16500; RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload501; RV32-NEXT: vse32.v v8, (a0)502; RV32-NEXT: csrr a0, vlenb503; RV32-NEXT: li a1, 72504; RV32-NEXT: mul a0, a0, a1505; RV32-NEXT: add sp, sp, a0506; RV32-NEXT: .cfi_def_cfa sp, 32507; RV32-NEXT: lw s0, 28(sp) # 4-byte Folded Reload508; RV32-NEXT: .cfi_restore s0509; RV32-NEXT: addi sp, sp, 32510; RV32-NEXT: .cfi_def_cfa_offset 0511; RV32-NEXT: ret512;513; RV64-LABEL: vtrunc_v128i32_v128i64:514; RV64: # %bb.0:515; RV64-NEXT: addi sp, sp, -48516; RV64-NEXT: .cfi_def_cfa_offset 48517; RV64-NEXT: sd s0, 40(sp) # 8-byte Folded Spill518; RV64-NEXT: .cfi_offset s0, -8519; RV64-NEXT: csrr a2, vlenb520; RV64-NEXT: li a3, 72521; RV64-NEXT: mul a2, a2, a3522; RV64-NEXT: sub sp, sp, a2523; RV64-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x30, 0x22, 0x11, 0xc8, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 48 + 72 * vlenb524; RV64-NEXT: vsetivli zero, 8, e8, m1, ta, ma525; RV64-NEXT: vmv1r.v v7, v0526; RV64-NEXT: csrr a2, vlenb527; RV64-NEXT: slli a2, a2, 5528; RV64-NEXT: add a2, sp, a2529; RV64-NEXT: addi a2, a2, 32530; RV64-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill531; RV64-NEXT: csrr a2, vlenb532; RV64-NEXT: li a3, 40533; RV64-NEXT: mul a2, a2, a3534; RV64-NEXT: add a2, sp, a2535; RV64-NEXT: addi a2, a2, 32536; RV64-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill537; RV64-NEXT: vslidedown.vi v5, v0, 8538; RV64-NEXT: vsetivli zero, 4, e8, mf2, ta, ma539; RV64-NEXT: vslidedown.vi v4, v0, 4540; RV64-NEXT: addi a2, a7, -64541; RV64-NEXT: vslidedown.vi v3, v5, 4542; RV64-NEXT: sltu a3, a7, a2543; RV64-NEXT: addi a3, a3, -1544; RV64-NEXT: and a4, a3, a2545; RV64-NEXT: addi a2, a4, -32546; RV64-NEXT: sltu a3, a4, a2547; RV64-NEXT: addi a3, a3, -1548; RV64-NEXT: and a3, a3, a2549; RV64-NEXT: li a2, 16550; RV64-NEXT: addi t0, a3, -16551; RV64-NEXT: mv a5, a3552; RV64-NEXT: bltu a3, a2, .LBB16_2553; RV64-NEXT: # %bb.1:554; RV64-NEXT: li a5, 16555; RV64-NEXT: .LBB16_2:556; RV64-NEXT: li t2, 64557; RV64-NEXT: sltu t1, a3, t0558; RV64-NEXT: mv a6, a7559; RV64-NEXT: bltu a7, t2, .LBB16_4560; RV64-NEXT: # %bb.3:561; RV64-NEXT: li a6, 64562; RV64-NEXT: .LBB16_4:563; RV64-NEXT: addi t2, a1, 128564; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma565; RV64-NEXT: vslidedown.vi v6, v4, 2566; RV64-NEXT: addi t6, a1, 512567; RV64-NEXT: addi t5, a1, 640568; RV64-NEXT: vslidedown.vi v0, v3, 2569; RV64-NEXT: addi t1, t1, -1570; RV64-NEXT: addi t3, a1, 384571; RV64-NEXT: vslidedown.vi v2, v5, 2572; RV64-NEXT: li a3, 32573; RV64-NEXT: addi t4, a6, -32574; RV64-NEXT: sltu a6, a6, t4575; RV64-NEXT: addi a6, a6, -1576; RV64-NEXT: and a6, a6, t4577; RV64-NEXT: addi t4, a6, -16578; RV64-NEXT: sltu s0, a6, t4579; RV64-NEXT: addi s0, s0, -1580; RV64-NEXT: bltu a6, a2, .LBB16_6581; RV64-NEXT: # %bb.5:582; RV64-NEXT: li a6, 16583; RV64-NEXT: .LBB16_6:584; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma585; RV64-NEXT: vle64.v v8, (t6)586; RV64-NEXT: csrr t6, vlenb587; RV64-NEXT: sd a0, 8(sp) # 8-byte Folded Spill588; RV64-NEXT: li a0, 56589; RV64-NEXT: mul t6, t6, a0590; RV64-NEXT: ld a0, 8(sp) # 8-byte Folded Reload591; RV64-NEXT: add t6, sp, t6592; RV64-NEXT: addi t6, t6, 32593; RV64-NEXT: vs8r.v v8, (t6) # vscale x 64-byte Folded Spill594; RV64-NEXT: vle64.v v8, (t5)595; RV64-NEXT: vle64.v v16, (t2)596; RV64-NEXT: vle64.v v24, (a1)597; RV64-NEXT: csrr t2, vlenb598; RV64-NEXT: li t5, 48599; RV64-NEXT: mul t2, t2, t5600; RV64-NEXT: add t2, sp, t2601; RV64-NEXT: addi t2, t2, 32602; RV64-NEXT: vs8r.v v24, (t2) # vscale x 64-byte Folded Spill603; RV64-NEXT: vle64.v v24, (t3)604; RV64-NEXT: csrr t2, vlenb605; RV64-NEXT: slli t2, t2, 3606; RV64-NEXT: add t2, sp, t2607; RV64-NEXT: addi t2, t2, 32608; RV64-NEXT: vs8r.v v24, (t2) # vscale x 64-byte Folded Spill609; RV64-NEXT: and t2, t1, t0610; RV64-NEXT: and t1, s0, t4611; RV64-NEXT: addi a1, a1, 256612; RV64-NEXT: mv t0, a4613; RV64-NEXT: bltu a4, a3, .LBB16_8614; RV64-NEXT: # %bb.7:615; RV64-NEXT: li t0, 32616; RV64-NEXT: .LBB16_8:617; RV64-NEXT: vsetvli zero, t2, e32, m4, ta, ma618; RV64-NEXT: vnsrl.wi v24, v8, 0, v0.t619; RV64-NEXT: csrr t2, vlenb620; RV64-NEXT: li t3, 24621; RV64-NEXT: mul t2, t2, t3622; RV64-NEXT: add t2, sp, t2623; RV64-NEXT: addi t2, t2, 32624; RV64-NEXT: vs8r.v v24, (t2) # vscale x 64-byte Folded Spill625; RV64-NEXT: vmv1r.v v0, v3626; RV64-NEXT: csrr t2, vlenb627; RV64-NEXT: li t3, 56628; RV64-NEXT: mul t2, t2, t3629; RV64-NEXT: add t2, sp, t2630; RV64-NEXT: addi t2, t2, 32631; RV64-NEXT: vl8r.v v24, (t2) # vscale x 64-byte Folded Reload632; RV64-NEXT: vsetvli zero, a5, e32, m4, ta, ma633; RV64-NEXT: vnsrl.wi v8, v24, 0, v0.t634; RV64-NEXT: csrr a5, vlenb635; RV64-NEXT: slli a5, a5, 6636; RV64-NEXT: add a5, sp, a5637; RV64-NEXT: addi a5, a5, 32638; RV64-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill639; RV64-NEXT: vmv1r.v v0, v6640; RV64-NEXT: vsetvli zero, t1, e32, m4, ta, ma641; RV64-NEXT: vnsrl.wi v8, v16, 0, v0.t642; RV64-NEXT: csrr a5, vlenb643; RV64-NEXT: slli a5, a5, 4644; RV64-NEXT: add a5, sp, a5645; RV64-NEXT: addi a5, a5, 32646; RV64-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill647; RV64-NEXT: addi a5, t0, -16648; RV64-NEXT: sltu t0, t0, a5649; RV64-NEXT: addi t0, t0, -1650; RV64-NEXT: and a5, t0, a5651; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma652; RV64-NEXT: vle64.v v8, (a1)653; RV64-NEXT: addi a1, sp, 32654; RV64-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill655; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma656; RV64-NEXT: vslidedown.vi v30, v7, 2657; RV64-NEXT: vmv1r.v v0, v4658; RV64-NEXT: csrr a1, vlenb659; RV64-NEXT: li t0, 48660; RV64-NEXT: mul a1, a1, t0661; RV64-NEXT: add a1, sp, a1662; RV64-NEXT: addi a1, a1, 32663; RV64-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload664; RV64-NEXT: vsetvli zero, a6, e32, m4, ta, ma665; RV64-NEXT: vnsrl.wi v8, v16, 0, v0.t666; RV64-NEXT: csrr a1, vlenb667; RV64-NEXT: li a6, 56668; RV64-NEXT: mul a1, a1, a6669; RV64-NEXT: add a1, sp, a1670; RV64-NEXT: addi a1, a1, 32671; RV64-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill672; RV64-NEXT: vmv1r.v v0, v2673; RV64-NEXT: csrr a1, vlenb674; RV64-NEXT: slli a1, a1, 3675; RV64-NEXT: add a1, sp, a1676; RV64-NEXT: addi a1, a1, 32677; RV64-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload678; RV64-NEXT: vsetvli zero, a5, e32, m4, ta, ma679; RV64-NEXT: vnsrl.wi v16, v8, 0, v0.t680; RV64-NEXT: bltu a4, a2, .LBB16_10681; RV64-NEXT: # %bb.9:682; RV64-NEXT: li a4, 16683; RV64-NEXT: .LBB16_10:684; RV64-NEXT: vmv1r.v v0, v5685; RV64-NEXT: addi a1, sp, 32686; RV64-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload687; RV64-NEXT: vsetvli zero, a4, e32, m4, ta, ma688; RV64-NEXT: vnsrl.wi v24, v8, 0, v0.t689; RV64-NEXT: csrr a1, vlenb690; RV64-NEXT: li a4, 48691; RV64-NEXT: mul a1, a1, a4692; RV64-NEXT: add a1, sp, a1693; RV64-NEXT: addi a1, a1, 32694; RV64-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill695; RV64-NEXT: mv a1, a7696; RV64-NEXT: bltu a7, a3, .LBB16_12697; RV64-NEXT: # %bb.11:698; RV64-NEXT: li a1, 32699; RV64-NEXT: .LBB16_12:700; RV64-NEXT: vmv1r.v v0, v30701; RV64-NEXT: csrr a4, vlenb702; RV64-NEXT: li a5, 24703; RV64-NEXT: mul a4, a4, a5704; RV64-NEXT: add a4, sp, a4705; RV64-NEXT: addi a4, a4, 32706; RV64-NEXT: vl8r.v v8, (a4) # vscale x 64-byte Folded Reload707; RV64-NEXT: csrr a4, vlenb708; RV64-NEXT: slli a4, a4, 4709; RV64-NEXT: add a4, sp, a4710; RV64-NEXT: addi a4, a4, 32711; RV64-NEXT: vl8r.v v24, (a4) # vscale x 64-byte Folded Reload712; RV64-NEXT: csrr a4, vlenb713; RV64-NEXT: li a5, 24714; RV64-NEXT: mul a4, a4, a5715; RV64-NEXT: add a4, sp, a4716; RV64-NEXT: addi a4, a4, 32717; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill718; RV64-NEXT: csrr a4, vlenb719; RV64-NEXT: slli a4, a4, 6720; RV64-NEXT: add a4, sp, a4721; RV64-NEXT: addi a4, a4, 32722; RV64-NEXT: vl8r.v v16, (a4) # vscale x 64-byte Folded Reload723; RV64-NEXT: vsetvli zero, a3, e32, m8, ta, ma724; RV64-NEXT: vslideup.vi v16, v8, 16725; RV64-NEXT: csrr a4, vlenb726; RV64-NEXT: slli a4, a4, 6727; RV64-NEXT: add a4, sp, a4728; RV64-NEXT: addi a4, a4, 32729; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill730; RV64-NEXT: addi a4, a1, -16731; RV64-NEXT: csrr a5, vlenb732; RV64-NEXT: li a6, 56733; RV64-NEXT: mul a5, a5, a6734; RV64-NEXT: add a5, sp, a5735; RV64-NEXT: addi a5, a5, 32736; RV64-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload737; RV64-NEXT: vslideup.vi v16, v24, 16738; RV64-NEXT: csrr a5, vlenb739; RV64-NEXT: li a6, 56740; RV64-NEXT: mul a5, a5, a6741; RV64-NEXT: add a5, sp, a5742; RV64-NEXT: addi a5, a5, 32743; RV64-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill744; RV64-NEXT: csrr a5, vlenb745; RV64-NEXT: li a6, 48746; RV64-NEXT: mul a5, a5, a6747; RV64-NEXT: add a5, sp, a5748; RV64-NEXT: addi a5, a5, 32749; RV64-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload750; RV64-NEXT: csrr a5, vlenb751; RV64-NEXT: li a6, 24752; RV64-NEXT: mul a5, a5, a6753; RV64-NEXT: add a5, sp, a5754; RV64-NEXT: addi a5, a5, 32755; RV64-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload756; RV64-NEXT: vslideup.vi v16, v8, 16757; RV64-NEXT: csrr a5, vlenb758; RV64-NEXT: li a6, 48759; RV64-NEXT: mul a5, a5, a6760; RV64-NEXT: add a5, sp, a5761; RV64-NEXT: addi a5, a5, 32762; RV64-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill763; RV64-NEXT: sltu a1, a1, a4764; RV64-NEXT: addi a1, a1, -1765; RV64-NEXT: and a1, a1, a4766; RV64-NEXT: csrr a4, vlenb767; RV64-NEXT: slli a4, a4, 5768; RV64-NEXT: add a4, sp, a4769; RV64-NEXT: addi a4, a4, 32770; RV64-NEXT: vl8r.v v16, (a4) # vscale x 64-byte Folded Reload771; RV64-NEXT: vsetvli zero, a1, e32, m4, ta, ma772; RV64-NEXT: vnsrl.wi v8, v16, 0, v0.t773; RV64-NEXT: bltu a7, a2, .LBB16_14774; RV64-NEXT: # %bb.13:775; RV64-NEXT: li a7, 16776; RV64-NEXT: .LBB16_14:777; RV64-NEXT: vmv1r.v v0, v7778; RV64-NEXT: csrr a1, vlenb779; RV64-NEXT: li a2, 40780; RV64-NEXT: mul a1, a1, a2781; RV64-NEXT: add a1, sp, a1782; RV64-NEXT: addi a1, a1, 32783; RV64-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload784; RV64-NEXT: vsetvli zero, a7, e32, m4, ta, ma785; RV64-NEXT: vnsrl.wi v24, v16, 0, v0.t786; RV64-NEXT: vsetvli zero, a3, e32, m8, ta, ma787; RV64-NEXT: vslideup.vi v24, v8, 16788; RV64-NEXT: vse32.v v24, (a0)789; RV64-NEXT: addi a1, a0, 256790; RV64-NEXT: csrr a2, vlenb791; RV64-NEXT: li a3, 48792; RV64-NEXT: mul a2, a2, a3793; RV64-NEXT: add a2, sp, a2794; RV64-NEXT: addi a2, a2, 32795; RV64-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload796; RV64-NEXT: vse32.v v8, (a1)797; RV64-NEXT: addi a1, a0, 128798; RV64-NEXT: csrr a2, vlenb799; RV64-NEXT: li a3, 56800; RV64-NEXT: mul a2, a2, a3801; RV64-NEXT: add a2, sp, a2802; RV64-NEXT: addi a2, a2, 32803; RV64-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload804; RV64-NEXT: vse32.v v8, (a1)805; RV64-NEXT: addi a0, a0, 384806; RV64-NEXT: csrr a1, vlenb807; RV64-NEXT: slli a1, a1, 6808; RV64-NEXT: add a1, sp, a1809; RV64-NEXT: addi a1, a1, 32810; RV64-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload811; RV64-NEXT: vse32.v v8, (a0)812; RV64-NEXT: csrr a0, vlenb813; RV64-NEXT: li a1, 72814; RV64-NEXT: mul a0, a0, a1815; RV64-NEXT: add sp, sp, a0816; RV64-NEXT: .cfi_def_cfa sp, 48817; RV64-NEXT: ld s0, 40(sp) # 8-byte Folded Reload818; RV64-NEXT: .cfi_restore s0819; RV64-NEXT: addi sp, sp, 48820; RV64-NEXT: .cfi_def_cfa_offset 0821; RV64-NEXT: ret822 %v = call <128 x i32> @llvm.vp.trunc.v128i32.v128i64(<128 x i64> %a, <128 x i1> %m, i32 %vl)823 ret <128 x i32> %v824}825 826define <32 x i32> @vtrunc_v32i32_v32i64(<32 x i64> %a, <32 x i1> %m, i32 zeroext %vl) {827; CHECK-LABEL: vtrunc_v32i32_v32i64:828; CHECK: # %bb.0:829; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma830; CHECK-NEXT: vmv8r.v v24, v8831; CHECK-NEXT: li a2, 16832; CHECK-NEXT: vslidedown.vi v12, v0, 2833; CHECK-NEXT: mv a1, a0834; CHECK-NEXT: bltu a0, a2, .LBB17_2835; CHECK-NEXT: # %bb.1:836; CHECK-NEXT: li a1, 16837; CHECK-NEXT: .LBB17_2:838; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma839; CHECK-NEXT: vnsrl.wi v8, v24, 0, v0.t840; CHECK-NEXT: addi a1, a0, -16841; CHECK-NEXT: sltu a0, a0, a1842; CHECK-NEXT: addi a0, a0, -1843; CHECK-NEXT: and a0, a0, a1844; CHECK-NEXT: vmv1r.v v0, v12845; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma846; CHECK-NEXT: vnsrl.wi v24, v16, 0, v0.t847; CHECK-NEXT: li a0, 32848; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma849; CHECK-NEXT: vslideup.vi v8, v24, 16850; CHECK-NEXT: ret851 %v = call <32 x i32> @llvm.vp.trunc.v32i32.v32i64(<32 x i64> %a, <32 x i1> %m, i32 %vl)852 ret <32 x i32> %v853}854 855define <2 x i7> @vtrunc_v2i7_v2i8(<2 x i8> %a, <2 x i1> %m, i32 zeroext %vl) {856; CHECK-LABEL: vtrunc_v2i7_v2i8:857; CHECK: # %bb.0:858; CHECK-NEXT: ret859 %v = call <2 x i7> @llvm.vp.trunc.v2i7.v2i8(<2 x i8> %a, <2 x i1> %m, i32 %vl)860 ret <2 x i7> %v861}862