614 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+m,+v -verify-machineinstrs < %s \3; RUN: | FileCheck %s --check-prefixes=SLOW,RV32-SLOW4; RUN: llc -mtriple=riscv64 -mattr=+m,+v -verify-machineinstrs < %s \5; RUN: | FileCheck %s --check-prefixes=SLOW,RV64-SLOW6; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+unaligned-vector-mem -verify-machineinstrs < %s \7; RUN: | FileCheck %s --check-prefixes=FAST,RV32-FAST8; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+unaligned-vector-mem -verify-machineinstrs < %s \9; RUN: | FileCheck %s --check-prefixes=FAST,RV64-FAST10 11define <4 x i32> @load_v4i32_align1(ptr %ptr) {12; SLOW-LABEL: load_v4i32_align1:13; SLOW: # %bb.0:14; SLOW-NEXT: vsetivli zero, 16, e8, m1, ta, ma15; SLOW-NEXT: vle8.v v8, (a0)16; SLOW-NEXT: ret17;18; FAST-LABEL: load_v4i32_align1:19; FAST: # %bb.0:20; FAST-NEXT: vsetivli zero, 4, e32, m1, ta, ma21; FAST-NEXT: vle32.v v8, (a0)22; FAST-NEXT: ret23 %z = load <4 x i32>, ptr %ptr, align 124 ret <4 x i32> %z25}26 27define <4 x i32> @load_v4i32_align2(ptr %ptr) {28; SLOW-LABEL: load_v4i32_align2:29; SLOW: # %bb.0:30; SLOW-NEXT: vsetivli zero, 16, e8, m1, ta, ma31; SLOW-NEXT: vle8.v v8, (a0)32; SLOW-NEXT: ret33;34; FAST-LABEL: load_v4i32_align2:35; FAST: # %bb.0:36; FAST-NEXT: vsetivli zero, 4, e32, m1, ta, ma37; FAST-NEXT: vle32.v v8, (a0)38; FAST-NEXT: ret39 %z = load <4 x i32>, ptr %ptr, align 240 ret <4 x i32> %z41}42 43define void @store_v4i32_align1(<4 x i32> %x, ptr %ptr) {44; SLOW-LABEL: store_v4i32_align1:45; SLOW: # %bb.0:46; SLOW-NEXT: vsetivli zero, 16, e8, m1, ta, ma47; SLOW-NEXT: vse8.v v8, (a0)48; SLOW-NEXT: ret49;50; FAST-LABEL: store_v4i32_align1:51; FAST: # %bb.0:52; FAST-NEXT: vsetivli zero, 4, e32, m1, ta, ma53; FAST-NEXT: vse32.v v8, (a0)54; FAST-NEXT: ret55 store <4 x i32> %x, ptr %ptr, align 156 ret void57}58 59define void @store_v4i32_align2(<4 x i32> %x, ptr %ptr) {60; SLOW-LABEL: store_v4i32_align2:61; SLOW: # %bb.0:62; SLOW-NEXT: vsetivli zero, 16, e8, m1, ta, ma63; SLOW-NEXT: vse8.v v8, (a0)64; SLOW-NEXT: ret65;66; FAST-LABEL: store_v4i32_align2:67; FAST: # %bb.0:68; FAST-NEXT: vsetivli zero, 4, e32, m1, ta, ma69; FAST-NEXT: vse32.v v8, (a0)70; FAST-NEXT: ret71 store <4 x i32> %x, ptr %ptr, align 272 ret void73}74 75define <2 x i16> @mgather_v2i16_align1(<2 x ptr> %ptrs, <2 x i1> %m, <2 x i16> %passthru) {76; RV32-SLOW-LABEL: mgather_v2i16_align1:77; RV32-SLOW: # %bb.0:78; RV32-SLOW-NEXT: vsetivli zero, 1, e8, m1, ta, ma79; RV32-SLOW-NEXT: vmv.x.s a0, v080; RV32-SLOW-NEXT: andi a1, a0, 181; RV32-SLOW-NEXT: beqz a1, .LBB4_282; RV32-SLOW-NEXT: # %bb.1: # %cond.load83; RV32-SLOW-NEXT: vsetvli zero, zero, e32, m4, ta, ma84; RV32-SLOW-NEXT: vmv.x.s a1, v885; RV32-SLOW-NEXT: lbu a2, 1(a1)86; RV32-SLOW-NEXT: lbu a1, 0(a1)87; RV32-SLOW-NEXT: slli a2, a2, 888; RV32-SLOW-NEXT: or a1, a2, a189; RV32-SLOW-NEXT: vsetvli zero, zero, e16, m2, tu, ma90; RV32-SLOW-NEXT: vmv.s.x v9, a191; RV32-SLOW-NEXT: .LBB4_2: # %else92; RV32-SLOW-NEXT: andi a0, a0, 293; RV32-SLOW-NEXT: beqz a0, .LBB4_494; RV32-SLOW-NEXT: # %bb.3: # %cond.load195; RV32-SLOW-NEXT: vsetivli zero, 1, e32, mf2, ta, ma96; RV32-SLOW-NEXT: vslidedown.vi v8, v8, 197; RV32-SLOW-NEXT: vmv.x.s a0, v898; RV32-SLOW-NEXT: lbu a1, 1(a0)99; RV32-SLOW-NEXT: lbu a0, 0(a0)100; RV32-SLOW-NEXT: slli a1, a1, 8101; RV32-SLOW-NEXT: or a0, a1, a0102; RV32-SLOW-NEXT: vmv.s.x v8, a0103; RV32-SLOW-NEXT: vsetivli zero, 2, e16, mf4, ta, ma104; RV32-SLOW-NEXT: vslideup.vi v9, v8, 1105; RV32-SLOW-NEXT: .LBB4_4: # %else2106; RV32-SLOW-NEXT: vsetivli zero, 1, e8, m1, ta, ma107; RV32-SLOW-NEXT: vmv1r.v v8, v9108; RV32-SLOW-NEXT: ret109;110; RV64-SLOW-LABEL: mgather_v2i16_align1:111; RV64-SLOW: # %bb.0:112; RV64-SLOW-NEXT: vsetivli zero, 1, e8, m1, ta, ma113; RV64-SLOW-NEXT: vmv.x.s a0, v0114; RV64-SLOW-NEXT: andi a1, a0, 1115; RV64-SLOW-NEXT: beqz a1, .LBB4_2116; RV64-SLOW-NEXT: # %bb.1: # %cond.load117; RV64-SLOW-NEXT: vsetvli zero, zero, e64, m8, ta, ma118; RV64-SLOW-NEXT: vmv.x.s a1, v8119; RV64-SLOW-NEXT: lbu a2, 1(a1)120; RV64-SLOW-NEXT: lbu a1, 0(a1)121; RV64-SLOW-NEXT: slli a2, a2, 8122; RV64-SLOW-NEXT: or a1, a2, a1123; RV64-SLOW-NEXT: vsetvli zero, zero, e16, m2, tu, ma124; RV64-SLOW-NEXT: vmv.s.x v9, a1125; RV64-SLOW-NEXT: .LBB4_2: # %else126; RV64-SLOW-NEXT: andi a0, a0, 2127; RV64-SLOW-NEXT: beqz a0, .LBB4_4128; RV64-SLOW-NEXT: # %bb.3: # %cond.load1129; RV64-SLOW-NEXT: vsetivli zero, 1, e64, m1, ta, ma130; RV64-SLOW-NEXT: vslidedown.vi v8, v8, 1131; RV64-SLOW-NEXT: vmv.x.s a0, v8132; RV64-SLOW-NEXT: lbu a1, 1(a0)133; RV64-SLOW-NEXT: lbu a0, 0(a0)134; RV64-SLOW-NEXT: slli a1, a1, 8135; RV64-SLOW-NEXT: or a0, a1, a0136; RV64-SLOW-NEXT: vmv.s.x v8, a0137; RV64-SLOW-NEXT: vsetivli zero, 2, e16, mf4, ta, ma138; RV64-SLOW-NEXT: vslideup.vi v9, v8, 1139; RV64-SLOW-NEXT: .LBB4_4: # %else2140; RV64-SLOW-NEXT: vsetivli zero, 1, e8, m1, ta, ma141; RV64-SLOW-NEXT: vmv1r.v v8, v9142; RV64-SLOW-NEXT: ret143;144; RV32-FAST-LABEL: mgather_v2i16_align1:145; RV32-FAST: # %bb.0:146; RV32-FAST-NEXT: vsetivli zero, 2, e16, mf4, ta, mu147; RV32-FAST-NEXT: vluxei32.v v9, (zero), v8, v0.t148; RV32-FAST-NEXT: vmv1r.v v8, v9149; RV32-FAST-NEXT: ret150;151; RV64-FAST-LABEL: mgather_v2i16_align1:152; RV64-FAST: # %bb.0:153; RV64-FAST-NEXT: vsetivli zero, 2, e16, mf4, ta, mu154; RV64-FAST-NEXT: vluxei64.v v9, (zero), v8, v0.t155; RV64-FAST-NEXT: vmv1r.v v8, v9156; RV64-FAST-NEXT: ret157 %v = call <2 x i16> @llvm.masked.gather.v2i16.v2p0(<2 x ptr> %ptrs, i32 1, <2 x i1> %m, <2 x i16> %passthru)158 ret <2 x i16> %v159}160 161define <2 x i64> @mgather_v2i64_align4(<2 x ptr> %ptrs, <2 x i1> %m, <2 x i64> %passthru) {162; RV32-SLOW-LABEL: mgather_v2i64_align4:163; RV32-SLOW: # %bb.0:164; RV32-SLOW-NEXT: vsetivli zero, 1, e8, m1, ta, ma165; RV32-SLOW-NEXT: vmv.x.s a0, v0166; RV32-SLOW-NEXT: andi a1, a0, 1167; RV32-SLOW-NEXT: beqz a1, .LBB5_2168; RV32-SLOW-NEXT: # %bb.1: # %cond.load169; RV32-SLOW-NEXT: vsetivli zero, 2, e32, m1, tu, ma170; RV32-SLOW-NEXT: vmv.x.s a1, v8171; RV32-SLOW-NEXT: lw a2, 0(a1)172; RV32-SLOW-NEXT: lw a1, 4(a1)173; RV32-SLOW-NEXT: vslide1down.vx v9, v9, a2174; RV32-SLOW-NEXT: vslide1down.vx v9, v9, a1175; RV32-SLOW-NEXT: .LBB5_2: # %else176; RV32-SLOW-NEXT: andi a0, a0, 2177; RV32-SLOW-NEXT: beqz a0, .LBB5_4178; RV32-SLOW-NEXT: # %bb.3: # %cond.load1179; RV32-SLOW-NEXT: vsetivli zero, 1, e32, mf2, ta, ma180; RV32-SLOW-NEXT: vslidedown.vi v8, v8, 1181; RV32-SLOW-NEXT: vmv.x.s a0, v8182; RV32-SLOW-NEXT: lw a1, 0(a0)183; RV32-SLOW-NEXT: lw a0, 4(a0)184; RV32-SLOW-NEXT: vsetivli zero, 2, e32, m1, ta, ma185; RV32-SLOW-NEXT: vslide1down.vx v8, v8, a1186; RV32-SLOW-NEXT: vslide1down.vx v8, v8, a0187; RV32-SLOW-NEXT: vsetivli zero, 2, e64, m1, ta, ma188; RV32-SLOW-NEXT: vslideup.vi v9, v8, 1189; RV32-SLOW-NEXT: .LBB5_4: # %else2190; RV32-SLOW-NEXT: vsetivli zero, 1, e8, m1, ta, ma191; RV32-SLOW-NEXT: vmv1r.v v8, v9192; RV32-SLOW-NEXT: ret193;194; RV64-SLOW-LABEL: mgather_v2i64_align4:195; RV64-SLOW: # %bb.0:196; RV64-SLOW-NEXT: vsetivli zero, 1, e8, m1, ta, ma197; RV64-SLOW-NEXT: vmv.x.s a0, v0198; RV64-SLOW-NEXT: andi a1, a0, 1199; RV64-SLOW-NEXT: beqz a1, .LBB5_2200; RV64-SLOW-NEXT: # %bb.1: # %cond.load201; RV64-SLOW-NEXT: vsetvli zero, zero, e64, m8, tu, ma202; RV64-SLOW-NEXT: vmv.x.s a1, v8203; RV64-SLOW-NEXT: lw a2, 4(a1)204; RV64-SLOW-NEXT: lwu a1, 0(a1)205; RV64-SLOW-NEXT: slli a2, a2, 32206; RV64-SLOW-NEXT: or a1, a2, a1207; RV64-SLOW-NEXT: vmv.s.x v9, a1208; RV64-SLOW-NEXT: .LBB5_2: # %else209; RV64-SLOW-NEXT: andi a0, a0, 2210; RV64-SLOW-NEXT: beqz a0, .LBB5_4211; RV64-SLOW-NEXT: # %bb.3: # %cond.load1212; RV64-SLOW-NEXT: vsetivli zero, 2, e64, m1, ta, ma213; RV64-SLOW-NEXT: vslidedown.vi v8, v8, 1214; RV64-SLOW-NEXT: vmv.x.s a0, v8215; RV64-SLOW-NEXT: lw a1, 4(a0)216; RV64-SLOW-NEXT: lwu a0, 0(a0)217; RV64-SLOW-NEXT: slli a1, a1, 32218; RV64-SLOW-NEXT: or a0, a1, a0219; RV64-SLOW-NEXT: vmv.s.x v8, a0220; RV64-SLOW-NEXT: vslideup.vi v9, v8, 1221; RV64-SLOW-NEXT: .LBB5_4: # %else2222; RV64-SLOW-NEXT: vsetivli zero, 1, e8, m1, ta, ma223; RV64-SLOW-NEXT: vmv1r.v v8, v9224; RV64-SLOW-NEXT: ret225;226; RV32-FAST-LABEL: mgather_v2i64_align4:227; RV32-FAST: # %bb.0:228; RV32-FAST-NEXT: vsetivli zero, 2, e64, m1, ta, mu229; RV32-FAST-NEXT: vluxei32.v v9, (zero), v8, v0.t230; RV32-FAST-NEXT: vmv.v.v v8, v9231; RV32-FAST-NEXT: ret232;233; RV64-FAST-LABEL: mgather_v2i64_align4:234; RV64-FAST: # %bb.0:235; RV64-FAST-NEXT: vsetivli zero, 2, e64, m1, ta, mu236; RV64-FAST-NEXT: vluxei64.v v9, (zero), v8, v0.t237; RV64-FAST-NEXT: vmv.v.v v8, v9238; RV64-FAST-NEXT: ret239 %v = call <2 x i64> @llvm.masked.gather.v2i64.v2p0(<2 x ptr> %ptrs, i32 4, <2 x i1> %m, <2 x i64> %passthru)240 ret <2 x i64> %v241}242 243define void @mscatter_v4i16_align1(<4 x i16> %val, <4 x ptr> %ptrs, <4 x i1> %m) {244; RV32-SLOW-LABEL: mscatter_v4i16_align1:245; RV32-SLOW: # %bb.0:246; RV32-SLOW-NEXT: vsetivli zero, 1, e8, m1, ta, ma247; RV32-SLOW-NEXT: vmv.x.s a0, v0248; RV32-SLOW-NEXT: andi a1, a0, 1249; RV32-SLOW-NEXT: bnez a1, .LBB6_5250; RV32-SLOW-NEXT: # %bb.1: # %else251; RV32-SLOW-NEXT: andi a1, a0, 2252; RV32-SLOW-NEXT: bnez a1, .LBB6_6253; RV32-SLOW-NEXT: .LBB6_2: # %else2254; RV32-SLOW-NEXT: andi a1, a0, 4255; RV32-SLOW-NEXT: bnez a1, .LBB6_7256; RV32-SLOW-NEXT: .LBB6_3: # %else4257; RV32-SLOW-NEXT: andi a0, a0, 8258; RV32-SLOW-NEXT: bnez a0, .LBB6_8259; RV32-SLOW-NEXT: .LBB6_4: # %else6260; RV32-SLOW-NEXT: ret261; RV32-SLOW-NEXT: .LBB6_5: # %cond.store262; RV32-SLOW-NEXT: vsetvli zero, zero, e16, m2, ta, ma263; RV32-SLOW-NEXT: vmv.x.s a1, v8264; RV32-SLOW-NEXT: vsetvli zero, zero, e32, m4, ta, ma265; RV32-SLOW-NEXT: vmv.x.s a2, v9266; RV32-SLOW-NEXT: srli a3, a1, 8267; RV32-SLOW-NEXT: sb a1, 0(a2)268; RV32-SLOW-NEXT: sb a3, 1(a2)269; RV32-SLOW-NEXT: andi a1, a0, 2270; RV32-SLOW-NEXT: beqz a1, .LBB6_2271; RV32-SLOW-NEXT: .LBB6_6: # %cond.store1272; RV32-SLOW-NEXT: vsetivli zero, 1, e16, mf2, ta, ma273; RV32-SLOW-NEXT: vslidedown.vi v10, v8, 1274; RV32-SLOW-NEXT: vmv.x.s a1, v10275; RV32-SLOW-NEXT: vsetvli zero, zero, e32, m1, ta, ma276; RV32-SLOW-NEXT: vslidedown.vi v10, v9, 1277; RV32-SLOW-NEXT: vmv.x.s a2, v10278; RV32-SLOW-NEXT: srli a3, a1, 8279; RV32-SLOW-NEXT: sb a1, 0(a2)280; RV32-SLOW-NEXT: sb a3, 1(a2)281; RV32-SLOW-NEXT: andi a1, a0, 4282; RV32-SLOW-NEXT: beqz a1, .LBB6_3283; RV32-SLOW-NEXT: .LBB6_7: # %cond.store3284; RV32-SLOW-NEXT: vsetivli zero, 1, e16, mf2, ta, ma285; RV32-SLOW-NEXT: vslidedown.vi v10, v8, 2286; RV32-SLOW-NEXT: vmv.x.s a1, v10287; RV32-SLOW-NEXT: vsetvli zero, zero, e32, m1, ta, ma288; RV32-SLOW-NEXT: vslidedown.vi v10, v9, 2289; RV32-SLOW-NEXT: vmv.x.s a2, v10290; RV32-SLOW-NEXT: srli a3, a1, 8291; RV32-SLOW-NEXT: sb a1, 0(a2)292; RV32-SLOW-NEXT: sb a3, 1(a2)293; RV32-SLOW-NEXT: andi a0, a0, 8294; RV32-SLOW-NEXT: beqz a0, .LBB6_4295; RV32-SLOW-NEXT: .LBB6_8: # %cond.store5296; RV32-SLOW-NEXT: vsetivli zero, 1, e16, mf2, ta, ma297; RV32-SLOW-NEXT: vslidedown.vi v8, v8, 3298; RV32-SLOW-NEXT: vsetvli zero, zero, e32, m1, ta, ma299; RV32-SLOW-NEXT: vslidedown.vi v9, v9, 3300; RV32-SLOW-NEXT: vsetvli zero, zero, e16, mf2, ta, ma301; RV32-SLOW-NEXT: vmv.x.s a0, v8302; RV32-SLOW-NEXT: vsetvli zero, zero, e32, m1, ta, ma303; RV32-SLOW-NEXT: vmv.x.s a1, v9304; RV32-SLOW-NEXT: srli a2, a0, 8305; RV32-SLOW-NEXT: sb a0, 0(a1)306; RV32-SLOW-NEXT: sb a2, 1(a1)307; RV32-SLOW-NEXT: ret308;309; RV64-SLOW-LABEL: mscatter_v4i16_align1:310; RV64-SLOW: # %bb.0:311; RV64-SLOW-NEXT: vsetivli zero, 1, e8, m1, ta, ma312; RV64-SLOW-NEXT: vmv.x.s a0, v0313; RV64-SLOW-NEXT: andi a1, a0, 1314; RV64-SLOW-NEXT: bnez a1, .LBB6_5315; RV64-SLOW-NEXT: # %bb.1: # %else316; RV64-SLOW-NEXT: andi a1, a0, 2317; RV64-SLOW-NEXT: bnez a1, .LBB6_6318; RV64-SLOW-NEXT: .LBB6_2: # %else2319; RV64-SLOW-NEXT: andi a1, a0, 4320; RV64-SLOW-NEXT: bnez a1, .LBB6_7321; RV64-SLOW-NEXT: .LBB6_3: # %else4322; RV64-SLOW-NEXT: andi a0, a0, 8323; RV64-SLOW-NEXT: bnez a0, .LBB6_8324; RV64-SLOW-NEXT: .LBB6_4: # %else6325; RV64-SLOW-NEXT: ret326; RV64-SLOW-NEXT: .LBB6_5: # %cond.store327; RV64-SLOW-NEXT: vsetvli zero, zero, e16, m2, ta, ma328; RV64-SLOW-NEXT: vmv.x.s a1, v8329; RV64-SLOW-NEXT: vsetvli zero, zero, e64, m8, ta, ma330; RV64-SLOW-NEXT: vmv.x.s a2, v10331; RV64-SLOW-NEXT: srli a3, a1, 8332; RV64-SLOW-NEXT: sb a1, 0(a2)333; RV64-SLOW-NEXT: sb a3, 1(a2)334; RV64-SLOW-NEXT: andi a1, a0, 2335; RV64-SLOW-NEXT: beqz a1, .LBB6_2336; RV64-SLOW-NEXT: .LBB6_6: # %cond.store1337; RV64-SLOW-NEXT: vsetivli zero, 1, e16, mf2, ta, ma338; RV64-SLOW-NEXT: vslidedown.vi v9, v8, 1339; RV64-SLOW-NEXT: vmv.x.s a1, v9340; RV64-SLOW-NEXT: vsetivli zero, 1, e64, m1, ta, ma341; RV64-SLOW-NEXT: vslidedown.vi v9, v10, 1342; RV64-SLOW-NEXT: vmv.x.s a2, v9343; RV64-SLOW-NEXT: srli a3, a1, 8344; RV64-SLOW-NEXT: sb a1, 0(a2)345; RV64-SLOW-NEXT: sb a3, 1(a2)346; RV64-SLOW-NEXT: andi a1, a0, 4347; RV64-SLOW-NEXT: beqz a1, .LBB6_3348; RV64-SLOW-NEXT: .LBB6_7: # %cond.store3349; RV64-SLOW-NEXT: vsetivli zero, 1, e16, mf2, ta, ma350; RV64-SLOW-NEXT: vslidedown.vi v9, v8, 2351; RV64-SLOW-NEXT: vmv.x.s a1, v9352; RV64-SLOW-NEXT: vsetvli zero, zero, e64, m2, ta, ma353; RV64-SLOW-NEXT: vslidedown.vi v12, v10, 2354; RV64-SLOW-NEXT: vmv.x.s a2, v12355; RV64-SLOW-NEXT: srli a3, a1, 8356; RV64-SLOW-NEXT: sb a1, 0(a2)357; RV64-SLOW-NEXT: sb a3, 1(a2)358; RV64-SLOW-NEXT: andi a0, a0, 8359; RV64-SLOW-NEXT: beqz a0, .LBB6_4360; RV64-SLOW-NEXT: .LBB6_8: # %cond.store5361; RV64-SLOW-NEXT: vsetivli zero, 1, e16, mf2, ta, ma362; RV64-SLOW-NEXT: vslidedown.vi v12, v8, 3363; RV64-SLOW-NEXT: vsetvli zero, zero, e64, m2, ta, ma364; RV64-SLOW-NEXT: vslidedown.vi v8, v10, 3365; RV64-SLOW-NEXT: vsetvli zero, zero, e16, mf2, ta, ma366; RV64-SLOW-NEXT: vmv.x.s a0, v12367; RV64-SLOW-NEXT: vsetvli zero, zero, e64, m2, ta, ma368; RV64-SLOW-NEXT: vmv.x.s a1, v8369; RV64-SLOW-NEXT: srli a2, a0, 8370; RV64-SLOW-NEXT: sb a0, 0(a1)371; RV64-SLOW-NEXT: sb a2, 1(a1)372; RV64-SLOW-NEXT: ret373;374; RV32-FAST-LABEL: mscatter_v4i16_align1:375; RV32-FAST: # %bb.0:376; RV32-FAST-NEXT: vsetivli zero, 4, e16, mf2, ta, ma377; RV32-FAST-NEXT: vsoxei32.v v8, (zero), v9, v0.t378; RV32-FAST-NEXT: ret379;380; RV64-FAST-LABEL: mscatter_v4i16_align1:381; RV64-FAST: # %bb.0:382; RV64-FAST-NEXT: vsetivli zero, 4, e16, mf2, ta, ma383; RV64-FAST-NEXT: vsoxei64.v v8, (zero), v10, v0.t384; RV64-FAST-NEXT: ret385 call void @llvm.masked.scatter.v4i16.v4p0(<4 x i16> %val, <4 x ptr> %ptrs, i32 1, <4 x i1> %m)386 ret void387}388 389define void @mscatter_v2i32_align2(<2 x i32> %val, <2 x ptr> %ptrs, <2 x i1> %m) {390; RV32-SLOW-LABEL: mscatter_v2i32_align2:391; RV32-SLOW: # %bb.0:392; RV32-SLOW-NEXT: vsetivli zero, 1, e8, m1, ta, ma393; RV32-SLOW-NEXT: vmv.x.s a0, v0394; RV32-SLOW-NEXT: andi a1, a0, 1395; RV32-SLOW-NEXT: bnez a1, .LBB7_3396; RV32-SLOW-NEXT: # %bb.1: # %else397; RV32-SLOW-NEXT: andi a0, a0, 2398; RV32-SLOW-NEXT: bnez a0, .LBB7_4399; RV32-SLOW-NEXT: .LBB7_2: # %else2400; RV32-SLOW-NEXT: ret401; RV32-SLOW-NEXT: .LBB7_3: # %cond.store402; RV32-SLOW-NEXT: vsetvli zero, zero, e32, m4, ta, ma403; RV32-SLOW-NEXT: vmv.x.s a1, v8404; RV32-SLOW-NEXT: vmv.x.s a2, v9405; RV32-SLOW-NEXT: srli a3, a1, 16406; RV32-SLOW-NEXT: sh a1, 0(a2)407; RV32-SLOW-NEXT: sh a3, 2(a2)408; RV32-SLOW-NEXT: andi a0, a0, 2409; RV32-SLOW-NEXT: beqz a0, .LBB7_2410; RV32-SLOW-NEXT: .LBB7_4: # %cond.store1411; RV32-SLOW-NEXT: vsetivli zero, 1, e32, mf2, ta, ma412; RV32-SLOW-NEXT: vslidedown.vi v8, v8, 1413; RV32-SLOW-NEXT: vslidedown.vi v9, v9, 1414; RV32-SLOW-NEXT: vmv.x.s a0, v8415; RV32-SLOW-NEXT: vmv.x.s a1, v9416; RV32-SLOW-NEXT: srli a2, a0, 16417; RV32-SLOW-NEXT: sh a0, 0(a1)418; RV32-SLOW-NEXT: sh a2, 2(a1)419; RV32-SLOW-NEXT: ret420;421; RV64-SLOW-LABEL: mscatter_v2i32_align2:422; RV64-SLOW: # %bb.0:423; RV64-SLOW-NEXT: vsetivli zero, 1, e8, m1, ta, ma424; RV64-SLOW-NEXT: vmv.x.s a0, v0425; RV64-SLOW-NEXT: andi a1, a0, 1426; RV64-SLOW-NEXT: bnez a1, .LBB7_3427; RV64-SLOW-NEXT: # %bb.1: # %else428; RV64-SLOW-NEXT: andi a0, a0, 2429; RV64-SLOW-NEXT: bnez a0, .LBB7_4430; RV64-SLOW-NEXT: .LBB7_2: # %else2431; RV64-SLOW-NEXT: ret432; RV64-SLOW-NEXT: .LBB7_3: # %cond.store433; RV64-SLOW-NEXT: vsetvli zero, zero, e32, m4, ta, ma434; RV64-SLOW-NEXT: vmv.x.s a1, v8435; RV64-SLOW-NEXT: vsetvli zero, zero, e64, m8, ta, ma436; RV64-SLOW-NEXT: vmv.x.s a2, v9437; RV64-SLOW-NEXT: srli a3, a1, 16438; RV64-SLOW-NEXT: sh a1, 0(a2)439; RV64-SLOW-NEXT: sh a3, 2(a2)440; RV64-SLOW-NEXT: andi a0, a0, 2441; RV64-SLOW-NEXT: beqz a0, .LBB7_2442; RV64-SLOW-NEXT: .LBB7_4: # %cond.store1443; RV64-SLOW-NEXT: vsetivli zero, 1, e32, mf2, ta, ma444; RV64-SLOW-NEXT: vslidedown.vi v8, v8, 1445; RV64-SLOW-NEXT: vsetvli zero, zero, e64, m1, ta, ma446; RV64-SLOW-NEXT: vslidedown.vi v9, v9, 1447; RV64-SLOW-NEXT: vsetvli zero, zero, e32, mf2, ta, ma448; RV64-SLOW-NEXT: vmv.x.s a0, v8449; RV64-SLOW-NEXT: vsetvli zero, zero, e64, m1, ta, ma450; RV64-SLOW-NEXT: vmv.x.s a1, v9451; RV64-SLOW-NEXT: srli a2, a0, 16452; RV64-SLOW-NEXT: sh a0, 0(a1)453; RV64-SLOW-NEXT: sh a2, 2(a1)454; RV64-SLOW-NEXT: ret455;456; RV32-FAST-LABEL: mscatter_v2i32_align2:457; RV32-FAST: # %bb.0:458; RV32-FAST-NEXT: vsetivli zero, 2, e32, mf2, ta, ma459; RV32-FAST-NEXT: vsoxei32.v v8, (zero), v9, v0.t460; RV32-FAST-NEXT: ret461;462; RV64-FAST-LABEL: mscatter_v2i32_align2:463; RV64-FAST: # %bb.0:464; RV64-FAST-NEXT: vsetivli zero, 2, e32, mf2, ta, ma465; RV64-FAST-NEXT: vsoxei64.v v8, (zero), v9, v0.t466; RV64-FAST-NEXT: ret467 call void @llvm.masked.scatter.v2i32.v2p0(<2 x i32> %val, <2 x ptr> %ptrs, i32 2, <2 x i1> %m)468 ret void469}470 471define void @masked_load_v2i32_align1(ptr %a, <2 x i32> %m, ptr %res_ptr) nounwind {472; RV32-SLOW-LABEL: masked_load_v2i32_align1:473; RV32-SLOW: # %bb.0:474; RV32-SLOW-NEXT: vsetivli zero, 2, e32, mf2, ta, ma475; RV32-SLOW-NEXT: vmseq.vi v8, v8, 0476; RV32-SLOW-NEXT: vsetvli zero, zero, e8, mf8, ta, ma477; RV32-SLOW-NEXT: vmv.x.s a2, v8478; RV32-SLOW-NEXT: andi a3, a2, 1479; RV32-SLOW-NEXT: # implicit-def: $v8480; RV32-SLOW-NEXT: beqz a3, .LBB8_2481; RV32-SLOW-NEXT: # %bb.1: # %cond.load482; RV32-SLOW-NEXT: lbu a3, 1(a0)483; RV32-SLOW-NEXT: lbu a4, 0(a0)484; RV32-SLOW-NEXT: lbu a5, 2(a0)485; RV32-SLOW-NEXT: lbu a6, 3(a0)486; RV32-SLOW-NEXT: slli a3, a3, 8487; RV32-SLOW-NEXT: or a3, a3, a4488; RV32-SLOW-NEXT: slli a5, a5, 16489; RV32-SLOW-NEXT: slli a6, a6, 24490; RV32-SLOW-NEXT: or a4, a6, a5491; RV32-SLOW-NEXT: or a3, a4, a3492; RV32-SLOW-NEXT: vsetvli zero, zero, e32, mf2, ta, ma493; RV32-SLOW-NEXT: vmv.s.x v8, a3494; RV32-SLOW-NEXT: .LBB8_2: # %else495; RV32-SLOW-NEXT: andi a2, a2, 2496; RV32-SLOW-NEXT: beqz a2, .LBB8_4497; RV32-SLOW-NEXT: # %bb.3: # %cond.load1498; RV32-SLOW-NEXT: lbu a2, 5(a0)499; RV32-SLOW-NEXT: lbu a3, 4(a0)500; RV32-SLOW-NEXT: lbu a4, 6(a0)501; RV32-SLOW-NEXT: lbu a0, 7(a0)502; RV32-SLOW-NEXT: slli a2, a2, 8503; RV32-SLOW-NEXT: or a2, a2, a3504; RV32-SLOW-NEXT: slli a4, a4, 16505; RV32-SLOW-NEXT: slli a0, a0, 24506; RV32-SLOW-NEXT: or a0, a0, a4507; RV32-SLOW-NEXT: or a0, a0, a2508; RV32-SLOW-NEXT: vsetvli zero, zero, e32, mf2, ta, ma509; RV32-SLOW-NEXT: vmv.s.x v9, a0510; RV32-SLOW-NEXT: vslideup.vi v8, v9, 1511; RV32-SLOW-NEXT: .LBB8_4: # %else2512; RV32-SLOW-NEXT: vsetvli zero, zero, e32, mf2, ta, ma513; RV32-SLOW-NEXT: vse32.v v8, (a1)514; RV32-SLOW-NEXT: ret515;516; RV64-SLOW-LABEL: masked_load_v2i32_align1:517; RV64-SLOW: # %bb.0:518; RV64-SLOW-NEXT: vsetivli zero, 2, e32, mf2, ta, ma519; RV64-SLOW-NEXT: vmseq.vi v8, v8, 0520; RV64-SLOW-NEXT: vsetvli zero, zero, e8, mf8, ta, ma521; RV64-SLOW-NEXT: vmv.x.s a2, v8522; RV64-SLOW-NEXT: andi a3, a2, 1523; RV64-SLOW-NEXT: # implicit-def: $v8524; RV64-SLOW-NEXT: beqz a3, .LBB8_2525; RV64-SLOW-NEXT: # %bb.1: # %cond.load526; RV64-SLOW-NEXT: lbu a3, 1(a0)527; RV64-SLOW-NEXT: lbu a4, 0(a0)528; RV64-SLOW-NEXT: lbu a5, 2(a0)529; RV64-SLOW-NEXT: lb a6, 3(a0)530; RV64-SLOW-NEXT: slli a3, a3, 8531; RV64-SLOW-NEXT: or a3, a3, a4532; RV64-SLOW-NEXT: slli a5, a5, 16533; RV64-SLOW-NEXT: slli a6, a6, 24534; RV64-SLOW-NEXT: or a4, a6, a5535; RV64-SLOW-NEXT: or a3, a4, a3536; RV64-SLOW-NEXT: vsetvli zero, zero, e32, mf2, ta, ma537; RV64-SLOW-NEXT: vmv.s.x v8, a3538; RV64-SLOW-NEXT: .LBB8_2: # %else539; RV64-SLOW-NEXT: andi a2, a2, 2540; RV64-SLOW-NEXT: beqz a2, .LBB8_4541; RV64-SLOW-NEXT: # %bb.3: # %cond.load1542; RV64-SLOW-NEXT: lbu a2, 5(a0)543; RV64-SLOW-NEXT: lbu a3, 4(a0)544; RV64-SLOW-NEXT: lbu a4, 6(a0)545; RV64-SLOW-NEXT: lb a0, 7(a0)546; RV64-SLOW-NEXT: slli a2, a2, 8547; RV64-SLOW-NEXT: or a2, a2, a3548; RV64-SLOW-NEXT: slli a4, a4, 16549; RV64-SLOW-NEXT: slli a0, a0, 24550; RV64-SLOW-NEXT: or a0, a0, a4551; RV64-SLOW-NEXT: or a0, a0, a2552; RV64-SLOW-NEXT: vsetvli zero, zero, e32, mf2, ta, ma553; RV64-SLOW-NEXT: vmv.s.x v9, a0554; RV64-SLOW-NEXT: vslideup.vi v8, v9, 1555; RV64-SLOW-NEXT: .LBB8_4: # %else2556; RV64-SLOW-NEXT: vsetvli zero, zero, e32, mf2, ta, ma557; RV64-SLOW-NEXT: vse32.v v8, (a1)558; RV64-SLOW-NEXT: ret559;560; FAST-LABEL: masked_load_v2i32_align1:561; FAST: # %bb.0:562; FAST-NEXT: vsetivli zero, 2, e32, mf2, ta, ma563; FAST-NEXT: vmseq.vi v0, v8, 0564; FAST-NEXT: vle32.v v8, (a0), v0.t565; FAST-NEXT: vse32.v v8, (a1)566; FAST-NEXT: ret567 %mask = icmp eq <2 x i32> %m, zeroinitializer568 %load = call <2 x i32> @llvm.masked.load.v2i32(ptr %a, i32 1, <2 x i1> %mask, <2 x i32> poison)569 store <2 x i32> %load, ptr %res_ptr570 ret void571}572 573define void @masked_store_v2i32_align2(<2 x i32> %val, ptr %a, <2 x i32> %m) nounwind {574; SLOW-LABEL: masked_store_v2i32_align2:575; SLOW: # %bb.0:576; SLOW-NEXT: vsetivli zero, 2, e32, mf2, ta, ma577; SLOW-NEXT: vmseq.vi v9, v9, 0578; SLOW-NEXT: vsetvli zero, zero, e8, mf8, ta, ma579; SLOW-NEXT: vmv.x.s a1, v9580; SLOW-NEXT: andi a2, a1, 1581; SLOW-NEXT: bnez a2, .LBB9_3582; SLOW-NEXT: # %bb.1: # %else583; SLOW-NEXT: andi a1, a1, 2584; SLOW-NEXT: bnez a1, .LBB9_4585; SLOW-NEXT: .LBB9_2: # %else2586; SLOW-NEXT: ret587; SLOW-NEXT: .LBB9_3: # %cond.store588; SLOW-NEXT: vsetvli zero, zero, e32, mf2, ta, ma589; SLOW-NEXT: vmv.x.s a2, v8590; SLOW-NEXT: srli a3, a2, 16591; SLOW-NEXT: sh a2, 0(a0)592; SLOW-NEXT: sh a3, 2(a0)593; SLOW-NEXT: andi a1, a1, 2594; SLOW-NEXT: beqz a1, .LBB9_2595; SLOW-NEXT: .LBB9_4: # %cond.store1596; SLOW-NEXT: vsetvli zero, zero, e32, mf2, ta, ma597; SLOW-NEXT: vslidedown.vi v8, v8, 1598; SLOW-NEXT: vmv.x.s a1, v8599; SLOW-NEXT: srli a2, a1, 16600; SLOW-NEXT: sh a1, 4(a0)601; SLOW-NEXT: sh a2, 6(a0)602; SLOW-NEXT: ret603;604; FAST-LABEL: masked_store_v2i32_align2:605; FAST: # %bb.0:606; FAST-NEXT: vsetivli zero, 2, e32, mf2, ta, ma607; FAST-NEXT: vmseq.vi v0, v9, 0608; FAST-NEXT: vse32.v v8, (a0), v0.t609; FAST-NEXT: ret610 %mask = icmp eq <2 x i32> %m, zeroinitializer611 call void @llvm.masked.store.v2i32.p0(<2 x i32> %val, ptr %a, i32 2, <2 x i1> %mask)612 ret void613}614