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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV323; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV644 5define <8 x i8> @vaaddu_vv_v8i8_floor(<8 x i8> %x, <8 x i8> %y) {6; CHECK-LABEL: vaaddu_vv_v8i8_floor:7; CHECK: # %bb.0:8; CHECK-NEXT: csrwi vxrm, 29; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma10; CHECK-NEXT: vaaddu.vv v8, v8, v911; CHECK-NEXT: ret12 %xzv = zext <8 x i8> %x to <8 x i16>13 %yzv = zext <8 x i8> %y to <8 x i16>14 %add = add nuw nsw <8 x i16> %xzv, %yzv15 %div = lshr <8 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>16 %ret = trunc <8 x i16> %div to <8 x i8>17 ret <8 x i8> %ret18}19 20define <8 x i8> @vaaddu_vx_v8i8_floor(<8 x i8> %x, i8 %y) {21; CHECK-LABEL: vaaddu_vx_v8i8_floor:22; CHECK: # %bb.0:23; CHECK-NEXT: csrwi vxrm, 224; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma25; CHECK-NEXT: vaaddu.vx v8, v8, a026; CHECK-NEXT: ret27 %xzv = zext <8 x i8> %x to <8 x i16>28 %yhead = insertelement <8 x i8> poison, i8 %y, i32 029 %ysplat = shufflevector <8 x i8> %yhead, <8 x i8> poison, <8 x i32> zeroinitializer30 %yzv = zext <8 x i8> %ysplat to <8 x i16>31 %add = add nuw nsw <8 x i16> %xzv, %yzv32 %div = lshr <8 x i16> %add, splat (i16 1)33 %ret = trunc <8 x i16> %div to <8 x i8>34 ret <8 x i8> %ret35}36 37 38define <8 x i8> @vaaddu_vv_v8i8_floor_sexti16(<8 x i8> %x, <8 x i8> %y) {39; CHECK-LABEL: vaaddu_vv_v8i8_floor_sexti16:40; CHECK: # %bb.0:41; CHECK-NEXT: csrwi vxrm, 242; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma43; CHECK-NEXT: vaadd.vv v8, v8, v944; CHECK-NEXT: ret45 %xzv = sext <8 x i8> %x to <8 x i16>46 %yzv = sext <8 x i8> %y to <8 x i16>47 %add = add nuw nsw <8 x i16> %xzv, %yzv48 %div = lshr <8 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>49 %ret = trunc <8 x i16> %div to <8 x i8>50 ret <8 x i8> %ret51}52 53define <8 x i8> @vaaddu_vv_v8i8_floor_zexti32(<8 x i8> %x, <8 x i8> %y) {54; CHECK-LABEL: vaaddu_vv_v8i8_floor_zexti32:55; CHECK: # %bb.0:56; CHECK-NEXT: csrwi vxrm, 257; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma58; CHECK-NEXT: vaaddu.vv v8, v8, v959; CHECK-NEXT: ret60 %xzv = zext <8 x i8> %x to <8 x i32>61 %yzv = zext <8 x i8> %y to <8 x i32>62 %add = add nuw nsw <8 x i32> %xzv, %yzv63 %div = lshr <8 x i32> %add, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>64 %ret = trunc <8 x i32> %div to <8 x i8>65 ret <8 x i8> %ret66}67 68define <8 x i8> @vaaddu_vv_v8i8_floor_lshr2(<8 x i8> %x, <8 x i8> %y) {69; CHECK-LABEL: vaaddu_vv_v8i8_floor_lshr2:70; CHECK: # %bb.0:71; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma72; CHECK-NEXT: vwaddu.vv v10, v8, v973; CHECK-NEXT: vnsrl.wi v8, v10, 274; CHECK-NEXT: ret75 %xzv = zext <8 x i8> %x to <8 x i16>76 %yzv = zext <8 x i8> %y to <8 x i16>77 %add = add nuw nsw <8 x i16> %xzv, %yzv78 %div = lshr <8 x i16> %add, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>79 %ret = trunc <8 x i16> %div to <8 x i8>80 ret <8 x i8> %ret81}82 83define <8 x i16> @vaaddu_vv_v8i16_floor(<8 x i16> %x, <8 x i16> %y) {84; CHECK-LABEL: vaaddu_vv_v8i16_floor:85; CHECK: # %bb.0:86; CHECK-NEXT: csrwi vxrm, 287; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma88; CHECK-NEXT: vaaddu.vv v8, v8, v989; CHECK-NEXT: ret90 %xzv = zext <8 x i16> %x to <8 x i32>91 %yzv = zext <8 x i16> %y to <8 x i32>92 %add = add nuw nsw <8 x i32> %xzv, %yzv93 %div = lshr <8 x i32> %add, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>94 %ret = trunc <8 x i32> %div to <8 x i16>95 ret <8 x i16> %ret96}97 98define <8 x i16> @vaaddu_vx_v8i16_floor(<8 x i16> %x, i16 %y) {99; CHECK-LABEL: vaaddu_vx_v8i16_floor:100; CHECK: # %bb.0:101; CHECK-NEXT: csrwi vxrm, 2102; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma103; CHECK-NEXT: vaaddu.vx v8, v8, a0104; CHECK-NEXT: ret105 %xzv = zext <8 x i16> %x to <8 x i32>106 %yhead = insertelement <8 x i16> poison, i16 %y, i16 0107 %ysplat = shufflevector <8 x i16> %yhead, <8 x i16> poison, <8 x i32> zeroinitializer108 %yzv = zext <8 x i16> %ysplat to <8 x i32>109 %add = add nuw nsw <8 x i32> %xzv, %yzv110 %div = lshr <8 x i32> %add, splat (i32 1)111 %ret = trunc <8 x i32> %div to <8 x i16>112 ret <8 x i16> %ret113}114 115define <8 x i32> @vaaddu_vv_v8i32_floor(<8 x i32> %x, <8 x i32> %y) {116; CHECK-LABEL: vaaddu_vv_v8i32_floor:117; CHECK: # %bb.0:118; CHECK-NEXT: csrwi vxrm, 2119; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma120; CHECK-NEXT: vaaddu.vv v8, v8, v10121; CHECK-NEXT: ret122 %xzv = zext <8 x i32> %x to <8 x i64>123 %yzv = zext <8 x i32> %y to <8 x i64>124 %add = add nuw nsw <8 x i64> %xzv, %yzv125 %div = lshr <8 x i64> %add, <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1>126 %ret = trunc <8 x i64> %div to <8 x i32>127 ret <8 x i32> %ret128}129 130define <8 x i32> @vaaddu_vx_v8i32_floor(<8 x i32> %x, i32 %y) {131; CHECK-LABEL: vaaddu_vx_v8i32_floor:132; CHECK: # %bb.0:133; CHECK-NEXT: csrwi vxrm, 2134; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma135; CHECK-NEXT: vaaddu.vx v8, v8, a0136; CHECK-NEXT: ret137 %xzv = zext <8 x i32> %x to <8 x i64>138 %yhead = insertelement <8 x i32> poison, i32 %y, i32 0139 %ysplat = shufflevector <8 x i32> %yhead, <8 x i32> poison, <8 x i32> zeroinitializer140 %yzv = zext <8 x i32> %ysplat to <8 x i64>141 %add = add nuw nsw <8 x i64> %xzv, %yzv142 %div = lshr <8 x i64> %add, splat (i64 1)143 %ret = trunc <8 x i64> %div to <8 x i32>144 ret <8 x i32> %ret145}146 147define <8 x i64> @vaaddu_vv_v8i64_floor(<8 x i64> %x, <8 x i64> %y) {148; CHECK-LABEL: vaaddu_vv_v8i64_floor:149; CHECK: # %bb.0:150; CHECK-NEXT: csrwi vxrm, 2151; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma152; CHECK-NEXT: vaaddu.vv v8, v8, v12153; CHECK-NEXT: ret154 %xzv = zext <8 x i64> %x to <8 x i128>155 %yzv = zext <8 x i64> %y to <8 x i128>156 %add = add nuw nsw <8 x i128> %xzv, %yzv157 %div = lshr <8 x i128> %add, <i128 1, i128 1, i128 1, i128 1, i128 1, i128 1, i128 1, i128 1>158 %ret = trunc <8 x i128> %div to <8 x i64>159 ret <8 x i64> %ret160}161 162define <8 x i1> @vaaddu_vv_v8i1_floor(<8 x i1> %x, <8 x i1> %y) {163; CHECK-LABEL: vaaddu_vv_v8i1_floor:164; CHECK: # %bb.0:165; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma166; CHECK-NEXT: vmv.v.i v9, 0167; CHECK-NEXT: vmerge.vim v10, v9, 1, v0168; CHECK-NEXT: vmv1r.v v0, v8169; CHECK-NEXT: vmerge.vim v8, v9, 1, v0170; CHECK-NEXT: csrwi vxrm, 2171; CHECK-NEXT: vaaddu.vv v8, v10, v8172; CHECK-NEXT: vand.vi v8, v8, 1173; CHECK-NEXT: vmsne.vi v0, v8, 0174; CHECK-NEXT: ret175 %xzv = zext <8 x i1> %x to <8 x i8>176 %yzv = zext <8 x i1> %y to <8 x i8>177 %add = add nuw nsw <8 x i8> %xzv, %yzv178 %div = lshr <8 x i8> %add, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>179 %ret = trunc <8 x i8> %div to <8 x i1>180 ret <8 x i1> %ret181}182 183define <8 x i64> @vaaddu_vx_v8i64_floor(<8 x i64> %x, i64 %y) {184; RV32-LABEL: vaaddu_vx_v8i64_floor:185; RV32: # %bb.0:186; RV32-NEXT: addi sp, sp, -16187; RV32-NEXT: .cfi_def_cfa_offset 16188; RV32-NEXT: sw a0, 8(sp)189; RV32-NEXT: sw a1, 12(sp)190; RV32-NEXT: addi a0, sp, 8191; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma192; RV32-NEXT: vlse64.v v12, (a0), zero193; RV32-NEXT: csrwi vxrm, 2194; RV32-NEXT: vaaddu.vv v8, v8, v12195; RV32-NEXT: addi sp, sp, 16196; RV32-NEXT: .cfi_def_cfa_offset 0197; RV32-NEXT: ret198;199; RV64-LABEL: vaaddu_vx_v8i64_floor:200; RV64: # %bb.0:201; RV64-NEXT: csrwi vxrm, 2202; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma203; RV64-NEXT: vaaddu.vx v8, v8, a0204; RV64-NEXT: ret205 %xzv = zext <8 x i64> %x to <8 x i128>206 %yhead = insertelement <8 x i64> poison, i64 %y, i64 0207 %ysplat = shufflevector <8 x i64> %yhead, <8 x i64> poison, <8 x i32> zeroinitializer208 %yzv = zext <8 x i64> %ysplat to <8 x i128>209 %add = add nuw nsw <8 x i128> %xzv, %yzv210 %div = lshr <8 x i128> %add, splat (i128 1)211 %ret = trunc <8 x i128> %div to <8 x i64>212 ret <8 x i64> %ret213}214 215define <8 x i8> @vaaddu_vv_v8i8_ceil(<8 x i8> %x, <8 x i8> %y) {216; CHECK-LABEL: vaaddu_vv_v8i8_ceil:217; CHECK: # %bb.0:218; CHECK-NEXT: csrwi vxrm, 0219; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma220; CHECK-NEXT: vaaddu.vv v8, v8, v9221; CHECK-NEXT: ret222 %xzv = zext <8 x i8> %x to <8 x i16>223 %yzv = zext <8 x i8> %y to <8 x i16>224 %add = add nuw nsw <8 x i16> %xzv, %yzv225 %add1 = add nuw nsw <8 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>226 %div = lshr <8 x i16> %add1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>227 %ret = trunc <8 x i16> %div to <8 x i8>228 ret <8 x i8> %ret229}230 231define <8 x i8> @vaaddu_vx_v8i8_ceil(<8 x i8> %x, i8 %y) {232; CHECK-LABEL: vaaddu_vx_v8i8_ceil:233; CHECK: # %bb.0:234; CHECK-NEXT: csrwi vxrm, 0235; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma236; CHECK-NEXT: vaaddu.vx v8, v8, a0237; CHECK-NEXT: ret238 %xzv = zext <8 x i8> %x to <8 x i16>239 %yhead = insertelement <8 x i8> poison, i8 %y, i32 0240 %ysplat = shufflevector <8 x i8> %yhead, <8 x i8> poison, <8 x i32> zeroinitializer241 %yzv = zext <8 x i8> %ysplat to <8 x i16>242 %add = add nuw nsw <8 x i16> %xzv, %yzv243 %add1 = add nuw nsw <8 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>244 %div = lshr <8 x i16> %add1, splat (i16 1)245 %ret = trunc <8 x i16> %div to <8 x i8>246 ret <8 x i8> %ret247}248 249define <8 x i8> @vaaddu_vv_v8i8_ceil_sexti16(<8 x i8> %x, <8 x i8> %y) {250; CHECK-LABEL: vaaddu_vv_v8i8_ceil_sexti16:251; CHECK: # %bb.0:252; CHECK-NEXT: csrwi vxrm, 0253; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma254; CHECK-NEXT: vaadd.vv v8, v8, v9255; CHECK-NEXT: ret256 %xzv = sext <8 x i8> %x to <8 x i16>257 %yzv = sext <8 x i8> %y to <8 x i16>258 %add = add nuw nsw <8 x i16> %xzv, %yzv259 %add1 = add nuw nsw <8 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>260 %div = lshr <8 x i16> %add1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>261 %ret = trunc <8 x i16> %div to <8 x i8>262 ret <8 x i8> %ret263}264 265define <8 x i8> @vaaddu_vv_v8i8_ceil_zexti32(<8 x i8> %x, <8 x i8> %y) {266; CHECK-LABEL: vaaddu_vv_v8i8_ceil_zexti32:267; CHECK: # %bb.0:268; CHECK-NEXT: csrwi vxrm, 0269; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma270; CHECK-NEXT: vaaddu.vv v8, v8, v9271; CHECK-NEXT: ret272 %xzv = zext <8 x i8> %x to <8 x i32>273 %yzv = zext <8 x i8> %y to <8 x i32>274 %add = add nuw nsw <8 x i32> %xzv, %yzv275 %add1 = add nuw nsw <8 x i32> %add, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>276 %div = lshr <8 x i32> %add1, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>277 %ret = trunc <8 x i32> %div to <8 x i8>278 ret <8 x i8> %ret279}280 281define <8 x i8> @vaaddu_vv_v8i8_ceil_lshr2(<8 x i8> %x, <8 x i8> %y) {282; CHECK-LABEL: vaaddu_vv_v8i8_ceil_lshr2:283; CHECK: # %bb.0:284; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma285; CHECK-NEXT: vwaddu.vv v10, v8, v9286; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma287; CHECK-NEXT: vadd.vi v8, v10, 2288; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma289; CHECK-NEXT: vnsrl.wi v8, v8, 2290; CHECK-NEXT: ret291 %xzv = zext <8 x i8> %x to <8 x i16>292 %yzv = zext <8 x i8> %y to <8 x i16>293 %add = add nuw nsw <8 x i16> %xzv, %yzv294 %add1 = add nuw nsw <8 x i16> %add, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>295 %div = lshr <8 x i16> %add1, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>296 %ret = trunc <8 x i16> %div to <8 x i8>297 ret <8 x i8> %ret298}299 300define <8 x i8> @vaaddu_vv_v8i8_ceil_add2(<8 x i8> %x, <8 x i8> %y) {301; CHECK-LABEL: vaaddu_vv_v8i8_ceil_add2:302; CHECK: # %bb.0:303; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma304; CHECK-NEXT: vwaddu.vv v10, v8, v9305; CHECK-NEXT: li a0, 2306; CHECK-NEXT: csrwi vxrm, 2307; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma308; CHECK-NEXT: vaaddu.vx v8, v10, a0309; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma310; CHECK-NEXT: vnsrl.wi v8, v8, 0311; CHECK-NEXT: ret312 %xzv = zext <8 x i8> %x to <8 x i16>313 %yzv = zext <8 x i8> %y to <8 x i16>314 %add = add nuw nsw <8 x i16> %xzv, %yzv315 %add1 = add nuw nsw <8 x i16> %add, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>316 %div = lshr <8 x i16> %add1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>317 %ret = trunc <8 x i16> %div to <8 x i8>318 ret <8 x i8> %ret319}320 321define <8 x i16> @vaaddu_vv_v8i16_ceil(<8 x i16> %x, <8 x i16> %y) {322; CHECK-LABEL: vaaddu_vv_v8i16_ceil:323; CHECK: # %bb.0:324; CHECK-NEXT: csrwi vxrm, 0325; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma326; CHECK-NEXT: vaaddu.vv v8, v8, v9327; CHECK-NEXT: ret328 %xzv = zext <8 x i16> %x to <8 x i32>329 %yzv = zext <8 x i16> %y to <8 x i32>330 %add = add nuw nsw <8 x i32> %xzv, %yzv331 %add1 = add nuw nsw <8 x i32> %add, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>332 %div = lshr <8 x i32> %add1, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>333 %ret = trunc <8 x i32> %div to <8 x i16>334 ret <8 x i16> %ret335}336 337define <8 x i16> @vaaddu_vx_v8i16_ceil(<8 x i16> %x, i16 %y) {338; CHECK-LABEL: vaaddu_vx_v8i16_ceil:339; CHECK: # %bb.0:340; CHECK-NEXT: csrwi vxrm, 0341; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma342; CHECK-NEXT: vaaddu.vx v8, v8, a0343; CHECK-NEXT: ret344 %xzv = zext <8 x i16> %x to <8 x i32>345 %yhead = insertelement <8 x i16> poison, i16 %y, i16 0346 %ysplat = shufflevector <8 x i16> %yhead, <8 x i16> poison, <8 x i32> zeroinitializer347 %yzv = zext <8 x i16> %ysplat to <8 x i32>348 %add = add nuw nsw <8 x i32> %xzv, %yzv349 %add1 = add nuw nsw <8 x i32> %add, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>350 %div = lshr <8 x i32> %add1, splat (i32 1)351 %ret = trunc <8 x i32> %div to <8 x i16>352 ret <8 x i16> %ret353}354 355define <8 x i32> @vaaddu_vv_v8i32_ceil(<8 x i32> %x, <8 x i32> %y) {356; CHECK-LABEL: vaaddu_vv_v8i32_ceil:357; CHECK: # %bb.0:358; CHECK-NEXT: csrwi vxrm, 0359; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma360; CHECK-NEXT: vaaddu.vv v8, v8, v10361; CHECK-NEXT: ret362 %xzv = zext <8 x i32> %x to <8 x i64>363 %yzv = zext <8 x i32> %y to <8 x i64>364 %add = add nuw nsw <8 x i64> %xzv, %yzv365 %add1 = add nuw nsw <8 x i64> %add, <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1>366 %div = lshr <8 x i64> %add1, <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1>367 %ret = trunc <8 x i64> %div to <8 x i32>368 ret <8 x i32> %ret369}370 371define <8 x i32> @vaaddu_vx_v8i32_ceil(<8 x i32> %x, i32 %y) {372; CHECK-LABEL: vaaddu_vx_v8i32_ceil:373; CHECK: # %bb.0:374; CHECK-NEXT: csrwi vxrm, 0375; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma376; CHECK-NEXT: vaaddu.vx v8, v8, a0377; CHECK-NEXT: ret378 %xzv = zext <8 x i32> %x to <8 x i64>379 %yhead = insertelement <8 x i32> poison, i32 %y, i32 0380 %ysplat = shufflevector <8 x i32> %yhead, <8 x i32> poison, <8 x i32> zeroinitializer381 %yzv = zext <8 x i32> %ysplat to <8 x i64>382 %add = add nuw nsw <8 x i64> %xzv, %yzv383 %add1 = add nuw nsw <8 x i64> %add, <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1>384 %div = lshr <8 x i64> %add1, splat (i64 1)385 %ret = trunc <8 x i64> %div to <8 x i32>386 ret <8 x i32> %ret387}388 389define <8 x i64> @vaaddu_vv_v8i64_ceil(<8 x i64> %x, <8 x i64> %y) {390; CHECK-LABEL: vaaddu_vv_v8i64_ceil:391; CHECK: # %bb.0:392; CHECK-NEXT: csrwi vxrm, 0393; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma394; CHECK-NEXT: vaaddu.vv v8, v8, v12395; CHECK-NEXT: ret396 %xzv = zext <8 x i64> %x to <8 x i128>397 %yzv = zext <8 x i64> %y to <8 x i128>398 %add = add nuw nsw <8 x i128> %xzv, %yzv399 %add1 = add nuw nsw <8 x i128> %add, <i128 1, i128 1, i128 1, i128 1, i128 1, i128 1, i128 1, i128 1>400 %div = lshr <8 x i128> %add1, <i128 1, i128 1, i128 1, i128 1, i128 1, i128 1, i128 1, i128 1>401 %ret = trunc <8 x i128> %div to <8 x i64>402 ret <8 x i64> %ret403}404 405define <8 x i1> @vaaddu_vv_v8i1_ceil(<8 x i1> %x, <8 x i1> %y) {406; CHECK-LABEL: vaaddu_vv_v8i1_ceil:407; CHECK: # %bb.0:408; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma409; CHECK-NEXT: vmv.v.i v9, 0410; CHECK-NEXT: vmerge.vim v10, v9, 1, v0411; CHECK-NEXT: vmv1r.v v0, v8412; CHECK-NEXT: vmerge.vim v8, v9, 1, v0413; CHECK-NEXT: csrwi vxrm, 0414; CHECK-NEXT: vaaddu.vv v8, v10, v8415; CHECK-NEXT: vand.vi v8, v8, 1416; CHECK-NEXT: vmsne.vi v0, v8, 0417; CHECK-NEXT: ret418 %xzv = zext <8 x i1> %x to <8 x i8>419 %yzv = zext <8 x i1> %y to <8 x i8>420 %add = add nuw nsw <8 x i8> %xzv, %yzv421 %add1 = add nuw nsw <8 x i8> %add, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>422 %div = lshr <8 x i8> %add1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>423 %ret = trunc <8 x i8> %div to <8 x i1>424 ret <8 x i1> %ret425}426 427define <8 x i64> @vaaddu_vx_v8i64_ceil(<8 x i64> %x, i64 %y) {428; RV32-LABEL: vaaddu_vx_v8i64_ceil:429; RV32: # %bb.0:430; RV32-NEXT: addi sp, sp, -16431; RV32-NEXT: .cfi_def_cfa_offset 16432; RV32-NEXT: sw a0, 8(sp)433; RV32-NEXT: sw a1, 12(sp)434; RV32-NEXT: addi a0, sp, 8435; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma436; RV32-NEXT: vlse64.v v12, (a0), zero437; RV32-NEXT: csrwi vxrm, 0438; RV32-NEXT: vaaddu.vv v8, v8, v12439; RV32-NEXT: addi sp, sp, 16440; RV32-NEXT: .cfi_def_cfa_offset 0441; RV32-NEXT: ret442;443; RV64-LABEL: vaaddu_vx_v8i64_ceil:444; RV64: # %bb.0:445; RV64-NEXT: csrwi vxrm, 0446; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma447; RV64-NEXT: vaaddu.vx v8, v8, a0448; RV64-NEXT: ret449 %xzv = zext <8 x i64> %x to <8 x i128>450 %yhead = insertelement <8 x i64> poison, i64 %y, i64 0451 %ysplat = shufflevector <8 x i64> %yhead, <8 x i64> poison, <8 x i32> zeroinitializer452 %yzv = zext <8 x i64> %ysplat to <8 x i128>453 %add = add nuw nsw <8 x i128> %xzv, %yzv454 %add1 = add nuw nsw <8 x i128> %add, <i128 1, i128 1, i128 1, i128 1, i128 1, i128 1, i128 1, i128 1>455 %div = lshr <8 x i128> %add1, splat (i128 1)456 %ret = trunc <8 x i128> %div to <8 x i64>457 ret <8 x i64> %ret458}459