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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \3; RUN: | FileCheck %s --check-prefixes=CHECK,RV324; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \5; RUN: | FileCheck %s --check-prefixes=CHECK,RV646 7define <8 x i7> @vadd_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroext %evl) {8; CHECK-LABEL: vadd_vv_v8i7:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma11; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t12; CHECK-NEXT: ret13 %v = call <8 x i7> @llvm.vp.add.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl)14 ret <8 x i7> %v15}16 17define <2 x i8> @vadd_vv_v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 zeroext %evl) {18; CHECK-LABEL: vadd_vv_v2i8:19; CHECK: # %bb.0:20; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma21; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t22; CHECK-NEXT: ret23 %v = call <2 x i8> @llvm.vp.add.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 %evl)24 ret <2 x i8> %v25}26 27define <2 x i8> @vadd_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext %evl) {28; CHECK-LABEL: vadd_vv_v2i8_unmasked:29; CHECK: # %bb.0:30; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma31; CHECK-NEXT: vadd.vv v8, v8, v932; CHECK-NEXT: ret33 %v = call <2 x i8> @llvm.vp.add.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> splat (i1 true), i32 %evl)34 ret <2 x i8> %v35}36 37define <2 x i8> @vadd_vx_v2i8(<2 x i8> %va, i8 %b, <2 x i1> %m, i32 zeroext %evl) {38; CHECK-LABEL: vadd_vx_v2i8:39; CHECK: # %bb.0:40; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma41; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t42; CHECK-NEXT: ret43 %elt.head = insertelement <2 x i8> poison, i8 %b, i32 044 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer45 %v = call <2 x i8> @llvm.vp.add.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl)46 ret <2 x i8> %v47}48 49define <2 x i8> @vadd_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) {50; CHECK-LABEL: vadd_vx_v2i8_unmasked:51; CHECK: # %bb.0:52; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma53; CHECK-NEXT: vadd.vx v8, v8, a054; CHECK-NEXT: ret55 %elt.head = insertelement <2 x i8> poison, i8 %b, i32 056 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer57 %v = call <2 x i8> @llvm.vp.add.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> splat (i1 true), i32 %evl)58 ret <2 x i8> %v59}60 61define <2 x i8> @vadd_vi_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) {62; CHECK-LABEL: vadd_vi_v2i8:63; CHECK: # %bb.0:64; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma65; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t66; CHECK-NEXT: ret67 %v = call <2 x i8> @llvm.vp.add.v2i8(<2 x i8> %va, <2 x i8> splat (i8 -1), <2 x i1> %m, i32 %evl)68 ret <2 x i8> %v69}70 71define <2 x i8> @vadd_vi_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) {72; CHECK-LABEL: vadd_vi_v2i8_unmasked:73; CHECK: # %bb.0:74; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma75; CHECK-NEXT: vadd.vi v8, v8, -176; CHECK-NEXT: ret77 %v = call <2 x i8> @llvm.vp.add.v2i8(<2 x i8> %va, <2 x i8> splat (i8 -1), <2 x i1> splat (i1 true), i32 %evl)78 ret <2 x i8> %v79}80 81define <4 x i8> @vadd_vv_v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 zeroext %evl) {82; CHECK-LABEL: vadd_vv_v4i8:83; CHECK: # %bb.0:84; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma85; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t86; CHECK-NEXT: ret87 %v = call <4 x i8> @llvm.vp.add.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 %evl)88 ret <4 x i8> %v89}90 91define <4 x i8> @vadd_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext %evl) {92; CHECK-LABEL: vadd_vv_v4i8_unmasked:93; CHECK: # %bb.0:94; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma95; CHECK-NEXT: vadd.vv v8, v8, v996; CHECK-NEXT: ret97 %v = call <4 x i8> @llvm.vp.add.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> splat (i1 true), i32 %evl)98 ret <4 x i8> %v99}100 101define <4 x i8> @vadd_vx_v4i8(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zeroext %evl) {102; CHECK-LABEL: vadd_vx_v4i8:103; CHECK: # %bb.0:104; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma105; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t106; CHECK-NEXT: ret107 %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0108 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer109 %v = call <4 x i8> @llvm.vp.add.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl)110 ret <4 x i8> %v111}112 113define <4 x i8> @vadd_vx_v4i8_commute(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zeroext %evl) {114; CHECK-LABEL: vadd_vx_v4i8_commute:115; CHECK: # %bb.0:116; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma117; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t118; CHECK-NEXT: ret119 %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0120 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer121 %v = call <4 x i8> @llvm.vp.add.v4i8(<4 x i8> %vb, <4 x i8> %va, <4 x i1> %m, i32 %evl)122 ret <4 x i8> %v123}124 125define <4 x i8> @vadd_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) {126; CHECK-LABEL: vadd_vx_v4i8_unmasked:127; CHECK: # %bb.0:128; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma129; CHECK-NEXT: vadd.vx v8, v8, a0130; CHECK-NEXT: ret131 %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0132 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer133 %v = call <4 x i8> @llvm.vp.add.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> splat (i1 true), i32 %evl)134 ret <4 x i8> %v135}136 137define <4 x i8> @vadd_vi_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {138; CHECK-LABEL: vadd_vi_v4i8:139; CHECK: # %bb.0:140; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma141; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t142; CHECK-NEXT: ret143 %v = call <4 x i8> @llvm.vp.add.v4i8(<4 x i8> %va, <4 x i8> splat (i8 -1), <4 x i1> %m, i32 %evl)144 ret <4 x i8> %v145}146 147define <4 x i8> @vadd_vi_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {148; CHECK-LABEL: vadd_vi_v4i8_unmasked:149; CHECK: # %bb.0:150; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma151; CHECK-NEXT: vadd.vi v8, v8, -1152; CHECK-NEXT: ret153 %v = call <4 x i8> @llvm.vp.add.v4i8(<4 x i8> %va, <4 x i8> splat (i8 -1), <4 x i1> splat (i1 true), i32 %evl)154 ret <4 x i8> %v155}156 157define <5 x i8> @vadd_vv_v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> %m, i32 zeroext %evl) {158; CHECK-LABEL: vadd_vv_v5i8:159; CHECK: # %bb.0:160; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma161; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t162; CHECK-NEXT: ret163 %v = call <5 x i8> @llvm.vp.add.v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> %m, i32 %evl)164 ret <5 x i8> %v165}166 167define <5 x i8> @vadd_vv_v5i8_unmasked(<5 x i8> %va, <5 x i8> %b, i32 zeroext %evl) {168; CHECK-LABEL: vadd_vv_v5i8_unmasked:169; CHECK: # %bb.0:170; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma171; CHECK-NEXT: vadd.vv v8, v8, v9172; CHECK-NEXT: ret173 %v = call <5 x i8> @llvm.vp.add.v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> splat (i1 true), i32 %evl)174 ret <5 x i8> %v175}176 177define <5 x i8> @vadd_vx_v5i8(<5 x i8> %va, i8 %b, <5 x i1> %m, i32 zeroext %evl) {178; CHECK-LABEL: vadd_vx_v5i8:179; CHECK: # %bb.0:180; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma181; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t182; CHECK-NEXT: ret183 %elt.head = insertelement <5 x i8> poison, i8 %b, i32 0184 %vb = shufflevector <5 x i8> %elt.head, <5 x i8> poison, <5 x i32> zeroinitializer185 %v = call <5 x i8> @llvm.vp.add.v5i8(<5 x i8> %va, <5 x i8> %vb, <5 x i1> %m, i32 %evl)186 ret <5 x i8> %v187}188 189define <5 x i8> @vadd_vx_v5i8_unmasked(<5 x i8> %va, i8 %b, i32 zeroext %evl) {190; CHECK-LABEL: vadd_vx_v5i8_unmasked:191; CHECK: # %bb.0:192; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma193; CHECK-NEXT: vadd.vx v8, v8, a0194; CHECK-NEXT: ret195 %elt.head = insertelement <5 x i8> poison, i8 %b, i32 0196 %vb = shufflevector <5 x i8> %elt.head, <5 x i8> poison, <5 x i32> zeroinitializer197 %v = call <5 x i8> @llvm.vp.add.v5i8(<5 x i8> %va, <5 x i8> %vb, <5 x i1> splat (i1 true), i32 %evl)198 ret <5 x i8> %v199}200 201define <5 x i8> @vadd_vi_v5i8(<5 x i8> %va, <5 x i1> %m, i32 zeroext %evl) {202; CHECK-LABEL: vadd_vi_v5i8:203; CHECK: # %bb.0:204; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma205; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t206; CHECK-NEXT: ret207 %v = call <5 x i8> @llvm.vp.add.v5i8(<5 x i8> %va, <5 x i8> splat (i8 -1), <5 x i1> %m, i32 %evl)208 ret <5 x i8> %v209}210 211define <5 x i8> @vadd_vi_v5i8_unmasked(<5 x i8> %va, i32 zeroext %evl) {212; CHECK-LABEL: vadd_vi_v5i8_unmasked:213; CHECK: # %bb.0:214; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma215; CHECK-NEXT: vadd.vi v8, v8, -1216; CHECK-NEXT: ret217 %v = call <5 x i8> @llvm.vp.add.v5i8(<5 x i8> %va, <5 x i8> splat (i8 -1), <5 x i1> splat (i1 true), i32 %evl)218 ret <5 x i8> %v219}220 221define <8 x i8> @vadd_vv_v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 zeroext %evl) {222; CHECK-LABEL: vadd_vv_v8i8:223; CHECK: # %bb.0:224; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma225; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t226; CHECK-NEXT: ret227 %v = call <8 x i8> @llvm.vp.add.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 %evl)228 ret <8 x i8> %v229}230 231define <8 x i8> @vadd_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext %evl) {232; CHECK-LABEL: vadd_vv_v8i8_unmasked:233; CHECK: # %bb.0:234; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma235; CHECK-NEXT: vadd.vv v8, v8, v9236; CHECK-NEXT: ret237 %v = call <8 x i8> @llvm.vp.add.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> splat (i1 true), i32 %evl)238 ret <8 x i8> %v239}240 241define <8 x i8> @vadd_vx_v8i8(<8 x i8> %va, i8 %b, <8 x i1> %m, i32 zeroext %evl) {242; CHECK-LABEL: vadd_vx_v8i8:243; CHECK: # %bb.0:244; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma245; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t246; CHECK-NEXT: ret247 %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0248 %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer249 %v = call <8 x i8> @llvm.vp.add.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl)250 ret <8 x i8> %v251}252 253define <8 x i8> @vadd_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) {254; CHECK-LABEL: vadd_vx_v8i8_unmasked:255; CHECK: # %bb.0:256; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma257; CHECK-NEXT: vadd.vx v8, v8, a0258; CHECK-NEXT: ret259 %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0260 %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer261 %v = call <8 x i8> @llvm.vp.add.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> splat (i1 true), i32 %evl)262 ret <8 x i8> %v263}264 265define <8 x i8> @vadd_vi_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) {266; CHECK-LABEL: vadd_vi_v8i8:267; CHECK: # %bb.0:268; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma269; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t270; CHECK-NEXT: ret271 %v = call <8 x i8> @llvm.vp.add.v8i8(<8 x i8> %va, <8 x i8> splat (i8 -1), <8 x i1> %m, i32 %evl)272 ret <8 x i8> %v273}274 275define <8 x i8> @vadd_vi_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) {276; CHECK-LABEL: vadd_vi_v8i8_unmasked:277; CHECK: # %bb.0:278; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma279; CHECK-NEXT: vadd.vi v8, v8, -1280; CHECK-NEXT: ret281 %v = call <8 x i8> @llvm.vp.add.v8i8(<8 x i8> %va, <8 x i8> splat (i8 -1), <8 x i1> splat (i1 true), i32 %evl)282 ret <8 x i8> %v283}284 285define <16 x i8> @vadd_vv_v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 zeroext %evl) {286; CHECK-LABEL: vadd_vv_v16i8:287; CHECK: # %bb.0:288; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma289; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t290; CHECK-NEXT: ret291 %v = call <16 x i8> @llvm.vp.add.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 %evl)292 ret <16 x i8> %v293}294 295define <16 x i8> @vadd_vv_v16i8_unmasked(<16 x i8> %va, <16 x i8> %b, i32 zeroext %evl) {296; CHECK-LABEL: vadd_vv_v16i8_unmasked:297; CHECK: # %bb.0:298; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma299; CHECK-NEXT: vadd.vv v8, v8, v9300; CHECK-NEXT: ret301 %v = call <16 x i8> @llvm.vp.add.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> splat (i1 true), i32 %evl)302 ret <16 x i8> %v303}304 305define <16 x i8> @vadd_vx_v16i8(<16 x i8> %va, i8 %b, <16 x i1> %m, i32 zeroext %evl) {306; CHECK-LABEL: vadd_vx_v16i8:307; CHECK: # %bb.0:308; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma309; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t310; CHECK-NEXT: ret311 %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0312 %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer313 %v = call <16 x i8> @llvm.vp.add.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl)314 ret <16 x i8> %v315}316 317define <16 x i8> @vadd_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %evl) {318; CHECK-LABEL: vadd_vx_v16i8_unmasked:319; CHECK: # %bb.0:320; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma321; CHECK-NEXT: vadd.vx v8, v8, a0322; CHECK-NEXT: ret323 %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0324 %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer325 %v = call <16 x i8> @llvm.vp.add.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> splat (i1 true), i32 %evl)326 ret <16 x i8> %v327}328 329define <16 x i8> @vadd_vi_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) {330; CHECK-LABEL: vadd_vi_v16i8:331; CHECK: # %bb.0:332; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma333; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t334; CHECK-NEXT: ret335 %v = call <16 x i8> @llvm.vp.add.v16i8(<16 x i8> %va, <16 x i8> splat (i8 -1), <16 x i1> %m, i32 %evl)336 ret <16 x i8> %v337}338 339define <16 x i8> @vadd_vi_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) {340; CHECK-LABEL: vadd_vi_v16i8_unmasked:341; CHECK: # %bb.0:342; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma343; CHECK-NEXT: vadd.vi v8, v8, -1344; CHECK-NEXT: ret345 %v = call <16 x i8> @llvm.vp.add.v16i8(<16 x i8> %va, <16 x i8> splat (i8 -1), <16 x i1> splat (i1 true), i32 %evl)346 ret <16 x i8> %v347}348 349define <256 x i8> @vadd_vi_v258i8(<256 x i8> %va, <256 x i1> %m, i32 zeroext %evl) {350; CHECK-LABEL: vadd_vi_v258i8:351; CHECK: # %bb.0:352; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma353; CHECK-NEXT: vmv1r.v v24, v0354; CHECK-NEXT: li a2, 128355; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma356; CHECK-NEXT: vlm.v v0, (a0)357; CHECK-NEXT: addi a0, a1, -128358; CHECK-NEXT: sltu a3, a1, a0359; CHECK-NEXT: addi a3, a3, -1360; CHECK-NEXT: and a0, a3, a0361; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma362; CHECK-NEXT: vadd.vi v16, v16, -1, v0.t363; CHECK-NEXT: bltu a1, a2, .LBB32_2364; CHECK-NEXT: # %bb.1:365; CHECK-NEXT: li a1, 128366; CHECK-NEXT: .LBB32_2:367; CHECK-NEXT: vmv1r.v v0, v24368; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma369; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t370; CHECK-NEXT: ret371 %v = call <256 x i8> @llvm.vp.add.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 %evl)372 ret <256 x i8> %v373}374 375define <256 x i8> @vadd_vi_v258i8_unmasked(<256 x i8> %va, i32 zeroext %evl) {376; CHECK-LABEL: vadd_vi_v258i8_unmasked:377; CHECK: # %bb.0:378; CHECK-NEXT: li a2, 128379; CHECK-NEXT: mv a1, a0380; CHECK-NEXT: bltu a0, a2, .LBB33_2381; CHECK-NEXT: # %bb.1:382; CHECK-NEXT: li a1, 128383; CHECK-NEXT: .LBB33_2:384; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma385; CHECK-NEXT: vadd.vi v8, v8, -1386; CHECK-NEXT: addi a1, a0, -128387; CHECK-NEXT: sltu a0, a0, a1388; CHECK-NEXT: addi a0, a0, -1389; CHECK-NEXT: and a0, a0, a1390; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma391; CHECK-NEXT: vadd.vi v16, v16, -1392; CHECK-NEXT: ret393 %v = call <256 x i8> @llvm.vp.add.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> splat (i1 true), i32 %evl)394 ret <256 x i8> %v395}396 397; Test splitting when the %evl is a known constant.398 399define <256 x i8> @vadd_vi_v258i8_evl129(<256 x i8> %va, <256 x i1> %m) {400; CHECK-LABEL: vadd_vi_v258i8_evl129:401; CHECK: # %bb.0:402; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, ma403; CHECK-NEXT: vlm.v v24, (a0)404; CHECK-NEXT: li a0, 128405; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma406; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t407; CHECK-NEXT: vmv1r.v v0, v24408; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, ma409; CHECK-NEXT: vadd.vi v16, v16, -1, v0.t410; CHECK-NEXT: ret411 %v = call <256 x i8> @llvm.vp.add.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 129)412 ret <256 x i8> %v413}414 415; FIXME: The upper half is doing nothing.416 417define <256 x i8> @vadd_vi_v258i8_evl128(<256 x i8> %va, <256 x i1> %m) {418; CHECK-LABEL: vadd_vi_v258i8_evl128:419; CHECK: # %bb.0:420; CHECK-NEXT: li a0, 128421; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma422; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t423; CHECK-NEXT: ret424 %v = call <256 x i8> @llvm.vp.add.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 128)425 ret <256 x i8> %v426}427 428define <2 x i16> @vadd_vv_v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 zeroext %evl) {429; CHECK-LABEL: vadd_vv_v2i16:430; CHECK: # %bb.0:431; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma432; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t433; CHECK-NEXT: ret434 %v = call <2 x i16> @llvm.vp.add.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 %evl)435 ret <2 x i16> %v436}437 438define <2 x i16> @vadd_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zeroext %evl) {439; CHECK-LABEL: vadd_vv_v2i16_unmasked:440; CHECK: # %bb.0:441; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma442; CHECK-NEXT: vadd.vv v8, v8, v9443; CHECK-NEXT: ret444 %v = call <2 x i16> @llvm.vp.add.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> splat (i1 true), i32 %evl)445 ret <2 x i16> %v446}447 448define <2 x i16> @vadd_vx_v2i16(<2 x i16> %va, i16 %b, <2 x i1> %m, i32 zeroext %evl) {449; CHECK-LABEL: vadd_vx_v2i16:450; CHECK: # %bb.0:451; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma452; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t453; CHECK-NEXT: ret454 %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0455 %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer456 %v = call <2 x i16> @llvm.vp.add.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl)457 ret <2 x i16> %v458}459 460define <2 x i16> @vadd_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %evl) {461; CHECK-LABEL: vadd_vx_v2i16_unmasked:462; CHECK: # %bb.0:463; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma464; CHECK-NEXT: vadd.vx v8, v8, a0465; CHECK-NEXT: ret466 %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0467 %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer468 %v = call <2 x i16> @llvm.vp.add.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> splat (i1 true), i32 %evl)469 ret <2 x i16> %v470}471 472define <2 x i16> @vadd_vi_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) {473; CHECK-LABEL: vadd_vi_v2i16:474; CHECK: # %bb.0:475; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma476; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t477; CHECK-NEXT: ret478 %v = call <2 x i16> @llvm.vp.add.v2i16(<2 x i16> %va, <2 x i16> splat (i16 -1), <2 x i1> %m, i32 %evl)479 ret <2 x i16> %v480}481 482define <2 x i16> @vadd_vi_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) {483; CHECK-LABEL: vadd_vi_v2i16_unmasked:484; CHECK: # %bb.0:485; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma486; CHECK-NEXT: vadd.vi v8, v8, -1487; CHECK-NEXT: ret488 %v = call <2 x i16> @llvm.vp.add.v2i16(<2 x i16> %va, <2 x i16> splat (i16 -1), <2 x i1> splat (i1 true), i32 %evl)489 ret <2 x i16> %v490}491 492define <4 x i16> @vadd_vv_v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 zeroext %evl) {493; CHECK-LABEL: vadd_vv_v4i16:494; CHECK: # %bb.0:495; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma496; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t497; CHECK-NEXT: ret498 %v = call <4 x i16> @llvm.vp.add.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 %evl)499 ret <4 x i16> %v500}501 502define <4 x i16> @vadd_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zeroext %evl) {503; CHECK-LABEL: vadd_vv_v4i16_unmasked:504; CHECK: # %bb.0:505; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma506; CHECK-NEXT: vadd.vv v8, v8, v9507; CHECK-NEXT: ret508 %v = call <4 x i16> @llvm.vp.add.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> splat (i1 true), i32 %evl)509 ret <4 x i16> %v510}511 512define <4 x i16> @vadd_vx_v4i16(<4 x i16> %va, i16 %b, <4 x i1> %m, i32 zeroext %evl) {513; CHECK-LABEL: vadd_vx_v4i16:514; CHECK: # %bb.0:515; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma516; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t517; CHECK-NEXT: ret518 %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0519 %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer520 %v = call <4 x i16> @llvm.vp.add.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl)521 ret <4 x i16> %v522}523 524define <4 x i16> @vadd_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %evl) {525; CHECK-LABEL: vadd_vx_v4i16_unmasked:526; CHECK: # %bb.0:527; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma528; CHECK-NEXT: vadd.vx v8, v8, a0529; CHECK-NEXT: ret530 %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0531 %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer532 %v = call <4 x i16> @llvm.vp.add.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> splat (i1 true), i32 %evl)533 ret <4 x i16> %v534}535 536define <4 x i16> @vadd_vi_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {537; CHECK-LABEL: vadd_vi_v4i16:538; CHECK: # %bb.0:539; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma540; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t541; CHECK-NEXT: ret542 %v = call <4 x i16> @llvm.vp.add.v4i16(<4 x i16> %va, <4 x i16> splat (i16 -1), <4 x i1> %m, i32 %evl)543 ret <4 x i16> %v544}545 546define <4 x i16> @vadd_vi_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {547; CHECK-LABEL: vadd_vi_v4i16_unmasked:548; CHECK: # %bb.0:549; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma550; CHECK-NEXT: vadd.vi v8, v8, -1551; CHECK-NEXT: ret552 %v = call <4 x i16> @llvm.vp.add.v4i16(<4 x i16> %va, <4 x i16> splat (i16 -1), <4 x i1> splat (i1 true), i32 %evl)553 ret <4 x i16> %v554}555 556define <8 x i16> @vadd_vv_v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 zeroext %evl) {557; CHECK-LABEL: vadd_vv_v8i16:558; CHECK: # %bb.0:559; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma560; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t561; CHECK-NEXT: ret562 %v = call <8 x i16> @llvm.vp.add.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 %evl)563 ret <8 x i16> %v564}565 566define <8 x i16> @vadd_vv_v8i16_unmasked(<8 x i16> %va, <8 x i16> %b, i32 zeroext %evl) {567; CHECK-LABEL: vadd_vv_v8i16_unmasked:568; CHECK: # %bb.0:569; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma570; CHECK-NEXT: vadd.vv v8, v8, v9571; CHECK-NEXT: ret572 %v = call <8 x i16> @llvm.vp.add.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> splat (i1 true), i32 %evl)573 ret <8 x i16> %v574}575 576define <8 x i16> @vadd_vx_v8i16(<8 x i16> %va, i16 %b, <8 x i1> %m, i32 zeroext %evl) {577; CHECK-LABEL: vadd_vx_v8i16:578; CHECK: # %bb.0:579; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma580; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t581; CHECK-NEXT: ret582 %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0583 %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer584 %v = call <8 x i16> @llvm.vp.add.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl)585 ret <8 x i16> %v586}587 588define <8 x i16> @vadd_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %evl) {589; CHECK-LABEL: vadd_vx_v8i16_unmasked:590; CHECK: # %bb.0:591; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma592; CHECK-NEXT: vadd.vx v8, v8, a0593; CHECK-NEXT: ret594 %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0595 %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer596 %v = call <8 x i16> @llvm.vp.add.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> splat (i1 true), i32 %evl)597 ret <8 x i16> %v598}599 600define <8 x i16> @vadd_vi_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) {601; CHECK-LABEL: vadd_vi_v8i16:602; CHECK: # %bb.0:603; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma604; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t605; CHECK-NEXT: ret606 %v = call <8 x i16> @llvm.vp.add.v8i16(<8 x i16> %va, <8 x i16> splat (i16 -1), <8 x i1> %m, i32 %evl)607 ret <8 x i16> %v608}609 610define <8 x i16> @vadd_vi_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) {611; CHECK-LABEL: vadd_vi_v8i16_unmasked:612; CHECK: # %bb.0:613; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma614; CHECK-NEXT: vadd.vi v8, v8, -1615; CHECK-NEXT: ret616 %v = call <8 x i16> @llvm.vp.add.v8i16(<8 x i16> %va, <8 x i16> splat (i16 -1), <8 x i1> splat (i1 true), i32 %evl)617 ret <8 x i16> %v618}619 620define <16 x i16> @vadd_vv_v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 zeroext %evl) {621; CHECK-LABEL: vadd_vv_v16i16:622; CHECK: # %bb.0:623; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma624; CHECK-NEXT: vadd.vv v8, v8, v10, v0.t625; CHECK-NEXT: ret626 %v = call <16 x i16> @llvm.vp.add.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 %evl)627 ret <16 x i16> %v628}629 630define <16 x i16> @vadd_vv_v16i16_unmasked(<16 x i16> %va, <16 x i16> %b, i32 zeroext %evl) {631; CHECK-LABEL: vadd_vv_v16i16_unmasked:632; CHECK: # %bb.0:633; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma634; CHECK-NEXT: vadd.vv v8, v8, v10635; CHECK-NEXT: ret636 %v = call <16 x i16> @llvm.vp.add.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> splat (i1 true), i32 %evl)637 ret <16 x i16> %v638}639 640define <16 x i16> @vadd_vx_v16i16(<16 x i16> %va, i16 %b, <16 x i1> %m, i32 zeroext %evl) {641; CHECK-LABEL: vadd_vx_v16i16:642; CHECK: # %bb.0:643; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma644; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t645; CHECK-NEXT: ret646 %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0647 %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer648 %v = call <16 x i16> @llvm.vp.add.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl)649 ret <16 x i16> %v650}651 652define <16 x i16> @vadd_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext %evl) {653; CHECK-LABEL: vadd_vx_v16i16_unmasked:654; CHECK: # %bb.0:655; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma656; CHECK-NEXT: vadd.vx v8, v8, a0657; CHECK-NEXT: ret658 %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0659 %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer660 %v = call <16 x i16> @llvm.vp.add.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> splat (i1 true), i32 %evl)661 ret <16 x i16> %v662}663 664define <16 x i16> @vadd_vi_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) {665; CHECK-LABEL: vadd_vi_v16i16:666; CHECK: # %bb.0:667; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma668; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t669; CHECK-NEXT: ret670 %v = call <16 x i16> @llvm.vp.add.v16i16(<16 x i16> %va, <16 x i16> splat (i16 -1), <16 x i1> %m, i32 %evl)671 ret <16 x i16> %v672}673 674define <16 x i16> @vadd_vi_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) {675; CHECK-LABEL: vadd_vi_v16i16_unmasked:676; CHECK: # %bb.0:677; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma678; CHECK-NEXT: vadd.vi v8, v8, -1679; CHECK-NEXT: ret680 %v = call <16 x i16> @llvm.vp.add.v16i16(<16 x i16> %va, <16 x i16> splat (i16 -1), <16 x i1> splat (i1 true), i32 %evl)681 ret <16 x i16> %v682}683 684define <2 x i32> @vadd_vv_v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 zeroext %evl) {685; CHECK-LABEL: vadd_vv_v2i32:686; CHECK: # %bb.0:687; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma688; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t689; CHECK-NEXT: ret690 %v = call <2 x i32> @llvm.vp.add.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 %evl)691 ret <2 x i32> %v692}693 694define <2 x i32> @vadd_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zeroext %evl) {695; CHECK-LABEL: vadd_vv_v2i32_unmasked:696; CHECK: # %bb.0:697; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma698; CHECK-NEXT: vadd.vv v8, v8, v9699; CHECK-NEXT: ret700 %v = call <2 x i32> @llvm.vp.add.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> splat (i1 true), i32 %evl)701 ret <2 x i32> %v702}703 704define <2 x i32> @vadd_vx_v2i32(<2 x i32> %va, i32 %b, <2 x i1> %m, i32 zeroext %evl) {705; CHECK-LABEL: vadd_vx_v2i32:706; CHECK: # %bb.0:707; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma708; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t709; CHECK-NEXT: ret710 %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0711 %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer712 %v = call <2 x i32> @llvm.vp.add.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl)713 ret <2 x i32> %v714}715 716define <2 x i32> @vadd_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %evl) {717; CHECK-LABEL: vadd_vx_v2i32_unmasked:718; CHECK: # %bb.0:719; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma720; CHECK-NEXT: vadd.vx v8, v8, a0721; CHECK-NEXT: ret722 %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0723 %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer724 %v = call <2 x i32> @llvm.vp.add.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> splat (i1 true), i32 %evl)725 ret <2 x i32> %v726}727 728define <2 x i32> @vadd_vi_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) {729; CHECK-LABEL: vadd_vi_v2i32:730; CHECK: # %bb.0:731; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma732; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t733; CHECK-NEXT: ret734 %v = call <2 x i32> @llvm.vp.add.v2i32(<2 x i32> %va, <2 x i32> splat (i32 -1), <2 x i1> %m, i32 %evl)735 ret <2 x i32> %v736}737 738define <2 x i32> @vadd_vi_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) {739; CHECK-LABEL: vadd_vi_v2i32_unmasked:740; CHECK: # %bb.0:741; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma742; CHECK-NEXT: vadd.vi v8, v8, -1743; CHECK-NEXT: ret744 %v = call <2 x i32> @llvm.vp.add.v2i32(<2 x i32> %va, <2 x i32> splat (i32 -1), <2 x i1> splat (i1 true), i32 %evl)745 ret <2 x i32> %v746}747 748define <4 x i32> @vadd_vv_v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 zeroext %evl) {749; CHECK-LABEL: vadd_vv_v4i32:750; CHECK: # %bb.0:751; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma752; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t753; CHECK-NEXT: ret754 %v = call <4 x i32> @llvm.vp.add.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 %evl)755 ret <4 x i32> %v756}757 758define <4 x i32> @vadd_vv_v4i32_unmasked(<4 x i32> %va, <4 x i32> %b, i32 zeroext %evl) {759; CHECK-LABEL: vadd_vv_v4i32_unmasked:760; CHECK: # %bb.0:761; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma762; CHECK-NEXT: vadd.vv v8, v8, v9763; CHECK-NEXT: ret764 %v = call <4 x i32> @llvm.vp.add.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> splat (i1 true), i32 %evl)765 ret <4 x i32> %v766}767 768define <4 x i32> @vadd_vx_v4i32(<4 x i32> %va, i32 %b, <4 x i1> %m, i32 zeroext %evl) {769; CHECK-LABEL: vadd_vx_v4i32:770; CHECK: # %bb.0:771; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma772; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t773; CHECK-NEXT: ret774 %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0775 %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer776 %v = call <4 x i32> @llvm.vp.add.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl)777 ret <4 x i32> %v778}779 780define <4 x i32> @vadd_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %evl) {781; CHECK-LABEL: vadd_vx_v4i32_unmasked:782; CHECK: # %bb.0:783; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma784; CHECK-NEXT: vadd.vx v8, v8, a0785; CHECK-NEXT: ret786 %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0787 %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer788 %v = call <4 x i32> @llvm.vp.add.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> splat (i1 true), i32 %evl)789 ret <4 x i32> %v790}791 792define <4 x i32> @vadd_vi_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {793; CHECK-LABEL: vadd_vi_v4i32:794; CHECK: # %bb.0:795; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma796; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t797; CHECK-NEXT: ret798 %v = call <4 x i32> @llvm.vp.add.v4i32(<4 x i32> %va, <4 x i32> splat (i32 -1), <4 x i1> %m, i32 %evl)799 ret <4 x i32> %v800}801 802define <4 x i32> @vadd_vi_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {803; CHECK-LABEL: vadd_vi_v4i32_unmasked:804; CHECK: # %bb.0:805; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma806; CHECK-NEXT: vadd.vi v8, v8, -1807; CHECK-NEXT: ret808 %v = call <4 x i32> @llvm.vp.add.v4i32(<4 x i32> %va, <4 x i32> splat (i32 -1), <4 x i1> splat (i1 true), i32 %evl)809 ret <4 x i32> %v810}811 812define <8 x i32> @vadd_vv_v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 zeroext %evl) {813; CHECK-LABEL: vadd_vv_v8i32:814; CHECK: # %bb.0:815; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma816; CHECK-NEXT: vadd.vv v8, v8, v10, v0.t817; CHECK-NEXT: ret818 %v = call <8 x i32> @llvm.vp.add.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 %evl)819 ret <8 x i32> %v820}821 822define <8 x i32> @vadd_vv_v8i32_unmasked(<8 x i32> %va, <8 x i32> %b, i32 zeroext %evl) {823; CHECK-LABEL: vadd_vv_v8i32_unmasked:824; CHECK: # %bb.0:825; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma826; CHECK-NEXT: vadd.vv v8, v8, v10827; CHECK-NEXT: ret828 %v = call <8 x i32> @llvm.vp.add.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> splat (i1 true), i32 %evl)829 ret <8 x i32> %v830}831 832define <8 x i32> @vadd_vx_v8i32(<8 x i32> %va, i32 %b, <8 x i1> %m, i32 zeroext %evl) {833; CHECK-LABEL: vadd_vx_v8i32:834; CHECK: # %bb.0:835; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma836; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t837; CHECK-NEXT: ret838 %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0839 %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer840 %v = call <8 x i32> @llvm.vp.add.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl)841 ret <8 x i32> %v842}843 844define <8 x i32> @vadd_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %evl) {845; CHECK-LABEL: vadd_vx_v8i32_unmasked:846; CHECK: # %bb.0:847; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma848; CHECK-NEXT: vadd.vx v8, v8, a0849; CHECK-NEXT: ret850 %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0851 %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer852 %v = call <8 x i32> @llvm.vp.add.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> splat (i1 true), i32 %evl)853 ret <8 x i32> %v854}855 856define <8 x i32> @vadd_vi_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) {857; CHECK-LABEL: vadd_vi_v8i32:858; CHECK: # %bb.0:859; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma860; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t861; CHECK-NEXT: ret862 %v = call <8 x i32> @llvm.vp.add.v8i32(<8 x i32> %va, <8 x i32> splat (i32 -1), <8 x i1> %m, i32 %evl)863 ret <8 x i32> %v864}865 866define <8 x i32> @vadd_vi_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) {867; CHECK-LABEL: vadd_vi_v8i32_unmasked:868; CHECK: # %bb.0:869; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma870; CHECK-NEXT: vadd.vi v8, v8, -1871; CHECK-NEXT: ret872 %v = call <8 x i32> @llvm.vp.add.v8i32(<8 x i32> %va, <8 x i32> splat (i32 -1), <8 x i1> splat (i1 true), i32 %evl)873 ret <8 x i32> %v874}875 876define <16 x i32> @vadd_vv_v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 zeroext %evl) {877; CHECK-LABEL: vadd_vv_v16i32:878; CHECK: # %bb.0:879; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma880; CHECK-NEXT: vadd.vv v8, v8, v12, v0.t881; CHECK-NEXT: ret882 %v = call <16 x i32> @llvm.vp.add.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 %evl)883 ret <16 x i32> %v884}885 886define <16 x i32> @vadd_vv_v16i32_unmasked(<16 x i32> %va, <16 x i32> %b, i32 zeroext %evl) {887; CHECK-LABEL: vadd_vv_v16i32_unmasked:888; CHECK: # %bb.0:889; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma890; CHECK-NEXT: vadd.vv v8, v8, v12891; CHECK-NEXT: ret892 %v = call <16 x i32> @llvm.vp.add.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> splat (i1 true), i32 %evl)893 ret <16 x i32> %v894}895 896define <16 x i32> @vadd_vx_v16i32(<16 x i32> %va, i32 %b, <16 x i1> %m, i32 zeroext %evl) {897; CHECK-LABEL: vadd_vx_v16i32:898; CHECK: # %bb.0:899; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma900; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t901; CHECK-NEXT: ret902 %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0903 %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer904 %v = call <16 x i32> @llvm.vp.add.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl)905 ret <16 x i32> %v906}907 908define <16 x i32> @vadd_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext %evl) {909; CHECK-LABEL: vadd_vx_v16i32_unmasked:910; CHECK: # %bb.0:911; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma912; CHECK-NEXT: vadd.vx v8, v8, a0913; CHECK-NEXT: ret914 %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0915 %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer916 %v = call <16 x i32> @llvm.vp.add.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> splat (i1 true), i32 %evl)917 ret <16 x i32> %v918}919 920define <16 x i32> @vadd_vi_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) {921; CHECK-LABEL: vadd_vi_v16i32:922; CHECK: # %bb.0:923; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma924; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t925; CHECK-NEXT: ret926 %v = call <16 x i32> @llvm.vp.add.v16i32(<16 x i32> %va, <16 x i32> splat (i32 -1), <16 x i1> %m, i32 %evl)927 ret <16 x i32> %v928}929 930define <16 x i32> @vadd_vi_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) {931; CHECK-LABEL: vadd_vi_v16i32_unmasked:932; CHECK: # %bb.0:933; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma934; CHECK-NEXT: vadd.vi v8, v8, -1935; CHECK-NEXT: ret936 %v = call <16 x i32> @llvm.vp.add.v16i32(<16 x i32> %va, <16 x i32> splat (i32 -1), <16 x i1> splat (i1 true), i32 %evl)937 ret <16 x i32> %v938}939 940define <2 x i64> @vadd_vv_v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 zeroext %evl) {941; CHECK-LABEL: vadd_vv_v2i64:942; CHECK: # %bb.0:943; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma944; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t945; CHECK-NEXT: ret946 %v = call <2 x i64> @llvm.vp.add.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 %evl)947 ret <2 x i64> %v948}949 950define <2 x i64> @vadd_vv_v2i64_unmasked(<2 x i64> %va, <2 x i64> %b, i32 zeroext %evl) {951; CHECK-LABEL: vadd_vv_v2i64_unmasked:952; CHECK: # %bb.0:953; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma954; CHECK-NEXT: vadd.vv v8, v8, v9955; CHECK-NEXT: ret956 %v = call <2 x i64> @llvm.vp.add.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> splat (i1 true), i32 %evl)957 ret <2 x i64> %v958}959 960define <2 x i64> @vadd_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext %evl) {961; RV32-LABEL: vadd_vx_v2i64:962; RV32: # %bb.0:963; RV32-NEXT: addi sp, sp, -16964; RV32-NEXT: .cfi_def_cfa_offset 16965; RV32-NEXT: sw a0, 8(sp)966; RV32-NEXT: sw a1, 12(sp)967; RV32-NEXT: addi a0, sp, 8968; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma969; RV32-NEXT: vlse64.v v9, (a0), zero970; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma971; RV32-NEXT: vadd.vv v8, v8, v9, v0.t972; RV32-NEXT: addi sp, sp, 16973; RV32-NEXT: .cfi_def_cfa_offset 0974; RV32-NEXT: ret975;976; RV64-LABEL: vadd_vx_v2i64:977; RV64: # %bb.0:978; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma979; RV64-NEXT: vadd.vx v8, v8, a0, v0.t980; RV64-NEXT: ret981 %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0982 %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer983 %v = call <2 x i64> @llvm.vp.add.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl)984 ret <2 x i64> %v985}986 987define <2 x i64> @vadd_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl) {988; RV32-LABEL: vadd_vx_v2i64_unmasked:989; RV32: # %bb.0:990; RV32-NEXT: addi sp, sp, -16991; RV32-NEXT: .cfi_def_cfa_offset 16992; RV32-NEXT: sw a0, 8(sp)993; RV32-NEXT: sw a1, 12(sp)994; RV32-NEXT: addi a0, sp, 8995; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma996; RV32-NEXT: vlse64.v v9, (a0), zero997; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma998; RV32-NEXT: vadd.vv v8, v8, v9999; RV32-NEXT: addi sp, sp, 161000; RV32-NEXT: .cfi_def_cfa_offset 01001; RV32-NEXT: ret1002;1003; RV64-LABEL: vadd_vx_v2i64_unmasked:1004; RV64: # %bb.0:1005; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma1006; RV64-NEXT: vadd.vx v8, v8, a01007; RV64-NEXT: ret1008 %elt.head = insertelement <2 x i64> poison, i64 %b, i32 01009 %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer1010 %v = call <2 x i64> @llvm.vp.add.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> splat (i1 true), i32 %evl)1011 ret <2 x i64> %v1012}1013 1014define <2 x i64> @vadd_vi_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {1015; CHECK-LABEL: vadd_vi_v2i64:1016; CHECK: # %bb.0:1017; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma1018; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t1019; CHECK-NEXT: ret1020 %v = call <2 x i64> @llvm.vp.add.v2i64(<2 x i64> %va, <2 x i64> splat (i64 -1), <2 x i1> %m, i32 %evl)1021 ret <2 x i64> %v1022}1023 1024define <2 x i64> @vadd_vi_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {1025; CHECK-LABEL: vadd_vi_v2i64_unmasked:1026; CHECK: # %bb.0:1027; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma1028; CHECK-NEXT: vadd.vi v8, v8, -11029; CHECK-NEXT: ret1030 %v = call <2 x i64> @llvm.vp.add.v2i64(<2 x i64> %va, <2 x i64> splat (i64 -1), <2 x i1> splat (i1 true), i32 %evl)1031 ret <2 x i64> %v1032}1033 1034define <4 x i64> @vadd_vv_v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 zeroext %evl) {1035; CHECK-LABEL: vadd_vv_v4i64:1036; CHECK: # %bb.0:1037; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma1038; CHECK-NEXT: vadd.vv v8, v8, v10, v0.t1039; CHECK-NEXT: ret1040 %v = call <4 x i64> @llvm.vp.add.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 %evl)1041 ret <4 x i64> %v1042}1043 1044define <4 x i64> @vadd_vv_v4i64_unmasked(<4 x i64> %va, <4 x i64> %b, i32 zeroext %evl) {1045; CHECK-LABEL: vadd_vv_v4i64_unmasked:1046; CHECK: # %bb.0:1047; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma1048; CHECK-NEXT: vadd.vv v8, v8, v101049; CHECK-NEXT: ret1050 %v = call <4 x i64> @llvm.vp.add.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> splat (i1 true), i32 %evl)1051 ret <4 x i64> %v1052}1053 1054define <4 x i64> @vadd_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext %evl) {1055; RV32-LABEL: vadd_vx_v4i64:1056; RV32: # %bb.0:1057; RV32-NEXT: addi sp, sp, -161058; RV32-NEXT: .cfi_def_cfa_offset 161059; RV32-NEXT: sw a0, 8(sp)1060; RV32-NEXT: sw a1, 12(sp)1061; RV32-NEXT: addi a0, sp, 81062; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma1063; RV32-NEXT: vlse64.v v10, (a0), zero1064; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma1065; RV32-NEXT: vadd.vv v8, v8, v10, v0.t1066; RV32-NEXT: addi sp, sp, 161067; RV32-NEXT: .cfi_def_cfa_offset 01068; RV32-NEXT: ret1069;1070; RV64-LABEL: vadd_vx_v4i64:1071; RV64: # %bb.0:1072; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma1073; RV64-NEXT: vadd.vx v8, v8, a0, v0.t1074; RV64-NEXT: ret1075 %elt.head = insertelement <4 x i64> poison, i64 %b, i32 01076 %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer1077 %v = call <4 x i64> @llvm.vp.add.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl)1078 ret <4 x i64> %v1079}1080 1081define <4 x i64> @vadd_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl) {1082; RV32-LABEL: vadd_vx_v4i64_unmasked:1083; RV32: # %bb.0:1084; RV32-NEXT: addi sp, sp, -161085; RV32-NEXT: .cfi_def_cfa_offset 161086; RV32-NEXT: sw a0, 8(sp)1087; RV32-NEXT: sw a1, 12(sp)1088; RV32-NEXT: addi a0, sp, 81089; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma1090; RV32-NEXT: vlse64.v v10, (a0), zero1091; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma1092; RV32-NEXT: vadd.vv v8, v8, v101093; RV32-NEXT: addi sp, sp, 161094; RV32-NEXT: .cfi_def_cfa_offset 01095; RV32-NEXT: ret1096;1097; RV64-LABEL: vadd_vx_v4i64_unmasked:1098; RV64: # %bb.0:1099; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma1100; RV64-NEXT: vadd.vx v8, v8, a01101; RV64-NEXT: ret1102 %elt.head = insertelement <4 x i64> poison, i64 %b, i32 01103 %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer1104 %v = call <4 x i64> @llvm.vp.add.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> splat (i1 true), i32 %evl)1105 ret <4 x i64> %v1106}1107 1108define <4 x i64> @vadd_vi_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {1109; CHECK-LABEL: vadd_vi_v4i64:1110; CHECK: # %bb.0:1111; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma1112; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t1113; CHECK-NEXT: ret1114 %v = call <4 x i64> @llvm.vp.add.v4i64(<4 x i64> %va, <4 x i64> splat (i64 -1), <4 x i1> %m, i32 %evl)1115 ret <4 x i64> %v1116}1117 1118define <4 x i64> @vadd_vi_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {1119; CHECK-LABEL: vadd_vi_v4i64_unmasked:1120; CHECK: # %bb.0:1121; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma1122; CHECK-NEXT: vadd.vi v8, v8, -11123; CHECK-NEXT: ret1124 %v = call <4 x i64> @llvm.vp.add.v4i64(<4 x i64> %va, <4 x i64> splat (i64 -1), <4 x i1> splat (i1 true), i32 %evl)1125 ret <4 x i64> %v1126}1127 1128define <8 x i64> @vadd_vv_v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 zeroext %evl) {1129; CHECK-LABEL: vadd_vv_v8i64:1130; CHECK: # %bb.0:1131; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma1132; CHECK-NEXT: vadd.vv v8, v8, v12, v0.t1133; CHECK-NEXT: ret1134 %v = call <8 x i64> @llvm.vp.add.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 %evl)1135 ret <8 x i64> %v1136}1137 1138define <8 x i64> @vadd_vv_v8i64_unmasked(<8 x i64> %va, <8 x i64> %b, i32 zeroext %evl) {1139; CHECK-LABEL: vadd_vv_v8i64_unmasked:1140; CHECK: # %bb.0:1141; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma1142; CHECK-NEXT: vadd.vv v8, v8, v121143; CHECK-NEXT: ret1144 %v = call <8 x i64> @llvm.vp.add.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> splat (i1 true), i32 %evl)1145 ret <8 x i64> %v1146}1147 1148define <8 x i64> @vadd_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {1149; RV32-LABEL: vadd_vx_v8i64:1150; RV32: # %bb.0:1151; RV32-NEXT: addi sp, sp, -161152; RV32-NEXT: .cfi_def_cfa_offset 161153; RV32-NEXT: sw a0, 8(sp)1154; RV32-NEXT: sw a1, 12(sp)1155; RV32-NEXT: addi a0, sp, 81156; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma1157; RV32-NEXT: vlse64.v v12, (a0), zero1158; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma1159; RV32-NEXT: vadd.vv v8, v8, v12, v0.t1160; RV32-NEXT: addi sp, sp, 161161; RV32-NEXT: .cfi_def_cfa_offset 01162; RV32-NEXT: ret1163;1164; RV64-LABEL: vadd_vx_v8i64:1165; RV64: # %bb.0:1166; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma1167; RV64-NEXT: vadd.vx v8, v8, a0, v0.t1168; RV64-NEXT: ret1169 %elt.head = insertelement <8 x i64> poison, i64 %b, i32 01170 %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer1171 %v = call <8 x i64> @llvm.vp.add.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl)1172 ret <8 x i64> %v1173}1174 1175define <8 x i64> @vadd_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl) {1176; RV32-LABEL: vadd_vx_v8i64_unmasked:1177; RV32: # %bb.0:1178; RV32-NEXT: addi sp, sp, -161179; RV32-NEXT: .cfi_def_cfa_offset 161180; RV32-NEXT: sw a0, 8(sp)1181; RV32-NEXT: sw a1, 12(sp)1182; RV32-NEXT: addi a0, sp, 81183; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma1184; RV32-NEXT: vlse64.v v12, (a0), zero1185; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma1186; RV32-NEXT: vadd.vv v8, v8, v121187; RV32-NEXT: addi sp, sp, 161188; RV32-NEXT: .cfi_def_cfa_offset 01189; RV32-NEXT: ret1190;1191; RV64-LABEL: vadd_vx_v8i64_unmasked:1192; RV64: # %bb.0:1193; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma1194; RV64-NEXT: vadd.vx v8, v8, a01195; RV64-NEXT: ret1196 %elt.head = insertelement <8 x i64> poison, i64 %b, i32 01197 %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer1198 %v = call <8 x i64> @llvm.vp.add.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> splat (i1 true), i32 %evl)1199 ret <8 x i64> %v1200}1201 1202define <8 x i64> @vadd_vi_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {1203; CHECK-LABEL: vadd_vi_v8i64:1204; CHECK: # %bb.0:1205; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma1206; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t1207; CHECK-NEXT: ret1208 %v = call <8 x i64> @llvm.vp.add.v8i64(<8 x i64> %va, <8 x i64> splat (i64 -1), <8 x i1> %m, i32 %evl)1209 ret <8 x i64> %v1210}1211 1212define <8 x i64> @vadd_vi_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {1213; CHECK-LABEL: vadd_vi_v8i64_unmasked:1214; CHECK: # %bb.0:1215; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma1216; CHECK-NEXT: vadd.vi v8, v8, -11217; CHECK-NEXT: ret1218 %v = call <8 x i64> @llvm.vp.add.v8i64(<8 x i64> %va, <8 x i64> splat (i64 -1), <8 x i1> splat (i1 true), i32 %evl)1219 ret <8 x i64> %v1220}1221 1222define <16 x i64> @vadd_vv_v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 zeroext %evl) {1223; CHECK-LABEL: vadd_vv_v16i64:1224; CHECK: # %bb.0:1225; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1226; CHECK-NEXT: vadd.vv v8, v8, v16, v0.t1227; CHECK-NEXT: ret1228 %v = call <16 x i64> @llvm.vp.add.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 %evl)1229 ret <16 x i64> %v1230}1231 1232define <16 x i64> @vadd_vv_v16i64_unmasked(<16 x i64> %va, <16 x i64> %b, i32 zeroext %evl) {1233; CHECK-LABEL: vadd_vv_v16i64_unmasked:1234; CHECK: # %bb.0:1235; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1236; CHECK-NEXT: vadd.vv v8, v8, v161237; CHECK-NEXT: ret1238 %v = call <16 x i64> @llvm.vp.add.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> splat (i1 true), i32 %evl)1239 ret <16 x i64> %v1240}1241 1242define <16 x i64> @vadd_vx_v16i64(<16 x i64> %va, i64 %b, <16 x i1> %m, i32 zeroext %evl) {1243; RV32-LABEL: vadd_vx_v16i64:1244; RV32: # %bb.0:1245; RV32-NEXT: addi sp, sp, -161246; RV32-NEXT: .cfi_def_cfa_offset 161247; RV32-NEXT: sw a0, 8(sp)1248; RV32-NEXT: sw a1, 12(sp)1249; RV32-NEXT: addi a0, sp, 81250; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma1251; RV32-NEXT: vlse64.v v16, (a0), zero1252; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma1253; RV32-NEXT: vadd.vv v8, v8, v16, v0.t1254; RV32-NEXT: addi sp, sp, 161255; RV32-NEXT: .cfi_def_cfa_offset 01256; RV32-NEXT: ret1257;1258; RV64-LABEL: vadd_vx_v16i64:1259; RV64: # %bb.0:1260; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma1261; RV64-NEXT: vadd.vx v8, v8, a0, v0.t1262; RV64-NEXT: ret1263 %elt.head = insertelement <16 x i64> poison, i64 %b, i32 01264 %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer1265 %v = call <16 x i64> @llvm.vp.add.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl)1266 ret <16 x i64> %v1267}1268 1269define <16 x i64> @vadd_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext %evl) {1270; RV32-LABEL: vadd_vx_v16i64_unmasked:1271; RV32: # %bb.0:1272; RV32-NEXT: addi sp, sp, -161273; RV32-NEXT: .cfi_def_cfa_offset 161274; RV32-NEXT: sw a0, 8(sp)1275; RV32-NEXT: sw a1, 12(sp)1276; RV32-NEXT: addi a0, sp, 81277; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma1278; RV32-NEXT: vlse64.v v16, (a0), zero1279; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma1280; RV32-NEXT: vadd.vv v8, v8, v161281; RV32-NEXT: addi sp, sp, 161282; RV32-NEXT: .cfi_def_cfa_offset 01283; RV32-NEXT: ret1284;1285; RV64-LABEL: vadd_vx_v16i64_unmasked:1286; RV64: # %bb.0:1287; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma1288; RV64-NEXT: vadd.vx v8, v8, a01289; RV64-NEXT: ret1290 %elt.head = insertelement <16 x i64> poison, i64 %b, i32 01291 %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer1292 %v = call <16 x i64> @llvm.vp.add.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> splat (i1 true), i32 %evl)1293 ret <16 x i64> %v1294}1295 1296define <16 x i64> @vadd_vi_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) {1297; CHECK-LABEL: vadd_vi_v16i64:1298; CHECK: # %bb.0:1299; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1300; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t1301; CHECK-NEXT: ret1302 %v = call <16 x i64> @llvm.vp.add.v16i64(<16 x i64> %va, <16 x i64> splat (i64 -1), <16 x i1> %m, i32 %evl)1303 ret <16 x i64> %v1304}1305 1306define <16 x i64> @vadd_vi_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {1307; CHECK-LABEL: vadd_vi_v16i64_unmasked:1308; CHECK: # %bb.0:1309; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1310; CHECK-NEXT: vadd.vi v8, v8, -11311; CHECK-NEXT: ret1312 %v = call <16 x i64> @llvm.vp.add.v16i64(<16 x i64> %va, <16 x i64> splat (i64 -1), <16 x i1> splat (i1 true), i32 %evl)1313 ret <16 x i64> %v1314}1315 1316; Test that split-legalization works as expected.1317 1318define <32 x i64> @vadd_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) {1319; CHECK-LABEL: vadd_vx_v32i64:1320; CHECK: # %bb.0:1321; CHECK-NEXT: li a2, 161322; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma1323; CHECK-NEXT: vslidedown.vi v24, v0, 21324; CHECK-NEXT: mv a1, a01325; CHECK-NEXT: bltu a0, a2, .LBB108_21326; CHECK-NEXT: # %bb.1:1327; CHECK-NEXT: li a1, 161328; CHECK-NEXT: .LBB108_2:1329; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma1330; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t1331; CHECK-NEXT: addi a1, a0, -161332; CHECK-NEXT: sltu a0, a0, a11333; CHECK-NEXT: addi a0, a0, -11334; CHECK-NEXT: and a0, a0, a11335; CHECK-NEXT: vmv1r.v v0, v241336; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1337; CHECK-NEXT: vadd.vi v16, v16, -1, v0.t1338; CHECK-NEXT: ret1339 %v = call <32 x i64> @llvm.vp.add.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 %evl)1340 ret <32 x i64> %v1341}1342 1343define <32 x i64> @vadd_vi_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {1344; CHECK-LABEL: vadd_vi_v32i64_unmasked:1345; CHECK: # %bb.0:1346; CHECK-NEXT: li a2, 161347; CHECK-NEXT: mv a1, a01348; CHECK-NEXT: bltu a0, a2, .LBB109_21349; CHECK-NEXT: # %bb.1:1350; CHECK-NEXT: li a1, 161351; CHECK-NEXT: .LBB109_2:1352; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma1353; CHECK-NEXT: vadd.vi v8, v8, -11354; CHECK-NEXT: addi a1, a0, -161355; CHECK-NEXT: sltu a0, a0, a11356; CHECK-NEXT: addi a0, a0, -11357; CHECK-NEXT: and a0, a0, a11358; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1359; CHECK-NEXT: vadd.vi v16, v16, -11360; CHECK-NEXT: ret1361 %v = call <32 x i64> @llvm.vp.add.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> splat (i1 true), i32 %evl)1362 ret <32 x i64> %v1363}1364 1365define <32 x i64> @vadd_vx_v32i64_evl12(<32 x i64> %va, <32 x i1> %m) {1366; CHECK-LABEL: vadd_vx_v32i64_evl12:1367; CHECK: # %bb.0:1368; CHECK-NEXT: vsetivli zero, 12, e64, m8, ta, ma1369; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t1370; CHECK-NEXT: ret1371 %v = call <32 x i64> @llvm.vp.add.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 12)1372 ret <32 x i64> %v1373}1374 1375define <32 x i64> @vadd_vx_v32i64_evl27(<32 x i64> %va, <32 x i1> %m) {1376; CHECK-LABEL: vadd_vx_v32i64_evl27:1377; CHECK: # %bb.0:1378; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma1379; CHECK-NEXT: vslidedown.vi v24, v0, 21380; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma1381; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t1382; CHECK-NEXT: vmv1r.v v0, v241383; CHECK-NEXT: vsetivli zero, 11, e64, m8, ta, ma1384; CHECK-NEXT: vadd.vi v16, v16, -1, v0.t1385; CHECK-NEXT: ret1386 %v = call <32 x i64> @llvm.vp.add.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 27)1387 ret <32 x i64> %v1388}1389 1390define <2 x i64> @vadd_vx_v2i64_to_sub(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) nounwind {1391; RV32-LABEL: vadd_vx_v2i64_to_sub:1392; RV32: # %bb.0:1393; RV32-NEXT: addi sp, sp, -161394; RV32-NEXT: li a1, -2561395; RV32-NEXT: li a2, 11396; RV32-NEXT: sw a2, 8(sp)1397; RV32-NEXT: sw a1, 12(sp)1398; RV32-NEXT: addi a1, sp, 81399; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma1400; RV32-NEXT: vlse64.v v9, (a1), zero1401; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma1402; RV32-NEXT: vadd.vv v8, v9, v8, v0.t1403; RV32-NEXT: addi sp, sp, 161404; RV32-NEXT: ret1405;1406; RV64-LABEL: vadd_vx_v2i64_to_sub:1407; RV64: # %bb.0:1408; RV64-NEXT: li a1, -11409; RV64-NEXT: srli a1, a1, 241410; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma1411; RV64-NEXT: vsub.vx v8, v8, a1, v0.t1412; RV64-NEXT: ret1413 %v = call <2 x i64> @llvm.vp.add.v2i64(<2 x i64> splat (i64 -1099511627775), <2 x i64> %va, <2 x i1> %m, i32 %evl)1414 ret <2 x i64> %v1415}1416 1417define <2 x i64> @vadd_vx_v2i64_to_sub_swapped(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) nounwind {1418; RV32-LABEL: vadd_vx_v2i64_to_sub_swapped:1419; RV32: # %bb.0:1420; RV32-NEXT: addi sp, sp, -161421; RV32-NEXT: li a1, -2561422; RV32-NEXT: li a2, 11423; RV32-NEXT: sw a2, 8(sp)1424; RV32-NEXT: sw a1, 12(sp)1425; RV32-NEXT: addi a1, sp, 81426; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma1427; RV32-NEXT: vlse64.v v9, (a1), zero1428; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma1429; RV32-NEXT: vadd.vv v8, v8, v9, v0.t1430; RV32-NEXT: addi sp, sp, 161431; RV32-NEXT: ret1432;1433; RV64-LABEL: vadd_vx_v2i64_to_sub_swapped:1434; RV64: # %bb.0:1435; RV64-NEXT: li a1, -11436; RV64-NEXT: srli a1, a1, 241437; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma1438; RV64-NEXT: vsub.vx v8, v8, a1, v0.t1439; RV64-NEXT: ret1440 %v = call <2 x i64> @llvm.vp.add.v2i64(<2 x i64> %va, <2 x i64> splat (i64 -1099511627775), <2 x i1> %m, i32 %evl)1441 ret <2 x i64> %v1442}1443