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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s4; RUN: llc -mtriple=riscv32 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB5; RUN: llc -mtriple=riscv64 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB6 7define <8 x i8> @not_signbit_mask_v8i8(<8 x i8> %a, <8 x i8> %b) {8; CHECK-LABEL: not_signbit_mask_v8i8:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma11; CHECK-NEXT: vmsgt.vi v0, v8, -112; CHECK-NEXT: vmv.v.i v8, 013; CHECK-NEXT: vmerge.vvm v8, v8, v9, v014; CHECK-NEXT: ret15;16; CHECK-ZVKB-LABEL: not_signbit_mask_v8i8:17; CHECK-ZVKB: # %bb.0:18; CHECK-ZVKB-NEXT: vsetivli zero, 8, e8, mf2, ta, ma19; CHECK-ZVKB-NEXT: vsra.vi v8, v8, 720; CHECK-ZVKB-NEXT: vandn.vv v8, v9, v821; CHECK-ZVKB-NEXT: ret22 %cond = icmp sgt <8 x i8> %a, splat (i8 -1)23 %r = select <8 x i1> %cond, <8 x i8> %b, <8 x i8> zeroinitializer24 ret <8 x i8> %r25}26 27define <4 x i16> @not_signbit_mask_v4i16(<4 x i16> %a, <4 x i16> %b) {28; CHECK-LABEL: not_signbit_mask_v4i16:29; CHECK: # %bb.0:30; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma31; CHECK-NEXT: vmsgt.vi v0, v8, -132; CHECK-NEXT: vmv.v.i v8, 033; CHECK-NEXT: vmerge.vvm v8, v8, v9, v034; CHECK-NEXT: ret35;36; CHECK-ZVKB-LABEL: not_signbit_mask_v4i16:37; CHECK-ZVKB: # %bb.0:38; CHECK-ZVKB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma39; CHECK-ZVKB-NEXT: vsra.vi v8, v8, 1540; CHECK-ZVKB-NEXT: vandn.vv v8, v9, v841; CHECK-ZVKB-NEXT: ret42 %cond = icmp sgt <4 x i16> %a, splat (i16 -1)43 %r = select <4 x i1> %cond, <4 x i16> %b, <4 x i16> zeroinitializer44 ret <4 x i16> %r45}46 47define <2 x i32> @not_signbit_mask_v2i32(<2 x i32> %a, <2 x i32> %b) {48; CHECK-LABEL: not_signbit_mask_v2i32:49; CHECK: # %bb.0:50; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma51; CHECK-NEXT: vmsgt.vi v0, v8, -152; CHECK-NEXT: vmv.v.i v8, 053; CHECK-NEXT: vmerge.vvm v8, v8, v9, v054; CHECK-NEXT: ret55;56; CHECK-ZVKB-LABEL: not_signbit_mask_v2i32:57; CHECK-ZVKB: # %bb.0:58; CHECK-ZVKB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma59; CHECK-ZVKB-NEXT: vsra.vi v8, v8, 3160; CHECK-ZVKB-NEXT: vandn.vv v8, v9, v861; CHECK-ZVKB-NEXT: ret62 %cond = icmp sgt <2 x i32> %a, splat (i32 -1)63 %r = select <2 x i1> %cond, <2 x i32> %b, <2 x i32> zeroinitializer64 ret <2 x i32> %r65}66 67define <2 x i64> @not_signbit_mask_v2i64(<2 x i64> %a, <2 x i64> %b) {68; CHECK-LABEL: not_signbit_mask_v2i64:69; CHECK: # %bb.0:70; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma71; CHECK-NEXT: vmsgt.vi v0, v8, -172; CHECK-NEXT: vmv.v.i v8, 073; CHECK-NEXT: vmerge.vvm v8, v8, v9, v074; CHECK-NEXT: ret75;76; CHECK-ZVKB-LABEL: not_signbit_mask_v2i64:77; CHECK-ZVKB: # %bb.0:78; CHECK-ZVKB-NEXT: li a0, 6379; CHECK-ZVKB-NEXT: vsetivli zero, 2, e64, m1, ta, ma80; CHECK-ZVKB-NEXT: vsra.vx v8, v8, a081; CHECK-ZVKB-NEXT: vandn.vv v8, v9, v882; CHECK-ZVKB-NEXT: ret83 %cond = icmp sgt <2 x i64> %a, splat (i64 -1)84 %r = select <2 x i1> %cond, <2 x i64> %b, <2 x i64> zeroinitializer85 ret <2 x i64> %r86}87