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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zvfh,+zvfbfmin,+v -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,ZVFH %s4; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zvfh,+zvfbfmin,+v -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,ZVFH %s6; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zvfh,+experimental-zvfbfa,+v -target-abi=ilp32d \7; RUN: -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,ZVFBFA %s8; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zvfh,+experimental-zvfbfa,+v -target-abi=lp64d \9; RUN: -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,ZVFBFA %s10 11define <2 x bfloat> @vfsgnj_vv_v2bf16(<2 x bfloat> %va, <2 x bfloat> %vb, <2 x i1> %m, i32 zeroext %evl) {12; ZVFH-LABEL: vfsgnj_vv_v2bf16:13; ZVFH: # %bb.0:14; ZVFH-NEXT: lui a1, 815; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma16; ZVFH-NEXT: vand.vx v9, v9, a1, v0.t17; ZVFH-NEXT: addi a1, a1, -118; ZVFH-NEXT: vand.vx v8, v8, a1, v0.t19; ZVFH-NEXT: vor.vv v8, v8, v9, v0.t20; ZVFH-NEXT: ret21;22; ZVFBFA-LABEL: vfsgnj_vv_v2bf16:23; ZVFBFA: # %bb.0:24; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, mf4, ta, ma25; ZVFBFA-NEXT: vfsgnj.vv v8, v8, v9, v0.t26; ZVFBFA-NEXT: ret27 %v = call <2 x bfloat> @llvm.vp.copysign.v2bf16(<2 x bfloat> %va, <2 x bfloat> %vb, <2 x i1> %m, i32 %evl)28 ret <2 x bfloat> %v29}30 31define <2 x bfloat> @vfsgnj_vv_v2bf16_unmasked(<2 x bfloat> %va, <2 x bfloat> %vb, i32 zeroext %evl) {32; ZVFH-LABEL: vfsgnj_vv_v2bf16_unmasked:33; ZVFH: # %bb.0:34; ZVFH-NEXT: lui a1, 835; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma36; ZVFH-NEXT: vand.vx v9, v9, a137; ZVFH-NEXT: addi a1, a1, -138; ZVFH-NEXT: vand.vx v8, v8, a139; ZVFH-NEXT: vor.vv v8, v8, v940; ZVFH-NEXT: ret41;42; ZVFBFA-LABEL: vfsgnj_vv_v2bf16_unmasked:43; ZVFBFA: # %bb.0:44; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, mf4, ta, ma45; ZVFBFA-NEXT: vfsgnj.vv v8, v8, v946; ZVFBFA-NEXT: ret47 %v = call <2 x bfloat> @llvm.vp.copysign.v2bf16(<2 x bfloat> %va, <2 x bfloat> %vb, <2 x i1> splat (i1 true), i32 %evl)48 ret <2 x bfloat> %v49}50 51define <4 x bfloat> @vfsgnj_vv_v4bf16(<4 x bfloat> %va, <4 x bfloat> %vb, <4 x i1> %m, i32 zeroext %evl) {52; ZVFH-LABEL: vfsgnj_vv_v4bf16:53; ZVFH: # %bb.0:54; ZVFH-NEXT: lui a1, 855; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma56; ZVFH-NEXT: vand.vx v9, v9, a1, v0.t57; ZVFH-NEXT: addi a1, a1, -158; ZVFH-NEXT: vand.vx v8, v8, a1, v0.t59; ZVFH-NEXT: vor.vv v8, v8, v9, v0.t60; ZVFH-NEXT: ret61;62; ZVFBFA-LABEL: vfsgnj_vv_v4bf16:63; ZVFBFA: # %bb.0:64; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, mf2, ta, ma65; ZVFBFA-NEXT: vfsgnj.vv v8, v8, v9, v0.t66; ZVFBFA-NEXT: ret67 %v = call <4 x bfloat> @llvm.vp.copysign.v4bf16(<4 x bfloat> %va, <4 x bfloat> %vb, <4 x i1> %m, i32 %evl)68 ret <4 x bfloat> %v69}70 71define <4 x bfloat> @vfsgnj_vv_v4bf16_unmasked(<4 x bfloat> %va, <4 x bfloat> %vb, i32 zeroext %evl) {72; ZVFH-LABEL: vfsgnj_vv_v4bf16_unmasked:73; ZVFH: # %bb.0:74; ZVFH-NEXT: lui a1, 875; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma76; ZVFH-NEXT: vand.vx v9, v9, a177; ZVFH-NEXT: addi a1, a1, -178; ZVFH-NEXT: vand.vx v8, v8, a179; ZVFH-NEXT: vor.vv v8, v8, v980; ZVFH-NEXT: ret81;82; ZVFBFA-LABEL: vfsgnj_vv_v4bf16_unmasked:83; ZVFBFA: # %bb.0:84; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, mf2, ta, ma85; ZVFBFA-NEXT: vfsgnj.vv v8, v8, v986; ZVFBFA-NEXT: ret87 %v = call <4 x bfloat> @llvm.vp.copysign.v4bf16(<4 x bfloat> %va, <4 x bfloat> %vb, <4 x i1> splat (i1 true), i32 %evl)88 ret <4 x bfloat> %v89}90 91define <8 x bfloat> @vfsgnj_vv_v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, <8 x i1> %m, i32 zeroext %evl) {92; ZVFH-LABEL: vfsgnj_vv_v8bf16:93; ZVFH: # %bb.0:94; ZVFH-NEXT: lui a1, 895; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma96; ZVFH-NEXT: vand.vx v9, v9, a1, v0.t97; ZVFH-NEXT: addi a1, a1, -198; ZVFH-NEXT: vand.vx v8, v8, a1, v0.t99; ZVFH-NEXT: vor.vv v8, v8, v9, v0.t100; ZVFH-NEXT: ret101;102; ZVFBFA-LABEL: vfsgnj_vv_v8bf16:103; ZVFBFA: # %bb.0:104; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m1, ta, ma105; ZVFBFA-NEXT: vfsgnj.vv v8, v8, v9, v0.t106; ZVFBFA-NEXT: ret107 %v = call <8 x bfloat> @llvm.vp.copysign.v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, <8 x i1> %m, i32 %evl)108 ret <8 x bfloat> %v109}110 111define <8 x bfloat> @vfsgnj_vv_v8bf16_unmasked(<8 x bfloat> %va, <8 x bfloat> %vb, i32 zeroext %evl) {112; ZVFH-LABEL: vfsgnj_vv_v8bf16_unmasked:113; ZVFH: # %bb.0:114; ZVFH-NEXT: lui a1, 8115; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma116; ZVFH-NEXT: vand.vx v9, v9, a1117; ZVFH-NEXT: addi a1, a1, -1118; ZVFH-NEXT: vand.vx v8, v8, a1119; ZVFH-NEXT: vor.vv v8, v8, v9120; ZVFH-NEXT: ret121;122; ZVFBFA-LABEL: vfsgnj_vv_v8bf16_unmasked:123; ZVFBFA: # %bb.0:124; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m1, ta, ma125; ZVFBFA-NEXT: vfsgnj.vv v8, v8, v9126; ZVFBFA-NEXT: ret127 %v = call <8 x bfloat> @llvm.vp.copysign.v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, <8 x i1> splat (i1 true), i32 %evl)128 ret <8 x bfloat> %v129}130 131define <16 x bfloat> @vfsgnj_vv_v16bf16(<16 x bfloat> %va, <16 x bfloat> %vb, <16 x i1> %m, i32 zeroext %evl) {132; ZVFH-LABEL: vfsgnj_vv_v16bf16:133; ZVFH: # %bb.0:134; ZVFH-NEXT: lui a1, 8135; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma136; ZVFH-NEXT: vand.vx v10, v10, a1, v0.t137; ZVFH-NEXT: addi a1, a1, -1138; ZVFH-NEXT: vand.vx v8, v8, a1, v0.t139; ZVFH-NEXT: vor.vv v8, v8, v10, v0.t140; ZVFH-NEXT: ret141;142; ZVFBFA-LABEL: vfsgnj_vv_v16bf16:143; ZVFBFA: # %bb.0:144; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m2, ta, ma145; ZVFBFA-NEXT: vfsgnj.vv v8, v8, v10, v0.t146; ZVFBFA-NEXT: ret147 %v = call <16 x bfloat> @llvm.vp.copysign.v16bf16(<16 x bfloat> %va, <16 x bfloat> %vb, <16 x i1> %m, i32 %evl)148 ret <16 x bfloat> %v149}150 151define <16 x bfloat> @vfsgnj_vv_v16bf16_unmasked(<16 x bfloat> %va, <16 x bfloat> %vb, i32 zeroext %evl) {152; ZVFH-LABEL: vfsgnj_vv_v16bf16_unmasked:153; ZVFH: # %bb.0:154; ZVFH-NEXT: lui a1, 8155; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma156; ZVFH-NEXT: vand.vx v10, v10, a1157; ZVFH-NEXT: addi a1, a1, -1158; ZVFH-NEXT: vand.vx v8, v8, a1159; ZVFH-NEXT: vor.vv v8, v8, v10160; ZVFH-NEXT: ret161;162; ZVFBFA-LABEL: vfsgnj_vv_v16bf16_unmasked:163; ZVFBFA: # %bb.0:164; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m2, ta, ma165; ZVFBFA-NEXT: vfsgnj.vv v8, v8, v10166; ZVFBFA-NEXT: ret167 %v = call <16 x bfloat> @llvm.vp.copysign.v16bf16(<16 x bfloat> %va, <16 x bfloat> %vb, <16 x i1> splat (i1 true), i32 %evl)168 ret <16 x bfloat> %v169}170 171define <2 x half> @vfsgnj_vv_v2f16(<2 x half> %va, <2 x half> %vb, <2 x i1> %m, i32 zeroext %evl) {172; CHECK-LABEL: vfsgnj_vv_v2f16:173; CHECK: # %bb.0:174; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma175; CHECK-NEXT: vfsgnj.vv v8, v8, v9, v0.t176; CHECK-NEXT: ret177 %v = call <2 x half> @llvm.vp.copysign.v2f16(<2 x half> %va, <2 x half> %vb, <2 x i1> %m, i32 %evl)178 ret <2 x half> %v179}180 181define <2 x half> @vfsgnj_vv_v2f16_unmasked(<2 x half> %va, <2 x half> %vb, i32 zeroext %evl) {182; CHECK-LABEL: vfsgnj_vv_v2f16_unmasked:183; CHECK: # %bb.0:184; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma185; CHECK-NEXT: vfsgnj.vv v8, v8, v9186; CHECK-NEXT: ret187 %v = call <2 x half> @llvm.vp.copysign.v2f16(<2 x half> %va, <2 x half> %vb, <2 x i1> splat (i1 true), i32 %evl)188 ret <2 x half> %v189}190 191define <4 x half> @vfsgnj_vv_v4f16(<4 x half> %va, <4 x half> %vb, <4 x i1> %m, i32 zeroext %evl) {192; CHECK-LABEL: vfsgnj_vv_v4f16:193; CHECK: # %bb.0:194; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma195; CHECK-NEXT: vfsgnj.vv v8, v8, v9, v0.t196; CHECK-NEXT: ret197 %v = call <4 x half> @llvm.vp.copysign.v4f16(<4 x half> %va, <4 x half> %vb, <4 x i1> %m, i32 %evl)198 ret <4 x half> %v199}200 201define <4 x half> @vfsgnj_vv_v4f16_unmasked(<4 x half> %va, <4 x half> %vb, i32 zeroext %evl) {202; CHECK-LABEL: vfsgnj_vv_v4f16_unmasked:203; CHECK: # %bb.0:204; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma205; CHECK-NEXT: vfsgnj.vv v8, v8, v9206; CHECK-NEXT: ret207 %v = call <4 x half> @llvm.vp.copysign.v4f16(<4 x half> %va, <4 x half> %vb, <4 x i1> splat (i1 true), i32 %evl)208 ret <4 x half> %v209}210 211define <8 x half> @vfsgnj_vv_v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> %m, i32 zeroext %evl) {212; CHECK-LABEL: vfsgnj_vv_v8f16:213; CHECK: # %bb.0:214; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma215; CHECK-NEXT: vfsgnj.vv v8, v8, v9, v0.t216; CHECK-NEXT: ret217 %v = call <8 x half> @llvm.vp.copysign.v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> %m, i32 %evl)218 ret <8 x half> %v219}220 221define <8 x half> @vfsgnj_vv_v8f16_unmasked(<8 x half> %va, <8 x half> %vb, i32 zeroext %evl) {222; CHECK-LABEL: vfsgnj_vv_v8f16_unmasked:223; CHECK: # %bb.0:224; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma225; CHECK-NEXT: vfsgnj.vv v8, v8, v9226; CHECK-NEXT: ret227 %v = call <8 x half> @llvm.vp.copysign.v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> splat (i1 true), i32 %evl)228 ret <8 x half> %v229}230 231define <16 x half> @vfsgnj_vv_v16f16(<16 x half> %va, <16 x half> %vb, <16 x i1> %m, i32 zeroext %evl) {232; CHECK-LABEL: vfsgnj_vv_v16f16:233; CHECK: # %bb.0:234; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma235; CHECK-NEXT: vfsgnj.vv v8, v8, v10, v0.t236; CHECK-NEXT: ret237 %v = call <16 x half> @llvm.vp.copysign.v16f16(<16 x half> %va, <16 x half> %vb, <16 x i1> %m, i32 %evl)238 ret <16 x half> %v239}240 241define <16 x half> @vfsgnj_vv_v16f16_unmasked(<16 x half> %va, <16 x half> %vb, i32 zeroext %evl) {242; CHECK-LABEL: vfsgnj_vv_v16f16_unmasked:243; CHECK: # %bb.0:244; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma245; CHECK-NEXT: vfsgnj.vv v8, v8, v10246; CHECK-NEXT: ret247 %v = call <16 x half> @llvm.vp.copysign.v16f16(<16 x half> %va, <16 x half> %vb, <16 x i1> splat (i1 true), i32 %evl)248 ret <16 x half> %v249}250 251define <2 x float> @vfsgnj_vv_v2f32(<2 x float> %va, <2 x float> %vb, <2 x i1> %m, i32 zeroext %evl) {252; CHECK-LABEL: vfsgnj_vv_v2f32:253; CHECK: # %bb.0:254; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma255; CHECK-NEXT: vfsgnj.vv v8, v8, v9, v0.t256; CHECK-NEXT: ret257 %v = call <2 x float> @llvm.vp.copysign.v2f32(<2 x float> %va, <2 x float> %vb, <2 x i1> %m, i32 %evl)258 ret <2 x float> %v259}260 261define <2 x float> @vfsgnj_vv_v2f32_unmasked(<2 x float> %va, <2 x float> %vb, i32 zeroext %evl) {262; CHECK-LABEL: vfsgnj_vv_v2f32_unmasked:263; CHECK: # %bb.0:264; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma265; CHECK-NEXT: vfsgnj.vv v8, v8, v9266; CHECK-NEXT: ret267 %v = call <2 x float> @llvm.vp.copysign.v2f32(<2 x float> %va, <2 x float> %vb, <2 x i1> splat (i1 true), i32 %evl)268 ret <2 x float> %v269}270 271define <4 x float> @vfsgnj_vv_v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> %m, i32 zeroext %evl) {272; CHECK-LABEL: vfsgnj_vv_v4f32:273; CHECK: # %bb.0:274; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma275; CHECK-NEXT: vfsgnj.vv v8, v8, v9, v0.t276; CHECK-NEXT: ret277 %v = call <4 x float> @llvm.vp.copysign.v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> %m, i32 %evl)278 ret <4 x float> %v279}280 281define <4 x float> @vfsgnj_vv_v4f32_unmasked(<4 x float> %va, <4 x float> %vb, i32 zeroext %evl) {282; CHECK-LABEL: vfsgnj_vv_v4f32_unmasked:283; CHECK: # %bb.0:284; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma285; CHECK-NEXT: vfsgnj.vv v8, v8, v9286; CHECK-NEXT: ret287 %v = call <4 x float> @llvm.vp.copysign.v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> splat (i1 true), i32 %evl)288 ret <4 x float> %v289}290 291define <8 x float> @vfsgnj_vv_v8f32(<8 x float> %va, <8 x float> %vb, <8 x i1> %m, i32 zeroext %evl) {292; CHECK-LABEL: vfsgnj_vv_v8f32:293; CHECK: # %bb.0:294; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma295; CHECK-NEXT: vfsgnj.vv v8, v8, v10, v0.t296; CHECK-NEXT: ret297 %v = call <8 x float> @llvm.vp.copysign.v8f32(<8 x float> %va, <8 x float> %vb, <8 x i1> %m, i32 %evl)298 ret <8 x float> %v299}300 301define <8 x float> @vfsgnj_vv_v8f32_unmasked(<8 x float> %va, <8 x float> %vb, i32 zeroext %evl) {302; CHECK-LABEL: vfsgnj_vv_v8f32_unmasked:303; CHECK: # %bb.0:304; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma305; CHECK-NEXT: vfsgnj.vv v8, v8, v10306; CHECK-NEXT: ret307 %v = call <8 x float> @llvm.vp.copysign.v8f32(<8 x float> %va, <8 x float> %vb, <8 x i1> splat (i1 true), i32 %evl)308 ret <8 x float> %v309}310 311define <16 x float> @vfsgnj_vv_v16f32(<16 x float> %va, <16 x float> %vb, <16 x i1> %m, i32 zeroext %evl) {312; CHECK-LABEL: vfsgnj_vv_v16f32:313; CHECK: # %bb.0:314; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma315; CHECK-NEXT: vfsgnj.vv v8, v8, v12, v0.t316; CHECK-NEXT: ret317 %v = call <16 x float> @llvm.vp.copysign.v16f32(<16 x float> %va, <16 x float> %vb, <16 x i1> %m, i32 %evl)318 ret <16 x float> %v319}320 321define <16 x float> @vfsgnj_vv_v16f32_unmasked(<16 x float> %va, <16 x float> %vb, i32 zeroext %evl) {322; CHECK-LABEL: vfsgnj_vv_v16f32_unmasked:323; CHECK: # %bb.0:324; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma325; CHECK-NEXT: vfsgnj.vv v8, v8, v12326; CHECK-NEXT: ret327 %v = call <16 x float> @llvm.vp.copysign.v16f32(<16 x float> %va, <16 x float> %vb, <16 x i1> splat (i1 true), i32 %evl)328 ret <16 x float> %v329}330 331define <2 x double> @vfsgnj_vv_v2f64(<2 x double> %va, <2 x double> %vb, <2 x i1> %m, i32 zeroext %evl) {332; CHECK-LABEL: vfsgnj_vv_v2f64:333; CHECK: # %bb.0:334; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma335; CHECK-NEXT: vfsgnj.vv v8, v8, v9, v0.t336; CHECK-NEXT: ret337 %v = call <2 x double> @llvm.vp.copysign.v2f64(<2 x double> %va, <2 x double> %vb, <2 x i1> %m, i32 %evl)338 ret <2 x double> %v339}340 341define <2 x double> @vfsgnj_vv_v2f64_unmasked(<2 x double> %va, <2 x double> %vb, i32 zeroext %evl) {342; CHECK-LABEL: vfsgnj_vv_v2f64_unmasked:343; CHECK: # %bb.0:344; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma345; CHECK-NEXT: vfsgnj.vv v8, v8, v9346; CHECK-NEXT: ret347 %v = call <2 x double> @llvm.vp.copysign.v2f64(<2 x double> %va, <2 x double> %vb, <2 x i1> splat (i1 true), i32 %evl)348 ret <2 x double> %v349}350 351define <4 x double> @vfsgnj_vv_v4f64(<4 x double> %va, <4 x double> %vb, <4 x i1> %m, i32 zeroext %evl) {352; CHECK-LABEL: vfsgnj_vv_v4f64:353; CHECK: # %bb.0:354; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma355; CHECK-NEXT: vfsgnj.vv v8, v8, v10, v0.t356; CHECK-NEXT: ret357 %v = call <4 x double> @llvm.vp.copysign.v4f64(<4 x double> %va, <4 x double> %vb, <4 x i1> %m, i32 %evl)358 ret <4 x double> %v359}360 361define <4 x double> @vfsgnj_vv_v4f64_unmasked(<4 x double> %va, <4 x double> %vb, i32 zeroext %evl) {362; CHECK-LABEL: vfsgnj_vv_v4f64_unmasked:363; CHECK: # %bb.0:364; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma365; CHECK-NEXT: vfsgnj.vv v8, v8, v10366; CHECK-NEXT: ret367 %v = call <4 x double> @llvm.vp.copysign.v4f64(<4 x double> %va, <4 x double> %vb, <4 x i1> splat (i1 true), i32 %evl)368 ret <4 x double> %v369}370 371define <8 x double> @vfsgnj_vv_v8f64(<8 x double> %va, <8 x double> %vb, <8 x i1> %m, i32 zeroext %evl) {372; CHECK-LABEL: vfsgnj_vv_v8f64:373; CHECK: # %bb.0:374; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma375; CHECK-NEXT: vfsgnj.vv v8, v8, v12, v0.t376; CHECK-NEXT: ret377 %v = call <8 x double> @llvm.vp.copysign.v8f64(<8 x double> %va, <8 x double> %vb, <8 x i1> %m, i32 %evl)378 ret <8 x double> %v379}380 381define <8 x double> @vfsgnj_vv_v8f64_unmasked(<8 x double> %va, <8 x double> %vb, i32 zeroext %evl) {382; CHECK-LABEL: vfsgnj_vv_v8f64_unmasked:383; CHECK: # %bb.0:384; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma385; CHECK-NEXT: vfsgnj.vv v8, v8, v12386; CHECK-NEXT: ret387 %v = call <8 x double> @llvm.vp.copysign.v8f64(<8 x double> %va, <8 x double> %vb, <8 x i1> splat (i1 true), i32 %evl)388 ret <8 x double> %v389}390 391define <15 x double> @vfsgnj_vv_v15f64(<15 x double> %va, <15 x double> %vb, <15 x i1> %m, i32 zeroext %evl) {392; CHECK-LABEL: vfsgnj_vv_v15f64:393; CHECK: # %bb.0:394; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma395; CHECK-NEXT: vfsgnj.vv v8, v8, v16, v0.t396; CHECK-NEXT: ret397 %v = call <15 x double> @llvm.vp.copysign.v15f64(<15 x double> %va, <15 x double> %vb, <15 x i1> %m, i32 %evl)398 ret <15 x double> %v399}400 401define <15 x double> @vfsgnj_vv_v15f64_unmasked(<15 x double> %va, <15 x double> %vb, i32 zeroext %evl) {402; CHECK-LABEL: vfsgnj_vv_v15f64_unmasked:403; CHECK: # %bb.0:404; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma405; CHECK-NEXT: vfsgnj.vv v8, v8, v16406; CHECK-NEXT: ret407 %v = call <15 x double> @llvm.vp.copysign.v15f64(<15 x double> %va, <15 x double> %vb, <15 x i1> splat (i1 true), i32 %evl)408 ret <15 x double> %v409}410 411define <16 x double> @vfsgnj_vv_v16f64(<16 x double> %va, <16 x double> %vb, <16 x i1> %m, i32 zeroext %evl) {412; CHECK-LABEL: vfsgnj_vv_v16f64:413; CHECK: # %bb.0:414; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma415; CHECK-NEXT: vfsgnj.vv v8, v8, v16, v0.t416; CHECK-NEXT: ret417 %v = call <16 x double> @llvm.vp.copysign.v16f64(<16 x double> %va, <16 x double> %vb, <16 x i1> %m, i32 %evl)418 ret <16 x double> %v419}420 421define <16 x double> @vfsgnj_vv_v16f64_unmasked(<16 x double> %va, <16 x double> %vb, i32 zeroext %evl) {422; CHECK-LABEL: vfsgnj_vv_v16f64_unmasked:423; CHECK: # %bb.0:424; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma425; CHECK-NEXT: vfsgnj.vv v8, v8, v16426; CHECK-NEXT: ret427 %v = call <16 x double> @llvm.vp.copysign.v16f64(<16 x double> %va, <16 x double> %vb, <16 x i1> splat (i1 true), i32 %evl)428 ret <16 x double> %v429}430 431define <32 x double> @vfsgnj_vv_v32f64(<32 x double> %va, <32 x double> %vb, <32 x i1> %m, i32 zeroext %evl) {432; CHECK-LABEL: vfsgnj_vv_v32f64:433; CHECK: # %bb.0:434; CHECK-NEXT: addi sp, sp, -16435; CHECK-NEXT: .cfi_def_cfa_offset 16436; CHECK-NEXT: csrr a1, vlenb437; CHECK-NEXT: slli a1, a1, 3438; CHECK-NEXT: sub sp, sp, a1439; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb440; CHECK-NEXT: addi a1, sp, 16441; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill442; CHECK-NEXT: addi a1, a0, 128443; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma444; CHECK-NEXT: vle64.v v16, (a1)445; CHECK-NEXT: vle64.v v24, (a0)446; CHECK-NEXT: li a1, 16447; CHECK-NEXT: mv a0, a2448; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma449; CHECK-NEXT: vslidedown.vi v7, v0, 2450; CHECK-NEXT: bltu a2, a1, .LBB34_2451; CHECK-NEXT: # %bb.1:452; CHECK-NEXT: li a0, 16453; CHECK-NEXT: .LBB34_2:454; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma455; CHECK-NEXT: vfsgnj.vv v8, v8, v24, v0.t456; CHECK-NEXT: addi a0, a2, -16457; CHECK-NEXT: sltu a1, a2, a0458; CHECK-NEXT: addi a1, a1, -1459; CHECK-NEXT: and a0, a1, a0460; CHECK-NEXT: vmv1r.v v0, v7461; CHECK-NEXT: addi a1, sp, 16462; CHECK-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload463; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma464; CHECK-NEXT: vfsgnj.vv v16, v24, v16, v0.t465; CHECK-NEXT: csrr a0, vlenb466; CHECK-NEXT: slli a0, a0, 3467; CHECK-NEXT: add sp, sp, a0468; CHECK-NEXT: .cfi_def_cfa sp, 16469; CHECK-NEXT: addi sp, sp, 16470; CHECK-NEXT: .cfi_def_cfa_offset 0471; CHECK-NEXT: ret472 %v = call <32 x double> @llvm.vp.copysign.v32f64(<32 x double> %va, <32 x double> %vb, <32 x i1> %m, i32 %evl)473 ret <32 x double> %v474}475 476define <32 x double> @vfsgnj_vv_v32f64_unmasked(<32 x double> %va, <32 x double> %vb, i32 zeroext %evl) {477; CHECK-LABEL: vfsgnj_vv_v32f64_unmasked:478; CHECK: # %bb.0:479; CHECK-NEXT: addi a1, a0, 128480; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma481; CHECK-NEXT: vle64.v v24, (a1)482; CHECK-NEXT: vle64.v v0, (a0)483; CHECK-NEXT: li a1, 16484; CHECK-NEXT: mv a0, a2485; CHECK-NEXT: bltu a2, a1, .LBB35_2486; CHECK-NEXT: # %bb.1:487; CHECK-NEXT: li a0, 16488; CHECK-NEXT: .LBB35_2:489; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma490; CHECK-NEXT: vfsgnj.vv v8, v8, v0491; CHECK-NEXT: addi a0, a2, -16492; CHECK-NEXT: sltu a1, a2, a0493; CHECK-NEXT: addi a1, a1, -1494; CHECK-NEXT: and a0, a1, a0495; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma496; CHECK-NEXT: vfsgnj.vv v16, v16, v24497; CHECK-NEXT: ret498 %v = call <32 x double> @llvm.vp.copysign.v32f64(<32 x double> %va, <32 x double> %vb, <32 x i1> splat (i1 true), i32 %evl)499 ret <32 x double> %v500}501