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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 62; RUN: llc -mtriple riscv32 -mattr=+v < %s | FileCheck %s3; RUN: llc -mtriple riscv64 -mattr=+v < %s | FileCheck %s4; RUN: llc -mtriple riscv32 -mattr=+v,+vl-dependent-latency < %s | FileCheck %s5; RUN: llc -mtriple riscv64 -mattr=+v,+vl-dependent-latency < %s | FileCheck %s6 7define <4 x i32> @splice_v4i32_slidedown(<4 x i32> %a, <4 x i32> %b) {8; CHECK-LABEL: splice_v4i32_slidedown:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma11; CHECK-NEXT: vrgather.vi v9, v8, 312; CHECK-NEXT: vmv.v.v v8, v913; CHECK-NEXT: ret14 %res = call <4 x i32> @llvm.vector.splice(<4 x i32> %a, <4 x i32> poison, i32 3)15 ret <4 x i32> %res16}17 18define <4 x i32> @splice_4i32_slideup(<4 x i32> %a) {19; CHECK-LABEL: splice_4i32_slideup:20; CHECK: # %bb.0:21; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma22; CHECK-NEXT: vrgather.vi v9, v8, 023; CHECK-NEXT: vmv.v.v v8, v924; CHECK-NEXT: ret25 %res = call <4 x i32> @llvm.vector.splice(<4 x i32> poison, <4 x i32> %a, i32 -3)26 ret <4 x i32> %res27}28 29define <8 x i32> @splice_v8i32_slidedown(<8 x i32> %a, <8 x i32> %b) {30; CHECK-LABEL: splice_v8i32_slidedown:31; CHECK: # %bb.0:32; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma33; CHECK-NEXT: vslidedown.vi v8, v8, 334; CHECK-NEXT: ret35 %res = call <8 x i32> @llvm.vector.splice(<8 x i32> %a, <8 x i32> poison, i32 3)36 ret <8 x i32> %res37}38 39define <8 x i32> @splice_v8i32_slideup(<8 x i32> %a) {40; CHECK-LABEL: splice_v8i32_slideup:41; CHECK: # %bb.0:42; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma43; CHECK-NEXT: vslideup.vi v10, v8, 344; CHECK-NEXT: vmv.v.v v8, v1045; CHECK-NEXT: ret46 %res = call <8 x i32> @llvm.vector.splice(<8 x i32> poison, <8 x i32> %a, i32 -3)47 ret <8 x i32> %res48}49 50define <4 x i32> @splice_v4i32_slidedown_undef(<4 x i32> %a, <4 x i32> %b) {51; CHECK-LABEL: splice_v4i32_slidedown_undef:52; CHECK: # %bb.0:53; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma54; CHECK-NEXT: vrgather.vi v9, v8, 355; CHECK-NEXT: vmv.v.v v8, v956; CHECK-NEXT: ret57 %res = call <4 x i32> @llvm.vector.splice(<4 x i32> %a, <4 x i32> undef, i32 3)58 ret <4 x i32> %res59}60 61define <4 x i32> @splice_4i32_slideup_undef(<4 x i32> %a) {62; CHECK-LABEL: splice_4i32_slideup_undef:63; CHECK: # %bb.0:64; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma65; CHECK-NEXT: vrgather.vi v9, v8, 066; CHECK-NEXT: vmv.v.v v8, v967; CHECK-NEXT: ret68 %res = call <4 x i32> @llvm.vector.splice(<4 x i32> undef, <4 x i32> %a, i32 -3)69 ret <4 x i32> %res70}71 72define <8 x i32> @splice_v8i32_slidedown_undef(<8 x i32> %a, <8 x i32> %b) {73; CHECK-LABEL: splice_v8i32_slidedown_undef:74; CHECK: # %bb.0:75; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma76; CHECK-NEXT: vslidedown.vi v8, v8, 377; CHECK-NEXT: ret78 %res = call <8 x i32> @llvm.vector.splice(<8 x i32> %a, <8 x i32> undef, i32 3)79 ret <8 x i32> %res80}81 82define <8 x i32> @splice_v8i32_slideup_undef(<8 x i32> %a) {83; CHECK-LABEL: splice_v8i32_slideup_undef:84; CHECK: # %bb.0:85; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma86; CHECK-NEXT: vslideup.vi v10, v8, 387; CHECK-NEXT: vmv.v.v v8, v1088; CHECK-NEXT: ret89 %res = call <8 x i32> @llvm.vector.splice(<8 x i32> undef, <8 x i32> %a, i32 -3)90 ret <8 x i32> %res91}92