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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zvfbfmin,+v -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH4; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zvfbfmin,+v -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH6; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+zvfbfmin,+v -target-abi=ilp32d \7; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN8; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+zvfbfmin,+v -target-abi=lp64d \9; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN10; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+experimental-zvfbfa,+v -target-abi=ilp32d \11; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFA12; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+experimental-zvfbfa,+v -target-abi=lp64d \13; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFA14 15define <2 x bfloat> @vfabs_vv_v2bf16(<2 x bfloat> %va, <2 x i1> %m, i32 zeroext %evl) {16; ZVFH-LABEL: vfabs_vv_v2bf16:17; ZVFH: # %bb.0:18; ZVFH-NEXT: lui a1, 819; ZVFH-NEXT: addi a1, a1, -120; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma21; ZVFH-NEXT: vand.vx v8, v8, a1, v0.t22; ZVFH-NEXT: ret23;24; ZVFHMIN-LABEL: vfabs_vv_v2bf16:25; ZVFHMIN: # %bb.0:26; ZVFHMIN-NEXT: lui a1, 827; ZVFHMIN-NEXT: addi a1, a1, -128; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma29; ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t30; ZVFHMIN-NEXT: ret31;32; ZVFBFA-LABEL: vfabs_vv_v2bf16:33; ZVFBFA: # %bb.0:34; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, mf4, ta, ma35; ZVFBFA-NEXT: vfabs.v v8, v8, v0.t36; ZVFBFA-NEXT: ret37 %v = call <2 x bfloat> @llvm.vp.fabs.v2bf16(<2 x bfloat> %va, <2 x i1> %m, i32 %evl)38 ret <2 x bfloat> %v39}40 41define <2 x bfloat> @vfabs_vv_v2bf16_unmasked(<2 x bfloat> %va, i32 zeroext %evl) {42; ZVFH-LABEL: vfabs_vv_v2bf16_unmasked:43; ZVFH: # %bb.0:44; ZVFH-NEXT: lui a1, 845; ZVFH-NEXT: addi a1, a1, -146; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma47; ZVFH-NEXT: vand.vx v8, v8, a148; ZVFH-NEXT: ret49;50; ZVFHMIN-LABEL: vfabs_vv_v2bf16_unmasked:51; ZVFHMIN: # %bb.0:52; ZVFHMIN-NEXT: lui a1, 853; ZVFHMIN-NEXT: addi a1, a1, -154; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma55; ZVFHMIN-NEXT: vand.vx v8, v8, a156; ZVFHMIN-NEXT: ret57;58; ZVFBFA-LABEL: vfabs_vv_v2bf16_unmasked:59; ZVFBFA: # %bb.0:60; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, mf4, ta, ma61; ZVFBFA-NEXT: vfabs.v v8, v862; ZVFBFA-NEXT: ret63 %v = call <2 x bfloat> @llvm.vp.fabs.v2bf16(<2 x bfloat> %va, <2 x i1> splat (i1 true), i32 %evl)64 ret <2 x bfloat> %v65}66 67define <4 x bfloat> @vfabs_vv_v4bf16(<4 x bfloat> %va, <4 x i1> %m, i32 zeroext %evl) {68; ZVFH-LABEL: vfabs_vv_v4bf16:69; ZVFH: # %bb.0:70; ZVFH-NEXT: lui a1, 871; ZVFH-NEXT: addi a1, a1, -172; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma73; ZVFH-NEXT: vand.vx v8, v8, a1, v0.t74; ZVFH-NEXT: ret75;76; ZVFHMIN-LABEL: vfabs_vv_v4bf16:77; ZVFHMIN: # %bb.0:78; ZVFHMIN-NEXT: lui a1, 879; ZVFHMIN-NEXT: addi a1, a1, -180; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma81; ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t82; ZVFHMIN-NEXT: ret83;84; ZVFBFA-LABEL: vfabs_vv_v4bf16:85; ZVFBFA: # %bb.0:86; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, mf2, ta, ma87; ZVFBFA-NEXT: vfabs.v v8, v8, v0.t88; ZVFBFA-NEXT: ret89 %v = call <4 x bfloat> @llvm.vp.fabs.v4bf16(<4 x bfloat> %va, <4 x i1> %m, i32 %evl)90 ret <4 x bfloat> %v91}92 93define <4 x bfloat> @vfabs_vv_v4bf16_unmasked(<4 x bfloat> %va, i32 zeroext %evl) {94; ZVFH-LABEL: vfabs_vv_v4bf16_unmasked:95; ZVFH: # %bb.0:96; ZVFH-NEXT: lui a1, 897; ZVFH-NEXT: addi a1, a1, -198; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma99; ZVFH-NEXT: vand.vx v8, v8, a1100; ZVFH-NEXT: ret101;102; ZVFHMIN-LABEL: vfabs_vv_v4bf16_unmasked:103; ZVFHMIN: # %bb.0:104; ZVFHMIN-NEXT: lui a1, 8105; ZVFHMIN-NEXT: addi a1, a1, -1106; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma107; ZVFHMIN-NEXT: vand.vx v8, v8, a1108; ZVFHMIN-NEXT: ret109;110; ZVFBFA-LABEL: vfabs_vv_v4bf16_unmasked:111; ZVFBFA: # %bb.0:112; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, mf2, ta, ma113; ZVFBFA-NEXT: vfabs.v v8, v8114; ZVFBFA-NEXT: ret115 %v = call <4 x bfloat> @llvm.vp.fabs.v4bf16(<4 x bfloat> %va, <4 x i1> splat (i1 true), i32 %evl)116 ret <4 x bfloat> %v117}118 119define <8 x bfloat> @vfabs_vv_v8bf16(<8 x bfloat> %va, <8 x i1> %m, i32 zeroext %evl) {120; ZVFH-LABEL: vfabs_vv_v8bf16:121; ZVFH: # %bb.0:122; ZVFH-NEXT: lui a1, 8123; ZVFH-NEXT: addi a1, a1, -1124; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma125; ZVFH-NEXT: vand.vx v8, v8, a1, v0.t126; ZVFH-NEXT: ret127;128; ZVFHMIN-LABEL: vfabs_vv_v8bf16:129; ZVFHMIN: # %bb.0:130; ZVFHMIN-NEXT: lui a1, 8131; ZVFHMIN-NEXT: addi a1, a1, -1132; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma133; ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t134; ZVFHMIN-NEXT: ret135;136; ZVFBFA-LABEL: vfabs_vv_v8bf16:137; ZVFBFA: # %bb.0:138; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m1, ta, ma139; ZVFBFA-NEXT: vfabs.v v8, v8, v0.t140; ZVFBFA-NEXT: ret141 %v = call <8 x bfloat> @llvm.vp.fabs.v8bf16(<8 x bfloat> %va, <8 x i1> %m, i32 %evl)142 ret <8 x bfloat> %v143}144 145define <8 x bfloat> @vfabs_vv_v8bf16_unmasked(<8 x bfloat> %va, i32 zeroext %evl) {146; ZVFH-LABEL: vfabs_vv_v8bf16_unmasked:147; ZVFH: # %bb.0:148; ZVFH-NEXT: lui a1, 8149; ZVFH-NEXT: addi a1, a1, -1150; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma151; ZVFH-NEXT: vand.vx v8, v8, a1152; ZVFH-NEXT: ret153;154; ZVFHMIN-LABEL: vfabs_vv_v8bf16_unmasked:155; ZVFHMIN: # %bb.0:156; ZVFHMIN-NEXT: lui a1, 8157; ZVFHMIN-NEXT: addi a1, a1, -1158; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma159; ZVFHMIN-NEXT: vand.vx v8, v8, a1160; ZVFHMIN-NEXT: ret161;162; ZVFBFA-LABEL: vfabs_vv_v8bf16_unmasked:163; ZVFBFA: # %bb.0:164; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m1, ta, ma165; ZVFBFA-NEXT: vfabs.v v8, v8166; ZVFBFA-NEXT: ret167 %v = call <8 x bfloat> @llvm.vp.fabs.v8bf16(<8 x bfloat> %va, <8 x i1> splat (i1 true), i32 %evl)168 ret <8 x bfloat> %v169}170 171define <16 x bfloat> @vfabs_vv_v16bf16(<16 x bfloat> %va, <16 x i1> %m, i32 zeroext %evl) {172; ZVFH-LABEL: vfabs_vv_v16bf16:173; ZVFH: # %bb.0:174; ZVFH-NEXT: lui a1, 8175; ZVFH-NEXT: addi a1, a1, -1176; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma177; ZVFH-NEXT: vand.vx v8, v8, a1, v0.t178; ZVFH-NEXT: ret179;180; ZVFHMIN-LABEL: vfabs_vv_v16bf16:181; ZVFHMIN: # %bb.0:182; ZVFHMIN-NEXT: lui a1, 8183; ZVFHMIN-NEXT: addi a1, a1, -1184; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma185; ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t186; ZVFHMIN-NEXT: ret187;188; ZVFBFA-LABEL: vfabs_vv_v16bf16:189; ZVFBFA: # %bb.0:190; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m2, ta, ma191; ZVFBFA-NEXT: vfabs.v v8, v8, v0.t192; ZVFBFA-NEXT: ret193 %v = call <16 x bfloat> @llvm.vp.fabs.v16bf16(<16 x bfloat> %va, <16 x i1> %m, i32 %evl)194 ret <16 x bfloat> %v195}196 197define <16 x bfloat> @vfabs_vv_v16bf16_unmasked(<16 x bfloat> %va, i32 zeroext %evl) {198; ZVFH-LABEL: vfabs_vv_v16bf16_unmasked:199; ZVFH: # %bb.0:200; ZVFH-NEXT: lui a1, 8201; ZVFH-NEXT: addi a1, a1, -1202; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma203; ZVFH-NEXT: vand.vx v8, v8, a1204; ZVFH-NEXT: ret205;206; ZVFHMIN-LABEL: vfabs_vv_v16bf16_unmasked:207; ZVFHMIN: # %bb.0:208; ZVFHMIN-NEXT: lui a1, 8209; ZVFHMIN-NEXT: addi a1, a1, -1210; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma211; ZVFHMIN-NEXT: vand.vx v8, v8, a1212; ZVFHMIN-NEXT: ret213;214; ZVFBFA-LABEL: vfabs_vv_v16bf16_unmasked:215; ZVFBFA: # %bb.0:216; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m2, ta, ma217; ZVFBFA-NEXT: vfabs.v v8, v8218; ZVFBFA-NEXT: ret219 %v = call <16 x bfloat> @llvm.vp.fabs.v16bf16(<16 x bfloat> %va, <16 x i1> splat (i1 true), i32 %evl)220 ret <16 x bfloat> %v221}222 223define <2 x half> @vfabs_vv_v2f16(<2 x half> %va, <2 x i1> %m, i32 zeroext %evl) {224; ZVFH-LABEL: vfabs_vv_v2f16:225; ZVFH: # %bb.0:226; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma227; ZVFH-NEXT: vfabs.v v8, v8, v0.t228; ZVFH-NEXT: ret229;230; ZVFHMIN-LABEL: vfabs_vv_v2f16:231; ZVFHMIN: # %bb.0:232; ZVFHMIN-NEXT: lui a1, 8233; ZVFHMIN-NEXT: addi a1, a1, -1234; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma235; ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t236; ZVFHMIN-NEXT: ret237;238; ZVFBFA-LABEL: vfabs_vv_v2f16:239; ZVFBFA: # %bb.0:240; ZVFBFA-NEXT: lui a1, 8241; ZVFBFA-NEXT: addi a1, a1, -1242; ZVFBFA-NEXT: vsetvli zero, a0, e16, mf4, ta, ma243; ZVFBFA-NEXT: vand.vx v8, v8, a1, v0.t244; ZVFBFA-NEXT: ret245 %v = call <2 x half> @llvm.vp.fabs.v2f16(<2 x half> %va, <2 x i1> %m, i32 %evl)246 ret <2 x half> %v247}248 249define <2 x half> @vfabs_vv_v2f16_unmasked(<2 x half> %va, i32 zeroext %evl) {250; ZVFH-LABEL: vfabs_vv_v2f16_unmasked:251; ZVFH: # %bb.0:252; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma253; ZVFH-NEXT: vfabs.v v8, v8254; ZVFH-NEXT: ret255;256; ZVFHMIN-LABEL: vfabs_vv_v2f16_unmasked:257; ZVFHMIN: # %bb.0:258; ZVFHMIN-NEXT: lui a1, 8259; ZVFHMIN-NEXT: addi a1, a1, -1260; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma261; ZVFHMIN-NEXT: vand.vx v8, v8, a1262; ZVFHMIN-NEXT: ret263;264; ZVFBFA-LABEL: vfabs_vv_v2f16_unmasked:265; ZVFBFA: # %bb.0:266; ZVFBFA-NEXT: lui a1, 8267; ZVFBFA-NEXT: addi a1, a1, -1268; ZVFBFA-NEXT: vsetvli zero, a0, e16, mf4, ta, ma269; ZVFBFA-NEXT: vand.vx v8, v8, a1270; ZVFBFA-NEXT: ret271 %v = call <2 x half> @llvm.vp.fabs.v2f16(<2 x half> %va, <2 x i1> splat (i1 true), i32 %evl)272 ret <2 x half> %v273}274 275define <4 x half> @vfabs_vv_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl) {276; ZVFH-LABEL: vfabs_vv_v4f16:277; ZVFH: # %bb.0:278; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma279; ZVFH-NEXT: vfabs.v v8, v8, v0.t280; ZVFH-NEXT: ret281;282; ZVFHMIN-LABEL: vfabs_vv_v4f16:283; ZVFHMIN: # %bb.0:284; ZVFHMIN-NEXT: lui a1, 8285; ZVFHMIN-NEXT: addi a1, a1, -1286; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma287; ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t288; ZVFHMIN-NEXT: ret289;290; ZVFBFA-LABEL: vfabs_vv_v4f16:291; ZVFBFA: # %bb.0:292; ZVFBFA-NEXT: lui a1, 8293; ZVFBFA-NEXT: addi a1, a1, -1294; ZVFBFA-NEXT: vsetvli zero, a0, e16, mf2, ta, ma295; ZVFBFA-NEXT: vand.vx v8, v8, a1, v0.t296; ZVFBFA-NEXT: ret297 %v = call <4 x half> @llvm.vp.fabs.v4f16(<4 x half> %va, <4 x i1> %m, i32 %evl)298 ret <4 x half> %v299}300 301define <4 x half> @vfabs_vv_v4f16_unmasked(<4 x half> %va, i32 zeroext %evl) {302; ZVFH-LABEL: vfabs_vv_v4f16_unmasked:303; ZVFH: # %bb.0:304; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma305; ZVFH-NEXT: vfabs.v v8, v8306; ZVFH-NEXT: ret307;308; ZVFHMIN-LABEL: vfabs_vv_v4f16_unmasked:309; ZVFHMIN: # %bb.0:310; ZVFHMIN-NEXT: lui a1, 8311; ZVFHMIN-NEXT: addi a1, a1, -1312; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma313; ZVFHMIN-NEXT: vand.vx v8, v8, a1314; ZVFHMIN-NEXT: ret315;316; ZVFBFA-LABEL: vfabs_vv_v4f16_unmasked:317; ZVFBFA: # %bb.0:318; ZVFBFA-NEXT: lui a1, 8319; ZVFBFA-NEXT: addi a1, a1, -1320; ZVFBFA-NEXT: vsetvli zero, a0, e16, mf2, ta, ma321; ZVFBFA-NEXT: vand.vx v8, v8, a1322; ZVFBFA-NEXT: ret323 %v = call <4 x half> @llvm.vp.fabs.v4f16(<4 x half> %va, <4 x i1> splat (i1 true), i32 %evl)324 ret <4 x half> %v325}326 327define <8 x half> @vfabs_vv_v8f16(<8 x half> %va, <8 x i1> %m, i32 zeroext %evl) {328; ZVFH-LABEL: vfabs_vv_v8f16:329; ZVFH: # %bb.0:330; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma331; ZVFH-NEXT: vfabs.v v8, v8, v0.t332; ZVFH-NEXT: ret333;334; ZVFHMIN-LABEL: vfabs_vv_v8f16:335; ZVFHMIN: # %bb.0:336; ZVFHMIN-NEXT: lui a1, 8337; ZVFHMIN-NEXT: addi a1, a1, -1338; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma339; ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t340; ZVFHMIN-NEXT: ret341;342; ZVFBFA-LABEL: vfabs_vv_v8f16:343; ZVFBFA: # %bb.0:344; ZVFBFA-NEXT: lui a1, 8345; ZVFBFA-NEXT: addi a1, a1, -1346; ZVFBFA-NEXT: vsetvli zero, a0, e16, m1, ta, ma347; ZVFBFA-NEXT: vand.vx v8, v8, a1, v0.t348; ZVFBFA-NEXT: ret349 %v = call <8 x half> @llvm.vp.fabs.v8f16(<8 x half> %va, <8 x i1> %m, i32 %evl)350 ret <8 x half> %v351}352 353define <8 x half> @vfabs_vv_v8f16_unmasked(<8 x half> %va, i32 zeroext %evl) {354; ZVFH-LABEL: vfabs_vv_v8f16_unmasked:355; ZVFH: # %bb.0:356; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma357; ZVFH-NEXT: vfabs.v v8, v8358; ZVFH-NEXT: ret359;360; ZVFHMIN-LABEL: vfabs_vv_v8f16_unmasked:361; ZVFHMIN: # %bb.0:362; ZVFHMIN-NEXT: lui a1, 8363; ZVFHMIN-NEXT: addi a1, a1, -1364; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma365; ZVFHMIN-NEXT: vand.vx v8, v8, a1366; ZVFHMIN-NEXT: ret367;368; ZVFBFA-LABEL: vfabs_vv_v8f16_unmasked:369; ZVFBFA: # %bb.0:370; ZVFBFA-NEXT: lui a1, 8371; ZVFBFA-NEXT: addi a1, a1, -1372; ZVFBFA-NEXT: vsetvli zero, a0, e16, m1, ta, ma373; ZVFBFA-NEXT: vand.vx v8, v8, a1374; ZVFBFA-NEXT: ret375 %v = call <8 x half> @llvm.vp.fabs.v8f16(<8 x half> %va, <8 x i1> splat (i1 true), i32 %evl)376 ret <8 x half> %v377}378 379define <16 x half> @vfabs_vv_v16f16(<16 x half> %va, <16 x i1> %m, i32 zeroext %evl) {380; ZVFH-LABEL: vfabs_vv_v16f16:381; ZVFH: # %bb.0:382; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma383; ZVFH-NEXT: vfabs.v v8, v8, v0.t384; ZVFH-NEXT: ret385;386; ZVFHMIN-LABEL: vfabs_vv_v16f16:387; ZVFHMIN: # %bb.0:388; ZVFHMIN-NEXT: lui a1, 8389; ZVFHMIN-NEXT: addi a1, a1, -1390; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma391; ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t392; ZVFHMIN-NEXT: ret393;394; ZVFBFA-LABEL: vfabs_vv_v16f16:395; ZVFBFA: # %bb.0:396; ZVFBFA-NEXT: lui a1, 8397; ZVFBFA-NEXT: addi a1, a1, -1398; ZVFBFA-NEXT: vsetvli zero, a0, e16, m2, ta, ma399; ZVFBFA-NEXT: vand.vx v8, v8, a1, v0.t400; ZVFBFA-NEXT: ret401 %v = call <16 x half> @llvm.vp.fabs.v16f16(<16 x half> %va, <16 x i1> %m, i32 %evl)402 ret <16 x half> %v403}404 405define <16 x half> @vfabs_vv_v16f16_unmasked(<16 x half> %va, i32 zeroext %evl) {406; ZVFH-LABEL: vfabs_vv_v16f16_unmasked:407; ZVFH: # %bb.0:408; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma409; ZVFH-NEXT: vfabs.v v8, v8410; ZVFH-NEXT: ret411;412; ZVFHMIN-LABEL: vfabs_vv_v16f16_unmasked:413; ZVFHMIN: # %bb.0:414; ZVFHMIN-NEXT: lui a1, 8415; ZVFHMIN-NEXT: addi a1, a1, -1416; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma417; ZVFHMIN-NEXT: vand.vx v8, v8, a1418; ZVFHMIN-NEXT: ret419;420; ZVFBFA-LABEL: vfabs_vv_v16f16_unmasked:421; ZVFBFA: # %bb.0:422; ZVFBFA-NEXT: lui a1, 8423; ZVFBFA-NEXT: addi a1, a1, -1424; ZVFBFA-NEXT: vsetvli zero, a0, e16, m2, ta, ma425; ZVFBFA-NEXT: vand.vx v8, v8, a1426; ZVFBFA-NEXT: ret427 %v = call <16 x half> @llvm.vp.fabs.v16f16(<16 x half> %va, <16 x i1> splat (i1 true), i32 %evl)428 ret <16 x half> %v429}430 431define <2 x float> @vfabs_vv_v2f32(<2 x float> %va, <2 x i1> %m, i32 zeroext %evl) {432; CHECK-LABEL: vfabs_vv_v2f32:433; CHECK: # %bb.0:434; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma435; CHECK-NEXT: vfabs.v v8, v8, v0.t436; CHECK-NEXT: ret437 %v = call <2 x float> @llvm.vp.fabs.v2f32(<2 x float> %va, <2 x i1> %m, i32 %evl)438 ret <2 x float> %v439}440 441define <2 x float> @vfabs_vv_v2f32_unmasked(<2 x float> %va, i32 zeroext %evl) {442; CHECK-LABEL: vfabs_vv_v2f32_unmasked:443; CHECK: # %bb.0:444; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma445; CHECK-NEXT: vfabs.v v8, v8446; CHECK-NEXT: ret447 %v = call <2 x float> @llvm.vp.fabs.v2f32(<2 x float> %va, <2 x i1> splat (i1 true), i32 %evl)448 ret <2 x float> %v449}450 451define <4 x float> @vfabs_vv_v4f32(<4 x float> %va, <4 x i1> %m, i32 zeroext %evl) {452; CHECK-LABEL: vfabs_vv_v4f32:453; CHECK: # %bb.0:454; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma455; CHECK-NEXT: vfabs.v v8, v8, v0.t456; CHECK-NEXT: ret457 %v = call <4 x float> @llvm.vp.fabs.v4f32(<4 x float> %va, <4 x i1> %m, i32 %evl)458 ret <4 x float> %v459}460 461define <4 x float> @vfabs_vv_v4f32_unmasked(<4 x float> %va, i32 zeroext %evl) {462; CHECK-LABEL: vfabs_vv_v4f32_unmasked:463; CHECK: # %bb.0:464; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma465; CHECK-NEXT: vfabs.v v8, v8466; CHECK-NEXT: ret467 %v = call <4 x float> @llvm.vp.fabs.v4f32(<4 x float> %va, <4 x i1> splat (i1 true), i32 %evl)468 ret <4 x float> %v469}470 471define <8 x float> @vfabs_vv_v8f32(<8 x float> %va, <8 x i1> %m, i32 zeroext %evl) {472; CHECK-LABEL: vfabs_vv_v8f32:473; CHECK: # %bb.0:474; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma475; CHECK-NEXT: vfabs.v v8, v8, v0.t476; CHECK-NEXT: ret477 %v = call <8 x float> @llvm.vp.fabs.v8f32(<8 x float> %va, <8 x i1> %m, i32 %evl)478 ret <8 x float> %v479}480 481define <8 x float> @vfabs_vv_v8f32_unmasked(<8 x float> %va, i32 zeroext %evl) {482; CHECK-LABEL: vfabs_vv_v8f32_unmasked:483; CHECK: # %bb.0:484; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma485; CHECK-NEXT: vfabs.v v8, v8486; CHECK-NEXT: ret487 %v = call <8 x float> @llvm.vp.fabs.v8f32(<8 x float> %va, <8 x i1> splat (i1 true), i32 %evl)488 ret <8 x float> %v489}490 491define <16 x float> @vfabs_vv_v16f32(<16 x float> %va, <16 x i1> %m, i32 zeroext %evl) {492; CHECK-LABEL: vfabs_vv_v16f32:493; CHECK: # %bb.0:494; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma495; CHECK-NEXT: vfabs.v v8, v8, v0.t496; CHECK-NEXT: ret497 %v = call <16 x float> @llvm.vp.fabs.v16f32(<16 x float> %va, <16 x i1> %m, i32 %evl)498 ret <16 x float> %v499}500 501define <16 x float> @vfabs_vv_v16f32_unmasked(<16 x float> %va, i32 zeroext %evl) {502; CHECK-LABEL: vfabs_vv_v16f32_unmasked:503; CHECK: # %bb.0:504; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma505; CHECK-NEXT: vfabs.v v8, v8506; CHECK-NEXT: ret507 %v = call <16 x float> @llvm.vp.fabs.v16f32(<16 x float> %va, <16 x i1> splat (i1 true), i32 %evl)508 ret <16 x float> %v509}510 511define <2 x double> @vfabs_vv_v2f64(<2 x double> %va, <2 x i1> %m, i32 zeroext %evl) {512; CHECK-LABEL: vfabs_vv_v2f64:513; CHECK: # %bb.0:514; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma515; CHECK-NEXT: vfabs.v v8, v8, v0.t516; CHECK-NEXT: ret517 %v = call <2 x double> @llvm.vp.fabs.v2f64(<2 x double> %va, <2 x i1> %m, i32 %evl)518 ret <2 x double> %v519}520 521define <2 x double> @vfabs_vv_v2f64_unmasked(<2 x double> %va, i32 zeroext %evl) {522; CHECK-LABEL: vfabs_vv_v2f64_unmasked:523; CHECK: # %bb.0:524; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma525; CHECK-NEXT: vfabs.v v8, v8526; CHECK-NEXT: ret527 %v = call <2 x double> @llvm.vp.fabs.v2f64(<2 x double> %va, <2 x i1> splat (i1 true), i32 %evl)528 ret <2 x double> %v529}530 531define <4 x double> @vfabs_vv_v4f64(<4 x double> %va, <4 x i1> %m, i32 zeroext %evl) {532; CHECK-LABEL: vfabs_vv_v4f64:533; CHECK: # %bb.0:534; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma535; CHECK-NEXT: vfabs.v v8, v8, v0.t536; CHECK-NEXT: ret537 %v = call <4 x double> @llvm.vp.fabs.v4f64(<4 x double> %va, <4 x i1> %m, i32 %evl)538 ret <4 x double> %v539}540 541define <4 x double> @vfabs_vv_v4f64_unmasked(<4 x double> %va, i32 zeroext %evl) {542; CHECK-LABEL: vfabs_vv_v4f64_unmasked:543; CHECK: # %bb.0:544; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma545; CHECK-NEXT: vfabs.v v8, v8546; CHECK-NEXT: ret547 %v = call <4 x double> @llvm.vp.fabs.v4f64(<4 x double> %va, <4 x i1> splat (i1 true), i32 %evl)548 ret <4 x double> %v549}550 551define <8 x double> @vfabs_vv_v8f64(<8 x double> %va, <8 x i1> %m, i32 zeroext %evl) {552; CHECK-LABEL: vfabs_vv_v8f64:553; CHECK: # %bb.0:554; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma555; CHECK-NEXT: vfabs.v v8, v8, v0.t556; CHECK-NEXT: ret557 %v = call <8 x double> @llvm.vp.fabs.v8f64(<8 x double> %va, <8 x i1> %m, i32 %evl)558 ret <8 x double> %v559}560 561define <8 x double> @vfabs_vv_v8f64_unmasked(<8 x double> %va, i32 zeroext %evl) {562; CHECK-LABEL: vfabs_vv_v8f64_unmasked:563; CHECK: # %bb.0:564; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma565; CHECK-NEXT: vfabs.v v8, v8566; CHECK-NEXT: ret567 %v = call <8 x double> @llvm.vp.fabs.v8f64(<8 x double> %va, <8 x i1> splat (i1 true), i32 %evl)568 ret <8 x double> %v569}570 571define <15 x double> @vfabs_vv_v15f64(<15 x double> %va, <15 x i1> %m, i32 zeroext %evl) {572; CHECK-LABEL: vfabs_vv_v15f64:573; CHECK: # %bb.0:574; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma575; CHECK-NEXT: vfabs.v v8, v8, v0.t576; CHECK-NEXT: ret577 %v = call <15 x double> @llvm.vp.fabs.v15f64(<15 x double> %va, <15 x i1> %m, i32 %evl)578 ret <15 x double> %v579}580 581define <15 x double> @vfabs_vv_v15f64_unmasked(<15 x double> %va, i32 zeroext %evl) {582; CHECK-LABEL: vfabs_vv_v15f64_unmasked:583; CHECK: # %bb.0:584; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma585; CHECK-NEXT: vfabs.v v8, v8586; CHECK-NEXT: ret587 %v = call <15 x double> @llvm.vp.fabs.v15f64(<15 x double> %va, <15 x i1> splat (i1 true), i32 %evl)588 ret <15 x double> %v589}590 591define <16 x double> @vfabs_vv_v16f64(<16 x double> %va, <16 x i1> %m, i32 zeroext %evl) {592; CHECK-LABEL: vfabs_vv_v16f64:593; CHECK: # %bb.0:594; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma595; CHECK-NEXT: vfabs.v v8, v8, v0.t596; CHECK-NEXT: ret597 %v = call <16 x double> @llvm.vp.fabs.v16f64(<16 x double> %va, <16 x i1> %m, i32 %evl)598 ret <16 x double> %v599}600 601define <16 x double> @vfabs_vv_v16f64_unmasked(<16 x double> %va, i32 zeroext %evl) {602; CHECK-LABEL: vfabs_vv_v16f64_unmasked:603; CHECK: # %bb.0:604; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma605; CHECK-NEXT: vfabs.v v8, v8606; CHECK-NEXT: ret607 %v = call <16 x double> @llvm.vp.fabs.v16f64(<16 x double> %va, <16 x i1> splat (i1 true), i32 %evl)608 ret <16 x double> %v609}610 611define <32 x double> @vfabs_vv_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroext %evl) {612; CHECK-LABEL: vfabs_vv_v32f64:613; CHECK: # %bb.0:614; CHECK-NEXT: li a2, 16615; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma616; CHECK-NEXT: vslidedown.vi v24, v0, 2617; CHECK-NEXT: mv a1, a0618; CHECK-NEXT: bltu a0, a2, .LBB34_2619; CHECK-NEXT: # %bb.1:620; CHECK-NEXT: li a1, 16621; CHECK-NEXT: .LBB34_2:622; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma623; CHECK-NEXT: vfabs.v v8, v8, v0.t624; CHECK-NEXT: addi a1, a0, -16625; CHECK-NEXT: sltu a0, a0, a1626; CHECK-NEXT: addi a0, a0, -1627; CHECK-NEXT: and a0, a0, a1628; CHECK-NEXT: vmv1r.v v0, v24629; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma630; CHECK-NEXT: vfabs.v v16, v16, v0.t631; CHECK-NEXT: ret632 %v = call <32 x double> @llvm.vp.fabs.v32f64(<32 x double> %va, <32 x i1> %m, i32 %evl)633 ret <32 x double> %v634}635 636define <32 x double> @vfabs_vv_v32f64_unmasked(<32 x double> %va, i32 zeroext %evl) {637; CHECK-LABEL: vfabs_vv_v32f64_unmasked:638; CHECK: # %bb.0:639; CHECK-NEXT: li a2, 16640; CHECK-NEXT: mv a1, a0641; CHECK-NEXT: bltu a0, a2, .LBB35_2642; CHECK-NEXT: # %bb.1:643; CHECK-NEXT: li a1, 16644; CHECK-NEXT: .LBB35_2:645; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma646; CHECK-NEXT: vfabs.v v8, v8647; CHECK-NEXT: addi a1, a0, -16648; CHECK-NEXT: sltu a0, a0, a1649; CHECK-NEXT: addi a0, a0, -1650; CHECK-NEXT: and a0, a0, a1651; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma652; CHECK-NEXT: vfabs.v v16, v16653; CHECK-NEXT: ret654 %v = call <32 x double> @llvm.vp.fabs.v32f64(<32 x double> %va, <32 x i1> splat (i1 true), i32 %evl)655 ret <32 x double> %v656}657