289 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s4; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck %s6 7define <2 x i1> @isnan_v2f16(<2 x half> %x, <2 x i1> %m, i32 zeroext %evl) {8; CHECK-LABEL: isnan_v2f16:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma11; CHECK-NEXT: vfclass.v v8, v8, v0.t12; CHECK-NEXT: li a0, 76813; CHECK-NEXT: vand.vx v8, v8, a0, v0.t14; CHECK-NEXT: vmsne.vi v0, v8, 0, v0.t15; CHECK-NEXT: ret16 %1 = call <2 x i1> @llvm.vp.is.fpclass.v2f16(<2 x half> %x, i32 3, <2 x i1> %m, i32 %evl) ; nan17 ret <2 x i1> %118}19 20define <2 x i1> @isnan_v2f16_unmasked(<2 x half> %x, i32 zeroext %evl) {21; CHECK-LABEL: isnan_v2f16_unmasked:22; CHECK: # %bb.0:23; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma24; CHECK-NEXT: vfclass.v v8, v825; CHECK-NEXT: li a0, 76826; CHECK-NEXT: vand.vx v8, v8, a027; CHECK-NEXT: vmsne.vi v0, v8, 028; CHECK-NEXT: ret29 %1 = call <2 x i1> @llvm.vp.is.fpclass.v2f16(<2 x half> %x, i32 3, <2 x i1> splat (i1 true), i32 %evl) ; nan30 ret <2 x i1> %131}32 33define <2 x i1> @isnan_v2f32(<2 x float> %x, <2 x i1> %m, i32 zeroext %evl) {34; CHECK-LABEL: isnan_v2f32:35; CHECK: # %bb.0:36; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma37; CHECK-NEXT: vfclass.v v8, v8, v0.t38; CHECK-NEXT: li a0, 92739; CHECK-NEXT: vand.vx v8, v8, a0, v0.t40; CHECK-NEXT: vmsne.vi v0, v8, 0, v0.t41; CHECK-NEXT: ret42 %1 = call <2 x i1> @llvm.vp.is.fpclass.v2f32(<2 x float> %x, i32 639, <2 x i1> %m, i32 %evl)43 ret <2 x i1> %144}45 46define <2 x i1> @isnan_v2f32_unmasked(<2 x float> %x, i32 zeroext %evl) {47; CHECK-LABEL: isnan_v2f32_unmasked:48; CHECK: # %bb.0:49; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma50; CHECK-NEXT: vfclass.v v8, v851; CHECK-NEXT: li a0, 92752; CHECK-NEXT: vand.vx v8, v8, a053; CHECK-NEXT: vmsne.vi v0, v8, 054; CHECK-NEXT: ret55 %1 = call <2 x i1> @llvm.vp.is.fpclass.v2f32(<2 x float> %x, i32 639, <2 x i1> splat (i1 true), i32 %evl)56 ret <2 x i1> %157}58 59define <4 x i1> @isnan_v4f32(<4 x float> %x, <4 x i1> %m, i32 zeroext %evl) {60; CHECK-LABEL: isnan_v4f32:61; CHECK: # %bb.0:62; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma63; CHECK-NEXT: vfclass.v v8, v8, v0.t64; CHECK-NEXT: li a0, 76865; CHECK-NEXT: vand.vx v8, v8, a0, v0.t66; CHECK-NEXT: vmsne.vi v0, v8, 0, v0.t67; CHECK-NEXT: ret68 %1 = call <4 x i1> @llvm.vp.is.fpclass.v4f32(<4 x float> %x, i32 3, <4 x i1> %m, i32 %evl) ; nan69 ret <4 x i1> %170}71 72define <4 x i1> @isnan_v4f32_unmasked(<4 x float> %x, i32 zeroext %evl) {73; CHECK-LABEL: isnan_v4f32_unmasked:74; CHECK: # %bb.0:75; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma76; CHECK-NEXT: vfclass.v v8, v877; CHECK-NEXT: li a0, 76878; CHECK-NEXT: vand.vx v8, v8, a079; CHECK-NEXT: vmsne.vi v0, v8, 080; CHECK-NEXT: ret81 %1 = call <4 x i1> @llvm.vp.is.fpclass.v4f32(<4 x float> %x, i32 3, <4 x i1> splat (i1 true), i32 %evl) ; nan82 ret <4 x i1> %183}84 85define <8 x i1> @isnan_v8f32(<8 x float> %x, <8 x i1> %m, i32 zeroext %evl) {86; CHECK-LABEL: isnan_v8f32:87; CHECK: # %bb.0:88; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma89; CHECK-NEXT: vfclass.v v10, v8, v0.t90; CHECK-NEXT: li a0, 51291; CHECK-NEXT: vmseq.vx v8, v10, a0, v0.t92; CHECK-NEXT: vmv1r.v v0, v893; CHECK-NEXT: ret94 %1 = call <8 x i1> @llvm.vp.is.fpclass.v8f32(<8 x float> %x, i32 2, <8 x i1> %m, i32 %evl)95 ret <8 x i1> %196}97 98define <8 x i1> @isnan_v8f32_unmasked(<8 x float> %x, i32 zeroext %evl) {99; CHECK-LABEL: isnan_v8f32_unmasked:100; CHECK: # %bb.0:101; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma102; CHECK-NEXT: vfclass.v v8, v8103; CHECK-NEXT: li a0, 512104; CHECK-NEXT: vmseq.vx v0, v8, a0105; CHECK-NEXT: ret106 %1 = call <8 x i1> @llvm.vp.is.fpclass.v8f32(<8 x float> %x, i32 2, <8 x i1> splat (i1 true), i32 %evl)107 ret <8 x i1> %1108}109 110define <16 x i1> @isnan_v16f32(<16 x float> %x, <16 x i1> %m, i32 zeroext %evl) {111; CHECK-LABEL: isnan_v16f32:112; CHECK: # %bb.0:113; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma114; CHECK-NEXT: vfclass.v v12, v8, v0.t115; CHECK-NEXT: li a0, 256116; CHECK-NEXT: vmseq.vx v8, v12, a0, v0.t117; CHECK-NEXT: vmv1r.v v0, v8118; CHECK-NEXT: ret119 %1 = call <16 x i1> @llvm.vp.is.fpclass.v16f32(<16 x float> %x, i32 1, <16 x i1> %m, i32 %evl)120 ret <16 x i1> %1121}122 123define <16 x i1> @isnan_v16f32_unmasked(<16 x float> %x, i32 zeroext %evl) {124; CHECK-LABEL: isnan_v16f32_unmasked:125; CHECK: # %bb.0:126; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma127; CHECK-NEXT: vfclass.v v8, v8128; CHECK-NEXT: li a0, 256129; CHECK-NEXT: vmseq.vx v0, v8, a0130; CHECK-NEXT: ret131 %1 = call <16 x i1> @llvm.vp.is.fpclass.v16f32(<16 x float> %x, i32 1, <16 x i1> splat (i1 true), i32 %evl)132 ret <16 x i1> %1133}134 135define <2 x i1> @isnormal_v2f64(<2 x double> %x, <2 x i1> %m, i32 zeroext %evl) {136; CHECK-LABEL: isnormal_v2f64:137; CHECK: # %bb.0:138; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma139; CHECK-NEXT: vfclass.v v8, v8, v0.t140; CHECK-NEXT: li a0, 129141; CHECK-NEXT: vand.vx v8, v8, a0, v0.t142; CHECK-NEXT: vmsne.vi v0, v8, 0, v0.t143; CHECK-NEXT: ret144 %1 = call <2 x i1> @llvm.vp.is.fpclass.v2f64(<2 x double> %x, i32 516, <2 x i1> %m, i32 %evl) ; 0x204 = "inf"145 ret <2 x i1> %1146}147 148define <2 x i1> @isnormal_v2f64_unmasked(<2 x double> %x, i32 zeroext %evl) {149; CHECK-LABEL: isnormal_v2f64_unmasked:150; CHECK: # %bb.0:151; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma152; CHECK-NEXT: vfclass.v v8, v8153; CHECK-NEXT: li a0, 129154; CHECK-NEXT: vand.vx v8, v8, a0155; CHECK-NEXT: vmsne.vi v0, v8, 0156; CHECK-NEXT: ret157 %1 = call <2 x i1> @llvm.vp.is.fpclass.v2f64(<2 x double> %x, i32 516, <2 x i1> splat (i1 true), i32 %evl) ; 0x204 = "inf"158 ret <2 x i1> %1159}160 161define <4 x i1> @isposinf_v4f64(<4 x double> %x, <4 x i1> %m, i32 zeroext %evl) {162; CHECK-LABEL: isposinf_v4f64:163; CHECK: # %bb.0:164; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma165; CHECK-NEXT: vfclass.v v10, v8, v0.t166; CHECK-NEXT: li a0, 128167; CHECK-NEXT: vmseq.vx v8, v10, a0, v0.t168; CHECK-NEXT: vmv1r.v v0, v8169; CHECK-NEXT: ret170 %1 = call <4 x i1> @llvm.vp.is.fpclass.v4f64(<4 x double> %x, i32 512, <4 x i1> %m, i32 %evl) ; 0x200 = "+inf"171 ret <4 x i1> %1172}173 174define <4 x i1> @isposinf_v4f64_unmasked(<4 x double> %x, i32 zeroext %evl) {175; CHECK-LABEL: isposinf_v4f64_unmasked:176; CHECK: # %bb.0:177; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma178; CHECK-NEXT: vfclass.v v8, v8179; CHECK-NEXT: li a0, 128180; CHECK-NEXT: vmseq.vx v0, v8, a0181; CHECK-NEXT: ret182 %1 = call <4 x i1> @llvm.vp.is.fpclass.v4f64(<4 x double> %x, i32 512, <4 x i1> splat (i1 true), i32 %evl) ; 0x200 = "+inf"183 ret <4 x i1> %1184}185 186define <8 x i1> @isneginf_v8f64(<8 x double> %x, <8 x i1> %m, i32 zeroext %evl) {187; CHECK-LABEL: isneginf_v8f64:188; CHECK: # %bb.0:189; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma190; CHECK-NEXT: vfclass.v v12, v8, v0.t191; CHECK-NEXT: vmseq.vi v8, v12, 1, v0.t192; CHECK-NEXT: vmv1r.v v0, v8193; CHECK-NEXT: ret194 %1 = call <8 x i1> @llvm.vp.is.fpclass.v8f64(<8 x double> %x, i32 4, <8 x i1> %m, i32 %evl) ; "-inf"195 ret <8 x i1> %1196}197 198define <8 x i1> @isneginf_v8f64_unmasked(<8 x double> %x, i32 zeroext %evl) {199; CHECK-LABEL: isneginf_v8f64_unmasked:200; CHECK: # %bb.0:201; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma202; CHECK-NEXT: vfclass.v v8, v8203; CHECK-NEXT: vmseq.vi v0, v8, 1204; CHECK-NEXT: ret205 %1 = call <8 x i1> @llvm.vp.is.fpclass.v8f64(<8 x double> %x, i32 4, <8 x i1> splat (i1 true), i32 %evl) ; "-inf"206 ret <8 x i1> %1207}208 209define <16 x i1> @isfinite_v16f64(<16 x double> %x, <16 x i1> %m, i32 zeroext %evl) {210; CHECK-LABEL: isfinite_v16f64:211; CHECK: # %bb.0:212; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma213; CHECK-NEXT: vfclass.v v8, v8, v0.t214; CHECK-NEXT: li a0, 126215; CHECK-NEXT: vand.vx v16, v8, a0, v0.t216; CHECK-NEXT: vmsne.vi v8, v16, 0, v0.t217; CHECK-NEXT: vmv1r.v v0, v8218; CHECK-NEXT: ret219 %1 = call <16 x i1> @llvm.vp.is.fpclass.v16f64(<16 x double> %x, i32 504, <16 x i1> %m, i32 %evl) ; 0x1f8 = "finite"220 ret <16 x i1> %1221}222 223define <16 x i1> @isfinite_v16f64_unmasked(<16 x double> %x, i32 zeroext %evl) {224; CHECK-LABEL: isfinite_v16f64_unmasked:225; CHECK: # %bb.0:226; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma227; CHECK-NEXT: vfclass.v v8, v8228; CHECK-NEXT: li a0, 126229; CHECK-NEXT: vand.vx v8, v8, a0230; CHECK-NEXT: vmsne.vi v0, v8, 0231; CHECK-NEXT: ret232 %1 = call <16 x i1> @llvm.vp.is.fpclass.v16f64(<16 x double> %x, i32 504, <16 x i1> splat (i1 true), i32 %evl) ; 0x1f8 = "finite"233 ret <16 x i1> %1234}235 236define <16 x i1> @isposfinite_v16f64(<16 x double> %x, <16 x i1> %m, i32 zeroext %evl) {237; CHECK-LABEL: isposfinite_v16f64:238; CHECK: # %bb.0:239; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma240; CHECK-NEXT: vfclass.v v8, v8, v0.t241; CHECK-NEXT: li a0, 112242; CHECK-NEXT: vand.vx v16, v8, a0, v0.t243; CHECK-NEXT: vmsne.vi v8, v16, 0, v0.t244; CHECK-NEXT: vmv1r.v v0, v8245; CHECK-NEXT: ret246 %1 = call <16 x i1> @llvm.vp.is.fpclass.v16f64(<16 x double> %x, i32 448, <16 x i1> %m, i32 %evl) ; 0x1c0 = "+finite"247 ret <16 x i1> %1248}249 250define <16 x i1> @isnegfinite_v16f64_unmasked(<16 x double> %x, i32 zeroext %evl) {251; CHECK-LABEL: isnegfinite_v16f64_unmasked:252; CHECK: # %bb.0:253; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma254; CHECK-NEXT: vfclass.v v8, v8255; CHECK-NEXT: vand.vi v8, v8, 14256; CHECK-NEXT: vmsne.vi v0, v8, 0257; CHECK-NEXT: ret258 %1 = call <16 x i1> @llvm.vp.is.fpclass.v16f64(<16 x double> %x, i32 56, <16 x i1> splat (i1 true), i32 %evl) ; 0x38 = "-finite"259 ret <16 x i1> %1260}261 262define <16 x i1> @isnotfinite_v16f64(<16 x double> %x, <16 x i1> %m, i32 zeroext %evl) {263; CHECK-LABEL: isnotfinite_v16f64:264; CHECK: # %bb.0:265; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma266; CHECK-NEXT: vfclass.v v8, v8, v0.t267; CHECK-NEXT: li a0, 897268; CHECK-NEXT: vand.vx v16, v8, a0, v0.t269; CHECK-NEXT: vmsne.vi v8, v16, 0, v0.t270; CHECK-NEXT: vmv1r.v v0, v8271; CHECK-NEXT: ret272 %1 = call <16 x i1> @llvm.vp.is.fpclass.v16f64(<16 x double> %x, i32 519, <16 x i1> %m, i32 %evl) ; 0x207 = "inf|nan"273 ret <16 x i1> %1274}275 276define <16 x i1> @isnotfinite_v16f64_unmasked(<16 x double> %x, i32 zeroext %evl) {277; CHECK-LABEL: isnotfinite_v16f64_unmasked:278; CHECK: # %bb.0:279; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma280; CHECK-NEXT: vfclass.v v8, v8281; CHECK-NEXT: li a0, 897282; CHECK-NEXT: vand.vx v8, v8, a0283; CHECK-NEXT: vmsne.vi v0, v8, 0284; CHECK-NEXT: ret285 %1 = call <16 x i1> @llvm.vp.is.fpclass.v16f64(<16 x double> %x, i32 519, <16 x i1> splat (i1 true), i32 %evl) ; 0x207 = "inf|nan"286 ret <16 x i1> %1287}288 289