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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH4; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH6; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+v -target-abi=ilp32d \7; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN8; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+v -target-abi=lp64d \9; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN10 11define <2 x half> @vfmin_vv_v2f16(<2 x half> %va, <2 x half> %vb, <2 x i1> %m, i32 zeroext %evl) {12; ZVFH-LABEL: vfmin_vv_v2f16:13; ZVFH: # %bb.0:14; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma15; ZVFH-NEXT: vfmin.vv v8, v8, v9, v0.t16; ZVFH-NEXT: ret17;18; ZVFHMIN-LABEL: vfmin_vv_v2f16:19; ZVFHMIN: # %bb.0:20; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma21; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9, v0.t22; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t23; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma24; ZVFHMIN-NEXT: vfmin.vv v9, v9, v10, v0.t25; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma26; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t27; ZVFHMIN-NEXT: ret28 %v = call <2 x half> @llvm.vp.minnum.v2f16(<2 x half> %va, <2 x half> %vb, <2 x i1> %m, i32 %evl)29 ret <2 x half> %v30}31 32define <2 x half> @vfmin_vv_v2f16_unmasked(<2 x half> %va, <2 x half> %vb, i32 zeroext %evl) {33; ZVFH-LABEL: vfmin_vv_v2f16_unmasked:34; ZVFH: # %bb.0:35; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma36; ZVFH-NEXT: vfmin.vv v8, v8, v937; ZVFH-NEXT: ret38;39; ZVFHMIN-LABEL: vfmin_vv_v2f16_unmasked:40; ZVFHMIN: # %bb.0:41; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma42; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v943; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v844; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma45; ZVFHMIN-NEXT: vfmin.vv v9, v9, v1046; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma47; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v948; ZVFHMIN-NEXT: ret49 %v = call <2 x half> @llvm.vp.minnum.v2f16(<2 x half> %va, <2 x half> %vb, <2 x i1> splat (i1 true), i32 %evl)50 ret <2 x half> %v51}52 53define <4 x half> @vfmin_vv_v4f16(<4 x half> %va, <4 x half> %vb, <4 x i1> %m, i32 zeroext %evl) {54; ZVFH-LABEL: vfmin_vv_v4f16:55; ZVFH: # %bb.0:56; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma57; ZVFH-NEXT: vfmin.vv v8, v8, v9, v0.t58; ZVFH-NEXT: ret59;60; ZVFHMIN-LABEL: vfmin_vv_v4f16:61; ZVFHMIN: # %bb.0:62; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma63; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9, v0.t64; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t65; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma66; ZVFHMIN-NEXT: vfmin.vv v9, v9, v10, v0.t67; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma68; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t69; ZVFHMIN-NEXT: ret70 %v = call <4 x half> @llvm.vp.minnum.v4f16(<4 x half> %va, <4 x half> %vb, <4 x i1> %m, i32 %evl)71 ret <4 x half> %v72}73 74define <4 x half> @vfmin_vv_v4f16_unmasked(<4 x half> %va, <4 x half> %vb, i32 zeroext %evl) {75; ZVFH-LABEL: vfmin_vv_v4f16_unmasked:76; ZVFH: # %bb.0:77; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma78; ZVFH-NEXT: vfmin.vv v8, v8, v979; ZVFH-NEXT: ret80;81; ZVFHMIN-LABEL: vfmin_vv_v4f16_unmasked:82; ZVFHMIN: # %bb.0:83; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma84; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v985; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v886; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma87; ZVFHMIN-NEXT: vfmin.vv v9, v9, v1088; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma89; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v990; ZVFHMIN-NEXT: ret91 %v = call <4 x half> @llvm.vp.minnum.v4f16(<4 x half> %va, <4 x half> %vb, <4 x i1> splat (i1 true), i32 %evl)92 ret <4 x half> %v93}94 95define <8 x half> @vfmin_vv_v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> %m, i32 zeroext %evl) {96; ZVFH-LABEL: vfmin_vv_v8f16:97; ZVFH: # %bb.0:98; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma99; ZVFH-NEXT: vfmin.vv v8, v8, v9, v0.t100; ZVFH-NEXT: ret101;102; ZVFHMIN-LABEL: vfmin_vv_v8f16:103; ZVFHMIN: # %bb.0:104; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma105; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9, v0.t106; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8, v0.t107; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma108; ZVFHMIN-NEXT: vfmin.vv v10, v12, v10, v0.t109; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma110; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t111; ZVFHMIN-NEXT: ret112 %v = call <8 x half> @llvm.vp.minnum.v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> %m, i32 %evl)113 ret <8 x half> %v114}115 116define <8 x half> @vfmin_vv_v8f16_unmasked(<8 x half> %va, <8 x half> %vb, i32 zeroext %evl) {117; ZVFH-LABEL: vfmin_vv_v8f16_unmasked:118; ZVFH: # %bb.0:119; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma120; ZVFH-NEXT: vfmin.vv v8, v8, v9121; ZVFH-NEXT: ret122;123; ZVFHMIN-LABEL: vfmin_vv_v8f16_unmasked:124; ZVFHMIN: # %bb.0:125; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma126; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9127; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8128; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma129; ZVFHMIN-NEXT: vfmin.vv v10, v12, v10130; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma131; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10132; ZVFHMIN-NEXT: ret133 %v = call <8 x half> @llvm.vp.minnum.v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> splat (i1 true), i32 %evl)134 ret <8 x half> %v135}136 137define <16 x half> @vfmin_vv_v16f16(<16 x half> %va, <16 x half> %vb, <16 x i1> %m, i32 zeroext %evl) {138; ZVFH-LABEL: vfmin_vv_v16f16:139; ZVFH: # %bb.0:140; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma141; ZVFH-NEXT: vfmin.vv v8, v8, v10, v0.t142; ZVFH-NEXT: ret143;144; ZVFHMIN-LABEL: vfmin_vv_v16f16:145; ZVFHMIN: # %bb.0:146; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma147; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10, v0.t148; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t149; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma150; ZVFHMIN-NEXT: vfmin.vv v12, v16, v12, v0.t151; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma152; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12, v0.t153; ZVFHMIN-NEXT: ret154 %v = call <16 x half> @llvm.vp.minnum.v16f16(<16 x half> %va, <16 x half> %vb, <16 x i1> %m, i32 %evl)155 ret <16 x half> %v156}157 158define <16 x half> @vfmin_vv_v16f16_unmasked(<16 x half> %va, <16 x half> %vb, i32 zeroext %evl) {159; ZVFH-LABEL: vfmin_vv_v16f16_unmasked:160; ZVFH: # %bb.0:161; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma162; ZVFH-NEXT: vfmin.vv v8, v8, v10163; ZVFH-NEXT: ret164;165; ZVFHMIN-LABEL: vfmin_vv_v16f16_unmasked:166; ZVFHMIN: # %bb.0:167; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma168; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10169; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8170; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma171; ZVFHMIN-NEXT: vfmin.vv v12, v16, v12172; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma173; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12174; ZVFHMIN-NEXT: ret175 %v = call <16 x half> @llvm.vp.minnum.v16f16(<16 x half> %va, <16 x half> %vb, <16 x i1> splat (i1 true), i32 %evl)176 ret <16 x half> %v177}178 179define <2 x float> @vfmin_vv_v2f32(<2 x float> %va, <2 x float> %vb, <2 x i1> %m, i32 zeroext %evl) {180; CHECK-LABEL: vfmin_vv_v2f32:181; CHECK: # %bb.0:182; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma183; CHECK-NEXT: vfmin.vv v8, v8, v9, v0.t184; CHECK-NEXT: ret185 %v = call <2 x float> @llvm.vp.minnum.v2f32(<2 x float> %va, <2 x float> %vb, <2 x i1> %m, i32 %evl)186 ret <2 x float> %v187}188 189define <2 x float> @vfmin_vv_v2f32_unmasked(<2 x float> %va, <2 x float> %vb, i32 zeroext %evl) {190; CHECK-LABEL: vfmin_vv_v2f32_unmasked:191; CHECK: # %bb.0:192; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma193; CHECK-NEXT: vfmin.vv v8, v8, v9194; CHECK-NEXT: ret195 %v = call <2 x float> @llvm.vp.minnum.v2f32(<2 x float> %va, <2 x float> %vb, <2 x i1> splat (i1 true), i32 %evl)196 ret <2 x float> %v197}198 199define <4 x float> @vfmin_vv_v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> %m, i32 zeroext %evl) {200; CHECK-LABEL: vfmin_vv_v4f32:201; CHECK: # %bb.0:202; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma203; CHECK-NEXT: vfmin.vv v8, v8, v9, v0.t204; CHECK-NEXT: ret205 %v = call <4 x float> @llvm.vp.minnum.v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> %m, i32 %evl)206 ret <4 x float> %v207}208 209define <4 x float> @vfmin_vv_v4f32_unmasked(<4 x float> %va, <4 x float> %vb, i32 zeroext %evl) {210; CHECK-LABEL: vfmin_vv_v4f32_unmasked:211; CHECK: # %bb.0:212; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma213; CHECK-NEXT: vfmin.vv v8, v8, v9214; CHECK-NEXT: ret215 %v = call <4 x float> @llvm.vp.minnum.v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> splat (i1 true), i32 %evl)216 ret <4 x float> %v217}218 219define <8 x float> @vfmin_vv_v8f32(<8 x float> %va, <8 x float> %vb, <8 x i1> %m, i32 zeroext %evl) {220; CHECK-LABEL: vfmin_vv_v8f32:221; CHECK: # %bb.0:222; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma223; CHECK-NEXT: vfmin.vv v8, v8, v10, v0.t224; CHECK-NEXT: ret225 %v = call <8 x float> @llvm.vp.minnum.v8f32(<8 x float> %va, <8 x float> %vb, <8 x i1> %m, i32 %evl)226 ret <8 x float> %v227}228 229define <8 x float> @vfmin_vv_v8f32_unmasked(<8 x float> %va, <8 x float> %vb, i32 zeroext %evl) {230; CHECK-LABEL: vfmin_vv_v8f32_unmasked:231; CHECK: # %bb.0:232; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma233; CHECK-NEXT: vfmin.vv v8, v8, v10234; CHECK-NEXT: ret235 %v = call <8 x float> @llvm.vp.minnum.v8f32(<8 x float> %va, <8 x float> %vb, <8 x i1> splat (i1 true), i32 %evl)236 ret <8 x float> %v237}238 239define <16 x float> @vfmin_vv_v16f32(<16 x float> %va, <16 x float> %vb, <16 x i1> %m, i32 zeroext %evl) {240; CHECK-LABEL: vfmin_vv_v16f32:241; CHECK: # %bb.0:242; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma243; CHECK-NEXT: vfmin.vv v8, v8, v12, v0.t244; CHECK-NEXT: ret245 %v = call <16 x float> @llvm.vp.minnum.v16f32(<16 x float> %va, <16 x float> %vb, <16 x i1> %m, i32 %evl)246 ret <16 x float> %v247}248 249define <16 x float> @vfmin_vv_v16f32_unmasked(<16 x float> %va, <16 x float> %vb, i32 zeroext %evl) {250; CHECK-LABEL: vfmin_vv_v16f32_unmasked:251; CHECK: # %bb.0:252; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma253; CHECK-NEXT: vfmin.vv v8, v8, v12254; CHECK-NEXT: ret255 %v = call <16 x float> @llvm.vp.minnum.v16f32(<16 x float> %va, <16 x float> %vb, <16 x i1> splat (i1 true), i32 %evl)256 ret <16 x float> %v257}258 259define <2 x double> @vfmin_vv_v2f64(<2 x double> %va, <2 x double> %vb, <2 x i1> %m, i32 zeroext %evl) {260; CHECK-LABEL: vfmin_vv_v2f64:261; CHECK: # %bb.0:262; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma263; CHECK-NEXT: vfmin.vv v8, v8, v9, v0.t264; CHECK-NEXT: ret265 %v = call <2 x double> @llvm.vp.minnum.v2f64(<2 x double> %va, <2 x double> %vb, <2 x i1> %m, i32 %evl)266 ret <2 x double> %v267}268 269define <2 x double> @vfmin_vv_v2f64_unmasked(<2 x double> %va, <2 x double> %vb, i32 zeroext %evl) {270; CHECK-LABEL: vfmin_vv_v2f64_unmasked:271; CHECK: # %bb.0:272; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma273; CHECK-NEXT: vfmin.vv v8, v8, v9274; CHECK-NEXT: ret275 %v = call <2 x double> @llvm.vp.minnum.v2f64(<2 x double> %va, <2 x double> %vb, <2 x i1> splat (i1 true), i32 %evl)276 ret <2 x double> %v277}278 279define <4 x double> @vfmin_vv_v4f64(<4 x double> %va, <4 x double> %vb, <4 x i1> %m, i32 zeroext %evl) {280; CHECK-LABEL: vfmin_vv_v4f64:281; CHECK: # %bb.0:282; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma283; CHECK-NEXT: vfmin.vv v8, v8, v10, v0.t284; CHECK-NEXT: ret285 %v = call <4 x double> @llvm.vp.minnum.v4f64(<4 x double> %va, <4 x double> %vb, <4 x i1> %m, i32 %evl)286 ret <4 x double> %v287}288 289define <4 x double> @vfmin_vv_v4f64_unmasked(<4 x double> %va, <4 x double> %vb, i32 zeroext %evl) {290; CHECK-LABEL: vfmin_vv_v4f64_unmasked:291; CHECK: # %bb.0:292; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma293; CHECK-NEXT: vfmin.vv v8, v8, v10294; CHECK-NEXT: ret295 %v = call <4 x double> @llvm.vp.minnum.v4f64(<4 x double> %va, <4 x double> %vb, <4 x i1> splat (i1 true), i32 %evl)296 ret <4 x double> %v297}298 299define <8 x double> @vfmin_vv_v8f64(<8 x double> %va, <8 x double> %vb, <8 x i1> %m, i32 zeroext %evl) {300; CHECK-LABEL: vfmin_vv_v8f64:301; CHECK: # %bb.0:302; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma303; CHECK-NEXT: vfmin.vv v8, v8, v12, v0.t304; CHECK-NEXT: ret305 %v = call <8 x double> @llvm.vp.minnum.v8f64(<8 x double> %va, <8 x double> %vb, <8 x i1> %m, i32 %evl)306 ret <8 x double> %v307}308 309define <8 x double> @vfmin_vv_v8f64_unmasked(<8 x double> %va, <8 x double> %vb, i32 zeroext %evl) {310; CHECK-LABEL: vfmin_vv_v8f64_unmasked:311; CHECK: # %bb.0:312; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma313; CHECK-NEXT: vfmin.vv v8, v8, v12314; CHECK-NEXT: ret315 %v = call <8 x double> @llvm.vp.minnum.v8f64(<8 x double> %va, <8 x double> %vb, <8 x i1> splat (i1 true), i32 %evl)316 ret <8 x double> %v317}318 319define <15 x double> @vfmin_vv_v15f64(<15 x double> %va, <15 x double> %vb, <15 x i1> %m, i32 zeroext %evl) {320; CHECK-LABEL: vfmin_vv_v15f64:321; CHECK: # %bb.0:322; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma323; CHECK-NEXT: vfmin.vv v8, v8, v16, v0.t324; CHECK-NEXT: ret325 %v = call <15 x double> @llvm.vp.minnum.v15f64(<15 x double> %va, <15 x double> %vb, <15 x i1> %m, i32 %evl)326 ret <15 x double> %v327}328 329define <15 x double> @vfmin_vv_v15f64_unmasked(<15 x double> %va, <15 x double> %vb, i32 zeroext %evl) {330; CHECK-LABEL: vfmin_vv_v15f64_unmasked:331; CHECK: # %bb.0:332; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma333; CHECK-NEXT: vfmin.vv v8, v8, v16334; CHECK-NEXT: ret335 %v = call <15 x double> @llvm.vp.minnum.v15f64(<15 x double> %va, <15 x double> %vb, <15 x i1> splat (i1 true), i32 %evl)336 ret <15 x double> %v337}338 339define <16 x double> @vfmin_vv_v16f64(<16 x double> %va, <16 x double> %vb, <16 x i1> %m, i32 zeroext %evl) {340; CHECK-LABEL: vfmin_vv_v16f64:341; CHECK: # %bb.0:342; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma343; CHECK-NEXT: vfmin.vv v8, v8, v16, v0.t344; CHECK-NEXT: ret345 %v = call <16 x double> @llvm.vp.minnum.v16f64(<16 x double> %va, <16 x double> %vb, <16 x i1> %m, i32 %evl)346 ret <16 x double> %v347}348 349define <16 x double> @vfmin_vv_v16f64_unmasked(<16 x double> %va, <16 x double> %vb, i32 zeroext %evl) {350; CHECK-LABEL: vfmin_vv_v16f64_unmasked:351; CHECK: # %bb.0:352; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma353; CHECK-NEXT: vfmin.vv v8, v8, v16354; CHECK-NEXT: ret355 %v = call <16 x double> @llvm.vp.minnum.v16f64(<16 x double> %va, <16 x double> %vb, <16 x i1> splat (i1 true), i32 %evl)356 ret <16 x double> %v357}358 359define <32 x double> @vfmin_vv_v32f64(<32 x double> %va, <32 x double> %vb, <32 x i1> %m, i32 zeroext %evl) {360; CHECK-LABEL: vfmin_vv_v32f64:361; CHECK: # %bb.0:362; CHECK-NEXT: addi sp, sp, -16363; CHECK-NEXT: .cfi_def_cfa_offset 16364; CHECK-NEXT: csrr a1, vlenb365; CHECK-NEXT: slli a1, a1, 3366; CHECK-NEXT: sub sp, sp, a1367; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb368; CHECK-NEXT: addi a1, sp, 16369; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill370; CHECK-NEXT: addi a1, a0, 128371; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma372; CHECK-NEXT: vle64.v v16, (a1)373; CHECK-NEXT: vle64.v v24, (a0)374; CHECK-NEXT: li a1, 16375; CHECK-NEXT: mv a0, a2376; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma377; CHECK-NEXT: vslidedown.vi v7, v0, 2378; CHECK-NEXT: bltu a2, a1, .LBB26_2379; CHECK-NEXT: # %bb.1:380; CHECK-NEXT: li a0, 16381; CHECK-NEXT: .LBB26_2:382; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma383; CHECK-NEXT: vfmin.vv v8, v8, v24, v0.t384; CHECK-NEXT: addi a0, a2, -16385; CHECK-NEXT: sltu a1, a2, a0386; CHECK-NEXT: addi a1, a1, -1387; CHECK-NEXT: and a0, a1, a0388; CHECK-NEXT: vmv1r.v v0, v7389; CHECK-NEXT: addi a1, sp, 16390; CHECK-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload391; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma392; CHECK-NEXT: vfmin.vv v16, v24, v16, v0.t393; CHECK-NEXT: csrr a0, vlenb394; CHECK-NEXT: slli a0, a0, 3395; CHECK-NEXT: add sp, sp, a0396; CHECK-NEXT: .cfi_def_cfa sp, 16397; CHECK-NEXT: addi sp, sp, 16398; CHECK-NEXT: .cfi_def_cfa_offset 0399; CHECK-NEXT: ret400 %v = call <32 x double> @llvm.vp.minnum.v32f64(<32 x double> %va, <32 x double> %vb, <32 x i1> %m, i32 %evl)401 ret <32 x double> %v402}403 404define <32 x double> @vfmin_vv_v32f64_unmasked(<32 x double> %va, <32 x double> %vb, i32 zeroext %evl) {405; CHECK-LABEL: vfmin_vv_v32f64_unmasked:406; CHECK: # %bb.0:407; CHECK-NEXT: addi a1, a0, 128408; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma409; CHECK-NEXT: vle64.v v24, (a1)410; CHECK-NEXT: vle64.v v0, (a0)411; CHECK-NEXT: li a1, 16412; CHECK-NEXT: mv a0, a2413; CHECK-NEXT: bltu a2, a1, .LBB27_2414; CHECK-NEXT: # %bb.1:415; CHECK-NEXT: li a0, 16416; CHECK-NEXT: .LBB27_2:417; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma418; CHECK-NEXT: vfmin.vv v8, v8, v0419; CHECK-NEXT: addi a0, a2, -16420; CHECK-NEXT: sltu a1, a2, a0421; CHECK-NEXT: addi a1, a1, -1422; CHECK-NEXT: and a0, a1, a0423; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma424; CHECK-NEXT: vfmin.vv v16, v16, v24425; CHECK-NEXT: ret426 %v = call <32 x double> @llvm.vp.minnum.v32f64(<32 x double> %va, <32 x double> %vb, <32 x i1> splat (i1 true), i32 %evl)427 ret <32 x double> %v428}429