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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zvfbfmin,+v -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH4; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zvfbfmin,+v -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH6; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+zvfbfmin,+v -target-abi=ilp32d \7; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN8; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+zvfbfmin,+v -target-abi=lp64d \9; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN10; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+experimental-zvfbfa,+v -target-abi=ilp32d \11; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFA12; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+experimental-zvfbfa,+v -target-abi=lp64d \13; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFA14 15define <2 x bfloat> @vfneg_vv_v2bf16(<2 x bfloat> %va, <2 x i1> %m, i32 zeroext %evl) {16; ZVFH-LABEL: vfneg_vv_v2bf16:17; ZVFH: # %bb.0:18; ZVFH-NEXT: lui a1, 819; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma20; ZVFH-NEXT: vxor.vx v8, v8, a1, v0.t21; ZVFH-NEXT: ret22;23; ZVFHMIN-LABEL: vfneg_vv_v2bf16:24; ZVFHMIN: # %bb.0:25; ZVFHMIN-NEXT: lui a1, 826; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma27; ZVFHMIN-NEXT: vxor.vx v8, v8, a1, v0.t28; ZVFHMIN-NEXT: ret29;30; ZVFBFA-LABEL: vfneg_vv_v2bf16:31; ZVFBFA: # %bb.0:32; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, mf4, ta, ma33; ZVFBFA-NEXT: vfneg.v v8, v8, v0.t34; ZVFBFA-NEXT: ret35 %v = call <2 x bfloat> @llvm.vp.fneg.v2bf16(<2 x bfloat> %va, <2 x i1> %m, i32 %evl)36 ret <2 x bfloat> %v37}38 39define <2 x bfloat> @vfneg_vv_v2bf16_unmasked(<2 x bfloat> %va, i32 zeroext %evl) {40; ZVFH-LABEL: vfneg_vv_v2bf16_unmasked:41; ZVFH: # %bb.0:42; ZVFH-NEXT: lui a1, 843; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma44; ZVFH-NEXT: vxor.vx v8, v8, a145; ZVFH-NEXT: ret46;47; ZVFHMIN-LABEL: vfneg_vv_v2bf16_unmasked:48; ZVFHMIN: # %bb.0:49; ZVFHMIN-NEXT: lui a1, 850; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma51; ZVFHMIN-NEXT: vxor.vx v8, v8, a152; ZVFHMIN-NEXT: ret53;54; ZVFBFA-LABEL: vfneg_vv_v2bf16_unmasked:55; ZVFBFA: # %bb.0:56; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, mf4, ta, ma57; ZVFBFA-NEXT: vfneg.v v8, v858; ZVFBFA-NEXT: ret59 %v = call <2 x bfloat> @llvm.vp.fneg.v2bf16(<2 x bfloat> %va, <2 x i1> splat (i1 true), i32 %evl)60 ret <2 x bfloat> %v61}62 63define <4 x bfloat> @vfneg_vv_v4bf16(<4 x bfloat> %va, <4 x i1> %m, i32 zeroext %evl) {64; ZVFH-LABEL: vfneg_vv_v4bf16:65; ZVFH: # %bb.0:66; ZVFH-NEXT: lui a1, 867; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma68; ZVFH-NEXT: vxor.vx v8, v8, a1, v0.t69; ZVFH-NEXT: ret70;71; ZVFHMIN-LABEL: vfneg_vv_v4bf16:72; ZVFHMIN: # %bb.0:73; ZVFHMIN-NEXT: lui a1, 874; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma75; ZVFHMIN-NEXT: vxor.vx v8, v8, a1, v0.t76; ZVFHMIN-NEXT: ret77;78; ZVFBFA-LABEL: vfneg_vv_v4bf16:79; ZVFBFA: # %bb.0:80; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, mf2, ta, ma81; ZVFBFA-NEXT: vfneg.v v8, v8, v0.t82; ZVFBFA-NEXT: ret83 %v = call <4 x bfloat> @llvm.vp.fneg.v4bf16(<4 x bfloat> %va, <4 x i1> %m, i32 %evl)84 ret <4 x bfloat> %v85}86 87define <4 x bfloat> @vfneg_vv_v4bf16_unmasked(<4 x bfloat> %va, i32 zeroext %evl) {88; ZVFH-LABEL: vfneg_vv_v4bf16_unmasked:89; ZVFH: # %bb.0:90; ZVFH-NEXT: lui a1, 891; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma92; ZVFH-NEXT: vxor.vx v8, v8, a193; ZVFH-NEXT: ret94;95; ZVFHMIN-LABEL: vfneg_vv_v4bf16_unmasked:96; ZVFHMIN: # %bb.0:97; ZVFHMIN-NEXT: lui a1, 898; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma99; ZVFHMIN-NEXT: vxor.vx v8, v8, a1100; ZVFHMIN-NEXT: ret101;102; ZVFBFA-LABEL: vfneg_vv_v4bf16_unmasked:103; ZVFBFA: # %bb.0:104; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, mf2, ta, ma105; ZVFBFA-NEXT: vfneg.v v8, v8106; ZVFBFA-NEXT: ret107 %v = call <4 x bfloat> @llvm.vp.fneg.v4bf16(<4 x bfloat> %va, <4 x i1> splat (i1 true), i32 %evl)108 ret <4 x bfloat> %v109}110 111define <8 x bfloat> @vfneg_vv_v8bf16(<8 x bfloat> %va, <8 x i1> %m, i32 zeroext %evl) {112; ZVFH-LABEL: vfneg_vv_v8bf16:113; ZVFH: # %bb.0:114; ZVFH-NEXT: lui a1, 8115; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma116; ZVFH-NEXT: vxor.vx v8, v8, a1, v0.t117; ZVFH-NEXT: ret118;119; ZVFHMIN-LABEL: vfneg_vv_v8bf16:120; ZVFHMIN: # %bb.0:121; ZVFHMIN-NEXT: lui a1, 8122; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma123; ZVFHMIN-NEXT: vxor.vx v8, v8, a1, v0.t124; ZVFHMIN-NEXT: ret125;126; ZVFBFA-LABEL: vfneg_vv_v8bf16:127; ZVFBFA: # %bb.0:128; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m1, ta, ma129; ZVFBFA-NEXT: vfneg.v v8, v8, v0.t130; ZVFBFA-NEXT: ret131 %v = call <8 x bfloat> @llvm.vp.fneg.v8bf16(<8 x bfloat> %va, <8 x i1> %m, i32 %evl)132 ret <8 x bfloat> %v133}134 135define <8 x bfloat> @vfneg_vv_v8bf16_unmasked(<8 x bfloat> %va, i32 zeroext %evl) {136; ZVFH-LABEL: vfneg_vv_v8bf16_unmasked:137; ZVFH: # %bb.0:138; ZVFH-NEXT: lui a1, 8139; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma140; ZVFH-NEXT: vxor.vx v8, v8, a1141; ZVFH-NEXT: ret142;143; ZVFHMIN-LABEL: vfneg_vv_v8bf16_unmasked:144; ZVFHMIN: # %bb.0:145; ZVFHMIN-NEXT: lui a1, 8146; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma147; ZVFHMIN-NEXT: vxor.vx v8, v8, a1148; ZVFHMIN-NEXT: ret149;150; ZVFBFA-LABEL: vfneg_vv_v8bf16_unmasked:151; ZVFBFA: # %bb.0:152; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m1, ta, ma153; ZVFBFA-NEXT: vfneg.v v8, v8154; ZVFBFA-NEXT: ret155 %v = call <8 x bfloat> @llvm.vp.fneg.v8bf16(<8 x bfloat> %va, <8 x i1> splat (i1 true), i32 %evl)156 ret <8 x bfloat> %v157}158 159define <16 x bfloat> @vfneg_vv_v16bf16(<16 x bfloat> %va, <16 x i1> %m, i32 zeroext %evl) {160; ZVFH-LABEL: vfneg_vv_v16bf16:161; ZVFH: # %bb.0:162; ZVFH-NEXT: lui a1, 8163; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma164; ZVFH-NEXT: vxor.vx v8, v8, a1, v0.t165; ZVFH-NEXT: ret166;167; ZVFHMIN-LABEL: vfneg_vv_v16bf16:168; ZVFHMIN: # %bb.0:169; ZVFHMIN-NEXT: lui a1, 8170; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma171; ZVFHMIN-NEXT: vxor.vx v8, v8, a1, v0.t172; ZVFHMIN-NEXT: ret173;174; ZVFBFA-LABEL: vfneg_vv_v16bf16:175; ZVFBFA: # %bb.0:176; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m2, ta, ma177; ZVFBFA-NEXT: vfneg.v v8, v8, v0.t178; ZVFBFA-NEXT: ret179 %v = call <16 x bfloat> @llvm.vp.fneg.v16bf16(<16 x bfloat> %va, <16 x i1> %m, i32 %evl)180 ret <16 x bfloat> %v181}182 183define <16 x bfloat> @vfneg_vv_v16bf16_unmasked(<16 x bfloat> %va, i32 zeroext %evl) {184; ZVFH-LABEL: vfneg_vv_v16bf16_unmasked:185; ZVFH: # %bb.0:186; ZVFH-NEXT: lui a1, 8187; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma188; ZVFH-NEXT: vxor.vx v8, v8, a1189; ZVFH-NEXT: ret190;191; ZVFHMIN-LABEL: vfneg_vv_v16bf16_unmasked:192; ZVFHMIN: # %bb.0:193; ZVFHMIN-NEXT: lui a1, 8194; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma195; ZVFHMIN-NEXT: vxor.vx v8, v8, a1196; ZVFHMIN-NEXT: ret197;198; ZVFBFA-LABEL: vfneg_vv_v16bf16_unmasked:199; ZVFBFA: # %bb.0:200; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m2, ta, ma201; ZVFBFA-NEXT: vfneg.v v8, v8202; ZVFBFA-NEXT: ret203 %v = call <16 x bfloat> @llvm.vp.fneg.v16bf16(<16 x bfloat> %va, <16 x i1> splat (i1 true), i32 %evl)204 ret <16 x bfloat> %v205}206 207define <2 x half> @vfneg_vv_v2f16(<2 x half> %va, <2 x i1> %m, i32 zeroext %evl) {208; ZVFH-LABEL: vfneg_vv_v2f16:209; ZVFH: # %bb.0:210; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma211; ZVFH-NEXT: vfneg.v v8, v8, v0.t212; ZVFH-NEXT: ret213;214; ZVFHMIN-LABEL: vfneg_vv_v2f16:215; ZVFHMIN: # %bb.0:216; ZVFHMIN-NEXT: lui a1, 8217; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma218; ZVFHMIN-NEXT: vxor.vx v8, v8, a1, v0.t219; ZVFHMIN-NEXT: ret220;221; ZVFBFA-LABEL: vfneg_vv_v2f16:222; ZVFBFA: # %bb.0:223; ZVFBFA-NEXT: lui a1, 8224; ZVFBFA-NEXT: vsetvli zero, a0, e16, mf4, ta, ma225; ZVFBFA-NEXT: vxor.vx v8, v8, a1, v0.t226; ZVFBFA-NEXT: ret227 %v = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %va, <2 x i1> %m, i32 %evl)228 ret <2 x half> %v229}230 231define <2 x half> @vfneg_vv_v2f16_unmasked(<2 x half> %va, i32 zeroext %evl) {232; ZVFH-LABEL: vfneg_vv_v2f16_unmasked:233; ZVFH: # %bb.0:234; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma235; ZVFH-NEXT: vfneg.v v8, v8236; ZVFH-NEXT: ret237;238; ZVFHMIN-LABEL: vfneg_vv_v2f16_unmasked:239; ZVFHMIN: # %bb.0:240; ZVFHMIN-NEXT: lui a1, 8241; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma242; ZVFHMIN-NEXT: vxor.vx v8, v8, a1243; ZVFHMIN-NEXT: ret244;245; ZVFBFA-LABEL: vfneg_vv_v2f16_unmasked:246; ZVFBFA: # %bb.0:247; ZVFBFA-NEXT: lui a1, 8248; ZVFBFA-NEXT: vsetvli zero, a0, e16, mf4, ta, ma249; ZVFBFA-NEXT: vxor.vx v8, v8, a1250; ZVFBFA-NEXT: ret251 %v = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %va, <2 x i1> splat (i1 true), i32 %evl)252 ret <2 x half> %v253}254 255define <4 x half> @vfneg_vv_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl) {256; ZVFH-LABEL: vfneg_vv_v4f16:257; ZVFH: # %bb.0:258; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma259; ZVFH-NEXT: vfneg.v v8, v8, v0.t260; ZVFH-NEXT: ret261;262; ZVFHMIN-LABEL: vfneg_vv_v4f16:263; ZVFHMIN: # %bb.0:264; ZVFHMIN-NEXT: lui a1, 8265; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma266; ZVFHMIN-NEXT: vxor.vx v8, v8, a1, v0.t267; ZVFHMIN-NEXT: ret268;269; ZVFBFA-LABEL: vfneg_vv_v4f16:270; ZVFBFA: # %bb.0:271; ZVFBFA-NEXT: lui a1, 8272; ZVFBFA-NEXT: vsetvli zero, a0, e16, mf2, ta, ma273; ZVFBFA-NEXT: vxor.vx v8, v8, a1, v0.t274; ZVFBFA-NEXT: ret275 %v = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %va, <4 x i1> %m, i32 %evl)276 ret <4 x half> %v277}278 279define <4 x half> @vfneg_vv_v4f16_unmasked(<4 x half> %va, i32 zeroext %evl) {280; ZVFH-LABEL: vfneg_vv_v4f16_unmasked:281; ZVFH: # %bb.0:282; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma283; ZVFH-NEXT: vfneg.v v8, v8284; ZVFH-NEXT: ret285;286; ZVFHMIN-LABEL: vfneg_vv_v4f16_unmasked:287; ZVFHMIN: # %bb.0:288; ZVFHMIN-NEXT: lui a1, 8289; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma290; ZVFHMIN-NEXT: vxor.vx v8, v8, a1291; ZVFHMIN-NEXT: ret292;293; ZVFBFA-LABEL: vfneg_vv_v4f16_unmasked:294; ZVFBFA: # %bb.0:295; ZVFBFA-NEXT: lui a1, 8296; ZVFBFA-NEXT: vsetvli zero, a0, e16, mf2, ta, ma297; ZVFBFA-NEXT: vxor.vx v8, v8, a1298; ZVFBFA-NEXT: ret299 %v = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %va, <4 x i1> splat (i1 true), i32 %evl)300 ret <4 x half> %v301}302 303define <8 x half> @vfneg_vv_v8f16(<8 x half> %va, <8 x i1> %m, i32 zeroext %evl) {304; ZVFH-LABEL: vfneg_vv_v8f16:305; ZVFH: # %bb.0:306; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma307; ZVFH-NEXT: vfneg.v v8, v8, v0.t308; ZVFH-NEXT: ret309;310; ZVFHMIN-LABEL: vfneg_vv_v8f16:311; ZVFHMIN: # %bb.0:312; ZVFHMIN-NEXT: lui a1, 8313; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma314; ZVFHMIN-NEXT: vxor.vx v8, v8, a1, v0.t315; ZVFHMIN-NEXT: ret316;317; ZVFBFA-LABEL: vfneg_vv_v8f16:318; ZVFBFA: # %bb.0:319; ZVFBFA-NEXT: lui a1, 8320; ZVFBFA-NEXT: vsetvli zero, a0, e16, m1, ta, ma321; ZVFBFA-NEXT: vxor.vx v8, v8, a1, v0.t322; ZVFBFA-NEXT: ret323 %v = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %va, <8 x i1> %m, i32 %evl)324 ret <8 x half> %v325}326 327define <8 x half> @vfneg_vv_v8f16_unmasked(<8 x half> %va, i32 zeroext %evl) {328; ZVFH-LABEL: vfneg_vv_v8f16_unmasked:329; ZVFH: # %bb.0:330; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma331; ZVFH-NEXT: vfneg.v v8, v8332; ZVFH-NEXT: ret333;334; ZVFHMIN-LABEL: vfneg_vv_v8f16_unmasked:335; ZVFHMIN: # %bb.0:336; ZVFHMIN-NEXT: lui a1, 8337; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma338; ZVFHMIN-NEXT: vxor.vx v8, v8, a1339; ZVFHMIN-NEXT: ret340;341; ZVFBFA-LABEL: vfneg_vv_v8f16_unmasked:342; ZVFBFA: # %bb.0:343; ZVFBFA-NEXT: lui a1, 8344; ZVFBFA-NEXT: vsetvli zero, a0, e16, m1, ta, ma345; ZVFBFA-NEXT: vxor.vx v8, v8, a1346; ZVFBFA-NEXT: ret347 %v = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %va, <8 x i1> splat (i1 true), i32 %evl)348 ret <8 x half> %v349}350 351define <16 x half> @vfneg_vv_v16f16(<16 x half> %va, <16 x i1> %m, i32 zeroext %evl) {352; ZVFH-LABEL: vfneg_vv_v16f16:353; ZVFH: # %bb.0:354; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma355; ZVFH-NEXT: vfneg.v v8, v8, v0.t356; ZVFH-NEXT: ret357;358; ZVFHMIN-LABEL: vfneg_vv_v16f16:359; ZVFHMIN: # %bb.0:360; ZVFHMIN-NEXT: lui a1, 8361; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma362; ZVFHMIN-NEXT: vxor.vx v8, v8, a1, v0.t363; ZVFHMIN-NEXT: ret364;365; ZVFBFA-LABEL: vfneg_vv_v16f16:366; ZVFBFA: # %bb.0:367; ZVFBFA-NEXT: lui a1, 8368; ZVFBFA-NEXT: vsetvli zero, a0, e16, m2, ta, ma369; ZVFBFA-NEXT: vxor.vx v8, v8, a1, v0.t370; ZVFBFA-NEXT: ret371 %v = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %va, <16 x i1> %m, i32 %evl)372 ret <16 x half> %v373}374 375define <16 x half> @vfneg_vv_v16f16_unmasked(<16 x half> %va, i32 zeroext %evl) {376; ZVFH-LABEL: vfneg_vv_v16f16_unmasked:377; ZVFH: # %bb.0:378; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma379; ZVFH-NEXT: vfneg.v v8, v8380; ZVFH-NEXT: ret381;382; ZVFHMIN-LABEL: vfneg_vv_v16f16_unmasked:383; ZVFHMIN: # %bb.0:384; ZVFHMIN-NEXT: lui a1, 8385; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma386; ZVFHMIN-NEXT: vxor.vx v8, v8, a1387; ZVFHMIN-NEXT: ret388;389; ZVFBFA-LABEL: vfneg_vv_v16f16_unmasked:390; ZVFBFA: # %bb.0:391; ZVFBFA-NEXT: lui a1, 8392; ZVFBFA-NEXT: vsetvli zero, a0, e16, m2, ta, ma393; ZVFBFA-NEXT: vxor.vx v8, v8, a1394; ZVFBFA-NEXT: ret395 %v = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %va, <16 x i1> splat (i1 true), i32 %evl)396 ret <16 x half> %v397}398 399define <2 x float> @vfneg_vv_v2f32(<2 x float> %va, <2 x i1> %m, i32 zeroext %evl) {400; CHECK-LABEL: vfneg_vv_v2f32:401; CHECK: # %bb.0:402; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma403; CHECK-NEXT: vfneg.v v8, v8, v0.t404; CHECK-NEXT: ret405 %v = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %va, <2 x i1> %m, i32 %evl)406 ret <2 x float> %v407}408 409define <2 x float> @vfneg_vv_v2f32_unmasked(<2 x float> %va, i32 zeroext %evl) {410; CHECK-LABEL: vfneg_vv_v2f32_unmasked:411; CHECK: # %bb.0:412; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma413; CHECK-NEXT: vfneg.v v8, v8414; CHECK-NEXT: ret415 %v = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %va, <2 x i1> splat (i1 true), i32 %evl)416 ret <2 x float> %v417}418 419define <4 x float> @vfneg_vv_v4f32(<4 x float> %va, <4 x i1> %m, i32 zeroext %evl) {420; CHECK-LABEL: vfneg_vv_v4f32:421; CHECK: # %bb.0:422; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma423; CHECK-NEXT: vfneg.v v8, v8, v0.t424; CHECK-NEXT: ret425 %v = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %va, <4 x i1> %m, i32 %evl)426 ret <4 x float> %v427}428 429define <4 x float> @vfneg_vv_v4f32_unmasked(<4 x float> %va, i32 zeroext %evl) {430; CHECK-LABEL: vfneg_vv_v4f32_unmasked:431; CHECK: # %bb.0:432; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma433; CHECK-NEXT: vfneg.v v8, v8434; CHECK-NEXT: ret435 %v = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %va, <4 x i1> splat (i1 true), i32 %evl)436 ret <4 x float> %v437}438 439define <8 x float> @vfneg_vv_v8f32(<8 x float> %va, <8 x i1> %m, i32 zeroext %evl) {440; CHECK-LABEL: vfneg_vv_v8f32:441; CHECK: # %bb.0:442; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma443; CHECK-NEXT: vfneg.v v8, v8, v0.t444; CHECK-NEXT: ret445 %v = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %va, <8 x i1> %m, i32 %evl)446 ret <8 x float> %v447}448 449define <8 x float> @vfneg_vv_v8f32_unmasked(<8 x float> %va, i32 zeroext %evl) {450; CHECK-LABEL: vfneg_vv_v8f32_unmasked:451; CHECK: # %bb.0:452; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma453; CHECK-NEXT: vfneg.v v8, v8454; CHECK-NEXT: ret455 %v = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %va, <8 x i1> splat (i1 true), i32 %evl)456 ret <8 x float> %v457}458 459define <16 x float> @vfneg_vv_v16f32(<16 x float> %va, <16 x i1> %m, i32 zeroext %evl) {460; CHECK-LABEL: vfneg_vv_v16f32:461; CHECK: # %bb.0:462; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma463; CHECK-NEXT: vfneg.v v8, v8, v0.t464; CHECK-NEXT: ret465 %v = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %va, <16 x i1> %m, i32 %evl)466 ret <16 x float> %v467}468 469define <16 x float> @vfneg_vv_v16f32_unmasked(<16 x float> %va, i32 zeroext %evl) {470; CHECK-LABEL: vfneg_vv_v16f32_unmasked:471; CHECK: # %bb.0:472; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma473; CHECK-NEXT: vfneg.v v8, v8474; CHECK-NEXT: ret475 %v = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %va, <16 x i1> splat (i1 true), i32 %evl)476 ret <16 x float> %v477}478 479define <2 x double> @vfneg_vv_v2f64(<2 x double> %va, <2 x i1> %m, i32 zeroext %evl) {480; CHECK-LABEL: vfneg_vv_v2f64:481; CHECK: # %bb.0:482; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma483; CHECK-NEXT: vfneg.v v8, v8, v0.t484; CHECK-NEXT: ret485 %v = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %va, <2 x i1> %m, i32 %evl)486 ret <2 x double> %v487}488 489define <2 x double> @vfneg_vv_v2f64_unmasked(<2 x double> %va, i32 zeroext %evl) {490; CHECK-LABEL: vfneg_vv_v2f64_unmasked:491; CHECK: # %bb.0:492; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma493; CHECK-NEXT: vfneg.v v8, v8494; CHECK-NEXT: ret495 %v = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %va, <2 x i1> splat (i1 true), i32 %evl)496 ret <2 x double> %v497}498 499define <4 x double> @vfneg_vv_v4f64(<4 x double> %va, <4 x i1> %m, i32 zeroext %evl) {500; CHECK-LABEL: vfneg_vv_v4f64:501; CHECK: # %bb.0:502; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma503; CHECK-NEXT: vfneg.v v8, v8, v0.t504; CHECK-NEXT: ret505 %v = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %va, <4 x i1> %m, i32 %evl)506 ret <4 x double> %v507}508 509define <4 x double> @vfneg_vv_v4f64_unmasked(<4 x double> %va, i32 zeroext %evl) {510; CHECK-LABEL: vfneg_vv_v4f64_unmasked:511; CHECK: # %bb.0:512; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma513; CHECK-NEXT: vfneg.v v8, v8514; CHECK-NEXT: ret515 %v = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %va, <4 x i1> splat (i1 true), i32 %evl)516 ret <4 x double> %v517}518 519define <8 x double> @vfneg_vv_v8f64(<8 x double> %va, <8 x i1> %m, i32 zeroext %evl) {520; CHECK-LABEL: vfneg_vv_v8f64:521; CHECK: # %bb.0:522; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma523; CHECK-NEXT: vfneg.v v8, v8, v0.t524; CHECK-NEXT: ret525 %v = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %va, <8 x i1> %m, i32 %evl)526 ret <8 x double> %v527}528 529define <8 x double> @vfneg_vv_v8f64_unmasked(<8 x double> %va, i32 zeroext %evl) {530; CHECK-LABEL: vfneg_vv_v8f64_unmasked:531; CHECK: # %bb.0:532; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma533; CHECK-NEXT: vfneg.v v8, v8534; CHECK-NEXT: ret535 %v = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %va, <8 x i1> splat (i1 true), i32 %evl)536 ret <8 x double> %v537}538 539define <15 x double> @vfneg_vv_v15f64(<15 x double> %va, <15 x i1> %m, i32 zeroext %evl) {540; CHECK-LABEL: vfneg_vv_v15f64:541; CHECK: # %bb.0:542; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma543; CHECK-NEXT: vfneg.v v8, v8, v0.t544; CHECK-NEXT: ret545 %v = call <15 x double> @llvm.vp.fneg.v15f64(<15 x double> %va, <15 x i1> %m, i32 %evl)546 ret <15 x double> %v547}548 549define <15 x double> @vfneg_vv_v15f64_unmasked(<15 x double> %va, i32 zeroext %evl) {550; CHECK-LABEL: vfneg_vv_v15f64_unmasked:551; CHECK: # %bb.0:552; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma553; CHECK-NEXT: vfneg.v v8, v8554; CHECK-NEXT: ret555 %v = call <15 x double> @llvm.vp.fneg.v15f64(<15 x double> %va, <15 x i1> splat (i1 true), i32 %evl)556 ret <15 x double> %v557}558 559define <16 x double> @vfneg_vv_v16f64(<16 x double> %va, <16 x i1> %m, i32 zeroext %evl) {560; CHECK-LABEL: vfneg_vv_v16f64:561; CHECK: # %bb.0:562; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma563; CHECK-NEXT: vfneg.v v8, v8, v0.t564; CHECK-NEXT: ret565 %v = call <16 x double> @llvm.vp.fneg.v16f64(<16 x double> %va, <16 x i1> %m, i32 %evl)566 ret <16 x double> %v567}568 569define <16 x double> @vfneg_vv_v16f64_unmasked(<16 x double> %va, i32 zeroext %evl) {570; CHECK-LABEL: vfneg_vv_v16f64_unmasked:571; CHECK: # %bb.0:572; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma573; CHECK-NEXT: vfneg.v v8, v8574; CHECK-NEXT: ret575 %v = call <16 x double> @llvm.vp.fneg.v16f64(<16 x double> %va, <16 x i1> splat (i1 true), i32 %evl)576 ret <16 x double> %v577}578 579define <32 x double> @vfneg_vv_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroext %evl) {580; CHECK-LABEL: vfneg_vv_v32f64:581; CHECK: # %bb.0:582; CHECK-NEXT: li a2, 16583; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma584; CHECK-NEXT: vslidedown.vi v24, v0, 2585; CHECK-NEXT: mv a1, a0586; CHECK-NEXT: bltu a0, a2, .LBB34_2587; CHECK-NEXT: # %bb.1:588; CHECK-NEXT: li a1, 16589; CHECK-NEXT: .LBB34_2:590; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma591; CHECK-NEXT: vfneg.v v8, v8, v0.t592; CHECK-NEXT: addi a1, a0, -16593; CHECK-NEXT: sltu a0, a0, a1594; CHECK-NEXT: addi a0, a0, -1595; CHECK-NEXT: and a0, a0, a1596; CHECK-NEXT: vmv1r.v v0, v24597; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma598; CHECK-NEXT: vfneg.v v16, v16, v0.t599; CHECK-NEXT: ret600 %v = call <32 x double> @llvm.vp.fneg.v32f64(<32 x double> %va, <32 x i1> %m, i32 %evl)601 ret <32 x double> %v602}603 604define <32 x double> @vfneg_vv_v32f64_unmasked(<32 x double> %va, i32 zeroext %evl) {605; CHECK-LABEL: vfneg_vv_v32f64_unmasked:606; CHECK: # %bb.0:607; CHECK-NEXT: li a2, 16608; CHECK-NEXT: mv a1, a0609; CHECK-NEXT: bltu a0, a2, .LBB35_2610; CHECK-NEXT: # %bb.1:611; CHECK-NEXT: li a1, 16612; CHECK-NEXT: .LBB35_2:613; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma614; CHECK-NEXT: vfneg.v v8, v8615; CHECK-NEXT: addi a1, a0, -16616; CHECK-NEXT: sltu a0, a0, a1617; CHECK-NEXT: addi a0, a0, -1618; CHECK-NEXT: and a0, a0, a1619; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma620; CHECK-NEXT: vfneg.v v16, v16621; CHECK-NEXT: ret622 %v = call <32 x double> @llvm.vp.fneg.v32f64(<32 x double> %va, <32 x i1> splat (i1 true), i32 %evl)623 ret <32 x double> %v624}625