388 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s4 5define <8 x i8> @vnsra_v8i16_v8i8_scalar(<8 x i16> %x, i16 %y) {6; CHECK-LABEL: vnsra_v8i16_v8i8_scalar:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma9; CHECK-NEXT: vnsra.wx v8, v8, a010; CHECK-NEXT: ret11 %insert = insertelement <8 x i16> poison, i16 %y, i16 012 %splat = shufflevector <8 x i16> %insert, <8 x i16> poison, <8 x i32> zeroinitializer13 %a = ashr <8 x i16> %x, %splat14 %b = trunc <8 x i16> %a to <8 x i8>15 ret <8 x i8> %b16}17 18define <8 x i8> @vnsra_v8i16_v8i8_scalar_sext(<8 x i16> %x, i8 %y) {19; CHECK-LABEL: vnsra_v8i16_v8i8_scalar_sext:20; CHECK: # %bb.0:21; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma22; CHECK-NEXT: vnsra.wx v8, v8, a023; CHECK-NEXT: ret24 %insert = insertelement <8 x i8> poison, i8 %y, i8 025 %splat = shufflevector <8 x i8> %insert, <8 x i8> poison, <8 x i32> zeroinitializer26 %sext = sext <8 x i8> %splat to <8 x i16>27 %a = ashr <8 x i16> %x, %sext28 %b = trunc <8 x i16> %a to <8 x i8>29 ret <8 x i8> %b30}31 32define <8 x i8> @vnsra_v8i16_v8i8_scalar_zext(<8 x i16> %x, i8 %y) {33; CHECK-LABEL: vnsra_v8i16_v8i8_scalar_zext:34; CHECK: # %bb.0:35; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma36; CHECK-NEXT: vnsra.wx v8, v8, a037; CHECK-NEXT: ret38 %insert = insertelement <8 x i8> poison, i8 %y, i8 039 %splat = shufflevector <8 x i8> %insert, <8 x i8> poison, <8 x i32> zeroinitializer40 %zext = zext <8 x i8> %splat to <8 x i16>41 %a = ashr <8 x i16> %x, %zext42 %b = trunc <8 x i16> %a to <8 x i8>43 ret <8 x i8> %b44}45 46define <4 x i16> @vnsra_v4i32_v4i16_scalar(<4 x i32> %x, i32 %y) {47; CHECK-LABEL: vnsra_v4i32_v4i16_scalar:48; CHECK: # %bb.0:49; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma50; CHECK-NEXT: vnsra.wx v8, v8, a051; CHECK-NEXT: ret52 %insert = insertelement <4 x i32> poison, i32 %y, i32 053 %splat = shufflevector <4 x i32> %insert, <4 x i32> poison, <4 x i32> zeroinitializer54 %a = ashr <4 x i32> %x, %splat55 %b = trunc <4 x i32> %a to <4 x i16>56 ret <4 x i16> %b57}58 59define <4 x i16> @vnsra_v4i32_v4i16_scalar_sext(<4 x i32> %x, i16 %y) {60; CHECK-LABEL: vnsra_v4i32_v4i16_scalar_sext:61; CHECK: # %bb.0:62; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma63; CHECK-NEXT: vnsra.wx v8, v8, a064; CHECK-NEXT: ret65 %insert = insertelement <4 x i16> poison, i16 %y, i16 066 %splat = shufflevector <4 x i16> %insert, <4 x i16> poison, <4 x i32> zeroinitializer67 %sext = sext <4 x i16> %splat to <4 x i32>68 %a = ashr <4 x i32> %x, %sext69 %b = trunc <4 x i32> %a to <4 x i16>70 ret <4 x i16> %b71}72 73define <4 x i16> @vnsra_v4i32_v4i16_scalar_zext(<4 x i32> %x, i16 %y) {74; CHECK-LABEL: vnsra_v4i32_v4i16_scalar_zext:75; CHECK: # %bb.0:76; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma77; CHECK-NEXT: vnsra.wx v8, v8, a078; CHECK-NEXT: ret79 %insert = insertelement <4 x i16> poison, i16 %y, i16 080 %splat = shufflevector <4 x i16> %insert, <4 x i16> poison, <4 x i32> zeroinitializer81 %zext = zext <4 x i16> %splat to <4 x i32>82 %a = ashr <4 x i32> %x, %zext83 %b = trunc <4 x i32> %a to <4 x i16>84 ret <4 x i16> %b85}86 87define <2 x i32> @vnsra_v2i64_v2i32_scalar(<2 x i64> %x, i64 %y) {88; CHECK-LABEL: vnsra_v2i64_v2i32_scalar:89; CHECK: # %bb.0:90; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma91; CHECK-NEXT: vnsra.wx v8, v8, a092; CHECK-NEXT: ret93 %insert = insertelement <2 x i64> poison, i64 %y, i32 094 %splat = shufflevector <2 x i64> %insert, <2 x i64> poison, <2 x i32> zeroinitializer95 %a = ashr <2 x i64> %x, %splat96 %b = trunc <2 x i64> %a to <2 x i32>97 ret <2 x i32> %b98}99 100define <2 x i32> @vnsra_v2i64_v2i32_scalar_sext(<2 x i64> %x, i32 %y) {101; CHECK-LABEL: vnsra_v2i64_v2i32_scalar_sext:102; CHECK: # %bb.0:103; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma104; CHECK-NEXT: vnsra.wx v8, v8, a0105; CHECK-NEXT: ret106 %insert = insertelement <2 x i32> poison, i32 %y, i32 0107 %splat = shufflevector <2 x i32> %insert, <2 x i32> poison, <2 x i32> zeroinitializer108 %sext = sext <2 x i32> %splat to <2 x i64>109 %a = ashr <2 x i64> %x, %sext110 %b = trunc <2 x i64> %a to <2 x i32>111 ret <2 x i32> %b112}113 114define <2 x i32> @vnsra_v2i64_v2i32_scalar_zext(<2 x i64> %x, i32 %y) {115; CHECK-LABEL: vnsra_v2i64_v2i32_scalar_zext:116; CHECK: # %bb.0:117; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma118; CHECK-NEXT: vnsra.wx v8, v8, a0119; CHECK-NEXT: ret120 %insert = insertelement <2 x i32> poison, i32 %y, i32 0121 %splat = shufflevector <2 x i32> %insert, <2 x i32> poison, <2 x i32> zeroinitializer122 %zext = zext <2 x i32> %splat to <2 x i64>123 %a = ashr <2 x i64> %x, %zext124 %b = trunc <2 x i64> %a to <2 x i32>125 ret <2 x i32> %b126}127 128define <8 x i8> @vnsra_v8i16_v8i8_imm(<8 x i16> %x) {129; CHECK-LABEL: vnsra_v8i16_v8i8_imm:130; CHECK: # %bb.0:131; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma132; CHECK-NEXT: vnsrl.wi v8, v8, 8133; CHECK-NEXT: ret134 %a = ashr <8 x i16> %x, <i16 8, i16 8, i16 8, i16 8,i16 8, i16 8, i16 8, i16 8>135 %b = trunc <8 x i16> %a to <8 x i8>136 ret <8 x i8> %b137}138 139define <4 x i16> @vnsra_v4i32_v4i16_imm(<4 x i32> %x) {140; CHECK-LABEL: vnsra_v4i32_v4i16_imm:141; CHECK: # %bb.0:142; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma143; CHECK-NEXT: vnsrl.wi v8, v8, 16144; CHECK-NEXT: ret145 %a = ashr <4 x i32> %x, <i32 16, i32 16, i32 16, i32 16>146 %b = trunc <4 x i32> %a to <4 x i16>147 ret <4 x i16> %b148}149 150define <2 x i32> @vnsra_v2i64_v2i32_imm(<2 x i64> %x) {151; CHECK-LABEL: vnsra_v2i64_v2i32_imm:152; CHECK: # %bb.0:153; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma154; CHECK-NEXT: vnsrl.wi v8, v8, 31155; CHECK-NEXT: ret156 %a = ashr <2 x i64> %x, <i64 31, i64 31>157 %b = trunc <2 x i64> %a to <2 x i32>158 ret <2 x i32> %b159}160 161define <8 x i8> @vnsra_v8i16_v8i8_sext(<8 x i16> %x, <8 x i8> %y) {162; CHECK-LABEL: vnsra_v8i16_v8i8_sext:163; CHECK: # %bb.0:164; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma165; CHECK-NEXT: vnsra.wv v8, v8, v9166; CHECK-NEXT: ret167 %sext = sext <8 x i8> %y to <8 x i16>168 %a = ashr <8 x i16> %x, %sext169 %b = trunc <8 x i16> %a to <8 x i8>170 ret <8 x i8> %b171}172 173define <8 x i8> @vnsra_v8i16_v8i8_zext(<8 x i16> %x, <8 x i8> %y) {174; CHECK-LABEL: vnsra_v8i16_v8i8_zext:175; CHECK: # %bb.0:176; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma177; CHECK-NEXT: vnsra.wv v8, v8, v9178; CHECK-NEXT: ret179 %sext = zext <8 x i8> %y to <8 x i16>180 %a = ashr <8 x i16> %x, %sext181 %b = trunc <8 x i16> %a to <8 x i8>182 ret <8 x i8> %b183}184 185define <8 x i8> @vnsrl_v8i16_v8i8_scalar(<8 x i16> %x, i16 %y) {186; CHECK-LABEL: vnsrl_v8i16_v8i8_scalar:187; CHECK: # %bb.0:188; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma189; CHECK-NEXT: vnsrl.wx v8, v8, a0190; CHECK-NEXT: ret191 %insert = insertelement <8 x i16> poison, i16 %y, i16 0192 %splat = shufflevector <8 x i16> %insert, <8 x i16> poison, <8 x i32> zeroinitializer193 %a = lshr <8 x i16> %x, %splat194 %b = trunc <8 x i16> %a to <8 x i8>195 ret <8 x i8> %b196}197 198define <8 x i8> @vnsrl_v8i16_v8i8_scalar_sext(<8 x i16> %x, i8 %y) {199; CHECK-LABEL: vnsrl_v8i16_v8i8_scalar_sext:200; CHECK: # %bb.0:201; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma202; CHECK-NEXT: vnsrl.wx v8, v8, a0203; CHECK-NEXT: ret204 %insert = insertelement <8 x i8> poison, i8 %y, i16 0205 %splat = shufflevector <8 x i8> %insert, <8 x i8> poison, <8 x i32> zeroinitializer206 %sext = sext <8 x i8> %splat to <8 x i16>207 %a = lshr <8 x i16> %x, %sext208 %b = trunc <8 x i16> %a to <8 x i8>209 ret <8 x i8> %b210}211 212define <8 x i8> @vnsrl_v8i16_v8i8_scalar_zext(<8 x i16> %x, i8 %y) {213; CHECK-LABEL: vnsrl_v8i16_v8i8_scalar_zext:214; CHECK: # %bb.0:215; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma216; CHECK-NEXT: vnsrl.wx v8, v8, a0217; CHECK-NEXT: ret218 %insert = insertelement <8 x i8> poison, i8 %y, i16 0219 %splat = shufflevector <8 x i8> %insert, <8 x i8> poison, <8 x i32> zeroinitializer220 %zext = zext <8 x i8> %splat to <8 x i16>221 %a = lshr <8 x i16> %x, %zext222 %b = trunc <8 x i16> %a to <8 x i8>223 ret <8 x i8> %b224}225 226define <4 x i16> @vnsrl_v4i32_v4i16_scalar(<4 x i32> %x, i32 %y) {227; CHECK-LABEL: vnsrl_v4i32_v4i16_scalar:228; CHECK: # %bb.0:229; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma230; CHECK-NEXT: vnsrl.wx v8, v8, a0231; CHECK-NEXT: ret232 %insert = insertelement <4 x i32> poison, i32 %y, i32 0233 %splat = shufflevector <4 x i32> %insert, <4 x i32> poison, <4 x i32> zeroinitializer234 %a = lshr <4 x i32> %x, %splat235 %b = trunc <4 x i32> %a to <4 x i16>236 ret <4 x i16> %b237}238 239define <4 x i16> @vnsrl_v4i32_v4i16_scalar_sext(<4 x i32> %x, i16 %y) {240; CHECK-LABEL: vnsrl_v4i32_v4i16_scalar_sext:241; CHECK: # %bb.0:242; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma243; CHECK-NEXT: vnsrl.wx v8, v8, a0244; CHECK-NEXT: ret245 %insert = insertelement <4 x i16> poison, i16 %y, i16 0246 %splat = shufflevector <4 x i16> %insert, <4 x i16> poison, <4 x i32> zeroinitializer247 %sext = sext <4 x i16> %splat to <4 x i32>248 %a = lshr <4 x i32> %x, %sext249 %b = trunc <4 x i32> %a to <4 x i16>250 ret <4 x i16> %b251}252 253define <4 x i16> @vnsrl_v4i32_v4i16_scalar_zext(<4 x i32> %x, i16 %y) {254; CHECK-LABEL: vnsrl_v4i32_v4i16_scalar_zext:255; CHECK: # %bb.0:256; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma257; CHECK-NEXT: vnsrl.wx v8, v8, a0258; CHECK-NEXT: ret259 %insert = insertelement <4 x i16> poison, i16 %y, i16 0260 %splat = shufflevector <4 x i16> %insert, <4 x i16> poison, <4 x i32> zeroinitializer261 %zext = zext <4 x i16> %splat to <4 x i32>262 %a = lshr <4 x i32> %x, %zext263 %b = trunc <4 x i32> %a to <4 x i16>264 ret <4 x i16> %b265}266 267define <2 x i32> @vnsrl_v2i64_v2i32_scalar(<2 x i64> %x, i64 %y) {268; CHECK-LABEL: vnsrl_v2i64_v2i32_scalar:269; CHECK: # %bb.0:270; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma271; CHECK-NEXT: vnsrl.wx v8, v8, a0272; CHECK-NEXT: ret273 %insert = insertelement <2 x i64> poison, i64 %y, i32 0274 %splat = shufflevector <2 x i64> %insert, <2 x i64> poison, <2 x i32> zeroinitializer275 %a = lshr <2 x i64> %x, %splat276 %b = trunc <2 x i64> %a to <2 x i32>277 ret <2 x i32> %b278}279 280define <2 x i32> @vnsrl_v2i64_v2i32_scalar_sext(<2 x i64> %x, i32 %y) {281; CHECK-LABEL: vnsrl_v2i64_v2i32_scalar_sext:282; CHECK: # %bb.0:283; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma284; CHECK-NEXT: vnsrl.wx v8, v8, a0285; CHECK-NEXT: ret286 %insert = insertelement <2 x i32> poison, i32 %y, i32 0287 %splat = shufflevector <2 x i32> %insert, <2 x i32> poison, <2 x i32> zeroinitializer288 %sext = sext <2 x i32> %splat to <2 x i64>289 %a = lshr <2 x i64> %x, %sext290 %b = trunc <2 x i64> %a to <2 x i32>291 ret <2 x i32> %b292}293 294define <2 x i32> @vnsrl_v2i64_v2i32_scalar_zext(<2 x i64> %x, i32 %y) {295; CHECK-LABEL: vnsrl_v2i64_v2i32_scalar_zext:296; CHECK: # %bb.0:297; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma298; CHECK-NEXT: vnsrl.wx v8, v8, a0299; CHECK-NEXT: ret300 %insert = insertelement <2 x i32> poison, i32 %y, i32 0301 %splat = shufflevector <2 x i32> %insert, <2 x i32> poison, <2 x i32> zeroinitializer302 %zext = zext <2 x i32> %splat to <2 x i64>303 %a = lshr <2 x i64> %x, %zext304 %b = trunc <2 x i64> %a to <2 x i32>305 ret <2 x i32> %b306}307 308define <8 x i8> @vnsrl_v8i16_v8i8_imm(<8 x i16> %x) {309; CHECK-LABEL: vnsrl_v8i16_v8i8_imm:310; CHECK: # %bb.0:311; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma312; CHECK-NEXT: vnsrl.wi v8, v8, 8313; CHECK-NEXT: ret314 %a = lshr <8 x i16> %x, <i16 8, i16 8, i16 8, i16 8,i16 8, i16 8, i16 8, i16 8>315 %b = trunc <8 x i16> %a to <8 x i8>316 ret <8 x i8> %b317}318 319define <4 x i16> @vnsrl_v4i32_v4i16_imm(<4 x i32> %x) {320; CHECK-LABEL: vnsrl_v4i32_v4i16_imm:321; CHECK: # %bb.0:322; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma323; CHECK-NEXT: vnsrl.wi v8, v8, 16324; CHECK-NEXT: ret325 %a = lshr <4 x i32> %x, <i32 16, i32 16, i32 16, i32 16>326 %b = trunc <4 x i32> %a to <4 x i16>327 ret <4 x i16> %b328}329 330define <2 x i32> @vnsrl_v2i64_v2i32_imm(<2 x i64> %x) {331; CHECK-LABEL: vnsrl_v2i64_v2i32_imm:332; CHECK: # %bb.0:333; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma334; CHECK-NEXT: vnsrl.wi v8, v8, 31335; CHECK-NEXT: ret336 %a = lshr <2 x i64> %x, <i64 31, i64 31>337 %b = trunc <2 x i64> %a to <2 x i32>338 ret <2 x i32> %b339}340 341define <4 x i16> @vnsrl_v4i32_v4i16_sext(<4 x i32> %x, <4 x i16> %y) {342; CHECK-LABEL: vnsrl_v4i32_v4i16_sext:343; CHECK: # %bb.0:344; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma345; CHECK-NEXT: vnsrl.wv v8, v8, v9346; CHECK-NEXT: ret347 %sext = sext <4 x i16> %y to <4 x i32>348 %a = lshr <4 x i32> %x, %sext349 %b = trunc <4 x i32> %a to <4 x i16>350 ret <4 x i16> %b351}352 353define <4 x i16> @vnsrl_v4i32_v4i16_zext(<4 x i32> %x, <4 x i16> %y) {354; CHECK-LABEL: vnsrl_v4i32_v4i16_zext:355; CHECK: # %bb.0:356; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma357; CHECK-NEXT: vnsrl.wv v8, v8, v9358; CHECK-NEXT: ret359 %zext = zext <4 x i16> %y to <4 x i32>360 %a = lshr <4 x i32> %x, %zext361 %b = trunc <4 x i32> %a to <4 x i16>362 ret <4 x i16> %b363}364 365define <2 x i32> @vnsrl_v2i64_v2i32_sext(<2 x i64> %x, <2 x i32> %y) {366; CHECK-LABEL: vnsrl_v2i64_v2i32_sext:367; CHECK: # %bb.0:368; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma369; CHECK-NEXT: vnsrl.wv v8, v8, v9370; CHECK-NEXT: ret371 %sext = sext <2 x i32> %y to <2 x i64>372 %a = lshr <2 x i64> %x, %sext373 %b = trunc <2 x i64> %a to <2 x i32>374 ret <2 x i32> %b375}376 377define <2 x i32> @vnsrl_v2i64_v2i32_zext(<2 x i64> %x, <2 x i32> %y) {378; CHECK-LABEL: vnsrl_v2i64_v2i32_zext:379; CHECK: # %bb.0:380; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma381; CHECK-NEXT: vnsrl.wv v8, v8, v9382; CHECK-NEXT: ret383 %zext = zext <2 x i32> %y to <2 x i64>384 %a = lshr <2 x i64> %x, %zext385 %b = trunc <2 x i64> %a to <2 x i32>386 ret <2 x i32> %b387}388